From d909a1293a8884ff5ff20e49490e67dcbf3cdc74 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 26 Aug 2026 11:56:14 +0100 Subject: [PATCH 01/89] Add clobber_types.odin --- core/rexcode/isa/arm64/clobber_types.odin | 82 +++++++++++++++++++ .../isa/arm64/tablegen/encoding_table.odin | 2 +- 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 core/rexcode/isa/arm64/clobber_types.odin diff --git a/core/rexcode/isa/arm64/clobber_types.odin b/core/rexcode/isa/arm64/clobber_types.odin new file mode 100644 index 000000000..f678381e2 --- /dev/null +++ b/core/rexcode/isa/arm64/clobber_types.odin @@ -0,0 +1,82 @@ +package rexcode_arm64 + +// Operand slots (indices into the Encoding operand list) that are read/written. +// Max 4 operands (R4-style FMA: FMADD rd, rn, rm, ra). Register lists on the +// LD1-4/ST1-4 structure forms count as a single operand slot. +Operand_Set :: distinct bit_set[0..<4; u8] + +// The NZCV condition flags โ€” the ONLY application-visible flag state in AArch64. +// There is no parity/aux-carry/direction flag as on x86. The other PSTATE bits +// (DAIF interrupt masks, PAN, UAO, SSBS, SP-select, ...) are system state +// reached only through MSR/MRS, and are modelled via the PRIVILEGED side effect +// rather than here. +NZCV_Flags :: distinct bit_set[NZCV_Flag; u8] +NZCV_Flag :: enum u8 { + N, // negative result + Z, // zero result + C, // carry-out / no-borrow (unsigned sense) + V, // signed overflow +} + +// FPSR cumulative exception + saturation flags โ€” the AArch64 analogue of RISC-V +// fflags / x86 MXCSR status. The rounding mode lives separately in FPCR (see +// reads_fpcr below), so there is no EFLAGS-style triad for FP either. +FPSR_Flags :: distinct bit_set[FPSR_Flag; u8] +FPSR_Flag :: enum u8 { + IOC, // invalid operation + DZC, // divide by zero + OFC, // overflow + UFC, // underflow + IXC, // inexact + IDC, // input denormal + QC, // cumulative saturation (Advanced SIMD saturating ops) +} + +// Implicitly-touched GPRs that are NOT distinct operands. Like RISC-V, AArch64 +// has very few of these: the SIMD/FP register file is always addressed through +// explicit operands, so there is no x86-style VECTOR/XMM0 implicit clobber. +// +// X16/X17 are here for the pointer-authentication *1716 hint forms +// (PACIA1716/AUTIA1716/...), which implicitly read X16 (modifier) and +// read-modify-write X17 (the pointer) without naming either as an operand. +Clobber_Regs :: distinct bit_set[Clobber_Reg; u8] +Clobber_Reg :: enum u8 { + LR, // x30, implicit link written by BL/BLR, implicitly read by RET + SP, // sp, implicit base on PACIASP/AUTIASP (and stack-relative forms) + X16, // implicit modifier register for PAC*1716 / AUT*1716 + X17, // implicit pointer register (read-modify-write) for PAC*1716 / AUT*1716 +} + +Side_Effects :: distinct bit_set[Side_Effect; u16] +Side_Effect :: enum u8 { + CONTROL, // writes pc: B/BL/BR/BLR/RET, B.cond, CBZ/CBNZ, TBZ/TBNZ + EXCEPTION, // exception-generating call: SVC / HVC / SMC + TRAP, // deliberately faults: BRK (breakpoint), UDF (undefined) + FENCE, // memory-ordering barrier: DMB/DSB, and acquire/release accesses + ISYNC, // instruction-stream / context synchronization: ISB + ATOMIC, // indivisible RMW: LDXR/STXR pair, LSE (LDADD/SWP/CAS...) + RESERVATION, // sets/tests/clears the local exclusive monitor: LDXR/STXR, CLREX + CACHE, // cache maintenance with coherence effects: DC, IC + HINT, // architecturally-inert hint: NOP/YIELD/PRFM/SEV/ESB/CSDB + BTI, // branch-target-identification landing pad (control-flow integrity) + PAC, // pointer authentication: reads an implicit key, may fault (FEAT_FPAC) + WAIT, // suspends execution until an event/interrupt: WFI/WFE + PRIVILEGED, // reads/writes system state: MSR/MRS, ERET, TLBI, AT, DAIF + FFR, // reads/writes the SVE first-fault register: SETFFR/RDFFR/WRFFR, LDFF* + NONDETERMINISTIC, // RNDR/RNDRRS, counter/timer reads (CNTVCT), TSTART +} + +Clobber :: struct { + written: Operand_Set, // operand slots whose register/SIMD reg is written + read: Operand_Set, // operand slots whose register / mem-base is read + implicit_wr: Clobber_Regs, // implicit reg writes (LR on BL/BLR) + implicit_rd: Clobber_Regs, // implicit reg reads (LR on RET, SP on PAC*SP) + nzcv_wr: NZCV_Flags, // condition flags written (ADDS/SUBS/ANDS, CMP, FCMP, CCMP...) + nzcv_undef: NZCV_Flags, // condition flags left UNKNOWN โ€” rare in A64, usually empty + nzcv_rd: NZCV_Flags, // condition flags read (B.cond, CSEL, ADC/SBC, CCMP...) + fpsr_wr: FPSR_Flags, // FP cumulative exception/saturation flags this op may raise + reads_fpcr: bool, // consumes the rounding mode / FP control from FPCR + writes_mem: bool, + reads_mem: bool, + side_effects: Side_Effects, +} diff --git a/core/rexcode/isa/arm64/tablegen/encoding_table.odin b/core/rexcode/isa/arm64/tablegen/encoding_table.odin index 164c02365..da6c85b17 100644 --- a/core/rexcode/isa/arm64/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm64/tablegen/encoding_table.odin @@ -28,7 +28,7 @@ package rexcode_arm64_tablegen // immediate encoding (N:imms:immr); they're deferred to a follow-up // turn that adds the bitmask encoder helper. @(rodata) -ENCODING_TABLE := #partial [Mnemonic][]Encoding{ +ENCODING_TABLE := [Mnemonic][]Encoding{ .INVALID = {}, // ========================================================================= From f2615fd527d8dd83db35b7688ba1c3188bb51346 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 26 Aug 2026 11:56:53 +0100 Subject: [PATCH 02/89] Add clobber_table.odin --- .../isa/arm64/tablegen/clobber_table.odin | 3612 +++++++++++++++++ 1 file changed, 3612 insertions(+) create mode 100644 core/rexcode/isa/arm64/tablegen/clobber_table.odin diff --git a/core/rexcode/isa/arm64/tablegen/clobber_table.odin b/core/rexcode/isa/arm64/tablegen/clobber_table.odin new file mode 100644 index 000000000..a217df0de --- /dev/null +++ b/core/rexcode/isa/arm64/tablegen/clobber_table.odin @@ -0,0 +1,3612 @@ +package rexcode_arm64_tablegen + +// rexcode ยท AArch64 CLOBBER_TABLE +// ============================================================================= +// Read/write + side-effect summary for every form of every mnemonic in +// ENCODING_TABLE. One Clobber per Encoding form; the slices are index-aligned +// with ENCODING_TABLE so CLOBBER_TABLE[m][i] describes ENCODING_TABLE[m][i]. +// +// Derivation (from each row's operand TYPES, operand ROLES, and Encoding_Flags): +// +// written / read -- operand slots (0..3) whose register / memory base is a +// def / use. A slot counts only if its TYPE is register- +// or memory-like; immediate slots never appear. Direction +// comes from the ROLE, refined by instruction class: +// * RD/VD/PD/RT/RT2/ZA_TILE* are destinations, EXCEPT +// the data operand of a store (RT/VD on ST*), which is +// a source; and the status result of STXR/STXP (RD), +// which stays a def while RT/RT2 become sources. +// * A pre/post-index base (OFFSET_BASE_PRE/POST) is both +// read and written (address write-back). +// * A destination register re-listed as a later source +// slot (SVE destructive Zdn, accumulate) is read. +// * Branches define no GPR operand; targets/modifiers +// are reads. +// implicit_wr/rd -- LR on BL/BLR/RET, LR+SP on PAC*SP / RETAA, X16/X17 on +// PAC*1716, etc. +// nzcv_wr -- set for sets_flags forms (ADDS/SUBS/ANDS/CMP/CCMP/FCMP, +// SVE compares, WHILE*, PTRUES, ...). +// nzcv_rd -- any COND operand (CSEL/FCSEL/B.cond/CCMP), plus the +// carry readers ADC/ADCS/SBC/SBCS/NGC/NGCS; CCMP/CCMN both. +// fpsr_wr/reads_fpcr -- per FP-op family (see notes); saturating integer ops +// (SQ*/UQ*/SUQ*/USQ*/SQRDML*) set QC. +// reads_mem/writes_mem -- loads / stores / RMW atomics / MOPS. +// side_effects -- control flow, barriers, atomics, cache/TLB, PAC, BTI, +// wait, privileged system access, FFR, etc. +// +// Heuristic / best-effort fields (structurally faithful, semantically approximate): +// * FPSR exception-bit sets and reads_fpcr are assigned per mnemonic family, +// not per-corner-case; treat them as "flags this class may raise". +// * Accumulate detection (destination is read-modified) is name-driven for +// the families that fold the accumulator into the destination (MLA/MLS/DOT/ +// FMLA/FCMLA/SQRDML*/MOPA, shift-accumulate, bit-insert, AES/SHA/SM3/SM4, +// PAC in-place). Multiply-adds with a separate Ra/Va operand (MADD/FMADD/...) +// are correctly NOT dest-reads. +// * LD1-4/ST1-4 register lists occupy a single operand slot, so max operand +// count stays at 4 (matches Operand_Set / the encoder's model). +// * Acquire/release accesses carry the FENCE side effect to model their +// one-way ordering (distinct from the register/memory read/write sets). +// * Requires the companion clobber_types.odin (adds X16/X17 to Clobber_Reg +// and FFR to Side_Effect). +// ============================================================================= + + +@(rodata) +CLOBBER_TABLE := [Mnemonic][]Clobber{ + .INVALID = {}, + + .ADD_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .ADDS_IMM = { + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SUB_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SUBS_IMM = { + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .MOVN = { + {written={0}, read={}}, + {written={0}, read={}}, + }, + .MOVZ = { + {written={0}, read={}}, + {written={0}, read={}}, + }, + .MOVK = { + {written={0}, read={}}, + {written={0}, read={}}, + }, + .ADR = { {written={0}, read={}} }, + .ADRP = { {written={0}, read={}} }, + .ADD_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ADDS_SR = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SUB_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SUBS_SR = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .AND_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .BIC_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ORR_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ORN_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .EOR_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .EON_SR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ANDS_SR = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .BICS_SR = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .ADD_ER = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ADDS_ER = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SUB_ER = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SUBS_ER = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .UDIV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SDIV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .LSLV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .LSRV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ASRV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .RORV = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .MADD = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .MSUB = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SMADDL = { {written={0}, read={1, 2, 3}} }, + .SMSUBL = { {written={0}, read={1, 2, 3}} }, + .UMADDL = { {written={0}, read={1, 2, 3}} }, + .UMSUBL = { {written={0}, read={1, 2, 3}} }, + .SMULH = { {written={0}, read={1, 2}} }, + .UMULH = { {written={0}, read={1, 2}} }, + .RBIT = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV16 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV32 = { {written={0}, read={1}} }, + .CLZ = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .CLS = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .EXTR = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CSEL = { + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CSINC = { + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CSINV = { + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CSNEG = { + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CCMP_REG = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CCMN_REG = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CCMP_IMM = { + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .CCMN_IMM = { + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .HINT = { {written={}, read={}, side_effects={.HINT}} }, + .MSR_IMM = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .USDOT = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .FMOV_IMM = { + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + }, + .FMOV_V_IMM = { + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + }, + .LDRB_POST = { {written={0, 1}, read={1}, reads_mem=true} }, + .LDRB_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, + .LDRB_REG = { {written={0}, read={1}, reads_mem=true} }, + .LDRH_POST = { {written={0, 1}, read={1}, reads_mem=true} }, + .LDRH_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, + .LDRH_REG = { {written={0}, read={1}, reads_mem=true} }, + .STRB_POST = { {written={1}, read={0, 1}, writes_mem=true} }, + .STRB_PRE = { {written={1}, read={0, 1}, writes_mem=true} }, + .STRB_REG = { {written={}, read={0, 1}, writes_mem=true} }, + .STRH_POST = { {written={1}, read={0, 1}, writes_mem=true} }, + .STRH_PRE = { {written={1}, read={0, 1}, writes_mem=true} }, + .STRH_REG = { {written={}, read={0, 1}, writes_mem=true} }, + .LDRSB_REG = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDRSH_REG = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDRSW_REG = { {written={0}, read={1}, reads_mem=true} }, + .LDP_V = { + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + }, + .STP_V = { + {written={}, read={0, 1, 2}, writes_mem=true}, + {written={}, read={0, 1, 2}, writes_mem=true}, + {written={}, read={0, 1, 2}, writes_mem=true}, + }, + .LDUR_V = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .STUR_V = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .B = { {written={}, read={}, side_effects={.CONTROL}} }, + .BL = { {written={}, read={}, implicit_wr={.LR}, side_effects={.CONTROL}} }, + .B_COND = { {written={}, read={}, nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}} }, + .CBZ = { + {written={}, read={0}, side_effects={.CONTROL}}, + {written={}, read={0}, side_effects={.CONTROL}}, + }, + .CBNZ = { + {written={}, read={0}, side_effects={.CONTROL}}, + {written={}, read={0}, side_effects={.CONTROL}}, + }, + .TBZ = { {written={}, read={0}, side_effects={.CONTROL}} }, + .TBNZ = { {written={}, read={0}, side_effects={.CONTROL}} }, + .BR = { {written={}, read={0}, side_effects={.CONTROL}} }, + .BLR = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL}} }, + .RET = { + {written={}, read={0}, side_effects={.CONTROL}}, + {written={}, read={}, implicit_rd={.LR}, side_effects={.CONTROL}}, + }, + .LDR = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .STR = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .LDRB = { {written={0}, read={1}, reads_mem=true} }, + .STRB = { {written={}, read={0, 1}, writes_mem=true} }, + .LDRSB = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDRH = { {written={0}, read={1}, reads_mem=true} }, + .STRH = { {written={}, read={0, 1}, writes_mem=true} }, + .LDRSH = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDRSW = { {written={0}, read={1}, reads_mem=true} }, + .LDR_LIT = { + {written={0}, read={}}, + {written={0}, read={}}, + }, + .LDP = { + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + }, + .STP = { + {written={}, read={0, 1, 2}, writes_mem=true}, + {written={}, read={0, 1, 2}, writes_mem=true}, + }, + .LDPSW = { {written={0, 1}, read={2}, reads_mem=true} }, + .NOP = { {written={}, read={}, side_effects={.HINT}} }, + .YIELD = { {written={}, read={}, side_effects={.HINT}} }, + .WFE = { {written={}, read={}, side_effects={.WAIT}} }, + .WFI = { {written={}, read={}, side_effects={.WAIT}} }, + .SEV = { {written={}, read={}, side_effects={.HINT}} }, + .SEVL = { {written={}, read={}, side_effects={.HINT}} }, + .ISB = { {written={}, read={}, side_effects={.ISYNC}} }, + .DSB = { {written={}, read={}, side_effects={.FENCE}} }, + .DMB = { {written={}, read={}, side_effects={.FENCE}} }, + .SVC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION}} }, + .HVC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}} }, + .SMC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}} }, + .BRK = { {written={}, read={}, side_effects={.CONTROL, .TRAP}} }, + .HLT = { {written={}, read={}, side_effects={.CONTROL, .TRAP}} }, + .ERET = { {written={}, read={}, side_effects={.CONTROL, .PRIVILEGED}} }, + .MRS = { {written={0}, read={1}, side_effects={.PRIVILEGED}} }, + .MSR_REG = { {written={0}, read={1}, side_effects={.PRIVILEGED}} }, + .FABS = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FNEG = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FSQRT = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FADD = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FSUB = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMUL = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FDIV = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FNMUL = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMAX = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMIN = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMAXNM = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINNM = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMADD = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMSUB = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FNMADD = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FNMSUB = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FCMP = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + }, + .FCMPE = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + }, + .FCSEL = { + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + }, + .FCVT = { + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SCVTF = { + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + }, + .UCVTF = { + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + }, + .FCVTZS = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTZU = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FMOV_REG = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FMOV_GEN = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .AND_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .ORR_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .EOR_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .ANDS_IMM = { + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .TST_IMM = { + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .LDUR = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .STUR = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .LDURB = { {written={0}, read={1}, reads_mem=true} }, + .STURB = { {written={}, read={0, 1}, writes_mem=true} }, + .LDURH = { {written={0}, read={1}, reads_mem=true} }, + .STURH = { {written={}, read={0, 1}, writes_mem=true} }, + .LDURSB = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDURSH = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .LDURSW = { {written={0}, read={1}, reads_mem=true} }, + .LDR_PRE = { + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + }, + .STR_PRE = { + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + }, + .LDR_POST = { + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + }, + .STR_POST = { + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + }, + .LDR_REG = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .STR_REG = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .LDP_PRE = { + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + }, + .STP_PRE = { + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + }, + .LDP_POST = { + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + }, + .STP_POST = { + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + }, + .LDPSW_PRE = { {written={0, 1, 2}, read={2}, reads_mem=true} }, + .LDPSW_POST = { {written={0, 1, 2}, read={2}, reads_mem=true} }, + .LDNP = { + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + }, + .STNP = { + {written={}, read={0, 1, 2}, writes_mem=true}, + {written={}, read={0, 1, 2}, writes_mem=true}, + }, + .LDXR = { + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + }, + .STXR = { + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + }, + .LDAXR = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + }, + .STLXR = { + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + }, + .LDXRB = { {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, + .STXRB = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, + .LDAXRB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, + .STLXRB = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, + .LDXRH = { {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, + .STXRH = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, + .LDAXRH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, + .STLXRH = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, + .LDXP = { + {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + }, + .STXP = { + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + }, + .LDAXP = { + {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + }, + .STLXP = { + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + }, + .LDAR = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + }, + .STLR = { + {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + }, + .LDARB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .STLRB = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, + .LDARH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .STLRH = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, + .LDAPR = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + }, + .LDAPRB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .LDAPRH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .LDADD = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDADDA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDADDL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDADDAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDCLR = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDCLRA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDCLRL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDCLRAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDEOR = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDEORA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDEORL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDEORAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSET = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDSETA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSETL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSETAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMAX = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDSMAXA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMAXL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMAXAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMIN = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDSMINA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMINL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDSMINAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMAX = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDUMAXA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMAXL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMAXAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMIN = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .LDUMINA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMINL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .LDUMINAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .SWP = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .SWPA = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .SWPL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .SWPAL = { + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CAS = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .CASA = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CASL = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CASAL = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CASB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}} }, + .CASAB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASLB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASALB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}} }, + .CASAH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASLH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASALH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, + .CASP = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + }, + .CASPA = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CASPL = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CASPAL = { + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + }, + .CRC32B = { {written={0}, read={1, 2}} }, + .CRC32H = { {written={0}, read={1, 2}} }, + .CRC32W = { {written={0}, read={1, 2}} }, + .CRC32X = { {written={0}, read={1, 2}} }, + .CRC32CB = { {written={0}, read={1, 2}} }, + .CRC32CH = { {written={0}, read={1, 2}} }, + .CRC32CW = { {written={0}, read={1, 2}} }, + .CRC32CX = { {written={0}, read={1, 2}} }, + .AESE = { {written={0}, read={0, 1}} }, + .AESD = { {written={0}, read={0, 1}} }, + .AESMC = { {written={0}, read={0, 1}} }, + .AESIMC = { {written={0}, read={0, 1}} }, + .SHA1H = { {written={0}, read={1}} }, + .SHA1SU1 = { {written={0}, read={0, 1}} }, + .SHA1C = { {written={0}, read={0, 1, 2}} }, + .SHA1P = { {written={0}, read={0, 1, 2}} }, + .SHA1M = { {written={0}, read={0, 1, 2}} }, + .SHA1SU0 = { {written={0}, read={0, 1, 2}} }, + .SHA256H = { {written={0}, read={0, 1, 2}} }, + .SHA256H2 = { {written={0}, read={0, 1, 2}} }, + .SHA256SU0 = { {written={0}, read={0, 1}} }, + .SHA256SU1 = { {written={0}, read={0, 1, 2}} }, + .SHA512H = { {written={0}, read={0, 1, 2}} }, + .SHA512H2 = { {written={0}, read={0, 1, 2}} }, + .SHA512SU0 = { {written={0}, read={0, 1}} }, + .SHA512SU1 = { {written={0}, read={0, 1, 2}} }, + .EOR3 = { {written={0}, read={1, 2, 3}} }, + .BCAX = { {written={0}, read={1, 2, 3}} }, + .RAX1 = { {written={0}, read={1, 2}} }, + .XAR = { {written={0}, read={1, 2}} }, + .SM3PARTW1 = { {written={0}, read={0, 1, 2}} }, + .SM3PARTW2 = { {written={0}, read={0, 1, 2}} }, + .SM3SS1 = { {written={0}, read={1, 2, 3}} }, + .SM3TT1A = { {written={0}, read={0, 1, 2}} }, + .SM3TT1B = { {written={0}, read={0, 1, 2}} }, + .SM3TT2A = { {written={0}, read={0, 1, 2}} }, + .SM3TT2B = { {written={0}, read={0, 1, 2}} }, + .SM4E = { {written={0}, read={0, 1}} }, + .SM4EKEY = { {written={0}, read={1, 2}} }, + .PMULL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .PMULL2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .PACIA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .PACIB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .PACDA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .PACDB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .AUTIA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .AUTIB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .AUTDA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .AUTDB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, + .PACIZA = { {written={0}, read={0}, side_effects={.PAC}} }, + .PACIZB = { {written={0}, read={0}, side_effects={.PAC}} }, + .PACDZA = { {written={0}, read={0}, side_effects={.PAC}} }, + .PACDZB = { {written={0}, read={0}, side_effects={.PAC}} }, + .AUTIZA = { {written={0}, read={0}, side_effects={.PAC}} }, + .AUTIZB = { {written={0}, read={0}, side_effects={.PAC}} }, + .AUTDZA = { {written={0}, read={0}, side_effects={.PAC}} }, + .AUTDZB = { {written={0}, read={0}, side_effects={.PAC}} }, + .XPACI = { {written={0}, read={0}, side_effects={.PAC}} }, + .XPACD = { {written={0}, read={0}, side_effects={.PAC}} }, + .XPACLRI = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}} }, + .PACIASP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, + .PACIBSP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, + .AUTIASP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, + .AUTIBSP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, + .PACIA1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, + .PACIB1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, + .AUTIA1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, + .AUTIB1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, + .PACGA = { {written={0}, read={0, 1, 2}, side_effects={.PAC}} }, + .RETAA = { {written={}, read={}, implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}} }, + .RETAB = { {written={}, read={}, implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}} }, + .BRAA = { {written={}, read={0, 1}, side_effects={.CONTROL, .PAC}} }, + .BRAB = { {written={}, read={0, 1}, side_effects={.CONTROL, .PAC}} }, + .BLRAA = { {written={}, read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, + .BLRAB = { {written={}, read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, + .BRAAZ = { {written={}, read={0}, side_effects={.CONTROL, .PAC}} }, + .BRABZ = { {written={}, read={0}, side_effects={.CONTROL, .PAC}} }, + .BLRAAZ = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, + .BLRABZ = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, + .ERETAA = { {written={}, read={}, side_effects={.CONTROL, .PAC, .PRIVILEGED}} }, + .ERETAB = { {written={}, read={}, side_effects={.CONTROL, .PAC, .PRIVILEGED}} }, + .BTI = { {written={}, read={}, side_effects={.BTI}} }, + .ADDG = { {written={0}, read={1}} }, + .SUBG = { {written={0}, read={1}} }, + .IRG = { {written={0}, read={1, 2}} }, + .GMI = { {written={0}, read={1, 2}} }, + .SUBP = { {written={0}, read={1, 2}} }, + .SUBPS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .STG = { {written={}, read={0, 1}, writes_mem=true} }, + .STZG = { {written={}, read={0, 1}, writes_mem=true} }, + .ST2G = { {written={}, read={0, 1}, writes_mem=true} }, + .STZ2G = { {written={}, read={0, 1}, writes_mem=true} }, + .LDG = { {written={0}, read={1}, reads_mem=true} }, + .STGM = { {written={}, read={0, 1}, writes_mem=true} }, + .LDGM = { {written={0}, read={1}, reads_mem=true} }, + .STZGM = { {written={}, read={0, 1}, writes_mem=true} }, + .STGP = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .FABS_H = { {written={0}, read={1}} }, + .FNEG_H = { {written={0}, read={1}} }, + .FSQRT_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true} }, + .FADD_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FSUB_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FMUL_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FDIV_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FNMUL_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FMAX_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, + .FMIN_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, + .FMAXNM_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, + .FMINNM_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, + .FCMP_H = { {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}} }, + .FCMPE_H = { {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}} }, + .FCSEL_H = { {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}} }, + .FMADD_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FMSUB_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FNMADD_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FNMSUB_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCVT_H_S = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCVT_H_D = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCVT_S_H = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCVT_D_H = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SCVTF_H = { {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true} }, + .UCVTF_H = { {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true} }, + .FCVTZS_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, + .FCVTZU_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, + .FMOV_H = { {written={0}, read={1}} }, + .BFCVT = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFCVTN = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFCVTN2 = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFDOT = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFMMLA = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFMLALB = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .BFMLALT = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .ADD_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SUB_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .MUL_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CMEQ = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CMGT = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CMHI = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .AND_V = { {written={0}, read={1, 2}} }, + .ORR_V = { {written={0}, read={1, 2}} }, + .EOR_V = { {written={0}, read={1, 2}} }, + .BIC_V = { {written={0}, read={1, 2}} }, + .ORN_V = { {written={0}, read={1, 2}} }, + .BIT = { {written={0}, read={0, 1, 2}} }, + .BIF = { {written={0}, read={0, 1, 2}} }, + .BSL = { {written={0}, read={0, 1, 2}} }, + .FADD_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FSUB_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMUL_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FDIV_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMLA_V = { + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMLS_V = { + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SDOT = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UDOT = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .LD1 = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .ST1 = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .TBL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .TBX = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .LD2 = { {written={0}, read={1}, reads_mem=true} }, + .LD3 = { {written={0}, read={1}, reads_mem=true} }, + .LD4 = { {written={0}, read={1}, reads_mem=true} }, + .ST2 = { {written={}, read={0, 1}, writes_mem=true} }, + .ST3 = { {written={}, read={0, 1}, writes_mem=true} }, + .ST4 = { {written={}, read={0, 1}, writes_mem=true} }, + .LD1R = { {written={0}, read={1}, reads_mem=true} }, + .LD2R = { {written={0}, read={1}, reads_mem=true} }, + .LD3R = { {written={0}, read={1}, reads_mem=true} }, + .LD4R = { {written={0}, read={1}, reads_mem=true} }, + .LD1_LANE = { + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + }, + .LD2_LANE = { + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + }, + .LD3_LANE = { + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + }, + .LD4_LANE = { + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + }, + .ST1_LANE = { + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + }, + .ST2_LANE = { + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + }, + .ST3_LANE = { + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + }, + .ST4_LANE = { + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + {written={}, read={0, 2}, writes_mem=true}, + }, + .LDR_V = { + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + }, + .STR_V = { + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + {written={}, read={0, 1}, writes_mem=true}, + }, + .SVE_ADD_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_SUB_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_SQADD_Z = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SVE_UQADD_Z = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SVE_SQSUB_Z = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SVE_UQSUB_Z = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SVE_ADD_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SUB_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SUBR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_MUL_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SMULH_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_UMULH_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SDIV_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_UDIV_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SMAX_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_UMAX_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SMIN_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_UMIN_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_SABD_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_UABD_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_AND_PRED = { {written={0}, read={1, 2, 3}} }, + .SVE_ORR_PRED = { {written={0}, read={1, 2, 3}} }, + .SVE_EOR_PRED = { {written={0}, read={1, 2, 3}} }, + .SVE_BIC_PRED = { {written={0}, read={1, 2, 3}} }, + .SVE_ASR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_LSR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_LSL_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_ABS_PRED = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_NEG_PRED = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_CLS_PRED = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_CLZ_PRED = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_CNT_PRED = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_FADD_Z = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FSUB_Z = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMUL_Z = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FRECPS = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FRSQRTS = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FTSMUL = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FADD_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FSUB_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMUL_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FDIV_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMAX_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMIN_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMAXNM_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMINNM_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .SVE_FABS_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_FNEG_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_FSQRT_Z = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMLA = { + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FMLS = { + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FNMLA = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SVE_FNMLS = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SVE_AND_P = { {written={0}, read={1, 2, 3}} }, + .SVE_BIC_P = { {written={0}, read={1, 2, 3}} }, + .SVE_ORR_P = { {written={0}, read={1, 2, 3}} }, + .SVE_ORN_P = { {written={0}, read={1, 2, 3}} }, + .SVE_EOR_P = { {written={0}, read={1, 2, 3}} }, + .SVE_NAND_P = { {written={0}, read={1, 2, 3}} }, + .SVE_NOR_P = { {written={0}, read={1, 2, 3}} }, + .SVE_SEL_P = { {written={0}, read={1, 2, 3}} }, + .SVE_ANDS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_BICS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_ORRS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_EORS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_PTRUE = { {written={0}, read={}} }, + .SVE_PTRUES = { {written={0}, read={}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_PFALSE = { {written={0}, read={}} }, + .SVE_PFIRST = { {written={0}, read={1, 2}} }, + .SVE_PNEXT = { {written={0}, read={1, 2}} }, + .SVE_CPY_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_EXT_Z = { {written={0}, read={1, 2}} }, + .SVE_MOV_PRED = { + {written={}, read={0, 1, 2}}, + {written={}, read={0, 1, 2}}, + {written={}, read={0, 1, 2}}, + {written={}, read={0, 1, 2}}, + }, + .SVE_NOT_P = { {written={0}, read={1, 2}} }, + .SVE_MOVS_P = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_MOV_P = { + {written={0}, read={1, 2}}, + {written={0}, read={1}}, + }, + .SVE_XAR_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_CMPEQ = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPNE = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPGE = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPGT = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPHI = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPHS = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_DUP_Z = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SVE_REV_Z = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SVE_REV_P = { {written={0}, read={1}} }, + .SVE_TBL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_ZIP1_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_ZIP2_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_UZP1_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_UZP2_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_TRN1_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_TRN2_Z = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_ZIP1_P = { {written={0}, read={1, 2}} }, + .SVE_ZIP2_P = { {written={0}, read={1, 2}} }, + .SVE_UZP1_P = { {written={0}, read={1, 2}} }, + .SVE_UZP2_P = { {written={0}, read={1, 2}} }, + .SVE_TRN1_P = { {written={0}, read={1, 2}} }, + .SVE_TRN2_P = { {written={0}, read={1, 2}} }, + .SVE_LD1B = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1H = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1W = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SB = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SH = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SW = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_ST1B = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1H = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1W = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_LDFF1B = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, + .SVE_LDFF1H = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, + .SVE_LDFF1W = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, + .SVE_LDFF1D = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, + .SVE_LDR_Z = { {written={0}, read={1}, reads_mem=true} }, + .SVE_STR_Z = { {written={}, read={0, 1}, writes_mem=true} }, + .SVE_LDR_P = { {written={0}, read={1}, reads_mem=true} }, + .SVE_STR_P = { {written={}, read={0, 1}, writes_mem=true} }, + .SVE_WHILELT = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILELE = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILELO = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILELS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILEGE = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILEGT = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILEHI = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_WHILEHS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_SQRDMLAH = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SVE_SQRDMLSH = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SVE_ADCLB = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_ADCLT = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_SBCLB = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_SBCLT = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_MATCH = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_NMATCH = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_TBL2 = { {written={0}, read={1, 2}} }, + .SVE_TBX = { {written={0}, read={0, 1, 2}} }, + .SVE_AESE = { {written={0}, read={0, 1}} }, + .SVE_AESD = { {written={0}, read={0, 1}} }, + .SVE_AESMC = { {written={0}, read={0}} }, + .SVE_AESIMC = { {written={0}, read={0}} }, + .SVE_HISTCNT = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_HISTSEG = { {written={0}, read={1, 2}} }, + .SME_SMSTART = { {written={}, read={}} }, + .SME_SMSTOP = { {written={}, read={}} }, + .SME_RDSVL = { {written={0}, read={}} }, + .SME_ZERO = { {written={}, read={}} }, + .SME_FMOPA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SME_FMOPS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SME_BFMOPA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SME_BFMOPS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SME_SMOPA = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SME_SMOPS = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SME_UMOPA = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SME_UMOPS = { + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + }, + .SME_USMOPA = { {written={0}, read={0, 1, 2, 3}} }, + .SME_SUMOPA = { {written={0}, read={0, 1, 2, 3}} }, + .SME_LDR_ZA = { {written={}, read={1}, reads_mem=true} }, + .SME_STR_ZA = { {written={}, read={1}, writes_mem=true} }, + .AMX_LDX = { {written={}, read={0}} }, + .AMX_LDY = { {written={}, read={0}} }, + .AMX_STX = { {written={}, read={0}} }, + .AMX_STY = { {written={}, read={0}} }, + .AMX_LDZ = { {written={}, read={0}} }, + .AMX_STZ = { {written={}, read={0}} }, + .AMX_LDZI = { {written={}, read={0}} }, + .AMX_STZI = { {written={}, read={0}} }, + .AMX_EXTRX = { {written={}, read={0}} }, + .AMX_EXTRY = { {written={}, read={0}} }, + .AMX_FMA64 = { {written={}, read={0}} }, + .AMX_FMS64 = { {written={}, read={0}} }, + .AMX_FMA32 = { {written={}, read={0}} }, + .AMX_FMS32 = { {written={}, read={0}} }, + .AMX_MAC16 = { {written={}, read={0}} }, + .AMX_FMA16 = { {written={}, read={0}} }, + .AMX_FMS16 = { {written={}, read={0}} }, + .AMX_SET = { {written={}, read={}} }, + .AMX_CLR = { {written={}, read={}} }, + .AMX_VECINT = { {written={}, read={0}} }, + .AMX_VECFP = { {written={}, read={0}} }, + .AMX_MATINT = { {written={}, read={0}} }, + .AMX_MATFP = { {written={}, read={0}} }, + .AMX_GENLUT = { {written={}, read={0}} }, + .CPYP = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .CPYM = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .CPYE = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .CPYFP = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .CPYFM = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .CPYFE = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, + .SETP = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, + .SETM = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, + .SETE = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, + .DC_IVAC = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, + .DC_ISW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, + .DC_CSW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, + .DC_CISW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, + .DC_ZVA = { {written={}, read={0}, writes_mem=true, side_effects={.CACHE}} }, + .DC_CVAC = { {written={}, read={0}, side_effects={.CACHE}} }, + .DC_CVAU = { {written={}, read={0}, side_effects={.CACHE}} }, + .DC_CIVAC = { {written={}, read={0}, side_effects={.CACHE}} }, + .IC_IALLUIS = { {written={}, read={}, side_effects={.CACHE, .PRIVILEGED}} }, + .IC_IALLU = { {written={}, read={}, side_effects={.CACHE, .PRIVILEGED}} }, + .IC_IVAU = { {written={}, read={0}, side_effects={.CACHE}} }, + .AT_S1E1R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E1W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E0R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E0W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E2R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E2W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E3R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S1E3W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S12E1R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S12E1W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S12E0R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .AT_S12E0W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VMALLE1IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_VAE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_ASIDE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VAAE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VALE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VAALE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VMALLE1 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_VAE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_ASIDE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VAAE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VALE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_VAALE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE1 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE1IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE2 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE2IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE3 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_ALLE3IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .PRFM = { {written={}, read={1}, side_effects={.HINT}} }, + .PRFUM = { {written={}, read={1}, side_effects={.HINT}} }, + .PRFM_LIT = { {written={}, read={}, side_effects={.HINT}} }, + .MOV_REG = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .MOV_BITMASK = { + {written={0}, read={}}, + {written={0}, read={}}, + }, + .MVN = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .NEG_SR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .NEGS = { + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMP_SR = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMP_ER = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMP_IMM = { + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMN_SR = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMN_ER = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .CMN_IMM = { + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .TST_SR = { + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_FMLA_IDX_H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_FMLA_IDX_S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_FMLA_IDX_D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_FMLS_IDX_H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_FMLS_IDX_S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_FMLS_IDX_D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_LD1B_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1B_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1H_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1H_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1W_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1W_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1D_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SB_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SB_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SH_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SH_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LD1SW_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_ST1B_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1B_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1H_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1H_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1W_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1W_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_ST1D_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_LD1B_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME_LD1H_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME_LD1W_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME_LD1D_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME_LD1Q_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME_ST1B_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_ST1H_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_ST1W_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_ST1D_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_ST1Q_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME_MOVA_Z_FROM_TILE = { {written={0}, read={1, 2}} }, + .SME_MOVA_TILE_FROM_Z = { {written={0}, read={1, 2}} }, + .SME_ADDHA = { {written={0}, read={0, 1, 2, 3}} }, + .SME_ADDVA = { {written={0}, read={0, 1, 2, 3}} }, + .FCMLA_4H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCMLA_8H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCMLA_4S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCMLA_2D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCADD_4H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCADD_8H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCADD_4S = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .FCADD_2D = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_PRFB = { {written={}, read={1, 2}, side_effects={.HINT}} }, + .SVE_PRFH = { {written={}, read={1, 2}, side_effects={.HINT}} }, + .SVE_PRFW = { {written={}, read={1, 2}, side_effects={.HINT}} }, + .SVE_PRFD = { {written={}, read={1, 2}, side_effects={.HINT}} }, + .SVE_LDNT1B = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LDNT1H = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LDNT1W = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_LDNT1D = { {written={0}, read={1, 2}, reads_mem=true} }, + .SVE_STNT1B = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_STNT1H = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_STNT1W = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_STNT1D = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SVE_EXT = { {written={0}, read={1, 2}} }, + .SVE_SPLICE = { {written={0}, read={1, 2, 3}} }, + .SVE_INDEX_II = { {written={0}, read={}} }, + .SVE_INDEX_IR = { {written={0}, read={2}} }, + .SVE_INDEX_RI = { {written={0}, read={1}} }, + .SVE_INDEX_RR = { {written={0}, read={1, 2}} }, + .SVE_BSL = { {written={0}, read={0, 1, 2, 3}} }, + .SVE_BSL1N = { {written={0}, read={1, 2, 3}} }, + .SVE_BSL2N = { {written={0}, read={1, 2, 3}} }, + .SVE_NBSL = { {written={0}, read={1, 2, 3}} }, + .SVE_PMUL_VEC = { {written={0}, read={1, 2}} }, + .SVE_PMULLB = { {written={0}, read={1, 2}} }, + .SVE_PMULLT = { {written={0}, read={1, 2}} }, + .SVE_BFCVT = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFCVTNT = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .LDRAA = { {written={0}, read={1}, reads_mem=true} }, + .LDRAB = { {written={0}, read={1}, reads_mem=true} }, + .LDRAA_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, + .LDRAB_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, + .TSTART = { {written={0}, read={}, side_effects={.NONDETERMINISTIC}} }, + .TCOMMIT = { {written={}, read={}} }, + .TCANCEL = { {written={}, read={}, side_effects={.CONTROL}} }, + .TTEST = { {written={0}, read={}} }, + .WFET = { {written={}, read={0}, side_effects={.WAIT}} }, + .WFIT = { {written={}, read={0}, side_effects={.WAIT}} }, + .BC_COND = { {written={}, read={}, nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}} }, + .UXTB = { {written={0}, read={1}} }, + .UXTH = { {written={0}, read={1}} }, + .UXTW = { {written={0}, read={1}} }, + .SXTB = { {written={0}, read={1}} }, + .SXTH = { {written={0}, read={1}} }, + .SXTW = { {written={0}, read={1}} }, + .ADC = { + {written={0}, read={1, 2}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_rd={.C}}, + }, + .ADCS = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + }, + .SBC = { + {written={0}, read={1, 2}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_rd={.C}}, + }, + .SBCS = { + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + }, + .NGC = { + {written={0}, read={1}, nzcv_rd={.C}}, + {written={0}, read={1}, nzcv_rd={.C}}, + }, + .NGCS = { + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + }, + .LDAPUR = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + }, + .STLUR = { + {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + }, + .LDAPURB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .STLURB = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, + .LDAPURH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .STLURH = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, + .LDAPURSB = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + }, + .LDAPURSH = { + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + }, + .LDAPURSW = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, + .SVE_BFADD = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFSUB = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFMUL = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFMLA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFMLS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SB = { {written={}, read={}, side_effects={.FENCE}} }, + .CSDB = { {written={}, read={}, side_effects={.FENCE}} }, + .DGH = { {written={}, read={}, side_effects={.HINT}} }, + .PSB_CSYNC = { {written={}, read={}, side_effects={.HINT}} }, + .TSB_CSYNC = { {written={}, read={}, side_effects={.HINT}} }, + .BTI_J = { {written={}, read={}, side_effects={.BTI}} }, + .BTI_C = { {written={}, read={}, side_effects={.BTI}} }, + .BTI_JC = { {written={}, read={}, side_effects={.BTI}} }, + .MOV_V_ALIAS = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .NOT_V_ALIAS = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .LSR_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .ASR_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .LSL_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .ROR_IMM = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SVE_BFADD_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFSUB_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFMUL_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, + .SVE_BFCLAMP = { {written={0}, read={1, 2}} }, + .SVE_BFMAXNM = { {written={0}, read={1, 2, 3}} }, + .SVE_BFMINNM = { {written={0}, read={1, 2, 3}} }, + .SME2_LUTI2_B = { {written={0}, read={1}} }, + .SME2_LUTI4_B = { {written={0}, read={1}} }, + .SME2_LD1B_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1H_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1W_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1D_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1B_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1H_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1W_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_LD1D_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, + .SME2_ST1B_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1H_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1W_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1D_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1B_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1H_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1W_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ST1D_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, + .SME2_ZIP_3 = { {written={0}, read={1, 2}} }, + .SME2_ZIP_4 = { {written={0}, read={1, 2}} }, + .SME2_UZP_3 = { {written={0}, read={1, 2}} }, + .SME2_UZP_4 = { {written={0}, read={1, 2}} }, + .TLBI_RPALOS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_RPAOS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .TLBI_PAALL = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .TLBI_PAALLOS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, + .AT_S1E1A = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, + .DC_CIPAPA = { {written={}, read={0}, side_effects={.CACHE}} }, + .DC_CIGDPAPA = { {written={}, read={0}, side_effects={.CACHE}} }, + .SHADD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UHADD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SHSUB = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UHSUB = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SRHADD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .URHADD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SQADD = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .UQADD = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SQSUB = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .UQSUB = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SMAX = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMAX = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMIN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMIN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SABD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UABD = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SABA = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UABA = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .MLA_V = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .MLS_V = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .CMGE = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CMHS = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .CMTST = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SQDMULH = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SQRDMULH = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .ADDP_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMAXP = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMINP = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMAXP = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMINP = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SSHL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .USHL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SRSHL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .URSHL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ZIP1 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ZIP2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UZP1 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UZP2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .TRN1 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .TRN2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ABS_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .NEG_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .NOT_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .RBIT_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV16_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV32_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .REV64 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .CLS_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .CLZ_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .CNT = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .URECPE_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .URSQRTE_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FMAX_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMIN_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMAXNM_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINNM_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMULX = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FRECPS = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FRSQRTS = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FACGE = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .FACGT = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .FCMEQ = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .FCMGE = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .FCMGT = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .FADDP_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FMAXP_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINP_V = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMAXNMP = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINNMP = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FABS_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FNEG_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FSQRT_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FRINTA_V = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTI_V = { + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + }, + .FRINTM_V = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTN_V = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTP_V = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTX_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + }, + .FRINTZ_V = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRECPE = { + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + }, + .FRSQRTE = { + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + }, + .FCVTAS_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTAU_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTMS_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTMU_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTNS_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTNU_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTPS_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTPU_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTZS_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTZU_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .SCVTF_V = { + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + }, + .UCVTF_V = { + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + }, + .SADDL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SADDL2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UADDL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UADDL2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SSUBL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SSUBL2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .USUBL = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .USUBL2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMULL_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMULL2_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMULL_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UMULL2_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SMLAL = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .SMLAL2 = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UMLAL = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UMLAL2 = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .SMLSL = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .SMLSL2 = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UMLSL = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .UMLSL2 = { + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + }, + .SQDMULL = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SQDMULL2 = { + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + }, + .SQDMLAL = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SQDMLAL2 = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SQDMLSL = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SQDMLSL2 = { + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + }, + .SADDW = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SADDW2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UADDW = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .UADDW2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SSUBW = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SSUBW2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .USUBW = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .USUBW2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ADDHN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .ADDHN2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SUBHN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SUBHN2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .RADDHN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .RADDHN2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .RSUBHN = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .RSUBHN2 = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .XTN = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .XTN2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SQXTN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQXTN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQXTN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQXTN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQXTUN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQXTUN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SXTL = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SXTL2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UXTL = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UXTL2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SADDLP = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UADDLP = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SADALP = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .UADALP = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .ADDV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SMAXV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SMINV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UMAXV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UMINV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SADDLV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .UADDLV = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FMAXV_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINV_V = { + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMAXNMV = { + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FMINNMV = { + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + }, + .FCVTL = { + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FCVTL2 = { + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FCVTN = { + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FCVTN2 = { + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .FCVTXN = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, + .FCVTXN2 = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, + .CMLE = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .CMLT = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .FCMLE = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FCMLT = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .SHL_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SLI = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .SQSHLU = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQSHL_V = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SSHR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .USHR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SRSHR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .URSHR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SSRA = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .USRA = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .SRSRA = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .URSRA = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .SRI = { + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + }, + .SSHLL = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SSHLL2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .USHLL = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .USHLL2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SHRN = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SHRN2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .RSHRN = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .RSHRN2 = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SQSHRN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQSHRN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQSHRN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQSHRN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQRSHRN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQRSHRN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQRSHRN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .UQRSHRN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQSHRUN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQSHRUN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQRSHRUN = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .SQRSHRUN2 = { + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + }, + .MOV_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .MVN_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .DUP_V = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .INS = { + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + }, + .EXT_V = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .FRINTN = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTP = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTM = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTZ = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTA = { + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + }, + .FRINTX = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + }, + .FRINTI = { + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + }, + .FRECPX = { + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + }, + .FCVTAS = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTAU = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTMS = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTMU = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTNS = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTNU = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTPS = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .FCVTPU = { + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + }, + .MOVI = { + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + }, + .MVNI = { + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + {written={0}, read={}}, + }, + .SVE_FRINTN = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FRINTP = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FRINTM = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FRINTZ = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FRINTA = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FRINTX = { + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + }, + .SVE_FRINTI = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + }, + .SVE_FRECPX_Z = { + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + }, + .SVE_ASRR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_LSLR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_LSRR_PRED = { + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + }, + .SVE_FSUBR_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FDIVR_PRED = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + }, + .SVE_FCMEQ = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + }, + .SVE_FCMGE = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + }, + .SVE_FCMGT = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + }, + .SVE_FCMNE = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + }, + .SVE_FCMUO = { + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + }, + .SVE_FCMLE = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_FCMLT = { + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + }, + .SVE_CMPLE = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPLO = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPLS = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_CMPLT = { + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + }, + .SVE_NANDS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_NORS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_ORNS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_BRKPA = { {written={0}, read={1, 2, 3}} }, + .SVE_BRKPB = { {written={0}, read={1, 2, 3}} }, + .SVE_BRKA = { {written={0}, read={1, 2}} }, + .SVE_BRKB = { {written={0}, read={1, 2}} }, + .SVE_BRKAS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_BRKBS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, + .SVE_EOR3_Z = { {written={0}, read={1, 2, 3}} }, + .SVE_BCAX_Z = { {written={0}, read={1, 2, 3}} }, + .SVE_INSR = { + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + }, + .SVE_COMPACT = { + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + }, + .SVE_SETFFR = { {written={}, read={}, side_effects={.FFR}} }, + .SVE_RDFFR = { {written={0}, read={}, side_effects={.FFR}} }, + .SVE_WRFFR = { {written={}, read={0}, side_effects={.FFR}} }, + .SVE_BRKN = { {written={0}, read={1, 2, 3}} }, +} From f354406a7950a791c5d70ebb6465b65b49b12be0 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 26 Aug 2026 12:54:15 +0100 Subject: [PATCH 03/89] Add `Clobber` alias --- core/rexcode/isa/arm64/tablegen/gen.odin | 1 + 1 file changed, 1 insertion(+) diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index 5a3edd497..43cc11a07 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -28,6 +28,7 @@ import lib "../" // Package-scope aliases so the moved SoT resolves Mnemonic/Encoding unqualified. Encoding :: lib.Encoding Mnemonic :: lib.Mnemonic +Clobber :: lib.Clobber Blob :: struct { global, file, typ: string } BLOBS := [?]Blob{ From 02f7bf5634efc52fc9c864744c8b3aaaa49b9c52 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 26 Aug 2026 14:03:45 +0100 Subject: [PATCH 04/89] Merge into `INSTRUCTION_TABLE` --- .../isa/arm64/tablegen/instruction_table.odin | 4658 +++++++++++++++++ 1 file changed, 4658 insertions(+) create mode 100644 core/rexcode/isa/arm64/tablegen/instruction_table.odin diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin new file mode 100644 index 000000000..c0556eb21 --- /dev/null +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -0,0 +1,4658 @@ +package rexcode_arm64_tablegen + +Form :: struct { + using encoding: Encoding, + clobber: Clobber, +} + +@(rodata) +INSTRUCTION_TABLE := [Mnemonic][]Form{ + .INVALID = { + }, + .ADD_IMM = { + {{.ADD_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.ADD_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ADDS_IMM = { + {{.ADDS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SUB_IMM = { + {{.SUB_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.SUB_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SUBS_IMM = { + {{.SUBS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .MOVZ = { + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + }, + .MOVN = { + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + }, + .MOVK = { + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + }, + .ADR = { + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, + }, + .ADRP = { + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, + }, + .ADD_SR = { + {{.ADD_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ADDS_SR = { + {{.ADDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SUB_SR = { + {{.SUB_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SUBS_SR = { + {{.SUBS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .AND_SR = { + {{.AND_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.AND_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ANDS_SR = { + {{.ANDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .ORR_SR = { + {{.ORR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .EOR_SR = { + {{.EOR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EOR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .BIC_SR = { + {{.BIC_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.BIC_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .BICS_SR = { + {{.BICS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .ORN_SR = { + {{.ORN_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORN_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .EON_SR = { + {{.EON_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EON_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ADD_ER = { + {{.ADD_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ADDS_ER = { + {{.ADDS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SUB_ER = { + {{.SUB_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SUBS_ER = { + {{.SUBS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .LSLV = { + {{.LSLV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSLV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .LSRV = { + {{.LSRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ASRV = { + {{.ASRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ASRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .RORV = { + {{.RORV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.RORV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .UDIV = { + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SDIV = { + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .MADD = { + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .MSUB = { + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SMADDL = { + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SMSUBL = { + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .UMADDL = { + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .UMSUBL = { + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SMULH = { + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .UMULH = { + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .CLZ = { + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .CLS = { + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .RBIT = { + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .REV = { + {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .REV16 = { + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .REV32 = { + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .CSEL = { + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSINC = { + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSINV = { + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSNEG = { + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CCMP_REG = { + {{.CCMP_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CCMP_IMM = { + {{.CCMP_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CCMN_REG = { + {{.CCMN_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CCMN_IMM = { + {{.CCMN_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .EXTR = { + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .B = { + {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, + }, + .BL = { + {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, + }, + .BR = { + {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + }, + .BLR = { + {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + }, + .RET = { + {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, + }, + .B_COND = { + {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + }, + .CBZ = { + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + }, + .CBNZ = { + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + }, + .TBZ = { + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + }, + .TBNZ = { + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + }, + .LDR = { + {{.LDR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STR = { + {{.STR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRB = { + {{.LDRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STRB = { + {{.STRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRSB = { + {{.LDRSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRH = { + {{.LDRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STRH = { + {{.STRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRSH = { + {{.LDRSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRSW = { + {{.LDRSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDP = { + {{.LDP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + }, + .STP = { + {{.STP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .LDPSW = { + {{.LDPSW, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + }, + .LDR_LIT = { + {{.LDR_LIT, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, + {{.LDR_LIT, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, + }, + .LDAR = { + {{.LDAR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLR = { + {{.STLR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDARB = { + {{.LDARB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLRB = { + {{.STLRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDARH = { + {{.LDARH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLRH = { + {{.STLRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDXR = { + {{.LDXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .STXR = { + {{.STXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .LDAXR = { + {{.LDAXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .STLXR = { + {{.STLXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .NOP = { + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .YIELD = { + {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .WFE = { + {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + }, + .WFI = { + {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + }, + .SEV = { + {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .SEVL = { + {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .HINT = { + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, + }, + .MRS = { + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + }, + .MSR_IMM = { + {{.MSR_IMM, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .MSR_REG = { + {{.MSR_REG, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + }, + .ISB = { + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, + }, + .DSB = { + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .DMB = { + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .SVC = { + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, + }, + .HVC = { + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + }, + .SMC = { + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + }, + .BRK = { + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + }, + .HLT = { + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + }, + .ERET = { + {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, + }, + .FMOV_REG = { + {{.FMOV_REG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV_REG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + }, + .FMOV_IMM = { + {{.FMOV_IMM, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV_IMM, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV_IMM, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, + }, + .FMOV_GEN = { + {{.FMOV_GEN, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV_GEN, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV_GEN, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + {{.FMOV_GEN, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + }, + .FABS = { + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + }, + .FNEG = { + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + }, + .FSQRT = { + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FADD = { + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FSUB = { + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMUL = { + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FDIV = { + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMUL = { + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMADD = { + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMSUB = { + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMADD = { + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMSUB = { + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCMP = { + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + }, + .FCMPE = { + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + }, + .FCSEL = { + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .FMAX = { + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMIN = { + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXNM = { + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINNM = { + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FCVT = { + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SCVTF = { + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .UCVTF = { + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .FCVTZS = { + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTZU = { + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTAS = { + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTAU = { + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTNS = { + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTNU = { + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTPS = { + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTPU = { + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTMS = { + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTMU = { + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FRINTA = { + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTI = { + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + }, + .FRINTM = { + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTN = { + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTP = { + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTX = { + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + }, + .FRINTZ = { + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .AND_IMM = { + {{.AND_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.AND_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ANDS_IMM = { + {{.ANDS_IMM, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS_IMM, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .ORR_IMM = { + {{.ORR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ORR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .EOR_IMM = { + {{.EOR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.EOR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .TST_IMM = { + {{.TST_IMM, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST_IMM, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .LDUR = { + {{.LDUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STUR = { + {{.STUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .LDURB = { + {{.LDURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STURB = { + {{.STURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDURSB = { + {{.LDURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDURH = { + {{.LDURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STURH = { + {{.STURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDURSH = { + {{.LDURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDURSW = { + {{.LDURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDR_PRE = { + {{.LDR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STR_PRE = { + {{.STR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDR_POST = { + {{.LDR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STR_POST = { + {{.STR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDRB_PRE = { + {{.LDRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STRB_PRE = { + {{.STRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDRB_POST = { + {{.LDRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STRB_POST = { + {{.STRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDRH_PRE = { + {{.LDRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STRH_PRE = { + {{.STRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDRH_POST = { + {{.LDRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .STRH_POST = { + {{.STRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + }, + .LDR_REG = { + {{.LDR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STR_REG = { + {{.STR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRB_REG = { + {{.LDRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STRB_REG = { + {{.STRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRH_REG = { + {{.LDRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STRH_REG = { + {{.STRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDRSB_REG = { + {{.LDRSB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRSH_REG = { + {{.LDRSH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRSW_REG = { + {{.LDRSW_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDP_PRE = { + {{.LDP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + }, + .STP_PRE = { + {{.STP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + }, + .LDP_POST = { + {{.LDP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + }, + .STP_POST = { + {{.STP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + }, + .LDPSW_PRE = { + {{.LDPSW_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + }, + .LDPSW_POST = { + {{.LDPSW_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + }, + .LDNP = { + {{.LDNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + }, + .STNP = { + {{.STNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .LDXP = { + {{.LDXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .STXP = { + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .LDAXP = { + {{.LDAXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .STLXP = { + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .LDXRB = { + {{.LDXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .STXRB = { + {{.STXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .LDAXRB = { + {{.LDAXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .STLXRB = { + {{.STLXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .LDXRH = { + {{.LDXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .STXRH = { + {{.STXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + }, + .LDAXRH = { + {{.LDAXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .STLXRH = { + {{.STLXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + }, + .LDAPR = { + {{.LDAPR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPRB = { + {{.LDAPRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPRH = { + {{.LDAPRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDADD = { + {{.LDADD, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDADDA = { + {{.LDADDA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDADDL = { + {{.LDADDL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDADDAL = { + {{.LDADDAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDCLR = { + {{.LDCLR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDCLRA = { + {{.LDCLRA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDCLRL = { + {{.LDCLRL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDCLRAL = { + {{.LDCLRAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDEOR = { + {{.LDEOR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDEORA = { + {{.LDEORA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDEORL = { + {{.LDEORL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDEORAL = { + {{.LDEORAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSET = { + {{.LDSET, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDSETA = { + {{.LDSETA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSETL = { + {{.LDSETL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSETAL = { + {{.LDSETAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMAX = { + {{.LDSMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDSMAXA = { + {{.LDSMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMAXL = { + {{.LDSMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMAXAL = { + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMIN = { + {{.LDSMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDSMINA = { + {{.LDSMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMINL = { + {{.LDSMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDSMINAL = { + {{.LDSMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMAX = { + {{.LDUMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDUMAXA = { + {{.LDUMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMAXL = { + {{.LDUMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMAXAL = { + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMIN = { + {{.LDUMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .LDUMINA = { + {{.LDUMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMINL = { + {{.LDUMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .LDUMINAL = { + {{.LDUMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .SWP = { + {{.SWP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .SWPA = { + {{.SWPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .SWPL = { + {{.SWPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .SWPAL = { + {{.SWPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CAS = { + {{.CAS, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .CASA = { + {{.CASA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASL = { + {{.CASL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASAL = { + {{.CASAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASB = { + {{.CASB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .CASAB = { + {{.CASAB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASLB = { + {{.CASLB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASALB = { + {{.CASALB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASH = { + {{.CASH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .CASAH = { + {{.CASAH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASLH = { + {{.CASLH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASALH = { + {{.CASALH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASP = { + {{.CASP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + }, + .CASPA = { + {{.CASPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASPL = { + {{.CASPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .CASPAL = { + {{.CASPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + }, + .PACIA = { + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .PACIB = { + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .PACDA = { + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .PACDB = { + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .PACIZA = { + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .PACIZB = { + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .PACDZA = { + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .PACDZB = { + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .AUTIA = { + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .AUTIB = { + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .AUTDA = { + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .AUTDB = { + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + }, + .AUTIZA = { + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .AUTIZB = { + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .AUTDZA = { + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .AUTDZB = { + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .PACIASP = { + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + }, + .PACIBSP = { + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + }, + .AUTIASP = { + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + }, + .AUTIBSP = { + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + }, + .PACIA1716 = { + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + }, + .PACIB1716 = { + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + }, + .AUTIA1716 = { + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + }, + .AUTIB1716 = { + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + }, + .PACGA = { + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + }, + .XPACI = { + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .XPACD = { + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + }, + .XPACLRI = { + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + }, + .RETAA = { + {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + }, + .RETAB = { + {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + }, + .BRAA = { + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + }, + .BRAB = { + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + }, + .BRAAZ = { + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + }, + .BRABZ = { + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + }, + .BLRAA = { + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + }, + .BLRAB = { + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + }, + .BLRAAZ = { + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + }, + .BLRABZ = { + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + }, + .ERETAA = { + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + }, + .ERETAB = { + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + }, + .BTI = { + {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .IRG = { + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ADDG = { + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SUBG = { + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + }, + .GMI = { + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SUBP = { + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SUBPS = { + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .LDG = { + {{.LDG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STG = { + {{.STG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .ST2G = { + {{.ST2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .STZG = { + {{.STZG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .STZ2G = { + {{.STZ2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .STGP = { + {{.STGP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .LDGM = { + {{.LDGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STGM = { + {{.STGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .STZGM = { + {{.STZGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + }, + .CRC32B = { + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32H = { + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32W = { + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32X = { + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .CRC32CB = { + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32CH = { + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32CW = { + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + }, + .CRC32CX = { + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .AESE = { + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .AESD = { + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .AESMC = { + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .AESIMC = { + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .SHA1H = { + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, + }, + .SHA1C = { + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA1P = { + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA1M = { + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA1SU0 = { + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA1SU1 = { + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .SHA256H = { + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA256H2 = { + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA256SU0 = { + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .SHA256SU1 = { + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA512H = { + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA512H2 = { + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHA512SU0 = { + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .SHA512SU1 = { + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .EOR3 = { + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + }, + .BCAX = { + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + }, + .RAX1 = { + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + }, + .XAR = { + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + }, + .SM3PARTW1 = { + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM3PARTW2 = { + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM3SS1 = { + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SM3TT1A = { + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM3TT1B = { + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM3TT2A = { + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM3TT2B = { + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SM4E = { + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + }, + .SM4EKEY = { + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + }, + .PMULL = { + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + }, + .PMULL2 = { + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + }, + .FABS_H = { + {{.FABS_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + }, + .FNEG_H = { + {{.FNEG_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + }, + .FSQRT_H = { + {{.FSQRT_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FADD_H = { + {{.FADD_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FSUB_H = { + {{.FSUB_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMUL_H = { + {{.FMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FDIV_H = { + {{.FDIV_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMUL_H = { + {{.FNMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMADD_H = { + {{.FMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMSUB_H = { + {{.FMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMADD_H = { + {{.FNMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMSUB_H = { + {{.FNMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCMP_H = { + {{.FCMP_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + }, + .FCMPE_H = { + {{.FCMPE_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + }, + .FCSEL_H = { + {{.FCSEL_H, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .FMAX_H = { + {{.FMAX_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMIN_H = { + {{.FMIN_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXNM_H = { + {{.FMAXNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINNM_H = { + {{.FMINNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FCVT_H_S = { + {{.FCVT_H_S, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVT_H_D = { + {{.FCVT_H_D, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVT_S_H = { + {{.FCVT_S_H, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVT_D_H = { + {{.FCVT_D_H, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMOV_H = { + {{.FMOV_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + }, + .SCVTF_H = { + {{.SCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .UCVTF_H = { + {{.UCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .FCVTZS_H = { + {{.FCVTZS_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTZU_H = { + {{.FCVTZU_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .BFCVT = { + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFDOT = { + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMMLA = { + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMLALB = { + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMLALT = { + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFCVTN = { + {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFCVTN2 = { + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .ADD_V = { + {{.ADD_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SUB_V = { + {{.SUB_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .MUL_V = { + {{.MUL_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .MLA_V = { + {{.MLA_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .MLS_V = { + {{.MLS_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .NEG_V = { + {{.NEG_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .ABS_V = { + {{.ABS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SHADD = { + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UHADD = { + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SHSUB = { + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UHSUB = { + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SRHADD = { + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .URHADD = { + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SQADD = { + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .UQADD = { + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SQSUB = { + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .UQSUB = { + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SMAX = { + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMAX = { + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SMIN = { + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMIN = { + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SABD = { + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UABD = { + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SABA = { + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UABA = { + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .ADDP_V = { + {{.ADDP_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ADDV = { + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SADDLP = { + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UADDLP = { + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SADALP = { + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .UADALP = { + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SADDLV = { + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UADDLV = { + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SMAXV = { + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UMAXV = { + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SMINV = { + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UMINV = { + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SMAXP = { + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMAXP = { + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SMINP = { + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMINP = { + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SADDL = { + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SADDL2 = { + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UADDL = { + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UADDL2 = { + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSUBL = { + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSUBL2 = { + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USUBL = { + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USUBL2 = { + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SADDW = { + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SADDW2 = { + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UADDW = { + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UADDW2 = { + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSUBW = { + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSUBW2 = { + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USUBW = { + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USUBW2 = { + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .RADDHN = { + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .RADDHN2 = { + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .RSUBHN = { + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .RSUBHN2 = { + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ADDHN = { + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ADDHN2 = { + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SUBHN = { + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SUBHN2 = { + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .XTN = { + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .XTN2 = { + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SQXTN = { + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQXTN2 = { + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQXTN = { + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQXTN2 = { + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQXTUN = { + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQXTUN2 = { + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SMULL_V = { + {{.SMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SMULL2_V = { + {{.SMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMULL_V = { + {{.UMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UMULL2_V = { + {{.UMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SMLAL = { + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SMLAL2 = { + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UMLAL = { + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UMLAL2 = { + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SMLSL = { + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SMLSL2 = { + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UMLSL = { + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UMLSL2 = { + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SQDMULL = { + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMULL2 = { + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMLAL = { + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMLAL2 = { + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMLSL = { + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMLSL2 = { + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SQDMULH = { + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SQRDMULH = { + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SDOT = { + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + }, + .UDOT = { + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + }, + .USDOT = { + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + }, + .FADD_V = { + {{.FADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FSUB_V = { + {{.FSUB_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMUL_V = { + {{.FMUL_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FDIV_V = { + {{.FDIV_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNEG_V = { + {{.FNEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + }, + .FABS_V = { + {{.FABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + }, + .FSQRT_V = { + {{.FSQRT_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMLA_V = { + {{.FMLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMLS_V = { + {{.FMLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMULX = { + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMAX_V = { + {{.FMAX_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMIN_V = { + {{.FMIN_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXNM_V = { + {{.FMAXNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINNM_V = { + {{.FMINNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXP_V = { + {{.FMAXP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINP_V = { + {{.FMINP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXNMP = { + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINNMP = { + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXV_V = { + {{.FMAXV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINV_V = { + {{.FMINV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMAXNMV = { + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FMINNMV = { + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .FRECPE = { + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + }, + .FRSQRTE = { + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + }, + .FRECPS = { + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FRSQRTS = { + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FRECPX = { + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + }, + .FADDP_V = { + {{.FADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FRINTA_V = { + {{.FRINTA_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTI_V = { + {{.FRINTI_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + }, + .FRINTM_V = { + {{.FRINTM_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTN_V = { + {{.FRINTN_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTP_V = { + {{.FRINTP_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FRINTX_V = { + {{.FRINTX_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + }, + .FRINTZ_V = { + {{.FRINTZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .SCVTF_V = { + {{.SCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .UCVTF_V = { + {{.UCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + }, + .FCVTAS_V = { + {{.FCVTAS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTAU_V = { + {{.FCVTAU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTMS_V = { + {{.FCVTMS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTMU_V = { + {{.FCVTMU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTNS_V = { + {{.FCVTNS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTNU_V = { + {{.FCVTNU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTPS_V = { + {{.FCVTPS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTPU_V = { + {{.FCVTPU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTZS_V = { + {{.FCVTZS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTZU_V = { + {{.FCVTZU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTL = { + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVTL2 = { + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVTN = { + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVTN2 = { + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCVTXN = { + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCVTXN2 = { + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + }, + .FCMEQ = { + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .FCMGE = { + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .FCMGT = { + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .FCMLE = { + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FCMLT = { + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + }, + .FACGE = { + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .FACGT = { + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .CMEQ = { + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .CMGE = { + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .CMGT = { + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .CMHI = { + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .CMHS = { + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .CMLE = { + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CMLT = { + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CMTST = { + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .AND_V = { + {{.AND_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ORR_V = { + {{.ORR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .EOR_V = { + {{.EOR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .BIC_V = { + {{.BIC_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ORN_V = { + {{.ORN_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .MVN_V = { + {{.MVN_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MVN_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .BIT = { + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .BIF = { + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .BSL = { + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SHL_V = { + {{.SHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SQSHL_V = { + {{.SQSHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHLU = { + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SRSHL = { + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .URSHL = { + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSHR = { + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHR = { + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SSRA = { + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .USRA = { + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SRSHR = { + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .URSHR = { + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SRSRA = { + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .URSRA = { + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SSHL = { + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USHL = { + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SLI = { + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SRI = { + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SSHLL = { + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SSHLL2 = { + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHLL = { + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHLL2 = { + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SXTL = { + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SXTL2 = { + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UXTL = { + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UXTL2 = { + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SHRN = { + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SHRN2 = { + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .RSHRN = { + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .RSHRN2 = { + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SQSHRN = { + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRN2 = { + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQSHRN = { + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQSHRN2 = { + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRN = { + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRN2 = { + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQRSHRN = { + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQRSHRN2 = { + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRUN = { + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRUN2 = { + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRUN = { + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRUN2 = { + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .DUP_V = { + {{.DUP_V, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP_V, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .INS = { + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, + }, + .MOV_V = { + {{.MOV_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .EXT_V = { + {{.EXT_V, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EXT_V, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .TBL = { + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .TBX = { + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .ZIP1 = { + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .ZIP2 = { + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UZP1 = { + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .UZP2 = { + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .TRN1 = { + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .TRN2 = { + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .NOT_V = { + {{.NOT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .RBIT_V = { + {{.RBIT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .REV16_V = { + {{.REV16_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .REV32_V = { + {{.REV32_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .REV64 = { + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CLS_V = { + {{.CLS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CLZ_V = { + {{.CLZ_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CNT = { + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .URECPE_V = { + {{.URECPE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .URSQRTE_V = { + {{.URSQRTE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .MOVI = { + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + }, + .MVNI = { + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + }, + .FMOV_V_IMM = { + {{.FMOV_V_IMM, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV_V_IMM, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV_V_IMM, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV_V_IMM, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV_V_IMM, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + }, + .LD1 = { + {{.LD1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD2 = { + {{.LD2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD3 = { + {{.LD3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD4 = { + {{.LD4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .ST1 = { + {{.ST1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + }, + .ST2 = { + {{.ST2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + }, + .ST3 = { + {{.ST3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + }, + .ST4 = { + {{.ST4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LD1R = { + {{.LD1R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD2R = { + {{.LD2R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD3R = { + {{.LD3R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD4R = { + {{.LD4R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD1_LANE = { + {{.LD1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD2_LANE = { + {{.LD2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD3_LANE = { + {{.LD3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD4_LANE = { + {{.LD4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .ST1_LANE = { + {{.ST1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST2_LANE = { + {{.ST2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST3_LANE = { + {{.ST3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST4_LANE = { + {{.ST4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .LDR_V = { + {{.LDR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STR_V = { + {{.STR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + }, + .LDP_V = { + {{.LDP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + }, + .STP_V = { + {{.STP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .LDUR_V = { + {{.LDUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .STUR_V = { + {{.STUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + }, + .SVE_ADD_Z = { + {{.SVE_ADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_SUB_Z = { + {{.SVE_SUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_SUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_SUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_SUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_SQADD_Z = { + {{.SVE_SQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_UQADD_Z = { + {{.SVE_UQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_SQSUB_Z = { + {{.SVE_SQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_UQSUB_Z = { + {{.SVE_UQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SVE_UQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_ADD_PRED = { + {{.SVE_ADD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SUB_PRED = { + {{.SVE_SUB_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SUBR_PRED = { + {{.SVE_SUBR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_MUL_PRED = { + {{.SVE_MUL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_MUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_MUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_MUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SMULH_PRED = { + {{.SVE_SMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_UMULH_PRED = { + {{.SVE_UMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SDIV_PRED = { + {{.SVE_SDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_UDIV_PRED = { + {{.SVE_UDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SMAX_PRED = { + {{.SVE_SMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_UMAX_PRED = { + {{.SVE_UMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SMIN_PRED = { + {{.SVE_SMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_UMIN_PRED = { + {{.SVE_UMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SABD_PRED = { + {{.SVE_SABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_SABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_UABD_PRED = { + {{.SVE_UABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_UABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_AND_PRED = { + {{.SVE_AND_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ORR_PRED = { + {{.SVE_ORR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_EOR_PRED = { + {{.SVE_EOR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BIC_PRED = { + {{.SVE_BIC_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ASR_PRED = { + {{.SVE_ASR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_LSL_PRED = { + {{.SVE_LSL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_LSR_PRED = { + {{.SVE_LSR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ASRR_PRED = { + {{.SVE_ASRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_ASRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_LSLR_PRED = { + {{.SVE_LSLR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSLR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSLR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSLR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_LSRR_PRED = { + {{.SVE_LSRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_LSRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ABS_PRED = { + {{.SVE_ABS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ABS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ABS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ABS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_NEG_PRED = { + {{.SVE_NEG_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_NEG_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_NEG_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_NEG_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_CLS_PRED = { + {{.SVE_CLS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_CLZ_PRED = { + {{.SVE_CLZ_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLZ_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLZ_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CLZ_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_CNT_PRED = { + {{.SVE_CNT_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CNT_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CNT_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CNT_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_MOV_PRED = { + {{.SVE_MOV_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.SVE_MOV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.SVE_MOV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.SVE_MOV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, + }, + .SVE_FADD_Z = { + {{.SVE_FADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FSUB_Z = { + {{.SVE_FSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMUL_Z = { + {{.SVE_FMUL_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMUL_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMUL_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FRECPS = { + {{.SVE_FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FRSQRTS = { + {{.SVE_FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FTSMUL = { + {{.SVE_FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FADD_PRED = { + {{.SVE_FADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FSUB_PRED = { + {{.SVE_FSUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FSUBR_PRED = { + {{.SVE_FSUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMUL_PRED = { + {{.SVE_FMUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FDIV_PRED = { + {{.SVE_FDIV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FDIVR_PRED = { + {{.SVE_FDIVR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FDIVR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FDIVR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMAX_PRED = { + {{.SVE_FMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMIN_PRED = { + {{.SVE_FMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMAXNM_PRED = { + {{.SVE_FMAXNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMAXNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMAXNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMINNM_PRED = { + {{.SVE_FMINNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMINNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMINNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FABS_Z = { + {{.SVE_FABS_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_FABS_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_FABS_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_FNEG_Z = { + {{.SVE_FNEG_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_FNEG_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_FNEG_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_FSQRT_Z = { + {{.SVE_FSQRT_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSQRT_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FSQRT_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FRECPX_Z = { + {{.SVE_FRECPX_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.SVE_FRECPX_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.SVE_FRECPX_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + }, + .SVE_FRINTN = { + {{.SVE_FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FRINTP = { + {{.SVE_FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FRINTM = { + {{.SVE_FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FRINTZ = { + {{.SVE_FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FRINTA = { + {{.SVE_FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FRINTX = { + {{.SVE_FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.SVE_FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.SVE_FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + }, + .SVE_FRINTI = { + {{.SVE_FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.SVE_FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.SVE_FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + }, + .SVE_FMLA = { + {{.SVE_FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLS = { + {{.SVE_FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.SVE_FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FNMLA = { + {{.SVE_FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SVE_FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SVE_FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SVE_FNMLS = { + {{.SVE_FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SVE_FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SVE_FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SVE_AND_P = { + {{.SVE_AND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BIC_P = { + {{.SVE_BIC_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ORR_P = { + {{.SVE_ORR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_EOR_P = { + {{.SVE_EOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_NAND_P = { + {{.SVE_NAND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_NOR_P = { + {{.SVE_NOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ORN_P = { + {{.SVE_ORN_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_SEL_P = { + {{.SVE_SEL_P, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_ANDS_P = { + {{.SVE_ANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_BICS_P = { + {{.SVE_BICS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_ORRS_P = { + {{.SVE_ORRS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_EORS_P = { + {{.SVE_EORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_NANDS_P = { + {{.SVE_NANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_NORS_P = { + {{.SVE_NORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_ORNS_P = { + {{.SVE_ORNS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_NOT_P = { + {{.SVE_NOT_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_MOV_P = { + {{.SVE_MOV_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_MOV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, + }, + .SVE_MOVS_P = { + {{.SVE_MOVS_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_PTRUE = { + {{.SVE_PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + }, + .SVE_PTRUES = { + {{.SVE_PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_PFALSE = { + {{.SVE_PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + }, + .SVE_PFIRST = { + {{.SVE_PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_PNEXT = { + {{.SVE_PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_BRKA = { + {{.SVE_BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_BRKB = { + {{.SVE_BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_BRKAS = { + {{.SVE_BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_BRKBS = { + {{.SVE_BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_BRKPA = { + {{.SVE_BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BRKPB = { + {{.SVE_BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BRKN = { + {{.SVE_BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_RDFFR = { + {{.SVE_RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + }, + .SVE_WRFFR = { + {{.SVE_WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + }, + .SVE_SETFFR = { + {{.SVE_SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, + }, + .SVE_CMPEQ = { + {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPNE = { + {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPGE = { + {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPGT = { + {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPLE = { + {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPLT = { + {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPHI = { + {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPHS = { + {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPLO = { + {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_CMPLS = { + {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_FCMEQ = { + {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMNE = { + {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMGE = { + {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMGT = { + {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMLE = { + {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMLT = { + {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + }, + .SVE_FCMUO = { + {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .SVE_DUP_Z = { + {{.SVE_DUP_Z, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_DUP_Z, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_DUP_Z, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_DUP_Z, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SVE_INSR = { + {{.SVE_INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SVE_REV_Z = { + {{.SVE_REV_Z, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_REV_Z, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_REV_Z, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.SVE_REV_Z, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SVE_REV_P = { + {{.SVE_REV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + }, + .SVE_TBL = { + {{.SVE_TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_ZIP1_Z = { + {{.SVE_ZIP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_ZIP2_Z = { + {{.SVE_ZIP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ZIP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_UZP1_Z = { + {{.SVE_UZP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_UZP2_Z = { + {{.SVE_UZP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_UZP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_TRN1_Z = { + {{.SVE_TRN1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_TRN2_Z = { + {{.SVE_TRN2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_TRN2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_ZIP1_P = { + {{.SVE_ZIP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_ZIP2_P = { + {{.SVE_ZIP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_UZP1_P = { + {{.SVE_UZP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_UZP2_P = { + {{.SVE_UZP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_TRN1_P = { + {{.SVE_TRN1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_TRN2_P = { + {{.SVE_TRN2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_CPY_Z = { + {{.SVE_CPY_Z, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CPY_Z, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CPY_Z, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_CPY_Z, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_COMPACT = { + {{.SVE_COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SVE_COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_EXT_Z = { + {{.SVE_EXT_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_LD1B = { + {{.SVE_LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1H = { + {{.SVE_LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1W = { + {{.SVE_LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1D = { + {{.SVE_LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SB = { + {{.SVE_LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SH = { + {{.SVE_LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SW = { + {{.SVE_LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_ST1B = { + {{.SVE_ST1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1H = { + {{.SVE_ST1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1W = { + {{.SVE_ST1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1D = { + {{.SVE_ST1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_LDR_Z = { + {{.SVE_LDR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .SVE_STR_Z = { + {{.SVE_STR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .SVE_LDR_P = { + {{.SVE_LDR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .SVE_STR_P = { + {{.SVE_STR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + }, + .SVE_LDFF1B = { + {{.SVE_LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .SVE_LDFF1H = { + {{.SVE_LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .SVE_LDFF1W = { + {{.SVE_LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .SVE_LDFF1D = { + {{.SVE_LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .SVE_WHILEGE = { + {{.SVE_WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILEGT = { + {{.SVE_WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILELE = { + {{.SVE_WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILELT = { + {{.SVE_WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILEHI = { + {{.SVE_WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILEHS = { + {{.SVE_WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILELO = { + {{.SVE_WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_WHILELS = { + {{.SVE_WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_SQRDMLAH = { + {{.SVE_SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_SQRDMLSH = { + {{.SVE_SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SVE_SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SVE_ADCLB = { + {{.SVE_ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_ADCLT = { + {{.SVE_ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_SBCLB = { + {{.SVE_SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_SBCLT = { + {{.SVE_SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_TBL2 = { + {{.SVE_TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_TBX = { + {{.SVE_TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, + }, + .SVE_AESE = { + {{.SVE_AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + }, + .SVE_AESD = { + {{.SVE_AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + }, + .SVE_AESMC = { + {{.SVE_AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + }, + .SVE_AESIMC = { + {{.SVE_AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + }, + .SVE_BCAX_Z = { + {{.SVE_BCAX_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_XAR_Z = { + {{.SVE_XAR_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_XAR_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_XAR_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SVE_XAR_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_EOR3_Z = { + {{.SVE_EOR3_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_MATCH = { + {{.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_NMATCH = { + {{.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SVE_HISTCNT = { + {{.SVE_HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.SVE_HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_HISTSEG = { + {{.SVE_HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .SME_SMSTART = { + {{.SME_SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, + }, + .SME_SMSTOP = { + {{.SME_SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, + }, + .SME_RDSVL = { + {{.SME_RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, + }, + .SME_ADDHA = { + {{.SME_ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_ADDVA = { + {{.SME_ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_ZERO = { + {{.SME_ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, + }, + .SME_FMOPA = { + {{.SME_FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SME_FMOPS = { + {{.SME_FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SME_BFMOPA = { + {{.SME_BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SME_BFMOPS = { + {{.SME_BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SME_SMOPA = { + {{.SME_SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SME_SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_SMOPS = { + {{.SME_SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SME_SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_UMOPA = { + {{.SME_UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SME_UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_UMOPS = { + {{.SME_UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SME_UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_USMOPA = { + {{.SME_USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_SUMOPA = { + {{.SME_SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SME_LDR_ZA = { + {{.SME_LDR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, + }, + .SME_STR_ZA = { + {{.SME_STR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, + }, + .SVE_FMLA_IDX_H = { + {{.SVE_FMLA_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLA_IDX_S = { + {{.SVE_FMLA_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLA_IDX_D = { + {{.SVE_FMLA_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLS_IDX_H = { + {{.SVE_FMLS_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLS_IDX_S = { + {{.SVE_FMLS_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_FMLS_IDX_D = { + {{.SVE_FMLS_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_LD1B_GATHER_S = { + {{.SVE_LD1B_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1B_GATHER_D = { + {{.SVE_LD1B_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1H_GATHER_S = { + {{.SVE_LD1H_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1H_GATHER_D = { + {{.SVE_LD1H_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1W_GATHER_S = { + {{.SVE_LD1W_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1W_GATHER_D = { + {{.SVE_LD1W_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1D_GATHER_D = { + {{.SVE_LD1D_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SB_GATHER_S = { + {{.SVE_LD1SB_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SB_GATHER_D = { + {{.SVE_LD1SB_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SH_GATHER_S = { + {{.SVE_LD1SH_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SH_GATHER_D = { + {{.SVE_LD1SH_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LD1SW_GATHER_D = { + {{.SVE_LD1SW_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_ST1B_SCATTER_S = { + {{.SVE_ST1B_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1B_SCATTER_D = { + {{.SVE_ST1B_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1H_SCATTER_S = { + {{.SVE_ST1H_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1H_SCATTER_D = { + {{.SVE_ST1H_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1W_SCATTER_S = { + {{.SVE_ST1W_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1W_SCATTER_D = { + {{.SVE_ST1W_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_ST1D_SCATTER_D = { + {{.SVE_ST1D_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_LD1B_TILE = { + {{.SME_LD1B_TILE, {.SME_SLICE_B, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME_LD1H_TILE = { + {{.SME_LD1H_TILE, {.SME_SLICE_H, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME_LD1W_TILE = { + {{.SME_LD1W_TILE, {.SME_SLICE_W, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME_LD1D_TILE = { + {{.SME_LD1D_TILE, {.SME_SLICE_D, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME_LD1Q_TILE = { + {{.SME_LD1Q_TILE, {.SME_SLICE_Q, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME_ST1B_TILE = { + {{.SME_ST1B_TILE, {.SME_SLICE_B, .P_REG, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_ST1H_TILE = { + {{.SME_ST1H_TILE, {.SME_SLICE_H, .P_REG, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_ST1W_TILE = { + {{.SME_ST1W_TILE, {.SME_SLICE_W, .P_REG, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_ST1D_TILE = { + {{.SME_ST1D_TILE, {.SME_SLICE_D, .P_REG, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_ST1Q_TILE = { + {{.SME_ST1Q_TILE, {.SME_SLICE_Q, .P_REG, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME_MOVA_Z_FROM_TILE = { + {{.SME_MOVA_Z_FROM_TILE, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .SME_MOVA_TILE_FROM_Z = { + {{.SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .FCMLA_4H = { + {{.FCMLA_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCMLA_8H = { + {{.FCMLA_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCMLA_4S = { + {{.FCMLA_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCMLA_2D = { + {{.FCMLA_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCADD_4H = { + {{.FCADD_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCADD_8H = { + {{.FCADD_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCADD_4S = { + {{.FCADD_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCADD_2D = { + {{.FCADD_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_PRFB = { + {{.SVE_PRFB, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .SVE_PRFH = { + {{.SVE_PRFH, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .SVE_PRFW = { + {{.SVE_PRFW, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .SVE_PRFD = { + {{.SVE_PRFD, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .SVE_LDNT1B = { + {{.SVE_LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LDNT1H = { + {{.SVE_LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LDNT1W = { + {{.SVE_LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_LDNT1D = { + {{.SVE_LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SVE_STNT1B = { + {{.SVE_STNT1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_STNT1H = { + {{.SVE_STNT1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_STNT1W = { + {{.SVE_STNT1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_STNT1D = { + {{.SVE_STNT1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SVE_EXT = { + {{.SVE_EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_SPLICE = { + {{.SVE_SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_INDEX_II = { + {{.SVE_INDEX_II, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + }, + .SVE_INDEX_IR = { + {{.SVE_INDEX_IR, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, + }, + .SVE_INDEX_RI = { + {{.SVE_INDEX_RI, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, + }, + .SVE_INDEX_RR = { + {{.SVE_INDEX_RR, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_BSL = { + {{.SVE_BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SVE_BSL1N = { + {{.SVE_BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BSL2N = { + {{.SVE_BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_NBSL = { + {{.SVE_NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_PMUL_VEC = { + {{.SVE_PMUL_VEC, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_PMULLB = { + {{.SVE_PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_PMULLT = { + {{.SVE_PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SVE_BFCVT = { + {{.SVE_BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFCVTNT = { + {{.SVE_BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .LDRAA = { + {{.LDRAA, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRAB = { + {{.LDRAB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LDRAA_PRE = { + {{.LDRAA_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .LDRAB_PRE = { + {{.LDRAB_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .TSTART = { + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, + }, + .TCOMMIT = { + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, + }, + .TCANCEL = { + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, + }, + .TTEST = { + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, + }, + .WFET = { + {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + }, + .WFIT = { + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + }, + .BC_COND = { + {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + }, + .UXTB = { + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .UXTH = { + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .UXTW = { + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SXTB = { + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .SXTH = { + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .SXTW = { + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ADC = { + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + }, + .ADCS = { + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .SBC = { + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + }, + .SBCS = { + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .NGC = { + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, + }, + .NGCS = { + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .LDAPUR = { + {{.LDAPUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLUR = { + {{.STLUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURB = { + {{.LDAPURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLURB = { + {{.STLURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURH = { + {{.LDAPURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLURH = { + {{.STLURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSB = { + {{.LDAPURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSH = { + {{.LDAPURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSW = { + {{.LDAPURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .SVE_BFADD = { + {{.SVE_BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFSUB = { + {{.SVE_BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFMUL = { + {{.SVE_BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFMLA = { + {{.SVE_BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFMLS = { + {{.SVE_BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SB = { + {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .CSDB = { + {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .DGH = { + {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .PSB_CSYNC = { + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .TSB_CSYNC = { + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .BTI_J = { + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .BTI_C = { + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .BTI_JC = { + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .MOV_V_ALIAS = { + {{.MOV_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .NOT_V_ALIAS = { + {{.NOT_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .LSL_IMM = { + {{.LSL_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.LSL_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .LSR_IMM = { + {{.LSR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ASR_IMM = { + {{.ASR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ROR_IMM = { + {{.ROR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ROR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SVE_BFADD_UNPRED = { + {{.SVE_BFADD_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFSUB_UNPRED = { + {{.SVE_BFSUB_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFMUL_UNPRED = { + {{.SVE_BFMUL_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SVE_BFCLAMP = { + {{.SVE_BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .SVE_BFMAXNM = { + {{.SVE_BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SVE_BFMINNM = { + {{.SVE_BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SME2_LUTI2_B = { + {{.SME2_LUTI2_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + }, + .SME2_LUTI4_B = { + {{.SME2_LUTI4_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + }, + .SME2_LD1B_X2 = { + {{.SME2_LD1B_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1H_X2 = { + {{.SME2_LD1H_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1W_X2 = { + {{.SME2_LD1W_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1D_X2 = { + {{.SME2_LD1D_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1B_X4 = { + {{.SME2_LD1B_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1H_X4 = { + {{.SME2_LD1H_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1W_X4 = { + {{.SME2_LD1W_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_LD1D_X4 = { + {{.SME2_LD1D_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .SME2_ST1B_X2 = { + {{.SME2_ST1B_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1H_X2 = { + {{.SME2_ST1H_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1W_X2 = { + {{.SME2_ST1W_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1D_X2 = { + {{.SME2_ST1D_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1B_X4 = { + {{.SME2_ST1B_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1H_X4 = { + {{.SME2_ST1H_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1W_X4 = { + {{.SME2_ST1W_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ST1D_X4 = { + {{.SME2_ST1D_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SME2_ZIP_3 = { + {{.SME2_ZIP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .SME2_ZIP_4 = { + {{.SME2_ZIP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .SME2_UZP_3 = { + {{.SME2_UZP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .SME2_UZP_4 = { + {{.SME2_UZP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .TLBI_RPALOS = { + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_RPAOS = { + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E1A = { + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .DC_CIPAPA = { + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CIGDPAPA = { + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .TLBI_PAALL = { + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_PAALLOS = { + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .AMX_LDX = { + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDY = { + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STX = { + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STY = { + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDZ = { + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STZ = { + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDZI = { + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STZI = { + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_EXTRX = { + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_EXTRY = { + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA64 = { + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS64 = { + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA32 = { + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS32 = { + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MAC16 = { + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA16 = { + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS16 = { + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_SET = { + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, + }, + .AMX_CLR = { + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, + }, + .AMX_VECINT = { + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_VECFP = { + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MATINT = { + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MATFP = { + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_GENLUT = { + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .CPYP = { + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYM = { + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYE = { + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFP = { + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFM = { + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFE = { + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .SETP = { + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .SETM = { + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .SETE = { + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .DC_IVAC = { + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_ISW = { + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_CSW = { + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_CISW = { + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_ZVA = { + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, + }, + .DC_CVAC = { + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CVAU = { + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CIVAC = { + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .IC_IALLUIS = { + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + }, + .IC_IALLU = { + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + }, + .IC_IVAU = { + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .AT_S1E1R = { + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E1W = { + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E0R = { + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E0W = { + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E2R = { + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E2W = { + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E3R = { + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E3W = { + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E1R = { + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E1W = { + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E0R = { + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E0W = { + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VMALLE1 = { + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_VMALLE1IS = { + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAE1 = { + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAE1IS = { + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ASIDE1 = { + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ASIDE1IS = { + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAAE1 = { + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAAE1IS = { + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VALE1 = { + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VALE1IS = { + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAALE1 = { + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAALE1IS = { + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE1 = { + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE1IS = { + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE2 = { + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE2IS = { + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE3 = { + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE3IS = { + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .PRFM = { + {{.PRFM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + }, + .PRFUM = { + {{.PRFUM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + }, + .PRFM_LIT = { + {{.PRFM_LIT, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, + }, + .MOV_REG = { + {{.MOV_REG, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MOV_REG, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .MOV_BITMASK = { + {{.MOV_BITMASK, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, + {{.MOV_BITMASK, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + }, + .MVN = { + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .NEG_SR = { + {{.NEG_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, + {{.NEG_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .NEGS = { + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMP_SR = { + {{.CMP_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMP_ER = { + {{.CMP_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMP_IMM = { + {{.CMP_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMN_SR = { + {{.CMN_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMN_ER = { + {{.CMN_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMN_IMM = { + {{.CMN_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .TST_SR = { + {{.TST_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + }, +} \ No newline at end of file From 82fd8791bfb24bdeb1a676813ccfb1078c72eee7 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 26 Aug 2026 14:14:02 +0100 Subject: [PATCH 05/89] Use `INSTRUCTION_TABLE` now --- .../isa/arm64/tablegen/clobber_table.odin | 3612 ------------ .../isa/arm64/tablegen/encoding_table.odin | 4887 ----------------- core/rexcode/isa/arm64/tablegen/gen.odin | 105 +- .../tablegen/generated/encode_tables.odin | 3547 ++++++++++++ .../isa/arm64/tablegen/generated/writer.odin | 1 + .../isa/arm64/tablegen/instruction_table.odin | 86 + core/rexcode/isa/arm64/tables.odin | 9 +- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 0 -> 34160 bytes 8 files changed, 3732 insertions(+), 8515 deletions(-) delete mode 100644 core/rexcode/isa/arm64/tablegen/clobber_table.odin delete mode 100644 core/rexcode/isa/arm64/tablegen/encoding_table.odin create mode 100644 core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin diff --git a/core/rexcode/isa/arm64/tablegen/clobber_table.odin b/core/rexcode/isa/arm64/tablegen/clobber_table.odin deleted file mode 100644 index a217df0de..000000000 --- a/core/rexcode/isa/arm64/tablegen/clobber_table.odin +++ /dev/null @@ -1,3612 +0,0 @@ -package rexcode_arm64_tablegen - -// rexcode ยท AArch64 CLOBBER_TABLE -// ============================================================================= -// Read/write + side-effect summary for every form of every mnemonic in -// ENCODING_TABLE. One Clobber per Encoding form; the slices are index-aligned -// with ENCODING_TABLE so CLOBBER_TABLE[m][i] describes ENCODING_TABLE[m][i]. -// -// Derivation (from each row's operand TYPES, operand ROLES, and Encoding_Flags): -// -// written / read -- operand slots (0..3) whose register / memory base is a -// def / use. A slot counts only if its TYPE is register- -// or memory-like; immediate slots never appear. Direction -// comes from the ROLE, refined by instruction class: -// * RD/VD/PD/RT/RT2/ZA_TILE* are destinations, EXCEPT -// the data operand of a store (RT/VD on ST*), which is -// a source; and the status result of STXR/STXP (RD), -// which stays a def while RT/RT2 become sources. -// * A pre/post-index base (OFFSET_BASE_PRE/POST) is both -// read and written (address write-back). -// * A destination register re-listed as a later source -// slot (SVE destructive Zdn, accumulate) is read. -// * Branches define no GPR operand; targets/modifiers -// are reads. -// implicit_wr/rd -- LR on BL/BLR/RET, LR+SP on PAC*SP / RETAA, X16/X17 on -// PAC*1716, etc. -// nzcv_wr -- set for sets_flags forms (ADDS/SUBS/ANDS/CMP/CCMP/FCMP, -// SVE compares, WHILE*, PTRUES, ...). -// nzcv_rd -- any COND operand (CSEL/FCSEL/B.cond/CCMP), plus the -// carry readers ADC/ADCS/SBC/SBCS/NGC/NGCS; CCMP/CCMN both. -// fpsr_wr/reads_fpcr -- per FP-op family (see notes); saturating integer ops -// (SQ*/UQ*/SUQ*/USQ*/SQRDML*) set QC. -// reads_mem/writes_mem -- loads / stores / RMW atomics / MOPS. -// side_effects -- control flow, barriers, atomics, cache/TLB, PAC, BTI, -// wait, privileged system access, FFR, etc. -// -// Heuristic / best-effort fields (structurally faithful, semantically approximate): -// * FPSR exception-bit sets and reads_fpcr are assigned per mnemonic family, -// not per-corner-case; treat them as "flags this class may raise". -// * Accumulate detection (destination is read-modified) is name-driven for -// the families that fold the accumulator into the destination (MLA/MLS/DOT/ -// FMLA/FCMLA/SQRDML*/MOPA, shift-accumulate, bit-insert, AES/SHA/SM3/SM4, -// PAC in-place). Multiply-adds with a separate Ra/Va operand (MADD/FMADD/...) -// are correctly NOT dest-reads. -// * LD1-4/ST1-4 register lists occupy a single operand slot, so max operand -// count stays at 4 (matches Operand_Set / the encoder's model). -// * Acquire/release accesses carry the FENCE side effect to model their -// one-way ordering (distinct from the register/memory read/write sets). -// * Requires the companion clobber_types.odin (adds X16/X17 to Clobber_Reg -// and FFR to Side_Effect). -// ============================================================================= - - -@(rodata) -CLOBBER_TABLE := [Mnemonic][]Clobber{ - .INVALID = {}, - - .ADD_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .ADDS_IMM = { - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SUB_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SUBS_IMM = { - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .MOVN = { - {written={0}, read={}}, - {written={0}, read={}}, - }, - .MOVZ = { - {written={0}, read={}}, - {written={0}, read={}}, - }, - .MOVK = { - {written={0}, read={}}, - {written={0}, read={}}, - }, - .ADR = { {written={0}, read={}} }, - .ADRP = { {written={0}, read={}} }, - .ADD_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ADDS_SR = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SUB_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SUBS_SR = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .AND_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .BIC_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ORR_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ORN_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .EOR_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .EON_SR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ANDS_SR = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .BICS_SR = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .ADD_ER = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ADDS_ER = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SUB_ER = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SUBS_ER = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .UDIV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SDIV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .LSLV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .LSRV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ASRV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .RORV = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .MADD = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .MSUB = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SMADDL = { {written={0}, read={1, 2, 3}} }, - .SMSUBL = { {written={0}, read={1, 2, 3}} }, - .UMADDL = { {written={0}, read={1, 2, 3}} }, - .UMSUBL = { {written={0}, read={1, 2, 3}} }, - .SMULH = { {written={0}, read={1, 2}} }, - .UMULH = { {written={0}, read={1, 2}} }, - .RBIT = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV16 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV32 = { {written={0}, read={1}} }, - .CLZ = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .CLS = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .EXTR = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CSEL = { - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CSINC = { - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CSINV = { - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CSNEG = { - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CCMP_REG = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CCMN_REG = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CCMP_IMM = { - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .CCMN_IMM = { - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .HINT = { {written={}, read={}, side_effects={.HINT}} }, - .MSR_IMM = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .USDOT = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .FMOV_IMM = { - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - }, - .FMOV_V_IMM = { - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - }, - .LDRB_POST = { {written={0, 1}, read={1}, reads_mem=true} }, - .LDRB_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, - .LDRB_REG = { {written={0}, read={1}, reads_mem=true} }, - .LDRH_POST = { {written={0, 1}, read={1}, reads_mem=true} }, - .LDRH_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, - .LDRH_REG = { {written={0}, read={1}, reads_mem=true} }, - .STRB_POST = { {written={1}, read={0, 1}, writes_mem=true} }, - .STRB_PRE = { {written={1}, read={0, 1}, writes_mem=true} }, - .STRB_REG = { {written={}, read={0, 1}, writes_mem=true} }, - .STRH_POST = { {written={1}, read={0, 1}, writes_mem=true} }, - .STRH_PRE = { {written={1}, read={0, 1}, writes_mem=true} }, - .STRH_REG = { {written={}, read={0, 1}, writes_mem=true} }, - .LDRSB_REG = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDRSH_REG = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDRSW_REG = { {written={0}, read={1}, reads_mem=true} }, - .LDP_V = { - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - }, - .STP_V = { - {written={}, read={0, 1, 2}, writes_mem=true}, - {written={}, read={0, 1, 2}, writes_mem=true}, - {written={}, read={0, 1, 2}, writes_mem=true}, - }, - .LDUR_V = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .STUR_V = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .B = { {written={}, read={}, side_effects={.CONTROL}} }, - .BL = { {written={}, read={}, implicit_wr={.LR}, side_effects={.CONTROL}} }, - .B_COND = { {written={}, read={}, nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}} }, - .CBZ = { - {written={}, read={0}, side_effects={.CONTROL}}, - {written={}, read={0}, side_effects={.CONTROL}}, - }, - .CBNZ = { - {written={}, read={0}, side_effects={.CONTROL}}, - {written={}, read={0}, side_effects={.CONTROL}}, - }, - .TBZ = { {written={}, read={0}, side_effects={.CONTROL}} }, - .TBNZ = { {written={}, read={0}, side_effects={.CONTROL}} }, - .BR = { {written={}, read={0}, side_effects={.CONTROL}} }, - .BLR = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL}} }, - .RET = { - {written={}, read={0}, side_effects={.CONTROL}}, - {written={}, read={}, implicit_rd={.LR}, side_effects={.CONTROL}}, - }, - .LDR = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .STR = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .LDRB = { {written={0}, read={1}, reads_mem=true} }, - .STRB = { {written={}, read={0, 1}, writes_mem=true} }, - .LDRSB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDRH = { {written={0}, read={1}, reads_mem=true} }, - .STRH = { {written={}, read={0, 1}, writes_mem=true} }, - .LDRSH = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDRSW = { {written={0}, read={1}, reads_mem=true} }, - .LDR_LIT = { - {written={0}, read={}}, - {written={0}, read={}}, - }, - .LDP = { - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - }, - .STP = { - {written={}, read={0, 1, 2}, writes_mem=true}, - {written={}, read={0, 1, 2}, writes_mem=true}, - }, - .LDPSW = { {written={0, 1}, read={2}, reads_mem=true} }, - .NOP = { {written={}, read={}, side_effects={.HINT}} }, - .YIELD = { {written={}, read={}, side_effects={.HINT}} }, - .WFE = { {written={}, read={}, side_effects={.WAIT}} }, - .WFI = { {written={}, read={}, side_effects={.WAIT}} }, - .SEV = { {written={}, read={}, side_effects={.HINT}} }, - .SEVL = { {written={}, read={}, side_effects={.HINT}} }, - .ISB = { {written={}, read={}, side_effects={.ISYNC}} }, - .DSB = { {written={}, read={}, side_effects={.FENCE}} }, - .DMB = { {written={}, read={}, side_effects={.FENCE}} }, - .SVC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION}} }, - .HVC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}} }, - .SMC = { {written={}, read={}, side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}} }, - .BRK = { {written={}, read={}, side_effects={.CONTROL, .TRAP}} }, - .HLT = { {written={}, read={}, side_effects={.CONTROL, .TRAP}} }, - .ERET = { {written={}, read={}, side_effects={.CONTROL, .PRIVILEGED}} }, - .MRS = { {written={0}, read={1}, side_effects={.PRIVILEGED}} }, - .MSR_REG = { {written={0}, read={1}, side_effects={.PRIVILEGED}} }, - .FABS = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FNEG = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FSQRT = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FADD = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FSUB = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMUL = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FDIV = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FNMUL = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMAX = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMIN = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMAXNM = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINNM = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMADD = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMSUB = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FNMADD = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FNMSUB = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FCMP = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - }, - .FCMPE = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - }, - .FCSEL = { - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - }, - .FCVT = { - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SCVTF = { - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - }, - .UCVTF = { - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - }, - .FCVTZS = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTZU = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FMOV_REG = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FMOV_GEN = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .AND_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .ORR_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .EOR_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .ANDS_IMM = { - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .TST_IMM = { - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .LDUR = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .STUR = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .LDURB = { {written={0}, read={1}, reads_mem=true} }, - .STURB = { {written={}, read={0, 1}, writes_mem=true} }, - .LDURH = { {written={0}, read={1}, reads_mem=true} }, - .STURH = { {written={}, read={0, 1}, writes_mem=true} }, - .LDURSB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDURSH = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .LDURSW = { {written={0}, read={1}, reads_mem=true} }, - .LDR_PRE = { - {written={0, 1}, read={1}, reads_mem=true}, - {written={0, 1}, read={1}, reads_mem=true}, - }, - .STR_PRE = { - {written={1}, read={0, 1}, writes_mem=true}, - {written={1}, read={0, 1}, writes_mem=true}, - }, - .LDR_POST = { - {written={0, 1}, read={1}, reads_mem=true}, - {written={0, 1}, read={1}, reads_mem=true}, - }, - .STR_POST = { - {written={1}, read={0, 1}, writes_mem=true}, - {written={1}, read={0, 1}, writes_mem=true}, - }, - .LDR_REG = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .STR_REG = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .LDP_PRE = { - {written={0, 1, 2}, read={2}, reads_mem=true}, - {written={0, 1, 2}, read={2}, reads_mem=true}, - }, - .STP_PRE = { - {written={2}, read={0, 1, 2}, writes_mem=true}, - {written={2}, read={0, 1, 2}, writes_mem=true}, - }, - .LDP_POST = { - {written={0, 1, 2}, read={2}, reads_mem=true}, - {written={0, 1, 2}, read={2}, reads_mem=true}, - }, - .STP_POST = { - {written={2}, read={0, 1, 2}, writes_mem=true}, - {written={2}, read={0, 1, 2}, writes_mem=true}, - }, - .LDPSW_PRE = { {written={0, 1, 2}, read={2}, reads_mem=true} }, - .LDPSW_POST = { {written={0, 1, 2}, read={2}, reads_mem=true} }, - .LDNP = { - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - }, - .STNP = { - {written={}, read={0, 1, 2}, writes_mem=true}, - {written={}, read={0, 1, 2}, writes_mem=true}, - }, - .LDXR = { - {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - }, - .STXR = { - {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - }, - .LDAXR = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - }, - .STLXR = { - {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - }, - .LDXRB = { {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, - .STXRB = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, - .LDAXRB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, - .STLXRB = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, - .LDXRH = { {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, - .STXRH = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}} }, - .LDAXRH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, - .STLXRH = { {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}} }, - .LDXP = { - {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - }, - .STXP = { - {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, - }, - .LDAXP = { - {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - }, - .STLXP = { - {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, - }, - .LDAR = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - }, - .STLR = { - {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, - {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, - }, - .LDARB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .STLRB = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, - .LDARH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .STLRH = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, - .LDAPR = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - }, - .LDAPRB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .LDAPRH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .LDADD = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDADDA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDADDL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDADDAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDCLR = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDCLRA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDCLRL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDCLRAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDEOR = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDEORA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDEORL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDEORAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSET = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDSETA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSETL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSETAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMAX = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDSMAXA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMAXL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMAXAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMIN = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDSMINA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMINL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDSMINAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMAX = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDUMAXA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMAXL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMAXAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMIN = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .LDUMINA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMINL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .LDUMINAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .SWP = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .SWPA = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .SWPL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .SWPAL = { - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CAS = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .CASA = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CASL = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CASAL = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CASB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}} }, - .CASAB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASLB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASALB = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}} }, - .CASAH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASLH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASALH = { {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}} }, - .CASP = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, - }, - .CASPA = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CASPL = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CASPAL = { - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, - }, - .CRC32B = { {written={0}, read={1, 2}} }, - .CRC32H = { {written={0}, read={1, 2}} }, - .CRC32W = { {written={0}, read={1, 2}} }, - .CRC32X = { {written={0}, read={1, 2}} }, - .CRC32CB = { {written={0}, read={1, 2}} }, - .CRC32CH = { {written={0}, read={1, 2}} }, - .CRC32CW = { {written={0}, read={1, 2}} }, - .CRC32CX = { {written={0}, read={1, 2}} }, - .AESE = { {written={0}, read={0, 1}} }, - .AESD = { {written={0}, read={0, 1}} }, - .AESMC = { {written={0}, read={0, 1}} }, - .AESIMC = { {written={0}, read={0, 1}} }, - .SHA1H = { {written={0}, read={1}} }, - .SHA1SU1 = { {written={0}, read={0, 1}} }, - .SHA1C = { {written={0}, read={0, 1, 2}} }, - .SHA1P = { {written={0}, read={0, 1, 2}} }, - .SHA1M = { {written={0}, read={0, 1, 2}} }, - .SHA1SU0 = { {written={0}, read={0, 1, 2}} }, - .SHA256H = { {written={0}, read={0, 1, 2}} }, - .SHA256H2 = { {written={0}, read={0, 1, 2}} }, - .SHA256SU0 = { {written={0}, read={0, 1}} }, - .SHA256SU1 = { {written={0}, read={0, 1, 2}} }, - .SHA512H = { {written={0}, read={0, 1, 2}} }, - .SHA512H2 = { {written={0}, read={0, 1, 2}} }, - .SHA512SU0 = { {written={0}, read={0, 1}} }, - .SHA512SU1 = { {written={0}, read={0, 1, 2}} }, - .EOR3 = { {written={0}, read={1, 2, 3}} }, - .BCAX = { {written={0}, read={1, 2, 3}} }, - .RAX1 = { {written={0}, read={1, 2}} }, - .XAR = { {written={0}, read={1, 2}} }, - .SM3PARTW1 = { {written={0}, read={0, 1, 2}} }, - .SM3PARTW2 = { {written={0}, read={0, 1, 2}} }, - .SM3SS1 = { {written={0}, read={1, 2, 3}} }, - .SM3TT1A = { {written={0}, read={0, 1, 2}} }, - .SM3TT1B = { {written={0}, read={0, 1, 2}} }, - .SM3TT2A = { {written={0}, read={0, 1, 2}} }, - .SM3TT2B = { {written={0}, read={0, 1, 2}} }, - .SM4E = { {written={0}, read={0, 1}} }, - .SM4EKEY = { {written={0}, read={1, 2}} }, - .PMULL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .PMULL2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .PACIA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .PACIB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .PACDA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .PACDB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .AUTIA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .AUTIB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .AUTDA = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .AUTDB = { {written={0}, read={0, 1}, side_effects={.PAC}} }, - .PACIZA = { {written={0}, read={0}, side_effects={.PAC}} }, - .PACIZB = { {written={0}, read={0}, side_effects={.PAC}} }, - .PACDZA = { {written={0}, read={0}, side_effects={.PAC}} }, - .PACDZB = { {written={0}, read={0}, side_effects={.PAC}} }, - .AUTIZA = { {written={0}, read={0}, side_effects={.PAC}} }, - .AUTIZB = { {written={0}, read={0}, side_effects={.PAC}} }, - .AUTDZA = { {written={0}, read={0}, side_effects={.PAC}} }, - .AUTDZB = { {written={0}, read={0}, side_effects={.PAC}} }, - .XPACI = { {written={0}, read={0}, side_effects={.PAC}} }, - .XPACD = { {written={0}, read={0}, side_effects={.PAC}} }, - .XPACLRI = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}} }, - .PACIASP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, - .PACIBSP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, - .AUTIASP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, - .AUTIBSP = { {written={}, read={}, implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}} }, - .PACIA1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, - .PACIB1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, - .AUTIA1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, - .AUTIB1716 = { {written={}, read={}, implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}} }, - .PACGA = { {written={0}, read={0, 1, 2}, side_effects={.PAC}} }, - .RETAA = { {written={}, read={}, implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}} }, - .RETAB = { {written={}, read={}, implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}} }, - .BRAA = { {written={}, read={0, 1}, side_effects={.CONTROL, .PAC}} }, - .BRAB = { {written={}, read={0, 1}, side_effects={.CONTROL, .PAC}} }, - .BLRAA = { {written={}, read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, - .BLRAB = { {written={}, read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, - .BRAAZ = { {written={}, read={0}, side_effects={.CONTROL, .PAC}} }, - .BRABZ = { {written={}, read={0}, side_effects={.CONTROL, .PAC}} }, - .BLRAAZ = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, - .BLRABZ = { {written={}, read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}} }, - .ERETAA = { {written={}, read={}, side_effects={.CONTROL, .PAC, .PRIVILEGED}} }, - .ERETAB = { {written={}, read={}, side_effects={.CONTROL, .PAC, .PRIVILEGED}} }, - .BTI = { {written={}, read={}, side_effects={.BTI}} }, - .ADDG = { {written={0}, read={1}} }, - .SUBG = { {written={0}, read={1}} }, - .IRG = { {written={0}, read={1, 2}} }, - .GMI = { {written={0}, read={1, 2}} }, - .SUBP = { {written={0}, read={1, 2}} }, - .SUBPS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .STG = { {written={}, read={0, 1}, writes_mem=true} }, - .STZG = { {written={}, read={0, 1}, writes_mem=true} }, - .ST2G = { {written={}, read={0, 1}, writes_mem=true} }, - .STZ2G = { {written={}, read={0, 1}, writes_mem=true} }, - .LDG = { {written={0}, read={1}, reads_mem=true} }, - .STGM = { {written={}, read={0, 1}, writes_mem=true} }, - .LDGM = { {written={0}, read={1}, reads_mem=true} }, - .STZGM = { {written={}, read={0, 1}, writes_mem=true} }, - .STGP = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .FABS_H = { {written={0}, read={1}} }, - .FNEG_H = { {written={0}, read={1}} }, - .FSQRT_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true} }, - .FADD_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FSUB_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FMUL_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FDIV_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FNMUL_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FMAX_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, - .FMIN_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, - .FMAXNM_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, - .FMINNM_H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true} }, - .FCMP_H = { {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}} }, - .FCMPE_H = { {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}} }, - .FCSEL_H = { {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}} }, - .FMADD_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FMSUB_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FNMADD_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FNMSUB_H = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCVT_H_S = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCVT_H_D = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCVT_S_H = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCVT_D_H = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SCVTF_H = { {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true} }, - .UCVTF_H = { {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true} }, - .FCVTZS_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, - .FCVTZU_H = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, - .FMOV_H = { {written={0}, read={1}} }, - .BFCVT = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFCVTN = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFCVTN2 = { {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFDOT = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFMMLA = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFMLALB = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .BFMLALT = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .ADD_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SUB_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .MUL_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CMEQ = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CMGT = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CMHI = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .AND_V = { {written={0}, read={1, 2}} }, - .ORR_V = { {written={0}, read={1, 2}} }, - .EOR_V = { {written={0}, read={1, 2}} }, - .BIC_V = { {written={0}, read={1, 2}} }, - .ORN_V = { {written={0}, read={1, 2}} }, - .BIT = { {written={0}, read={0, 1, 2}} }, - .BIF = { {written={0}, read={0, 1, 2}} }, - .BSL = { {written={0}, read={0, 1, 2}} }, - .FADD_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FSUB_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMUL_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FDIV_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMLA_V = { - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMLS_V = { - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SDOT = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UDOT = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .LD1 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .ST1 = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .TBL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .TBX = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .LD2 = { {written={0}, read={1}, reads_mem=true} }, - .LD3 = { {written={0}, read={1}, reads_mem=true} }, - .LD4 = { {written={0}, read={1}, reads_mem=true} }, - .ST2 = { {written={}, read={0, 1}, writes_mem=true} }, - .ST3 = { {written={}, read={0, 1}, writes_mem=true} }, - .ST4 = { {written={}, read={0, 1}, writes_mem=true} }, - .LD1R = { {written={0}, read={1}, reads_mem=true} }, - .LD2R = { {written={0}, read={1}, reads_mem=true} }, - .LD3R = { {written={0}, read={1}, reads_mem=true} }, - .LD4R = { {written={0}, read={1}, reads_mem=true} }, - .LD1_LANE = { - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - }, - .LD2_LANE = { - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - }, - .LD3_LANE = { - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - }, - .LD4_LANE = { - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - }, - .ST1_LANE = { - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - }, - .ST2_LANE = { - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - }, - .ST3_LANE = { - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - }, - .ST4_LANE = { - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - {written={}, read={0, 2}, writes_mem=true}, - }, - .LDR_V = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .STR_V = { - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - {written={}, read={0, 1}, writes_mem=true}, - }, - .SVE_ADD_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_SUB_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_SQADD_Z = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SVE_UQADD_Z = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SVE_SQSUB_Z = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SVE_UQSUB_Z = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SVE_ADD_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SUB_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SUBR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_MUL_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SMULH_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_UMULH_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SDIV_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_UDIV_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SMAX_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_UMAX_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SMIN_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_UMIN_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_SABD_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_UABD_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_AND_PRED = { {written={0}, read={1, 2, 3}} }, - .SVE_ORR_PRED = { {written={0}, read={1, 2, 3}} }, - .SVE_EOR_PRED = { {written={0}, read={1, 2, 3}} }, - .SVE_BIC_PRED = { {written={0}, read={1, 2, 3}} }, - .SVE_ASR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_LSR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_LSL_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_ABS_PRED = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_NEG_PRED = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_CLS_PRED = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_CLZ_PRED = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_CNT_PRED = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_FADD_Z = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FSUB_Z = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMUL_Z = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FRECPS = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FRSQRTS = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FTSMUL = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FADD_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FSUB_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMUL_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FDIV_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMAX_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMIN_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMAXNM_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMINNM_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .SVE_FABS_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_FNEG_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_FSQRT_Z = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMLA = { - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FMLS = { - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FNMLA = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SVE_FNMLS = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SVE_AND_P = { {written={0}, read={1, 2, 3}} }, - .SVE_BIC_P = { {written={0}, read={1, 2, 3}} }, - .SVE_ORR_P = { {written={0}, read={1, 2, 3}} }, - .SVE_ORN_P = { {written={0}, read={1, 2, 3}} }, - .SVE_EOR_P = { {written={0}, read={1, 2, 3}} }, - .SVE_NAND_P = { {written={0}, read={1, 2, 3}} }, - .SVE_NOR_P = { {written={0}, read={1, 2, 3}} }, - .SVE_SEL_P = { {written={0}, read={1, 2, 3}} }, - .SVE_ANDS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_BICS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_ORRS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_EORS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_PTRUE = { {written={0}, read={}} }, - .SVE_PTRUES = { {written={0}, read={}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_PFALSE = { {written={0}, read={}} }, - .SVE_PFIRST = { {written={0}, read={1, 2}} }, - .SVE_PNEXT = { {written={0}, read={1, 2}} }, - .SVE_CPY_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_EXT_Z = { {written={0}, read={1, 2}} }, - .SVE_MOV_PRED = { - {written={}, read={0, 1, 2}}, - {written={}, read={0, 1, 2}}, - {written={}, read={0, 1, 2}}, - {written={}, read={0, 1, 2}}, - }, - .SVE_NOT_P = { {written={0}, read={1, 2}} }, - .SVE_MOVS_P = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_MOV_P = { - {written={0}, read={1, 2}}, - {written={0}, read={1}}, - }, - .SVE_XAR_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_CMPEQ = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPNE = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPGE = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPGT = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPHI = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPHS = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_DUP_Z = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SVE_REV_Z = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SVE_REV_P = { {written={0}, read={1}} }, - .SVE_TBL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_ZIP1_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_ZIP2_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_UZP1_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_UZP2_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_TRN1_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_TRN2_Z = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_ZIP1_P = { {written={0}, read={1, 2}} }, - .SVE_ZIP2_P = { {written={0}, read={1, 2}} }, - .SVE_UZP1_P = { {written={0}, read={1, 2}} }, - .SVE_UZP2_P = { {written={0}, read={1, 2}} }, - .SVE_TRN1_P = { {written={0}, read={1, 2}} }, - .SVE_TRN2_P = { {written={0}, read={1, 2}} }, - .SVE_LD1B = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1H = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1W = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SB = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SH = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SW = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_ST1B = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1H = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1W = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_LDFF1B = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, - .SVE_LDFF1H = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, - .SVE_LDFF1W = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, - .SVE_LDFF1D = { {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}} }, - .SVE_LDR_Z = { {written={0}, read={1}, reads_mem=true} }, - .SVE_STR_Z = { {written={}, read={0, 1}, writes_mem=true} }, - .SVE_LDR_P = { {written={0}, read={1}, reads_mem=true} }, - .SVE_STR_P = { {written={}, read={0, 1}, writes_mem=true} }, - .SVE_WHILELT = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILELE = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILELO = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILELS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILEGE = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILEGT = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILEHI = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_WHILEHS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_SQRDMLAH = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SVE_SQRDMLSH = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SVE_ADCLB = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_ADCLT = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_SBCLB = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_SBCLT = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_MATCH = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_NMATCH = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_TBL2 = { {written={0}, read={1, 2}} }, - .SVE_TBX = { {written={0}, read={0, 1, 2}} }, - .SVE_AESE = { {written={0}, read={0, 1}} }, - .SVE_AESD = { {written={0}, read={0, 1}} }, - .SVE_AESMC = { {written={0}, read={0}} }, - .SVE_AESIMC = { {written={0}, read={0}} }, - .SVE_HISTCNT = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_HISTSEG = { {written={0}, read={1, 2}} }, - .SME_SMSTART = { {written={}, read={}} }, - .SME_SMSTOP = { {written={}, read={}} }, - .SME_RDSVL = { {written={0}, read={}} }, - .SME_ZERO = { {written={}, read={}} }, - .SME_FMOPA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SME_FMOPS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SME_BFMOPA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SME_BFMOPS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SME_SMOPA = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SME_SMOPS = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SME_UMOPA = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SME_UMOPS = { - {written={0}, read={0, 1, 2, 3}}, - {written={0}, read={0, 1, 2, 3}}, - }, - .SME_USMOPA = { {written={0}, read={0, 1, 2, 3}} }, - .SME_SUMOPA = { {written={0}, read={0, 1, 2, 3}} }, - .SME_LDR_ZA = { {written={}, read={1}, reads_mem=true} }, - .SME_STR_ZA = { {written={}, read={1}, writes_mem=true} }, - .AMX_LDX = { {written={}, read={0}} }, - .AMX_LDY = { {written={}, read={0}} }, - .AMX_STX = { {written={}, read={0}} }, - .AMX_STY = { {written={}, read={0}} }, - .AMX_LDZ = { {written={}, read={0}} }, - .AMX_STZ = { {written={}, read={0}} }, - .AMX_LDZI = { {written={}, read={0}} }, - .AMX_STZI = { {written={}, read={0}} }, - .AMX_EXTRX = { {written={}, read={0}} }, - .AMX_EXTRY = { {written={}, read={0}} }, - .AMX_FMA64 = { {written={}, read={0}} }, - .AMX_FMS64 = { {written={}, read={0}} }, - .AMX_FMA32 = { {written={}, read={0}} }, - .AMX_FMS32 = { {written={}, read={0}} }, - .AMX_MAC16 = { {written={}, read={0}} }, - .AMX_FMA16 = { {written={}, read={0}} }, - .AMX_FMS16 = { {written={}, read={0}} }, - .AMX_SET = { {written={}, read={}} }, - .AMX_CLR = { {written={}, read={}} }, - .AMX_VECINT = { {written={}, read={0}} }, - .AMX_VECFP = { {written={}, read={0}} }, - .AMX_MATINT = { {written={}, read={0}} }, - .AMX_MATFP = { {written={}, read={0}} }, - .AMX_GENLUT = { {written={}, read={0}} }, - .CPYP = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .CPYM = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .CPYE = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .CPYFP = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .CPYFM = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .CPYFE = { {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true} }, - .SETP = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, - .SETM = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, - .SETE = { {written={0, 1}, read={0, 1, 2}, writes_mem=true} }, - .DC_IVAC = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, - .DC_ISW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, - .DC_CSW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, - .DC_CISW = { {written={}, read={0}, side_effects={.CACHE, .PRIVILEGED}} }, - .DC_ZVA = { {written={}, read={0}, writes_mem=true, side_effects={.CACHE}} }, - .DC_CVAC = { {written={}, read={0}, side_effects={.CACHE}} }, - .DC_CVAU = { {written={}, read={0}, side_effects={.CACHE}} }, - .DC_CIVAC = { {written={}, read={0}, side_effects={.CACHE}} }, - .IC_IALLUIS = { {written={}, read={}, side_effects={.CACHE, .PRIVILEGED}} }, - .IC_IALLU = { {written={}, read={}, side_effects={.CACHE, .PRIVILEGED}} }, - .IC_IVAU = { {written={}, read={0}, side_effects={.CACHE}} }, - .AT_S1E1R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E1W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E0R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E0W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E2R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E2W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E3R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S1E3W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S12E1R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S12E1W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S12E0R = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .AT_S12E0W = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VMALLE1IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_VAE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_ASIDE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VAAE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VALE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VAALE1IS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VMALLE1 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_VAE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_ASIDE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VAAE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VALE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_VAALE1 = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE1 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE1IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE2 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE2IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE3 = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_ALLE3IS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .PRFM = { {written={}, read={1}, side_effects={.HINT}} }, - .PRFUM = { {written={}, read={1}, side_effects={.HINT}} }, - .PRFM_LIT = { {written={}, read={}, side_effects={.HINT}} }, - .MOV_REG = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MOV_BITMASK = { - {written={0}, read={}}, - {written={0}, read={}}, - }, - .MVN = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .NEG_SR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .NEGS = { - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMP_SR = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMP_ER = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMP_IMM = { - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMN_SR = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMN_ER = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .CMN_IMM = { - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .TST_SR = { - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={}, read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_FMLA_IDX_H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_FMLA_IDX_S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_FMLA_IDX_D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_FMLS_IDX_H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_FMLS_IDX_S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_FMLS_IDX_D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_LD1B_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1B_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1H_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1H_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1W_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1W_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1D_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SB_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SB_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SH_GATHER_S = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SH_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LD1SW_GATHER_D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_ST1B_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1B_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1H_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1H_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1W_SCATTER_S = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1W_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_ST1D_SCATTER_D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_LD1B_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME_LD1H_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME_LD1W_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME_LD1D_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME_LD1Q_TILE = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME_ST1B_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_ST1H_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_ST1W_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_ST1D_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_ST1Q_TILE = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME_MOVA_Z_FROM_TILE = { {written={0}, read={1, 2}} }, - .SME_MOVA_TILE_FROM_Z = { {written={0}, read={1, 2}} }, - .SME_ADDHA = { {written={0}, read={0, 1, 2, 3}} }, - .SME_ADDVA = { {written={0}, read={0, 1, 2, 3}} }, - .FCMLA_4H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCMLA_8H = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCMLA_4S = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCMLA_2D = { {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCADD_4H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCADD_8H = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCADD_4S = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .FCADD_2D = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_PRFB = { {written={}, read={1, 2}, side_effects={.HINT}} }, - .SVE_PRFH = { {written={}, read={1, 2}, side_effects={.HINT}} }, - .SVE_PRFW = { {written={}, read={1, 2}, side_effects={.HINT}} }, - .SVE_PRFD = { {written={}, read={1, 2}, side_effects={.HINT}} }, - .SVE_LDNT1B = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LDNT1H = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LDNT1W = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_LDNT1D = { {written={0}, read={1, 2}, reads_mem=true} }, - .SVE_STNT1B = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_STNT1H = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_STNT1W = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_STNT1D = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SVE_EXT = { {written={0}, read={1, 2}} }, - .SVE_SPLICE = { {written={0}, read={1, 2, 3}} }, - .SVE_INDEX_II = { {written={0}, read={}} }, - .SVE_INDEX_IR = { {written={0}, read={2}} }, - .SVE_INDEX_RI = { {written={0}, read={1}} }, - .SVE_INDEX_RR = { {written={0}, read={1, 2}} }, - .SVE_BSL = { {written={0}, read={0, 1, 2, 3}} }, - .SVE_BSL1N = { {written={0}, read={1, 2, 3}} }, - .SVE_BSL2N = { {written={0}, read={1, 2, 3}} }, - .SVE_NBSL = { {written={0}, read={1, 2, 3}} }, - .SVE_PMUL_VEC = { {written={0}, read={1, 2}} }, - .SVE_PMULLB = { {written={0}, read={1, 2}} }, - .SVE_PMULLT = { {written={0}, read={1, 2}} }, - .SVE_BFCVT = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFCVTNT = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .LDRAA = { {written={0}, read={1}, reads_mem=true} }, - .LDRAB = { {written={0}, read={1}, reads_mem=true} }, - .LDRAA_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, - .LDRAB_PRE = { {written={0, 1}, read={1}, reads_mem=true} }, - .TSTART = { {written={0}, read={}, side_effects={.NONDETERMINISTIC}} }, - .TCOMMIT = { {written={}, read={}} }, - .TCANCEL = { {written={}, read={}, side_effects={.CONTROL}} }, - .TTEST = { {written={0}, read={}} }, - .WFET = { {written={}, read={0}, side_effects={.WAIT}} }, - .WFIT = { {written={}, read={0}, side_effects={.WAIT}} }, - .BC_COND = { {written={}, read={}, nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}} }, - .UXTB = { {written={0}, read={1}} }, - .UXTH = { {written={0}, read={1}} }, - .UXTW = { {written={0}, read={1}} }, - .SXTB = { {written={0}, read={1}} }, - .SXTH = { {written={0}, read={1}} }, - .SXTW = { {written={0}, read={1}} }, - .ADC = { - {written={0}, read={1, 2}, nzcv_rd={.C}}, - {written={0}, read={1, 2}, nzcv_rd={.C}}, - }, - .ADCS = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - }, - .SBC = { - {written={0}, read={1, 2}, nzcv_rd={.C}}, - {written={0}, read={1, 2}, nzcv_rd={.C}}, - }, - .SBCS = { - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - }, - .NGC = { - {written={0}, read={1}, nzcv_rd={.C}}, - {written={0}, read={1}, nzcv_rd={.C}}, - }, - .NGCS = { - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, - }, - .LDAPUR = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - }, - .STLUR = { - {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, - {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}}, - }, - .LDAPURB = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .STLURB = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, - .LDAPURH = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .STLURH = { {written={}, read={0, 1}, writes_mem=true, side_effects={.FENCE}} }, - .LDAPURSB = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - }, - .LDAPURSH = { - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - }, - .LDAPURSW = { {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}} }, - .SVE_BFADD = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFSUB = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFMUL = { {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFMLA = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFMLS = { {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SB = { {written={}, read={}, side_effects={.FENCE}} }, - .CSDB = { {written={}, read={}, side_effects={.FENCE}} }, - .DGH = { {written={}, read={}, side_effects={.HINT}} }, - .PSB_CSYNC = { {written={}, read={}, side_effects={.HINT}} }, - .TSB_CSYNC = { {written={}, read={}, side_effects={.HINT}} }, - .BTI_J = { {written={}, read={}, side_effects={.BTI}} }, - .BTI_C = { {written={}, read={}, side_effects={.BTI}} }, - .BTI_JC = { {written={}, read={}, side_effects={.BTI}} }, - .MOV_V_ALIAS = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .NOT_V_ALIAS = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .LSR_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .ASR_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .LSL_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .ROR_IMM = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SVE_BFADD_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFSUB_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFMUL_UNPRED = { {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true} }, - .SVE_BFCLAMP = { {written={0}, read={1, 2}} }, - .SVE_BFMAXNM = { {written={0}, read={1, 2, 3}} }, - .SVE_BFMINNM = { {written={0}, read={1, 2, 3}} }, - .SME2_LUTI2_B = { {written={0}, read={1}} }, - .SME2_LUTI4_B = { {written={0}, read={1}} }, - .SME2_LD1B_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1H_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1W_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1D_X2 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1B_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1H_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1W_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_LD1D_X4 = { {written={0}, read={1, 2}, reads_mem=true} }, - .SME2_ST1B_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1H_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1W_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1D_X2 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1B_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1H_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1W_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ST1D_X4 = { {written={}, read={0, 1, 2}, writes_mem=true} }, - .SME2_ZIP_3 = { {written={0}, read={1, 2}} }, - .SME2_ZIP_4 = { {written={0}, read={1, 2}} }, - .SME2_UZP_3 = { {written={0}, read={1, 2}} }, - .SME2_UZP_4 = { {written={0}, read={1, 2}} }, - .TLBI_RPALOS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_RPAOS = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .TLBI_PAALL = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .TLBI_PAALLOS = { {written={}, read={}, side_effects={.PRIVILEGED}} }, - .AT_S1E1A = { {written={}, read={0}, side_effects={.PRIVILEGED}} }, - .DC_CIPAPA = { {written={}, read={0}, side_effects={.CACHE}} }, - .DC_CIGDPAPA = { {written={}, read={0}, side_effects={.CACHE}} }, - .SHADD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UHADD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SHSUB = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UHSUB = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SRHADD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .URHADD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SQADD = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .UQADD = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SQSUB = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .UQSUB = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SMAX = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMAX = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMIN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMIN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SABD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UABD = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SABA = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UABA = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .MLA_V = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .MLS_V = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .CMGE = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CMHS = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .CMTST = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SQDMULH = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SQRDMULH = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .ADDP_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMAXP = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMINP = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMAXP = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMINP = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SSHL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .USHL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SRSHL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .URSHL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ZIP1 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ZIP2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UZP1 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UZP2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .TRN1 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .TRN2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ABS_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .NEG_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .NOT_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .RBIT_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV16_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV32_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .REV64 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .CLS_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .CLZ_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .CNT = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .URECPE_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .URSQRTE_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FMAX_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMIN_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMAXNM_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINNM_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMULX = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FRECPS = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FRSQRTS = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FACGE = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .FACGT = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .FCMEQ = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .FCMGE = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .FCMGT = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .FADDP_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FMAXP_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINP_V = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMAXNMP = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINNMP = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FABS_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FNEG_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FSQRT_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FRINTA_V = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTI_V = { - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - }, - .FRINTM_V = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTN_V = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTP_V = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTX_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - }, - .FRINTZ_V = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRECPE = { - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - }, - .FRSQRTE = { - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - }, - .FCVTAS_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTAU_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTMS_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTMU_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTNS_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTNU_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTPS_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTPU_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTZS_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTZU_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .SCVTF_V = { - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - }, - .UCVTF_V = { - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - }, - .SADDL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SADDL2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UADDL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UADDL2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SSUBL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SSUBL2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .USUBL = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .USUBL2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMULL_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMULL2_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMULL_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UMULL2_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SMLAL = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .SMLAL2 = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UMLAL = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UMLAL2 = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .SMLSL = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .SMLSL2 = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UMLSL = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .UMLSL2 = { - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - {written={0}, read={0, 1, 2}}, - }, - .SQDMULL = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SQDMULL2 = { - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - }, - .SQDMLAL = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SQDMLAL2 = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SQDMLSL = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SQDMLSL2 = { - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - }, - .SADDW = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SADDW2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UADDW = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .UADDW2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SSUBW = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SSUBW2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .USUBW = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .USUBW2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ADDHN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .ADDHN2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SUBHN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SUBHN2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .RADDHN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .RADDHN2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .RSUBHN = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .RSUBHN2 = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .XTN = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .XTN2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SQXTN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQXTN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQXTN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQXTN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQXTUN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQXTUN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SXTL = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SXTL2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UXTL = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UXTL2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SADDLP = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UADDLP = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SADALP = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .UADALP = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .ADDV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SMAXV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SMINV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UMAXV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UMINV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SADDLV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .UADDLV = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FMAXV_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINV_V = { - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMAXNMV = { - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FMINNMV = { - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - }, - .FCVTL = { - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FCVTL2 = { - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FCVTN = { - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FCVTN2 = { - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .FCVTXN = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, - .FCVTXN2 = { {written={0}, read={1}, fpsr_wr={.IOC, .IXC}} }, - .CMLE = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .CMLT = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .FCMLE = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FCMLT = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .SHL_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SLI = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .SQSHLU = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQSHL_V = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SSHR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .USHR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SRSHR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .URSHR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SSRA = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .USRA = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .SRSRA = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .URSRA = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .SRI = { - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - {written={0}, read={0, 1}}, - }, - .SSHLL = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SSHLL2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .USHLL = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .USHLL2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SHRN = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SHRN2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .RSHRN = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .RSHRN2 = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SQSHRN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQSHRN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQSHRN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQSHRN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQRSHRN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQRSHRN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQRSHRN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .UQRSHRN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQSHRUN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQSHRUN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQRSHRUN = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .SQRSHRUN2 = { - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - {written={0}, read={1}, fpsr_wr={.QC}}, - }, - .MOV_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MVN_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .DUP_V = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .INS = { - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - {written={0}, read={0, 2}}, - }, - .EXT_V = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .FRINTN = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTP = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTM = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTZ = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTA = { - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - }, - .FRINTX = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - }, - .FRINTI = { - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - }, - .FRECPX = { - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - {written={0}, read={1}, reads_fpcr=true}, - }, - .FCVTAS = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTAU = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTMS = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTMU = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTNS = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTNU = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTPS = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .FCVTPU = { - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - }, - .MOVI = { - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - }, - .MVNI = { - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - {written={0}, read={}}, - }, - .SVE_FRINTN = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FRINTP = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FRINTM = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FRINTZ = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FRINTA = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FRINTX = { - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - }, - .SVE_FRINTI = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - }, - .SVE_FRECPX_Z = { - {written={0}, read={1, 2}, reads_fpcr=true}, - {written={0}, read={1, 2}, reads_fpcr=true}, - {written={0}, read={1, 2}, reads_fpcr=true}, - }, - .SVE_ASRR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_LSLR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_LSRR_PRED = { - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - }, - .SVE_FSUBR_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FDIVR_PRED = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - }, - .SVE_FCMEQ = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - }, - .SVE_FCMGE = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - }, - .SVE_FCMGT = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - }, - .SVE_FCMNE = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - }, - .SVE_FCMUO = { - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - }, - .SVE_FCMLE = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_FCMLT = { - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - }, - .SVE_CMPLE = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPLO = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPLS = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_CMPLT = { - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - }, - .SVE_NANDS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_NORS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_ORNS_P = { {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_BRKPA = { {written={0}, read={1, 2, 3}} }, - .SVE_BRKPB = { {written={0}, read={1, 2, 3}} }, - .SVE_BRKA = { {written={0}, read={1, 2}} }, - .SVE_BRKB = { {written={0}, read={1, 2}} }, - .SVE_BRKAS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_BRKBS = { {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}} }, - .SVE_EOR3_Z = { {written={0}, read={1, 2, 3}} }, - .SVE_BCAX_Z = { {written={0}, read={1, 2, 3}} }, - .SVE_INSR = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .SVE_COMPACT = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - }, - .SVE_SETFFR = { {written={}, read={}, side_effects={.FFR}} }, - .SVE_RDFFR = { {written={0}, read={}, side_effects={.FFR}} }, - .SVE_WRFFR = { {written={}, read={0}, side_effects={.FFR}} }, - .SVE_BRKN = { {written={0}, read={1, 2, 3}} }, -} diff --git a/core/rexcode/isa/arm64/tablegen/encoding_table.odin b/core/rexcode/isa/arm64/tablegen/encoding_table.odin deleted file mode 100644 index da6c85b17..000000000 --- a/core/rexcode/isa/arm64/tablegen/encoding_table.odin +++ /dev/null @@ -1,4887 +0,0 @@ -// rexcode ยท Brendan Punsky (dotbmp@github), original author - -package rexcode_arm64_tablegen - -// ============================================================================= -// AArch64 ENCODING_TABLE (v1: base integer + FP scalar) -// ============================================================================= -// -// (bits, mask) model -- same shape as MIPS/RISC-V. `bits` carries the -// static opcode pattern; `mask` covers exactly the bits that are fixed -// by the form. Operand-driven fields (Rd/Rn/Rm/imm*/sh/cond/...) land in -// zero positions of `bits` and are ORed in by the encoder. -// -// Sections (each follows the ARM ARM "C4.1.x Data-processing /" division): -// ยง1 Data-processing -- immediate (Add/Sub imm, Mov-wide, PC-rel) -// ยง2 Data-processing -- shifted reg (Add/Sub/AND/ORR/EOR/BIC/ORN/EON) -// ยง3 Data-processing -- extended reg (Add/Sub extended) -// ยง4 Data-processing -- 2-source (LSLV/LSRV/ASRV/RORV, UDIV/SDIV) -// ยง5 Data-processing -- 3-source (MADD/MSUB/SMADDL/.../UMULH) -// ยง6 Data-processing -- 1-source (CLZ/CLS/RBIT/REV/REV16/REV32) -// ยง7 Conditional (CSEL/CSINC/CSINV/CSNEG) -// ยง8 Branches (B/BL/BR/BLR/RET, B.cond, CBZ, TBZ) -// ยง9 Loads / stores (LDR/STR families, LDP/STP, LDUR) -// ยง10 System (NOP/HINT/ISB/MSR/MRS/SVC/...) -// ยง11 FP scalar (FMOV/FADD/FCVT/FCMP/FCSEL/...) -// -// Logical-immediate forms (AND/ORR/EOR/ANDS imm) use the bitmask- -// immediate encoding (N:imms:immr); they're deferred to a follow-up -// turn that adds the bitmask encoder helper. -@(rodata) -ENCODING_TABLE := [Mnemonic][]Encoding{ - .INVALID = {}, - - // ========================================================================= - // ยง1 Data-processing -- immediate - // ========================================================================= - // - // ADD/SUB imm12 -- sf:op:S 10001 0 sh imm12 Rn Rd - // sh (bit 22) is operand-driven (LSL #0 or LSL #12); v1 callers - // typically pass sh=0 by passing imm <= 4095. Mask covers bits[31:23] - // (sf, op, S, "10001 0" fixed); sh, imm12, Rn, Rd are operand-driven. - - .ADD_IMM = { - {.ADD_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, - {.ADD_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, - }, - .ADDS_IMM = { - {.ADDS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, - {.ADDS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - }, - .SUB_IMM = { - {.SUB_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, - {.SUB_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, - }, - .SUBS_IMM = { - {.SUBS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, - {.SUBS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - }, - - // Move wide -- sf:opc:100101 hw imm16 Rd - // opc: 00=MOVN, 10=MOVZ, 11=MOVK - // hw (bits 22:21): 0/16/32/48 shift (only 0/16 valid in 32-bit mode) - // Mask covers bits[31:23] (sf + opc + fixed "100101") - .MOVN = { - {.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, - {.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, - }, - .MOVZ = { - {.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, - {.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, - }, - .MOVK = { - {.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, - {.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, - }, - - // PC-relative addressing -- op immlo 10000 immhi Rd - // ADR (op=0): byte target, ยฑ1MB signed - // ADRP (op=1): 4KB-page target, ยฑ4GB signed - .ADR = { {.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}} }, - .ADRP = { {.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}} }, - - // ========================================================================= - // ยง2 Data-processing -- shifted register - // ========================================================================= - // - // ADD/SUB shifted -- sf:op:S 01011 shift 0 Rm imm6 Rn Rd - // shift type at bits 23:22 (LSL/LSR/ASR/ROR), N=0 fixed at bit 21 - // Mask covers bits[31:29] + [28:24]=01011 + bit[21]=0 = 0xFF200000 - - .ADD_SR = { - {.ADD_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, - {.ADD_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, - }, - .ADDS_SR = { - {.ADDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.ADDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - }, - .SUB_SR = { - {.SUB_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, - {.SUB_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, - }, - .SUBS_SR = { - {.SUBS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.SUBS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - }, - - // Logical shifted register -- sf:opc 01010 shift N Rm imm6 Rn Rd - // opc/N pair selects: AND/BIC/ORR/ORN/EOR/EON/ANDS/BICS - .AND_SR = { - {.AND_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, - {.AND_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, - }, - .BIC_SR = { - {.BIC_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, - {.BIC_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, - }, - .ORR_SR = { - {.ORR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, - {.ORR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, - }, - .ORN_SR = { - {.ORN_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, - {.ORN_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, - }, - .EOR_SR = { - {.EOR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, - {.EOR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, - }, - .EON_SR = { - {.EON_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, - {.EON_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, - }, - .ANDS_SR = { - {.ANDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, - {.ANDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - }, - .BICS_SR = { - {.BICS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, - {.BICS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, - }, - - // ========================================================================= - // ยง3 Data-processing -- extended register - // ========================================================================= - // - // ADD/SUB extended -- sf:op:S 01011 001 Rm option imm3 Rn Rd - // bits[28:21] = 01011001 fixed; option at 15:13, imm3 at 12:10 - // Mask = bits[31:29] + bits[28:21] = 0xFFE00000 - - .ADD_ER = { - {.ADD_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, - {.ADD_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, - }, - .ADDS_ER = { - {.ADDS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, - {.ADDS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, - }, - .SUB_ER = { - {.SUB_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, - {.SUB_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, - }, - .SUBS_ER = { - {.SUBS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, - {.SUBS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, - }, - - // ========================================================================= - // ยง4 Data-processing -- 2-source (variable shift + division) - // ========================================================================= - // - // sf 0 S 11010110 Rm op2 Rn Rd - // Mask covers bits[31:21] + bits[15:10] = 0xFFE0FC00 - - .UDIV = { - {.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, - {.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .SDIV = { - {.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, - {.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .LSLV = { - {.LSLV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, - {.LSLV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .LSRV = { - {.LSRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, - {.LSRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .ASRV = { - {.ASRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, - {.ASRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .RORV = { - {.RORV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, - {.RORV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - - // ========================================================================= - // ยง5 Data-processing -- 3-source (multiply-accumulate) - // ========================================================================= - // - // sf op54 11011 op31 Rm o0 Ra Rn Rd - // Mask = bits[31:21] + bit[15] = 0xFFE08000 - - .MADD = { - {.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, - {.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, - }, - .MSUB = { - {.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, - {.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, - }, - .SMADDL = { {.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}} }, - .SMSUBL = { {.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}} }, - .UMADDL = { {.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}} }, - .UMSUBL = { {.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}} }, - // SMULH/UMULH have Ra=XZR (=11111) fixed; include in mask. - .SMULH = { {.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}} }, - .UMULH = { {.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง6 Data-processing -- 1-source (bit twiddling) - // ========================================================================= - // - // sf 1 S 11010110 op2 op Rn Rd - // Mask covers bits[31:10] = 0xFFFFFC00 - - .RBIT = { - {.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, - {.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .REV16 = { - {.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, - {.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .REV = { - // 32-bit REV (== REV32 conceptually on 32-bit registers) - {.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, - // 64-bit REV (= REV64): op=000011 - {.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .REV32 = { {.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}} }, - .CLZ = { - {.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, - {.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .CLS = { - {.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, - {.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - - // EXTR (immediate-rotate; used by ROR alias) - // sf:0:0 10011 1:N 0 Rm imms Rn Rd (N=sf) - .EXTR = { - {.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, - {.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, - }, - - // ========================================================================= - // ยง7 Conditional select - // ========================================================================= - // - // sf op S 11010100 Rm cond op2 Rn Rd - // Mask = bits[31:21] + bits[11:10] = 0xFFE00C00 - - .CSEL = { - {.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, - {.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .CSINC = { - {.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, - {.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .CSINV = { - {.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, - {.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .CSNEG = { - {.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, - {.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, - }, - - // ========================================================================= - // ยง7b Conditional compare (register form) - // ========================================================================= - // - // sf op S 11010010 Rm cond 0 o2 Rn o3 nzcv (o2 = bit11 = 0 for register) - // Mask = bits[31:21] + bits[11:10] + bit[4] = 0xFFE00C10 - // CCMP op=1 (0x7A/0xFA), CCMN op=0 (0x3A/0xBA); nzcv@3:0, cond@15:12. - // (imm5 forms, which place the immediate at bits 20:16, need a new - // Operand_Encoding and are added separately.) - - .CCMP_REG = { - {.CCMP_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, - {.CCMP_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, - }, - .CCMN_REG = { - {.CCMN_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, - {.CCMN_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, - }, - // Conditional compare (immediate): imm5 at 20:16 replaces Rm; bit 11 = 1. - .CCMP_IMM = { - {.CCMP_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, - {.CCMP_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, - }, - .CCMN_IMM = { - {.CCMN_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, - {.CCMN_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, - }, - // HINT #imm7 (imm at 11:5); NOP/YIELD/etc. are specific values of this. - .HINT = { {.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}} }, - // MSR , #imm: op1:op2 selector (combined) + CRm immediate. - .MSR_IMM = { {.MSR_IMM, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}} }, - // USDOT (unsigned-by-signed dot product, I8MM): Vd.<2S|4S>, Vn.<8B|16B>, Vm.<8B|16B>. - .USDOT = { - {.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, - {.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, - }, - // FMOV (immediate): scalar Hd/Sd/Dd, #imm (8-bit float at 20:13). - .FMOV_IMM = { - {.FMOV_IMM, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, - {.FMOV_IMM, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, - {.FMOV_IMM, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, - }, - // FMOV (vector, immediate): Vd., #imm (8-bit float in abc:defgh, cmode=1111). - .FMOV_V_IMM = { - {.FMOV_V_IMM, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, - {.FMOV_V_IMM, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, - {.FMOV_V_IMM, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, - {.FMOV_V_IMM, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, - {.FMOV_V_IMM, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, - }, - - // ========================================================================= - // Byte / half / signed scalar loads & stores (pre / post / register offset) - // and vector LDP/STP/LDUR/STUR -- reusing the standard addressing encodings. - // ========================================================================= - .LDRB_POST = { {.LDRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}} }, - .LDRB_PRE = { {.LDRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}} }, - .LDRB_REG = { {.LDRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}} }, - .LDRH_POST = { {.LDRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}} }, - .LDRH_PRE = { {.LDRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}} }, - .LDRH_REG = { {.LDRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}} }, - .STRB_POST = { {.STRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}} }, - .STRB_PRE = { {.STRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}} }, - .STRB_REG = { {.STRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}} }, - .STRH_POST = { {.STRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}} }, - .STRH_PRE = { {.STRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}} }, - .STRH_REG = { {.STRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}} }, - // Signed register-offset loads (sign-extend to W or X). - .LDRSB_REG = { - {.LDRSB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, - {.LDRSB_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .LDRSH_REG = { - {.LDRSH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, - {.LDRSH_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .LDRSW_REG = { {.LDRSW_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}} }, - // Vector load/store pair (S/D/Q) and unscaled (LDUR/STUR). - .LDP_V = { - {.LDP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, - {.LDP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, - {.LDP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, - }, - .STP_V = { - {.STP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, - {.STP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, - {.STP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, - }, - .LDUR_V = { - {.LDUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, - {.LDUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, - {.LDUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, - }, - .STUR_V = { - {.STUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, - {.STUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, - {.STUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, - }, - - // ========================================================================= - // ยง8 Branches - // ========================================================================= - - // Unconditional immediate -- op 00101 imm26 - .B = { {.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}} }, - .BL = { {.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}} }, - - // Conditional branch -- 01010100 imm19 0 cond - // Mask covers bits 31:24 + bit 4 (the lone static "0" between imm19 and - // cond). Bits 23:5 (imm19) and bits 3:0 (cond) are both operand-driven. - .B_COND = { {.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, - 0x54000000, 0xFF000010, .BASE, {cond_branch=true}} }, - - // Compare-and-branch -- sf:011010:op:imm19:Rt - .CBZ = { - {.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, - {.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, - }, - .CBNZ = { - {.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, - {.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, - }, - - // Test-bit-and-branch -- b5:011011:op:b40:imm14:Rt - .TBZ = { - {.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, - }, - .TBNZ = { - {.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, - }, - - // Register indirect -- 11010110 opc 11111 000000 Rn 00000 - // opc: 0000=BR, 0001=BLR, 0010=RET (with Rn=X30 default if absent) - .BR = { {.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}} }, - .BLR = { {.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}} }, - .RET = { - {.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, - {.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, - }, - - // ========================================================================= - // ยง9 Loads / stores (subset: unsigned-offset, unscaled, pre/post, pair, literal) - // ========================================================================= - - // Unsigned-offset (LDR/STR imm12 scaled) -- size 111 001 opc imm12 Rn Rt - // Mask = bits[31:22] = 0xFFC00000 - - .LDR = { - // Plain LDR - {.LDR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, - {.LDR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .STR = { - {.STR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, - {.STR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .LDRB = { {.LDRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}} }, - .STRB = { {.STRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}} }, - .LDRSB = { - // LDRSB Xt: opc=10 - {.LDRSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, - // LDRSB Wt: opc=11 - {.LDRSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, - }, - .LDRH = { {.LDRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}} }, - .STRH = { {.STRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}} }, - .LDRSH = { - {.LDRSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, - {.LDRSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, - }, - .LDRSW = { {.LDRSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}} }, - - // LDR literal (PC-rel 19-bit signed scaled by 4) -- opc 011 V 00 imm19 Rt - .LDR_LIT = { - {.LDR_LIT, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, - {.LDR_LIT, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, - }, - - // Load/store pair -- opc 101 V 010 L imm7 Rt2 Rn Rt - // Mask covers bits[31:22] for the offset form - .LDP = { - {.LDP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, - {.LDP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .STP = { - {.STP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, - {.STP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .LDPSW = { {.LDPSW, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง10 System - // ========================================================================= - // - // HINT space (NOP/YIELD/WFI/WFE/SEV/SEVL): 11010101 00000011 0010 CRm op2 11111 - - .NOP = { {.NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}} }, - .YIELD = { {.YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}} }, - .WFE = { {.WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}} }, - .WFI = { {.WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}} }, - .SEV = { {.SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}} }, - .SEVL = { {.SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}} }, - - // Barriers -- 11010101 00000011 0011 CRm opc 11111 - .ISB = { {.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}} }, - .DSB = { {.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}} }, - .DMB = { {.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}} }, - - // Exception generation -- 11010100 opc imm16 op2 LL - // SVC = opc=000, LL=01 -> 0xD4000001 - // HVC = opc=000, LL=10 -> 0xD4000002 - // SMC = opc=000, LL=11 -> 0xD4000003 - // BRK = opc=001, LL=00 -> 0xD4200000 - // HLT = opc=010, LL=00 -> 0xD4400000 - .SVC = { {.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}} }, - .HVC = { {.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}} }, - .SMC = { {.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}} }, - .BRK = { {.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}} }, - .HLT = { {.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}} }, - - // ERET -- 11010110 1001111 1 0000 00 11111 00000 - .ERET = { {.ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}} }, - - // System register access -- MRS Xt, sysreg = 1101010100 1 1 op0 op1 CRn CRm op2 Rt - // MSR sysreg, Xt = 1101010100 0 1 op0 op1 CRn CRm op2 Rt - // Mask covers bits[31:20] static (1101010100 1 1 for MRS) + the 5 LSBs left for Rt - .MRS = { {.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}} }, - .MSR_REG = { {.MSR_REG, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}} }, - - // ========================================================================= - // ยง11 FP scalar (single + double; half-precision deferred to FP16 turn) - // ========================================================================= - // - // OP-FP data-proc 1-source -- 0 0 0 11110 ftype 1 opcode 10000 Rn Rd - // ftype: 00=S, 01=D, 11=H (FP16, deferred) - - .FABS = { - {.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, - {.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, - }, - .FNEG = { - {.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, - {.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, - }, - .FSQRT = { - {.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, - {.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, - }, - - // OP-FP 2-source -- 0 0 0 11110 ftype 1 Rm opcode 10 Rn Rd - .FADD = { - {.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, - {.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, - }, - .FSUB = { - {.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, - {.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, - }, - .FMUL = { - {.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, - {.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, - }, - .FDIV = { - {.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, - {.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, - }, - .FNMUL = { - {.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, - {.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, - }, - .FMAX = { - {.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, - {.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, - }, - .FMIN = { - {.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, - {.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, - }, - .FMAXNM = { - {.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, - {.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, - }, - .FMINNM = { - {.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, - {.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, - }, - - // OP-FP 3-source (FMADD/FMSUB/FNMADD/FNMSUB) -- 0 0 0 11111 ftype o1 Rm o0 Ra Rn Rd - .FMADD = { - {.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, - {.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, - }, - .FMSUB = { - {.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, - {.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, - }, - .FNMADD = { - {.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, - {.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, - }, - .FNMSUB = { - {.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, - {.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, - }, - - // FP compare -- 0 0 0 11110 ftype 1 Rm 0 0 1000 Rn opc opc opc 0 0 0 - .FCMP = { - {.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, - }, - .FCMPE = { - {.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, - {.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, - }, - - // FCSEL -- 0 0 0 11110 ftype 1 Rm cond 1 1 Rn Rd - .FCSEL = { - {.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, - {.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, - }, - - // FP -> FP conversion -- 0 0 0 11110 ftype 1 0001 opc 10000 Rn Rd - // opc selects target type. We expose three common variants: - // FCVT D <- S : 0x1E22C000 (ftype=00 src=S, opc=01 dst=D) - // FCVT S <- D : 0x1E624000 (ftype=01 src=D, opc=00 dst=S) - .FCVT = { - {.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, - {.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, - }, - - // Int<->FP conversions -- sf 0 0 11110 ftype 1 rmode opc 000000 Rn Rd - // SCVTF/UCVTF: int -> FP. rmode=00, opc=010(SCVTF)/011(UCVTF) - // FCVTZS/FCVTZU: FP -> int (round toward zero). rmode=11, opc=000/001 - .SCVTF = { - {.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, - {.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, - {.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, - {.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, - }, - .UCVTF = { - {.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, - {.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, - {.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, - {.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, - }, - .FCVTZS = { - {.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, - {.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, - {.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, - }, - .FCVTZU = { - {.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, - {.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, - {.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, - }, - - // FMOV -- three flavours: reg<->reg same type, GPR<->FP, immediate - // v1 covers reg-reg + GPR<->FP (the most common). FP-immediate - // uses an 8-bit encoded constant and is deferred. - .FMOV_REG = { - {.FMOV_REG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, - {.FMOV_REG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, - }, - .FMOV_GEN = { - // W<->S, X<->D in both directions. - // FMOV Wd, Sn: sf=0 ftype=00 rmode=00 opc=110 -> 0x1E260000 - // FMOV Sd, Wn: sf=0 ftype=00 rmode=00 opc=111 -> 0x1E270000 - // FMOV Xd, Dn: sf=1 ftype=01 rmode=00 opc=110 -> 0x9E660000 - // FMOV Dd, Xn: sf=1 ftype=01 rmode=00 opc=111 -> 0x9E670000 - {.FMOV_GEN, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, - {.FMOV_GEN, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, - {.FMOV_GEN, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, - {.FMOV_GEN, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, - }, - - // ========================================================================= - // ยง12 Logical immediate (bitmask-encoded N:imms:immr) - // ========================================================================= - // sf:opc 100100 N immr imms Rn Rd - // opc: 00=AND, 01=ORR, 10=EOR, 11=ANDS - // The user passes a pre-encoded 13-bit value (N<<12 | immr<<6 | imms) - // in the IMMEDIATE; bitmask_encode() in bitmask.odin computes it - // from a raw 32/64-bit immediate. - // Mask covers sf + opc + 100100 + (for 32-bit) N=0 = 0xFF800000 / 0x7F800000. - - .AND_IMM = { - {.AND_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, - {.AND_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, - }, - .ORR_IMM = { - {.ORR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, - {.ORR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, - }, - .EOR_IMM = { - {.EOR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, - {.EOR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, - }, - .ANDS_IMM = { - {.ANDS_IMM, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, - {.ANDS_IMM, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, - }, - // TST is the ANDS_IMM alias with Rd=ZR; we emit explicit bits with Rd=31. - .TST_IMM = { - {.TST_IMM, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, - {.TST_IMM, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - }, - - // ========================================================================= - // ยง13 Additional load/store addressing modes - // ========================================================================= - // - // Unscaled signed-9 (LDUR/STUR) -- size:111 000 opc:0 imm9:9 00 Rn Rt - // Mask covers bits[31:21] + bits[11:10] = 0xFFE00C00 - - .LDUR = { - {.LDUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, - {.LDUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .STUR = { - {.STUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, - {.STUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .LDURB = { {.LDURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}} }, - .STURB = { {.STURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}} }, - .LDURH = { {.LDURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}} }, - .STURH = { {.STURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}} }, - .LDURSB = { - {.LDURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, - }, - .LDURSH = { - {.LDURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, - }, - .LDURSW = { {.LDURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}} }, - - // Pre-index (mode bits[11:10] = 11) - .LDR_PRE = { - {.LDR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, - {.LDR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .STR_PRE = { - {.STR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, - {.STR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, - }, - // Post-index (mode bits[11:10] = 01) - .LDR_POST = { - {.LDR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, - {.LDR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .STR_POST = { - {.STR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, - {.STR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, - }, - - // Register-offset load/store -- size:111 000 opc:1 Rm option S:1 10 Rn Rt - // Mask covers bits[31:21] + bits[15:10] -- option/S/index are operand - .LDR_REG = { - {.LDR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, - {.LDR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .STR_REG = { - {.STR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, - {.STR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, - }, - - // LDP/STP pre/post-index (variants of the offset form with bits[24:23] = 11/01) - .LDP_PRE = { - {.LDP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, - {.LDP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .STP_PRE = { - {.STP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, - {.STP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .LDP_POST = { - {.LDP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, - {.LDP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .STP_POST = { - {.STP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, - {.STP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .LDPSW_PRE = { {.LDPSW_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}} }, - .LDPSW_POST = { {.LDPSW_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}} }, - .LDNP = { - {.LDNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, - {.LDNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .STNP = { - {.STNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, - {.STNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, - }, - - // Exclusive (LDXR/STXR) -- size:001000 010 0 11111 0 11111 Rn Rt - .LDXR = { - {.LDXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, - {.LDXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .STXR = { - {.STXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, - {.STXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .LDAXR = { - {.LDAXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, - {.LDAXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .STLXR = { - {.STLXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, - {.STLXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .LDXRB = { {.LDXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}} }, - .STXRB = { {.STXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}} }, - .LDAXRB = { {.LDAXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}} }, - .STLXRB = { {.STLXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}} }, - .LDXRH = { {.LDXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}} }, - .STXRH = { {.STXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}} }, - .LDAXRH = { {.LDAXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}} }, - .STLXRH = { {.STLXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}} }, - - // Exclusive pair (LDXP/STXP) -- two registers - .LDXP = { - {.LDXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, - {.LDXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, - }, - .STXP = { - {.STXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, - {.STXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, - }, - .LDAXP = { - {.LDAXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, - {.LDAXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, - }, - .STLXP = { - {.STLXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, - {.STLXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, - }, - - // Acquire/Release (single register) - .LDAR = { - {.LDAR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, - {.LDAR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .STLR = { - {.STLR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, - {.STLR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, - }, - .LDARB = { {.LDARB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}} }, - .STLRB = { {.STLRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}} }, - .LDARH = { {.LDARH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}} }, - .STLRH = { {.STLRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}} }, - - // LDAPR (load-acquire RCpc, v8.3-A) - .LDAPR = { - {.LDAPR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, - {.LDAPR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, - }, - .LDAPRB = { {.LDAPRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}} }, - .LDAPRH = { {.LDAPRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}} }, - - // ========================================================================= - // ยง14 LSE atomics (v8.1-A) - // ========================================================================= - // - // Format: size:111000 A:R 1 Rs:5 o3:opc:3 00 Rn:5 Rt:5 - // size (bits 31:30): 10=W, 11=X - // A (bit 23): acquire semantics - // R (bit 22): release semantics - // opc (bits 14:12): 000=ADD, 001=CLR, 010=EOR, 011=SET, - // 100=SMAX, 101=SMIN, 110=UMAX, 111=UMIN - // o3 (bit 15): 0 for LDADD/LDCLR/LDEOR/LDSET/LD{S,U}{MAX,MIN} - // Mask covers size + 11100 + A + R + 1 + Rs(operand) + o3 + opc + 00 - // Operand-driven: A/R via flag in mask, Rs/Rn/Rt - // - // Per the ARM ARM these are encoded with bit 23 = A, bit 22 = R. - // We emit one entry per (mnemonic, width) pair; A/L embedded in bits. - - // Macro-style: each LDxxx has 4 variants (none/A/L/AL) x 2 widths (W/X) - .LDADD = { - {.LDADD, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, - {.LDADD, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDADDA = { - {.LDADDA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, - {.LDADDA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDADDL = { - {.LDADDL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, - {.LDADDL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDADDAL = { - {.LDADDAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, - {.LDADDAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDCLR = { - {.LDCLR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, - {.LDCLR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDCLRA = { - {.LDCLRA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDCLRL = { - {.LDCLRL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDCLRAL = { - {.LDCLRAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, - {.LDCLRAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDEOR = { - {.LDEOR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, - {.LDEOR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDEORA = { - {.LDEORA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, - {.LDEORA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDEORL = { - {.LDEORL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, - {.LDEORL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDEORAL = { - {.LDEORAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, - {.LDEORAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSET = { - {.LDSET, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, - {.LDSET, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSETA = { - {.LDSETA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, - {.LDSETA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSETL = { - {.LDSETL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, - {.LDSETL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSETAL = { - {.LDSETAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, - {.LDSETAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMAX = { - {.LDSMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMAXA = { - {.LDSMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMAXL = { - {.LDSMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMAXAL = { - {.LDSMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, - {.LDSMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMIN = { - {.LDSMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, - {.LDSMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMINA = { - {.LDSMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMINL = { - {.LDSMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDSMINAL = { - {.LDSMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, - {.LDSMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMAX = { - {.LDUMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMAXA = { - {.LDUMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMAXL = { - {.LDUMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMAXAL = { - {.LDUMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, - {.LDUMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMIN = { - {.LDUMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, - {.LDUMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMINA = { - {.LDUMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMINL = { - {.LDUMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .LDUMINAL = { - {.LDUMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, - {.LDUMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - - // SWP (swap) -- opc=1000 - .SWP = { - {.SWP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, - {.SWP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .SWPA = { - {.SWPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, - {.SWPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .SWPL = { - {.SWPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, - {.SWPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .SWPAL = { - {.SWPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, - {.SWPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - - // CAS (compare-and-swap) -- size:1000100 A:1 1 Rs:5 R 11111 Rn Rt - .CAS = { - {.CAS, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, - {.CAS, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASA = { - {.CASA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, - {.CASA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASL = { - {.CASL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASAL = { - {.CASAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, - {.CASAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASB = { {.CASB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}} }, - .CASAB = { {.CASAB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}} }, - .CASLB = { {.CASLB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}} }, - .CASALB = { {.CASALB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}} }, - .CASH = { {.CASH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}} }, - .CASAH = { {.CASAH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}} }, - .CASLH = { {.CASLH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}} }, - .CASALH = { {.CASALH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}} }, - - // CASP (compare-and-swap pair) -- Rs, Rs+1 with Rt, Rt+1 - .CASP = { - {.CASP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, - {.CASP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASPA = { - {.CASPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, - {.CASPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASPL = { - {.CASPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, - {.CASPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - .CASPAL = { - {.CASPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, - {.CASPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, - }, - - // ========================================================================= - // ยง15 CRC32 (v8.0-A optional, mandatory v8.1+) - // ========================================================================= - // sf 0 0 11010110 Rm 0100 sz Rn Rd (CRC32; sz=00 byte / 01 half / 10 word / 11 dword) - // CRC32C: bit 12 = 1 - // Mask = bits[31:21] + bits[15:10] = 0xFFE0FC00 - - .CRC32B = { {.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}} }, - .CRC32H = { {.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}} }, - .CRC32W = { {.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}} }, - .CRC32X = { {.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}} }, - .CRC32CB = { {.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}} }, - .CRC32CH = { {.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}} }, - .CRC32CW = { {.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}} }, - .CRC32CX = { {.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}} }, - - // ========================================================================= - // ยง16 Crypto (AES / SHA1 / SHA256 / SHA512 / SHA3 / SM3 / SM4 / PMULL) - // ========================================================================= - // - // AES: 0 1 0 01110 0 0 10100 op 10 Vn Vd (V regs treated as 16B) - .AESE = { {.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}} }, - .AESD = { {.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}} }, - .AESMC = { {.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}} }, - .AESIMC = { {.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}} }, - - // SHA1: 0 1 0 11110 0 0 10100 ... 10 Vn Vd - .SHA1H = { {.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}} }, - .SHA1SU1 = { {.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}} }, - .SHA1C = { {.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA1P = { {.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA1M = { {.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA1SU0 = { {.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}} }, - - // SHA256 - .SHA256H = { {.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA256H2 = { {.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA256SU0 = { {.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}} }, - .SHA256SU1 = { {.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}} }, - - // SHA512 (v8.2-A) - .SHA512H = { {.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA512H2 = { {.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}} }, - .SHA512SU0 = { {.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}} }, - .SHA512SU1 = { {.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}} }, - - // SHA3 (v8.2-A) - .EOR3 = { {.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}} }, - .BCAX = { {.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}} }, - .RAX1 = { {.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}} }, - .XAR = { {.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}} }, - - // SM3 / SM4 - .SM3PARTW1 = { {.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}} }, - .SM3PARTW2 = { {.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}} }, - .SM3SS1 = { {.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}} }, - .SM3TT1A = { {.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}} }, - .SM3TT1B = { {.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}} }, - .SM3TT2A = { {.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}} }, - .SM3TT2B = { {.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}} }, - .SM4E = { {.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}} }, - .SM4EKEY = { {.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}} }, - - // PMULL / PMULL2 (polynomial multiply long; AES/GHASH) - .PMULL = { - {.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, - }, - .PMULL2 = { - {.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, - {.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, - }, - - // ========================================================================= - // ยง17 Pointer Authentication (PAC v8.3-A) - // ========================================================================= - // PAC* / AUT* / XPAC* live in data-processing 1-source (op0=x110). - // The "Z" forms use Rn=XZR (encoded as register 31). - - .PACIA = { {.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}} }, - .PACIB = { {.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}} }, - .PACDA = { {.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}} }, - .PACDB = { {.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}} }, - .AUTIA = { {.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}} }, - .AUTIB = { {.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}} }, - .AUTDA = { {.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}} }, - .AUTDB = { {.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}} }, - - .PACIZA = { {.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .PACIZB = { {.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .PACDZA = { {.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .PACDZB = { {.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .AUTIZA = { {.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .AUTIZB = { {.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .AUTDZA = { {.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .AUTDZB = { {.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - - .XPACI = { {.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .XPACD = { {.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}} }, - .XPACLRI = { {.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}} }, - - // PAC SP-variant hints - .PACIASP = { {.PACIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}} }, - .PACIBSP = { {.PACIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}} }, - .AUTIASP = { {.AUTIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}} }, - .AUTIBSP = { {.AUTIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}} }, - - // PAC* / AUT* / RET* with key A or B and X16/X17 - .PACIA1716 = { {.PACIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}} }, - .PACIB1716 = { {.PACIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}} }, - .AUTIA1716 = { {.AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}} }, - .AUTIB1716 = { {.AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}} }, - - .PACGA = { {.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}} }, - - .RETAA = { {.RETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}} }, - .RETAB = { {.RETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}} }, - - .BRAA = { {.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}} }, - .BRAB = { {.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}} }, - .BLRAA = { {.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}} }, - .BLRAB = { {.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}} }, - .BRAAZ = { {.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}} }, - .BRABZ = { {.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}} }, - .BLRAAZ = { {.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}} }, - .BLRABZ = { {.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}} }, - .ERETAA = { {.ERETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}} }, - .ERETAB = { {.ERETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}} }, - - // ========================================================================= - // ยง18 Branch Target Identification (BTI v8.5-A) - // ========================================================================= - // HINT space; opc selects {nop|c|j|jc} via CRm:op2 = 0100:000/010/100/110 - .BTI = { {.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}} }, - - // ========================================================================= - // ยง19 Memory Tagging Extension (MTE v8.5-A) - // ========================================================================= - // - // ADDG/SUBG: sf=1 op:1 0 100011 0 uimm6 op3:2 uimm4 Rn Rd - .ADDG = { {.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}} }, - .SUBG = { {.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}} }, - - // IRG: 10011010110 Rm 000100 Rn Rd - .IRG = { {.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}} }, - .GMI = { {.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}} }, - .SUBP = { {.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}} }, - .SUBPS = { {.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}} }, - - // Tagged load/store (encoded in the load-store offset/pre/post space) - // STG Xt, [Xn|SP], #imm -- 1101100100 ... opc=10 ... bits[31:24] = 11011001 etc. - .STG = { {.STG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}} }, - .STZG = { {.STZG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}} }, - .ST2G = { {.ST2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}} }, - .STZ2G = { {.STZ2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}} }, - .LDG = { {.LDG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}} }, - .STGM = { {.STGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}} }, - .LDGM = { {.LDGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}} }, - .STZGM = { {.STZGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}} }, - .STGP = { {.STGP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}} }, - - // ========================================================================= - // ยง20 FP scalar half-precision (FP16, v8.2-A) - // ========================================================================= - // Mirror of FP single/double but with ftype=11 (bits[23:22]=11). - .FABS_H = { {.FABS_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}} }, - .FNEG_H = { {.FNEG_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}} }, - .FSQRT_H = { {.FSQRT_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}} }, - .FADD_H = { {.FADD_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}} }, - .FSUB_H = { {.FSUB_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}} }, - .FMUL_H = { {.FMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}} }, - .FDIV_H = { {.FDIV_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}} }, - .FNMUL_H = { {.FNMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}} }, - .FMAX_H = { {.FMAX_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}} }, - .FMIN_H = { {.FMIN_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}} }, - .FMAXNM_H = { {.FMAXNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}} }, - .FMINNM_H = { {.FMINNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}} }, - .FCMP_H = { {.FCMP_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}} }, - .FCMPE_H = { {.FCMPE_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}} }, - .FCSEL_H = { {.FCSEL_H, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}} }, - .FMADD_H = { {.FMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}} }, - .FMSUB_H = { {.FMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}} }, - .FNMADD_H = { {.FNMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}} }, - .FNMSUB_H = { {.FNMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}} }, - .FCVT_H_S = { {.FCVT_H_S, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}} }, - .FCVT_H_D = { {.FCVT_H_D, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}} }, - .FCVT_S_H = { {.FCVT_S_H, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}} }, - .FCVT_D_H = { {.FCVT_D_H, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}} }, - .SCVTF_H = { {.SCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}} }, - .UCVTF_H = { {.UCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}} }, - .FCVTZS_H = { {.FCVTZS_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}} }, - .FCVTZU_H = { {.FCVTZU_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}} }, - .FMOV_H = { {.FMOV_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}} }, - - // ========================================================================= - // ยง21 BFloat16 (BF16, v8.6-A) - // ========================================================================= - .BFCVT = { {.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}} }, - .BFCVTN = { {.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}} }, - .BFCVTN2 = { {.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}} }, - .BFDOT = { {.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}} }, - .BFMMLA = { {.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}} }, - .BFMLALB = { {.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}} }, - .BFMLALT = { {.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}} }, - - // ========================================================================= - // ยง22 NEON Advanced SIMD (3-same arithmetic + compare + logical + shift) - // ========================================================================= - // - // Format: 0Q U 01110 size:2 1 Rm opcode:5 1 Rn Rd - // Q (bit 30): 0=64-bit / 1=128-bit vector - // U (bit 29): selects signed/unsigned or alternate op - // size (bits 23:22): element-size 00=B 01=H 10=S 11=D - // bits[28:24] = 01110, bit 21 = 1, bit 10 = 1 - // opcode at bits 15:11 - // - // Per-arrangement entries: each vector mnemonic has up to 7 forms - // (8B/16B/4H/8H/2S/4S/2D; 1D is reserved for most). For brevity we - // list the densely-used arrangements (16B/8H/4S/2D) on the 128-bit - // path and 8B/4H/2S on the 64-bit path. Some ops (like FADD) only - // accept FP arrangements (4S/2S/2D + 8H if FP16). - - .ADD_V = { - {.ADD_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, - {.ADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, - }, - .SUB_V = { - {.SUB_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, - {.SUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, - }, - .MUL_V = { - // opcode = 10011 -> 0x4E209C00 for 16B - {.MUL_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, - {.MUL_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, - {.MUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, - }, - - // Vector compares - .CMEQ = { - {.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, - {.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, - }, - .CMGT = { - {.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, - {.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, - }, - .CMHI = { - {.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, - {.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, - }, - - // Logical (vector) - .AND_V = { {.AND_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}} }, - .ORR_V = { {.ORR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}} }, - .EOR_V = { {.EOR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}} }, - .BIC_V = { {.BIC_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}} }, - .ORN_V = { {.ORN_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}} }, - - // Bit insert/select (BIT/BIF/BSL): U=1 - .BIT = { {.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}} }, - .BIF = { {.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}} }, - .BSL = { {.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}} }, - - // FP vector arithmetic (3-same FP encoding) - .FADD_V = { - {.FADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, - }, - .FSUB_V = { - {.FSUB_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, - {.FSUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, - {.FSUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, - }, - .FMUL_V = { - {.FMUL_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMUL_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, - }, - .FDIV_V = { - {.FDIV_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FDIV_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FDIV_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, - }, - .FMLA_V = { - {.FMLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, - {.FMLA_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, - }, - .FMLS_V = { - {.FMLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, - {.FMLS_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, - }, - - // Dot product (SDOT/UDOT - v8.2-A optional, mandatory v8.4) - .SDOT = { - {.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, - {.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, - }, - .UDOT = { - {.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, - {.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, - }, - - // NEON load/store: LD1/ST1 multiple structures (the simplest form) - // Single register, 1 vector: 0Q 001100 010 00000 0111 size Rn Rt - // Layout details vary by # registers and replicate vs. lane vs. multiple. - // v1 covers the common LD1/ST1 to one vector (1 reg, contiguous). - .LD1 = { - {.LD1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, - {.LD1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, - {.LD1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, - {.LD1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, - }, - .ST1 = { - {.ST1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, - {.ST1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, - {.ST1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, - {.ST1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, - }, - - // Table lookup (TBL/TBX): the table operand is a register list whose first - // register is encoded at Vn; the list length (here 1) is fixed in the bits. - .TBL = { - {.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, - {.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, - }, - .TBX = { - {.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, - {.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, - }, - // Structured load/store of 2/3/4 registers, and load-and-replicate (LD#R). - // The register list is encoded by its first register (Vd); the count and - // arrangement (here .16b) are fixed in the bits (mirrors the LD1/ST1 forms). - .LD2 = { {.LD2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}} }, - .LD3 = { {.LD3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}} }, - .LD4 = { {.LD4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}} }, - .ST2 = { {.ST2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}} }, - .ST3 = { {.ST3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}} }, - .ST4 = { {.ST4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}} }, - .LD1R = { {.LD1R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}} }, - .LD2R = { {.LD2R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}} }, - .LD3R = { {.LD3R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}} }, - .LD4R = { {.LD4R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}} }, - - // Single-structure (one lane) load/store: LD#_LANE / ST#_LANE. The lane - // index is split across Q (30), S (12) and size (11:10) per element size; - // the list length + load/store bit are fixed in the bits. - .LD1_LANE = { - {.LD1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, - {.LD1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, - {.LD1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, - {.LD1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, - }, - .LD2_LANE = { - {.LD2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, - {.LD2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, - {.LD2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, - {.LD2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, - }, - .LD3_LANE = { - {.LD3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, - {.LD3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, - {.LD3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, - {.LD3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, - }, - .LD4_LANE = { - {.LD4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, - {.LD4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, - {.LD4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, - {.LD4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, - }, - .ST1_LANE = { - {.ST1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, - {.ST1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, - {.ST1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, - {.ST1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, - }, - .ST2_LANE = { - {.ST2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, - {.ST2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, - {.ST2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, - {.ST2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, - }, - .ST3_LANE = { - {.ST3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, - {.ST3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, - {.ST3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, - {.ST3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, - }, - .ST4_LANE = { - {.ST4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, - {.ST4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, - {.ST4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, - {.ST4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, - }, - - // FP/SIMD scalar load/store via V regs (offset-form) - .LDR_V = { - {.LDR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, - {.LDR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, - }, - .STR_V = { - {.STR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, - {.STR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, - }, - - // ========================================================================= - // ยง23 SVE / SVE2 (real coverage) - // ========================================================================= - // - // All SVE instructions live in op0 bucket 0b0010 (bits[28:25]) -- they - // start with byte 0x04 / 0x05 / 0x24 / 0x25 / 0x44 / 0x45 / 0x64 / 0x65 - // (and the load/store family at 0x84 / 0x85 / 0xA4 / 0xA5 / 0xC4 / 0xC5 - // / 0xE4 / 0xE5). All are 4 bytes. - // - // Element size: when an instruction has 4 forms (B/H/S/D), the size - // bits[23:22] differ -- 00/01/10/11. - // - // ------------------------------------------------------------------------- - // ยง23.1 Integer arithmetic, vectors unpredicated - // ------------------------------------------------------------------------- - // ADD/SUB/SQADD/UQADD/SQSUB/UQSUB Zd.T, Zn.T, Zm.T - // 00000100 SS 1 Zm 0000 oo Zn Zd (oo selects op) - - .SVE_ADD_Z = { - {.SVE_ADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_SUB_Z = { - {.SVE_SUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, - {.SVE_SUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_SQADD_Z = { - {.SVE_SQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_UQADD_Z = { - {.SVE_UQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_SQSUB_Z = { - {.SVE_SQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, - {.SVE_SQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_UQSUB_Z = { - {.SVE_UQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.2 Integer arithmetic, predicated (destructive merging) - // ------------------------------------------------------------------------- - // ADD Zdn.T, Pg/M, Zdn.T, Zm.T - // 00000100 SS 000 opc 001 Pg Zm Zdn (opc selects op) - // Operand 1 (Pg) is governing predicate at bits 12:10 (P0..P7). - - .SVE_ADD_PRED = { - {.SVE_ADD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, - {.SVE_ADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, - {.SVE_ADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, - {.SVE_ADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SUB_PRED = { - {.SVE_SUB_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SUBR_PRED = { - {.SVE_SUBR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, - {.SVE_SUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_MUL_PRED = { - {.SVE_MUL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, - {.SVE_MUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SMULH_PRED = { - {.SVE_SMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_UMULH_PRED = { - {.SVE_UMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SDIV_PRED = { - {.SVE_SDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, - {.SVE_SDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_UDIV_PRED = { - {.SVE_UDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, - {.SVE_UDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SMAX_PRED = { - {.SVE_SMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_UMAX_PRED = { - {.SVE_UMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SMIN_PRED = { - {.SVE_SMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_UMIN_PRED = { - {.SVE_UMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_SABD_PRED = { - {.SVE_SABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, - {.SVE_SABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_UABD_PRED = { - {.SVE_UABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, - {.SVE_UABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.3 Bitwise predicated (AND/ORR/EOR/BIC Zdn.D, Pg/M, Zdn.D, Zm.D) - // 00000100 011 opc 001 Pg Zm Zdn (size always 11 = D for the - // element-agnostic logical forms) - // ------------------------------------------------------------------------- - .SVE_AND_PRED = { {.SVE_AND_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}} }, - .SVE_ORR_PRED = { {.SVE_ORR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}} }, - .SVE_EOR_PRED = { {.SVE_EOR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}} }, - .SVE_BIC_PRED = { {.SVE_BIC_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}} }, - - // ------------------------------------------------------------------------- - // ยง23.4 Shifts predicated (ASR/LSR/LSL Zdn, Pg/M, Zdn, Zm) - // 00000100 SS 010 opc 100 Pg Zm Zdn - // ------------------------------------------------------------------------- - .SVE_ASR_PRED = { - {.SVE_ASR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, - {.SVE_ASR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_LSR_PRED = { - {.SVE_LSR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_LSL_PRED = { - {.SVE_LSL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, - {.SVE_LSL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.5 Unary integer predicated - // ABS / NEG / CLS / CLZ / CNT / NOT Zd.T, Pg/M, Zn.T - // 00000100 SS 010 opc 101 Pg Zn Zd - // ------------------------------------------------------------------------- - .SVE_ABS_PRED = { - {.SVE_ABS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, - {.SVE_ABS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_NEG_PRED = { - {.SVE_NEG_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, - {.SVE_NEG_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, - {.SVE_NEG_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, - {.SVE_NEG_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_CLS_PRED = { - {.SVE_CLS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_CLZ_PRED = { - {.SVE_CLZ_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLZ_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLZ_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, - {.SVE_CLZ_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_CNT_PRED = { - {.SVE_CNT_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, - {.SVE_CNT_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.6 FP arithmetic vectors unpredicated (FADD/FSUB/FMUL Zd, Zn, Zm) - // 01100101 SS 0 Zm 000 opc Zn Zd - // ------------------------------------------------------------------------- - .SVE_FADD_Z = { - {.SVE_FADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, - {.SVE_FADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, - {.SVE_FADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FSUB_Z = { - {.SVE_FSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, - {.SVE_FSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, - {.SVE_FSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FMUL_Z = { - {.SVE_FMUL_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMUL_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FMUL_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FRECPS = { - {.SVE_FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FRSQRTS = { - {.SVE_FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FTSMUL = { - {.SVE_FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.7 FP arithmetic predicated (FADD/FSUB/FMUL Zdn, Pg/M, Zdn, Zm) - // 01100101 SS 0 opc 100 Pg Zm Zdn - // ------------------------------------------------------------------------- - .SVE_FADD_PRED = { - {.SVE_FADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, - {.SVE_FADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, - {.SVE_FADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FSUB_PRED = { - {.SVE_FSUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMUL_PRED = { - {.SVE_FMUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FDIV_PRED = { - {.SVE_FDIV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, - {.SVE_FDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, - {.SVE_FDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMAX_PRED = { - {.SVE_FMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMIN_PRED = { - {.SVE_FMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMAXNM_PRED = { - {.SVE_FMAXNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAXNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMAXNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMINNM_PRED = { - {.SVE_FMINNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMINNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMINNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // FP unary predicated (FABS/FNEG/FSQRT Zd, Pg/M, Zn) - .SVE_FABS_Z = { - {.SVE_FABS_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FABS_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FABS_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FNEG_Z = { - {.SVE_FNEG_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNEG_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNEG_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FSQRT_Z = { - {.SVE_FSQRT_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSQRT_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, - {.SVE_FSQRT_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.8 FP fused multiply-accumulate (predicated) - // FMLA Zda, Pg/M, Zn, Zm - // 01100101 SS 1 Zm 000 Pg Zn Zda (FMLA) - // 01100101 SS 1 Zm 001 Pg Zn Zda (FMLS) - // 01100101 SS 1 Zm 010 Pg Zn Zda (FNMLA) - // 01100101 SS 1 Zm 011 Pg Zn Zda (FNMLS) - // ------------------------------------------------------------------------- - .SVE_FMLA = { - {.SVE_FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FMLS = { - {.SVE_FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, - {.SVE_FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FNMLA = { - {.SVE_FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_FNMLS = { - {.SVE_FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, - {.SVE_FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.9 Predicate logical operations (Pd.B, Pg/Z, Pn.B, Pm.B) - // 00100101 SS 0 Pm o1 Pg o2 Pn O Pd (SS=00 typically; opc differentiates) - // AND/BIC/ORR/EOR + NAND/NOR/ORN/SEL, with optional S setting flags - // ------------------------------------------------------------------------- - .SVE_AND_P = { {.SVE_AND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}} }, - .SVE_BIC_P = { {.SVE_BIC_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}} }, - .SVE_ORR_P = { {.SVE_ORR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}} }, - .SVE_ORN_P = { {.SVE_ORN_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}} }, - .SVE_EOR_P = { {.SVE_EOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}} }, - .SVE_NAND_P = { {.SVE_NAND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}} }, - .SVE_NOR_P = { {.SVE_NOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}} }, - .SVE_SEL_P = { {.SVE_SEL_P, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}} }, - - // Flag-setting variants - .SVE_ANDS_P = { {.SVE_ANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}} }, - .SVE_BICS_P = { {.SVE_BICS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}} }, - .SVE_ORRS_P = { {.SVE_ORRS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}} }, - .SVE_EORS_P = { {.SVE_EORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}} }, - - // ------------------------------------------------------------------------- - // ยง23.10 PTRUE/PFALSE/PFIRST/PNEXT - // ------------------------------------------------------------------------- - // PTRUE Pd.T, pattern = 00100101 SS 011000 1110 0 pattern 0 Pd - // PFALSE Pd.B = 00100101 0001 1000 1110 0100 0000 Pd - // PFIRST Pdn.B, Pg, Pdn.B = 00100101 0101 1000 1100 000 Pg Pdn - // PNEXT Pdn.T, Pg, Pdn.T = 00100101 SS 011001 1100 010 Pg 0000 Pdn - .SVE_PTRUE = { - {.SVE_PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, - }, - .SVE_PTRUES = { - {.SVE_PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, - }, - .SVE_PFALSE = { - {.SVE_PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, - }, - .SVE_PFIRST = { - {.SVE_PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, - }, - .SVE_PNEXT = { - {.SVE_PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, - }, - - // ------------------------------------------------------------------------- - // SVE alias / copy / permute stragglers (duplicated-field encodings). - // ------------------------------------------------------------------------- - // CPY (predicated, from general register): Zd.T, Pg/m, Wn/Xn. - .SVE_CPY_Z = { - {.SVE_CPY_Z, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, - {.SVE_CPY_Z, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, - {.SVE_CPY_Z, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, - {.SVE_CPY_Z, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - // EXT (destructive vector extract): Zdn.B, Zdn.B, Zm.B, #imm (imm8 split). - .SVE_EXT_Z = { {.SVE_EXT_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}} }, - // MOV (predicated, = SEL Zd, Pg, Zn, Zd): Zd.T, Pg/m, Zn.T. - .SVE_MOV_PRED = { - {.SVE_MOV_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, - {.SVE_MOV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, - {.SVE_MOV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, - {.SVE_MOV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - // Predicate aliases (EOR/ORR/AND with a duplicated predicate field). - .SVE_NOT_P = { {.SVE_NOT_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}} }, - .SVE_MOVS_P = { {.SVE_MOVS_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}} }, - .SVE_MOV_P = { - {.SVE_MOV_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, - {.SVE_MOV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, - }, - // SVE2 XAR (destructive): Zdn.T, Zdn.T, Zm.T, #rotate. The rotate amount is - // V = 2*esize - amount, split tszh:tszl:imm3; esize selected by the Z type. - .SVE_XAR_Z = { - {.SVE_XAR_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, - {.SVE_XAR_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, - {.SVE_XAR_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, - {.SVE_XAR_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.11 Integer compare (Zn vs Zm) -> Pd.T - // CMPEQ Pd.T, Pg/Z, Zn.T, Zm.T = 00100100 SS 1 Zm 101 Pg Zn O Pd - // opc bits at 15:13 distinguish HI/HS/EQ/NE/GE/GT/LE/LT - // ------------------------------------------------------------------------- - .SVE_CMPEQ = { - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, - {.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPNE = { - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPGE = { - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPGT = { - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPHI = { - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPHS = { - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.12 SVE DUP / INSR / REV / TBL - // ------------------------------------------------------------------------- - // DUP Zd.T, Zn.T[imm] = 00000101 SS 1 imm 001000 Zn Zd (broadcast lane) - // INSR Zd.T, Rn = 00000101 SS 1 00100 001110 Rn Zd - // REV Pd.T, Pn.T = 00000101 SS 11 0100 010 0000 Pn Pd - // REV Zd.T, Zn.T = 00000101 SS 11 1000 001110 Zn Zd - .SVE_DUP_Z = { - // Broadcast a GPR (DUP Zd.B, Wn): 00000101 SS 1 00 000 001110 Rn Zd - {.SVE_DUP_Z, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, - {.SVE_DUP_Z, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, - {.SVE_DUP_Z, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, - {.SVE_DUP_Z, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, - }, - .SVE_REV_Z = { - {.SVE_REV_Z, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, - {.SVE_REV_Z, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, - }, - .SVE_REV_P = { - {.SVE_REV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, - }, - .SVE_TBL = { - {.SVE_TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.13 Permute (ZIP1/2, UZP1/2, TRN1/2) for Z and P registers - // 00000101 SS 1 Zm 011 oo o Zn Zd (Z variants; oo=00 ZIP1, 01 ZIP2, etc.) - // 00000101 SS 1 0 Pm 010 oo o Pn 0 Pd (P variants) - // ------------------------------------------------------------------------- - .SVE_ZIP1_Z = { - {.SVE_ZIP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_ZIP2_Z = { - {.SVE_ZIP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, - {.SVE_ZIP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_UZP1_Z = { - {.SVE_UZP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_UZP2_Z = { - {.SVE_UZP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, - {.SVE_UZP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_TRN1_Z = { - {.SVE_TRN1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_TRN2_Z = { - {.SVE_TRN2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, - {.SVE_TRN2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - - // P-register permutes - .SVE_ZIP1_P = { {.SVE_ZIP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}} }, - .SVE_ZIP2_P = { {.SVE_ZIP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}} }, - .SVE_UZP1_P = { {.SVE_UZP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}} }, - .SVE_UZP2_P = { {.SVE_UZP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}} }, - .SVE_TRN1_P = { {.SVE_TRN1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}} }, - .SVE_TRN2_P = { {.SVE_TRN2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}} }, - - // ------------------------------------------------------------------------- - // ยง23.14 Contiguous load/store (scalar+scalar) - // LD1B { Zt.T }, Pg/Z, [Xn, Xm] - // 1010010 0 SS 0 Xm 010 Pg Xn Zt (size: B=00, H=01, W=10, D=11) - // ST1B { Zt.T }, Pg, [Xn, Xm] - // 1110010 0 SS 0 Xm 010 Pg Xn Zt - // ------------------------------------------------------------------------- - .SVE_LD1B = { - {.SVE_LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LD1H = { - {.SVE_LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LD1W = { - {.SVE_LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LD1D = { - {.SVE_LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1SB = { - {.SVE_LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LD1SH = { - {.SVE_LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LD1SW = { - {.SVE_LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - .SVE_ST1B = { - {.SVE_ST1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_ST1H = { - {.SVE_ST1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_ST1W = { - {.SVE_ST1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_ST1D = { - {.SVE_ST1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // First-faulting (LDFF1*) variants -- same family, bit 23/22 chooses non-fault. - // Spec uses bits[14:13] = 11 instead of 10 to mark FF; we encode them - // explicitly so the mnemonic distinguishes the faulting behavior. - .SVE_LDFF1B = { - {.SVE_LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LDFF1H = { - {.SVE_LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LDFF1W = { - {.SVE_LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, - }, - .SVE_LDFF1D = { - {.SVE_LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, - }, - - // Unpredicated LDR/STR of full Z/P registers (scalar+imm with MUL VL). - // LDR Zt, [Xn{, #imm, MUL VL}] = 10000101 10 imm9 010 Xn Zt - // STR Zt, [Xn{, #imm, MUL VL}] = 11100101 10 imm9 010 Xn Zt - // LDR Pt, [Xn{, #imm, MUL VL}] = 10000101 10 imm9 000 Xn 0 Pt - .SVE_LDR_Z = { {.SVE_LDR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}} }, - .SVE_STR_Z = { {.SVE_STR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}} }, - .SVE_LDR_P = { {.SVE_LDR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}} }, - .SVE_STR_P = { {.SVE_STR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}} }, - - // ------------------------------------------------------------------------- - // ยง23.15 SVE2 -- WHILE family (Pd, Xn, Xm) - // WHILELT Pd.T, Wn, Wm = 00100101 SS 1 Rm 0 0 0 1 0 0 Rn 0 0000 Pd - // We encode the X variant (sf=1, bit 12 in original spec) for 64-bit. - // ------------------------------------------------------------------------- - .SVE_WHILELT = { - {.SVE_WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILELE = { - {.SVE_WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILELO = { - {.SVE_WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILELS = { - {.SVE_WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILEGE = { - {.SVE_WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILEGT = { - {.SVE_WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILEHI = { - {.SVE_WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - .SVE_WHILEHS = { - {.SVE_WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, - }, - - // ------------------------------------------------------------------------- - // ยง23.16 SVE2 saturating rounding multiply-accumulate - // SQRDMLAH Zda.T, Zn.T, Zm.T = 01000100 SS 0 Zm 0111 00 Zn Zda - // SQRDMLSH Zda.T, Zn.T, Zm.T = 01000100 SS 0 Zm 0111 01 Zn Zda - // ------------------------------------------------------------------------- - .SVE_SQRDMLAH = { - {.SVE_SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - .SVE_SQRDMLSH = { - {.SVE_SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - - // SVE2 Add/sub with carry (long), AESE/AESD/AESMC/AESIMC SVE2 forms - .SVE_ADCLB = { - {.SVE_ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - .SVE_ADCLT = { - {.SVE_ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - .SVE_SBCLB = { - {.SVE_SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - .SVE_SBCLT = { - {.SVE_SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, - {.SVE_SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, - }, - - .SVE_MATCH = { - {.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, - }, - .SVE_NMATCH = { - {.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, - {.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, - }, - - .SVE_TBL2 = { - {.SVE_TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, - }, - .SVE_TBX = { - {.SVE_TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, - }, - - // SVE2 AES/SM4 (Z-form encryption) - .SVE_AESE = { {.SVE_AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}} }, - .SVE_AESD = { {.SVE_AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}} }, - .SVE_AESMC = { {.SVE_AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}} }, - .SVE_AESIMC = { {.SVE_AESIMC,{.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}} }, - - .SVE_HISTCNT = { - {.SVE_HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, - {.SVE_HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, - }, - .SVE_HISTSEG = { - {.SVE_HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, - }, - - // ------------------------------------------------------------------------- - // ยง24 SME (Scalable Matrix Extension) - // ------------------------------------------------------------------------- - // SMSTART / SMSTOP control PSTATE.SM and PSTATE.ZA. - // SMSTART = D503447F (default = both SM + ZA on) - // SMSTOP = D503467F - // - // These are hint-encoded as MSR (immediate) writes to SVCR. - - .SME_SMSTART = { {.SME_SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}} }, - .SME_SMSTOP = { {.SME_SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}} }, - - // RDSVL Xd, #imm6 -- read streaming-mode vector length (in bytes) * imm6. - // 00000100 10111111 010101 imm6 Xd - .SME_RDSVL = { - {.SME_RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, - }, - - // ZERO {} -- zero a list of ZA tiles using the 8-bit list as 4-bit field. - // 11000000 00000011 00 0 imm4 11 0000 00000 - .SME_ZERO = { - {.SME_ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, - }, - - // FMOPA ZAd.S, Pn/M, Pm/M, Zn.S, Zm.S (outer-product accumulate) - // 10000000 10 0 Zm 0 Pm 0 Pn Zn 0 0000 ZAd - .SME_FMOPA = { - {.SME_FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, - }, - .SME_FMOPS = { - {.SME_FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, - }, - .SME_BFMOPA = { - {.SME_BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, - }, - .SME_BFMOPS = { - {.SME_BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, - }, - .SME_SMOPA = { - {.SME_SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, - {.SME_SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, - }, - .SME_SMOPS = { - {.SME_SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, - {.SME_SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, - }, - .SME_UMOPA = { - {.SME_UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, - {.SME_UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, - }, - .SME_UMOPS = { - {.SME_UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, - {.SME_UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, - }, - .SME_USMOPA = { - {.SME_USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, - }, - .SME_SUMOPA = { - {.SME_SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, - }, - - // SME LDR/STR ZA -- transfer single ZA slice from/to memory by tile-vector ref. - // 11100001 00 0 Wv 000 Xn 00 ZAt (encoded scaffolding; user supplies - // immediate tile selector as IMM_5 and vector base register as - // SVE_OFFSET_BASE_SI for the memory address) - .SME_LDR_ZA = { - {.SME_LDR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, - }, - .SME_STR_ZA = { - {.SME_STR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, - }, - - // ========================================================================= - // ยง25 Apple AMX (undocumented coprocessor; A13+, M1+) - // ========================================================================= - // - // Encoding: 0x00201000 | (op << 5) | operand - // bits[31:25] = 0000000 (op0 = 0b0000 -- "reserved" in standard ARM) - // bit [24] = 0 - // bit [23] = 0 - // bit [22] = 0 - // bit [21] = 1 - // bits[20:13] = 00000000 - // bit [12] = 1 - // bits[11:10] = 00 - // bits[9:5] = op (5-bit AMX opcode 0..23) - // bits[4:0] = operand (5-bit; usually GPR holding pointer + control) - // - // The static bits including the op field give mask 0xFFFFFFE0, leaving - // bits[4:0] for the operand. SET/CLR have no operand and use mask - // 0xFFFFFFFF (the operand field is fixed at 0). - - .AMX_LDX = { {.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_LDY = { {.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_STX = { {.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_STY = { {.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_LDZ = { {.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_STZ = { {.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_LDZI = { {.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_STZI = { {.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_EXTRX = { {.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_EXTRY = { {.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMA64 = { {.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMS64 = { {.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMA32 = { {.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMS32 = { {.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_MAC16 = { {.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMA16 = { {.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_FMS16 = { {.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}} }, - - // SET / CLR: no operand. Operand field is forced to 0; mask covers it. - .AMX_SET = { {.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}} }, - .AMX_CLR = { {.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}} }, - - .AMX_VECINT = { {.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_VECFP = { {.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_MATINT = { {.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_MATFP = { {.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - .AMX_GENLUT = { {.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}} }, - - // ========================================================================= - // ยง26 MOPS (v8.8-A memory operations) - // ========================================================================= - // - // Layout (general copy / set): - // bits 31:24 = 0x19 (CPY / SET), 0x1D (CPYF forward-only) - // bits 23:22 = stage (00=P, 01=M, 10=E) - // bits 20:16 = Rn (size register; updated on completion) - // bits 15:14 = options (00 = default) - // bits 13:12 = 01 - // bits 11:10 = 00 - // bits 9:5 = Rs (source / set value) - // bits 4:0 = Rd (destination address; updated) - // - // Mask covers bits 31:21 + 13:10 = 0xFFE03C00. All three GPRs are - // updated on completion; user passes the initial addresses / size. - - .CPYP = { {.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}} }, - .CPYM = { {.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}} }, - .CPYE = { {.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}} }, - .CPYFP = { {.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}} }, - .CPYFM = { {.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}} }, - .CPYFE = { {.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}} }, - // SET* shares the layout but uses bits 23:22 = 11 to mark memset. - .SETP = { {.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}} }, - .SETM = { {.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}} }, - .SETE = { {.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง27 Cache management (SYS-encoded) - // ========================================================================= - // - // SYS instruction layout: - // bits 31:22 = 1101_0101_00 (0xD500) - // bit 21 = L (0 = SYS, 1 = SYSL) - // bit 20 = 1 (system instruction marker) - // bits 18:16 = op1 - // bits 15:12 = CRn - // bits 11:8 = CRm - // bits 7:5 = op2 - // bits 4:0 = Rt (operand register, or 0x1F for register-less variants) - // - // We encode each DC/IC/AT/TLBI variant as its own mnemonic so the - // disassembly reads canonically. Entries with mask 0xFFFFFFE0 leave only - // bits 4:0 (Rt) operand-driven; "no-Rt" variants use mask 0xFFFFFFFF - // (Rt forced to ZR = 0x1F in the bits field). - - // ---- DC (Data Cache) ---------------------------------------------------- - // DC IVAC Xt SYS #0 C7 C6 #1, Xt - // DC ISW Xt SYS #0 C7 C6 #2, Xt - // DC CSW Xt SYS #0 C7 C10 #2, Xt - // DC CISW Xt SYS #0 C7 C14 #2, Xt - // DC ZVA Xt SYS #3 C7 C4 #1, Xt - // DC CVAC Xt SYS #3 C7 C10 #1, Xt - // DC CVAU Xt SYS #3 C7 C11 #1, Xt - // DC CIVAC Xt SYS #3 C7 C14 #1, Xt - .DC_IVAC = { {.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_ISW = { {.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CSW = { {.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CISW = { {.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_ZVA = { {.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CVAC = { {.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CVAU = { {.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CIVAC = { {.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ---- IC (Instruction Cache) -------------------------------------------- - // IC IALLUIS SYS #0 C7 C1 #0 - // IC IALLU SYS #0 C7 C5 #0 - // IC IVAU Xt SYS #3 C7 C5 #1, Xt - .IC_IALLUIS = { {.IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}} }, - .IC_IALLU = { {.IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}} }, - .IC_IVAU = { {.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ---- AT (Address Translate, PE current EL) ------------------------------ - // AT S1E1R Xt SYS #0 C7 C8 #0, Xt - // AT S1E1W Xt SYS #0 C7 C8 #1, Xt - // AT S1E0R Xt SYS #0 C7 C8 #2, Xt - // AT S1E0W Xt SYS #0 C7 C8 #3, Xt - // AT S1E2R Xt SYS #4 C7 C8 #0, Xt - // AT S1E2W Xt SYS #4 C7 C8 #1, Xt - // AT S1E3R Xt SYS #6 C7 C8 #0, Xt - // AT S1E3W Xt SYS #6 C7 C8 #1, Xt - // AT S12E1R Xt SYS #4 C7 C8 #4, Xt - // AT S12E1W Xt SYS #4 C7 C8 #5, Xt - // AT S12E0R Xt SYS #4 C7 C8 #6, Xt - // AT S12E0W Xt SYS #4 C7 C8 #7, Xt - .AT_S1E1R = { {.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E1W = { {.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E0R = { {.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E0W = { {.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E2R = { {.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E2W = { {.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E3R = { {.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S1E3W = { {.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S12E1R = { {.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S12E1W = { {.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S12E0R = { {.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .AT_S12E0W = { {.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ---- TLBI (TLB Invalidate, EL1 + EL2/3 broadcasts) ---------------------- - // TLBI VMALLE1IS SYS #0 C8 C3 #0 -- broadcast inner-shareable - // TLBI VAE1IS Xt SYS #0 C8 C3 #1, Xt - // TLBI ASIDE1IS Xt SYS #0 C8 C3 #2, Xt - // TLBI VAAE1IS Xt SYS #0 C8 C3 #3, Xt - // TLBI VALE1IS Xt SYS #0 C8 C3 #5, Xt - // TLBI VAALE1IS Xt SYS #0 C8 C3 #7, Xt - // TLBI VMALLE1 SYS #0 C8 C7 #0 - // TLBI VAE1 Xt SYS #0 C8 C7 #1, Xt - // TLBI ASIDE1 Xt SYS #0 C8 C7 #2, Xt - // TLBI VAAE1 Xt SYS #0 C8 C7 #3, Xt - // TLBI VALE1 Xt SYS #0 C8 C7 #5, Xt - // TLBI VAALE1 Xt SYS #0 C8 C7 #7, Xt - .TLBI_VMALLE1IS = { {.TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_VAE1IS = { {.TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_ASIDE1IS = { {.TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VAAE1IS = { {.TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VALE1IS = { {.TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VAALE1IS = { {.TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VMALLE1 = { {.TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_VAE1 = { {.TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_ASIDE1 = { {.TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VAAE1 = { {.TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VALE1 = { {.TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_VAALE1 = { {.TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - // EL2/EL3 "ALL" variants (no Rt) - .TLBI_ALLE1 = { {.TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_ALLE1IS = { {.TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_ALLE2 = { {.TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_ALLE2IS = { {.TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_ALLE3 = { {.TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_ALLE3IS = { {.TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}} }, - - // ========================================================================= - // ยง28 PRFM (Prefetch Memory) - // ========================================================================= - // - // PRFM , [Xn, #imm] unsigned-offset form (imm scaled by 8) - // bits 31:22 = 1111_1000_10 (0x3E2 << 22) - // -> base 0xF9800000 - // bits 21:10 = imm12 (operand) - // bits 9:5 = Rn (base) - // bits 4:0 = prfop (5-bit prefetch operation selector) - // PRFUM (unscaled): bits 31:21 = 1111_1000_100, base 0xF8800000 - // PRFM (literal): bits 31:24 = 1101_1000, base 0xD8000000 - - .PRFM = { {.PRFM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}} }, - .PRFUM = { {.PRFUM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}} }, - .PRFM_LIT = { {.PRFM_LIT, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง29 Aliases (printed canonically; encode with Rd=ZR or Rn=ZR) - // ========================================================================= - // - // MOV Rd, Rm = ORR Rd, ZR, Rm (sf=1 0101010 shift=00 Rm imm6=0 Rn=31 Rd) - // MOV Rd, #imm = ORR Rd, ZR, #bitmask (sf=1 01100100 N immr imms Rn=31 Rd) - // MVN Rd, Rm = ORN Rd, ZR, Rm (sf=1 0101010 shift=00 1 Rm imm6=0 Rn=31 Rd) - // NEG Rd, Rm{,shift} = SUB Rd, ZR, Rm{,shift} (sf=1 1001011 shift Rm imm6 Rn=31 Rd) - // NEGS Rd, Rm{,shift} = SUBS Rd, ZR, Rm{,shift} - // CMP Rn, Rm{,shift} = SUBS ZR, Rn, Rm{,shift} - // CMP Rn, Rm, ext = SUBS ZR, Rn, Rm, ext - // CMP Rn, #imm = SUBS ZR, Rn, #imm - // CMN Rn, Rm{,shift} = ADDS ZR, Rn, Rm{,shift} - // CMN Rn, Rm, ext = ADDS ZR, Rn, Rm, ext - // CMN Rn, #imm = ADDS ZR, Rn, #imm - // TST Rn, Rm{,shift} = ANDS ZR, Rn, Rm{,shift} - - .MOV_REG = { - // 32-bit: ORR Wd, WZR, Wm -- base 0x2A0003E0 = ORR Wd, W31, Wm (shift=LSL, imm6=0, Rn=31) - {.MOV_REG, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, - {.MOV_REG, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - }, - .MOV_BITMASK = { - {.MOV_BITMASK, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, - {.MOV_BITMASK, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, - }, - .MVN = { - // ORN Wd, WZR, Wm -- base 0x2A2003E0 - {.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, - {.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - }, - .NEG_SR = { - // SUB Wd, WZR, Wm{, shift #imm6} -- base 0x4B0003E0 - {.NEG_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, - {.NEG_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, - }, - .NEGS = { - // SUBS Wd, WZR, Wm{, shift #imm6} -- base 0x6B0003E0 - {.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, - {.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMP_SR = { - // SUBS WZR, Wn, Wm{, shift} -- base 0x6B00001F - {.CMP_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.CMP_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMP_ER = { - // SUBS WZR, Wn, Wm, ext -- base 0x6B20001F - {.CMP_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, - {.CMP_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMP_IMM = { - // SUBS WZR, Wn, #imm12{, LSL #12} -- base 0x7100001F - {.CMP_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, - {.CMP_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMN_SR = { - // ADDS WZR, Wn, Wm{, shift} -- base 0x2B00001F - {.CMN_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.CMN_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMN_ER = { - // ADDS WZR, Wn, Wm, ext -- base 0x2B20001F - {.CMN_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, - {.CMN_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .CMN_IMM = { - // ADDS WZR, Wn, #imm12 -- base 0x3100001F - {.CMN_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, - {.CMN_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, - }, - .TST_SR = { - // ANDS WZR, Wn, Wm{, shift} -- base 0x6A00001F - {.TST_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, - {.TST_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, - }, - - // ========================================================================= - // ยง30 SVE indexed FMLA / FMLS (lane-broadcast multiply-accumulate) - // ========================================================================= - // - // Layout (.D, 1-bit lane): - // bits 31:22 = 01100100 11 - // bit 21 = 1 - // bit 20 = i1 (lane[0]) - // bits 19:16 = Zm (4-bit, Z0-Z15) - // bits 15:13 = 000 - // bit 12 = 0 (FMLA) / 1 (FMLS) - // bits 11:10 = 00 - // bits 9:5 = Zn - // bits 4:0 = Zda - // - // .S form: lane is 2-bit at bits 20:19, Zm is 3-bit at 18:16 (Z0-Z7) - // .H form: lane is 3-bit (bit 22, bits 20:19), Zm is 3-bit at 18:16 - - .SVE_FMLA_IDX_H = { - {.SVE_FMLA_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, - }, - .SVE_FMLA_IDX_S = { - {.SVE_FMLA_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, - }, - .SVE_FMLA_IDX_D = { - {.SVE_FMLA_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_FMLS_IDX_H = { - {.SVE_FMLS_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, - }, - .SVE_FMLS_IDX_S = { - {.SVE_FMLS_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, - }, - .SVE_FMLS_IDX_D = { - {.SVE_FMLS_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - - // ========================================================================= - // ยง31 SVE gather loads / scatter stores - // ========================================================================= - // - // Layout (scalar+vector form): - // bits 31:25 = 1000010 (gather) / 1110010 (scatter) - // bits 24:23 = size (00=B, 01=H, 10=W, 11=D) - // bits 22:21 = signed/unsigned + offsets-32/64 marker - // bits 20:16 = Zm (vector index register) - // bits 15:13 = options (extend type encoded here for 32-bit offsets) - // bits 12:10 = Pg (governing predicate, P0-P7) - // bits 9:5 = Xn (base register) - // bits 4:0 = Zt (destination) - // - // We commit to the most common variants: unscaled-byte and naturally- - // scaled half/word/double gather/scatter with 32-bit or 64-bit vector - // offsets. - - // Gather LD1B { Zt.S }, Pg/Z, [Xn, Zm.S, UXTW] - .SVE_LD1B_GATHER_S = { - {.SVE_LD1B_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_LD1B_GATHER_D = { - {.SVE_LD1B_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1H_GATHER_S = { - {.SVE_LD1H_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_LD1H_GATHER_D = { - {.SVE_LD1H_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1W_GATHER_S = { - {.SVE_LD1W_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_LD1W_GATHER_D = { - {.SVE_LD1W_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1D_GATHER_D = { - {.SVE_LD1D_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - - // Signed-extending gather loads (LD1SB / LD1SH / LD1SW) - .SVE_LD1SB_GATHER_S = { - {.SVE_LD1SB_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_LD1SB_GATHER_D = { - {.SVE_LD1SB_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1SH_GATHER_S = { - {.SVE_LD1SH_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_LD1SH_GATHER_D = { - {.SVE_LD1SH_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_LD1SW_GATHER_D = { - {.SVE_LD1SW_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - - // Scatter stores - .SVE_ST1B_SCATTER_S = { - {.SVE_ST1B_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_ST1B_SCATTER_D = { - {.SVE_ST1B_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_ST1H_SCATTER_S = { - {.SVE_ST1H_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_ST1H_SCATTER_D = { - {.SVE_ST1H_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_ST1W_SCATTER_S = { - {.SVE_ST1W_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, - }, - .SVE_ST1W_SCATTER_D = { - {.SVE_ST1W_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - .SVE_ST1D_SCATTER_D = { - {.SVE_ST1D_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, - }, - - // ========================================================================= - // ยง32 SME tile slice load/store - // ========================================================================= - // - // Layout for LD1B { ZAt.B[Ws, #imm] }, Pg/Z, [Xn, Xm]: - // bits 31:22 = 1110000000 (0xE00) - // bit 21 = 0 - // bits 20:16 = Xm - // bit 15 = V flag (0=H, 1=V) - // bit 14 = 0 - // bits 13:10 = ws[1:0] || pg[2:0] (the slice descriptor packer - // splits the 4 bits as Ws<<13 + imm<<0 + Pg via the - // separate PG operand encoding; for v1 we treat the - // whole 4-bit field as Pg+Ws packed) - // bits 9:5 = Xn - // bit 4 = 0 - // bits 3:0 = packed imm + sub-tile bits per element size - // - // Mask covers bits 31:22 + bit 21 + bit 14 + bit 4 (the always-fixed - // ones) = 0xFFE00010. The H/V flag (bit 15), tile number (bits 22 or - // 23:22 etc.), and operand fields stay operand-driven. - - // - // Verified against LLVM's MC tests for AArch64 SME: - // ld1b {za0h.b[w12,0]}, p0/z, [x0, x0] = 0xE0000000 - // ld1h {za0h.h[w12,0]}, p0/z, [x0, x0] = 0xE0400000 - // ld1w {za0h.s[w12,0]}, p0/z, [x0] = 0xE0800000 - // ld1d {za0h.d[w12,0]}, p0/z, [x0, x0] = 0xE0C00000 - // ld1q {za0h.q[w12,0]}, p0/z, [x0, x0] = 0xE0E00000 (note: same as - // ST1D bit pattern in the bits[31:22] field, but the tile/imm slot - // at bits 3:0 differs; the user-side slice descriptor encodes the - // element-size sub-format) - // - // The static prefix at bits 31:21 (0xE0 in byte 3, 0xE0 in byte 2's - // top 3 bits) identifies the SME LD1 family. bits 23:22 select the - // element size {00=B, 01=H, 10=W, 11=D}; bit 21 selects LD1Q (when set - // alongside bits 23:22 = 11). Tile number and imm offset are *packed* - // into bits 3:0 of the instruction (per element size): - // .B : imm[3:0] (single tile, ZA0.B implicit) - // .H : tile[0]<<3 | imm[2:0] (2 tiles, 8 slices each) - // .W : tile[1:0]<<2 | imm[1:0] (4 tiles, 4 slices each) - // .D : tile[2:0]<<1 | imm[0] (8 tiles, 2 slices each) - // .Q : tile[3:0] (16 tiles, 1 slice each) - - .SME_LD1B_TILE = { - {.SME_LD1B_TILE, {.SME_SLICE_B, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, - }, - .SME_LD1H_TILE = { - {.SME_LD1H_TILE, {.SME_SLICE_H, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, - }, - .SME_LD1W_TILE = { - {.SME_LD1W_TILE, {.SME_SLICE_W, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, - }, - .SME_LD1D_TILE = { - {.SME_LD1D_TILE, {.SME_SLICE_D, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, - }, - .SME_LD1Q_TILE = { - {.SME_LD1Q_TILE, {.SME_SLICE_Q, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, - }, - - // Store family: same prefix but bit 21 set (LD vs ST distinguisher). - .SME_ST1B_TILE = { - {.SME_ST1B_TILE, {.SME_SLICE_B, .P_REG, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, - }, - .SME_ST1H_TILE = { - {.SME_ST1H_TILE, {.SME_SLICE_H, .P_REG, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, - }, - .SME_ST1W_TILE = { - {.SME_ST1W_TILE, {.SME_SLICE_W, .P_REG, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, - }, - .SME_ST1D_TILE = { - {.SME_ST1D_TILE, {.SME_SLICE_D, .P_REG, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, - }, - .SME_ST1Q_TILE = { - {.SME_ST1Q_TILE, {.SME_SLICE_Q, .P_REG, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, - }, - - // ========================================================================= - // ยง33 SME MOVA (transfer between Z register and ZA tile slice) - // ========================================================================= - // - // MOVA Zt.T, Pg/M, ZAt.T[Ws, #imm] -- tile slice -> Z reg - // MOVA ZAt.T[Ws, #imm], Pg/M, Zn.T -- Z reg -> tile slice - - .SME_MOVA_Z_FROM_TILE = { - {.SME_MOVA_Z_FROM_TILE, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, - }, - .SME_MOVA_TILE_FROM_Z = { - {.SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, - }, - - // SME ZA outer-sum accumulate: ADDHA/ADDVA ZAda.S, Pn/m, Pm/m, Zn.S. - // ZAda tile at bits 2:0, Pn (Pg) at 12:10, Pm at 15:13, Zn at 9:5. - .SME_ADDHA = { {.SME_ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}} }, - .SME_ADDVA = { {.SME_ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}} }, - - // ========================================================================= - // ยง34 NEON complex FP multiply-add (v8.3-A FCMA extension) - // ========================================================================= - // - // Verified against LLVM MC golden tests (test/MC/AArch64/armv8.3a-complex.s): - // fcmla v0.4h, v1.4h, v2.4h, #0 = 0x2E42C420 - // fcmla v0.8h, v1.8h, v2.8h, #0 = 0x6E42C420 - // fcmla v0.4s, v1.4s, v2.4s, #0 = 0x6E82C420 - // fcmla v0.2d, v1.2d, v2.2d, #0 = 0x6EC2C420 - // fcadd v0.4s, v1.4s, v2.4s, #90 = 0x6E82E420 - // - // FCMLA layout: bit 30 = Q, bit 29 = U=1, bits 28:24 = 01110, bits 23:22 - // = size (01=H, 10=S, 11=D), bit 21 = 0, bits 20:16 = Rm, bits 15:14 = 11, - // bits 13:12 = rot (4 rotations), bits 11:10 = 01, Rn at 9:5, Rd at 4:0. - // - // FCADD layout: same except bit 13 = 1 (static), bit 12 = rot (0=90ยฐ, 1=270ยฐ). - - .FCMLA_4H = { {.FCMLA_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}} }, - .FCMLA_8H = { {.FCMLA_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}} }, - .FCMLA_4S = { {.FCMLA_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}} }, - .FCMLA_2D = { {.FCMLA_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}} }, - - .FCADD_4H = { {.FCADD_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}} }, - .FCADD_8H = { {.FCADD_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}} }, - .FCADD_4S = { {.FCADD_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}} }, - .FCADD_2D = { {.FCADD_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}} }, - - // ========================================================================= - // ยง35 SVE prefetch - // ========================================================================= - .SVE_PRFB = { {.SVE_PRFB, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}} }, - .SVE_PRFH = { {.SVE_PRFH, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}} }, - .SVE_PRFW = { {.SVE_PRFW, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}} }, - .SVE_PRFD = { {.SVE_PRFD, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}} }, - - // ========================================================================= - // ยง36 SVE non-temporal load/store - // ========================================================================= - .SVE_LDNT1B = { {.SVE_LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}} }, - .SVE_LDNT1H = { {.SVE_LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}} }, - .SVE_LDNT1W = { {.SVE_LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}} }, - .SVE_LDNT1D = { {.SVE_LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}} }, - .SVE_STNT1B = { {.SVE_STNT1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}} }, - .SVE_STNT1H = { {.SVE_STNT1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}} }, - .SVE_STNT1W = { {.SVE_STNT1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}} }, - .SVE_STNT1D = { {.SVE_STNT1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}} }, - - // ========================================================================= - // ยง37 SVE permute / init: EXT, SPLICE, INDEX (II / IR / RI / RR) - // ========================================================================= - .SVE_EXT = { {.SVE_EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}} }, - .SVE_SPLICE = { {.SVE_SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}} }, - .SVE_INDEX_II = { {.SVE_INDEX_II, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}} }, - .SVE_INDEX_IR = { {.SVE_INDEX_IR, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}} }, - .SVE_INDEX_RI = { {.SVE_INDEX_RI, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}} }, - .SVE_INDEX_RR = { {.SVE_INDEX_RR, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}} }, - - // ========================================================================= - // ยง38 SVE2 bit-select family - // ========================================================================= - // Verified vs LLVM golden (test/MC/AArch64/SVE2/bsl.s): - // bsl z0.d, z0.d, z1.d, z2.d = 0x04213C40 - // Decompose: Zdn=0 at bits 4:0, Zm=1 at bits 20:16, Zk=2 at bits 9:5 - // Base (operands zero) = 0x04203C00. - // The other three variants (BSL1N/BSL2N/NBSL) differ at bit 22/23 in - // most family-encoding traditions; values below are best-memory. - .SVE_BSL = { {.SVE_BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}} }, - .SVE_BSL1N = { {.SVE_BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}} }, - .SVE_BSL2N = { {.SVE_BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}} }, - .SVE_NBSL = { {.SVE_NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}} }, - - // ========================================================================= - // ยง39 SVE2 polynomial multiply - // ========================================================================= - .SVE_PMUL_VEC = { {.SVE_PMUL_VEC, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}} }, - .SVE_PMULLB = { {.SVE_PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}} }, - .SVE_PMULLT = { {.SVE_PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}} }, - - // ========================================================================= - // ยง40 SVE BF16 conversions - // ========================================================================= - .SVE_BFCVT = { {.SVE_BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}} }, - .SVE_BFCVTNT = { {.SVE_BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}} }, - - // ========================================================================= - // ยง41 PAC-authenticated loads (v8.3-A) - // ========================================================================= - // - // LDRAA Xt, [Xn{, #imm}] -- key A, offset form - // LDRAB Xt, [Xn{, #imm}] -- key B, offset form - // LDRAA Xt, [Xn{, #imm}]! -- pre-index variant - // LDRAB Xt, [Xn{, #imm}]! - // - // bits 31:24 = 11111000, bit 23 = M (key), bits 22:12 = imm10 (scaled by 8), - // bits 11:10 = 01 (offset) or 11 (pre-index), bits 9:5 = Rn, bits 4:0 = Rt. - - .LDRAA = { {.LDRAA, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}} }, - .LDRAB = { {.LDRAB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}} }, - .LDRAA_PRE = { {.LDRAA_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}} }, - .LDRAB_PRE = { {.LDRAB_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}} }, - - // ========================================================================= - // ยง42 TME (Transactional Memory Extension, v9.0-A) - // ========================================================================= - .TSTART = { {.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TCOMMIT = { {.TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}} }, - .TCANCEL = { {.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}} }, - .TTEST = { {.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง43 WFIT / WFET (v8.7-A wait with timeout) - // ========================================================================= - .WFET = { {.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .WFIT = { {.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง44 BC.cond (v8.8-A branch consistency) - // ========================================================================= - // - // Identical to B.cond layout except bit 4 = 1 (the "consistency" hint). - // The condition code at bits 3:0 is still operand-driven. - - .BC_COND = { {.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, - 0x54000010, 0xFF000010, .BASE, {cond_branch=true}} }, - - // ========================================================================= - // ยง45 Sign/zero-extend aliases (UBFM/SBFM specific cases) - // ========================================================================= - // - // UXTB Wd, Wn = UBFM Wd, Wn, #0, #7 - // UXTH Wd, Wn = UBFM Wd, Wn, #0, #15 - // UXTW Xd, Wn = UBFM Xd, Xn, #0, #31 (N=1 for 64-bit form) - // SXTB Wd, Wn = SBFM Wd, Wn, #0, #7 - // SXTH Wd, Wn = SBFM Wd, Wn, #0, #15 - // SXTW Xd, Wn = SBFM Xd, Wn, #0, #31 - - .UXTB = { {.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}} }, - .UXTH = { {.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}} }, - .UXTW = { {.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}} }, - .SXTB = { {.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}} }, - .SXTH = { {.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}} }, - .SXTW = { {.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง46 Carry arithmetic (ADC / ADCS / SBC / SBCS / NGC / NGCS) - // ========================================================================= - // - // ADC Rd, Rn, Rm Rd = Rn + Rm + C - // ADCS Rd, Rn, Rm flags-setting variant - // SBC Rd, Rn, Rm Rd = Rn - Rm - !C - // SBCS Rd, Rn, Rm flags-setting - // NGC Rd, Rm alias of SBC Rd, ZR, Rm - // NGCS Rd, Rm alias of SBCS Rd, ZR, Rm - // - // Layout: sf | op | S | 11010000 | Rm | 000000 | Rn | Rd. Mask covers - // the static funct field at bits 30:21 + bits 15:10 = 0xFFE0FC00. - - .ADC = { - {.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, - {.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .ADCS = { - {.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, - {.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, - }, - .SBC = { - {.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, - {.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, - }, - .SBCS = { - {.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, - {.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, - }, - // NGC/NGCS: Rn = ZR (= 31). Static Rn=31 at bits 9:5 = 0x3E0. - .NGC = { - {.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, - {.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, - }, - .NGCS = { - {.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, - {.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, - }, - - // ========================================================================= - // ยง47 RCpc-unscaled load/store (LDAPUR / STLUR family, v8.4-A) - // ========================================================================= - // - // LDAPUR Rt, [Xn{, #imm9}] -- load-acquire RCpc, unscaled signed-9 - // STLUR Rt, [Xn{, #imm9}] -- store-release RCpc, unscaled signed-9 - // LDAPURB Wt, ... / STLURB Wt -- byte - // LDAPURH Wt, ... / STLURH Wt -- halfword - // LDAPURSB Wt/Xt -- signed-extend byte - // LDAPURSH Wt/Xt -- signed-extend half - // LDAPURSW Xt -- signed-extend word (64-bit dest) - // - // Layout: size:111001 0 0 imm9 00 Rn Rt. opc field selects load/store - // (00=STLUR, 01=LDAPUR, 10=LDAPURS-64, 11=LDAPURS-32). Mask covers - // bits 31:21 + bits 11:10 = 0xFFE00C00. - - .LDAPUR = { - {.LDAPUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, - {.LDAPUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .STLUR = { - {.STLUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, - {.STLUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, - }, - .LDAPURB = { {.LDAPURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}} }, - .STLURB = { {.STLURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}} }, - .LDAPURH = { {.LDAPURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}} }, - .STLURH = { {.STLURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}} }, - .LDAPURSB = { - {.LDAPURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDAPURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, - }, - .LDAPURSH = { - {.LDAPURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, - {.LDAPURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, - }, - .LDAPURSW = { {.LDAPURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}} }, - - // ========================================================================= - // ยง48 SVE BF16 predicated arithmetic (3-same) - // ========================================================================= - // - // BFADD Zd.H, Pg/M, Zd.H, Zm.H Zd = Zd + Zm - // BFSUB Zd.H, Pg/M, Zd.H, Zm.H Zd = Zd - Zm - // BFMUL Zd.H, Pg/M, Zd.H, Zm.H Zd = Zd * Zm - // BFMLA Zda.H, Pg/M, Zn.H, Zm.H Zda += Zn * Zm - // BFMLS Zda.H, Pg/M, Zn.H, Zm.H Zda -= Zn * Zm - // - // All use the standard SVE predicated 3-same layout (same shape as - // FADD_PRED etc.) but with BF16-specific opcode bits. - - .SVE_BFADD = { {.SVE_BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}} }, - .SVE_BFSUB = { {.SVE_BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}} }, - .SVE_BFMUL = { {.SVE_BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}} }, - .SVE_BFMLA = { {.SVE_BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}} }, - .SVE_BFMLS = { {.SVE_BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}} }, - - // ========================================================================= - // ยง49 Speculation / profiling barriers + speculation hints - // ========================================================================= - // - // SB = 0xD50330FF (Speculation Barrier, v8.0) - // CSDB = 0xD503229F (Consumption of Speculative Data Barrier) - // DGH = 0xD50320DF (Data Gathering Hint, v8.5-A) - // PSB CSYNC = 0xD503223F (Profile Sync Barrier) - // TSB CSYNC = 0xD503225F (Trace Sync Barrier, v8.4-A SPE) - // BTI j = 0xD503245F (Branch Target Identification: j) - // BTI c = 0xD503249F (BTI: c) - // BTI jc = 0xD50324DF (BTI: jc) - - .SB = { {.SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}} }, - .CSDB = { {.CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}} }, - .DGH = { {.DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}} }, - .PSB_CSYNC = { {.PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}} }, - .TSB_CSYNC = { {.TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}} }, - .BTI_J = { {.BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}} }, - .BTI_C = { {.BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}} }, - .BTI_JC = { {.BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}} }, - - // ========================================================================= - // ยง50 NEON aliases (printed canonically; encode as the underlying op) - // ========================================================================= - // - // MOV Vd., Vn. = ORR Vd., Vn., Vn. (Rm = Rn) - // NOT Vd., Vn. = MVN with Rm = Rn (NEON vector form) - // - // For both we use Rn at both bit positions; the user passes Vd, Vn and - // the encoder duplicates Vn into the Rm slot via two RM-style packs. - - .MOV_V_ALIAS = { - // 8B form: 0x0EA01C00 base; Rm=Rn duplicated - {.MOV_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, - // 16B: 0x4EA01C00 - {.MOV_V_ALIAS, {.V_16B,.V_16B,.NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, - }, - .NOT_V_ALIAS = { - // NOT.8B Vd, Vn = 0x2E205800 (Q=0) - {.NOT_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, - // NOT.16B Vd, Vn = 0x6E205800 (Q=1) - {.NOT_V_ALIAS, {.V_16B,.V_16B,.NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, - }, - - // ========================================================================= - // ยง51 Shift-by-immediate aliases (LSR / ASR with shift in IMM_5 / IMM_6) - // ========================================================================= - // - // LSR Wd, Wn, #imm = UBFM Wd, Wn, #imm, #31 base 0x53007C00 - // LSR Xd, Xn, #imm = UBFM Xd, Xn, #imm, #63 base 0xD340FC00 - // ASR Wd, Wn, #imm = SBFM Wd, Wn, #imm, #31 base 0x13007C00 - // ASR Xd, Xn, #imm = SBFM Xd, Xn, #imm, #63 base 0x9340FC00 - // - // The shift amount (user-passed immediate) goes into the immr field at - // bits 21:16. The imms field is fully static (31 or 63 baked in). - // - // LSL Wd/Xd is more complex (immr = -imm mod regsize, imms = regsize-1-imm) - // and is intentionally omitted -- users construct via UBFM directly with - // pre-computed fields. - - .LSR_IMM = { - {.LSR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, - {.LSR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, - }, - .ASR_IMM = { - {.ASR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, - {.ASR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, - }, - - // Note: IMM12 encoding places the operand into bits 21:10 (12 bits). - // For LSR/ASR we want immr at bits 21:16 (5 bits) but use IMM12 since - // bits 15:10 are static (imms field = 31/63 baked in). The packer's - // 12-bit shift puts the user value at bits 21:10, and the static imms - // bits OR over the low 6 to fix imms = 31 (for W) or 63 (for X). - // Mask 0xFFC0FC00 leaves bits 21:16 + 15:10 free for operand + verifies imms. - // (Operand encoding done in encoder.odin packer; mask above ensures - // imms is verified static at 31 for W and 63 for X via the bits field.) - // Actually 0x53007C00 has bits 15:10 = 011111 = 31 โœ“ and mask - // 0xFFC0FC00 covers bits 15:10 too (mask byte 1 = 0xFC) so imms is - // matched static. Good. - - // ========================================================================= - // ยง52 LSL_IMM / ROR_IMM composite-packed aliases - // ========================================================================= - // - // LSL Rd, Rn, #imm = UBFM Rd, Rn, #(-imm % regsize), #(regsize-1-imm) - // ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm (Rm = Rn) - // - // LSL: the user's single shift amount drives BOTH immr (bits 21:16) - // and imms (bits 15:10). The ENC_LSL_IMM_W/X packer computes both - // fields from one operand. - // - // ROR: the source register is packed at BOTH the Rn (9:5) and Rm - // (20:16) slots via ENC_DUAL_RN_RM; shift goes to imms (15:10). - - .LSL_IMM = { - {.LSL_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, - {.LSL_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, - }, - .ROR_IMM = { - // EXTR Rd, Rn, Rn, #lsb: bits = 0x13800000 (32-bit) / 0x93C00000 (64-bit, N=1) - {.ROR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, - {.ROR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, - }, - - // ========================================================================= - // ยง53 SVE2.1 / SME2 BF16 unpredicated + min/max + clamp - // ========================================================================= - // - // BFADD Zd.H, Zn.H, Zm.H (unpredicated, SVE2.1) - // BFSUB Zd.H, Zn.H, Zm.H - // BFMUL Zd.H, Zn.H, Zm.H - // BFCLAMP Zd.H, Zn.H, Zm.H -- Zd = clamp(Zd, Zn, Zm) (min then max) - // BFMAXNM, BFMINNM -- predicated max/min-num for BF16 - - .SVE_BFADD_UNPRED = { {.SVE_BFADD_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}} }, - .SVE_BFSUB_UNPRED = { {.SVE_BFSUB_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}} }, - .SVE_BFMUL_UNPRED = { {.SVE_BFMUL_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}} }, - .SVE_BFCLAMP = { {.SVE_BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}} }, - .SVE_BFMAXNM = { {.SVE_BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}} }, - .SVE_BFMINNM = { {.SVE_BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}} }, - - // ========================================================================= - // ยง54 SME2 multi-vector: LUTI2/LUTI4 + contiguous list LD1/ST1 - // ========================================================================= - // - // SME2 introduces multi-vector instructions taking a 2-vector list - // {Zt-Zt+1} or 4-vector list {Zt-Zt+3} as the operand. The starting - // Z register's number is constrained to be even (pair) or a multiple - // of 4 (quad), validated by the matcher (Z_PAIR / Z_QUAD types). - // - // The encodings here are representative starting bases; the exact - // sub-opcode bits within each family are best-memory and will need - // verification against the SME2 spec when actually exercised. - - .SME2_LUTI2_B = { {.SME2_LUTI2_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}} }, - .SME2_LUTI4_B = { {.SME2_LUTI4_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}} }, - - // SME2 multi-vector contiguous loads / stores. Form: - // LD1B { Zt0.B, Zt1.B }, Pg/Z, [Xn, Xm] (2-vector) - // LD1B { Zt0.B - Zt3.B }, Pg/Z, [Xn, Xm] (4-vector) - // ST1B { Zt0.B, Zt1.B }, Pg, [Xn, Xm] - // ST1B { Zt0.B - Zt3.B }, Pg, [Xn, Xm] - // - // Bases differ by the {x2}/{x4} marker in the sub-opcode bits. - - .SME2_LD1B_X2 = { {.SME2_LD1B_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1H_X2 = { {.SME2_LD1H_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1W_X2 = { {.SME2_LD1W_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1D_X2 = { {.SME2_LD1D_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}} }, - - .SME2_LD1B_X4 = { {.SME2_LD1B_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1H_X4 = { {.SME2_LD1H_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1W_X4 = { {.SME2_LD1W_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}} }, - .SME2_LD1D_X4 = { {.SME2_LD1D_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}} }, - - .SME2_ST1B_X2 = { {.SME2_ST1B_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1H_X2 = { {.SME2_ST1H_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1W_X2 = { {.SME2_ST1W_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1D_X2 = { {.SME2_ST1D_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}} }, - - .SME2_ST1B_X4 = { {.SME2_ST1B_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1H_X4 = { {.SME2_ST1H_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1W_X4 = { {.SME2_ST1W_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}} }, - .SME2_ST1D_X4 = { {.SME2_ST1D_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}} }, - - // SME2 ZIP/UZP 3-way and 4-way multi-vector permutations (subset). - // ZIP_3/UZP_3: pair result from two single sources (3-operand) - // ZIP_4/UZP_4: quad list result from quad list source (2-operand, 4-vec) - .SME2_ZIP_3 = { {.SME2_ZIP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}} }, - .SME2_ZIP_4 = { {.SME2_ZIP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}} }, - .SME2_UZP_3 = { {.SME2_UZP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}} }, - .SME2_UZP_4 = { {.SME2_UZP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}} }, - - // ========================================================================= - // ยง55 RME (Realm Management Extension, ARMv9-A) - // ========================================================================= - // - // TLBI RPALOS Xt -- invalidate by physical addr (last level) - // TLBI RPAOS Xt -- invalidate by physical addr (all levels) - // TLBI PAALL -- invalidate all entries in physical AS - // TLBI PAALLOS -- same, outer shareable - // AT S1E1A Xt -- stage-1 translate with implicit authority - // DC CIPAPA Xt -- cache mgmt by physical addr, clean+invalidate - // DC CIGDPAPA Xt -- same, including tags - - .TLBI_RPALOS = { {.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_RPAOS = { {.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .TLBI_PAALL = { {.TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}} }, - .TLBI_PAALLOS = { {.TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}} }, - .AT_S1E1A = { {.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CIPAPA = { {.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - .DC_CIGDPAPA = { {.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}} }, - - // ========================================================================= - // SPECGEN โ€” auto-generated, llvm-mc-verified encode forms (NEON/SVE/SME/...). - // Regenerate via: luajit tablegen/specgen.lua ยท do NOT hand-edit this region. - // ========================================================================= - // SPECGEN:BEGIN - // Advanced SIMD three-same (integer). - .SHADD = { - {.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, - {.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, - {.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, - {.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, - {.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, - {.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, - }, - .UHADD = { - {.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, - {.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, - {.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, - {.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, - {.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, - {.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, - }, - .SHSUB = { - {.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, - {.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, - {.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, - {.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, - {.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, - {.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, - }, - .UHSUB = { - {.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, - {.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, - {.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, - {.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, - {.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, - {.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, - }, - .SRHADD = { - {.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, - {.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, - {.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, - {.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, - {.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, - {.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, - }, - .URHADD = { - {.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, - {.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, - {.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, - {.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, - {.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, - {.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, - }, - .SQADD = { - {.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, - {.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, - }, - .UQADD = { - {.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, - {.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQSUB = { - {.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, - {.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, - }, - .UQSUB = { - {.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, - {.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, - }, - .SMAX = { - {.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, - {.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, - {.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, - {.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, - {.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, - {.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, - }, - .UMAX = { - {.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, - {.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, - {.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, - {.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, - {.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, - {.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, - }, - .SMIN = { - {.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, - {.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, - {.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, - {.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, - {.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, - {.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, - }, - .UMIN = { - {.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, - {.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, - {.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, - {.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, - {.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, - {.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, - }, - .SABD = { - {.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, - {.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, - {.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, - {.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, - {.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, - {.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, - }, - .UABD = { - {.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, - {.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, - {.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, - {.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, - {.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, - {.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, - }, - .SABA = { - {.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, - {.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, - {.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, - {.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, - {.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, - {.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, - }, - .UABA = { - {.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, - {.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, - {.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, - {.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, - {.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, - {.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, - }, - .MLA_V = { - {.MLA_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, - {.MLA_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, - {.MLA_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, - {.MLA_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, - {.MLA_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, - {.MLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, - }, - .MLS_V = { - {.MLS_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, - {.MLS_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, - {.MLS_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, - {.MLS_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, - {.MLS_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, - {.MLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, - }, - .CMGE = { - {.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, - {.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, - }, - .CMHS = { - {.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, - {.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, - }, - .CMTST = { - {.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, - {.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMULH = { - {.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, - {.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, - {.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, - {.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, - }, - .SQRDMULH = { - {.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, - {.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, - {.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, - {.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, - }, - .ADDP_V = { - {.ADDP_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, - {.ADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, - }, - .SMAXP = { - {.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, - {.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, - {.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, - {.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, - {.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, - {.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, - }, - .SMINP = { - {.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, - {.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, - {.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, - {.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, - {.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, - {.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, - }, - .UMAXP = { - {.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, - {.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, - {.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, - {.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, - {.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, - {.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, - }, - .UMINP = { - {.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, - {.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, - {.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, - {.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, - {.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, - {.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, - }, - .SSHL = { - {.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, - {.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, - }, - .USHL = { - {.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, - {.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, - }, - .SRSHL = { - {.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, - {.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, - }, - .URSHL = { - {.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, - {.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD permute (ZIP/UZP/TRN). - .ZIP1 = { - {.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, - {.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, - }, - .ZIP2 = { - {.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, - {.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, - }, - .UZP1 = { - {.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, - {.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, - }, - .UZP2 = { - {.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, - {.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, - }, - .TRN1 = { - {.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, - {.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, - }, - .TRN2 = { - {.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, - {.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD two-register misc. - .ABS_V = { - {.ABS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, - {.ABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, - }, - .NEG_V = { - {.NEG_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, - {.NEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, - }, - .NOT_V = { - {.NOT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, - {.NOT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, - }, - .RBIT_V = { - {.RBIT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, - {.RBIT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, - }, - .REV16_V = { - {.REV16_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, - {.REV16_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, - }, - .REV32_V = { - {.REV32_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, - {.REV32_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, - {.REV32_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, - {.REV32_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, - }, - .REV64 = { - {.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, - {.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, - {.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, - {.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, - {.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, - {.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, - }, - .CLS_V = { - {.CLS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, - {.CLS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, - {.CLS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, - {.CLS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, - {.CLS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, - {.CLS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, - }, - .CLZ_V = { - {.CLZ_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, - {.CLZ_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, - {.CLZ_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, - {.CLZ_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, - {.CLZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, - {.CLZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, - }, - .CNT = { - {.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, - {.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, - }, - .URECPE_V = { - {.URECPE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, - {.URECPE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, - }, - .URSQRTE_V = { - {.URSQRTE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, - {.URSQRTE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD floating-point three-same. - .FMAX_V = { - {.FMAX_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, - {.FMAX_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, - {.FMAX_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, - {.FMAX_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, - {.FMAX_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, - }, - .FMIN_V = { - {.FMIN_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, - {.FMIN_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, - {.FMIN_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, - {.FMIN_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, - {.FMIN_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, - }, - .FMAXNM_V = { - {.FMAXNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, - {.FMAXNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, - }, - .FMINNM_V = { - {.FMINNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, - {.FMINNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, - }, - .FMULX = { - {.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, - {.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, - {.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, - {.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, - }, - .FRECPS = { - {.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, - {.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, - {.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, - {.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, - }, - .FRSQRTS = { - {.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, - {.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, - {.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, - {.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, - {.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, - }, - .FACGE = { - {.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, - {.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, - }, - .FACGT = { - {.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, - {.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, - {.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, - }, - .FCMEQ = { - {.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, - {.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, - {.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, - {.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, - {.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, - }, - .FCMGE = { - {.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, - {.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, - }, - .FCMGT = { - {.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, - {.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, - {.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, - }, - .FADDP_V = { - {.FADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, - {.FADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, - {.FADDP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, - {.FADDP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, - }, - .FMAXP_V = { - {.FMAXP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, - {.FMAXP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, - {.FMAXP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, - {.FMAXP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, - {.FMAXP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, - }, - .FMINP_V = { - {.FMINP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, - {.FMINP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, - {.FMINP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, - {.FMINP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, - {.FMINP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, - }, - .FMAXNMP = { - {.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, - {.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, - {.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, - }, - .FMINNMP = { - {.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, - {.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, - {.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, - }, - - // Advanced SIMD floating-point two-register. - .FABS_V = { - {.FABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, - {.FABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, - {.FABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, - {.FABS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, - {.FABS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, - }, - .FNEG_V = { - {.FNEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, - {.FNEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, - {.FNEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, - {.FNEG_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, - {.FNEG_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, - }, - .FSQRT_V = { - {.FSQRT_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, - {.FSQRT_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, - {.FSQRT_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, - {.FSQRT_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, - {.FSQRT_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTA_V = { - {.FRINTA_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, - {.FRINTA_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, - {.FRINTA_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, - {.FRINTA_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, - {.FRINTA_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTI_V = { - {.FRINTI_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTI_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTI_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTI_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, - {.FRINTI_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTM_V = { - {.FRINTM_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, - {.FRINTM_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, - {.FRINTM_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, - {.FRINTM_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, - {.FRINTM_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTN_V = { - {.FRINTN_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, - {.FRINTN_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, - {.FRINTN_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, - {.FRINTN_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, - {.FRINTN_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTP_V = { - {.FRINTP_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, - {.FRINTP_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, - {.FRINTP_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, - {.FRINTP_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, - {.FRINTP_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTX_V = { - {.FRINTX_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, - {.FRINTX_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, - {.FRINTX_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, - {.FRINTX_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, - {.FRINTX_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTZ_V = { - {.FRINTZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTZ_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, - {.FRINTZ_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, - {.FRINTZ_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, - }, - .FRECPE = { - {.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, - {.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, - {.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, - {.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, - {.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, - }, - .FRSQRTE = { - {.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, - {.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, - {.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, - {.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, - {.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, - }, - - // Advanced SIMD floating-point convert (vector, register form). - .FCVTAS_V = { - {.FCVTAS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, - {.FCVTAS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTAU_V = { - {.FCVTAU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, - {.FCVTAU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, - {.FCVTAU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTMS_V = { - {.FCVTMS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, - {.FCVTMS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTMU_V = { - {.FCVTMU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTMU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, - {.FCVTMU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTNS_V = { - {.FCVTNS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, - {.FCVTNS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTNU_V = { - {.FCVTNU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTNU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, - {.FCVTNU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTPS_V = { - {.FCVTPS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, - {.FCVTPS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTPU_V = { - {.FCVTPU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, - {.FCVTPU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, - {.FCVTPU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTZS_V = { - {.FCVTZS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, - {.FCVTZS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTZU_V = { - {.FCVTZU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, - {.FCVTZU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, - {.FCVTZU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, - }, - .SCVTF_V = { - {.SCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, - {.SCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, - {.SCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, - {.SCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, - {.SCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, - }, - .UCVTF_V = { - {.UCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, - {.UCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, - {.UCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, - {.UCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, - {.UCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, - }, - - // Advanced SIMD three-different (long). - .SADDL = { - {.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, - {.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, - {.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, - }, - .SADDL2 = { - {.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, - {.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, - {.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, - }, - .UADDL = { - {.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, - {.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, - {.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, - }, - .UADDL2 = { - {.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, - {.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, - {.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, - }, - .SSUBL = { - {.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, - {.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, - {.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, - }, - .SSUBL2 = { - {.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, - {.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, - {.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, - }, - .USUBL = { - {.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, - {.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, - {.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, - }, - .USUBL2 = { - {.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, - {.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, - {.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, - }, - .SMULL_V = { - {.SMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, - {.SMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, - {.SMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, - }, - .SMULL2_V = { - {.SMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, - {.SMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, - {.SMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, - }, - .UMULL_V = { - {.UMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, - {.UMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, - {.UMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, - }, - .UMULL2_V = { - {.UMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, - {.UMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, - {.UMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, - }, - .SMLAL = { - {.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, - {.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, - {.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, - }, - .SMLAL2 = { - {.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, - {.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, - {.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, - }, - .UMLAL = { - {.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, - {.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, - {.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, - }, - .UMLAL2 = { - {.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, - {.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, - {.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, - }, - .SMLSL = { - {.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, - {.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, - {.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, - }, - .SMLSL2 = { - {.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, - {.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, - {.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, - }, - .UMLSL = { - {.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, - {.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, - {.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, - }, - .UMLSL2 = { - {.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, - {.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, - {.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMULL = { - {.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, - {.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMULL2 = { - {.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, - {.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMLAL = { - {.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, - {.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMLAL2 = { - {.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, - {.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMLSL = { - {.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, - {.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, - }, - .SQDMLSL2 = { - {.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, - {.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD three-different (wide). - .SADDW = { - {.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, - {.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, - {.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, - }, - .SADDW2 = { - {.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, - {.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, - {.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, - }, - .UADDW = { - {.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, - {.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, - {.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, - }, - .UADDW2 = { - {.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, - {.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, - {.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, - }, - .SSUBW = { - {.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, - {.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, - {.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, - }, - .SSUBW2 = { - {.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, - {.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, - {.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, - }, - .USUBW = { - {.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, - {.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, - {.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, - }, - .USUBW2 = { - {.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, - {.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, - {.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD three-different (narrow, halving). - .ADDHN = { - {.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, - {.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, - {.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, - }, - .ADDHN2 = { - {.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, - {.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, - {.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, - }, - .SUBHN = { - {.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, - {.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, - {.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, - }, - .SUBHN2 = { - {.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, - {.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, - {.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, - }, - .RADDHN = { - {.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, - {.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, - {.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, - }, - .RADDHN2 = { - {.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, - {.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, - {.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, - }, - .RSUBHN = { - {.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, - {.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, - {.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, - }, - .RSUBHN2 = { - {.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, - {.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, - {.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD two-register narrowing (XTN). - .XTN = { - {.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, - {.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, - {.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, - }, - .XTN2 = { - {.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, - {.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, - {.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, - }, - .SQXTN = { - {.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, - {.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, - {.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, - }, - .SQXTN2 = { - {.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, - {.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, - {.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, - }, - .UQXTN = { - {.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, - {.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, - {.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, - }, - .UQXTN2 = { - {.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, - {.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, - {.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, - }, - .SQXTUN = { - {.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, - {.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, - {.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, - }, - .SQXTUN2 = { - {.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, - {.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, - {.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD two-register widen (SXTL/UXTL = SSHLL/USHLL #0). - .SXTL = { - {.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, - {.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, - {.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, - }, - .SXTL2 = { - {.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, - {.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, - {.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, - }, - .UXTL = { - {.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, - {.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, - {.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, - }, - .UXTL2 = { - {.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, - {.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, - {.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD two-register pairwise long. - .SADDLP = { - {.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, - {.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, - {.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, - {.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, - {.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, - {.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, - }, - .UADDLP = { - {.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, - {.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, - {.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, - {.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, - {.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, - {.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, - }, - .SADALP = { - {.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, - {.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, - {.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, - {.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, - {.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, - {.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, - }, - .UADALP = { - {.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, - {.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, - {.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, - {.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, - {.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, - {.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD across lanes. - .ADDV = { - {.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, - {.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, - {.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, - {.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, - {.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, - }, - .SMAXV = { - {.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, - {.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, - {.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, - {.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, - {.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, - }, - .SMINV = { - {.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, - {.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, - {.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, - {.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, - {.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, - }, - .UMAXV = { - {.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, - {.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, - {.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, - {.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, - {.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, - }, - .UMINV = { - {.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, - {.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, - {.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, - {.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, - {.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, - }, - .SADDLV = { - {.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, - {.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, - {.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, - {.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, - {.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, - }, - .UADDLV = { - {.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, - {.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, - {.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, - {.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, - {.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD floating-point across lanes. - .FMAXV_V = { - {.FMAXV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, - {.FMAXV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, - {.FMAXV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, - }, - .FMINV_V = { - {.FMINV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, - {.FMINV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, - {.FMINV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, - }, - .FMAXNMV = { - {.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, - {.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, - {.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, - }, - .FMINNMV = { - {.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, - {.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, - {.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, - }, - - // Advanced SIMD floating-point widen / narrow. - .FCVTL = { - {.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, - {.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, - }, - .FCVTL2 = { - {.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, - {.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, - }, - .FCVTN = { - {.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, - {.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, - }, - .FCVTN2 = { - {.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, - {.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, - }, - .FCVTXN = { - {.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, - }, - .FCVTXN2 = { - {.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, - }, - - // Advanced SIMD compare against zero. - .CMLE = { - {.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, - {.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, - }, - .CMLT = { - {.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, - {.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, - }, - .FCMLE = { - {.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, - {.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, - {.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, - {.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, - {.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, - }, - .FCMLT = { - {.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, - {.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, - {.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, - {.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, - {.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, - }, - - // Advanced SIMD shift by immediate. - .SHL_V = { - {.SHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, - {.SHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, - {.SHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, - {.SHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, - {.SHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, - {.SHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, - {.SHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, - }, - .SLI = { - {.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, - {.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, - {.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, - {.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, - {.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, - {.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, - {.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, - }, - .SQSHLU = { - {.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, - {.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, - {.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, - {.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, - {.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, - {.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, - {.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, - }, - .SQSHL_V = { - {.SQSHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, - {.SQSHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, - {.SQSHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, - {.SQSHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, - {.SQSHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, - {.SQSHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, - {.SQSHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, - }, - .SSHR = { - {.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, - {.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, - {.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, - {.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, - {.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, - {.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, - {.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, - }, - .USHR = { - {.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, - {.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, - {.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, - {.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, - {.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, - {.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, - {.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, - }, - .SRSHR = { - {.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, - {.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, - {.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, - {.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, - {.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, - {.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, - {.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, - }, - .URSHR = { - {.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, - {.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, - {.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, - {.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, - {.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, - {.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, - {.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, - }, - .SSRA = { - {.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, - {.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, - {.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, - {.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, - {.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, - {.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, - {.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, - }, - .USRA = { - {.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, - {.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, - {.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, - {.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, - {.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, - {.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, - {.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, - }, - .SRSRA = { - {.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, - {.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, - {.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, - {.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, - {.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, - {.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, - {.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, - }, - .URSRA = { - {.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, - {.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, - {.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, - {.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, - {.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, - {.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, - {.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, - }, - .SRI = { - {.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, - {.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, - {.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, - {.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, - {.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, - {.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, - {.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, - }, - .SSHLL = { - {.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, - {.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, - {.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, - }, - .SSHLL2 = { - {.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, - {.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, - {.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, - }, - .USHLL = { - {.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, - {.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, - {.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, - }, - .USHLL2 = { - {.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, - {.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, - {.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, - }, - .SHRN = { - {.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, - {.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, - {.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, - }, - .SHRN2 = { - {.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, - {.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, - {.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, - }, - .RSHRN = { - {.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, - {.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, - {.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, - }, - .RSHRN2 = { - {.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, - {.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, - {.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQSHRN = { - {.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, - {.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, - {.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, - }, - .SQSHRN2 = { - {.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, - {.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, - {.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, - }, - .UQSHRN = { - {.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, - {.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, - {.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, - }, - .UQSHRN2 = { - {.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, - {.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, - {.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, - }, - .SQRSHRN = { - {.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, - {.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, - {.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQRSHRN2 = { - {.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, - {.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, - {.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, - }, - .UQRSHRN = { - {.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, - {.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, - {.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, - }, - .UQRSHRN2 = { - {.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, - {.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, - {.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQSHRUN = { - {.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, - {.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, - {.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, - }, - .SQSHRUN2 = { - {.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, - {.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, - {.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, - }, - .SQRSHRUN = { - {.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, - {.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, - {.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, - }, - .SQRSHRUN2 = { - {.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, - {.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, - {.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, - }, - - // Advanced SIMD copy / permute (MOV/MVN/DUP/INS/EXT). - .MOV_V = { - {.MOV_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, - {.MOV_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, - }, - .MVN_V = { - {.MVN_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, - {.MVN_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, - }, - .DUP_V = { - {.DUP_V, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, - {.DUP_V, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, - {.DUP_V, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, - {.DUP_V, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, - {.DUP_V, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, - {.DUP_V, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, - {.DUP_V, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, - {.DUP_V, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, - {.DUP_V, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, - }, - .INS = { - {.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, - {.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, - {.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, - {.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, - {.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, - {.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, - {.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, - {.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, - }, - .EXT_V = { - {.EXT_V, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, - {.EXT_V, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, - }, - - // Scalar FP round/reciprocal + FP-to-GPR convert. - .FRINTN = { - {.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, - {.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, - {.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTP = { - {.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, - {.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, - {.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTM = { - {.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, - {.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, - {.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTZ = { - {.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, - {.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, - {.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTA = { - {.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, - {.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, - {.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTX = { - {.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, - {.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, - {.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, - }, - .FRINTI = { - {.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, - {.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, - {.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, - }, - .FRECPX = { - {.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, - {.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, - {.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTAS = { - {.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, - {.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, - {.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, - {.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, - {.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, - {.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTAU = { - {.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, - {.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, - {.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, - {.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, - {.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, - {.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTMS = { - {.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, - {.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, - {.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, - {.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, - {.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, - {.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTMU = { - {.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, - {.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, - {.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, - {.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, - {.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, - {.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTNS = { - {.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, - {.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, - {.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, - {.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, - {.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, - {.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTNU = { - {.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, - {.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, - {.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, - {.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, - {.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, - {.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTPS = { - {.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, - {.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, - {.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, - {.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, - {.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, - {.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, - }, - .FCVTPU = { - {.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, - {.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, - {.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, - {.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, - {.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, - {.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, - }, - - // NEON modified immediate (MOVI/MVNI). - .MOVI = { - {.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, - {.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, - }, - .MVNI = { - {.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, - {.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, - {.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, - {.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, - }, - - // SVE predicated / compare / predicate-logical / SVE2. - .SVE_FRINTN = { - {.SVE_FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTP = { - {.SVE_FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTM = { - {.SVE_FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTZ = { - {.SVE_FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTA = { - {.SVE_FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTX = { - {.SVE_FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRINTI = { - {.SVE_FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FRECPX_Z = { - {.SVE_FRECPX_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRECPX_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, - {.SVE_FRECPX_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_ASRR_PRED = { - {.SVE_ASRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, - {.SVE_ASRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, - {.SVE_ASRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, - {.SVE_ASRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_LSLR_PRED = { - {.SVE_LSLR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSLR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSLR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSLR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_LSRR_PRED = { - {.SVE_LSRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, - {.SVE_LSRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FSUBR_PRED = { - {.SVE_FSUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, - {.SVE_FSUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, - {.SVE_FSUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FDIVR_PRED = { - {.SVE_FDIVR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, - {.SVE_FDIVR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, - {.SVE_FDIVR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_FCMEQ = { - {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, - }, - .SVE_FCMGE = { - {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, - }, - .SVE_FCMGT = { - {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, - }, - .SVE_FCMNE = { - {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, - }, - .SVE_FCMUO = { - {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, - {.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, - }, - .SVE_FCMLE = { - {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, - {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, - {.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, - }, - .SVE_FCMLT = { - {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, - {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, - {.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, - }, - .SVE_CMPLE = { - {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPLO = { - {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPLS = { - {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_CMPLT = { - {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, - {.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, - }, - .SVE_NANDS_P = { - {.SVE_NANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, - }, - .SVE_NORS_P = { - {.SVE_NORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, - }, - .SVE_ORNS_P = { - {.SVE_ORNS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, - }, - .SVE_BRKPA = { - {.SVE_BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, - }, - .SVE_BRKPB = { - {.SVE_BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, - }, - .SVE_BRKA = { - {.SVE_BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, - }, - .SVE_BRKB = { - {.SVE_BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, - }, - .SVE_BRKAS = { - {.SVE_BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, - }, - .SVE_BRKBS = { - {.SVE_BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, - }, - .SVE_EOR3_Z = { - {.SVE_EOR3_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_BCAX_Z = { - {.SVE_BCAX_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, - }, - .SVE_INSR = { - {.SVE_INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, - {.SVE_INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, - {.SVE_INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, - {.SVE_INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, - }, - .SVE_COMPACT = { - {.SVE_COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, - {.SVE_COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, - }, - .SVE_SETFFR = { - {.SVE_SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, - }, - .SVE_RDFFR = { - {.SVE_RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, - }, - .SVE_WRFFR = { - {.SVE_WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, - }, - .SVE_BRKN = { - {.SVE_BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, - }, - // SPECGEN:END -} diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index 43cc11a07..b8174b428 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -32,10 +32,11 @@ Clobber :: lib.Clobber Blob :: struct { global, file, typ: string } BLOBS := [?]Blob{ - {"ENCODE_FORMS", "arm64.encode_forms.bin", "Encoding"}, - {"ENCODE_RUNS", "arm64.encode_runs.bin", "Encode_Run"}, - {"DECODE_ENTRIES", "arm64.entries.bin", "Decode_Entry"}, - {"DECODE_INDEX_OP0", "arm64.idx_op0.bin", "Decode_Index"}, + {"ENCODE_FORMS", "arm64.encode_forms.bin", "Encoding"}, + {"CLOBBER_FORMS", "arm64.clobber_forms.bin", "Clobber"}, + {"ENCODE_RUNS", "arm64.encode_runs.bin", "Encode_Run"}, + {"DECODE_ENTRIES", "arm64.entries.bin", "Decode_Entry"}, + {"DECODE_INDEX_OP0", "arm64.idx_op0.bin", "Decode_Index"}, } DIR_GEN :: #directory + "/generated/" @@ -73,16 +74,29 @@ emit_encode_tables :: proc() -> (total: int) { strings.write_string(&sb, "// Flattened encode forms + per-mnemonic run index (source: ENCODING_TABLE).\n\n") strings.write_string(&sb, "import lib \"../..\"\n\n") - for m in Mnemonic { total += len(ENCODING_TABLE[m]) } + for m in Mnemonic { total += len(INSTRUCTION_TABLE[m]) } strings.write_string(&sb, "@(rodata)\n") fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total) for m in Mnemonic { - forms := ENCODING_TABLE[m] + forms := INSTRUCTION_TABLE[m] if len(forms) == 0 { continue } fmt.sbprintfln(&sb, "\t// .%v", m) for f in forms { - write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags) + e := f.encoding + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags) + } + } + strings.write_string(&sb, "}\n\n") + + strings.write_string(&sb, "@(rodata)\n") + fmt.sbprintfln(&sb, "CLOBBER_FORMS := [%d]lib.Clobber{{", total) + for m in Mnemonic { + forms := INSTRUCTION_TABLE[m] + if len(forms) == 0 { continue } + fmt.sbprintfln(&sb, "\t// .%v", m) + for f in forms { + write_clobber(&sb, f.clobber) } } strings.write_string(&sb, "}\n\n") @@ -93,7 +107,7 @@ emit_encode_tables :: proc() -> (total: int) { strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") start := 0 for m in Mnemonic { - c := len(ENCODING_TABLE[m]) + c := len(INSTRUCTION_TABLE[m]) name := reflect.enum_string(m) fmt.sbprintf(&sb, "\t.%s", name) for _ in 0.. (total: int) { return } +write_clobber :: proc(sb: ^strings.Builder, clobber: lib.Clobber) { + strings.write_string(sb, "\t{") + defer strings.write_string(sb, "},\n") + + n := 0 + for field in reflect.struct_fields_zipped(lib.Clobber) { + value := reflect.struct_field_value(clobber, field) + if reflect.is_bit_set(field.type) { + if !reflect.is_nil(value) { + if n > 0 { strings.write_string(sb, ", ") } + defer n += 1 + + value_int := value + switch type_info_of(value.id).size { + case 1: value_int.id = u8 + case 2: value_int.id = u16 + case 4: value_int.id = u32 + case 8: value_int.id = u64 + } + bits := reflect.as_u64(value_int) or_else panic("cannot get bits") + + bs := reflect.type_info_base(field.type).variant.(reflect.Type_Info_Bit_Set) + et := reflect.type_info_base(bs.elem) + lower := bs.lower + upper := bs.upper + + strings.write_string(sb, field.name) + strings.write_string(sb, "={") + defer strings.write_byte(sb, '}') + + e, is_enum := et.variant.(reflect.Type_Info_Enum) + + commas := 0 + loop: for i in transmute(bit_set[0..<64])bits { + elem := i64(i) + lower + if commas > 0 { strings.write_string(sb, ", ") } + + if is_enum { + for ev, evi in e.values { + v := u64(ev) + if v == u64(elem) { + strings.write_string(sb, ".") + strings.write_string(sb, e.names[evi]) + commas += 1 + continue loop + } + } + } else { + fmt.sbprintf(sb, "%d", elem) + commas += 1 + } + } + } + } else if reflect.is_boolean(field.type) { + if reflect.as_bool(value) or_else false { + if n > 0 { strings.write_string(sb, ", ") } + defer n += 1 + strings.write_string(sb, field.name) + strings.write_string(sb, "=true") + } + } else { + panic("unhandled type") + } + } +} + // ----------------------------------------------------------------------------- // Decode side // ----------------------------------------------------------------------------- @@ -119,13 +199,14 @@ emit_decode_tables :: proc() -> (total: int) { all: [dynamic]Entry defer delete(all) for mn in Mnemonic { - for f in ENCODING_TABLE[mn] { - op0_static := u8((f.bits >> 25) & 0xF) - op0_mask := u8((f.mask >> 25) & 0xF) + for form in INSTRUCTION_TABLE[mn] { + e := form.encoding + op0_static := u8((e.bits >> 25) & 0xF) + op0_mask := u8((e.mask >> 25) & 0xF) // Enumerate every 4-bit bucket B such that (B & op0_mask) == op0_static. for b: u8 = 0; b < 16; b += 1 { if (b & op0_mask) != op0_static { continue } - append(&all, Entry{f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.flags, b}) + append(&all, Entry{e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags, b}) } } } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 9758f501e..52ed8fa3a 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -3554,6 +3554,3553 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, } +@(rodata) +CLOBBER_FORMS := [2440]lib.Clobber{ + // .ADD_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ADDS_IMM + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + // .SUB_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SUBS_IMM + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + // .MOVZ + {written={0}}, + {written={0}}, + // .MOVN + {written={0}}, + {written={0}}, + // .MOVK + {written={0}}, + {written={0}}, + // .ADR + {written={0}}, + // .ADRP + {written={0}}, + // .ADD_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADDS_SR + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SUB_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SUBS_SR + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .AND_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ANDS_SR + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .ORR_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .EOR_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .BIC_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .BICS_SR + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .ORN_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .EON_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADD_ER + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADDS_ER + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SUB_ER + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SUBS_ER + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .LSLV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .LSRV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ASRV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .RORV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UDIV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SDIV + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .MADD + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .MSUB + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SMADDL + {written={0}, read={1, 2, 3}}, + // .SMSUBL + {written={0}, read={1, 2, 3}}, + // .UMADDL + {written={0}, read={1, 2, 3}}, + // .UMSUBL + {written={0}, read={1, 2, 3}}, + // .SMULH + {written={0}, read={1, 2}}, + // .UMULH + {written={0}, read={1, 2}}, + // .CLZ + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CLS + {written={0}, read={1}}, + {written={0}, read={1}}, + // .RBIT + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV16 + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV32 + {written={0}, read={1}}, + // .CSEL + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .CSINC + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .CSINV + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .CSNEG + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .CCMP_REG + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + // .CCMP_IMM + {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + // .CCMN_REG + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + // .CCMN_IMM + {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + // .EXTR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .B + {side_effects={.CONTROL}}, + // .BL + {implicit_wr={.LR}, side_effects={.CONTROL}}, + // .BR + {read={0}, side_effects={.CONTROL}}, + // .BLR + {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}, + // .RET + {read={0}, side_effects={.CONTROL}}, + {implicit_rd={.LR}, side_effects={.CONTROL}}, + // .B_COND + {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}, + // .CBZ + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + // .CBNZ + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + // .TBZ + {read={0}, side_effects={.CONTROL}}, + // .TBNZ + {read={0}, side_effects={.CONTROL}}, + // .LDR + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .STR + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .LDRB + {written={0}, read={1}, reads_mem=true}, + // .STRB + {read={0, 1}, writes_mem=true}, + // .LDRSB + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDRH + {written={0}, read={1}, reads_mem=true}, + // .STRH + {read={0, 1}, writes_mem=true}, + // .LDRSH + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDRSW + {written={0}, read={1}, reads_mem=true}, + // .LDP + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + // .STP + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .LDPSW + {written={0, 1}, read={2}, reads_mem=true}, + // .LDR_LIT + {written={0}}, + {written={0}}, + // .LDAR + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLR + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDARB + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLRB + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDARH + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLRH + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDXR + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .STXR + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .LDAXR + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .STLXR + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .NOP + {side_effects={.HINT}}, + // .YIELD + {side_effects={.HINT}}, + // .WFE + {side_effects={.WAIT}}, + // .WFI + {side_effects={.WAIT}}, + // .SEV + {side_effects={.HINT}}, + // .SEVL + {side_effects={.HINT}}, + // .HINT + {side_effects={.HINT}}, + // .MRS + {written={0}, read={1}, side_effects={.PRIVILEGED}}, + // .MSR_IMM + {side_effects={.PRIVILEGED}}, + // .MSR_REG + {written={0}, read={1}, side_effects={.PRIVILEGED}}, + // .ISB + {side_effects={.ISYNC}}, + // .DSB + {side_effects={.FENCE}}, + // .DMB + {side_effects={.FENCE}}, + // .SVC + {side_effects={.CONTROL, .EXCEPTION}}, + // .HVC + {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}, + // .SMC + {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}, + // .BRK + {side_effects={.CONTROL, .TRAP}}, + // .HLT + {side_effects={.CONTROL, .TRAP}}, + // .ERET + {side_effects={.CONTROL, .PRIVILEGED}}, + // .FMOV_REG + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FMOV_IMM + {written={0}}, + {written={0}}, + {written={0}}, + // .FMOV_GEN + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FABS + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FNEG + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FSQRT + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + // .FADD + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FSUB + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMUL + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FDIV + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMUL + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMADD + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMSUB + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMADD + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMSUB + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCMP + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + // .FCMPE + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + // .FCSEL + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .FMAX + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMIN + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXNM + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINNM + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FCVT + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SCVTF + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .UCVTF + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .FCVTZS + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTZU + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTAS + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTAU + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTNS + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTNU + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTPS + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTPU + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTMS + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTMU + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FRINTA + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTI + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + // .FRINTM + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTN + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTP + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTX + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + // .FRINTZ + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .AND_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ANDS_IMM + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + // .ORR_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .EOR_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .TST_IMM + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + // .LDUR + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .STUR + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .LDURB + {written={0}, read={1}, reads_mem=true}, + // .STURB + {read={0, 1}, writes_mem=true}, + // .LDURSB + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDURH + {written={0}, read={1}, reads_mem=true}, + // .STURH + {read={0, 1}, writes_mem=true}, + // .LDURSH + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDURSW + {written={0}, read={1}, reads_mem=true}, + // .LDR_PRE + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + // .STR_PRE + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + // .LDR_POST + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + // .STR_POST + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + // .LDRB_PRE + {written={0, 1}, read={1}, reads_mem=true}, + // .STRB_PRE + {written={1}, read={0, 1}, writes_mem=true}, + // .LDRB_POST + {written={0, 1}, read={1}, reads_mem=true}, + // .STRB_POST + {written={1}, read={0, 1}, writes_mem=true}, + // .LDRH_PRE + {written={0, 1}, read={1}, reads_mem=true}, + // .STRH_PRE + {written={1}, read={0, 1}, writes_mem=true}, + // .LDRH_POST + {written={0, 1}, read={1}, reads_mem=true}, + // .STRH_POST + {written={1}, read={0, 1}, writes_mem=true}, + // .LDR_REG + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .STR_REG + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .LDRB_REG + {written={0}, read={1}, reads_mem=true}, + // .STRB_REG + {read={0, 1}, writes_mem=true}, + // .LDRH_REG + {written={0}, read={1}, reads_mem=true}, + // .STRH_REG + {read={0, 1}, writes_mem=true}, + // .LDRSB_REG + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDRSH_REG + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LDRSW_REG + {written={0}, read={1}, reads_mem=true}, + // .LDP_PRE + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + // .STP_PRE + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + // .LDP_POST + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + // .STP_POST + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + // .LDPSW_PRE + {written={0, 1, 2}, read={2}, reads_mem=true}, + // .LDPSW_POST + {written={0, 1, 2}, read={2}, reads_mem=true}, + // .LDNP + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + // .STNP + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .LDXP + {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .STXP + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .LDAXP + {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .STLXP + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .LDXRB + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .STXRB + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .LDAXRB + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .STLXRB + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .LDXRH + {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .STXRH + {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}, + // .LDAXRH + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .STLXRH + {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}, + // .LDAPR + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .LDAPRB + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .LDAPRH + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .LDADD + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDADDA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDADDL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDADDAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDCLR + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDCLRA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDCLRL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDCLRAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDEOR + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDEORA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDEORL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDEORAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSET + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDSETA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSETL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSETAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMAX + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDSMAXA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMAXL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMAXAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMIN + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDSMINA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMINL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDSMINAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMAX + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDUMAXA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMAXL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMAXAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMIN + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .LDUMINA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMINL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .LDUMINAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .SWP + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .SWPA + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .SWPL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .SWPAL + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CAS + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .CASA + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASL + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASAL + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASB + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .CASAB + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASLB + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASALB + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASH + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .CASAH + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASLH + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASALH + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASP + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}, + // .CASPA + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASPL + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .CASPAL + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}, + // .PACIA + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .PACIB + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .PACDA + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .PACDB + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .PACIZA + {written={0}, read={0}, side_effects={.PAC}}, + // .PACIZB + {written={0}, read={0}, side_effects={.PAC}}, + // .PACDZA + {written={0}, read={0}, side_effects={.PAC}}, + // .PACDZB + {written={0}, read={0}, side_effects={.PAC}}, + // .AUTIA + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .AUTIB + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .AUTDA + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .AUTDB + {written={0}, read={0, 1}, side_effects={.PAC}}, + // .AUTIZA + {written={0}, read={0}, side_effects={.PAC}}, + // .AUTIZB + {written={0}, read={0}, side_effects={.PAC}}, + // .AUTDZA + {written={0}, read={0}, side_effects={.PAC}}, + // .AUTDZB + {written={0}, read={0}, side_effects={.PAC}}, + // .PACIASP + {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}, + // .PACIBSP + {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}, + // .AUTIASP + {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}, + // .AUTIBSP + {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}, + // .PACIA1716 + {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}, + // .PACIB1716 + {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}, + // .AUTIA1716 + {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}, + // .AUTIB1716 + {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}, + // .PACGA + {written={0}, read={0, 1, 2}, side_effects={.PAC}}, + // .XPACI + {written={0}, read={0}, side_effects={.PAC}}, + // .XPACD + {written={0}, read={0}, side_effects={.PAC}}, + // .XPACLRI + {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}, + // .RETAA + {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}, + // .RETAB + {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}, + // .BRAA + {read={0, 1}, side_effects={.CONTROL, .PAC}}, + // .BRAB + {read={0, 1}, side_effects={.CONTROL, .PAC}}, + // .BRAAZ + {read={0}, side_effects={.CONTROL, .PAC}}, + // .BRABZ + {read={0}, side_effects={.CONTROL, .PAC}}, + // .BLRAA + {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}, + // .BLRAB + {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}, + // .BLRAAZ + {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}, + // .BLRABZ + {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}, + // .ERETAA + {side_effects={.CONTROL, .PAC, .PRIVILEGED}}, + // .ERETAB + {side_effects={.CONTROL, .PAC, .PRIVILEGED}}, + // .BTI + {side_effects={.BTI}}, + // .IRG + {written={0}, read={1, 2}}, + // .ADDG + {written={0}, read={1}}, + // .SUBG + {written={0}, read={1}}, + // .GMI + {written={0}, read={1, 2}}, + // .SUBP + {written={0}, read={1, 2}}, + // .SUBPS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .LDG + {written={0}, read={1}, reads_mem=true}, + // .STG + {read={0, 1}, writes_mem=true}, + // .ST2G + {read={0, 1}, writes_mem=true}, + // .STZG + {read={0, 1}, writes_mem=true}, + // .STZ2G + {read={0, 1}, writes_mem=true}, + // .STGP + {read={0, 1, 2}, writes_mem=true}, + // .LDGM + {written={0}, read={1}, reads_mem=true}, + // .STGM + {read={0, 1}, writes_mem=true}, + // .STZGM + {read={0, 1}, writes_mem=true}, + // .CRC32B + {written={0}, read={1, 2}}, + // .CRC32H + {written={0}, read={1, 2}}, + // .CRC32W + {written={0}, read={1, 2}}, + // .CRC32X + {written={0}, read={1, 2}}, + // .CRC32CB + {written={0}, read={1, 2}}, + // .CRC32CH + {written={0}, read={1, 2}}, + // .CRC32CW + {written={0}, read={1, 2}}, + // .CRC32CX + {written={0}, read={1, 2}}, + // .AESE + {written={0}, read={0, 1}}, + // .AESD + {written={0}, read={0, 1}}, + // .AESMC + {written={0}, read={0, 1}}, + // .AESIMC + {written={0}, read={0, 1}}, + // .SHA1H + {written={0}, read={1}}, + // .SHA1C + {written={0}, read={0, 1, 2}}, + // .SHA1P + {written={0}, read={0, 1, 2}}, + // .SHA1M + {written={0}, read={0, 1, 2}}, + // .SHA1SU0 + {written={0}, read={0, 1, 2}}, + // .SHA1SU1 + {written={0}, read={0, 1}}, + // .SHA256H + {written={0}, read={0, 1, 2}}, + // .SHA256H2 + {written={0}, read={0, 1, 2}}, + // .SHA256SU0 + {written={0}, read={0, 1}}, + // .SHA256SU1 + {written={0}, read={0, 1, 2}}, + // .SHA512H + {written={0}, read={0, 1, 2}}, + // .SHA512H2 + {written={0}, read={0, 1, 2}}, + // .SHA512SU0 + {written={0}, read={0, 1}}, + // .SHA512SU1 + {written={0}, read={0, 1, 2}}, + // .EOR3 + {written={0}, read={1, 2, 3}}, + // .BCAX + {written={0}, read={1, 2, 3}}, + // .RAX1 + {written={0}, read={1, 2}}, + // .XAR + {written={0}, read={1, 2}}, + // .SM3PARTW1 + {written={0}, read={0, 1, 2}}, + // .SM3PARTW2 + {written={0}, read={0, 1, 2}}, + // .SM3SS1 + {written={0}, read={1, 2, 3}}, + // .SM3TT1A + {written={0}, read={0, 1, 2}}, + // .SM3TT1B + {written={0}, read={0, 1, 2}}, + // .SM3TT2A + {written={0}, read={0, 1, 2}}, + // .SM3TT2B + {written={0}, read={0, 1, 2}}, + // .SM4E + {written={0}, read={0, 1}}, + // .SM4EKEY + {written={0}, read={1, 2}}, + // .PMULL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .PMULL2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .FABS_H + {written={0}, read={1}}, + // .FNEG_H + {written={0}, read={1}}, + // .FSQRT_H + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + // .FADD_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FSUB_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMUL_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FDIV_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMUL_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMADD_H + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMSUB_H + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMADD_H + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNMSUB_H + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCMP_H + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + // .FCMPE_H + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + // .FCSEL_H + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + // .FMAX_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMIN_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXNM_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINNM_H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FCVT_H_S + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVT_H_D + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVT_S_H + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVT_D_H + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMOV_H + {written={0}, read={1}}, + // .SCVTF_H + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .UCVTF_H + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .FCVTZS_H + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTZU_H + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .BFCVT + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFDOT + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFMMLA + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFMLALB + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFMLALT + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFCVTN + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFCVTN2 + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .ADD_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SUB_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .MUL_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .MLA_V + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .MLS_V + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .NEG_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ABS_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SHADD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UHADD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SHSUB + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UHSUB + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SRHADD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .URHADD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SQADD + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .UQADD + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SQSUB + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .UQSUB + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SMAX + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMAX + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SMIN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMIN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SABD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UABD + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SABA + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UABA + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .ADDP_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADDV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SADDLP + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UADDLP + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SADALP + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .UADALP + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .SADDLV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UADDLV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SMAXV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UMAXV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SMINV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UMINV + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SMAXP + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMAXP + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SMINP + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMINP + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SADDL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SADDL2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UADDL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UADDL2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SSUBL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SSUBL2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .USUBL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .USUBL2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SADDW + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SADDW2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UADDW + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UADDW2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SSUBW + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SSUBW2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .USUBW + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .USUBW2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .RADDHN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .RADDHN2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .RSUBHN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .RSUBHN2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADDHN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ADDHN2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SUBHN + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SUBHN2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .XTN + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .XTN2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SQXTN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQXTN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQXTN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQXTN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQXTUN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQXTUN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SMULL_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SMULL2_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMULL_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UMULL2_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SMLAL + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .SMLAL2 + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UMLAL + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UMLAL2 + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .SMLSL + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .SMLSL2 + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UMLSL + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UMLSL2 + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .SQDMULL + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SQDMULL2 + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SQDMLAL + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SQDMLAL2 + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SQDMLSL + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SQDMLSL2 + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SQDMULH + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SQRDMULH + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SDOT + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .UDOT + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .USDOT + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .FADD_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FSUB_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMUL_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FDIV_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FNEG_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FABS_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .FSQRT_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + // .FMLA_V + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMLS_V + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMULX + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMAX_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMIN_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXNM_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINNM_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXP_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINP_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXNMP + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINNMP + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXV_V + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINV_V + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMAXNMV + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FMINNMV + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .FRECPE + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + // .FRSQRTE + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + // .FRECPS + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FRSQRTS + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FRECPX + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + {written={0}, read={1}, reads_fpcr=true}, + // .FADDP_V + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FRINTA_V + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTI_V + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + // .FRINTM_V + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTN_V + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTP_V + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FRINTX_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + // .FRINTZ_V + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .SCVTF_V + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .UCVTF_V + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + // .FCVTAS_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTAU_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTMS_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTMU_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTNS_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTNU_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTPS_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTPU_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTZS_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTZU_V + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTL + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVTL2 + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVTN + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVTN2 + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCVTXN + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCVTXN2 + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + // .FCMEQ + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .FCMGE + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .FCMGT + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .FCMLE + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FCMLT + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + // .FACGE + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .FACGT + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .CMEQ + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .CMGE + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .CMGT + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .CMHI + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .CMHS + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .CMLE + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CMLT + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CMTST + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .AND_V + {written={0}, read={1, 2}}, + // .ORR_V + {written={0}, read={1, 2}}, + // .EOR_V + {written={0}, read={1, 2}}, + // .BIC_V + {written={0}, read={1, 2}}, + // .ORN_V + {written={0}, read={1, 2}}, + // .MVN_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .BIT + {written={0}, read={0, 1, 2}}, + // .BIF + {written={0}, read={0, 1, 2}}, + // .BSL + {written={0}, read={0, 1, 2}}, + // .SHL_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SQSHL_V + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQSHLU + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SRSHL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .URSHL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SSHR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .USHR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SSRA + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .USRA + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .SRSHR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .URSHR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SRSRA + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .URSRA + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .SSHL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .USHL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SLI + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .SRI + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, + // .SSHLL + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SSHLL2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .USHLL + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .USHLL2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SXTL + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SXTL2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UXTL + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .UXTL2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SHRN + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SHRN2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .RSHRN + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .RSHRN2 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SQSHRN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQSHRN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQSHRN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQSHRN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQRSHRN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQRSHRN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQRSHRN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .UQRSHRN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQSHRUN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQSHRUN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQRSHRUN + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .SQRSHRUN2 + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + {written={0}, read={1}, fpsr_wr={.QC}}, + // .DUP_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .INS + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + {written={0}, read={0, 2}}, + // .MOV_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .EXT_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .TBL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .TBX + {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, + // .ZIP1 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .ZIP2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UZP1 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .UZP2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .TRN1 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .TRN2 + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .NOT_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .RBIT_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV16_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV32_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .REV64 + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CLS_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CLZ_V + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .CNT + {written={0}, read={1}}, + {written={0}, read={1}}, + // .URECPE_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .URSQRTE_V + {written={0}, read={1}}, + {written={0}, read={1}}, + // .MOVI + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + // .MVNI + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + // .FMOV_V_IMM + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + // .LD1 + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .LD2 + {written={0}, read={1}, reads_mem=true}, + // .LD3 + {written={0}, read={1}, reads_mem=true}, + // .LD4 + {written={0}, read={1}, reads_mem=true}, + // .ST1 + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .ST2 + {read={0, 1}, writes_mem=true}, + // .ST3 + {read={0, 1}, writes_mem=true}, + // .ST4 + {read={0, 1}, writes_mem=true}, + // .LD1R + {written={0}, read={1}, reads_mem=true}, + // .LD2R + {written={0}, read={1}, reads_mem=true}, + // .LD3R + {written={0}, read={1}, reads_mem=true}, + // .LD4R + {written={0}, read={1}, reads_mem=true}, + // .LD1_LANE + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + // .LD2_LANE + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + // .LD3_LANE + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + // .LD4_LANE + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + // .ST1_LANE + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + // .ST2_LANE + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + // .ST3_LANE + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + // .ST4_LANE + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + // .LDR_V + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .STR_V + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .LDP_V + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + // .STP_V + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .LDUR_V + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + // .STUR_V + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + // .SVE_ADD_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_SUB_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_SQADD_Z + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SVE_UQADD_Z + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SVE_SQSUB_Z + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SVE_UQSUB_Z + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + // .SVE_ADD_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SUB_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SUBR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_MUL_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SMULH_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_UMULH_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SDIV_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_UDIV_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SMAX_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_UMAX_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SMIN_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_UMIN_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_SABD_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_UABD_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_AND_PRED + {written={0}, read={1, 2, 3}}, + // .SVE_ORR_PRED + {written={0}, read={1, 2, 3}}, + // .SVE_EOR_PRED + {written={0}, read={1, 2, 3}}, + // .SVE_BIC_PRED + {written={0}, read={1, 2, 3}}, + // .SVE_ASR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_LSL_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_LSR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_ASRR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_LSLR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_LSRR_PRED + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_ABS_PRED + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_NEG_PRED + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_CLS_PRED + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_CLZ_PRED + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_CNT_PRED + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_MOV_PRED + {read={0, 1, 2}}, + {read={0, 1, 2}}, + {read={0, 1, 2}}, + {read={0, 1, 2}}, + // .SVE_FADD_Z + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FSUB_Z + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMUL_Z + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FRECPS + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FRSQRTS + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FTSMUL + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FADD_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FSUB_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FSUBR_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMUL_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FDIV_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FDIVR_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMAX_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .SVE_FMIN_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .SVE_FMAXNM_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .SVE_FMINNM_PRED + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + // .SVE_FABS_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_FNEG_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_FSQRT_Z + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FRECPX_Z + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + // .SVE_FRINTN + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FRINTP + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FRINTM + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FRINTZ + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FRINTA + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FRINTX + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + // .SVE_FRINTI + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + // .SVE_FMLA + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLS + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FNMLA + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SVE_FNMLS + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SVE_AND_P + {written={0}, read={1, 2, 3}}, + // .SVE_BIC_P + {written={0}, read={1, 2, 3}}, + // .SVE_ORR_P + {written={0}, read={1, 2, 3}}, + // .SVE_EOR_P + {written={0}, read={1, 2, 3}}, + // .SVE_NAND_P + {written={0}, read={1, 2, 3}}, + // .SVE_NOR_P + {written={0}, read={1, 2, 3}}, + // .SVE_ORN_P + {written={0}, read={1, 2, 3}}, + // .SVE_SEL_P + {written={0}, read={1, 2, 3}}, + // .SVE_ANDS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_BICS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_ORRS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_EORS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_NANDS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_NORS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_ORNS_P + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_NOT_P + {written={0}, read={1, 2}}, + // .SVE_MOV_P + {written={0}, read={1, 2}}, + {written={0}, read={1}}, + // .SVE_MOVS_P + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_PTRUE + {written={0}}, + // .SVE_PTRUES + {written={0}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_PFALSE + {written={0}}, + // .SVE_PFIRST + {written={0}, read={1, 2}}, + // .SVE_PNEXT + {written={0}, read={1, 2}}, + // .SVE_BRKA + {written={0}, read={1, 2}}, + // .SVE_BRKB + {written={0}, read={1, 2}}, + // .SVE_BRKAS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_BRKBS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_BRKPA + {written={0}, read={1, 2, 3}}, + // .SVE_BRKPB + {written={0}, read={1, 2, 3}}, + // .SVE_BRKN + {written={0}, read={1, 2, 3}}, + // .SVE_RDFFR + {written={0}, side_effects={.FFR}}, + // .SVE_WRFFR + {read={0}, side_effects={.FFR}}, + // .SVE_SETFFR + {side_effects={.FFR}}, + // .SVE_CMPEQ + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPNE + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPGE + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPGT + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPLE + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPLT + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPHI + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPHS + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPLO + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_CMPLS + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_FCMEQ + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + // .SVE_FCMNE + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + // .SVE_FCMGE + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + // .SVE_FCMGT + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + // .SVE_FCMLE + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FCMLT + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .SVE_FCMUO + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + // .SVE_DUP_Z + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SVE_INSR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SVE_REV_Z + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SVE_REV_P + {written={0}, read={1}}, + // .SVE_TBL + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_ZIP1_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_ZIP2_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_UZP1_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_UZP2_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_TRN1_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_TRN2_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_ZIP1_P + {written={0}, read={1, 2}}, + // .SVE_ZIP2_P + {written={0}, read={1, 2}}, + // .SVE_UZP1_P + {written={0}, read={1, 2}}, + // .SVE_UZP2_P + {written={0}, read={1, 2}}, + // .SVE_TRN1_P + {written={0}, read={1, 2}}, + // .SVE_TRN2_P + {written={0}, read={1, 2}}, + // .SVE_CPY_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_COMPACT + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_EXT_Z + {written={0}, read={1, 2}}, + // .SVE_LD1B + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1H + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1W + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SB + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SH + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SW + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_ST1B + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1H + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1W + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1D + {read={0, 1, 2}, writes_mem=true}, + // .SVE_LDR_Z + {written={0}, read={1}, reads_mem=true}, + // .SVE_STR_Z + {read={0, 1}, writes_mem=true}, + // .SVE_LDR_P + {written={0}, read={1}, reads_mem=true}, + // .SVE_STR_P + {read={0, 1}, writes_mem=true}, + // .SVE_LDFF1B + {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, + // .SVE_LDFF1H + {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, + // .SVE_LDFF1W + {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, + // .SVE_LDFF1D + {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, + // .SVE_WHILEGE + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILEGT + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILELE + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILELT + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILEHI + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILEHS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILELO + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_WHILELS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_SQRDMLAH + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SVE_SQRDMLSH + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, + // .SVE_ADCLB + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_ADCLT + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_SBCLB + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_SBCLT + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_TBL2 + {written={0}, read={1, 2}}, + // .SVE_TBX + {written={0}, read={0, 1, 2}}, + // .SVE_AESE + {written={0}, read={0, 1}}, + // .SVE_AESD + {written={0}, read={0, 1}}, + // .SVE_AESMC + {written={0}, read={0}}, + // .SVE_AESIMC + {written={0}, read={0}}, + // .SVE_BCAX_Z + {written={0}, read={1, 2, 3}}, + // .SVE_XAR_Z + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .SVE_EOR3_Z + {written={0}, read={1, 2, 3}}, + // .SVE_MATCH + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_NMATCH + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .SVE_HISTCNT + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SVE_HISTSEG + {written={0}, read={1, 2}}, + // .SME_SMSTART + {}, + // .SME_SMSTOP + {}, + // .SME_RDSVL + {written={0}}, + // .SME_ADDHA + {written={0}, read={0, 1, 2, 3}}, + // .SME_ADDVA + {written={0}, read={0, 1, 2, 3}}, + // .SME_ZERO + {}, + // .SME_FMOPA + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SME_FMOPS + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SME_BFMOPA + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SME_BFMOPS + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SME_SMOPA + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SME_SMOPS + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SME_UMOPA + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SME_UMOPS + {written={0}, read={0, 1, 2, 3}}, + {written={0}, read={0, 1, 2, 3}}, + // .SME_USMOPA + {written={0}, read={0, 1, 2, 3}}, + // .SME_SUMOPA + {written={0}, read={0, 1, 2, 3}}, + // .SME_LDR_ZA + {read={1}, reads_mem=true}, + // .SME_STR_ZA + {read={1}, writes_mem=true}, + // .SVE_FMLA_IDX_H + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLA_IDX_S + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLA_IDX_D + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLS_IDX_H + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLS_IDX_S + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_FMLS_IDX_D + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_LD1B_GATHER_S + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1B_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1H_GATHER_S + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1H_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1W_GATHER_S + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1W_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1D_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SB_GATHER_S + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SB_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SH_GATHER_S + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SH_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LD1SW_GATHER_D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_ST1B_SCATTER_S + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1B_SCATTER_D + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1H_SCATTER_S + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1H_SCATTER_D + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1W_SCATTER_S + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1W_SCATTER_D + {read={0, 1, 2}, writes_mem=true}, + // .SVE_ST1D_SCATTER_D + {read={0, 1, 2}, writes_mem=true}, + // .SME_LD1B_TILE + {written={0}, read={1, 2}, reads_mem=true}, + // .SME_LD1H_TILE + {written={0}, read={1, 2}, reads_mem=true}, + // .SME_LD1W_TILE + {written={0}, read={1, 2}, reads_mem=true}, + // .SME_LD1D_TILE + {written={0}, read={1, 2}, reads_mem=true}, + // .SME_LD1Q_TILE + {written={0}, read={1, 2}, reads_mem=true}, + // .SME_ST1B_TILE + {read={0, 1, 2}, writes_mem=true}, + // .SME_ST1H_TILE + {read={0, 1, 2}, writes_mem=true}, + // .SME_ST1W_TILE + {read={0, 1, 2}, writes_mem=true}, + // .SME_ST1D_TILE + {read={0, 1, 2}, writes_mem=true}, + // .SME_ST1Q_TILE + {read={0, 1, 2}, writes_mem=true}, + // .SME_MOVA_Z_FROM_TILE + {written={0}, read={1, 2}}, + // .SME_MOVA_TILE_FROM_Z + {written={0}, read={1, 2}}, + // .FCMLA_4H + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCMLA_8H + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCMLA_4S + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCMLA_2D + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCADD_4H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCADD_8H + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCADD_4S + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FCADD_2D + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_PRFB + {read={1, 2}, side_effects={.HINT}}, + // .SVE_PRFH + {read={1, 2}, side_effects={.HINT}}, + // .SVE_PRFW + {read={1, 2}, side_effects={.HINT}}, + // .SVE_PRFD + {read={1, 2}, side_effects={.HINT}}, + // .SVE_LDNT1B + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LDNT1H + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LDNT1W + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_LDNT1D + {written={0}, read={1, 2}, reads_mem=true}, + // .SVE_STNT1B + {read={0, 1, 2}, writes_mem=true}, + // .SVE_STNT1H + {read={0, 1, 2}, writes_mem=true}, + // .SVE_STNT1W + {read={0, 1, 2}, writes_mem=true}, + // .SVE_STNT1D + {read={0, 1, 2}, writes_mem=true}, + // .SVE_EXT + {written={0}, read={1, 2}}, + // .SVE_SPLICE + {written={0}, read={1, 2, 3}}, + // .SVE_INDEX_II + {written={0}}, + // .SVE_INDEX_IR + {written={0}, read={2}}, + // .SVE_INDEX_RI + {written={0}, read={1}}, + // .SVE_INDEX_RR + {written={0}, read={1, 2}}, + // .SVE_BSL + {written={0}, read={0, 1, 2, 3}}, + // .SVE_BSL1N + {written={0}, read={1, 2, 3}}, + // .SVE_BSL2N + {written={0}, read={1, 2, 3}}, + // .SVE_NBSL + {written={0}, read={1, 2, 3}}, + // .SVE_PMUL_VEC + {written={0}, read={1, 2}}, + // .SVE_PMULLB + {written={0}, read={1, 2}}, + // .SVE_PMULLT + {written={0}, read={1, 2}}, + // .SVE_BFCVT + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFCVTNT + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .LDRAA + {written={0}, read={1}, reads_mem=true}, + // .LDRAB + {written={0}, read={1}, reads_mem=true}, + // .LDRAA_PRE + {written={0, 1}, read={1}, reads_mem=true}, + // .LDRAB_PRE + {written={0, 1}, read={1}, reads_mem=true}, + // .TSTART + {written={0}, side_effects={.NONDETERMINISTIC}}, + // .TCOMMIT + {}, + // .TCANCEL + {side_effects={.CONTROL}}, + // .TTEST + {written={0}}, + // .WFET + {read={0}, side_effects={.WAIT}}, + // .WFIT + {read={0}, side_effects={.WAIT}}, + // .BC_COND + {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}, + // .UXTB + {written={0}, read={1}}, + // .UXTH + {written={0}, read={1}}, + // .UXTW + {written={0}, read={1}}, + // .SXTB + {written={0}, read={1}}, + // .SXTH + {written={0}, read={1}}, + // .SXTW + {written={0}, read={1}}, + // .ADC + {written={0}, read={1, 2}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_rd={.C}}, + // .ADCS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + // .SBC + {written={0}, read={1, 2}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_rd={.C}}, + // .SBCS + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + // .NGC + {written={0}, read={1}, nzcv_rd={.C}}, + {written={0}, read={1}, nzcv_rd={.C}}, + // .NGCS + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}, + // .LDAPUR + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLUR + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDAPURB + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLURB + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDAPURH + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .STLURH + {read={0, 1}, writes_mem=true, side_effects={.FENCE}}, + // .LDAPURSB + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .LDAPURSH + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .LDAPURSW + {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, + // .SVE_BFADD + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFSUB + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFMUL + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFMLA + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFMLS + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SB + {side_effects={.FENCE}}, + // .CSDB + {side_effects={.FENCE}}, + // .DGH + {side_effects={.HINT}}, + // .PSB_CSYNC + {side_effects={.HINT}}, + // .TSB_CSYNC + {side_effects={.HINT}}, + // .BTI_J + {side_effects={.BTI}}, + // .BTI_C + {side_effects={.BTI}}, + // .BTI_JC + {side_effects={.BTI}}, + // .MOV_V_ALIAS + {written={0}, read={1}}, + {written={0}, read={1}}, + // .NOT_V_ALIAS + {written={0}, read={1}}, + {written={0}, read={1}}, + // .LSL_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .LSR_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ASR_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ROR_IMM + {written={0}, read={1}}, + {written={0}, read={1}}, + // .SVE_BFADD_UNPRED + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFSUB_UNPRED + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFMUL_UNPRED + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .SVE_BFCLAMP + {written={0}, read={1, 2}}, + // .SVE_BFMAXNM + {written={0}, read={1, 2, 3}}, + // .SVE_BFMINNM + {written={0}, read={1, 2, 3}}, + // .SME2_LUTI2_B + {written={0}, read={1}}, + // .SME2_LUTI4_B + {written={0}, read={1}}, + // .SME2_LD1B_X2 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1H_X2 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1W_X2 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1D_X2 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1B_X4 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1H_X4 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1W_X4 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_LD1D_X4 + {written={0}, read={1, 2}, reads_mem=true}, + // .SME2_ST1B_X2 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1H_X2 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1W_X2 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1D_X2 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1B_X4 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1H_X4 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1W_X4 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ST1D_X4 + {read={0, 1, 2}, writes_mem=true}, + // .SME2_ZIP_3 + {written={0}, read={1, 2}}, + // .SME2_ZIP_4 + {written={0}, read={1, 2}}, + // .SME2_UZP_3 + {written={0}, read={1, 2}}, + // .SME2_UZP_4 + {written={0}, read={1, 2}}, + // .TLBI_RPALOS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_RPAOS + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E1A + {read={0}, side_effects={.PRIVILEGED}}, + // .DC_CIPAPA + {read={0}, side_effects={.CACHE}}, + // .DC_CIGDPAPA + {read={0}, side_effects={.CACHE}}, + // .TLBI_PAALL + {side_effects={.PRIVILEGED}}, + // .TLBI_PAALLOS + {side_effects={.PRIVILEGED}}, + // .AMX_LDX + {read={0}}, + // .AMX_LDY + {read={0}}, + // .AMX_STX + {read={0}}, + // .AMX_STY + {read={0}}, + // .AMX_LDZ + {read={0}}, + // .AMX_STZ + {read={0}}, + // .AMX_LDZI + {read={0}}, + // .AMX_STZI + {read={0}}, + // .AMX_EXTRX + {read={0}}, + // .AMX_EXTRY + {read={0}}, + // .AMX_FMA64 + {read={0}}, + // .AMX_FMS64 + {read={0}}, + // .AMX_FMA32 + {read={0}}, + // .AMX_FMS32 + {read={0}}, + // .AMX_MAC16 + {read={0}}, + // .AMX_FMA16 + {read={0}}, + // .AMX_FMS16 + {read={0}}, + // .AMX_SET + {}, + // .AMX_CLR + {}, + // .AMX_VECINT + {read={0}}, + // .AMX_VECFP + {read={0}}, + // .AMX_MATINT + {read={0}}, + // .AMX_MATFP + {read={0}}, + // .AMX_GENLUT + {read={0}}, + // .CPYP + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .CPYM + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .CPYE + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .CPYFP + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .CPYFM + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .CPYFE + {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}, + // .SETP + {written={0, 1}, read={0, 1, 2}, writes_mem=true}, + // .SETM + {written={0, 1}, read={0, 1, 2}, writes_mem=true}, + // .SETE + {written={0, 1}, read={0, 1, 2}, writes_mem=true}, + // .DC_IVAC + {read={0}, side_effects={.CACHE, .PRIVILEGED}}, + // .DC_ISW + {read={0}, side_effects={.CACHE, .PRIVILEGED}}, + // .DC_CSW + {read={0}, side_effects={.CACHE, .PRIVILEGED}}, + // .DC_CISW + {read={0}, side_effects={.CACHE, .PRIVILEGED}}, + // .DC_ZVA + {read={0}, writes_mem=true, side_effects={.CACHE}}, + // .DC_CVAC + {read={0}, side_effects={.CACHE}}, + // .DC_CVAU + {read={0}, side_effects={.CACHE}}, + // .DC_CIVAC + {read={0}, side_effects={.CACHE}}, + // .IC_IALLUIS + {side_effects={.CACHE, .PRIVILEGED}}, + // .IC_IALLU + {side_effects={.CACHE, .PRIVILEGED}}, + // .IC_IVAU + {read={0}, side_effects={.CACHE}}, + // .AT_S1E1R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E1W + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E0R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E0W + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E2R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E2W + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E3R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S1E3W + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S12E1R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S12E1W + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S12E0R + {read={0}, side_effects={.PRIVILEGED}}, + // .AT_S12E0W + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VMALLE1 + {side_effects={.PRIVILEGED}}, + // .TLBI_VMALLE1IS + {side_effects={.PRIVILEGED}}, + // .TLBI_VAE1 + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VAE1IS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_ASIDE1 + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_ASIDE1IS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VAAE1 + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VAAE1IS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VALE1 + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VALE1IS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VAALE1 + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_VAALE1IS + {read={0}, side_effects={.PRIVILEGED}}, + // .TLBI_ALLE1 + {side_effects={.PRIVILEGED}}, + // .TLBI_ALLE1IS + {side_effects={.PRIVILEGED}}, + // .TLBI_ALLE2 + {side_effects={.PRIVILEGED}}, + // .TLBI_ALLE2IS + {side_effects={.PRIVILEGED}}, + // .TLBI_ALLE3 + {side_effects={.PRIVILEGED}}, + // .TLBI_ALLE3IS + {side_effects={.PRIVILEGED}}, + // .PRFM + {read={1}, side_effects={.HINT}}, + // .PRFUM + {read={1}, side_effects={.HINT}}, + // .PRFM_LIT + {side_effects={.HINT}}, + // .MOV_REG + {written={0}, read={1}}, + {written={0}, read={1}}, + // .MOV_BITMASK + {written={0}}, + {written={0}}, + // .MVN + {written={0}, read={1}}, + {written={0}, read={1}}, + // .NEG_SR + {written={0}, read={1}}, + {written={0}, read={1}}, + // .NEGS + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMP_SR + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMP_ER + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMP_IMM + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMN_SR + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMN_ER + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + // .CMN_IMM + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + // .TST_SR + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, +} + @(rodata) ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .INVALID = { 0, 0}, diff --git a/core/rexcode/isa/arm64/tablegen/generated/writer.odin b/core/rexcode/isa/arm64/tablegen/generated/writer.odin index d47ce43ad..da79253fd 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/writer.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/writer.odin @@ -23,6 +23,7 @@ w :: proc(file: string, data: []u8) { main :: proc() { w(TABLES + "arm64.encode_forms.bin", raw(&ENCODE_FORMS, size_of(ENCODE_FORMS))) + w(TABLES + "arm64.clobber_forms.bin", raw(&CLOBBER_FORMS, size_of(CLOBBER_FORMS))) w(TABLES + "arm64.encode_runs.bin", raw(&ENCODE_RUNS, size_of(ENCODE_RUNS))) w(TABLES + "arm64.entries.bin", raw(&DECODE_ENTRIES, size_of(DECODE_ENTRIES))) w(TABLES + "arm64.idx_op0.bin", raw(&DECODE_INDEX_OP0, size_of(DECODE_INDEX_OP0))) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index c0556eb21..4f5707b05 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -1,5 +1,91 @@ package rexcode_arm64_tablegen +// ============================================================================= +// rexcode ยท AArch64 INSTRUCTION_TABLE (v1: base integer + FP scalar) +// ============================================================================= +// +// One []Form per Mnemonic. A Form fuses an instruction form's Encoding with its +// Clobber, so INSTRUCTION_TABLE[m][i] carries both the bit pattern and the +// read/write + side-effect summary for form i of mnemonic m. This replaces the +// old pair of index-aligned tables (ENCODING_TABLE[m][i] / CLOBBER_TABLE[m][i]); +// co-locating the two in one struct removes the alignment invariant, so a form's +// encoding and clobber can no longer drift out of sync. +// +// +// --- Encoding: (bits, mask) model -------------------------------------------- +// +// Same shape as MIPS/RISC-V. `bits` carries the static opcode pattern; `mask` +// covers exactly the bits that are fixed by the form. Operand-driven fields +// (Rd/Rn/Rm/imm*/sh/cond/...) land in zero positions of `bits` and are ORed in +// by the encoder. +// +// Sections (each follows the ARM ARM "C4.1.x Data-processing /" division): +// ยง1 Data-processing -- immediate (Add/Sub imm, Mov-wide, PC-rel) +// ยง2 Data-processing -- shifted reg (Add/Sub/AND/ORR/EOR/BIC/ORN/EON) +// ยง3 Data-processing -- extended reg (Add/Sub extended) +// ยง4 Data-processing -- 2-source (LSLV/LSRV/ASRV/RORV, UDIV/SDIV) +// ยง5 Data-processing -- 3-source (MADD/MSUB/SMADDL/.../UMULH) +// ยง6 Data-processing -- 1-source (CLZ/CLS/RBIT/REV/REV16/REV32) +// ยง7 Conditional (CSEL/CSINC/CSINV/CSNEG) +// ยง8 Branches (B/BL/BR/BLR/RET, B.cond, CBZ, TBZ) +// ยง9 Loads / stores (LDR/STR families, LDP/STP, LDUR) +// ยง10 System (NOP/HINT/ISB/MSR/MRS/SVC/...) +// ยง11 FP scalar (FMOV/FADD/FCVT/FCMP/FCSEL/...) +// +// Logical-immediate forms (AND/ORR/EOR/ANDS imm) use the bitmask-immediate +// encoding (N:imms:immr); they're deferred to a follow-up turn that adds the +// bitmask encoder helper. +// +// +// --- Clobber: read/write + side-effect summary ------------------------------- +// +// One Clobber per Form -- a read/write + side-effect summary for every form of +// every mnemonic. Derivation (from each form's operand TYPES, operand ROLES, +// and Encoding_Flags): +// +// written / read -- operand slots (0..3) whose register / memory base is a +// def / use. A slot counts only if its TYPE is register- +// or memory-like; immediate slots never appear. Direction +// comes from the ROLE, refined by instruction class: +// * RD/VD/PD/RT/RT2/ZA_TILE* are destinations, EXCEPT +// the data operand of a store (RT/VD on ST*), which is +// a source; and the status result of STXR/STXP (RD), +// which stays a def while RT/RT2 become sources. +// * A pre/post-index base (OFFSET_BASE_PRE/POST) is both +// read and written (address write-back). +// * A destination register re-listed as a later source +// slot (SVE destructive Zdn, accumulate) is read. +// * Branches define no GPR operand; targets/modifiers +// are reads. +// implicit_wr/rd -- LR on BL/BLR/RET, LR+SP on PAC*SP / RETAA, X16/X17 on +// PAC*1716, etc. +// nzcv_wr -- set for sets_flags forms (ADDS/SUBS/ANDS/CMP/CCMP/FCMP, +// SVE compares, WHILE*, PTRUES, ...). +// nzcv_rd -- any COND operand (CSEL/FCSEL/B.cond/CCMP), plus the +// carry readers ADC/ADCS/SBC/SBCS/NGC/NGCS; CCMP/CCMN both. +// fpsr_wr/reads_fpcr -- per FP-op family (see notes); saturating integer ops +// (SQ*/UQ*/SUQ*/USQ*/SQRDML*) set QC. +// reads_mem/writes_mem -- loads / stores / RMW atomics / MOPS. +// side_effects -- control flow, barriers, atomics, cache/TLB, PAC, BTI, +// wait, privileged system access, FFR, etc. +// +// Heuristic / best-effort fields (structurally faithful, semantically approximate): +// * FPSR exception-bit sets and reads_fpcr are assigned per mnemonic family, +// not per-corner-case; treat them as "flags this class may raise". +// * Accumulate detection (destination is read-modified) is name-driven for +// the families that fold the accumulator into the destination (MLA/MLS/DOT/ +// FMLA/FCMLA/SQRDML*/MOPA, shift-accumulate, bit-insert, AES/SHA/SM3/SM4, +// PAC in-place). Multiply-adds with a separate Ra/Va operand (MADD/FMADD/...) +// are correctly NOT dest-reads. +// * LD1-4/ST1-4 register lists occupy a single operand slot, so max operand +// count stays at 4 (matches Operand_Set / the encoder's model). +// * Acquire/release accesses carry the FENCE side effect to model their +// one-way ordering (distinct from the register/memory read/write sets). +// * Requires the companion clobber_types.odin (adds X16/X17 to Clobber_Reg +// and FFR to Side_Effect). +// ============================================================================= + + Form :: struct { using encoding: Encoding, clobber: Clobber, diff --git a/core/rexcode/isa/arm64/tables.odin b/core/rexcode/isa/arm64/tables.odin index b7bf2baff..1f19e6ed1 100644 --- a/core/rexcode/isa/arm64/tables.odin +++ b/core/rexcode/isa/arm64/tables.odin @@ -44,10 +44,11 @@ Decode_Index :: struct #packed { // Loaded tables (rodata, embedded from tables/*.bin at compile time) // ----------------------------------------------------------------------------- -@(rodata) ENCODE_FORMS := #load("tables/arm64.encode_forms.bin", []Encoding) -@(rodata) ENCODE_RUNS := #load("tables/arm64.encode_runs.bin", []Encode_Run) -@(rodata) DECODE_ENTRIES := #load("tables/arm64.entries.bin", []Decode_Entry) -@(rodata) DECODE_INDEX_OP0 := #load("tables/arm64.idx_op0.bin", []Decode_Index) +@(rodata) ENCODE_FORMS := #load("tables/arm64.encode_forms.bin", []Encoding) +@(rodata) CLOBBER_FORMS := #load("tables/arm64.clobber_forms.bin", []Clobber) +@(rodata) ENCODE_RUNS := #load("tables/arm64.encode_runs.bin", []Encode_Run) +@(rodata) DECODE_ENTRIES := #load("tables/arm64.entries.bin", []Decode_Entry) +@(rodata) DECODE_INDEX_OP0 := #load("tables/arm64.idx_op0.bin", []Decode_Index) // ----------------------------------------------------------------------------- // Accessors diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin new file mode 100644 index 0000000000000000000000000000000000000000..744c8483bf551557e82b6910f92511eb2ede5f1c GIT binary patch literal 34160 zcmeI5O?KNj49BH7Gs$A!G<|OlknXze0p?APl4XyPqYp?BB>t2P!whB14z+0g3rKts zq)6Fu=7&jL^Mbx*X^|p2ee|k8csUnb$W&Wt#qlj#ikNLRQmLh&04d}%UaT9)YKbz7(1O(xWrxS)SxhX_ z^aNf5VM~=V>QYg@Q_j;fpv!A(}&ya%9a1=!o=NeRWHR+bWp&y+svfp#$LS}?`ViXl>+I97Rm%xKWmgi0=5h8D-81s_NJ~JuZ1P*cmVOJ+a+*|3v=8vp z^Ith6>gT0gk)gAh3G$_Q8g?i--nphMp+1kLU8JHT$dC>NLq8y8JoE!u4xB9fqoAVc zA@2)fqjK*LSdr`?xaES%IiU25K1uBCpr7(Ofxev5Sw*z)GrE5yh9;Rr#5(rZq!6Y@OLO<{eZ z*(eJF(Ax9Xh9|5XyLfgk#cIjxi}e)Mdd?@-xhBph%WHp4?6;+Vu3Wd}+C0Jv*+1>K z3WjG=J=g+Fo^X*_n(RD-nsnNw_AIp%J1PW>W=|;_xmM(M5E=k zDtY_4IV{N7j!cY9-2blRYgPGncdj>{Ea`djSD{;}9{=ulw3Jof$^?(QRJos6r}W#N z{GRn`Y2~a{#-7PDf&=b1ld_9Nh1G;t`X~`>E#`{ouDo((}4OvLhRr zs58M;E_vBIrMLX#{r6PmX@*~ndd^f?Ct7v-V{f&9{n%c5=QWK(Gr@?>t;7rcXMNd` z7V9(eep&OVKqjpBt}iXK-YXw6`83nW#2zyt>pZWY+tYd#@LDb_!#z;f`w^^sk|n=| z{pFJbl0DxbI}<$8lBL@uu0e@mzhq_C|IEYE(o^=v3BA$hwEL|Bzh^y1Q)b7db?*0F ze7|Rx&e<0B{L${WrGMt^x8;7b>-TJn`W!m1wL+hp`P<$XaI_-^d0ybp#I4llx}Wm< z=utXvPu8qzy*pWFgjSuSpVZ69gk-|1-66Z}EG6&xzx23IBDx1zuFnvgyl2Y4Hra>r z?|F0bWY^r0n*9vFpB}Fm``ytbcWut~-BI(nL(TW8PyPKw^c4tDOGwtYBcaS6pFf6+ ze=h*<65i50yFbF;(;vhGUA~ix*VmDkk(W^usRn3w<)07ZlqE9$ED-I{z#oh?`-pP)^?@bN)>0b-C(Oxy#> zXD2y!i{!JY+;W}x>%e5j^(0vp%NLH(Pv%zQ`5-zkLdDf^H|$QSb~z-e-9-8P7dXh2 zb#9XW4F!EvW?48PQ##SQKl9qp*ZeJ4;is=!G`((;-7Q9J=u885{ShNaWG&~4+#~TE z6VLjPKU!QvZiP;)OJ(J#R?N{)=H|#mS{zD+gelmE^2v>7wVdis5@MR>ym1kxZ%N&fa$bVPl9vmSjC(Mrzv*~MTp6()wM62zTx6{gp%x-F zwr5dtB*cI^!L!n8`3k}__xjj3oeEk{AxT;D*`g$jG_`7(@*Os2K`26+4-y|&&u1x* zN-$Aoz}~2J#q{^<6T9D@)w1{!in5~Cap#eidU4Z~D|iVKSMt8uLU6mdA{EAtHq014nHE% z9iKs%{wO4;gZgF9Lf1|d^CCmT! zf#RX24;`}3;Ic(}G(TW$okThKsH;ciWg!a=rHd@6tFi|=C-7`%q+%e?^tCUq(X&3J rSLnH%+(@~qfk4&jt^3tYwP&BY Date: Wed, 26 Aug 2026 14:18:13 +0100 Subject: [PATCH 06/89] Remove unneeded comments --- core/rexcode/isa/arm64/clobber_types.odin | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/core/rexcode/isa/arm64/clobber_types.odin b/core/rexcode/isa/arm64/clobber_types.odin index f678381e2..406094291 100644 --- a/core/rexcode/isa/arm64/clobber_types.odin +++ b/core/rexcode/isa/arm64/clobber_types.odin @@ -1,15 +1,7 @@ package rexcode_arm64 -// Operand slots (indices into the Encoding operand list) that are read/written. -// Max 4 operands (R4-style FMA: FMADD rd, rn, rm, ra). Register lists on the -// LD1-4/ST1-4 structure forms count as a single operand slot. Operand_Set :: distinct bit_set[0..<4; u8] -// The NZCV condition flags โ€” the ONLY application-visible flag state in AArch64. -// There is no parity/aux-carry/direction flag as on x86. The other PSTATE bits -// (DAIF interrupt masks, PAN, UAO, SSBS, SP-select, ...) are system state -// reached only through MSR/MRS, and are modelled via the PRIVILEGED side effect -// rather than here. NZCV_Flags :: distinct bit_set[NZCV_Flag; u8] NZCV_Flag :: enum u8 { N, // negative result @@ -18,9 +10,6 @@ NZCV_Flag :: enum u8 { V, // signed overflow } -// FPSR cumulative exception + saturation flags โ€” the AArch64 analogue of RISC-V -// fflags / x86 MXCSR status. The rounding mode lives separately in FPCR (see -// reads_fpcr below), so there is no EFLAGS-style triad for FP either. FPSR_Flags :: distinct bit_set[FPSR_Flag; u8] FPSR_Flag :: enum u8 { IOC, // invalid operation @@ -32,13 +21,6 @@ FPSR_Flag :: enum u8 { QC, // cumulative saturation (Advanced SIMD saturating ops) } -// Implicitly-touched GPRs that are NOT distinct operands. Like RISC-V, AArch64 -// has very few of these: the SIMD/FP register file is always addressed through -// explicit operands, so there is no x86-style VECTOR/XMM0 implicit clobber. -// -// X16/X17 are here for the pointer-authentication *1716 hint forms -// (PACIA1716/AUTIA1716/...), which implicitly read X16 (modifier) and -// read-modify-write X17 (the pointer) without naming either as an operand. Clobber_Regs :: distinct bit_set[Clobber_Reg; u8] Clobber_Reg :: enum u8 { LR, // x30, implicit link written by BL/BLR, implicitly read by RET From f4bd6d74f42fd1f76c5fa871c63f8aaaa1257c06 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Wed, 26 Aug 2026 17:51:36 -0400 Subject: [PATCH 07/89] rexcode/arm64: mnemonics are assembler mnemonics, not per-encoding names The Mnemonic enum had one member per encoding form -- ADD_IMM, ADD_SR, ADD_ER, ADD_V for what an assembler just calls ADD; LDR, LDR_LIT, LDR_PRE, LDR_POST, LDR_REG, LDR_V for LDR; SVE_ADD_Z / SVE_ADD_PRED / SVE_AND_P for names SVE spells ADD and AND. The encoder never needed that: like x86, it already resolves a mnemonic by scanning its run of forms and matching operand types, so the split bought nothing and cost a printer that had to strip suffixes back off at runtime -- incompletely, so ADD_V printed "add.v", LDR_PRE "ldr.pre" and FCVT_H_S "fcvt.h.s". Collapse the enum to the names assemblers accept: 1104 -> 785 mnemonics, with the variants becoming forms under one name (ADD now has 13, LDR 15). LSLV/LSRV/ASRV/RORV fold into LSL/LSR/ASR/ROR. Form order within a run is precedence, and the original declaration order is already the order an assembler resolves: "add w0,w1,w2" takes the shifted-register form, and only the extended form can encode SP. This needed one structural change. The matcher was blind to addressing mode -- `case .MEM: return op.kind == .MEMORY` -- which is precisely why LDR/LDR_PRE/LDR_POST/LDR_REG had to be separate mnemonics; all 20 merge collisions were this and nothing else. Split Operand_Type.MEM into mode-specific types (MEM_OFFSET/PRE/POST/REG/EXT plus four SVE), matching how W_REG/W_SHIFTED/W_EXTENDED are already distinct types over one register class. The decoder derives Address_Mode from `enc`, so it is unaffected. Encodings are unchanged: the multiset of (ops, enc, bits, mask, feature, flags) over all forms is identical before and after except for two entries deliberately dropped. NOT_V_ALIAS duplicated NOT_V byte for byte, and MOV_V_ALIAS was wrong -- it encoded VN where the ORR-based MOV alias needs VN_VM_DUP, so "mov v1.8b, v2.8b" would have emitted "orr v1.8b, v2.8b, v0.8b". AMX_* keeps its prefix: Apple's coprocessor is undocumented with no assembler spelling, so there is no canonical name to collapse to and bare "set"/"clr"/"ldx" would mislead. The two-token system instructions keep theirs too and print with a space (dc zva, tlbi vae1, bti j). Verified: all 11 rexcode suites match HEAD exactly (arm64 461/461); the three generator stages round-trip idempotently; 754 of 785 mnemonics are accepted by llvm-mc, the rest being AMX (24), TME (4, no +tme in this LLVM build), B_COND/BC_COND and TBL2; and a 39-case encode/print differential against llvm-mc matches 34, with the 5 others confirmed byte-identical at HEAD (pre-existing LSR/ASR immediate and LDP pre-index packing bugs, and printer gaps for vector arrangements and MOVZ/MOVK shifts). Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm64/encoder.odin | 26 +- core/rexcode/isa/arm64/encoding_types.odin | 22 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 7930 ++++++++--------- core/rexcode/isa/arm64/mnemonics.odin | 382 +- core/rexcode/isa/arm64/printer.odin | 49 +- .../tablegen/generated/decode_tables.odin | 3256 ++++--- .../tablegen/generated/encode_tables.odin | 7246 +++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 6933 +++++++------- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 34160 -> 34104 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 48800 -> 48720 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 8832 -> 6288 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 48840 -> 48760 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes .../isa/arm64/tests/pipeline_smoke.odin | 66 +- core/rexcode/isa/arm64/tests/smoke.odin | 318 +- .../arm64/tools/gen_mnemonic_builders.odin | 67 +- 16 files changed, 11850 insertions(+), 14445 deletions(-) diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index ae83b443d..b8de703d7 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -283,8 +283,30 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .IMMEDIATE && is_valid_bitmask_imm(u64(op.immediate), form.flags.is_64) case .REL_26, .REL_19, .REL_14, .REL_PG21: return op.kind == .RELATIVE - case .MEM: - return op.kind == .MEMORY + // Memory: the addressing mode is what selects between the forms of one + // mnemonic (LDR [Xn,#i] / [Xn,#i]! / [Xn],#i / [Xn,Xm]), so it has to + // be matched, not just packed. + case .MEM_OFFSET: + return op.kind == .MEMORY && op.mem.mode == .OFFSET + case .MEM_PRE: + return op.kind == .MEMORY && op.mem.mode == .PRE_INDEXED + case .MEM_POST: + return op.kind == .MEMORY && op.mem.mode == .POST_INDEXED + case .MEM_REG: + return op.kind == .MEMORY && op.mem.mode == .REG_OFFSET + case .MEM_EXT: + return op.kind == .MEMORY && op.mem.mode == .EXT_REG_OFFSET + // SVE: the plain mode is not enough -- a gather's scalar+scalar and + // scalar+vector forms are both REG_OFFSET and differ only in whether + // the index (or base) is a Z register. + case .MEM_SVE_SS: + return op.kind == .MEMORY && op.mem.mode == .REG_OFFSET && reg_class(op.mem.index) != REG_Z + case .MEM_SVE_SI: + return op.kind == .MEMORY && op.mem.mode == .OFFSET && reg_class(op.mem.base) != REG_Z + case .MEM_SVE_VEC: + return op.kind == .MEMORY && op.mem.mode == .REG_OFFSET && reg_class(op.mem.index) == REG_Z + case .MEM_SVE_VB: + return op.kind == .MEMORY && op.mem.mode == .OFFSET && reg_class(op.mem.base) == REG_Z case .COND: return op.kind == .COND } diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index e2c4a29ec..2b8c2775d 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -162,7 +162,27 @@ Operand_Type :: enum u8 { REL_PG21, // ADR / ADRP (signed 21-bit; ADRP scales by 4096) // ---- Memory ---- - MEM, // memory operand with addressing mode + // + // One operand type per addressing mode. The mode has to be part of the + // operand TYPE, not just the operand encoding, because it is a matching + // criterion: `LDR Xt, [Xn, #imm]`, `[Xn, #imm]!`, `[Xn], #imm` and + // `[Xn, Xm]` are all the mnemonic LDR, and the matcher picks between + // their forms on the addressing mode alone. (Same reason W_REG / + // W_SHIFTED / W_EXTENDED are distinct types over one register class.) + // Each maps to exactly one Address_Mode; the form's Operand_Encoding + // then says how the fields are packed. + MEM_OFFSET, // [Xn{, #imm}] -> Address_Mode.OFFSET + MEM_PRE, // [Xn, #imm]! -> PRE_INDEXED + MEM_POST, // [Xn], #imm -> POST_INDEXED + MEM_REG, // [Xn, Rm{, LSL #s}] -> REG_OFFSET + MEM_EXT, // [Xn, Wm, SXTW|UXTW|SXTX #s] -> EXT_REG_OFFSET + // SVE addressing. Kept distinct from the plain modes above: a gather + // load has both a scalar+scalar and a scalar+vector form under the one + // mnemonic, and those two differ only in the index register's class. + MEM_SVE_SS, // [Xn, Xm, LSL #s] -> REG_OFFSET, X index + MEM_SVE_SI, // [Xn, #imm, MUL VL] -> OFFSET + MEM_SVE_VEC, // [Xn, Zm.S/D, UXTW|SXTW|LSL #s] -> REG_OFFSET, Z index + MEM_SVE_VB, // [Zn.S/D, #imm5] -> OFFSET, Z base // ---- Condition code ---- COND, diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 7319f54bb..ee731a3be 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -21,4454 +21,3492 @@ package rexcode_arm64 // Individual Typed Builder Procedures // ============================================================================= -inst_add_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD_IMM, dst, src, imm) } -emit_add_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_imm_r_r_i(dst, src, imm)) } -inst_adds_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS_IMM, dst, src, imm) } -emit_adds_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_imm_r_r_i(dst, src, imm)) } -inst_sub_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB_IMM, dst, src, imm) } -emit_sub_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_imm_r_r_i(dst, src, imm)) } -inst_subs_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS_IMM, dst, src, imm) } -emit_subs_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_imm_r_r_i(dst, src, imm)) } -inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } -inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } -inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } -inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } -inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } -inst_add_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_add_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_adds_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_adds_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_sub_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_sub_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_subs_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_subs_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_and_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_and_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_ands_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_ands_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_orr_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_orr_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_eor_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_eor_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_bic_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_bic_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_bics_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_bics_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_orn_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_orn_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_eon_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_eon_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_add_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_add_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_adds_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_adds_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_sub_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_sub_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_subs_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_subs_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_lslv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSLV, dst, src, src2) } -emit_lslv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lslv_r_r_r(dst, src, src2)) } -inst_lsrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSRV, dst, src, src2) } -emit_lsrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsrv_r_r_r(dst, src, src2)) } -inst_asrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASRV, dst, src, src2) } -emit_asrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asrv_r_r_r(dst, src, src2)) } -inst_rorv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.RORV, dst, src, src2) } -emit_rorv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rorv_r_r_r(dst, src, src2)) } -inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } -emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } -inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } -emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } -inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } -emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } -inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } -emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } -inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } -emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } -inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } -emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } -inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } -inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } -inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } -emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } -inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } -emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } -inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } -emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } -inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } -emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } -inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } -emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } -inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } -inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } -inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } -inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } -inst_ccmp_reg_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP_REG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -emit_ccmp_reg_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_reg_r_r_i_c(dst, src, imm, cond)) } -inst_ccmp_imm_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP_IMM, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } -emit_ccmp_imm_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_imm_r_i_i_c(dst, imm, imm2, cond)) } -inst_ccmn_reg_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN_REG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -emit_ccmn_reg_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_reg_r_r_i_c(dst, src, imm, cond)) } -inst_ccmn_imm_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN_IMM, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } -emit_ccmn_imm_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_imm_r_i_i_c(dst, imm, imm2, cond)) } -inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } -emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } -inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } -emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } -inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } -emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } -inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } -emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } -inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } -emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } -inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } -inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } -emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } -emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } -inst_b_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } -emit_b_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_b_cond_c_l(cond, label)) } -inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } -inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } -inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } -emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } -inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } -emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } -inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } -emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } -inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } -inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } -emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } -inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } -emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } -inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } -emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } -inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } -emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } -inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } -emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } -inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } -emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } -inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } -emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } -inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } -emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } -inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } -emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } -inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } -emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } -inst_ldr_lit_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR_LIT, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_ldr_lit_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_lit_r_l(dst, label)) } -inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } -emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } -inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } -emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } -inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } -emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } -inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } -emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } -inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } -emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } -inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } -emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } -inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } -emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } -inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } -emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } -inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } -emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } -inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } -emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } -emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } -inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } -emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } -inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } -emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } -inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } -emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } -inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } -emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } -inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } -emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } -inst_mrs_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MRS, dst, imm) } -emit_mrs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_i(dst, imm)) } -inst_msr_imm_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR_IMM, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } -emit_msr_imm_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_imm_i_i(imm, imm2)) } -inst_msr_reg_i_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR_REG, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_reg(src), {}, {}}} } -emit_msr_reg_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_reg_i_r(imm, src)) } -inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } -inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } -inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } -inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } -inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } -inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } -inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } -inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } -inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } -emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } -inst_fmov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_REG, dst, src) } -emit_fmov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_reg_r_r(dst, src)) } -inst_fmov_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV_IMM, dst, imm) } -emit_fmov_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_imm_r_i(dst, imm)) } -inst_fmov_gen_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_GEN, dst, src) } -emit_fmov_gen_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_gen_r_r(dst, src)) } -inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } -emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } -inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } -emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } -inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } -emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } -inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } -emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } -inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } -emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } -inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } -emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } -inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } -emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } -inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } -emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } -inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } -emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } -emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } -emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } -emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } -emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } -inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } -emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } -inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } -inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } -emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } -inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } -emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } -inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } -emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } -inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } -emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } -inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } -emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } -inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } -emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } -inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } -emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } -inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } -emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } -inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } -emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } -inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } -emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } -inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } -emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } -inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } -emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } -inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } -emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } -inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } -emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } -inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } -emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } -inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } -emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } -inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } -emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } -inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } -emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } -inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } -emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } -inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } -emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } -inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } -emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } -inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } -emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } -inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } -emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } -inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } -emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } -inst_and_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND_IMM, dst, src, imm) } -emit_and_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_imm_r_r_i(dst, src, imm)) } -inst_ands_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS_IMM, dst, src, imm) } -emit_ands_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_imm_r_r_i(dst, src, imm)) } -inst_orr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR_IMM, dst, src, imm) } -emit_orr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_imm_r_r_i(dst, src, imm)) } -inst_eor_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR_IMM, dst, src, imm) } -emit_eor_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_imm_r_r_i(dst, src, imm)) } -inst_tst_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST_IMM, dst, imm) } -emit_tst_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_imm_r_i(dst, imm)) } -inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } -emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } -inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } -emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } -inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } -emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } -inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } -emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } -inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } -emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } -inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } -emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } -inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } -emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } -inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } -emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } -inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } -emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } -inst_ldr_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_PRE, dst, mem) } -emit_ldr_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_pre_r_m(dst, mem)) } -inst_str_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_PRE, dst, mem) } -emit_str_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_pre_r_m(dst, mem)) } -inst_ldr_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_POST, dst, mem) } -emit_ldr_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_post_r_m(dst, mem)) } -inst_str_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_POST, dst, mem) } -emit_str_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_post_r_m(dst, mem)) } -inst_ldrb_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_PRE, dst, mem) } -emit_ldrb_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_pre_r_m(dst, mem)) } -inst_strb_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_PRE, dst, mem) } -emit_strb_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_pre_r_m(dst, mem)) } -inst_ldrb_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_POST, dst, mem) } -emit_ldrb_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_post_r_m(dst, mem)) } -inst_strb_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_POST, dst, mem) } -emit_strb_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_post_r_m(dst, mem)) } -inst_ldrh_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_PRE, dst, mem) } -emit_ldrh_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_pre_r_m(dst, mem)) } -inst_strh_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_PRE, dst, mem) } -emit_strh_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_pre_r_m(dst, mem)) } -inst_ldrh_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_POST, dst, mem) } -emit_ldrh_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_post_r_m(dst, mem)) } -inst_strh_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_POST, dst, mem) } -emit_strh_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_post_r_m(dst, mem)) } -inst_ldr_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_REG, dst, mem) } -emit_ldr_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_reg_r_m(dst, mem)) } -inst_str_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_REG, dst, mem) } -emit_str_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_reg_r_m(dst, mem)) } -inst_ldrb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB_REG, dst, mem) } -emit_ldrb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_reg_r_m(dst, mem)) } -inst_strb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB_REG, dst, mem) } -emit_strb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_reg_r_m(dst, mem)) } -inst_ldrh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH_REG, dst, mem) } -emit_ldrh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_reg_r_m(dst, mem)) } -inst_strh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH_REG, dst, mem) } -emit_strh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_reg_r_m(dst, mem)) } -inst_ldrsb_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB_REG, dst, mem) } -emit_ldrsb_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_reg_r_m(dst, mem)) } -inst_ldrsh_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH_REG, dst, mem) } -emit_ldrsh_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_reg_r_m(dst, mem)) } -inst_ldrsw_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW_REG, dst, mem) } -emit_ldrsw_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_reg_r_m(dst, mem)) } -inst_ldp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_PRE, dst, src, mem) } -emit_ldp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_pre_r_r_m(dst, src, mem)) } -inst_stp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_PRE, dst, src, mem) } -emit_stp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_pre_r_r_m(dst, src, mem)) } -inst_ldp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_POST, dst, src, mem) } -emit_ldp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_post_r_r_m(dst, src, mem)) } -inst_stp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_POST, dst, src, mem) } -emit_stp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_post_r_r_m(dst, src, mem)) } -inst_ldpsw_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_PRE, dst, src, mem) } -emit_ldpsw_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_pre_r_r_m(dst, src, mem)) } -inst_ldpsw_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_POST, dst, src, mem) } -emit_ldpsw_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_post_r_r_m(dst, src, mem)) } -inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } -emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } -inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } -emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } -inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } -emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } -inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } -emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } -inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } -emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } -inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } -emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } -inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } -emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } -inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } -emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } -inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } -emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } -inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } -emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } -inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } -emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } -inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } -emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } -inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } -emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } -inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } -emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } -inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } -emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } -inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } -emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } -inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } -emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } -inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } -emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } -inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } -emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } -inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } -emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } -inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } -emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } -inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } -emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } -inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } -emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } -inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } -emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } -inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } -emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } -inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } -emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } -inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } -emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } -inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } -emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } -inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } -emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } -inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } -emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } -inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } -emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } -inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } -emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } -inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } -emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } -inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } -emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } -inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } -emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } -inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } -emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } -inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } -emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } -inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } -emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } -inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } -emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } -inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } -emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } -inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } -emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } -inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } -emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } -inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } -emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } -inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } -emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } -inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } -emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } -inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } -emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } -inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } -emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } -inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } -emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } -inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } -emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } -inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } -emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } -inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } -emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } -inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } -emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } -inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } -emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } -inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } -emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } -inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } -emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } -inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } -emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } -inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } -emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } -inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } -emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } -inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } -emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } -inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } -emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } -inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } -emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } -inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } -emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } -inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } -emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } -inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } -emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } -inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } -emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } -inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } -emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } -inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } -emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } -inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } -emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } -inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } -emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } -inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } -emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } -inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } -emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } -inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } -emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } -inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } -emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } -inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } -emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } -inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } -emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } -inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } -emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } -inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } -emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } -inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } -emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } -inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } -emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } -inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } -emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } -inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } -emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } -inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } -emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } -inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } -emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } -inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } -emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } -inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } -emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } -inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } -emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } -inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } -emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } -inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } -emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } -inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } -emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } -inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } -emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } -inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } -emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } -inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } -emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } -inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } -emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } -inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } -emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } -inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } -emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } -inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } -emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } -inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } -emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } -inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } -emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } -inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } -emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } -inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } -emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } -inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } -emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } -inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } -emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } -inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } -emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } -inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } -emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } -inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } -emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } -inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } -emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } -inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } -emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } -inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } -inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } -emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } -inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } -inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } -inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } -emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } -inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } -emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } -inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } -emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } -inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } -emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } -inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } -emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } -inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } -emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } -inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } -emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } -inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } -emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } -inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } -emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } -inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } -emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } -inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } -emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } -inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } -emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } -inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } -emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } -inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } -emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } -inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } -emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } -inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } -emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } -inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } -emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } -inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } -emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } -inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } -emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } -inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } -emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } -inst_aese_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_aese_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_r_r(dst, src)) } -inst_aesd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_aesd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_r_r(dst, src)) } -inst_aesmc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_aesmc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_r_r(dst, src)) } -inst_aesimc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_aesimc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_r_r(dst, src)) } -inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } -emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } -inst_sha1c_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1c_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_r(dst, src, src2)) } -inst_sha1p_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1p_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_r(dst, src, src2)) } -inst_sha1m_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1m_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_r(dst, src, src2)) } -inst_sha1su0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1su0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_r_r_r(dst, src, src2)) } -inst_sha1su1_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sha1su1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_r_r(dst, src)) } -inst_sha256h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_r(dst, src, src2)) } -inst_sha256h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_r(dst, src, src2)) } -inst_sha256su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sha256su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_r_r(dst, src)) } -inst_sha256su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_r_r_r(dst, src, src2)) } -inst_sha512h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_r(dst, src, src2)) } -inst_sha512h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_r(dst, src, src2)) } -inst_sha512su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_sha512su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_r_r(dst, src)) } -inst_sha512su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_r_r_r(dst, src, src2)) } -inst_eor3_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } -emit_eor3_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_r_r_r_r(dst, src, src2, src3)) } -inst_bcax_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } -emit_bcax_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_r_r_r_r(dst, src, src2, src3)) } -inst_rax1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_rax1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_r_r_r(dst, src, src2)) } -inst_xar_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_xar_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_r_r_r_i(dst, src, src2, imm)) } -inst_sm3partw1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm3partw1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_r_r_r(dst, src, src2)) } -inst_sm3partw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm3partw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_r_r_r(dst, src, src2)) } -inst_sm3ss1_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_v_4s(u8(reg_hw(src3)))}} } -emit_sm3ss1_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_r_r_r_r(dst, src, src2, src3)) } -inst_sm3tt1a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt1a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_r_r_r(dst, src, src2)) } -inst_sm3tt1b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt1b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_r_r_r(dst, src, src2)) } -inst_sm3tt2a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt2a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_r_r_r(dst, src, src2)) } -inst_sm3tt2b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt2b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_r_r_r(dst, src, src2)) } -inst_sm4e_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sm4e_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_r_r(dst, src)) } -inst_sm4ekey_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm4ekey_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_r_r_r(dst, src, src2)) } -inst_pmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_pmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_r_r_r(dst, src, src2)) } -inst_pmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_pmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_r_r_r(dst, src, src2)) } -inst_fabs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS_H, dst, src) } -emit_fabs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_h_r_r(dst, src)) } -inst_fneg_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG_H, dst, src) } -emit_fneg_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_h_r_r(dst, src)) } -inst_fsqrt_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT_H, dst, src) } -emit_fsqrt_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_h_r_r(dst, src)) } -inst_fadd_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD_H, dst, src, src2) } -emit_fadd_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_h_r_r_r(dst, src, src2)) } -inst_fsub_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB_H, dst, src, src2) } -emit_fsub_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_h_r_r_r(dst, src, src2)) } -inst_fmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL_H, dst, src, src2) } -emit_fmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_h_r_r_r(dst, src, src2)) } -inst_fdiv_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV_H, dst, src, src2) } -emit_fdiv_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_h_r_r_r(dst, src, src2)) } -inst_fnmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL_H, dst, src, src2) } -emit_fnmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_h_r_r_r(dst, src, src2)) } -inst_fmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD_H, dst, src, src2, src3) } -emit_fmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_h_r_r_r_r(dst, src, src2, src3)) } -inst_fmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB_H, dst, src, src2, src3) } -emit_fmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_h_r_r_r_r(dst, src, src2, src3)) } -inst_fnmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD_H, dst, src, src2, src3) } -emit_fnmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_h_r_r_r_r(dst, src, src2, src3)) } -inst_fnmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB_H, dst, src, src2, src3) } -emit_fnmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_h_r_r_r_r(dst, src, src2, src3)) } -inst_fcmp_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP_H, dst, src) } -emit_fcmp_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_h_r_r(dst, src)) } -inst_fcmpe_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE_H, dst, src) } -emit_fcmpe_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_h_r_r(dst, src)) } -inst_fcsel_h_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL_H, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_fcsel_h_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_h_r_r_r_c(dst, src, src2, cond)) } -inst_fmax_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX_H, dst, src, src2) } -emit_fmax_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_h_r_r_r(dst, src, src2)) } -inst_fmin_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN_H, dst, src, src2) } -emit_fmin_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_h_r_r_r(dst, src, src2)) } -inst_fmaxnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM_H, dst, src, src2) } -emit_fmaxnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_h_r_r_r(dst, src, src2)) } -inst_fminnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM_H, dst, src, src2) } -emit_fminnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_h_r_r_r(dst, src, src2)) } -inst_fcvt_h_s_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_S, dst, src) } -emit_fcvt_h_s_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_s_r_r(dst, src)) } -inst_fcvt_h_d_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_D, dst, src) } -emit_fcvt_h_d_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_d_r_r(dst, src)) } -inst_fcvt_s_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_S_H, dst, src) } -emit_fcvt_s_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_s_h_r_r(dst, src)) } -inst_fcvt_d_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_D_H, dst, src) } -emit_fcvt_d_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_d_h_r_r(dst, src)) } -inst_fmov_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_H, dst, src) } -emit_fmov_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_h_r_r(dst, src)) } -inst_scvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF_H, dst, src) } -emit_scvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_h_r_r(dst, src)) } -inst_ucvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF_H, dst, src) } -emit_ucvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_h_r_r(dst, src)) } -inst_fcvtzs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS_H, dst, src) } -emit_fcvtzs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_h_r_r(dst, src)) } -inst_fcvtzu_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU_H, dst, src) } -emit_fcvtzu_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_h_r_r(dst, src)) } -inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } -inst_bfdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_r_r_r(dst, src, src2)) } -inst_bfmmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_r_r_r(dst, src, src2)) } -inst_bfmlalb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmlalb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_r_r_r(dst, src, src2)) } -inst_bfmlalt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmlalt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_r_r_r(dst, src, src2)) } -inst_bfcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_bfcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_r_r(dst, src)) } -inst_bfcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_bfcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_r_r(dst, src)) } -inst_add_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_add_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v_r_r_r(dst, src, src2)) } -inst_sub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_sub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v_r_r_r(dst, src, src2)) } -inst_mul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_mul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v_r_r_r(dst, src, src2)) } -inst_mla_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_mla_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v_r_r_r(dst, src, src2)) } -inst_mls_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_mls_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v_r_r_r(dst, src, src2)) } -inst_neg_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_neg_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v_r_r(dst, src)) } -inst_abs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_abs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v_r_r(dst, src)) } -inst_shadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_shadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_r_r_r(dst, src, src2)) } -inst_uhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_r_r_r(dst, src, src2)) } -inst_shsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_shsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_r_r_r(dst, src, src2)) } -inst_uhsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uhsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_r_r_r(dst, src, src2)) } -inst_srhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_srhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_r_r_r(dst, src, src2)) } -inst_urhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_urhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_r_r_r(dst, src, src2)) } -inst_sqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_r_r_r(dst, src, src2)) } -inst_uqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_r_r_r(dst, src, src2)) } -inst_sqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_r_r_r(dst, src, src2)) } -inst_uqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_r_r_r(dst, src, src2)) } -inst_smax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_r_r_r(dst, src, src2)) } -inst_umax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_r_r_r(dst, src, src2)) } -inst_smin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_r_r_r(dst, src, src2)) } -inst_umin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_r_r_r(dst, src, src2)) } -inst_sabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_r_r_r(dst, src, src2)) } -inst_uabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_r_r_r(dst, src, src2)) } -inst_saba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_r_r_r(dst, src, src2)) } -inst_uaba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_r_r_r(dst, src, src2)) } -inst_addp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_addp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v_r_r_r(dst, src, src2)) } -inst_addv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_addv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_r(dst, src)) } -inst_saddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_saddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_r_r(dst, src)) } -inst_uaddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uaddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_r_r(dst, src)) } -inst_sadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_r_r(dst, src)) } -inst_uadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_r_r(dst, src)) } -inst_saddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_saddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_r(dst, src)) } -inst_uaddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uaddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_r(dst, src)) } -inst_smaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_smaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_r(dst, src)) } -inst_umaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_umaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_r(dst, src)) } -inst_sminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_r(dst, src)) } -inst_uminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_r(dst, src)) } -inst_smaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_r_r_r(dst, src, src2)) } -inst_umaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_r_r_r(dst, src, src2)) } -inst_sminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_r_r_r(dst, src, src2)) } -inst_uminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_r_r_r(dst, src, src2)) } -inst_saddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_r_r_r(dst, src, src2)) } -inst_saddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_saddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_r_r_r(dst, src, src2)) } -inst_uaddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_r_r_r(dst, src, src2)) } -inst_uaddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_uaddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_r_r_r(dst, src, src2)) } -inst_ssubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ssubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_r_r_r(dst, src, src2)) } -inst_ssubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_ssubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_r_r_r(dst, src, src2)) } -inst_usubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_r_r_r(dst, src, src2)) } -inst_usubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_usubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_r_r_r(dst, src, src2)) } -inst_saddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_r_r_r(dst, src, src2)) } -inst_saddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_saddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_r_r_r(dst, src, src2)) } -inst_uaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_r_r_r(dst, src, src2)) } -inst_uaddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_uaddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_r_r_r(dst, src, src2)) } -inst_ssubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ssubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_r_r_r(dst, src, src2)) } -inst_ssubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_ssubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_r_r_r(dst, src, src2)) } -inst_usubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_r_r_r(dst, src, src2)) } -inst_usubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_usubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_r_r_r(dst, src, src2)) } -inst_raddhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_raddhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_r_r_r(dst, src, src2)) } -inst_raddhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_raddhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_r_r_r(dst, src, src2)) } -inst_rsubhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_rsubhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_r_r_r(dst, src, src2)) } -inst_rsubhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_rsubhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_r_r_r(dst, src, src2)) } -inst_addhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_addhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_r_r_r(dst, src, src2)) } -inst_addhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_addhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_r_r_r(dst, src, src2)) } -inst_subhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_subhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_r_r_r(dst, src, src2)) } -inst_subhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_subhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_r_r_r(dst, src, src2)) } -inst_xtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_xtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_r_r(dst, src)) } -inst_xtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_xtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_r_r(dst, src)) } -inst_sqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_r_r(dst, src)) } -inst_sqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_r_r(dst, src)) } -inst_uqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_uqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_r_r(dst, src)) } -inst_uqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_uqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_r_r(dst, src)) } -inst_sqxtun_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtun_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_r_r(dst, src)) } -inst_sqxtun2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtun2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_r_r(dst, src)) } -inst_smull_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smull_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v_r_r_r(dst, src, src2)) } -inst_smull2_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smull2_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v_r_r_r(dst, src, src2)) } -inst_umull_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umull_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v_r_r_r(dst, src, src2)) } -inst_umull2_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umull2_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v_r_r_r(dst, src, src2)) } -inst_smlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_r_r_r(dst, src, src2)) } -inst_smlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_r_r_r(dst, src, src2)) } -inst_umlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_r_r_r(dst, src, src2)) } -inst_umlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_r_r_r(dst, src, src2)) } -inst_smlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_r_r_r(dst, src, src2)) } -inst_smlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_r_r_r(dst, src, src2)) } -inst_umlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_r_r_r(dst, src, src2)) } -inst_umlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_r_r_r(dst, src, src2)) } -inst_sqdmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_r_r_r(dst, src, src2)) } -inst_sqdmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_r_r_r(dst, src, src2)) } -inst_sqdmlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_r_r_r(dst, src, src2)) } -inst_sqdmlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_r_r_r(dst, src, src2)) } -inst_sqdmlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_r_r_r(dst, src, src2)) } -inst_sqdmlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_r_r_r(dst, src, src2)) } -inst_sqdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_r_r_r(dst, src, src2)) } -inst_sqrdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqrdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_r_r_r(dst, src, src2)) } -inst_sdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_r_r_r(dst, src, src2)) } -inst_udot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_udot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_r_r_r(dst, src, src2)) } -inst_usdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_r_r_r(dst, src, src2)) } -inst_fadd_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fadd_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v_r_r_r(dst, src, src2)) } -inst_fsub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fsub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v_r_r_r(dst, src, src2)) } -inst_fmul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v_r_r_r(dst, src, src2)) } -inst_fdiv_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fdiv_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v_r_r_r(dst, src, src2)) } -inst_fneg_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fneg_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v_r_r(dst, src)) } -inst_fabs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fabs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v_r_r(dst, src)) } -inst_fsqrt_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fsqrt_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v_r_r(dst, src)) } -inst_fmla_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_fmla_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v_r_r_r(dst, src, src2)) } -inst_fmls_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_fmls_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v_r_r_r(dst, src, src2)) } -inst_fmulx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmulx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_r_r_r(dst, src, src2)) } -inst_fmax_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmax_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v_r_r_r(dst, src, src2)) } -inst_fmin_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmin_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v_r_r_r(dst, src, src2)) } -inst_fmaxnm_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmaxnm_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v_r_r_r(dst, src, src2)) } -inst_fminnm_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fminnm_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v_r_r_r(dst, src, src2)) } -inst_fmaxp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmaxp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v_r_r_r(dst, src, src2)) } -inst_fminp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fminp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v_r_r_r(dst, src, src2)) } -inst_fmaxnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmaxnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_r_r_r(dst, src, src2)) } -inst_fminnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fminnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_r_r_r(dst, src, src2)) } -inst_fmaxv_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV_V, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fmaxv_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_v_r_r(dst, src)) } -inst_fminv_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV_V, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fminv_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_v_r_r(dst, src)) } -inst_fmaxnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fmaxnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_r(dst, src)) } -inst_fminnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fminnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_r(dst, src)) } -inst_frecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_r_r(dst, src)) } -inst_frsqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frsqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_r_r(dst, src)) } -inst_frecps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_frecps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_r_r_r(dst, src, src2)) } -inst_frsqrts_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_frsqrts_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_r_r_r(dst, src, src2)) } -inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } -emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } -inst_faddp_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_faddp_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v_r_r_r(dst, src, src2)) } -inst_frinta_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frinta_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v_r_r(dst, src)) } -inst_frinti_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frinti_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v_r_r(dst, src)) } -inst_frintm_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frintm_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v_r_r(dst, src)) } -inst_frintn_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frintn_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v_r_r(dst, src)) } -inst_frintp_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frintp_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v_r_r(dst, src)) } -inst_frintx_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frintx_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v_r_r(dst, src)) } -inst_frintz_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frintz_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v_r_r(dst, src)) } -inst_scvtf_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_scvtf_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v_r_r(dst, src)) } -inst_ucvtf_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_ucvtf_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v_r_r(dst, src)) } -inst_fcvtas_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtas_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v_r_r(dst, src)) } -inst_fcvtau_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtau_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v_r_r(dst, src)) } -inst_fcvtms_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtms_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v_r_r(dst, src)) } -inst_fcvtmu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtmu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v_r_r(dst, src)) } -inst_fcvtns_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtns_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v_r_r(dst, src)) } -inst_fcvtnu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtnu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v_r_r(dst, src)) } -inst_fcvtps_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtps_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v_r_r(dst, src)) } -inst_fcvtpu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtpu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v_r_r(dst, src)) } -inst_fcvtzs_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtzs_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v_r_r(dst, src)) } -inst_fcvtzu_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtzu_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v_r_r(dst, src)) } -inst_fcvtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), {}, {}}} } -emit_fcvtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_r_r(dst, src)) } -inst_fcvtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_fcvtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_r_r(dst, src)) } -inst_fcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_r_r(dst, src)) } -inst_fcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_r_r(dst, src)) } -inst_fcvtxn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_fcvtxn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_r_r(dst, src)) } -inst_fcvtxn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_fcvtxn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_r_r(dst, src)) } -inst_fcmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fcmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_r_r_r(dst, src, src2)) } -inst_fcmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fcmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_r_r_r(dst, src, src2)) } -inst_fcmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fcmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_r_r_r(dst, src, src2)) } -inst_fcmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_r_r(dst, src)) } -inst_fcmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_fcmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_r_r(dst, src)) } -inst_facge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_facge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_r_r_r(dst, src, src2)) } -inst_facgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_facgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_r_r_r(dst, src, src2)) } -inst_cmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_r_r_r(dst, src, src2)) } -inst_cmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_r_r_r(dst, src, src2)) } -inst_cmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_r_r_r(dst, src, src2)) } -inst_cmhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_r_r_r(dst, src, src2)) } -inst_cmhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_r_r_r(dst, src, src2)) } -inst_cmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_r_r(dst, src)) } -inst_cmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_r_r(dst, src)) } -inst_cmtst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmtst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_r_r_r(dst, src, src2)) } -inst_and_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_and_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v_r_r_r(dst, src, src2)) } -inst_orr_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_orr_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v_r_r_r(dst, src, src2)) } -inst_eor_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_eor_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v_r_r_r(dst, src, src2)) } -inst_bic_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bic_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v_r_r_r(dst, src, src2)) } -inst_orn_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_orn_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v_r_r_r(dst, src, src2)) } -inst_mvn_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_mvn_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v_r_r(dst, src)) } -inst_bit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_r_r_r(dst, src, src2)) } -inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) } -inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) } -inst_shl_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shl_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v_r_r_i(dst, src, imm)) } -inst_sqshl_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshl_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v_r_r_i(dst, src, imm)) } -inst_sqshlu_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshlu_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_r_r_i(dst, src, imm)) } -inst_srshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_srshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_r_r_r(dst, src, src2)) } -inst_urshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_urshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_r_r_r(dst, src, src2)) } -inst_sshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_r_r_i(dst, src, imm)) } -inst_ushr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_r_r_i(dst, src, imm)) } -inst_ssra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ssra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_r_r_i(dst, src, imm)) } -inst_usra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_usra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_r_r_i(dst, src, imm)) } -inst_srshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_srshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_r_r_i(dst, src, imm)) } -inst_urshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_urshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_r_r_i(dst, src, imm)) } -inst_srsra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_srsra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_r_r_i(dst, src, imm)) } -inst_ursra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ursra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_r_r_i(dst, src, imm)) } -inst_sshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_r_r_r(dst, src, src2)) } -inst_ushl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ushl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_r_r_r(dst, src, src2)) } -inst_sli_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sli_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_r_r_i(dst, src, imm)) } -inst_sri_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sri_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_r_r_i(dst, src, imm)) } -inst_sshll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_r_r_i(dst, src, imm)) } -inst_sshll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_r_r_i(dst, src, imm)) } -inst_ushll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_r_r_i(dst, src, imm)) } -inst_ushll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_r_r_i(dst, src, imm)) } -inst_sxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_r_r(dst, src)) } -inst_sxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_sxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_r_r(dst, src)) } -inst_uxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_r_r(dst, src)) } -inst_uxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_uxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_r_r(dst, src)) } -inst_shrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_r_r_i(dst, src, imm)) } -inst_shrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_r_r_i(dst, src, imm)) } -inst_rshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_rshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_r_r_i(dst, src, imm)) } -inst_rshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_rshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_r_r_i(dst, src, imm)) } -inst_sqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_r_r_i(dst, src, imm)) } -inst_sqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_r_r_i(dst, src, imm)) } -inst_uqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_r_r_i(dst, src, imm)) } -inst_uqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_r_r_i(dst, src, imm)) } -inst_sqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_r_r_i(dst, src, imm)) } -inst_sqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_r_r_i(dst, src, imm)) } -inst_uqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_r_r_i(dst, src, imm)) } -inst_uqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_r_r_i(dst, src, imm)) } -inst_sqshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_r_r_i(dst, src, imm)) } -inst_sqshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_r_r_i(dst, src, imm)) } -inst_sqrshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_r_r_i(dst, src, imm)) } -inst_sqrshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_r_r_i(dst, src, imm)) } -inst_dup_v_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP_V, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_elem_b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -inst_dup_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_reg(src), {}, {}}} } -emit_dup_v_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v_r_r_i(dst, src, imm)) } -emit_dup_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v_r_r(dst, src)) } -inst_ins_r_i_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_v_elem_b(u8(reg_hw(src))), op_imm(imm2, 4)}} } -inst_ins_r_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_reg(src), {}}} } -emit_ins_r_i_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_r_i_r_i(dst, imm, src, imm2)) } -emit_ins_r_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_r_i_r(dst, imm, src)) } -inst_mov_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_mov_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v_r_r(dst, src)) } -inst_ext_v_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT_V, operand_count = 4, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), op_imm(imm, 4)}} } -emit_ext_v_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v_r_r_r_i(dst, src, src2, imm)) } -inst_tbl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_tbl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_r_r_r(dst, src, src2)) } -inst_tbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_tbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_r_r_r(dst, src, src2)) } -inst_zip1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_zip1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_r_r_r(dst, src, src2)) } -inst_zip2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_zip2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_r_r_r(dst, src, src2)) } -inst_uzp1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uzp1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_r_r_r(dst, src, src2)) } -inst_uzp2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uzp2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_r_r_r(dst, src, src2)) } -inst_trn1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_trn1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_r_r_r(dst, src, src2)) } -inst_trn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_trn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_r_r_r(dst, src, src2)) } -inst_not_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_not_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_r_r(dst, src)) } -inst_rbit_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_rbit_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v_r_r(dst, src)) } -inst_rev16_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_rev16_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v_r_r(dst, src)) } -inst_rev32_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_rev32_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v_r_r(dst, src)) } -inst_rev64_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_rev64_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_r_r(dst, src)) } -inst_cls_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cls_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v_r_r(dst, src)) } -inst_clz_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ_V, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_clz_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v_r_r(dst, src)) } -inst_cnt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cnt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_r_r(dst, src)) } -inst_urecpe_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_urecpe_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v_r_r(dst, src)) } -inst_ursqrte_v_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE_V, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_ursqrte_v_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v_r_r(dst, src)) } -inst_movi_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } -emit_movi_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_r_i(dst, imm)) } -inst_mvni_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } -emit_mvni_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_r_i(dst, imm)) } -inst_fmov_v_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV_V_IMM, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } -emit_fmov_v_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v_imm_r_i(dst, imm)) } -inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) } -inst_ld2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_r_m(dst, mem)) } -inst_ld3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_r_m(dst, mem)) } -inst_ld4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_r_m(dst, mem)) } -inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_st1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_r_m(dst, mem)) } -inst_st2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_st2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_r_m(dst, mem)) } -inst_st3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_st3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_r_m(dst, mem)) } -inst_st4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_st4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_r_m(dst, mem)) } -inst_ld1r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld1r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_r_m(dst, mem)) } -inst_ld2r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld2r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_r_m(dst, mem)) } -inst_ld3r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld3r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_r_m(dst, mem)) } -inst_ld4r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld4r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_r_m(dst, mem)) } -inst_ld1_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld1_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_lane_r_i_m(dst, imm, mem)) } -inst_ld2_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld2_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_lane_r_i_m(dst, imm, mem)) } -inst_ld3_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld3_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_lane_r_i_m(dst, imm, mem)) } -inst_ld4_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld4_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_lane_r_i_m(dst, imm, mem)) } -inst_st1_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st1_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_lane_r_i_m(dst, imm, mem)) } -inst_st2_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st2_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_lane_r_i_m(dst, imm, mem)) } -inst_st3_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st3_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_lane_r_i_m(dst, imm, mem)) } -inst_st4_lane_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4_LANE, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st4_lane_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_lane_r_i_m(dst, imm, mem)) } -inst_ldr_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_V, dst, mem) } -emit_ldr_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_v_r_m(dst, mem)) } -inst_str_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_V, dst, mem) } -emit_str_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_v_r_m(dst, mem)) } -inst_ldp_v_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_V, dst, src, mem) } -emit_ldp_v_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_v_r_r_m(dst, src, mem)) } -inst_stp_v_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_V, dst, src, mem) } -emit_stp_v_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_v_r_r_m(dst, src, mem)) } -inst_ldur_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR_V, dst, mem) } -emit_ldur_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_v_r_m(dst, mem)) } -inst_stur_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR_V, dst, mem) } -emit_stur_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_v_r_m(dst, mem)) } -inst_sve_add_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_add_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_add_z_z_z_z(rz, rz2, rz3)) } -inst_sve_sub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_sub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sub_z_z_z_z(rz, rz2, rz3)) } -inst_sve_sqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_sqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqadd_z_z_z_z(rz, rz2, rz3)) } -inst_sve_uqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_uqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqadd_z_z_z_z(rz, rz2, rz3)) } -inst_sve_sqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_sqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqsub_z_z_z_z(rz, rz2, rz3)) } -inst_sve_uqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_uqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqsub_z_z_z_z(rz, rz2, rz3)) } -inst_sve_add_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_add_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_add_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_sub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_sub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sub_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_subr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUBR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_subr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_subr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_mul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MUL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_mul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_mul_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_smulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_smulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_umulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_umulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_sdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_sve_sdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_udiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_sve_udiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_udiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_smax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_smax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_umax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_umax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_smin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_smin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_umin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_umin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_sabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_sabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_uabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_uabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_uabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_and_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_and_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_orr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_orr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_eor_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_eor_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bic_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_bic_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_asr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_asr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_lsl_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_lsl_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsl_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_lsr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_lsr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_asrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_asrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_lslr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSLR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_lslr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lslr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_lsrr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSRR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_lsrr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsrr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_abs_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ABS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_abs_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_abs_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_neg_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NEG_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_neg_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_neg_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_cls_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_cls_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cls_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_clz_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLZ_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_clz_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_clz_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_cnt_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CNT_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_cnt_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cnt_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_mov_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_sve_mov_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_mov_pred_z_p_z(rz, rz2, rz3)) } -inst_sve_fadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_fadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fadd_z_z_z_z(rz, rz2, rz3)) } -inst_sve_fsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_fsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsub_z_z_z_z(rz, rz2, rz3)) } -inst_sve_fmul_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_fmul_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fmul_z_z_z_z(rz, rz2, rz3)) } -inst_sve_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecps_z_z_z(rz, rz2, rz3)) } -inst_sve_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frsqrts_z_z_z(rz, rz2, rz3)) } -inst_sve_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_ftsmul_z_z_z(rz, rz2, rz3)) } -inst_sve_fadd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fadd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fadd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fsub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fsub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsub_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fsubr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUBR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fsubr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsubr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fmul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmul_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIV_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fdivr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIVR_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fdivr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdivr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fmax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAX_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fmin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMIN_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAXNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmaxnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fminnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMINNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fminnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fminnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fabs_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FABS_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_fabs_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fabs_z_z_p_z(rz, rz2, rz3)) } -inst_sve_fneg_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNEG_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_fneg_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fneg_z_z_p_z(rz, rz2, rz3)) } -inst_sve_fsqrt_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSQRT_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_fsqrt_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsqrt_z_z_p_z(rz, rz2, rz3)) } -inst_sve_frecpx_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPX_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frecpx_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecpx_z_z_p_z(rz, rz2, rz3)) } -inst_sve_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintn_z_p_z(rz, rz2, rz3)) } -inst_sve_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintp_z_p_z(rz, rz2, rz3)) } -inst_sve_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintm_z_p_z(rz, rz2, rz3)) } -inst_sve_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintz_z_p_z(rz, rz2, rz3)) } -inst_sve_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinta_z_p_z(rz, rz2, rz3)) } -inst_sve_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frintx_z_p_z(rz, rz2, rz3)) } -inst_sve_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frinti_z_p_z(rz, rz2, rz3)) } -inst_sve_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_and_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_and_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_bic_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_bic_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_orr_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_orr_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_eor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_eor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_nand_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NAND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_nand_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nand_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_nor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_nor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nor_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_orn_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORN_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_orn_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orn_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_sel_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SEL_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_sel_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sel_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_ands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_ands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_ands_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_bics_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BICS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_bics_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bics_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_orrs_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORRS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_orrs_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orrs_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_eors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_eors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eors_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_nands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_nands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nands_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_nors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_nors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nors_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_orns_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORNS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_orns_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orns_p_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_not_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NOT_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_not_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_not_p_p_p_p(rz, rz2, rz3)) } -inst_sve_mov_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_sve_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sve_mov_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_mov_p_p_p_p(rz, rz2, rz3)) } -emit_sve_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_mov_p_p_p(rz, rz2)) } -inst_sve_movs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_MOVS_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_movs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_movs_p_p_p_p(rz, rz2, rz3)) } -inst_sve_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_sve_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrue_p_i(rz, imm)) } -inst_sve_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_sve_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrues_p_i(rz, imm)) } -inst_sve_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_sve_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_pfalse_p(rz)) } -inst_sve_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pfirst_p_p_p(rz, rz2, rz3)) } -inst_sve_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pnext_p_p_p(rz, rz2, rz3)) } -inst_sve_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brka_p_p_p(rz, rz2, rz3)) } -inst_sve_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkb_p_p_p(rz, rz2, rz3)) } -inst_sve_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkas_p_p_p(rz, rz2, rz3)) } -inst_sve_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_brkbs_p_p_p(rz, rz2, rz3)) } -inst_sve_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sve_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_brkn_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sve_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_sve_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_rdffr_p(rz)) } -inst_sve_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_sve_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_wrffr_p(rz)) } -inst_sve_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SVE_SETFFR) } -emit_sve_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sve_setffr_none()) } -inst_sve_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmle_p_p_z(rz, rz2, rz3)) } -inst_sve_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_sve_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fcmlt_p_p_z(rz, rz2, rz3)) } -inst_sve_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_dup_z_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_DUP_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -emit_sve_dup_z_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_dup_z_z_r(rz, src)) } -inst_sve_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -emit_sve_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_insr_z_r(rz, src)) } -inst_sve_rev_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -emit_sve_rev_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_z_z_z(rz, rz2)) } -inst_sve_rev_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sve_rev_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_p_p_p(rz, rz2)) } -inst_sve_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl_z_z_z(rz, rz2, rz3)) } -inst_sve_zip1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_zip1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_z_z_z_z(rz, rz2, rz3)) } -inst_sve_zip2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_zip2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_z_z_z_z(rz, rz2, rz3)) } -inst_sve_uzp1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_uzp1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_z_z_z_z(rz, rz2, rz3)) } -inst_sve_uzp2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_uzp2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_z_z_z_z(rz, rz2, rz3)) } -inst_sve_trn1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_trn1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_z_z_z_z(rz, rz2, rz3)) } -inst_sve_trn2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_trn2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_z_z_z_z(rz, rz2, rz3)) } -inst_sve_zip1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_zip1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_p_p_p_p(rz, rz2, rz3)) } -inst_sve_zip2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_zip2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_p_p_p_p(rz, rz2, rz3)) } -inst_sve_uzp1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_uzp1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_p_p_p_p(rz, rz2, rz3)) } -inst_sve_uzp2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_uzp2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_p_p_p_p(rz, rz2, rz3)) } -inst_sve_trn1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_trn1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_p_p_p_p(rz, rz2, rz3)) } -inst_sve_trn2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_sve_trn2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_p_p_p_p(rz, rz2, rz3)) } -inst_sve_cpy_z_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_CPY_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -emit_sve_cpy_z_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_sve_cpy_z_z_p_r(rz, rz2, src)) } -inst_sve_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_sve_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_compact_z_p_z(rz, rz2, rz3)) } -inst_sve_ext_z_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_EXT_Z, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } -emit_sve_ext_z_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_ext_z_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_z_p_m(rz, rz2, mem)) } -inst_sve_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_z_p_m(rz, rz2, mem)) } -inst_sve_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_z_p_m(rz, rz2, mem)) } -inst_sve_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_z_p_m(rz, rz2, mem)) } -inst_sve_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_z_p_m(rz, rz2, mem)) } -inst_sve_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_z_p_m(rz, rz2, mem)) } -inst_sve_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_z_p_m(rz, rz2, mem)) } -inst_sve_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_z_p_m(rz, rz2, mem)) } -inst_sve_ldr_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -emit_sve_ldr_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_z_z_m(rz, mem)) } -inst_sve_str_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -emit_sve_str_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_z_z_m(rz, mem)) } -inst_sve_ldr_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -emit_sve_ldr_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_p_p_m(rz, mem)) } -inst_sve_str_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -emit_sve_str_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_p_p_m(rz, mem)) } -inst_sve_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1b_z_p_m(rz, rz2, mem)) } -inst_sve_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1h_z_p_m(rz, rz2, mem)) } -inst_sve_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1w_z_p_m(rz, rz2, mem)) } -inst_sve_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1d_z_p_m(rz, rz2, mem)) } -inst_sve_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilege_p_r_r(rz, src, src2)) } -inst_sve_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilegt_p_r_r(rz, src, src2)) } -inst_sve_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilele_p_r_r(rz, src, src2)) } -inst_sve_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelt_p_r_r(rz, src, src2)) } -inst_sve_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehi_p_r_r(rz, src, src2)) } -inst_sve_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehs_p_r_r(rz, src, src2)) } -inst_sve_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelo_p_r_r(rz, src, src2)) } -inst_sve_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_sve_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilels_p_r_r(rz, src, src2)) } -inst_sve_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlah_z_z_z(rz, rz2, rz3)) } -inst_sve_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlsh_z_z_z(rz, rz2, rz3)) } -inst_sve_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclb_z_z_z(rz, rz2, rz3)) } -inst_sve_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclt_z_z_z(rz, rz2, rz3)) } -inst_sve_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclb_z_z_z(rz, rz2, rz3)) } -inst_sve_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclt_z_z_z(rz, rz2, rz3)) } -inst_sve_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl2_z_z_z(rz, rz2, rz3)) } -inst_sve_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbx_z_z_z(rz, rz2, rz3)) } -inst_sve_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -emit_sve_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aese_z_z(rz, rz2)) } -inst_sve_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -emit_sve_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aesd_z_z(rz, rz2)) } -inst_sve_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } -emit_sve_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesmc_z(rz)) } -inst_sve_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } -emit_sve_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesimc_z(rz)) } -inst_sve_bcax_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BCAX_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_bcax_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bcax_z_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_xar_z_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_XAR_Z, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } -emit_sve_xar_z_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_xar_z_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_eor3_z_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR3_Z, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_eor3_z_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor3_z_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_match_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_sve_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_histseg_z_z_z(rz, rz2, rz3)) } -inst_sme_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTART) } -emit_sme_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstart_none()) } -inst_sme_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTOP) } -emit_sme_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstop_none()) } -inst_sme_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.SME_RDSVL, dst, imm) } -emit_sme_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sme_rdsvl_r_i(dst, imm)) } -inst_sme_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_sme_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_addha_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_sme_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_addva_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SME_ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } -emit_sme_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sme_zero_i(imm)) } -inst_sme_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_sme_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_sme_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_sme_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_sme_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sme_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sme_ldr_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LDR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_sme_ldr_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_ldr_za_i_m(imm, mem)) } -inst_sme_str_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_STR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_sme_str_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_str_za_i_m(imm, mem)) } -inst_sve_fmla_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } -emit_sve_fmla_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_h_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_fmla_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} } -emit_sve_fmla_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_s_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_fmla_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} } -emit_sve_fmla_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_d_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_fmls_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } -emit_sve_fmls_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_h_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_fmls_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} } -emit_sve_fmls_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_s_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_fmls_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} } -emit_sve_fmls_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_d_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_ld1b_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1b_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_s_z_p_m(rz, rz2, mem)) } -inst_sve_ld1b_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1b_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1h_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1h_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_s_z_p_m(rz, rz2, mem)) } -inst_sve_ld1h_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1h_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1w_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1w_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_s_z_p_m(rz, rz2, mem)) } -inst_sve_ld1w_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1w_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1d_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1d_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sb_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sb_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_s_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sb_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sb_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sh_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sh_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_s_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sh_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sh_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_ld1sw_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ld1sw_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_gather_d_z_p_m(rz, rz2, mem)) } -inst_sve_st1b_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1b_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_s_z_p_m(rz, rz2, mem)) } -inst_sve_st1b_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1b_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_d_z_p_m(rz, rz2, mem)) } -inst_sve_st1h_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1h_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_s_z_p_m(rz, rz2, mem)) } -inst_sve_st1h_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1h_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_d_z_p_m(rz, rz2, mem)) } -inst_sve_st1w_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1w_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_s_z_p_m(rz, rz2, mem)) } -inst_sve_st1w_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1w_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_d_z_p_m(rz, rz2, mem)) } -inst_sve_st1d_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_st1d_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_scatter_d_z_p_m(rz, rz2, mem)) } -inst_sme_ld1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_ld1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1b_tile_i_p_m(imm, rz1, mem)) } -inst_sme_ld1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_ld1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1h_tile_i_p_m(imm, rz1, mem)) } -inst_sme_ld1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_ld1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1w_tile_i_p_m(imm, rz1, mem)) } -inst_sme_ld1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_ld1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1d_tile_i_p_m(imm, rz1, mem)) } -inst_sme_ld1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_ld1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1q_tile_i_p_m(imm, rz1, mem)) } -inst_sme_st1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_st1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1b_tile_i_p_m(imm, rz1, mem)) } -inst_sme_st1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_st1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1h_tile_i_p_m(imm, rz1, mem)) } -inst_sme_st1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_st1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1w_tile_i_p_m(imm, rz1, mem)) } -inst_sme_st1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_st1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1d_tile_i_p_m(imm, rz1, mem)) } -inst_sme_st1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sme_st1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1q_tile_i_p_m(imm, rz1, mem)) } -inst_sme_mova_z_from_tile_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME_MOVA_Z_FROM_TILE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } -emit_sme_mova_z_from_tile_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_sme_mova_z_from_tile_z_p_i(rz, rz2, imm)) } -inst_sme_mova_tile_from_z_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME_MOVA_TILE_FROM_Z, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } -emit_sme_mova_tile_from_z_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_sme_mova_tile_from_z_i_p_z(imm, rz1, rz2)) } -inst_fcmla_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcmla_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4h_r_r_r_i(dst, src, src2, imm)) } -inst_fcmla_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcmla_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_8h_r_r_r_i(dst, src, src2, imm)) } -inst_fcmla_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcmla_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4s_r_r_r_i(dst, src, src2, imm)) } -inst_fcmla_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcmla_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_2d_r_r_r_i(dst, src, src2, imm)) } -inst_fcadd_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcadd_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4h_r_r_r_i(dst, src, src2, imm)) } -inst_fcadd_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcadd_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_8h_r_r_r_i(dst, src, src2, imm)) } -inst_fcadd_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcadd_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4s_r_r_r_i(dst, src, src2, imm)) } -inst_fcadd_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcadd_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_2d_r_r_r_i(dst, src, src2, imm)) } -inst_sve_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sve_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfb_i_p_m(imm, rz1, mem)) } -inst_sve_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sve_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfh_i_p_m(imm, rz1, mem)) } -inst_sve_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sve_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfw_i_p_m(imm, rz1, mem)) } -inst_sve_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_sve_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfd_i_p_m(imm, rz1, mem)) } -inst_sve_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1b_z_p_m(rz, rz2, mem)) } -inst_sve_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1h_z_p_m(rz, rz2, mem)) } -inst_sve_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1w_z_p_m(rz, rz2, mem)) } -inst_sve_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1d_z_p_m(rz, rz2, mem)) } -inst_sve_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1b_z_p_m(rz, rz2, mem)) } -inst_sve_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1h_z_p_m(rz, rz2, mem)) } -inst_sve_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1w_z_p_m(rz, rz2, mem)) } -inst_sve_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sve_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1d_z_p_m(rz, rz2, mem)) } -inst_sve_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } -emit_sve_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_ext_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sve_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sve_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_splice_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_index_ii_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_II, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -emit_sve_index_ii_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sve_index_ii_z_i_i(rz, imm, imm2)) } -inst_sve_index_ir_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_IR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } -emit_sve_index_ir_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_sve_index_ir_z_i_r(rz, imm, src)) } -inst_sve_index_ri_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RI, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } -emit_sve_index_ri_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_sve_index_ri_z_r_i(rz, src, imm)) } -inst_sve_index_rr_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } -emit_sve_index_rr_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_index_rr_z_r_r(rz, src, src2)) } -inst_sve_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_sve_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_sve_pmul_vec_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMUL_VEC, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sve_pmul_vec_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmul_vec_z_z_z(rz, rz2, rz3)) } -inst_sve_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullb_z_z_z(rz, rz2, rz3)) } -inst_sve_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sve_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullt_z_z_z(rz, rz2, rz3)) } -inst_sve_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_sve_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvt_z_p_z(rz, rz2, rz3)) } -inst_sve_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_sve_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvtnt_z_p_z(rz, rz2, rz3)) } -inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } -emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } -inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } -emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } -inst_ldraa_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA_PRE, dst, mem) } -emit_ldraa_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_pre_r_m(dst, mem)) } -inst_ldrab_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB_PRE, dst, mem) } -emit_ldrab_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_pre_r_m(dst, mem)) } -inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } -emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } -inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } -emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } -inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } -inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } -emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } -inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } -emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } -inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } -emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } -inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } -emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) } -inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } -emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } -inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } -emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } -inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } -emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } -inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } -emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } -inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } -emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } -inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } -emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } -inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } -emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } -inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } -emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } -inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } -emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } -inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } -emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } -inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } -emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } -inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } -emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } -inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } -emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } -inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } -emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } -inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } -emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } -inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } -emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } -inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } -emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } -inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } -emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } -inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } -emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } -inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } -emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } -inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } -emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_sve_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } -emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } -inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } -emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } -inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } -emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } -inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } -emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } -inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } -emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } -inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } -emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } -inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } -emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } -inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } -emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_mov_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_mov_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v_alias_r_r(dst, src)) } -inst_not_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_not_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_alias_r_r(dst, src)) } -inst_lsl_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL_IMM, dst, src, imm) } -emit_lsl_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_imm_r_r_i(dst, src, imm)) } -inst_lsr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR_IMM, dst, src, imm) } -emit_lsr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_imm_r_r_i(dst, src, imm)) } -inst_asr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR_IMM, dst, src, imm) } -emit_asr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_imm_r_r_i(dst, src, imm)) } -inst_ror_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR_IMM, dst, src, imm) } -emit_ror_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_imm_r_r_i(dst, src, imm)) } -inst_sve_bfadd_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_bfadd_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfadd_unpred_z_z_z(rz, rz2, rz3)) } -inst_sve_bfsub_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_bfsub_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfsub_unpred_z_z_z(rz, rz2, rz3)) } -inst_sve_bfmul_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_bfmul_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfmul_unpred_z_z_z(rz, rz2, rz3)) } -inst_sve_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_sve_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfclamp_z_z_z(rz, rz2, rz3)) } -inst_sve_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sve_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_sve_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sme2_luti2_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI2_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_sme2_luti2_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti2_b_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sme2_luti4_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI4_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_sme2_luti4_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti4_b_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sme2_ld1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_ld1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_ld1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_st1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_st1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_st1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_st1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x2_z_p_m(rz, rz2, mem)) } -inst_sme2_st1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_st1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_st1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_st1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_sme2_st1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x4_z_p_m(rz, rz2, mem)) } -inst_sme2_zip_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sme2_zip_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_zip_3_z_z_z(rz, rz2, rz3)) } -inst_sme2_zip_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_sme2_zip_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_zip_4_z_z(rz, rz2)) } -inst_sme2_uzp_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sme2_uzp_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_uzp_3_z_z_z(rz, rz2, rz3)) } -inst_sme2_uzp_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_sme2_uzp_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_uzp_4_z_z(rz, rz2)) } -inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } -emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } -inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } -emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } -inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } -emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } -inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } -emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } -inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } -emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } -inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } -emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } -inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } -emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } -inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } -emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } -inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } -emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } -inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } -emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } -inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } -emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } -inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } -emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } -inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } -emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } -inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } -emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } -inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } -emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } -inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } -emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } -inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } -emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } -inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } -emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } -inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } -emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } -inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } -emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } -inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } -emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } -inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } -emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } -inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } -emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } -inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } -emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } -inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } -emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } -inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } -emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } -inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } -emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } -inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } -emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } -inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } -emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } -inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } -emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } -inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } -emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } -inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } -emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } -inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } -emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } -inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } -emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } -inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } -emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } -inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } -emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } -inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } -emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } -inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } -emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } -inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } -emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } -inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } -emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } -inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } -emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } -inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } -emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } -inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } -emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } -inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } -emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } -inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } -emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } -inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } -emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } -inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } -emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } -inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } -emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } -inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } -emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } -inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } -emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } -inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } -emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } -inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } -emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } -inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } -emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } -inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } -emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } -inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } -emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } -inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } -emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } -inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } -emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } -inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } -emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } -inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } -emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } -inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } -emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } -inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } -emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } -inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } -emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } -inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } -emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } -inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } -emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } -inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } -emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } -inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } -emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } -inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } -emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } -inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } -emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } -inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } -emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } -inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } -emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } -inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } -emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } -inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } -emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } -inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } -emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } -inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } -emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } -inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } -emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } -inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } -emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } -inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } -emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } -inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } -emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } -inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } -emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } -inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } -emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } -inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } -emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } -inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } -inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } -inst_prfm_lit_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM_LIT, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } -emit_prfm_lit_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_lit_i_l(imm, label)) } -inst_mov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV_REG, dst, src) } -emit_mov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_reg_r_r(dst, src)) } -inst_mov_bitmask_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV_BITMASK, dst, imm) } -emit_mov_bitmask_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_bitmask_r_i(dst, imm)) } -inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } -emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } -inst_neg_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_neg_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_sr_r_sh(dst, src, src_shift, src_amount)) } -inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } -inst_cmp_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_cmp_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_sr_r_sh(dst, src, src_shift, src_amount)) } -inst_cmp_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } -emit_cmp_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_er_r_ex(dst, src, src_ext, src_amount)) } -inst_cmp_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP_IMM, dst, imm) } -emit_cmp_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_imm_r_i(dst, imm)) } -inst_cmn_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_cmn_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_sr_r_sh(dst, src, src_shift, src_amount)) } -inst_cmn_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } -emit_cmn_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_er_r_ex(dst, src, src_ext, src_amount)) } -inst_cmn_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN_IMM, dst, imm) } -emit_cmn_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_imm_r_i(dst, imm)) } -inst_tst_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_tst_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_sr_r_sh(dst, src, src_shift, src_amount)) } +inst_add_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD, dst, src, imm) } +inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_add_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_add_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_add_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } +emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +emit_add_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_r_r_r(dst, src, src2)) } +emit_add_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_z_z_z(rz, rz2, rz3)) } +emit_add_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } +inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_adds_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_r_r_i(dst, src, imm)) } +emit_adds_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_adds_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_sub_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB, dst, src, imm) } +inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_sub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_sub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } +emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +emit_sub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_r_r_r(dst, src, src2)) } +emit_sub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_z_z_z(rz, rz2, rz3)) } +emit_sub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } +inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_subs_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_r_r_i(dst, src, imm)) } +emit_subs_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_subs_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } +inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } +inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } +inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } +inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } +inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } +inst_and_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_and_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_and_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } +emit_and_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_r_r_r(dst, src, src2)) } +emit_and_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_and_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } +inst_ands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } +emit_ands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } +inst_orr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_orr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_orr_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } +emit_orr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_r_r_r(dst, src, src2)) } +emit_orr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_orr_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } +inst_eor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_eor_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } +emit_eor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_r_r_r(dst, src, src2)) } +emit_eor_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_eor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_bic_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_bic_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_bic_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_bic_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_r_r_r(dst, src, src2)) } +emit_bic_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bic_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_bics_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_bics_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_orn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_orn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_r_r_r(dst, src, src2)) } +emit_orn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } +inst_lsl_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } +emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } +emit_lsl_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } +inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } +inst_lsr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } +emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } +emit_lsr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } +inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } +inst_asr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } +emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } +emit_asr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_asr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_i(dst, src, imm)) } +inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ROR, dst, src, src2) } +inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR, dst, src, imm) } +emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } +emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } +inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } +inst_udiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } +emit_udiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } +inst_sdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } +emit_sdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } +emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } +inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } +emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } +inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } +emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } +inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } +emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } +inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } +emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } +inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } +emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } +inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } +inst_smulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } +emit_smulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } +inst_umulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } +emit_umulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } +inst_clz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } +emit_clz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_z_p_z(rz, rz2, rz3)) } +inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } +inst_cls_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } +emit_cls_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_z_p_z(rz, rz2, rz3)) } +inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } +emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } +inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } +inst_rev_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_rev_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } +emit_rev_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_z_z(rz, rz2)) } +emit_rev_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_p_p(rz, rz2)) } +inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } +emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } +inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } +emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } +inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } +inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } +inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } +inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } +inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } +inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +emit_ccmp_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_r_r_i_c(dst, src, imm, cond)) } +emit_ccmp_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_r_i_i_c(dst, imm, imm2, cond)) } +inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } +inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } +emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } +inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } +emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } +inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } +emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } +inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } +emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } +inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } +emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } +inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } +emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } +inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } +inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } +emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } +emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } +inst_b_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } +emit_b_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_b_cond_c_l(cond, label)) } +inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } +inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } +inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } +inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } +inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } +inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } +emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } +emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } +emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } +emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } +inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } +inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } +emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } +emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } +emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } +inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } +emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } +inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } +emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } +inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } +emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } +inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } +emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } +inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } +emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } +inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } +emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } +inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } +emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } +inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } +emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } +inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } +emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } +inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } +emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } +inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } +emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } +inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } +emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } +inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } +emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } +inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } +emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } +inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } +emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } +inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } +emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } +inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } +emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } +inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } +emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } +inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } +emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } +inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } +emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } +emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } +inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } +emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } +inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } +emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } +inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } +emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } +inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } +emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } +inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } +emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } +inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } +inst_mrs_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MRS, dst, imm) } +emit_mrs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_i(dst, imm)) } +inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } +inst_msr_i_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_reg(src), {}, {}}} } +emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } +emit_msr_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_i_r(imm, src)) } +inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } +inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } +inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } +inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } +inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } +inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } +inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } +inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } +inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } +emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } +inst_fmov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV, dst, src) } +inst_fmov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV, dst, imm) } +emit_fmov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_r_r(dst, src)) } +emit_fmov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_r_i(dst, imm)) } +inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } +inst_fabs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } +emit_fabs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_z_p_z(rz, rz2, rz3)) } +inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } +inst_fneg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } +emit_fneg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_z_p_z(rz, rz2, rz3)) } +inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } +inst_fsqrt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } +emit_fsqrt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_z_p_z(rz, rz2, rz3)) } +inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } +inst_fadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } +emit_fadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_z_z_z(rz, rz2, rz3)) } +emit_fadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } +inst_fsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } +emit_fsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_z_z_z(rz, rz2, rz3)) } +emit_fsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } +inst_fmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } +emit_fmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_z_z_z(rz, rz2, rz3)) } +emit_fmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } +inst_fdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } +emit_fdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } +emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } +inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } +emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } +emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } +emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } +emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } +emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } +inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } +emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } +inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } +inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } +inst_fmax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } +emit_fmax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } +inst_fmin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } +emit_fmin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } +inst_fmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } +emit_fmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } +inst_fminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } +emit_fminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } +emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } +inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } +emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } +inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } +emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } +inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } +emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } +inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } +emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } +inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } +emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } +inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } +emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } +inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } +emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } +inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } +emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } +inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } +emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } +inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } +emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } +inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } +emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } +inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } +emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } +inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } +inst_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } +emit_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_z_p_z(rz, rz2, rz3)) } +inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } +inst_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } +emit_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_z_p_z(rz, rz2, rz3)) } +inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } +inst_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } +emit_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_z_p_z(rz, rz2, rz3)) } +inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } +inst_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } +emit_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_z_p_z(rz, rz2, rz3)) } +inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } +inst_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } +emit_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_z_p_z(rz, rz2, rz3)) } +inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } +inst_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } +emit_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_z_p_z(rz, rz2, rz3)) } +inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } +inst_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } +emit_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_z_p_z(rz, rz2, rz3)) } +inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } +inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } +emit_tst_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_r_sh(dst, src, src_shift, src_amount)) } +inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } +emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } +inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } +emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } +inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } +emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } +inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } +emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } +inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } +emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } +inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } +emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } +inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } +emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } +inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } +emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } +inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } +emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } +inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } +emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } +inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } +emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } +inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } +emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } +inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } +emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } +inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } +emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } +inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } +emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } +inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } +emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } +inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } +emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } +inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } +emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } +inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } +emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } +inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } +emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } +inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } +emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } +inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } +emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } +inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } +emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } +inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } +emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } +inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } +emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } +inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } +emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } +inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } +emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } +inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } +emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } +inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } +emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } +inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } +emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } +inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } +emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } +inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } +emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } +inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } +emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } +inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } +emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } +inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } +emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } +inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } +emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } +inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } +emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } +inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } +emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } +inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } +emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } +inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } +emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } +inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } +emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } +inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } +emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } +inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } +emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } +inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } +emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } +inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } +emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } +inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } +emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } +inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } +emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } +inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } +emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } +inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } +emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } +inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } +emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } +inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } +emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } +inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } +emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } +inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } +emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } +inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } +emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } +inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } +emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } +inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } +emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } +inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } +emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } +inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } +emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } +inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } +emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } +inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } +emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } +inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } +emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } +inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } +emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } +inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } +emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } +inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } +emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } +inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } +emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } +inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } +emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } +inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } +emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } +inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } +emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } +inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } +emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } +inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } +emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } +inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } +emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } +inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } +emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } +inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } +emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } +inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } +emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } +inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } +emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } +inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } +emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } +inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } +emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } +inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } +emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } +inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } +emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } +inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } +emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } +inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } +emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } +inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } +emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } +inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } +emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } +inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } +emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } +inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } +emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } +inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } +emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } +inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } +emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } +inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } +emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } +inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } +emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } +inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } +emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } +inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } +emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } +inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } +emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } +inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } +emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } +inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } +emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } +inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } +emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } +inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } +emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } +inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } +emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } +inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } +emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } +inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } +emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } +inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } +emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } +inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } +emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } +inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } +emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } +inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } +emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } +inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } +emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } +inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } +emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } +inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } +emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } +inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } +emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } +inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } +emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } +inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } +emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } +inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } +emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } +inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } +emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } +inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } +emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } +inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } +emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } +inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } +emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } +inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } +emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } +inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } +emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } +inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } +inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } +emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } +inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } +inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } +inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } +emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } +inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } +emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } +inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } +emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } +inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } +emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } +inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } +emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } +inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } +emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } +inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } +emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } +inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } +emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } +inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } +emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } +inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } +emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } +inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } +emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } +inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } +emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } +inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } +emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } +inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } +emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } +inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } +emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } +inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } +emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } +inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } +emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } +inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } +emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } +inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } +emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } +inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } +emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } +inst_aese_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +inst_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_aese_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_r_r(dst, src)) } +emit_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_z_z(rz, rz2)) } +inst_aesd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +inst_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_aesd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_r_r(dst, src)) } +emit_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_z_z(rz, rz2)) } +inst_aesmc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +inst_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_aesmc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_r_r(dst, src)) } +emit_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_z(rz)) } +inst_aesimc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +inst_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_aesimc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_r_r(dst, src)) } +emit_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_z(rz)) } +inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } +emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } +inst_sha1c_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1c_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_r(dst, src, src2)) } +inst_sha1p_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1p_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_r(dst, src, src2)) } +inst_sha1m_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1m_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_r(dst, src, src2)) } +inst_sha1su0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1su0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_r_r_r(dst, src, src2)) } +inst_sha1su1_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sha1su1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_r_r(dst, src)) } +inst_sha256h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_r(dst, src, src2)) } +inst_sha256h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_r(dst, src, src2)) } +inst_sha256su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sha256su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_r_r(dst, src)) } +inst_sha256su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_r_r_r(dst, src, src2)) } +inst_sha512h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_r(dst, src, src2)) } +inst_sha512h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_r(dst, src, src2)) } +inst_sha512su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } +emit_sha512su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_r_r(dst, src)) } +inst_sha512su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_r_r_r(dst, src, src2)) } +inst_eor3_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } +inst_eor3_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_eor3_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_r_r_r_r(dst, src, src2, src3)) } +emit_eor3_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_bcax_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } +inst_bcax_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bcax_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_r_r_r_r(dst, src, src2, src3)) } +emit_bcax_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_rax1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_rax1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_r_r_r(dst, src, src2)) } +inst_xar_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } +inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +emit_xar_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_r_r_r_i(dst, src, src2, imm)) } +emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sm3partw1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm3partw1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_r_r_r(dst, src, src2)) } +inst_sm3partw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm3partw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_r_r_r(dst, src, src2)) } +inst_sm3ss1_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_v_4s(u8(reg_hw(src3)))}} } +emit_sm3ss1_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_r_r_r_r(dst, src, src2, src3)) } +inst_sm3tt1a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } +emit_sm3tt1a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_r_r_r(dst, src, src2)) } +inst_sm3tt1b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } +emit_sm3tt1b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_r_r_r(dst, src, src2)) } +inst_sm3tt2a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } +emit_sm3tt2a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_r_r_r(dst, src, src2)) } +inst_sm3tt2b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } +emit_sm3tt2b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_r_r_r(dst, src, src2)) } +inst_sm4e_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sm4e_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_r_r(dst, src)) } +inst_sm4ekey_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm4ekey_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_r_r_r(dst, src, src2)) } +inst_pmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_pmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_r_r_r(dst, src, src2)) } +inst_pmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_pmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_r_r_r(dst, src, src2)) } +inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } +inst_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } +emit_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_z_p_z(rz, rz2, rz3)) } +inst_bfdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_r_r_r(dst, src, src2)) } +inst_bfmmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_r_r_r(dst, src, src2)) } +inst_bfmlalb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmlalb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_r_r_r(dst, src, src2)) } +inst_bfmlalt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmlalt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_r_r_r(dst, src, src2)) } +inst_bfcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_bfcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_r_r(dst, src)) } +inst_bfcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_bfcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_r_r(dst, src)) } +inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_mul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } +emit_mul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_mla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_mla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_r_r_r(dst, src, src2)) } +inst_mls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_mls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_r_r_r(dst, src, src2)) } +inst_neg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +inst_neg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_neg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_r_r(dst, src)) } +emit_neg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_z_p_z(rz, rz2, rz3)) } +emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } +inst_abs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +inst_abs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_abs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_r_r(dst, src)) } +emit_abs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_z_p_z(rz, rz2, rz3)) } +inst_shadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_shadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_r_r_r(dst, src, src2)) } +inst_uhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_r_r_r(dst, src, src2)) } +inst_shsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_shsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_r_r_r(dst, src, src2)) } +inst_uhsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uhsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_r_r_r(dst, src, src2)) } +inst_srhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_srhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_r_r_r(dst, src, src2)) } +inst_urhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_urhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_r_r_r(dst, src, src2)) } +inst_sqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_sqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_r_r_r(dst, src, src2)) } +emit_sqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_z_z_z(rz, rz2, rz3)) } +inst_uqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_uqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_uqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_r_r_r(dst, src, src2)) } +emit_uqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_z_z_z(rz, rz2, rz3)) } +inst_sqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_sqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_r_r_r(dst, src, src2)) } +emit_sqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_z_z_z(rz, rz2, rz3)) } +inst_uqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_uqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_uqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_r_r_r(dst, src, src2)) } +emit_uqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_z_z_z(rz, rz2, rz3)) } +inst_smax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_smax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_r_r_r(dst, src, src2)) } +emit_smax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_umax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_r_r_r(dst, src, src2)) } +emit_umax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_smin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_smin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_r_r_r(dst, src, src2)) } +emit_smin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_umin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_r_r_r(dst, src, src2)) } +emit_umin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_sabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_r_r_r(dst, src, src2)) } +emit_sabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_uabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_uabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_uabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_r_r_r(dst, src, src2)) } +emit_uabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_saba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_saba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_r_r_r(dst, src, src2)) } +inst_uaba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uaba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_r_r_r(dst, src, src2)) } +inst_addp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_addp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_r_r_r(dst, src, src2)) } +inst_addv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_addv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_r(dst, src)) } +inst_saddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_saddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_r_r(dst, src)) } +inst_uaddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_uaddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_r_r(dst, src)) } +inst_sadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_sadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_r_r(dst, src)) } +inst_uadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_uadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_r_r(dst, src)) } +inst_saddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_saddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_r(dst, src)) } +inst_uaddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_uaddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_r(dst, src)) } +inst_smaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_smaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_r(dst, src)) } +inst_umaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_umaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_r(dst, src)) } +inst_sminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_sminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_r(dst, src)) } +inst_uminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_uminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_r(dst, src)) } +inst_smaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_smaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_r_r_r(dst, src, src2)) } +inst_umaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_umaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_r_r_r(dst, src, src2)) } +inst_sminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_sminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_r_r_r(dst, src, src2)) } +inst_uminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_r_r_r(dst, src, src2)) } +inst_saddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_saddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_r_r_r(dst, src, src2)) } +inst_saddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_saddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_r_r_r(dst, src, src2)) } +inst_uaddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uaddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_r_r_r(dst, src, src2)) } +inst_uaddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_uaddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_r_r_r(dst, src, src2)) } +inst_ssubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_ssubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_r_r_r(dst, src, src2)) } +inst_ssubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_ssubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_r_r_r(dst, src, src2)) } +inst_usubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_usubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_r_r_r(dst, src, src2)) } +inst_usubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_usubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_r_r_r(dst, src, src2)) } +inst_saddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_saddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_r_r_r(dst, src, src2)) } +inst_saddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_saddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_r_r_r(dst, src, src2)) } +inst_uaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_r_r_r(dst, src, src2)) } +inst_uaddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_uaddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_r_r_r(dst, src, src2)) } +inst_ssubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_ssubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_r_r_r(dst, src, src2)) } +inst_ssubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_ssubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_r_r_r(dst, src, src2)) } +inst_usubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_usubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_r_r_r(dst, src, src2)) } +inst_usubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_usubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_r_r_r(dst, src, src2)) } +inst_raddhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_raddhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_r_r_r(dst, src, src2)) } +inst_raddhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_raddhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_r_r_r(dst, src, src2)) } +inst_rsubhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_rsubhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_r_r_r(dst, src, src2)) } +inst_rsubhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_rsubhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_r_r_r(dst, src, src2)) } +inst_addhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_addhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_r_r_r(dst, src, src2)) } +inst_addhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_addhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_r_r_r(dst, src, src2)) } +inst_subhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_subhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_r_r_r(dst, src, src2)) } +inst_subhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_subhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_r_r_r(dst, src, src2)) } +inst_xtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_xtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_r_r(dst, src)) } +inst_xtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_xtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_r_r(dst, src)) } +inst_sqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_r_r(dst, src)) } +inst_sqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_r_r(dst, src)) } +inst_uqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_uqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_r_r(dst, src)) } +inst_uqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_uqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_r_r(dst, src)) } +inst_sqxtun_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtun_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_r_r(dst, src)) } +inst_sqxtun2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtun2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_r_r(dst, src)) } +inst_smull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_smull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_r_r_r(dst, src, src2)) } +inst_smull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_smull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_r_r_r(dst, src, src2)) } +inst_umull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_umull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_r_r_r(dst, src, src2)) } +inst_umull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_umull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_r_r_r(dst, src, src2)) } +inst_smlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_smlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_r_r_r(dst, src, src2)) } +inst_smlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_smlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_r_r_r(dst, src, src2)) } +inst_umlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_umlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_r_r_r(dst, src, src2)) } +inst_umlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_umlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_r_r_r(dst, src, src2)) } +inst_smlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_smlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_r_r_r(dst, src, src2)) } +inst_smlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_smlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_r_r_r(dst, src, src2)) } +inst_umlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_umlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_r_r_r(dst, src, src2)) } +inst_umlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_umlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_r_r_r(dst, src, src2)) } +inst_sqdmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } +emit_sqdmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_r_r_r(dst, src, src2)) } +inst_sqdmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_sqdmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_r_r_r(dst, src, src2)) } +inst_sqdmlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } +emit_sqdmlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_r_r_r(dst, src, src2)) } +inst_sqdmlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_sqdmlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_r_r_r(dst, src, src2)) } +inst_sqdmlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } +emit_sqdmlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_r_r_r(dst, src, src2)) } +inst_sqdmlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_sqdmlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_r_r_r(dst, src, src2)) } +inst_sqdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } +emit_sqdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_r_r_r(dst, src, src2)) } +inst_sqrdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } +emit_sqrdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_r_r_r(dst, src, src2)) } +inst_sdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_sdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_r_r_r(dst, src, src2)) } +inst_udot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_udot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_r_r_r(dst, src, src2)) } +inst_usdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_usdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_r_r_r(dst, src, src2)) } +inst_fmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +inst_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmla_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_fmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_r_r_r(dst, src, src2)) } +emit_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmla_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_z_z_z_i(rz, rz2, rz3, imm)) } +inst_fmls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +inst_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmls_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_fmls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_r_r_r(dst, src, src2)) } +emit_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmls_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_z_z_z_i(rz, rz2, rz3, imm)) } +inst_fmulx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fmulx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_r_r_r(dst, src, src2)) } +inst_fmaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fmaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_r_r_r(dst, src, src2)) } +inst_fminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_r_r_r(dst, src, src2)) } +inst_fmaxnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fmaxnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_r_r_r(dst, src, src2)) } +inst_fminnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fminnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_r_r_r(dst, src, src2)) } +inst_fmaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fmaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_r(dst, src)) } +inst_fminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_r(dst, src)) } +inst_fmaxnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fmaxnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_r(dst, src)) } +inst_fminnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fminnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_r(dst, src)) } +inst_frecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_frecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_r_r(dst, src)) } +inst_frsqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_frsqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_r_r(dst, src)) } +inst_frecps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +inst_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_frecps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_r_r_r(dst, src, src2)) } +emit_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_z_z_z(rz, rz2, rz3)) } +inst_frsqrts_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +inst_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_frsqrts_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_r_r_r(dst, src, src2)) } +emit_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_z_z_z(rz, rz2, rz3)) } +inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } +inst_frecpx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } +emit_frecpx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_z_p_z(rz, rz2, rz3)) } +inst_faddp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_faddp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_r_r_r(dst, src, src2)) } +inst_fcvtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), {}, {}}} } +emit_fcvtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_r_r(dst, src)) } +inst_fcvtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_fcvtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_r_r(dst, src)) } +inst_fcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_r_r(dst, src)) } +inst_fcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_fcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_r_r(dst, src)) } +inst_fcvtxn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } +emit_fcvtxn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_r_r(dst, src)) } +inst_fcvtxn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } +emit_fcvtxn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_r_r(dst, src)) } +inst_fcmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +inst_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_r_r_r(dst, src, src2)) } +emit_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +inst_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_r_r_r(dst, src, src2)) } +emit_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +inst_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_r_r_r(dst, src, src2)) } +emit_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +inst_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fcmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_r_r(dst, src)) } +emit_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_p_p_z(rz, rz2, rz3)) } +inst_fcmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +inst_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fcmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_r_r(dst, src)) } +emit_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_p_p_z(rz, rz2, rz3)) } +inst_facge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_facge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_r_r_r(dst, src, src2)) } +inst_facgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_facgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_r_r_r(dst, src, src2)) } +inst_cmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_r_r_r(dst, src, src2)) } +inst_cmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_cmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_r_r_r(dst, src, src2)) } +inst_cmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_r_r_r(dst, src, src2)) } +inst_cmhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_r_r_r(dst, src, src2)) } +inst_cmhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_cmhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_r_r_r(dst, src, src2)) } +inst_cmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_cmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_r_r(dst, src)) } +inst_cmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_cmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_r_r(dst, src)) } +inst_cmtst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_cmtst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_r_r_r(dst, src, src2)) } +inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } +inst_bit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_r_r_r(dst, src, src2)) } +inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) } +inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +inst_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) } +emit_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_shl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_shl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_r_r_i(dst, src, imm)) } +inst_sqshl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_r_r_i(dst, src, imm)) } +inst_sqshlu_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshlu_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_r_r_i(dst, src, imm)) } +inst_srshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_srshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_r_r_r(dst, src, src2)) } +inst_urshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_urshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_r_r_r(dst, src, src2)) } +inst_sshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_r_r_i(dst, src, imm)) } +inst_ushr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_ushr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_r_r_i(dst, src, imm)) } +inst_ssra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_ssra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_r_r_i(dst, src, imm)) } +inst_usra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_usra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_r_r_i(dst, src, imm)) } +inst_srshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_srshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_r_r_i(dst, src, imm)) } +inst_urshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_urshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_r_r_i(dst, src, imm)) } +inst_srsra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_srsra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_r_r_i(dst, src, imm)) } +inst_ursra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_ursra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_r_r_i(dst, src, imm)) } +inst_sshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_sshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_r_r_r(dst, src, src2)) } +inst_ushl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_ushl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_r_r_r(dst, src, src2)) } +inst_sli_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sli_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_r_r_i(dst, src, imm)) } +inst_sri_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sri_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_r_r_i(dst, src, imm)) } +inst_sshll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sshll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_r_r_i(dst, src, imm)) } +inst_sshll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sshll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_r_r_i(dst, src, imm)) } +inst_ushll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_ushll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_r_r_i(dst, src, imm)) } +inst_ushll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_ushll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_r_r_i(dst, src, imm)) } +inst_sxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_sxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_r_r(dst, src)) } +inst_sxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_sxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_r_r(dst, src)) } +inst_uxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_uxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_r_r(dst, src)) } +inst_uxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_uxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_r_r(dst, src)) } +inst_shrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_shrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_r_r_i(dst, src, imm)) } +inst_shrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_shrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_r_r_i(dst, src, imm)) } +inst_rshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_rshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_r_r_i(dst, src, imm)) } +inst_rshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_rshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_r_r_i(dst, src, imm)) } +inst_sqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_r_r_i(dst, src, imm)) } +inst_sqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_r_r_i(dst, src, imm)) } +inst_uqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_uqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_r_r_i(dst, src, imm)) } +inst_uqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_uqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_r_r_i(dst, src, imm)) } +inst_sqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_r_r_i(dst, src, imm)) } +inst_sqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_r_r_i(dst, src, imm)) } +inst_uqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_uqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_r_r_i(dst, src, imm)) } +inst_uqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_uqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_r_r_i(dst, src, imm)) } +inst_sqshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_r_r_i(dst, src, imm)) } +inst_sqshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_r_r_i(dst, src, imm)) } +inst_sqrshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqrshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_r_r_i(dst, src, imm)) } +inst_sqrshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +emit_sqrshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_r_r_i(dst, src, imm)) } +inst_dup_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_elem_b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } +inst_dup_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_reg(src), {}, {}}} } +inst_dup_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_dup_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_r_r_i(dst, src, imm)) } +emit_dup_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_r_r(dst, src)) } +emit_dup_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_z_r(rz, src)) } +inst_ins_r_i_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_v_elem_b(u8(reg_hw(src))), op_imm(imm2, 4)}} } +inst_ins_r_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_reg(src), {}}} } +emit_ins_r_i_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_r_i_r_i(dst, imm, src, imm2)) } +emit_ins_r_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_r_i_r(dst, imm, src)) } +inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +inst_mov_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_mov_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } +emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } +emit_mov_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_z_p_z(rz, rz2, rz3)) } +emit_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_p_p_p(rz, rz2, rz3)) } +emit_mov_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_p_p(rz, rz2)) } +emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } +inst_ext_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), op_imm(imm, 4)}} } +inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +emit_ext_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_r_r_r_i(dst, src, src2, imm)) } +emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } +inst_tbl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_r_r_r(dst, src, src2)) } +emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } +inst_tbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_r_r_r(dst, src, src2)) } +emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } +inst_zip1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_zip1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_zip1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_r_r_r(dst, src, src2)) } +emit_zip1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_z_z_z(rz, rz2, rz3)) } +emit_zip1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_p_p_p(rz, rz2, rz3)) } +inst_zip2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_zip2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_zip2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_r_r_r(dst, src, src2)) } +emit_zip2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_z_z_z(rz, rz2, rz3)) } +emit_zip2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_p_p_p(rz, rz2, rz3)) } +inst_uzp1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_uzp1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_uzp1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_r_r_r(dst, src, src2)) } +emit_uzp1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_z_z_z(rz, rz2, rz3)) } +emit_uzp1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_p_p_p(rz, rz2, rz3)) } +inst_uzp2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_uzp2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_uzp2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_r_r_r(dst, src, src2)) } +emit_uzp2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_z_z_z(rz, rz2, rz3)) } +emit_uzp2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_p_p_p(rz, rz2, rz3)) } +inst_trn1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_trn1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_trn1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_r_r_r(dst, src, src2)) } +emit_trn1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_z_z_z(rz, rz2, rz3)) } +emit_trn1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_p_p_p(rz, rz2, rz3)) } +inst_trn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +inst_trn2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_trn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_r_r_r(dst, src, src2)) } +emit_trn2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_z_z_z(rz, rz2, rz3)) } +emit_trn2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_p_p_p(rz, rz2, rz3)) } +inst_not_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +inst_not_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_not_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_r_r(dst, src)) } +emit_not_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_p_p_p(rz, rz2, rz3)) } +inst_rev64_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_rev64_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_r_r(dst, src)) } +inst_cnt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +inst_cnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_cnt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_r_r(dst, src)) } +emit_cnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_z_p_z(rz, rz2, rz3)) } +inst_urecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_urecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_r_r(dst, src)) } +inst_ursqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } +emit_ursqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_r_r(dst, src)) } +inst_movi_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } +emit_movi_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_r_i(dst, imm)) } +inst_mvni_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } +emit_mvni_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_r_i(dst, imm)) } +inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_ld1_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) } +emit_ld1_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_r_i_m(dst, imm, mem)) } +inst_ld2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_ld2_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_r_m(dst, mem)) } +emit_ld2_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_r_i_m(dst, imm, mem)) } +inst_ld3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_ld3_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_r_m(dst, mem)) } +emit_ld3_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_r_i_m(dst, imm, mem)) } +inst_ld4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_ld4_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_r_m(dst, mem)) } +emit_ld4_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_r_i_m(dst, imm, mem)) } +inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_st1_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_r_m(dst, mem)) } +emit_st1_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_r_i_m(dst, imm, mem)) } +inst_st2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_st2_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_r_m(dst, mem)) } +emit_st2_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_r_i_m(dst, imm, mem)) } +inst_st3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_st3_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_r_m(dst, mem)) } +emit_st3_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_r_i_m(dst, imm, mem)) } +inst_st4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +inst_st4_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_r_m(dst, mem)) } +emit_st4_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_r_i_m(dst, imm, mem)) } +inst_ld1r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_ld1r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_r_m(dst, mem)) } +inst_ld2r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_ld2r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_r_m(dst, mem)) } +inst_ld3r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_ld3r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_r_m(dst, mem)) } +inst_ld4r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_ld4r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_r_m(dst, mem)) } +inst_subr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_subr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_asrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_asrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_lslr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_lslr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_lsrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_lsrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_z_z_z(rz, rz2, rz3)) } +inst_fsubr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fsubr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fdivr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fdivr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_nand_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nand_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sel_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sel_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orrs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orrs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orns_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orns_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_movs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_movs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_p_p_p(rz, rz2, rz3)) } +inst_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_p_i(rz, imm)) } +inst_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_p_i(rz, imm)) } +inst_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_p(rz)) } +inst_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_p_p_p(rz, rz2, rz3)) } +inst_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_p_p_p(rz, rz2, rz3)) } +inst_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_p_p_p(rz, rz2, rz3)) } +inst_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_p_p_p(rz, rz2, rz3)) } +inst_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_p_p_p(rz, rz2, rz3)) } +inst_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_p_p_p(rz, rz2, rz3)) } +inst_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_p(rz)) } +inst_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_p(rz)) } +inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } +emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } +inst_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_z_r(rz, src)) } +inst_cpy_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +emit_cpy_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_z_p_r(rz, rz2, src)) } +inst_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_z_p_z(rz, rz2, rz3)) } +inst_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_z_p_m(rz, rz2, mem)) } +emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } +inst_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_z_p_m(rz, rz2, mem)) } +emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } +inst_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_z_p_m(rz, rz2, mem)) } +emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } +inst_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_z_p_m(rz, rz2, mem)) } +emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } +inst_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_z_p_m(rz, rz2, mem)) } +inst_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_z_p_m(rz, rz2, mem)) } +inst_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_z_p_m(rz, rz2, mem)) } +inst_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_z_p_m(rz, rz2, mem)) } +emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } +inst_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_z_p_m(rz, rz2, mem)) } +emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } +inst_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_z_p_m(rz, rz2, mem)) } +emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } +inst_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_z_p_m(rz, rz2, mem)) } +emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } +inst_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_z_p_m(rz, rz2, mem)) } +inst_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_z_p_m(rz, rz2, mem)) } +inst_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_z_p_m(rz, rz2, mem)) } +inst_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_z_p_m(rz, rz2, mem)) } +inst_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_p_r_r(rz, src, src2)) } +inst_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_p_r_r(rz, src, src2)) } +inst_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_p_r_r(rz, src, src2)) } +inst_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_p_r_r(rz, src, src2)) } +inst_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_p_r_r(rz, src, src2)) } +inst_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_p_r_r(rz, src, src2)) } +inst_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_p_r_r(rz, src, src2)) } +inst_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_p_r_r(rz, src, src2)) } +inst_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_z_z_z(rz, rz2, rz3)) } +inst_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_z_z_z(rz, rz2, rz3)) } +inst_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_z_z_z(rz, rz2, rz3)) } +inst_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_z_z_z(rz, rz2, rz3)) } +inst_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_z_z_z(rz, rz2, rz3)) } +inst_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_z_z_z(rz, rz2, rz3)) } +inst_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_z_z_z(rz, rz2, rz3)) } +inst_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_z_z_z(rz, rz2, rz3)) } +inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } +emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } +inst_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTOP) } +emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } +inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } +emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } +inst_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } +emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } +inst_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } +inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } +inst_mova_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } +inst_mova_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +emit_mova_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_z_p_i(rz, rz2, imm)) } +emit_mova_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_z(imm, rz1, rz2)) } +inst_fcmla_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcmla_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_r_r_r_i(dst, src, src2, imm)) } +inst_fcadd_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcadd_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_r_r_r_i(dst, src, src2, imm)) } +inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfb_i_p_m(imm, rz1, mem)) } +inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfh_i_p_m(imm, rz1, mem)) } +inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } +inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } +inst_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_z_p_m(rz, rz2, mem)) } +inst_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_z_p_m(rz, rz2, mem)) } +inst_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_z_p_m(rz, rz2, mem)) } +inst_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_z_p_m(rz, rz2, mem)) } +inst_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_z_p_m(rz, rz2, mem)) } +inst_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_z_p_m(rz, rz2, mem)) } +inst_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_z_p_m(rz, rz2, mem)) } +inst_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_z_p_m(rz, rz2, mem)) } +inst_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_index_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } +emit_index_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_z_i_i(rz, imm, imm2)) } +emit_index_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_z_i_r(rz, imm, src)) } +emit_index_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_z_r_i(rz, src, imm)) } +emit_index_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_z_r_r(rz, src, src2)) } +inst_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_pmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_pmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_z_z_z(rz, rz2, rz3)) } +inst_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_z_z_z(rz, rz2, rz3)) } +inst_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_z_z_z(rz, rz2, rz3)) } +inst_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_z_p_z(rz, rz2, rz3)) } +inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } +emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } +inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } +emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } +inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } +emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } +inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } +emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } +inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } +inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } +emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } +inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } +emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } +inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } +emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } +inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } +emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) } +inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } +emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } +inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } +emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } +inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } +emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } +inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } +emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } +inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } +emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } +inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } +emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } +inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } +emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } +inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } +emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } +inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } +emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } +inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } +emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } +inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } +emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } +inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } +emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } +inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } +emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } +inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } +emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } +inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } +emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } +inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } +emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } +inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } +emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } +inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } +emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } +inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } +emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } +inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } +emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } +inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } +emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } +inst_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_z_z_z(rz, rz2, rz3)) } +inst_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_z_z_z(rz, rz2, rz3)) } +inst_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_z_z_z(rz, rz2, rz3)) } +inst_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } +emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } +inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } +emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } +inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } +emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } +inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } +emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } +inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } +emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } +inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } +emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } +inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } +emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } +inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } +emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } +inst_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_z_z_z(rz, rz2, rz3)) } +inst_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_luti2_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti2_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_z_z_z_i(rz, rz2, rz3, imm)) } +inst_luti4_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti4_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_z_z_z_i(rz, rz2, rz3, imm)) } +inst_zip_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_zip_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_z_z_z(rz, rz2, rz3)) } +emit_zip_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_z_z(rz, rz2)) } +inst_uzp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_uzp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_z_z_z(rz, rz2, rz3)) } +emit_uzp_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_z_z(rz, rz2)) } +inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } +emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } +inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } +emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } +inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } +emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } +inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } +emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } +inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } +emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } +inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } +emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } +inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } +emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } +inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } +emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } +inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } +emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } +inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } +emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } +inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } +emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } +inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } +emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } +inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } +emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } +inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } +emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } +inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } +emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } +inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } +emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } +inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } +emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } +inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } +emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } +inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } +emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } +inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } +emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } +inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } +emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } +inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } +emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } +inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } +emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } +inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } +emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } +inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } +emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } +inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } +emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } +inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } +emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } +inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } +emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } +inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } +emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } +inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } +emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } +inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } +emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } +inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } +emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } +inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } +emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } +inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } +emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } +inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } +emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } +inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } +emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } +inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } +emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } +inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } +emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } +inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } +emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } +inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } +emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } +inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } +emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } +inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } +emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } +inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } +emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } +inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } +emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } +inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } +emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } +inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } +emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } +inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } +emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } +inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } +emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } +inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } +emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } +inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } +emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } +inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } +emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } +inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } +emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } +inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } +emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } +inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } +emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } +inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } +emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } +inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } +emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } +inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } +emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } +inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } +emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } +inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } +emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } +inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } +emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } +inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } +emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } +inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } +emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } +inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } +emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } +inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } +emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } +inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } +emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } +inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } +emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } +inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } +emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } +inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } +emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } +inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } +emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } +inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } +emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } +inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } +emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } +inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } +emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } +inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } +emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } +inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } +emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } +inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } +emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } +inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } +emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } +inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } +emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } +inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } +emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } +inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } +emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } +inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } +emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } +inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } +emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } +inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } +emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } +emit_prfm_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_i_l(imm, label)) } +inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } +inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } +inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmp_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP, dst, imm) } +emit_cmp_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_r_sh(dst, src, src_shift, src_amount)) } +emit_cmp_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_r_ex(dst, src, src_ext, src_amount)) } +emit_cmp_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_i(dst, imm)) } +inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmn_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN, dst, imm) } +emit_cmn_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_r_sh(dst, src, src_shift, src_amount)) } +emit_cmn_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_r_ex(dst, src, src_ext, src_amount)) } +emit_cmn_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_i(dst, imm)) } // ============================================================================= // Overload Groups // ============================================================================= -inst_add_imm :: inst_add_imm_r_r_i -emit_add_imm :: emit_add_imm_r_r_i -inst_adds_imm :: inst_adds_imm_r_r_i -emit_adds_imm :: emit_adds_imm_r_r_i -inst_sub_imm :: inst_sub_imm_r_r_i -emit_sub_imm :: emit_sub_imm_r_r_i -inst_subs_imm :: inst_subs_imm_r_r_i -emit_subs_imm :: emit_subs_imm_r_r_i -inst_movz :: inst_movz_r_i_i -emit_movz :: emit_movz_r_i_i -inst_movn :: inst_movn_r_i_i -emit_movn :: emit_movn_r_i_i -inst_movk :: inst_movk_r_i_i -emit_movk :: emit_movk_r_i_i -inst_adr :: inst_adr_r_l -emit_adr :: emit_adr_r_l -inst_adrp :: inst_adrp_r_l -emit_adrp :: emit_adrp_r_l -inst_add_sr :: inst_add_sr_r_r_sh -emit_add_sr :: emit_add_sr_r_r_sh -inst_adds_sr :: inst_adds_sr_r_r_sh -emit_adds_sr :: emit_adds_sr_r_r_sh -inst_sub_sr :: inst_sub_sr_r_r_sh -emit_sub_sr :: emit_sub_sr_r_r_sh -inst_subs_sr :: inst_subs_sr_r_r_sh -emit_subs_sr :: emit_subs_sr_r_r_sh -inst_and_sr :: inst_and_sr_r_r_sh -emit_and_sr :: emit_and_sr_r_r_sh -inst_ands_sr :: inst_ands_sr_r_r_sh -emit_ands_sr :: emit_ands_sr_r_r_sh -inst_orr_sr :: inst_orr_sr_r_r_sh -emit_orr_sr :: emit_orr_sr_r_r_sh -inst_eor_sr :: inst_eor_sr_r_r_sh -emit_eor_sr :: emit_eor_sr_r_r_sh -inst_bic_sr :: inst_bic_sr_r_r_sh -emit_bic_sr :: emit_bic_sr_r_r_sh -inst_bics_sr :: inst_bics_sr_r_r_sh -emit_bics_sr :: emit_bics_sr_r_r_sh -inst_orn_sr :: inst_orn_sr_r_r_sh -emit_orn_sr :: emit_orn_sr_r_r_sh -inst_eon_sr :: inst_eon_sr_r_r_sh -emit_eon_sr :: emit_eon_sr_r_r_sh -inst_add_er :: inst_add_er_r_r_ex -emit_add_er :: emit_add_er_r_r_ex -inst_adds_er :: inst_adds_er_r_r_ex -emit_adds_er :: emit_adds_er_r_r_ex -inst_sub_er :: inst_sub_er_r_r_ex -emit_sub_er :: emit_sub_er_r_r_ex -inst_subs_er :: inst_subs_er_r_r_ex -emit_subs_er :: emit_subs_er_r_r_ex -inst_lslv :: inst_lslv_r_r_r -emit_lslv :: emit_lslv_r_r_r -inst_lsrv :: inst_lsrv_r_r_r -emit_lsrv :: emit_lsrv_r_r_r -inst_asrv :: inst_asrv_r_r_r -emit_asrv :: emit_asrv_r_r_r -inst_rorv :: inst_rorv_r_r_r -emit_rorv :: emit_rorv_r_r_r -inst_udiv :: inst_udiv_r_r_r -emit_udiv :: emit_udiv_r_r_r -inst_sdiv :: inst_sdiv_r_r_r -emit_sdiv :: emit_sdiv_r_r_r -inst_madd :: inst_madd_r_r_r_r -emit_madd :: emit_madd_r_r_r_r -inst_msub :: inst_msub_r_r_r_r -emit_msub :: emit_msub_r_r_r_r -inst_smaddl :: inst_smaddl_r_r_r_r -emit_smaddl :: emit_smaddl_r_r_r_r -inst_smsubl :: inst_smsubl_r_r_r_r -emit_smsubl :: emit_smsubl_r_r_r_r -inst_umaddl :: inst_umaddl_r_r_r_r -emit_umaddl :: emit_umaddl_r_r_r_r -inst_umsubl :: inst_umsubl_r_r_r_r -emit_umsubl :: emit_umsubl_r_r_r_r -inst_smulh :: inst_smulh_r_r_r -emit_smulh :: emit_smulh_r_r_r -inst_umulh :: inst_umulh_r_r_r -emit_umulh :: emit_umulh_r_r_r -inst_clz :: inst_clz_r_r -emit_clz :: emit_clz_r_r -inst_cls :: inst_cls_r_r -emit_cls :: emit_cls_r_r -inst_rbit :: inst_rbit_r_r -emit_rbit :: emit_rbit_r_r -inst_rev :: inst_rev_r_r -emit_rev :: emit_rev_r_r -inst_rev16 :: inst_rev16_r_r -emit_rev16 :: emit_rev16_r_r -inst_rev32 :: inst_rev32_r_r -emit_rev32 :: emit_rev32_r_r -inst_csel :: inst_csel_r_r_r_c -emit_csel :: emit_csel_r_r_r_c -inst_csinc :: inst_csinc_r_r_r_c -emit_csinc :: emit_csinc_r_r_r_c -inst_csinv :: inst_csinv_r_r_r_c -emit_csinv :: emit_csinv_r_r_r_c -inst_csneg :: inst_csneg_r_r_r_c -emit_csneg :: emit_csneg_r_r_r_c -inst_ccmp_reg :: inst_ccmp_reg_r_r_i_c -emit_ccmp_reg :: emit_ccmp_reg_r_r_i_c -inst_ccmp_imm :: inst_ccmp_imm_r_i_i_c -emit_ccmp_imm :: emit_ccmp_imm_r_i_i_c -inst_ccmn_reg :: inst_ccmn_reg_r_r_i_c -emit_ccmn_reg :: emit_ccmn_reg_r_r_i_c -inst_ccmn_imm :: inst_ccmn_imm_r_i_i_c -emit_ccmn_imm :: emit_ccmn_imm_r_i_i_c -inst_extr :: inst_extr_r_r_r_i -emit_extr :: emit_extr_r_r_r_i -inst_b :: inst_b_l -emit_b :: emit_b_l -inst_bl :: inst_bl_l -emit_bl :: emit_bl_l -inst_br :: inst_br_r -emit_br :: emit_br_r -inst_blr :: inst_blr_r -emit_blr :: emit_blr_r -inst_ret :: proc{ inst_ret_r, inst_ret_none } -emit_ret :: proc{ emit_ret_r, emit_ret_none } -inst_b_cond :: inst_b_cond_c_l -emit_b_cond :: emit_b_cond_c_l -inst_cbz :: inst_cbz_r_l -emit_cbz :: emit_cbz_r_l -inst_cbnz :: inst_cbnz_r_l -emit_cbnz :: emit_cbnz_r_l -inst_tbz :: inst_tbz_r_i_l -emit_tbz :: emit_tbz_r_i_l -inst_tbnz :: inst_tbnz_r_i_l -emit_tbnz :: emit_tbnz_r_i_l -inst_ldr :: inst_ldr_r_m -emit_ldr :: emit_ldr_r_m -inst_str :: inst_str_r_m -emit_str :: emit_str_r_m -inst_ldrb :: inst_ldrb_r_m -emit_ldrb :: emit_ldrb_r_m -inst_strb :: inst_strb_r_m -emit_strb :: emit_strb_r_m -inst_ldrsb :: inst_ldrsb_r_m -emit_ldrsb :: emit_ldrsb_r_m -inst_ldrh :: inst_ldrh_r_m -emit_ldrh :: emit_ldrh_r_m -inst_strh :: inst_strh_r_m -emit_strh :: emit_strh_r_m -inst_ldrsh :: inst_ldrsh_r_m -emit_ldrsh :: emit_ldrsh_r_m -inst_ldrsw :: inst_ldrsw_r_m -emit_ldrsw :: emit_ldrsw_r_m -inst_ldp :: inst_ldp_r_r_m -emit_ldp :: emit_ldp_r_r_m -inst_stp :: inst_stp_r_r_m -emit_stp :: emit_stp_r_r_m -inst_ldpsw :: inst_ldpsw_r_r_m -emit_ldpsw :: emit_ldpsw_r_r_m -inst_ldr_lit :: inst_ldr_lit_r_l -emit_ldr_lit :: emit_ldr_lit_r_l -inst_ldar :: inst_ldar_r_m -emit_ldar :: emit_ldar_r_m -inst_stlr :: inst_stlr_r_m -emit_stlr :: emit_stlr_r_m -inst_ldarb :: inst_ldarb_r_m -emit_ldarb :: emit_ldarb_r_m -inst_stlrb :: inst_stlrb_r_m -emit_stlrb :: emit_stlrb_r_m -inst_ldarh :: inst_ldarh_r_m -emit_ldarh :: emit_ldarh_r_m -inst_stlrh :: inst_stlrh_r_m -emit_stlrh :: emit_stlrh_r_m -inst_ldxr :: inst_ldxr_r_m -emit_ldxr :: emit_ldxr_r_m -inst_stxr :: inst_stxr_r_r_m -emit_stxr :: emit_stxr_r_r_m -inst_ldaxr :: inst_ldaxr_r_m -emit_ldaxr :: emit_ldaxr_r_m -inst_stlxr :: inst_stlxr_r_r_m -emit_stlxr :: emit_stlxr_r_r_m -inst_nop :: inst_nop_none -emit_nop :: emit_nop_none -inst_yield :: inst_yield_none -emit_yield :: emit_yield_none -inst_wfe :: inst_wfe_none -emit_wfe :: emit_wfe_none -inst_wfi :: inst_wfi_none -emit_wfi :: emit_wfi_none -inst_sev :: inst_sev_none -emit_sev :: emit_sev_none -inst_sevl :: inst_sevl_none -emit_sevl :: emit_sevl_none -inst_hint :: inst_hint_i -emit_hint :: emit_hint_i -inst_mrs :: inst_mrs_r_i -emit_mrs :: emit_mrs_r_i -inst_msr_imm :: inst_msr_imm_i_i -emit_msr_imm :: emit_msr_imm_i_i -inst_msr_reg :: inst_msr_reg_i_r -emit_msr_reg :: emit_msr_reg_i_r -inst_isb :: inst_isb_i -emit_isb :: emit_isb_i -inst_dsb :: inst_dsb_i -emit_dsb :: emit_dsb_i -inst_dmb :: inst_dmb_i -emit_dmb :: emit_dmb_i -inst_svc :: inst_svc_i -emit_svc :: emit_svc_i -inst_hvc :: inst_hvc_i -emit_hvc :: emit_hvc_i -inst_smc :: inst_smc_i -emit_smc :: emit_smc_i -inst_brk :: inst_brk_i -emit_brk :: emit_brk_i -inst_hlt :: inst_hlt_i -emit_hlt :: emit_hlt_i -inst_eret :: inst_eret_none -emit_eret :: emit_eret_none -inst_fmov_reg :: inst_fmov_reg_r_r -emit_fmov_reg :: emit_fmov_reg_r_r -inst_fmov_imm :: inst_fmov_imm_r_i -emit_fmov_imm :: emit_fmov_imm_r_i -inst_fmov_gen :: inst_fmov_gen_r_r -emit_fmov_gen :: emit_fmov_gen_r_r -inst_fabs :: inst_fabs_r_r -emit_fabs :: emit_fabs_r_r -inst_fneg :: inst_fneg_r_r -emit_fneg :: emit_fneg_r_r -inst_fsqrt :: inst_fsqrt_r_r -emit_fsqrt :: emit_fsqrt_r_r -inst_fadd :: inst_fadd_r_r_r -emit_fadd :: emit_fadd_r_r_r -inst_fsub :: inst_fsub_r_r_r -emit_fsub :: emit_fsub_r_r_r -inst_fmul :: inst_fmul_r_r_r -emit_fmul :: emit_fmul_r_r_r -inst_fdiv :: inst_fdiv_r_r_r -emit_fdiv :: emit_fdiv_r_r_r -inst_fnmul :: inst_fnmul_r_r_r -emit_fnmul :: emit_fnmul_r_r_r -inst_fmadd :: inst_fmadd_r_r_r_r -emit_fmadd :: emit_fmadd_r_r_r_r -inst_fmsub :: inst_fmsub_r_r_r_r -emit_fmsub :: emit_fmsub_r_r_r_r -inst_fnmadd :: inst_fnmadd_r_r_r_r -emit_fnmadd :: emit_fnmadd_r_r_r_r -inst_fnmsub :: inst_fnmsub_r_r_r_r -emit_fnmsub :: emit_fnmsub_r_r_r_r -inst_fcmp :: inst_fcmp_r_r -emit_fcmp :: emit_fcmp_r_r -inst_fcmpe :: inst_fcmpe_r_r -emit_fcmpe :: emit_fcmpe_r_r -inst_fcsel :: inst_fcsel_r_r_r_c -emit_fcsel :: emit_fcsel_r_r_r_c -inst_fmax :: inst_fmax_r_r_r -emit_fmax :: emit_fmax_r_r_r -inst_fmin :: inst_fmin_r_r_r -emit_fmin :: emit_fmin_r_r_r -inst_fmaxnm :: inst_fmaxnm_r_r_r -emit_fmaxnm :: emit_fmaxnm_r_r_r -inst_fminnm :: inst_fminnm_r_r_r -emit_fminnm :: emit_fminnm_r_r_r -inst_fcvt :: inst_fcvt_r_r -emit_fcvt :: emit_fcvt_r_r -inst_scvtf :: inst_scvtf_r_r -emit_scvtf :: emit_scvtf_r_r -inst_ucvtf :: inst_ucvtf_r_r -emit_ucvtf :: emit_ucvtf_r_r -inst_fcvtzs :: inst_fcvtzs_r_r -emit_fcvtzs :: emit_fcvtzs_r_r -inst_fcvtzu :: inst_fcvtzu_r_r -emit_fcvtzu :: emit_fcvtzu_r_r -inst_fcvtas :: inst_fcvtas_r_r -emit_fcvtas :: emit_fcvtas_r_r -inst_fcvtau :: inst_fcvtau_r_r -emit_fcvtau :: emit_fcvtau_r_r -inst_fcvtns :: inst_fcvtns_r_r -emit_fcvtns :: emit_fcvtns_r_r -inst_fcvtnu :: inst_fcvtnu_r_r -emit_fcvtnu :: emit_fcvtnu_r_r -inst_fcvtps :: inst_fcvtps_r_r -emit_fcvtps :: emit_fcvtps_r_r -inst_fcvtpu :: inst_fcvtpu_r_r -emit_fcvtpu :: emit_fcvtpu_r_r -inst_fcvtms :: inst_fcvtms_r_r -emit_fcvtms :: emit_fcvtms_r_r -inst_fcvtmu :: inst_fcvtmu_r_r -emit_fcvtmu :: emit_fcvtmu_r_r -inst_frinta :: inst_frinta_r_r -emit_frinta :: emit_frinta_r_r -inst_frinti :: inst_frinti_r_r -emit_frinti :: emit_frinti_r_r -inst_frintm :: inst_frintm_r_r -emit_frintm :: emit_frintm_r_r -inst_frintn :: inst_frintn_r_r -emit_frintn :: emit_frintn_r_r -inst_frintp :: inst_frintp_r_r -emit_frintp :: emit_frintp_r_r -inst_frintx :: inst_frintx_r_r -emit_frintx :: emit_frintx_r_r -inst_frintz :: inst_frintz_r_r -emit_frintz :: emit_frintz_r_r -inst_and_imm :: inst_and_imm_r_r_i -emit_and_imm :: emit_and_imm_r_r_i -inst_ands_imm :: inst_ands_imm_r_r_i -emit_ands_imm :: emit_ands_imm_r_r_i -inst_orr_imm :: inst_orr_imm_r_r_i -emit_orr_imm :: emit_orr_imm_r_r_i -inst_eor_imm :: inst_eor_imm_r_r_i -emit_eor_imm :: emit_eor_imm_r_r_i -inst_tst_imm :: inst_tst_imm_r_i -emit_tst_imm :: emit_tst_imm_r_i -inst_ldur :: inst_ldur_r_m -emit_ldur :: emit_ldur_r_m -inst_stur :: inst_stur_r_m -emit_stur :: emit_stur_r_m -inst_ldurb :: inst_ldurb_r_m -emit_ldurb :: emit_ldurb_r_m -inst_sturb :: inst_sturb_r_m -emit_sturb :: emit_sturb_r_m -inst_ldursb :: inst_ldursb_r_m -emit_ldursb :: emit_ldursb_r_m -inst_ldurh :: inst_ldurh_r_m -emit_ldurh :: emit_ldurh_r_m -inst_sturh :: inst_sturh_r_m -emit_sturh :: emit_sturh_r_m -inst_ldursh :: inst_ldursh_r_m -emit_ldursh :: emit_ldursh_r_m -inst_ldursw :: inst_ldursw_r_m -emit_ldursw :: emit_ldursw_r_m -inst_ldr_pre :: inst_ldr_pre_r_m -emit_ldr_pre :: emit_ldr_pre_r_m -inst_str_pre :: inst_str_pre_r_m -emit_str_pre :: emit_str_pre_r_m -inst_ldr_post :: inst_ldr_post_r_m -emit_ldr_post :: emit_ldr_post_r_m -inst_str_post :: inst_str_post_r_m -emit_str_post :: emit_str_post_r_m -inst_ldrb_pre :: inst_ldrb_pre_r_m -emit_ldrb_pre :: emit_ldrb_pre_r_m -inst_strb_pre :: inst_strb_pre_r_m -emit_strb_pre :: emit_strb_pre_r_m -inst_ldrb_post :: inst_ldrb_post_r_m -emit_ldrb_post :: emit_ldrb_post_r_m -inst_strb_post :: inst_strb_post_r_m -emit_strb_post :: emit_strb_post_r_m -inst_ldrh_pre :: inst_ldrh_pre_r_m -emit_ldrh_pre :: emit_ldrh_pre_r_m -inst_strh_pre :: inst_strh_pre_r_m -emit_strh_pre :: emit_strh_pre_r_m -inst_ldrh_post :: inst_ldrh_post_r_m -emit_ldrh_post :: emit_ldrh_post_r_m -inst_strh_post :: inst_strh_post_r_m -emit_strh_post :: emit_strh_post_r_m -inst_ldr_reg :: inst_ldr_reg_r_m -emit_ldr_reg :: emit_ldr_reg_r_m -inst_str_reg :: inst_str_reg_r_m -emit_str_reg :: emit_str_reg_r_m -inst_ldrb_reg :: inst_ldrb_reg_r_m -emit_ldrb_reg :: emit_ldrb_reg_r_m -inst_strb_reg :: inst_strb_reg_r_m -emit_strb_reg :: emit_strb_reg_r_m -inst_ldrh_reg :: inst_ldrh_reg_r_m -emit_ldrh_reg :: emit_ldrh_reg_r_m -inst_strh_reg :: inst_strh_reg_r_m -emit_strh_reg :: emit_strh_reg_r_m -inst_ldrsb_reg :: inst_ldrsb_reg_r_m -emit_ldrsb_reg :: emit_ldrsb_reg_r_m -inst_ldrsh_reg :: inst_ldrsh_reg_r_m -emit_ldrsh_reg :: emit_ldrsh_reg_r_m -inst_ldrsw_reg :: inst_ldrsw_reg_r_m -emit_ldrsw_reg :: emit_ldrsw_reg_r_m -inst_ldp_pre :: inst_ldp_pre_r_r_m -emit_ldp_pre :: emit_ldp_pre_r_r_m -inst_stp_pre :: inst_stp_pre_r_r_m -emit_stp_pre :: emit_stp_pre_r_r_m -inst_ldp_post :: inst_ldp_post_r_r_m -emit_ldp_post :: emit_ldp_post_r_r_m -inst_stp_post :: inst_stp_post_r_r_m -emit_stp_post :: emit_stp_post_r_r_m -inst_ldpsw_pre :: inst_ldpsw_pre_r_r_m -emit_ldpsw_pre :: emit_ldpsw_pre_r_r_m -inst_ldpsw_post :: inst_ldpsw_post_r_r_m -emit_ldpsw_post :: emit_ldpsw_post_r_r_m -inst_ldnp :: inst_ldnp_r_r_m -emit_ldnp :: emit_ldnp_r_r_m -inst_stnp :: inst_stnp_r_r_m -emit_stnp :: emit_stnp_r_r_m -inst_ldxp :: inst_ldxp_r_r_m -emit_ldxp :: emit_ldxp_r_r_m -inst_stxp :: inst_stxp_r_r_r_m -emit_stxp :: emit_stxp_r_r_r_m -inst_ldaxp :: inst_ldaxp_r_r_m -emit_ldaxp :: emit_ldaxp_r_r_m -inst_stlxp :: inst_stlxp_r_r_r_m -emit_stlxp :: emit_stlxp_r_r_r_m -inst_ldxrb :: inst_ldxrb_r_m -emit_ldxrb :: emit_ldxrb_r_m -inst_stxrb :: inst_stxrb_r_r_m -emit_stxrb :: emit_stxrb_r_r_m -inst_ldaxrb :: inst_ldaxrb_r_m -emit_ldaxrb :: emit_ldaxrb_r_m -inst_stlxrb :: inst_stlxrb_r_r_m -emit_stlxrb :: emit_stlxrb_r_r_m -inst_ldxrh :: inst_ldxrh_r_m -emit_ldxrh :: emit_ldxrh_r_m -inst_stxrh :: inst_stxrh_r_r_m -emit_stxrh :: emit_stxrh_r_r_m -inst_ldaxrh :: inst_ldaxrh_r_m -emit_ldaxrh :: emit_ldaxrh_r_m -inst_stlxrh :: inst_stlxrh_r_r_m -emit_stlxrh :: emit_stlxrh_r_r_m -inst_ldapr :: inst_ldapr_r_m -emit_ldapr :: emit_ldapr_r_m -inst_ldaprb :: inst_ldaprb_r_m -emit_ldaprb :: emit_ldaprb_r_m -inst_ldaprh :: inst_ldaprh_r_m -emit_ldaprh :: emit_ldaprh_r_m -inst_ldadd :: inst_ldadd_r_r_m -emit_ldadd :: emit_ldadd_r_r_m -inst_ldadda :: inst_ldadda_r_r_m -emit_ldadda :: emit_ldadda_r_r_m -inst_ldaddl :: inst_ldaddl_r_r_m -emit_ldaddl :: emit_ldaddl_r_r_m -inst_ldaddal :: inst_ldaddal_r_r_m -emit_ldaddal :: emit_ldaddal_r_r_m -inst_ldclr :: inst_ldclr_r_r_m -emit_ldclr :: emit_ldclr_r_r_m -inst_ldclra :: inst_ldclra_r_r_m -emit_ldclra :: emit_ldclra_r_r_m -inst_ldclrl :: inst_ldclrl_r_r_m -emit_ldclrl :: emit_ldclrl_r_r_m -inst_ldclral :: inst_ldclral_r_r_m -emit_ldclral :: emit_ldclral_r_r_m -inst_ldeor :: inst_ldeor_r_r_m -emit_ldeor :: emit_ldeor_r_r_m -inst_ldeora :: inst_ldeora_r_r_m -emit_ldeora :: emit_ldeora_r_r_m -inst_ldeorl :: inst_ldeorl_r_r_m -emit_ldeorl :: emit_ldeorl_r_r_m -inst_ldeoral :: inst_ldeoral_r_r_m -emit_ldeoral :: emit_ldeoral_r_r_m -inst_ldset :: inst_ldset_r_r_m -emit_ldset :: emit_ldset_r_r_m -inst_ldseta :: inst_ldseta_r_r_m -emit_ldseta :: emit_ldseta_r_r_m -inst_ldsetl :: inst_ldsetl_r_r_m -emit_ldsetl :: emit_ldsetl_r_r_m -inst_ldsetal :: inst_ldsetal_r_r_m -emit_ldsetal :: emit_ldsetal_r_r_m -inst_ldsmax :: inst_ldsmax_r_r_m -emit_ldsmax :: emit_ldsmax_r_r_m -inst_ldsmaxa :: inst_ldsmaxa_r_r_m -emit_ldsmaxa :: emit_ldsmaxa_r_r_m -inst_ldsmaxl :: inst_ldsmaxl_r_r_m -emit_ldsmaxl :: emit_ldsmaxl_r_r_m -inst_ldsmaxal :: inst_ldsmaxal_r_r_m -emit_ldsmaxal :: emit_ldsmaxal_r_r_m -inst_ldsmin :: inst_ldsmin_r_r_m -emit_ldsmin :: emit_ldsmin_r_r_m -inst_ldsmina :: inst_ldsmina_r_r_m -emit_ldsmina :: emit_ldsmina_r_r_m -inst_ldsminl :: inst_ldsminl_r_r_m -emit_ldsminl :: emit_ldsminl_r_r_m -inst_ldsminal :: inst_ldsminal_r_r_m -emit_ldsminal :: emit_ldsminal_r_r_m -inst_ldumax :: inst_ldumax_r_r_m -emit_ldumax :: emit_ldumax_r_r_m -inst_ldumaxa :: inst_ldumaxa_r_r_m -emit_ldumaxa :: emit_ldumaxa_r_r_m -inst_ldumaxl :: inst_ldumaxl_r_r_m -emit_ldumaxl :: emit_ldumaxl_r_r_m -inst_ldumaxal :: inst_ldumaxal_r_r_m -emit_ldumaxal :: emit_ldumaxal_r_r_m -inst_ldumin :: inst_ldumin_r_r_m -emit_ldumin :: emit_ldumin_r_r_m -inst_ldumina :: inst_ldumina_r_r_m -emit_ldumina :: emit_ldumina_r_r_m -inst_lduminl :: inst_lduminl_r_r_m -emit_lduminl :: emit_lduminl_r_r_m -inst_lduminal :: inst_lduminal_r_r_m -emit_lduminal :: emit_lduminal_r_r_m -inst_swp :: inst_swp_r_r_m -emit_swp :: emit_swp_r_r_m -inst_swpa :: inst_swpa_r_r_m -emit_swpa :: emit_swpa_r_r_m -inst_swpl :: inst_swpl_r_r_m -emit_swpl :: emit_swpl_r_r_m -inst_swpal :: inst_swpal_r_r_m -emit_swpal :: emit_swpal_r_r_m -inst_cas :: inst_cas_r_r_m -emit_cas :: emit_cas_r_r_m -inst_casa :: inst_casa_r_r_m -emit_casa :: emit_casa_r_r_m -inst_casl :: inst_casl_r_r_m -emit_casl :: emit_casl_r_r_m -inst_casal :: inst_casal_r_r_m -emit_casal :: emit_casal_r_r_m -inst_casb :: inst_casb_r_r_m -emit_casb :: emit_casb_r_r_m -inst_casab :: inst_casab_r_r_m -emit_casab :: emit_casab_r_r_m -inst_caslb :: inst_caslb_r_r_m -emit_caslb :: emit_caslb_r_r_m -inst_casalb :: inst_casalb_r_r_m -emit_casalb :: emit_casalb_r_r_m -inst_cash :: inst_cash_r_r_m -emit_cash :: emit_cash_r_r_m -inst_casah :: inst_casah_r_r_m -emit_casah :: emit_casah_r_r_m -inst_caslh :: inst_caslh_r_r_m -emit_caslh :: emit_caslh_r_r_m -inst_casalh :: inst_casalh_r_r_m -emit_casalh :: emit_casalh_r_r_m -inst_casp :: inst_casp_r_r_m -emit_casp :: emit_casp_r_r_m -inst_caspa :: inst_caspa_r_r_m -emit_caspa :: emit_caspa_r_r_m -inst_caspl :: inst_caspl_r_r_m -emit_caspl :: emit_caspl_r_r_m -inst_caspal :: inst_caspal_r_r_m -emit_caspal :: emit_caspal_r_r_m -inst_pacia :: inst_pacia_r_r -emit_pacia :: emit_pacia_r_r -inst_pacib :: inst_pacib_r_r -emit_pacib :: emit_pacib_r_r -inst_pacda :: inst_pacda_r_r -emit_pacda :: emit_pacda_r_r -inst_pacdb :: inst_pacdb_r_r -emit_pacdb :: emit_pacdb_r_r -inst_paciza :: inst_paciza_r -emit_paciza :: emit_paciza_r -inst_pacizb :: inst_pacizb_r -emit_pacizb :: emit_pacizb_r -inst_pacdza :: inst_pacdza_r -emit_pacdza :: emit_pacdza_r -inst_pacdzb :: inst_pacdzb_r -emit_pacdzb :: emit_pacdzb_r -inst_autia :: inst_autia_r_r -emit_autia :: emit_autia_r_r -inst_autib :: inst_autib_r_r -emit_autib :: emit_autib_r_r -inst_autda :: inst_autda_r_r -emit_autda :: emit_autda_r_r -inst_autdb :: inst_autdb_r_r -emit_autdb :: emit_autdb_r_r -inst_autiza :: inst_autiza_r -emit_autiza :: emit_autiza_r -inst_autizb :: inst_autizb_r -emit_autizb :: emit_autizb_r -inst_autdza :: inst_autdza_r -emit_autdza :: emit_autdza_r -inst_autdzb :: inst_autdzb_r -emit_autdzb :: emit_autdzb_r -inst_paciasp :: inst_paciasp_none -emit_paciasp :: emit_paciasp_none -inst_pacibsp :: inst_pacibsp_none -emit_pacibsp :: emit_pacibsp_none -inst_autiasp :: inst_autiasp_none -emit_autiasp :: emit_autiasp_none -inst_autibsp :: inst_autibsp_none -emit_autibsp :: emit_autibsp_none -inst_pacia1716 :: inst_pacia1716_none -emit_pacia1716 :: emit_pacia1716_none -inst_pacib1716 :: inst_pacib1716_none -emit_pacib1716 :: emit_pacib1716_none -inst_autia1716 :: inst_autia1716_none -emit_autia1716 :: emit_autia1716_none -inst_autib1716 :: inst_autib1716_none -emit_autib1716 :: emit_autib1716_none -inst_pacga :: inst_pacga_r_r_r -emit_pacga :: emit_pacga_r_r_r -inst_xpaci :: inst_xpaci_r -emit_xpaci :: emit_xpaci_r -inst_xpacd :: inst_xpacd_r -emit_xpacd :: emit_xpacd_r -inst_xpaclri :: inst_xpaclri_none -emit_xpaclri :: emit_xpaclri_none -inst_retaa :: inst_retaa_none -emit_retaa :: emit_retaa_none -inst_retab :: inst_retab_none -emit_retab :: emit_retab_none -inst_braa :: inst_braa_r_r -emit_braa :: emit_braa_r_r -inst_brab :: inst_brab_r_r -emit_brab :: emit_brab_r_r -inst_braaz :: inst_braaz_r -emit_braaz :: emit_braaz_r -inst_brabz :: inst_brabz_r -emit_brabz :: emit_brabz_r -inst_blraa :: inst_blraa_r_r -emit_blraa :: emit_blraa_r_r -inst_blrab :: inst_blrab_r_r -emit_blrab :: emit_blrab_r_r -inst_blraaz :: inst_blraaz_r -emit_blraaz :: emit_blraaz_r -inst_blrabz :: inst_blrabz_r -emit_blrabz :: emit_blrabz_r -inst_eretaa :: inst_eretaa_none -emit_eretaa :: emit_eretaa_none -inst_eretab :: inst_eretab_none -emit_eretab :: emit_eretab_none -inst_bti :: inst_bti_i -emit_bti :: emit_bti_i -inst_irg :: inst_irg_r_r_r -emit_irg :: emit_irg_r_r_r -inst_addg :: inst_addg_r_r_i_i -emit_addg :: emit_addg_r_r_i_i -inst_subg :: inst_subg_r_r_i_i -emit_subg :: emit_subg_r_r_i_i -inst_gmi :: inst_gmi_r_r_r -emit_gmi :: emit_gmi_r_r_r -inst_subp :: inst_subp_r_r_r -emit_subp :: emit_subp_r_r_r -inst_subps :: inst_subps_r_r_r -emit_subps :: emit_subps_r_r_r -inst_ldg :: inst_ldg_r_m -emit_ldg :: emit_ldg_r_m -inst_stg :: inst_stg_r_m -emit_stg :: emit_stg_r_m -inst_st2g :: inst_st2g_r_m -emit_st2g :: emit_st2g_r_m -inst_stzg :: inst_stzg_r_m -emit_stzg :: emit_stzg_r_m -inst_stz2g :: inst_stz2g_r_m -emit_stz2g :: emit_stz2g_r_m -inst_stgp :: inst_stgp_r_r_m -emit_stgp :: emit_stgp_r_r_m -inst_ldgm :: inst_ldgm_r_m -emit_ldgm :: emit_ldgm_r_m -inst_stgm :: inst_stgm_r_m -emit_stgm :: emit_stgm_r_m -inst_stzgm :: inst_stzgm_r_m -emit_stzgm :: emit_stzgm_r_m -inst_crc32b :: inst_crc32b_r_r_r -emit_crc32b :: emit_crc32b_r_r_r -inst_crc32h :: inst_crc32h_r_r_r -emit_crc32h :: emit_crc32h_r_r_r -inst_crc32w :: inst_crc32w_r_r_r -emit_crc32w :: emit_crc32w_r_r_r -inst_crc32x :: inst_crc32x_r_r_r -emit_crc32x :: emit_crc32x_r_r_r -inst_crc32cb :: inst_crc32cb_r_r_r -emit_crc32cb :: emit_crc32cb_r_r_r -inst_crc32ch :: inst_crc32ch_r_r_r -emit_crc32ch :: emit_crc32ch_r_r_r -inst_crc32cw :: inst_crc32cw_r_r_r -emit_crc32cw :: emit_crc32cw_r_r_r -inst_crc32cx :: inst_crc32cx_r_r_r -emit_crc32cx :: emit_crc32cx_r_r_r -inst_aese :: inst_aese_r_r -emit_aese :: emit_aese_r_r -inst_aesd :: inst_aesd_r_r -emit_aesd :: emit_aesd_r_r -inst_aesmc :: inst_aesmc_r_r -emit_aesmc :: emit_aesmc_r_r -inst_aesimc :: inst_aesimc_r_r -emit_aesimc :: emit_aesimc_r_r -inst_sha1h :: inst_sha1h_r_r -emit_sha1h :: emit_sha1h_r_r -inst_sha1c :: inst_sha1c_r_r_r -emit_sha1c :: emit_sha1c_r_r_r -inst_sha1p :: inst_sha1p_r_r_r -emit_sha1p :: emit_sha1p_r_r_r -inst_sha1m :: inst_sha1m_r_r_r -emit_sha1m :: emit_sha1m_r_r_r -inst_sha1su0 :: inst_sha1su0_r_r_r -emit_sha1su0 :: emit_sha1su0_r_r_r -inst_sha1su1 :: inst_sha1su1_r_r -emit_sha1su1 :: emit_sha1su1_r_r -inst_sha256h :: inst_sha256h_r_r_r -emit_sha256h :: emit_sha256h_r_r_r -inst_sha256h2 :: inst_sha256h2_r_r_r -emit_sha256h2 :: emit_sha256h2_r_r_r -inst_sha256su0 :: inst_sha256su0_r_r -emit_sha256su0 :: emit_sha256su0_r_r -inst_sha256su1 :: inst_sha256su1_r_r_r -emit_sha256su1 :: emit_sha256su1_r_r_r -inst_sha512h :: inst_sha512h_r_r_r -emit_sha512h :: emit_sha512h_r_r_r -inst_sha512h2 :: inst_sha512h2_r_r_r -emit_sha512h2 :: emit_sha512h2_r_r_r -inst_sha512su0 :: inst_sha512su0_r_r -emit_sha512su0 :: emit_sha512su0_r_r -inst_sha512su1 :: inst_sha512su1_r_r_r -emit_sha512su1 :: emit_sha512su1_r_r_r -inst_eor3 :: inst_eor3_r_r_r_r -emit_eor3 :: emit_eor3_r_r_r_r -inst_bcax :: inst_bcax_r_r_r_r -emit_bcax :: emit_bcax_r_r_r_r -inst_rax1 :: inst_rax1_r_r_r -emit_rax1 :: emit_rax1_r_r_r -inst_xar :: inst_xar_r_r_r_i -emit_xar :: emit_xar_r_r_r_i -inst_sm3partw1 :: inst_sm3partw1_r_r_r -emit_sm3partw1 :: emit_sm3partw1_r_r_r -inst_sm3partw2 :: inst_sm3partw2_r_r_r -emit_sm3partw2 :: emit_sm3partw2_r_r_r -inst_sm3ss1 :: inst_sm3ss1_r_r_r_r -emit_sm3ss1 :: emit_sm3ss1_r_r_r_r -inst_sm3tt1a :: inst_sm3tt1a_r_r_r -emit_sm3tt1a :: emit_sm3tt1a_r_r_r -inst_sm3tt1b :: inst_sm3tt1b_r_r_r -emit_sm3tt1b :: emit_sm3tt1b_r_r_r -inst_sm3tt2a :: inst_sm3tt2a_r_r_r -emit_sm3tt2a :: emit_sm3tt2a_r_r_r -inst_sm3tt2b :: inst_sm3tt2b_r_r_r -emit_sm3tt2b :: emit_sm3tt2b_r_r_r -inst_sm4e :: inst_sm4e_r_r -emit_sm4e :: emit_sm4e_r_r -inst_sm4ekey :: inst_sm4ekey_r_r_r -emit_sm4ekey :: emit_sm4ekey_r_r_r -inst_pmull :: inst_pmull_r_r_r -emit_pmull :: emit_pmull_r_r_r -inst_pmull2 :: inst_pmull2_r_r_r -emit_pmull2 :: emit_pmull2_r_r_r -inst_fabs_h :: inst_fabs_h_r_r -emit_fabs_h :: emit_fabs_h_r_r -inst_fneg_h :: inst_fneg_h_r_r -emit_fneg_h :: emit_fneg_h_r_r -inst_fsqrt_h :: inst_fsqrt_h_r_r -emit_fsqrt_h :: emit_fsqrt_h_r_r -inst_fadd_h :: inst_fadd_h_r_r_r -emit_fadd_h :: emit_fadd_h_r_r_r -inst_fsub_h :: inst_fsub_h_r_r_r -emit_fsub_h :: emit_fsub_h_r_r_r -inst_fmul_h :: inst_fmul_h_r_r_r -emit_fmul_h :: emit_fmul_h_r_r_r -inst_fdiv_h :: inst_fdiv_h_r_r_r -emit_fdiv_h :: emit_fdiv_h_r_r_r -inst_fnmul_h :: inst_fnmul_h_r_r_r -emit_fnmul_h :: emit_fnmul_h_r_r_r -inst_fmadd_h :: inst_fmadd_h_r_r_r_r -emit_fmadd_h :: emit_fmadd_h_r_r_r_r -inst_fmsub_h :: inst_fmsub_h_r_r_r_r -emit_fmsub_h :: emit_fmsub_h_r_r_r_r -inst_fnmadd_h :: inst_fnmadd_h_r_r_r_r -emit_fnmadd_h :: emit_fnmadd_h_r_r_r_r -inst_fnmsub_h :: inst_fnmsub_h_r_r_r_r -emit_fnmsub_h :: emit_fnmsub_h_r_r_r_r -inst_fcmp_h :: inst_fcmp_h_r_r -emit_fcmp_h :: emit_fcmp_h_r_r -inst_fcmpe_h :: inst_fcmpe_h_r_r -emit_fcmpe_h :: emit_fcmpe_h_r_r -inst_fcsel_h :: inst_fcsel_h_r_r_r_c -emit_fcsel_h :: emit_fcsel_h_r_r_r_c -inst_fmax_h :: inst_fmax_h_r_r_r -emit_fmax_h :: emit_fmax_h_r_r_r -inst_fmin_h :: inst_fmin_h_r_r_r -emit_fmin_h :: emit_fmin_h_r_r_r -inst_fmaxnm_h :: inst_fmaxnm_h_r_r_r -emit_fmaxnm_h :: emit_fmaxnm_h_r_r_r -inst_fminnm_h :: inst_fminnm_h_r_r_r -emit_fminnm_h :: emit_fminnm_h_r_r_r -inst_fcvt_h_s :: inst_fcvt_h_s_r_r -emit_fcvt_h_s :: emit_fcvt_h_s_r_r -inst_fcvt_h_d :: inst_fcvt_h_d_r_r -emit_fcvt_h_d :: emit_fcvt_h_d_r_r -inst_fcvt_s_h :: inst_fcvt_s_h_r_r -emit_fcvt_s_h :: emit_fcvt_s_h_r_r -inst_fcvt_d_h :: inst_fcvt_d_h_r_r -emit_fcvt_d_h :: emit_fcvt_d_h_r_r -inst_fmov_h :: inst_fmov_h_r_r -emit_fmov_h :: emit_fmov_h_r_r -inst_scvtf_h :: inst_scvtf_h_r_r -emit_scvtf_h :: emit_scvtf_h_r_r -inst_ucvtf_h :: inst_ucvtf_h_r_r -emit_ucvtf_h :: emit_ucvtf_h_r_r -inst_fcvtzs_h :: inst_fcvtzs_h_r_r -emit_fcvtzs_h :: emit_fcvtzs_h_r_r -inst_fcvtzu_h :: inst_fcvtzu_h_r_r -emit_fcvtzu_h :: emit_fcvtzu_h_r_r -inst_bfcvt :: inst_bfcvt_r_r -emit_bfcvt :: emit_bfcvt_r_r -inst_bfdot :: inst_bfdot_r_r_r -emit_bfdot :: emit_bfdot_r_r_r -inst_bfmmla :: inst_bfmmla_r_r_r -emit_bfmmla :: emit_bfmmla_r_r_r -inst_bfmlalb :: inst_bfmlalb_r_r_r -emit_bfmlalb :: emit_bfmlalb_r_r_r -inst_bfmlalt :: inst_bfmlalt_r_r_r -emit_bfmlalt :: emit_bfmlalt_r_r_r -inst_bfcvtn :: inst_bfcvtn_r_r -emit_bfcvtn :: emit_bfcvtn_r_r -inst_bfcvtn2 :: inst_bfcvtn2_r_r -emit_bfcvtn2 :: emit_bfcvtn2_r_r -inst_add_v :: inst_add_v_r_r_r -emit_add_v :: emit_add_v_r_r_r -inst_sub_v :: inst_sub_v_r_r_r -emit_sub_v :: emit_sub_v_r_r_r -inst_mul_v :: inst_mul_v_r_r_r -emit_mul_v :: emit_mul_v_r_r_r -inst_mla_v :: inst_mla_v_r_r_r -emit_mla_v :: emit_mla_v_r_r_r -inst_mls_v :: inst_mls_v_r_r_r -emit_mls_v :: emit_mls_v_r_r_r -inst_neg_v :: inst_neg_v_r_r -emit_neg_v :: emit_neg_v_r_r -inst_abs_v :: inst_abs_v_r_r -emit_abs_v :: emit_abs_v_r_r -inst_shadd :: inst_shadd_r_r_r -emit_shadd :: emit_shadd_r_r_r -inst_uhadd :: inst_uhadd_r_r_r -emit_uhadd :: emit_uhadd_r_r_r -inst_shsub :: inst_shsub_r_r_r -emit_shsub :: emit_shsub_r_r_r -inst_uhsub :: inst_uhsub_r_r_r -emit_uhsub :: emit_uhsub_r_r_r -inst_srhadd :: inst_srhadd_r_r_r -emit_srhadd :: emit_srhadd_r_r_r -inst_urhadd :: inst_urhadd_r_r_r -emit_urhadd :: emit_urhadd_r_r_r -inst_sqadd :: inst_sqadd_r_r_r -emit_sqadd :: emit_sqadd_r_r_r -inst_uqadd :: inst_uqadd_r_r_r -emit_uqadd :: emit_uqadd_r_r_r -inst_sqsub :: inst_sqsub_r_r_r -emit_sqsub :: emit_sqsub_r_r_r -inst_uqsub :: inst_uqsub_r_r_r -emit_uqsub :: emit_uqsub_r_r_r -inst_smax :: inst_smax_r_r_r -emit_smax :: emit_smax_r_r_r -inst_umax :: inst_umax_r_r_r -emit_umax :: emit_umax_r_r_r -inst_smin :: inst_smin_r_r_r -emit_smin :: emit_smin_r_r_r -inst_umin :: inst_umin_r_r_r -emit_umin :: emit_umin_r_r_r -inst_sabd :: inst_sabd_r_r_r -emit_sabd :: emit_sabd_r_r_r -inst_uabd :: inst_uabd_r_r_r -emit_uabd :: emit_uabd_r_r_r -inst_saba :: inst_saba_r_r_r -emit_saba :: emit_saba_r_r_r -inst_uaba :: inst_uaba_r_r_r -emit_uaba :: emit_uaba_r_r_r -inst_addp_v :: inst_addp_v_r_r_r -emit_addp_v :: emit_addp_v_r_r_r -inst_addv :: inst_addv_r_r -emit_addv :: emit_addv_r_r -inst_saddlp :: inst_saddlp_r_r -emit_saddlp :: emit_saddlp_r_r -inst_uaddlp :: inst_uaddlp_r_r -emit_uaddlp :: emit_uaddlp_r_r -inst_sadalp :: inst_sadalp_r_r -emit_sadalp :: emit_sadalp_r_r -inst_uadalp :: inst_uadalp_r_r -emit_uadalp :: emit_uadalp_r_r -inst_saddlv :: inst_saddlv_r_r -emit_saddlv :: emit_saddlv_r_r -inst_uaddlv :: inst_uaddlv_r_r -emit_uaddlv :: emit_uaddlv_r_r -inst_smaxv :: inst_smaxv_r_r -emit_smaxv :: emit_smaxv_r_r -inst_umaxv :: inst_umaxv_r_r -emit_umaxv :: emit_umaxv_r_r -inst_sminv :: inst_sminv_r_r -emit_sminv :: emit_sminv_r_r -inst_uminv :: inst_uminv_r_r -emit_uminv :: emit_uminv_r_r -inst_smaxp :: inst_smaxp_r_r_r -emit_smaxp :: emit_smaxp_r_r_r -inst_umaxp :: inst_umaxp_r_r_r -emit_umaxp :: emit_umaxp_r_r_r -inst_sminp :: inst_sminp_r_r_r -emit_sminp :: emit_sminp_r_r_r -inst_uminp :: inst_uminp_r_r_r -emit_uminp :: emit_uminp_r_r_r -inst_saddl :: inst_saddl_r_r_r -emit_saddl :: emit_saddl_r_r_r -inst_saddl2 :: inst_saddl2_r_r_r -emit_saddl2 :: emit_saddl2_r_r_r -inst_uaddl :: inst_uaddl_r_r_r -emit_uaddl :: emit_uaddl_r_r_r -inst_uaddl2 :: inst_uaddl2_r_r_r -emit_uaddl2 :: emit_uaddl2_r_r_r -inst_ssubl :: inst_ssubl_r_r_r -emit_ssubl :: emit_ssubl_r_r_r -inst_ssubl2 :: inst_ssubl2_r_r_r -emit_ssubl2 :: emit_ssubl2_r_r_r -inst_usubl :: inst_usubl_r_r_r -emit_usubl :: emit_usubl_r_r_r -inst_usubl2 :: inst_usubl2_r_r_r -emit_usubl2 :: emit_usubl2_r_r_r -inst_saddw :: inst_saddw_r_r_r -emit_saddw :: emit_saddw_r_r_r -inst_saddw2 :: inst_saddw2_r_r_r -emit_saddw2 :: emit_saddw2_r_r_r -inst_uaddw :: inst_uaddw_r_r_r -emit_uaddw :: emit_uaddw_r_r_r -inst_uaddw2 :: inst_uaddw2_r_r_r -emit_uaddw2 :: emit_uaddw2_r_r_r -inst_ssubw :: inst_ssubw_r_r_r -emit_ssubw :: emit_ssubw_r_r_r -inst_ssubw2 :: inst_ssubw2_r_r_r -emit_ssubw2 :: emit_ssubw2_r_r_r -inst_usubw :: inst_usubw_r_r_r -emit_usubw :: emit_usubw_r_r_r -inst_usubw2 :: inst_usubw2_r_r_r -emit_usubw2 :: emit_usubw2_r_r_r -inst_raddhn :: inst_raddhn_r_r_r -emit_raddhn :: emit_raddhn_r_r_r -inst_raddhn2 :: inst_raddhn2_r_r_r -emit_raddhn2 :: emit_raddhn2_r_r_r -inst_rsubhn :: inst_rsubhn_r_r_r -emit_rsubhn :: emit_rsubhn_r_r_r -inst_rsubhn2 :: inst_rsubhn2_r_r_r -emit_rsubhn2 :: emit_rsubhn2_r_r_r -inst_addhn :: inst_addhn_r_r_r -emit_addhn :: emit_addhn_r_r_r -inst_addhn2 :: inst_addhn2_r_r_r -emit_addhn2 :: emit_addhn2_r_r_r -inst_subhn :: inst_subhn_r_r_r -emit_subhn :: emit_subhn_r_r_r -inst_subhn2 :: inst_subhn2_r_r_r -emit_subhn2 :: emit_subhn2_r_r_r -inst_xtn :: inst_xtn_r_r -emit_xtn :: emit_xtn_r_r -inst_xtn2 :: inst_xtn2_r_r -emit_xtn2 :: emit_xtn2_r_r -inst_sqxtn :: inst_sqxtn_r_r -emit_sqxtn :: emit_sqxtn_r_r -inst_sqxtn2 :: inst_sqxtn2_r_r -emit_sqxtn2 :: emit_sqxtn2_r_r -inst_uqxtn :: inst_uqxtn_r_r -emit_uqxtn :: emit_uqxtn_r_r -inst_uqxtn2 :: inst_uqxtn2_r_r -emit_uqxtn2 :: emit_uqxtn2_r_r -inst_sqxtun :: inst_sqxtun_r_r -emit_sqxtun :: emit_sqxtun_r_r -inst_sqxtun2 :: inst_sqxtun2_r_r -emit_sqxtun2 :: emit_sqxtun2_r_r -inst_smull_v :: inst_smull_v_r_r_r -emit_smull_v :: emit_smull_v_r_r_r -inst_smull2_v :: inst_smull2_v_r_r_r -emit_smull2_v :: emit_smull2_v_r_r_r -inst_umull_v :: inst_umull_v_r_r_r -emit_umull_v :: emit_umull_v_r_r_r -inst_umull2_v :: inst_umull2_v_r_r_r -emit_umull2_v :: emit_umull2_v_r_r_r -inst_smlal :: inst_smlal_r_r_r -emit_smlal :: emit_smlal_r_r_r -inst_smlal2 :: inst_smlal2_r_r_r -emit_smlal2 :: emit_smlal2_r_r_r -inst_umlal :: inst_umlal_r_r_r -emit_umlal :: emit_umlal_r_r_r -inst_umlal2 :: inst_umlal2_r_r_r -emit_umlal2 :: emit_umlal2_r_r_r -inst_smlsl :: inst_smlsl_r_r_r -emit_smlsl :: emit_smlsl_r_r_r -inst_smlsl2 :: inst_smlsl2_r_r_r -emit_smlsl2 :: emit_smlsl2_r_r_r -inst_umlsl :: inst_umlsl_r_r_r -emit_umlsl :: emit_umlsl_r_r_r -inst_umlsl2 :: inst_umlsl2_r_r_r -emit_umlsl2 :: emit_umlsl2_r_r_r -inst_sqdmull :: inst_sqdmull_r_r_r -emit_sqdmull :: emit_sqdmull_r_r_r -inst_sqdmull2 :: inst_sqdmull2_r_r_r -emit_sqdmull2 :: emit_sqdmull2_r_r_r -inst_sqdmlal :: inst_sqdmlal_r_r_r -emit_sqdmlal :: emit_sqdmlal_r_r_r -inst_sqdmlal2 :: inst_sqdmlal2_r_r_r -emit_sqdmlal2 :: emit_sqdmlal2_r_r_r -inst_sqdmlsl :: inst_sqdmlsl_r_r_r -emit_sqdmlsl :: emit_sqdmlsl_r_r_r -inst_sqdmlsl2 :: inst_sqdmlsl2_r_r_r -emit_sqdmlsl2 :: emit_sqdmlsl2_r_r_r -inst_sqdmulh :: inst_sqdmulh_r_r_r -emit_sqdmulh :: emit_sqdmulh_r_r_r -inst_sqrdmulh :: inst_sqrdmulh_r_r_r -emit_sqrdmulh :: emit_sqrdmulh_r_r_r -inst_sdot :: inst_sdot_r_r_r -emit_sdot :: emit_sdot_r_r_r -inst_udot :: inst_udot_r_r_r -emit_udot :: emit_udot_r_r_r -inst_usdot :: inst_usdot_r_r_r -emit_usdot :: emit_usdot_r_r_r -inst_fadd_v :: inst_fadd_v_r_r_r -emit_fadd_v :: emit_fadd_v_r_r_r -inst_fsub_v :: inst_fsub_v_r_r_r -emit_fsub_v :: emit_fsub_v_r_r_r -inst_fmul_v :: inst_fmul_v_r_r_r -emit_fmul_v :: emit_fmul_v_r_r_r -inst_fdiv_v :: inst_fdiv_v_r_r_r -emit_fdiv_v :: emit_fdiv_v_r_r_r -inst_fneg_v :: inst_fneg_v_r_r -emit_fneg_v :: emit_fneg_v_r_r -inst_fabs_v :: inst_fabs_v_r_r -emit_fabs_v :: emit_fabs_v_r_r -inst_fsqrt_v :: inst_fsqrt_v_r_r -emit_fsqrt_v :: emit_fsqrt_v_r_r -inst_fmla_v :: inst_fmla_v_r_r_r -emit_fmla_v :: emit_fmla_v_r_r_r -inst_fmls_v :: inst_fmls_v_r_r_r -emit_fmls_v :: emit_fmls_v_r_r_r -inst_fmulx :: inst_fmulx_r_r_r -emit_fmulx :: emit_fmulx_r_r_r -inst_fmax_v :: inst_fmax_v_r_r_r -emit_fmax_v :: emit_fmax_v_r_r_r -inst_fmin_v :: inst_fmin_v_r_r_r -emit_fmin_v :: emit_fmin_v_r_r_r -inst_fmaxnm_v :: inst_fmaxnm_v_r_r_r -emit_fmaxnm_v :: emit_fmaxnm_v_r_r_r -inst_fminnm_v :: inst_fminnm_v_r_r_r -emit_fminnm_v :: emit_fminnm_v_r_r_r -inst_fmaxp_v :: inst_fmaxp_v_r_r_r -emit_fmaxp_v :: emit_fmaxp_v_r_r_r -inst_fminp_v :: inst_fminp_v_r_r_r -emit_fminp_v :: emit_fminp_v_r_r_r -inst_fmaxnmp :: inst_fmaxnmp_r_r_r -emit_fmaxnmp :: emit_fmaxnmp_r_r_r -inst_fminnmp :: inst_fminnmp_r_r_r -emit_fminnmp :: emit_fminnmp_r_r_r -inst_fmaxv_v :: inst_fmaxv_v_r_r -emit_fmaxv_v :: emit_fmaxv_v_r_r -inst_fminv_v :: inst_fminv_v_r_r -emit_fminv_v :: emit_fminv_v_r_r -inst_fmaxnmv :: inst_fmaxnmv_r_r -emit_fmaxnmv :: emit_fmaxnmv_r_r -inst_fminnmv :: inst_fminnmv_r_r -emit_fminnmv :: emit_fminnmv_r_r -inst_frecpe :: inst_frecpe_r_r -emit_frecpe :: emit_frecpe_r_r -inst_frsqrte :: inst_frsqrte_r_r -emit_frsqrte :: emit_frsqrte_r_r -inst_frecps :: inst_frecps_r_r_r -emit_frecps :: emit_frecps_r_r_r -inst_frsqrts :: inst_frsqrts_r_r_r -emit_frsqrts :: emit_frsqrts_r_r_r -inst_frecpx :: inst_frecpx_r_r -emit_frecpx :: emit_frecpx_r_r -inst_faddp_v :: inst_faddp_v_r_r_r -emit_faddp_v :: emit_faddp_v_r_r_r -inst_frinta_v :: inst_frinta_v_r_r -emit_frinta_v :: emit_frinta_v_r_r -inst_frinti_v :: inst_frinti_v_r_r -emit_frinti_v :: emit_frinti_v_r_r -inst_frintm_v :: inst_frintm_v_r_r -emit_frintm_v :: emit_frintm_v_r_r -inst_frintn_v :: inst_frintn_v_r_r -emit_frintn_v :: emit_frintn_v_r_r -inst_frintp_v :: inst_frintp_v_r_r -emit_frintp_v :: emit_frintp_v_r_r -inst_frintx_v :: inst_frintx_v_r_r -emit_frintx_v :: emit_frintx_v_r_r -inst_frintz_v :: inst_frintz_v_r_r -emit_frintz_v :: emit_frintz_v_r_r -inst_scvtf_v :: inst_scvtf_v_r_r -emit_scvtf_v :: emit_scvtf_v_r_r -inst_ucvtf_v :: inst_ucvtf_v_r_r -emit_ucvtf_v :: emit_ucvtf_v_r_r -inst_fcvtas_v :: inst_fcvtas_v_r_r -emit_fcvtas_v :: emit_fcvtas_v_r_r -inst_fcvtau_v :: inst_fcvtau_v_r_r -emit_fcvtau_v :: emit_fcvtau_v_r_r -inst_fcvtms_v :: inst_fcvtms_v_r_r -emit_fcvtms_v :: emit_fcvtms_v_r_r -inst_fcvtmu_v :: inst_fcvtmu_v_r_r -emit_fcvtmu_v :: emit_fcvtmu_v_r_r -inst_fcvtns_v :: inst_fcvtns_v_r_r -emit_fcvtns_v :: emit_fcvtns_v_r_r -inst_fcvtnu_v :: inst_fcvtnu_v_r_r -emit_fcvtnu_v :: emit_fcvtnu_v_r_r -inst_fcvtps_v :: inst_fcvtps_v_r_r -emit_fcvtps_v :: emit_fcvtps_v_r_r -inst_fcvtpu_v :: inst_fcvtpu_v_r_r -emit_fcvtpu_v :: emit_fcvtpu_v_r_r -inst_fcvtzs_v :: inst_fcvtzs_v_r_r -emit_fcvtzs_v :: emit_fcvtzs_v_r_r -inst_fcvtzu_v :: inst_fcvtzu_v_r_r -emit_fcvtzu_v :: emit_fcvtzu_v_r_r -inst_fcvtl :: inst_fcvtl_r_r -emit_fcvtl :: emit_fcvtl_r_r -inst_fcvtl2 :: inst_fcvtl2_r_r -emit_fcvtl2 :: emit_fcvtl2_r_r -inst_fcvtn :: inst_fcvtn_r_r -emit_fcvtn :: emit_fcvtn_r_r -inst_fcvtn2 :: inst_fcvtn2_r_r -emit_fcvtn2 :: emit_fcvtn2_r_r -inst_fcvtxn :: inst_fcvtxn_r_r -emit_fcvtxn :: emit_fcvtxn_r_r -inst_fcvtxn2 :: inst_fcvtxn2_r_r -emit_fcvtxn2 :: emit_fcvtxn2_r_r -inst_fcmeq :: inst_fcmeq_r_r_r -emit_fcmeq :: emit_fcmeq_r_r_r -inst_fcmge :: inst_fcmge_r_r_r -emit_fcmge :: emit_fcmge_r_r_r -inst_fcmgt :: inst_fcmgt_r_r_r -emit_fcmgt :: emit_fcmgt_r_r_r -inst_fcmle :: inst_fcmle_r_r -emit_fcmle :: emit_fcmle_r_r -inst_fcmlt :: inst_fcmlt_r_r -emit_fcmlt :: emit_fcmlt_r_r -inst_facge :: inst_facge_r_r_r -emit_facge :: emit_facge_r_r_r -inst_facgt :: inst_facgt_r_r_r -emit_facgt :: emit_facgt_r_r_r -inst_cmeq :: inst_cmeq_r_r_r -emit_cmeq :: emit_cmeq_r_r_r -inst_cmge :: inst_cmge_r_r_r -emit_cmge :: emit_cmge_r_r_r -inst_cmgt :: inst_cmgt_r_r_r -emit_cmgt :: emit_cmgt_r_r_r -inst_cmhi :: inst_cmhi_r_r_r -emit_cmhi :: emit_cmhi_r_r_r -inst_cmhs :: inst_cmhs_r_r_r -emit_cmhs :: emit_cmhs_r_r_r -inst_cmle :: inst_cmle_r_r -emit_cmle :: emit_cmle_r_r -inst_cmlt :: inst_cmlt_r_r -emit_cmlt :: emit_cmlt_r_r -inst_cmtst :: inst_cmtst_r_r_r -emit_cmtst :: emit_cmtst_r_r_r -inst_and_v :: inst_and_v_r_r_r -emit_and_v :: emit_and_v_r_r_r -inst_orr_v :: inst_orr_v_r_r_r -emit_orr_v :: emit_orr_v_r_r_r -inst_eor_v :: inst_eor_v_r_r_r -emit_eor_v :: emit_eor_v_r_r_r -inst_bic_v :: inst_bic_v_r_r_r -emit_bic_v :: emit_bic_v_r_r_r -inst_orn_v :: inst_orn_v_r_r_r -emit_orn_v :: emit_orn_v_r_r_r -inst_mvn_v :: inst_mvn_v_r_r -emit_mvn_v :: emit_mvn_v_r_r -inst_bit :: inst_bit_r_r_r -emit_bit :: emit_bit_r_r_r -inst_bif :: inst_bif_r_r_r -emit_bif :: emit_bif_r_r_r -inst_bsl :: inst_bsl_r_r_r -emit_bsl :: emit_bsl_r_r_r -inst_shl_v :: inst_shl_v_r_r_i -emit_shl_v :: emit_shl_v_r_r_i -inst_sqshl_v :: inst_sqshl_v_r_r_i -emit_sqshl_v :: emit_sqshl_v_r_r_i -inst_sqshlu :: inst_sqshlu_r_r_i -emit_sqshlu :: emit_sqshlu_r_r_i -inst_srshl :: inst_srshl_r_r_r -emit_srshl :: emit_srshl_r_r_r -inst_urshl :: inst_urshl_r_r_r -emit_urshl :: emit_urshl_r_r_r -inst_sshr :: inst_sshr_r_r_i -emit_sshr :: emit_sshr_r_r_i -inst_ushr :: inst_ushr_r_r_i -emit_ushr :: emit_ushr_r_r_i -inst_ssra :: inst_ssra_r_r_i -emit_ssra :: emit_ssra_r_r_i -inst_usra :: inst_usra_r_r_i -emit_usra :: emit_usra_r_r_i -inst_srshr :: inst_srshr_r_r_i -emit_srshr :: emit_srshr_r_r_i -inst_urshr :: inst_urshr_r_r_i -emit_urshr :: emit_urshr_r_r_i -inst_srsra :: inst_srsra_r_r_i -emit_srsra :: emit_srsra_r_r_i -inst_ursra :: inst_ursra_r_r_i -emit_ursra :: emit_ursra_r_r_i -inst_sshl :: inst_sshl_r_r_r -emit_sshl :: emit_sshl_r_r_r -inst_ushl :: inst_ushl_r_r_r -emit_ushl :: emit_ushl_r_r_r -inst_sli :: inst_sli_r_r_i -emit_sli :: emit_sli_r_r_i -inst_sri :: inst_sri_r_r_i -emit_sri :: emit_sri_r_r_i -inst_sshll :: inst_sshll_r_r_i -emit_sshll :: emit_sshll_r_r_i -inst_sshll2 :: inst_sshll2_r_r_i -emit_sshll2 :: emit_sshll2_r_r_i -inst_ushll :: inst_ushll_r_r_i -emit_ushll :: emit_ushll_r_r_i -inst_ushll2 :: inst_ushll2_r_r_i -emit_ushll2 :: emit_ushll2_r_r_i -inst_sxtl :: inst_sxtl_r_r -emit_sxtl :: emit_sxtl_r_r -inst_sxtl2 :: inst_sxtl2_r_r -emit_sxtl2 :: emit_sxtl2_r_r -inst_uxtl :: inst_uxtl_r_r -emit_uxtl :: emit_uxtl_r_r -inst_uxtl2 :: inst_uxtl2_r_r -emit_uxtl2 :: emit_uxtl2_r_r -inst_shrn :: inst_shrn_r_r_i -emit_shrn :: emit_shrn_r_r_i -inst_shrn2 :: inst_shrn2_r_r_i -emit_shrn2 :: emit_shrn2_r_r_i -inst_rshrn :: inst_rshrn_r_r_i -emit_rshrn :: emit_rshrn_r_r_i -inst_rshrn2 :: inst_rshrn2_r_r_i -emit_rshrn2 :: emit_rshrn2_r_r_i -inst_sqshrn :: inst_sqshrn_r_r_i -emit_sqshrn :: emit_sqshrn_r_r_i -inst_sqshrn2 :: inst_sqshrn2_r_r_i -emit_sqshrn2 :: emit_sqshrn2_r_r_i -inst_uqshrn :: inst_uqshrn_r_r_i -emit_uqshrn :: emit_uqshrn_r_r_i -inst_uqshrn2 :: inst_uqshrn2_r_r_i -emit_uqshrn2 :: emit_uqshrn2_r_r_i -inst_sqrshrn :: inst_sqrshrn_r_r_i -emit_sqrshrn :: emit_sqrshrn_r_r_i -inst_sqrshrn2 :: inst_sqrshrn2_r_r_i -emit_sqrshrn2 :: emit_sqrshrn2_r_r_i -inst_uqrshrn :: inst_uqrshrn_r_r_i -emit_uqrshrn :: emit_uqrshrn_r_r_i -inst_uqrshrn2 :: inst_uqrshrn2_r_r_i -emit_uqrshrn2 :: emit_uqrshrn2_r_r_i -inst_sqshrun :: inst_sqshrun_r_r_i -emit_sqshrun :: emit_sqshrun_r_r_i -inst_sqshrun2 :: inst_sqshrun2_r_r_i -emit_sqshrun2 :: emit_sqshrun2_r_r_i -inst_sqrshrun :: inst_sqrshrun_r_r_i -emit_sqrshrun :: emit_sqrshrun_r_r_i -inst_sqrshrun2 :: inst_sqrshrun2_r_r_i -emit_sqrshrun2 :: emit_sqrshrun2_r_r_i -inst_dup_v :: proc{ inst_dup_v_r_r_i, inst_dup_v_r_r } -emit_dup_v :: proc{ emit_dup_v_r_r_i, emit_dup_v_r_r } -inst_ins :: proc{ inst_ins_r_i_r_i, inst_ins_r_i_r } -emit_ins :: proc{ emit_ins_r_i_r_i, emit_ins_r_i_r } -inst_mov_v :: inst_mov_v_r_r -emit_mov_v :: emit_mov_v_r_r -inst_ext_v :: inst_ext_v_r_r_r_i -emit_ext_v :: emit_ext_v_r_r_r_i -inst_tbl :: inst_tbl_r_r_r -emit_tbl :: emit_tbl_r_r_r -inst_tbx :: inst_tbx_r_r_r -emit_tbx :: emit_tbx_r_r_r -inst_zip1 :: inst_zip1_r_r_r -emit_zip1 :: emit_zip1_r_r_r -inst_zip2 :: inst_zip2_r_r_r -emit_zip2 :: emit_zip2_r_r_r -inst_uzp1 :: inst_uzp1_r_r_r -emit_uzp1 :: emit_uzp1_r_r_r -inst_uzp2 :: inst_uzp2_r_r_r -emit_uzp2 :: emit_uzp2_r_r_r -inst_trn1 :: inst_trn1_r_r_r -emit_trn1 :: emit_trn1_r_r_r -inst_trn2 :: inst_trn2_r_r_r -emit_trn2 :: emit_trn2_r_r_r -inst_not_v :: inst_not_v_r_r -emit_not_v :: emit_not_v_r_r -inst_rbit_v :: inst_rbit_v_r_r -emit_rbit_v :: emit_rbit_v_r_r -inst_rev16_v :: inst_rev16_v_r_r -emit_rev16_v :: emit_rev16_v_r_r -inst_rev32_v :: inst_rev32_v_r_r -emit_rev32_v :: emit_rev32_v_r_r -inst_rev64 :: inst_rev64_r_r -emit_rev64 :: emit_rev64_r_r -inst_cls_v :: inst_cls_v_r_r -emit_cls_v :: emit_cls_v_r_r -inst_clz_v :: inst_clz_v_r_r -emit_clz_v :: emit_clz_v_r_r -inst_cnt :: inst_cnt_r_r -emit_cnt :: emit_cnt_r_r -inst_urecpe_v :: inst_urecpe_v_r_r -emit_urecpe_v :: emit_urecpe_v_r_r -inst_ursqrte_v :: inst_ursqrte_v_r_r -emit_ursqrte_v :: emit_ursqrte_v_r_r -inst_movi :: inst_movi_r_i -emit_movi :: emit_movi_r_i -inst_mvni :: inst_mvni_r_i -emit_mvni :: emit_mvni_r_i -inst_fmov_v_imm :: inst_fmov_v_imm_r_i -emit_fmov_v_imm :: emit_fmov_v_imm_r_i -inst_ld1 :: inst_ld1_r_m -emit_ld1 :: emit_ld1_r_m -inst_ld2 :: inst_ld2_r_m -emit_ld2 :: emit_ld2_r_m -inst_ld3 :: inst_ld3_r_m -emit_ld3 :: emit_ld3_r_m -inst_ld4 :: inst_ld4_r_m -emit_ld4 :: emit_ld4_r_m -inst_st1 :: inst_st1_r_m -emit_st1 :: emit_st1_r_m -inst_st2 :: inst_st2_r_m -emit_st2 :: emit_st2_r_m -inst_st3 :: inst_st3_r_m -emit_st3 :: emit_st3_r_m -inst_st4 :: inst_st4_r_m -emit_st4 :: emit_st4_r_m -inst_ld1r :: inst_ld1r_r_m -emit_ld1r :: emit_ld1r_r_m -inst_ld2r :: inst_ld2r_r_m -emit_ld2r :: emit_ld2r_r_m -inst_ld3r :: inst_ld3r_r_m -emit_ld3r :: emit_ld3r_r_m -inst_ld4r :: inst_ld4r_r_m -emit_ld4r :: emit_ld4r_r_m -inst_ld1_lane :: inst_ld1_lane_r_i_m -emit_ld1_lane :: emit_ld1_lane_r_i_m -inst_ld2_lane :: inst_ld2_lane_r_i_m -emit_ld2_lane :: emit_ld2_lane_r_i_m -inst_ld3_lane :: inst_ld3_lane_r_i_m -emit_ld3_lane :: emit_ld3_lane_r_i_m -inst_ld4_lane :: inst_ld4_lane_r_i_m -emit_ld4_lane :: emit_ld4_lane_r_i_m -inst_st1_lane :: inst_st1_lane_r_i_m -emit_st1_lane :: emit_st1_lane_r_i_m -inst_st2_lane :: inst_st2_lane_r_i_m -emit_st2_lane :: emit_st2_lane_r_i_m -inst_st3_lane :: inst_st3_lane_r_i_m -emit_st3_lane :: emit_st3_lane_r_i_m -inst_st4_lane :: inst_st4_lane_r_i_m -emit_st4_lane :: emit_st4_lane_r_i_m -inst_ldr_v :: inst_ldr_v_r_m -emit_ldr_v :: emit_ldr_v_r_m -inst_str_v :: inst_str_v_r_m -emit_str_v :: emit_str_v_r_m -inst_ldp_v :: inst_ldp_v_r_r_m -emit_ldp_v :: emit_ldp_v_r_r_m -inst_stp_v :: inst_stp_v_r_r_m -emit_stp_v :: emit_stp_v_r_r_m -inst_ldur_v :: inst_ldur_v_r_m -emit_ldur_v :: emit_ldur_v_r_m -inst_stur_v :: inst_stur_v_r_m -emit_stur_v :: emit_stur_v_r_m -inst_sve_add_z :: inst_sve_add_z_z_z_z -emit_sve_add_z :: emit_sve_add_z_z_z_z -inst_sve_sub_z :: inst_sve_sub_z_z_z_z -emit_sve_sub_z :: emit_sve_sub_z_z_z_z -inst_sve_sqadd_z :: inst_sve_sqadd_z_z_z_z -emit_sve_sqadd_z :: emit_sve_sqadd_z_z_z_z -inst_sve_uqadd_z :: inst_sve_uqadd_z_z_z_z -emit_sve_uqadd_z :: emit_sve_uqadd_z_z_z_z -inst_sve_sqsub_z :: inst_sve_sqsub_z_z_z_z -emit_sve_sqsub_z :: emit_sve_sqsub_z_z_z_z -inst_sve_uqsub_z :: inst_sve_uqsub_z_z_z_z -emit_sve_uqsub_z :: emit_sve_uqsub_z_z_z_z -inst_sve_add_pred :: inst_sve_add_pred_z_p_z_z -emit_sve_add_pred :: emit_sve_add_pred_z_p_z_z -inst_sve_sub_pred :: inst_sve_sub_pred_z_p_z_z -emit_sve_sub_pred :: emit_sve_sub_pred_z_p_z_z -inst_sve_subr_pred :: inst_sve_subr_pred_z_p_z_z -emit_sve_subr_pred :: emit_sve_subr_pred_z_p_z_z -inst_sve_mul_pred :: inst_sve_mul_pred_z_p_z_z -emit_sve_mul_pred :: emit_sve_mul_pred_z_p_z_z -inst_sve_smulh_pred :: inst_sve_smulh_pred_z_p_z_z -emit_sve_smulh_pred :: emit_sve_smulh_pred_z_p_z_z -inst_sve_umulh_pred :: inst_sve_umulh_pred_z_p_z_z -emit_sve_umulh_pred :: emit_sve_umulh_pred_z_p_z_z -inst_sve_sdiv_pred :: inst_sve_sdiv_pred_z_p_z_z -emit_sve_sdiv_pred :: emit_sve_sdiv_pred_z_p_z_z -inst_sve_udiv_pred :: inst_sve_udiv_pred_z_p_z_z -emit_sve_udiv_pred :: emit_sve_udiv_pred_z_p_z_z -inst_sve_smax_pred :: inst_sve_smax_pred_z_p_z_z -emit_sve_smax_pred :: emit_sve_smax_pred_z_p_z_z -inst_sve_umax_pred :: inst_sve_umax_pred_z_p_z_z -emit_sve_umax_pred :: emit_sve_umax_pred_z_p_z_z -inst_sve_smin_pred :: inst_sve_smin_pred_z_p_z_z -emit_sve_smin_pred :: emit_sve_smin_pred_z_p_z_z -inst_sve_umin_pred :: inst_sve_umin_pred_z_p_z_z -emit_sve_umin_pred :: emit_sve_umin_pred_z_p_z_z -inst_sve_sabd_pred :: inst_sve_sabd_pred_z_p_z_z -emit_sve_sabd_pred :: emit_sve_sabd_pred_z_p_z_z -inst_sve_uabd_pred :: inst_sve_uabd_pred_z_p_z_z -emit_sve_uabd_pred :: emit_sve_uabd_pred_z_p_z_z -inst_sve_and_pred :: inst_sve_and_pred_z_p_z_z -emit_sve_and_pred :: emit_sve_and_pred_z_p_z_z -inst_sve_orr_pred :: inst_sve_orr_pred_z_p_z_z -emit_sve_orr_pred :: emit_sve_orr_pred_z_p_z_z -inst_sve_eor_pred :: inst_sve_eor_pred_z_p_z_z -emit_sve_eor_pred :: emit_sve_eor_pred_z_p_z_z -inst_sve_bic_pred :: inst_sve_bic_pred_z_p_z_z -emit_sve_bic_pred :: emit_sve_bic_pred_z_p_z_z -inst_sve_asr_pred :: inst_sve_asr_pred_z_p_z_z -emit_sve_asr_pred :: emit_sve_asr_pred_z_p_z_z -inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z -emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z -inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z -emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z -inst_sve_asrr_pred :: inst_sve_asrr_pred_z_p_z_z -emit_sve_asrr_pred :: emit_sve_asrr_pred_z_p_z_z -inst_sve_lslr_pred :: inst_sve_lslr_pred_z_p_z_z -emit_sve_lslr_pred :: emit_sve_lslr_pred_z_p_z_z -inst_sve_lsrr_pred :: inst_sve_lsrr_pred_z_p_z_z -emit_sve_lsrr_pred :: emit_sve_lsrr_pred_z_p_z_z -inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z -emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z -inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z -emit_sve_neg_pred :: emit_sve_neg_pred_z_p_z -inst_sve_cls_pred :: inst_sve_cls_pred_z_p_z -emit_sve_cls_pred :: emit_sve_cls_pred_z_p_z -inst_sve_clz_pred :: inst_sve_clz_pred_z_p_z -emit_sve_clz_pred :: emit_sve_clz_pred_z_p_z -inst_sve_cnt_pred :: inst_sve_cnt_pred_z_p_z -emit_sve_cnt_pred :: emit_sve_cnt_pred_z_p_z -inst_sve_mov_pred :: inst_sve_mov_pred_z_p_z -emit_sve_mov_pred :: emit_sve_mov_pred_z_p_z -inst_sve_fadd_z :: inst_sve_fadd_z_z_z_z -emit_sve_fadd_z :: emit_sve_fadd_z_z_z_z -inst_sve_fsub_z :: inst_sve_fsub_z_z_z_z -emit_sve_fsub_z :: emit_sve_fsub_z_z_z_z -inst_sve_fmul_z :: inst_sve_fmul_z_z_z_z -emit_sve_fmul_z :: emit_sve_fmul_z_z_z_z -inst_sve_frecps :: inst_sve_frecps_z_z_z -emit_sve_frecps :: emit_sve_frecps_z_z_z -inst_sve_frsqrts :: inst_sve_frsqrts_z_z_z -emit_sve_frsqrts :: emit_sve_frsqrts_z_z_z -inst_sve_ftsmul :: inst_sve_ftsmul_z_z_z -emit_sve_ftsmul :: emit_sve_ftsmul_z_z_z -inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z -emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z -inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z -emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z -inst_sve_fsubr_pred :: inst_sve_fsubr_pred_z_p_z_z -emit_sve_fsubr_pred :: emit_sve_fsubr_pred_z_p_z_z -inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z -emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z -inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z -emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z -inst_sve_fdivr_pred :: inst_sve_fdivr_pred_z_p_z_z -emit_sve_fdivr_pred :: emit_sve_fdivr_pred_z_p_z_z -inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z -emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z -inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z -emit_sve_fmin_pred :: emit_sve_fmin_pred_z_p_z_z -inst_sve_fmaxnm_pred :: inst_sve_fmaxnm_pred_z_p_z_z -emit_sve_fmaxnm_pred :: emit_sve_fmaxnm_pred_z_p_z_z -inst_sve_fminnm_pred :: inst_sve_fminnm_pred_z_p_z_z -emit_sve_fminnm_pred :: emit_sve_fminnm_pred_z_p_z_z -inst_sve_fabs_z :: inst_sve_fabs_z_z_p_z -emit_sve_fabs_z :: emit_sve_fabs_z_z_p_z -inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z -emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z -inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z -emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z -inst_sve_frecpx_z :: inst_sve_frecpx_z_z_p_z -emit_sve_frecpx_z :: emit_sve_frecpx_z_z_p_z -inst_sve_frintn :: inst_sve_frintn_z_p_z -emit_sve_frintn :: emit_sve_frintn_z_p_z -inst_sve_frintp :: inst_sve_frintp_z_p_z -emit_sve_frintp :: emit_sve_frintp_z_p_z -inst_sve_frintm :: inst_sve_frintm_z_p_z -emit_sve_frintm :: emit_sve_frintm_z_p_z -inst_sve_frintz :: inst_sve_frintz_z_p_z -emit_sve_frintz :: emit_sve_frintz_z_p_z -inst_sve_frinta :: inst_sve_frinta_z_p_z -emit_sve_frinta :: emit_sve_frinta_z_p_z -inst_sve_frintx :: inst_sve_frintx_z_p_z -emit_sve_frintx :: emit_sve_frintx_z_p_z -inst_sve_frinti :: inst_sve_frinti_z_p_z -emit_sve_frinti :: emit_sve_frinti_z_p_z -inst_sve_fmla :: inst_sve_fmla_z_p_z_z -emit_sve_fmla :: emit_sve_fmla_z_p_z_z -inst_sve_fmls :: inst_sve_fmls_z_p_z_z -emit_sve_fmls :: emit_sve_fmls_z_p_z_z -inst_sve_fnmla :: inst_sve_fnmla_z_p_z_z -emit_sve_fnmla :: emit_sve_fnmla_z_p_z_z -inst_sve_fnmls :: inst_sve_fnmls_z_p_z_z -emit_sve_fnmls :: emit_sve_fnmls_z_p_z_z -inst_sve_and_p :: inst_sve_and_p_p_p_p_p -emit_sve_and_p :: emit_sve_and_p_p_p_p_p -inst_sve_bic_p :: inst_sve_bic_p_p_p_p_p -emit_sve_bic_p :: emit_sve_bic_p_p_p_p_p -inst_sve_orr_p :: inst_sve_orr_p_p_p_p_p -emit_sve_orr_p :: emit_sve_orr_p_p_p_p_p -inst_sve_eor_p :: inst_sve_eor_p_p_p_p_p -emit_sve_eor_p :: emit_sve_eor_p_p_p_p_p -inst_sve_nand_p :: inst_sve_nand_p_p_p_p_p -emit_sve_nand_p :: emit_sve_nand_p_p_p_p_p -inst_sve_nor_p :: inst_sve_nor_p_p_p_p_p -emit_sve_nor_p :: emit_sve_nor_p_p_p_p_p -inst_sve_orn_p :: inst_sve_orn_p_p_p_p_p -emit_sve_orn_p :: emit_sve_orn_p_p_p_p_p -inst_sve_sel_p :: inst_sve_sel_p_p_p_p_p -emit_sve_sel_p :: emit_sve_sel_p_p_p_p_p -inst_sve_ands_p :: inst_sve_ands_p_p_p_p_p -emit_sve_ands_p :: emit_sve_ands_p_p_p_p_p -inst_sve_bics_p :: inst_sve_bics_p_p_p_p_p -emit_sve_bics_p :: emit_sve_bics_p_p_p_p_p -inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p -emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p -inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p -emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p -inst_sve_nands_p :: inst_sve_nands_p_p_p_p_p -emit_sve_nands_p :: emit_sve_nands_p_p_p_p_p -inst_sve_nors_p :: inst_sve_nors_p_p_p_p_p -emit_sve_nors_p :: emit_sve_nors_p_p_p_p_p -inst_sve_orns_p :: inst_sve_orns_p_p_p_p_p -emit_sve_orns_p :: emit_sve_orns_p_p_p_p_p -inst_sve_not_p :: inst_sve_not_p_p_p_p -emit_sve_not_p :: emit_sve_not_p_p_p_p -inst_sve_mov_p :: proc{ inst_sve_mov_p_p_p_p, inst_sve_mov_p_p_p } -emit_sve_mov_p :: proc{ emit_sve_mov_p_p_p_p, emit_sve_mov_p_p_p } -inst_sve_movs_p :: inst_sve_movs_p_p_p_p -emit_sve_movs_p :: emit_sve_movs_p_p_p_p -inst_sve_ptrue :: inst_sve_ptrue_p_i -emit_sve_ptrue :: emit_sve_ptrue_p_i -inst_sve_ptrues :: inst_sve_ptrues_p_i -emit_sve_ptrues :: emit_sve_ptrues_p_i -inst_sve_pfalse :: inst_sve_pfalse_p -emit_sve_pfalse :: emit_sve_pfalse_p -inst_sve_pfirst :: inst_sve_pfirst_p_p_p -emit_sve_pfirst :: emit_sve_pfirst_p_p_p -inst_sve_pnext :: inst_sve_pnext_p_p_p -emit_sve_pnext :: emit_sve_pnext_p_p_p -inst_sve_brka :: inst_sve_brka_p_p_p -emit_sve_brka :: emit_sve_brka_p_p_p -inst_sve_brkb :: inst_sve_brkb_p_p_p -emit_sve_brkb :: emit_sve_brkb_p_p_p -inst_sve_brkas :: inst_sve_brkas_p_p_p -emit_sve_brkas :: emit_sve_brkas_p_p_p -inst_sve_brkbs :: inst_sve_brkbs_p_p_p -emit_sve_brkbs :: emit_sve_brkbs_p_p_p -inst_sve_brkpa :: inst_sve_brkpa_p_p_p_p -emit_sve_brkpa :: emit_sve_brkpa_p_p_p_p -inst_sve_brkpb :: inst_sve_brkpb_p_p_p_p -emit_sve_brkpb :: emit_sve_brkpb_p_p_p_p -inst_sve_brkn :: inst_sve_brkn_p_p_p_p -emit_sve_brkn :: emit_sve_brkn_p_p_p_p -inst_sve_rdffr :: inst_sve_rdffr_p -emit_sve_rdffr :: emit_sve_rdffr_p -inst_sve_wrffr :: inst_sve_wrffr_p -emit_sve_wrffr :: emit_sve_wrffr_p -inst_sve_setffr :: inst_sve_setffr_none -emit_sve_setffr :: emit_sve_setffr_none -inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z -emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z -inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z -emit_sve_cmpne :: emit_sve_cmpne_p_p_z_z -inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z -emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z -inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z -emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z -inst_sve_cmple :: inst_sve_cmple_p_p_z_z -emit_sve_cmple :: emit_sve_cmple_p_p_z_z -inst_sve_cmplt :: inst_sve_cmplt_p_p_z_z -emit_sve_cmplt :: emit_sve_cmplt_p_p_z_z -inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z -emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z -inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z -emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z -inst_sve_cmplo :: inst_sve_cmplo_p_p_z_z -emit_sve_cmplo :: emit_sve_cmplo_p_p_z_z -inst_sve_cmpls :: inst_sve_cmpls_p_p_z_z -emit_sve_cmpls :: emit_sve_cmpls_p_p_z_z -inst_sve_fcmeq :: inst_sve_fcmeq_p_p_z_z -emit_sve_fcmeq :: emit_sve_fcmeq_p_p_z_z -inst_sve_fcmne :: inst_sve_fcmne_p_p_z_z -emit_sve_fcmne :: emit_sve_fcmne_p_p_z_z -inst_sve_fcmge :: inst_sve_fcmge_p_p_z_z -emit_sve_fcmge :: emit_sve_fcmge_p_p_z_z -inst_sve_fcmgt :: inst_sve_fcmgt_p_p_z_z -emit_sve_fcmgt :: emit_sve_fcmgt_p_p_z_z -inst_sve_fcmle :: inst_sve_fcmle_p_p_z -emit_sve_fcmle :: emit_sve_fcmle_p_p_z -inst_sve_fcmlt :: inst_sve_fcmlt_p_p_z -emit_sve_fcmlt :: emit_sve_fcmlt_p_p_z -inst_sve_fcmuo :: inst_sve_fcmuo_p_p_z_z -emit_sve_fcmuo :: emit_sve_fcmuo_p_p_z_z -inst_sve_dup_z :: inst_sve_dup_z_z_r -emit_sve_dup_z :: emit_sve_dup_z_z_r -inst_sve_insr :: inst_sve_insr_z_r -emit_sve_insr :: emit_sve_insr_z_r -inst_sve_rev_z :: inst_sve_rev_z_z_z -emit_sve_rev_z :: emit_sve_rev_z_z_z -inst_sve_rev_p :: inst_sve_rev_p_p_p -emit_sve_rev_p :: emit_sve_rev_p_p_p -inst_sve_tbl :: inst_sve_tbl_z_z_z -emit_sve_tbl :: emit_sve_tbl_z_z_z -inst_sve_zip1_z :: inst_sve_zip1_z_z_z_z -emit_sve_zip1_z :: emit_sve_zip1_z_z_z_z -inst_sve_zip2_z :: inst_sve_zip2_z_z_z_z -emit_sve_zip2_z :: emit_sve_zip2_z_z_z_z -inst_sve_uzp1_z :: inst_sve_uzp1_z_z_z_z -emit_sve_uzp1_z :: emit_sve_uzp1_z_z_z_z -inst_sve_uzp2_z :: inst_sve_uzp2_z_z_z_z -emit_sve_uzp2_z :: emit_sve_uzp2_z_z_z_z -inst_sve_trn1_z :: inst_sve_trn1_z_z_z_z -emit_sve_trn1_z :: emit_sve_trn1_z_z_z_z -inst_sve_trn2_z :: inst_sve_trn2_z_z_z_z -emit_sve_trn2_z :: emit_sve_trn2_z_z_z_z -inst_sve_zip1_p :: inst_sve_zip1_p_p_p_p -emit_sve_zip1_p :: emit_sve_zip1_p_p_p_p -inst_sve_zip2_p :: inst_sve_zip2_p_p_p_p -emit_sve_zip2_p :: emit_sve_zip2_p_p_p_p -inst_sve_uzp1_p :: inst_sve_uzp1_p_p_p_p -emit_sve_uzp1_p :: emit_sve_uzp1_p_p_p_p -inst_sve_uzp2_p :: inst_sve_uzp2_p_p_p_p -emit_sve_uzp2_p :: emit_sve_uzp2_p_p_p_p -inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p -emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p -inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p -emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p -inst_sve_cpy_z :: inst_sve_cpy_z_z_p_r -emit_sve_cpy_z :: emit_sve_cpy_z_z_p_r -inst_sve_compact :: inst_sve_compact_z_p_z -emit_sve_compact :: emit_sve_compact_z_p_z -inst_sve_ext_z :: inst_sve_ext_z_z_z_z_i -emit_sve_ext_z :: emit_sve_ext_z_z_z_z_i -inst_sve_ld1b :: inst_sve_ld1b_z_p_m -emit_sve_ld1b :: emit_sve_ld1b_z_p_m -inst_sve_ld1h :: inst_sve_ld1h_z_p_m -emit_sve_ld1h :: emit_sve_ld1h_z_p_m -inst_sve_ld1w :: inst_sve_ld1w_z_p_m -emit_sve_ld1w :: emit_sve_ld1w_z_p_m -inst_sve_ld1d :: inst_sve_ld1d_z_p_m -emit_sve_ld1d :: emit_sve_ld1d_z_p_m -inst_sve_ld1sb :: inst_sve_ld1sb_z_p_m -emit_sve_ld1sb :: emit_sve_ld1sb_z_p_m -inst_sve_ld1sh :: inst_sve_ld1sh_z_p_m -emit_sve_ld1sh :: emit_sve_ld1sh_z_p_m -inst_sve_ld1sw :: inst_sve_ld1sw_z_p_m -emit_sve_ld1sw :: emit_sve_ld1sw_z_p_m -inst_sve_st1b :: inst_sve_st1b_z_p_m -emit_sve_st1b :: emit_sve_st1b_z_p_m -inst_sve_st1h :: inst_sve_st1h_z_p_m -emit_sve_st1h :: emit_sve_st1h_z_p_m -inst_sve_st1w :: inst_sve_st1w_z_p_m -emit_sve_st1w :: emit_sve_st1w_z_p_m -inst_sve_st1d :: inst_sve_st1d_z_p_m -emit_sve_st1d :: emit_sve_st1d_z_p_m -inst_sve_ldr_z :: inst_sve_ldr_z_z_m -emit_sve_ldr_z :: emit_sve_ldr_z_z_m -inst_sve_str_z :: inst_sve_str_z_z_m -emit_sve_str_z :: emit_sve_str_z_z_m -inst_sve_ldr_p :: inst_sve_ldr_p_p_m -emit_sve_ldr_p :: emit_sve_ldr_p_p_m -inst_sve_str_p :: inst_sve_str_p_p_m -emit_sve_str_p :: emit_sve_str_p_p_m -inst_sve_ldff1b :: inst_sve_ldff1b_z_p_m -emit_sve_ldff1b :: emit_sve_ldff1b_z_p_m -inst_sve_ldff1h :: inst_sve_ldff1h_z_p_m -emit_sve_ldff1h :: emit_sve_ldff1h_z_p_m -inst_sve_ldff1w :: inst_sve_ldff1w_z_p_m -emit_sve_ldff1w :: emit_sve_ldff1w_z_p_m -inst_sve_ldff1d :: inst_sve_ldff1d_z_p_m -emit_sve_ldff1d :: emit_sve_ldff1d_z_p_m -inst_sve_whilege :: inst_sve_whilege_p_r_r -emit_sve_whilege :: emit_sve_whilege_p_r_r -inst_sve_whilegt :: inst_sve_whilegt_p_r_r -emit_sve_whilegt :: emit_sve_whilegt_p_r_r -inst_sve_whilele :: inst_sve_whilele_p_r_r -emit_sve_whilele :: emit_sve_whilele_p_r_r -inst_sve_whilelt :: inst_sve_whilelt_p_r_r -emit_sve_whilelt :: emit_sve_whilelt_p_r_r -inst_sve_whilehi :: inst_sve_whilehi_p_r_r -emit_sve_whilehi :: emit_sve_whilehi_p_r_r -inst_sve_whilehs :: inst_sve_whilehs_p_r_r -emit_sve_whilehs :: emit_sve_whilehs_p_r_r -inst_sve_whilelo :: inst_sve_whilelo_p_r_r -emit_sve_whilelo :: emit_sve_whilelo_p_r_r -inst_sve_whilels :: inst_sve_whilels_p_r_r -emit_sve_whilels :: emit_sve_whilels_p_r_r -inst_sve_sqrdmlah :: inst_sve_sqrdmlah_z_z_z -emit_sve_sqrdmlah :: emit_sve_sqrdmlah_z_z_z -inst_sve_sqrdmlsh :: inst_sve_sqrdmlsh_z_z_z -emit_sve_sqrdmlsh :: emit_sve_sqrdmlsh_z_z_z -inst_sve_adclb :: inst_sve_adclb_z_z_z -emit_sve_adclb :: emit_sve_adclb_z_z_z -inst_sve_adclt :: inst_sve_adclt_z_z_z -emit_sve_adclt :: emit_sve_adclt_z_z_z -inst_sve_sbclb :: inst_sve_sbclb_z_z_z -emit_sve_sbclb :: emit_sve_sbclb_z_z_z -inst_sve_sbclt :: inst_sve_sbclt_z_z_z -emit_sve_sbclt :: emit_sve_sbclt_z_z_z -inst_sve_tbl2 :: inst_sve_tbl2_z_z_z -emit_sve_tbl2 :: emit_sve_tbl2_z_z_z -inst_sve_tbx :: inst_sve_tbx_z_z_z -emit_sve_tbx :: emit_sve_tbx_z_z_z -inst_sve_aese :: inst_sve_aese_z_z -emit_sve_aese :: emit_sve_aese_z_z -inst_sve_aesd :: inst_sve_aesd_z_z -emit_sve_aesd :: emit_sve_aesd_z_z -inst_sve_aesmc :: inst_sve_aesmc_z -emit_sve_aesmc :: emit_sve_aesmc_z -inst_sve_aesimc :: inst_sve_aesimc_z -emit_sve_aesimc :: emit_sve_aesimc_z -inst_sve_bcax_z :: inst_sve_bcax_z_z_z_z_z -emit_sve_bcax_z :: emit_sve_bcax_z_z_z_z_z -inst_sve_xar_z :: inst_sve_xar_z_z_z_z_i -emit_sve_xar_z :: emit_sve_xar_z_z_z_z_i -inst_sve_eor3_z :: inst_sve_eor3_z_z_z_z_z -emit_sve_eor3_z :: emit_sve_eor3_z_z_z_z_z -inst_sve_match :: inst_sve_match_p_p_z_z -emit_sve_match :: emit_sve_match_p_p_z_z -inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z -emit_sve_nmatch :: emit_sve_nmatch_p_p_z_z -inst_sve_histcnt :: inst_sve_histcnt_z_p_z_z -emit_sve_histcnt :: emit_sve_histcnt_z_p_z_z -inst_sve_histseg :: inst_sve_histseg_z_z_z -emit_sve_histseg :: emit_sve_histseg_z_z_z -inst_sme_smstart :: inst_sme_smstart_none -emit_sme_smstart :: emit_sme_smstart_none -inst_sme_smstop :: inst_sme_smstop_none -emit_sme_smstop :: emit_sme_smstop_none -inst_sme_rdsvl :: inst_sme_rdsvl_r_i -emit_sme_rdsvl :: emit_sme_rdsvl_r_i -inst_sme_addha :: inst_sme_addha_i_p_p_z -emit_sme_addha :: emit_sme_addha_i_p_p_z -inst_sme_addva :: inst_sme_addva_i_p_p_z -emit_sme_addva :: emit_sme_addva_i_p_p_z -inst_sme_zero :: inst_sme_zero_i -emit_sme_zero :: emit_sme_zero_i -inst_sme_fmopa :: inst_sme_fmopa_i_p_p_z -emit_sme_fmopa :: emit_sme_fmopa_i_p_p_z -inst_sme_fmops :: inst_sme_fmops_i_p_p_z -emit_sme_fmops :: emit_sme_fmops_i_p_p_z -inst_sme_bfmopa :: inst_sme_bfmopa_i_p_p_z -emit_sme_bfmopa :: emit_sme_bfmopa_i_p_p_z -inst_sme_bfmops :: inst_sme_bfmops_i_p_p_z -emit_sme_bfmops :: emit_sme_bfmops_i_p_p_z -inst_sme_smopa :: inst_sme_smopa_i_p_p_z -emit_sme_smopa :: emit_sme_smopa_i_p_p_z -inst_sme_smops :: inst_sme_smops_i_p_p_z -emit_sme_smops :: emit_sme_smops_i_p_p_z -inst_sme_umopa :: inst_sme_umopa_i_p_p_z -emit_sme_umopa :: emit_sme_umopa_i_p_p_z -inst_sme_umops :: inst_sme_umops_i_p_p_z -emit_sme_umops :: emit_sme_umops_i_p_p_z -inst_sme_usmopa :: inst_sme_usmopa_i_p_p_z -emit_sme_usmopa :: emit_sme_usmopa_i_p_p_z -inst_sme_sumopa :: inst_sme_sumopa_i_p_p_z -emit_sme_sumopa :: emit_sme_sumopa_i_p_p_z -inst_sme_ldr_za :: inst_sme_ldr_za_i_m -emit_sme_ldr_za :: emit_sme_ldr_za_i_m -inst_sme_str_za :: inst_sme_str_za_i_m -emit_sme_str_za :: emit_sme_str_za_i_m -inst_sve_fmla_idx_h :: inst_sve_fmla_idx_h_z_z_z_i -emit_sve_fmla_idx_h :: emit_sve_fmla_idx_h_z_z_z_i -inst_sve_fmla_idx_s :: inst_sve_fmla_idx_s_z_z_z_i -emit_sve_fmla_idx_s :: emit_sve_fmla_idx_s_z_z_z_i -inst_sve_fmla_idx_d :: inst_sve_fmla_idx_d_z_z_z_i -emit_sve_fmla_idx_d :: emit_sve_fmla_idx_d_z_z_z_i -inst_sve_fmls_idx_h :: inst_sve_fmls_idx_h_z_z_z_i -emit_sve_fmls_idx_h :: emit_sve_fmls_idx_h_z_z_z_i -inst_sve_fmls_idx_s :: inst_sve_fmls_idx_s_z_z_z_i -emit_sve_fmls_idx_s :: emit_sve_fmls_idx_s_z_z_z_i -inst_sve_fmls_idx_d :: inst_sve_fmls_idx_d_z_z_z_i -emit_sve_fmls_idx_d :: emit_sve_fmls_idx_d_z_z_z_i -inst_sve_ld1b_gather_s :: inst_sve_ld1b_gather_s_z_p_m -emit_sve_ld1b_gather_s :: emit_sve_ld1b_gather_s_z_p_m -inst_sve_ld1b_gather_d :: inst_sve_ld1b_gather_d_z_p_m -emit_sve_ld1b_gather_d :: emit_sve_ld1b_gather_d_z_p_m -inst_sve_ld1h_gather_s :: inst_sve_ld1h_gather_s_z_p_m -emit_sve_ld1h_gather_s :: emit_sve_ld1h_gather_s_z_p_m -inst_sve_ld1h_gather_d :: inst_sve_ld1h_gather_d_z_p_m -emit_sve_ld1h_gather_d :: emit_sve_ld1h_gather_d_z_p_m -inst_sve_ld1w_gather_s :: inst_sve_ld1w_gather_s_z_p_m -emit_sve_ld1w_gather_s :: emit_sve_ld1w_gather_s_z_p_m -inst_sve_ld1w_gather_d :: inst_sve_ld1w_gather_d_z_p_m -emit_sve_ld1w_gather_d :: emit_sve_ld1w_gather_d_z_p_m -inst_sve_ld1d_gather_d :: inst_sve_ld1d_gather_d_z_p_m -emit_sve_ld1d_gather_d :: emit_sve_ld1d_gather_d_z_p_m -inst_sve_ld1sb_gather_s :: inst_sve_ld1sb_gather_s_z_p_m -emit_sve_ld1sb_gather_s :: emit_sve_ld1sb_gather_s_z_p_m -inst_sve_ld1sb_gather_d :: inst_sve_ld1sb_gather_d_z_p_m -emit_sve_ld1sb_gather_d :: emit_sve_ld1sb_gather_d_z_p_m -inst_sve_ld1sh_gather_s :: inst_sve_ld1sh_gather_s_z_p_m -emit_sve_ld1sh_gather_s :: emit_sve_ld1sh_gather_s_z_p_m -inst_sve_ld1sh_gather_d :: inst_sve_ld1sh_gather_d_z_p_m -emit_sve_ld1sh_gather_d :: emit_sve_ld1sh_gather_d_z_p_m -inst_sve_ld1sw_gather_d :: inst_sve_ld1sw_gather_d_z_p_m -emit_sve_ld1sw_gather_d :: emit_sve_ld1sw_gather_d_z_p_m -inst_sve_st1b_scatter_s :: inst_sve_st1b_scatter_s_z_p_m -emit_sve_st1b_scatter_s :: emit_sve_st1b_scatter_s_z_p_m -inst_sve_st1b_scatter_d :: inst_sve_st1b_scatter_d_z_p_m -emit_sve_st1b_scatter_d :: emit_sve_st1b_scatter_d_z_p_m -inst_sve_st1h_scatter_s :: inst_sve_st1h_scatter_s_z_p_m -emit_sve_st1h_scatter_s :: emit_sve_st1h_scatter_s_z_p_m -inst_sve_st1h_scatter_d :: inst_sve_st1h_scatter_d_z_p_m -emit_sve_st1h_scatter_d :: emit_sve_st1h_scatter_d_z_p_m -inst_sve_st1w_scatter_s :: inst_sve_st1w_scatter_s_z_p_m -emit_sve_st1w_scatter_s :: emit_sve_st1w_scatter_s_z_p_m -inst_sve_st1w_scatter_d :: inst_sve_st1w_scatter_d_z_p_m -emit_sve_st1w_scatter_d :: emit_sve_st1w_scatter_d_z_p_m -inst_sve_st1d_scatter_d :: inst_sve_st1d_scatter_d_z_p_m -emit_sve_st1d_scatter_d :: emit_sve_st1d_scatter_d_z_p_m -inst_sme_ld1b_tile :: inst_sme_ld1b_tile_i_p_m -emit_sme_ld1b_tile :: emit_sme_ld1b_tile_i_p_m -inst_sme_ld1h_tile :: inst_sme_ld1h_tile_i_p_m -emit_sme_ld1h_tile :: emit_sme_ld1h_tile_i_p_m -inst_sme_ld1w_tile :: inst_sme_ld1w_tile_i_p_m -emit_sme_ld1w_tile :: emit_sme_ld1w_tile_i_p_m -inst_sme_ld1d_tile :: inst_sme_ld1d_tile_i_p_m -emit_sme_ld1d_tile :: emit_sme_ld1d_tile_i_p_m -inst_sme_ld1q_tile :: inst_sme_ld1q_tile_i_p_m -emit_sme_ld1q_tile :: emit_sme_ld1q_tile_i_p_m -inst_sme_st1b_tile :: inst_sme_st1b_tile_i_p_m -emit_sme_st1b_tile :: emit_sme_st1b_tile_i_p_m -inst_sme_st1h_tile :: inst_sme_st1h_tile_i_p_m -emit_sme_st1h_tile :: emit_sme_st1h_tile_i_p_m -inst_sme_st1w_tile :: inst_sme_st1w_tile_i_p_m -emit_sme_st1w_tile :: emit_sme_st1w_tile_i_p_m -inst_sme_st1d_tile :: inst_sme_st1d_tile_i_p_m -emit_sme_st1d_tile :: emit_sme_st1d_tile_i_p_m -inst_sme_st1q_tile :: inst_sme_st1q_tile_i_p_m -emit_sme_st1q_tile :: emit_sme_st1q_tile_i_p_m -inst_sme_mova_z_from_tile :: inst_sme_mova_z_from_tile_z_p_i -emit_sme_mova_z_from_tile :: emit_sme_mova_z_from_tile_z_p_i -inst_sme_mova_tile_from_z :: inst_sme_mova_tile_from_z_i_p_z -emit_sme_mova_tile_from_z :: emit_sme_mova_tile_from_z_i_p_z -inst_fcmla_4h :: inst_fcmla_4h_r_r_r_i -emit_fcmla_4h :: emit_fcmla_4h_r_r_r_i -inst_fcmla_8h :: inst_fcmla_8h_r_r_r_i -emit_fcmla_8h :: emit_fcmla_8h_r_r_r_i -inst_fcmla_4s :: inst_fcmla_4s_r_r_r_i -emit_fcmla_4s :: emit_fcmla_4s_r_r_r_i -inst_fcmla_2d :: inst_fcmla_2d_r_r_r_i -emit_fcmla_2d :: emit_fcmla_2d_r_r_r_i -inst_fcadd_4h :: inst_fcadd_4h_r_r_r_i -emit_fcadd_4h :: emit_fcadd_4h_r_r_r_i -inst_fcadd_8h :: inst_fcadd_8h_r_r_r_i -emit_fcadd_8h :: emit_fcadd_8h_r_r_r_i -inst_fcadd_4s :: inst_fcadd_4s_r_r_r_i -emit_fcadd_4s :: emit_fcadd_4s_r_r_r_i -inst_fcadd_2d :: inst_fcadd_2d_r_r_r_i -emit_fcadd_2d :: emit_fcadd_2d_r_r_r_i -inst_sve_prfb :: inst_sve_prfb_i_p_m -emit_sve_prfb :: emit_sve_prfb_i_p_m -inst_sve_prfh :: inst_sve_prfh_i_p_m -emit_sve_prfh :: emit_sve_prfh_i_p_m -inst_sve_prfw :: inst_sve_prfw_i_p_m -emit_sve_prfw :: emit_sve_prfw_i_p_m -inst_sve_prfd :: inst_sve_prfd_i_p_m -emit_sve_prfd :: emit_sve_prfd_i_p_m -inst_sve_ldnt1b :: inst_sve_ldnt1b_z_p_m -emit_sve_ldnt1b :: emit_sve_ldnt1b_z_p_m -inst_sve_ldnt1h :: inst_sve_ldnt1h_z_p_m -emit_sve_ldnt1h :: emit_sve_ldnt1h_z_p_m -inst_sve_ldnt1w :: inst_sve_ldnt1w_z_p_m -emit_sve_ldnt1w :: emit_sve_ldnt1w_z_p_m -inst_sve_ldnt1d :: inst_sve_ldnt1d_z_p_m -emit_sve_ldnt1d :: emit_sve_ldnt1d_z_p_m -inst_sve_stnt1b :: inst_sve_stnt1b_z_p_m -emit_sve_stnt1b :: emit_sve_stnt1b_z_p_m -inst_sve_stnt1h :: inst_sve_stnt1h_z_p_m -emit_sve_stnt1h :: emit_sve_stnt1h_z_p_m -inst_sve_stnt1w :: inst_sve_stnt1w_z_p_m -emit_sve_stnt1w :: emit_sve_stnt1w_z_p_m -inst_sve_stnt1d :: inst_sve_stnt1d_z_p_m -emit_sve_stnt1d :: emit_sve_stnt1d_z_p_m -inst_sve_ext :: inst_sve_ext_z_z_z_i -emit_sve_ext :: emit_sve_ext_z_z_z_i -inst_sve_splice :: inst_sve_splice_z_p_z_z -emit_sve_splice :: emit_sve_splice_z_p_z_z -inst_sve_index_ii :: inst_sve_index_ii_z_i_i -emit_sve_index_ii :: emit_sve_index_ii_z_i_i -inst_sve_index_ir :: inst_sve_index_ir_z_i_r -emit_sve_index_ir :: emit_sve_index_ir_z_i_r -inst_sve_index_ri :: inst_sve_index_ri_z_r_i -emit_sve_index_ri :: emit_sve_index_ri_z_r_i -inst_sve_index_rr :: inst_sve_index_rr_z_r_r -emit_sve_index_rr :: emit_sve_index_rr_z_r_r -inst_sve_bsl :: inst_sve_bsl_z_z_z_z -emit_sve_bsl :: emit_sve_bsl_z_z_z_z -inst_sve_bsl1n :: inst_sve_bsl1n_z_z_z_z -emit_sve_bsl1n :: emit_sve_bsl1n_z_z_z_z -inst_sve_bsl2n :: inst_sve_bsl2n_z_z_z_z -emit_sve_bsl2n :: emit_sve_bsl2n_z_z_z_z -inst_sve_nbsl :: inst_sve_nbsl_z_z_z_z -emit_sve_nbsl :: emit_sve_nbsl_z_z_z_z -inst_sve_pmul_vec :: inst_sve_pmul_vec_z_z_z -emit_sve_pmul_vec :: emit_sve_pmul_vec_z_z_z -inst_sve_pmullb :: inst_sve_pmullb_z_z_z -emit_sve_pmullb :: emit_sve_pmullb_z_z_z -inst_sve_pmullt :: inst_sve_pmullt_z_z_z -emit_sve_pmullt :: emit_sve_pmullt_z_z_z -inst_sve_bfcvt :: inst_sve_bfcvt_z_p_z -emit_sve_bfcvt :: emit_sve_bfcvt_z_p_z -inst_sve_bfcvtnt :: inst_sve_bfcvtnt_z_p_z -emit_sve_bfcvtnt :: emit_sve_bfcvtnt_z_p_z -inst_ldraa :: inst_ldraa_r_m -emit_ldraa :: emit_ldraa_r_m -inst_ldrab :: inst_ldrab_r_m -emit_ldrab :: emit_ldrab_r_m -inst_ldraa_pre :: inst_ldraa_pre_r_m -emit_ldraa_pre :: emit_ldraa_pre_r_m -inst_ldrab_pre :: inst_ldrab_pre_r_m -emit_ldrab_pre :: emit_ldrab_pre_r_m -inst_tstart :: inst_tstart_r -emit_tstart :: emit_tstart_r -inst_tcommit :: inst_tcommit_none -emit_tcommit :: emit_tcommit_none -inst_tcancel :: inst_tcancel_i -emit_tcancel :: emit_tcancel_i -inst_ttest :: inst_ttest_r -emit_ttest :: emit_ttest_r -inst_wfet :: inst_wfet_r -emit_wfet :: emit_wfet_r -inst_wfit :: inst_wfit_r -emit_wfit :: emit_wfit_r -inst_bc_cond :: inst_bc_cond_c_l -emit_bc_cond :: emit_bc_cond_c_l -inst_uxtb :: inst_uxtb_r_r -emit_uxtb :: emit_uxtb_r_r -inst_uxth :: inst_uxth_r_r -emit_uxth :: emit_uxth_r_r -inst_uxtw :: inst_uxtw_r_r -emit_uxtw :: emit_uxtw_r_r -inst_sxtb :: inst_sxtb_r_r -emit_sxtb :: emit_sxtb_r_r -inst_sxth :: inst_sxth_r_r -emit_sxth :: emit_sxth_r_r -inst_sxtw :: inst_sxtw_r_r -emit_sxtw :: emit_sxtw_r_r -inst_adc :: inst_adc_r_r_r -emit_adc :: emit_adc_r_r_r -inst_adcs :: inst_adcs_r_r_r -emit_adcs :: emit_adcs_r_r_r -inst_sbc :: inst_sbc_r_r_r -emit_sbc :: emit_sbc_r_r_r -inst_sbcs :: inst_sbcs_r_r_r -emit_sbcs :: emit_sbcs_r_r_r -inst_ngc :: inst_ngc_r_r -emit_ngc :: emit_ngc_r_r -inst_ngcs :: inst_ngcs_r_r -emit_ngcs :: emit_ngcs_r_r -inst_ldapur :: inst_ldapur_r_m -emit_ldapur :: emit_ldapur_r_m -inst_stlur :: inst_stlur_r_m -emit_stlur :: emit_stlur_r_m -inst_ldapurb :: inst_ldapurb_r_m -emit_ldapurb :: emit_ldapurb_r_m -inst_stlurb :: inst_stlurb_r_m -emit_stlurb :: emit_stlurb_r_m -inst_ldapurh :: inst_ldapurh_r_m -emit_ldapurh :: emit_ldapurh_r_m -inst_stlurh :: inst_stlurh_r_m -emit_stlurh :: emit_stlurh_r_m -inst_ldapursb :: inst_ldapursb_r_m -emit_ldapursb :: emit_ldapursb_r_m -inst_ldapursh :: inst_ldapursh_r_m -emit_ldapursh :: emit_ldapursh_r_m -inst_ldapursw :: inst_ldapursw_r_m -emit_ldapursw :: emit_ldapursw_r_m -inst_sve_bfadd :: inst_sve_bfadd_z_p_z_z -emit_sve_bfadd :: emit_sve_bfadd_z_p_z_z -inst_sve_bfsub :: inst_sve_bfsub_z_p_z_z -emit_sve_bfsub :: emit_sve_bfsub_z_p_z_z -inst_sve_bfmul :: inst_sve_bfmul_z_p_z_z -emit_sve_bfmul :: emit_sve_bfmul_z_p_z_z -inst_sve_bfmla :: inst_sve_bfmla_z_p_z_z -emit_sve_bfmla :: emit_sve_bfmla_z_p_z_z -inst_sve_bfmls :: inst_sve_bfmls_z_p_z_z -emit_sve_bfmls :: emit_sve_bfmls_z_p_z_z -inst_sb :: inst_sb_none -emit_sb :: emit_sb_none -inst_csdb :: inst_csdb_none -emit_csdb :: emit_csdb_none -inst_dgh :: inst_dgh_none -emit_dgh :: emit_dgh_none -inst_psb_csync :: inst_psb_csync_none -emit_psb_csync :: emit_psb_csync_none -inst_tsb_csync :: inst_tsb_csync_none -emit_tsb_csync :: emit_tsb_csync_none -inst_bti_j :: inst_bti_j_none -emit_bti_j :: emit_bti_j_none -inst_bti_c :: inst_bti_c_none -emit_bti_c :: emit_bti_c_none -inst_bti_jc :: inst_bti_jc_none -emit_bti_jc :: emit_bti_jc_none -inst_mov_v_alias :: inst_mov_v_alias_r_r -emit_mov_v_alias :: emit_mov_v_alias_r_r -inst_not_v_alias :: inst_not_v_alias_r_r -emit_not_v_alias :: emit_not_v_alias_r_r -inst_lsl_imm :: inst_lsl_imm_r_r_i -emit_lsl_imm :: emit_lsl_imm_r_r_i -inst_lsr_imm :: inst_lsr_imm_r_r_i -emit_lsr_imm :: emit_lsr_imm_r_r_i -inst_asr_imm :: inst_asr_imm_r_r_i -emit_asr_imm :: emit_asr_imm_r_r_i -inst_ror_imm :: inst_ror_imm_r_r_i -emit_ror_imm :: emit_ror_imm_r_r_i -inst_sve_bfadd_unpred :: inst_sve_bfadd_unpred_z_z_z -emit_sve_bfadd_unpred :: emit_sve_bfadd_unpred_z_z_z -inst_sve_bfsub_unpred :: inst_sve_bfsub_unpred_z_z_z -emit_sve_bfsub_unpred :: emit_sve_bfsub_unpred_z_z_z -inst_sve_bfmul_unpred :: inst_sve_bfmul_unpred_z_z_z -emit_sve_bfmul_unpred :: emit_sve_bfmul_unpred_z_z_z -inst_sve_bfclamp :: inst_sve_bfclamp_z_z_z -emit_sve_bfclamp :: emit_sve_bfclamp_z_z_z -inst_sve_bfmaxnm :: inst_sve_bfmaxnm_z_p_z_z -emit_sve_bfmaxnm :: emit_sve_bfmaxnm_z_p_z_z -inst_sve_bfminnm :: inst_sve_bfminnm_z_p_z_z -emit_sve_bfminnm :: emit_sve_bfminnm_z_p_z_z -inst_sme2_luti2_b :: inst_sme2_luti2_b_z_z_z_i -emit_sme2_luti2_b :: emit_sme2_luti2_b_z_z_z_i -inst_sme2_luti4_b :: inst_sme2_luti4_b_z_z_z_i -emit_sme2_luti4_b :: emit_sme2_luti4_b_z_z_z_i -inst_sme2_ld1b_x2 :: inst_sme2_ld1b_x2_z_p_m -emit_sme2_ld1b_x2 :: emit_sme2_ld1b_x2_z_p_m -inst_sme2_ld1h_x2 :: inst_sme2_ld1h_x2_z_p_m -emit_sme2_ld1h_x2 :: emit_sme2_ld1h_x2_z_p_m -inst_sme2_ld1w_x2 :: inst_sme2_ld1w_x2_z_p_m -emit_sme2_ld1w_x2 :: emit_sme2_ld1w_x2_z_p_m -inst_sme2_ld1d_x2 :: inst_sme2_ld1d_x2_z_p_m -emit_sme2_ld1d_x2 :: emit_sme2_ld1d_x2_z_p_m -inst_sme2_ld1b_x4 :: inst_sme2_ld1b_x4_z_p_m -emit_sme2_ld1b_x4 :: emit_sme2_ld1b_x4_z_p_m -inst_sme2_ld1h_x4 :: inst_sme2_ld1h_x4_z_p_m -emit_sme2_ld1h_x4 :: emit_sme2_ld1h_x4_z_p_m -inst_sme2_ld1w_x4 :: inst_sme2_ld1w_x4_z_p_m -emit_sme2_ld1w_x4 :: emit_sme2_ld1w_x4_z_p_m -inst_sme2_ld1d_x4 :: inst_sme2_ld1d_x4_z_p_m -emit_sme2_ld1d_x4 :: emit_sme2_ld1d_x4_z_p_m -inst_sme2_st1b_x2 :: inst_sme2_st1b_x2_z_p_m -emit_sme2_st1b_x2 :: emit_sme2_st1b_x2_z_p_m -inst_sme2_st1h_x2 :: inst_sme2_st1h_x2_z_p_m -emit_sme2_st1h_x2 :: emit_sme2_st1h_x2_z_p_m -inst_sme2_st1w_x2 :: inst_sme2_st1w_x2_z_p_m -emit_sme2_st1w_x2 :: emit_sme2_st1w_x2_z_p_m -inst_sme2_st1d_x2 :: inst_sme2_st1d_x2_z_p_m -emit_sme2_st1d_x2 :: emit_sme2_st1d_x2_z_p_m -inst_sme2_st1b_x4 :: inst_sme2_st1b_x4_z_p_m -emit_sme2_st1b_x4 :: emit_sme2_st1b_x4_z_p_m -inst_sme2_st1h_x4 :: inst_sme2_st1h_x4_z_p_m -emit_sme2_st1h_x4 :: emit_sme2_st1h_x4_z_p_m -inst_sme2_st1w_x4 :: inst_sme2_st1w_x4_z_p_m -emit_sme2_st1w_x4 :: emit_sme2_st1w_x4_z_p_m -inst_sme2_st1d_x4 :: inst_sme2_st1d_x4_z_p_m -emit_sme2_st1d_x4 :: emit_sme2_st1d_x4_z_p_m -inst_sme2_zip_3 :: inst_sme2_zip_3_z_z_z -emit_sme2_zip_3 :: emit_sme2_zip_3_z_z_z -inst_sme2_zip_4 :: inst_sme2_zip_4_z_z -emit_sme2_zip_4 :: emit_sme2_zip_4_z_z -inst_sme2_uzp_3 :: inst_sme2_uzp_3_z_z_z -emit_sme2_uzp_3 :: emit_sme2_uzp_3_z_z_z -inst_sme2_uzp_4 :: inst_sme2_uzp_4_z_z -emit_sme2_uzp_4 :: emit_sme2_uzp_4_z_z -inst_tlbi_rpalos :: inst_tlbi_rpalos_r -emit_tlbi_rpalos :: emit_tlbi_rpalos_r -inst_tlbi_rpaos :: inst_tlbi_rpaos_r -emit_tlbi_rpaos :: emit_tlbi_rpaos_r -inst_at_s1e1a :: inst_at_s1e1a_r -emit_at_s1e1a :: emit_at_s1e1a_r -inst_dc_cipapa :: inst_dc_cipapa_r -emit_dc_cipapa :: emit_dc_cipapa_r -inst_dc_cigdpapa :: inst_dc_cigdpapa_r -emit_dc_cigdpapa :: emit_dc_cigdpapa_r -inst_tlbi_paall :: inst_tlbi_paall_none -emit_tlbi_paall :: emit_tlbi_paall_none -inst_tlbi_paallos :: inst_tlbi_paallos_none -emit_tlbi_paallos :: emit_tlbi_paallos_none -inst_amx_ldx :: inst_amx_ldx_r -emit_amx_ldx :: emit_amx_ldx_r -inst_amx_ldy :: inst_amx_ldy_r -emit_amx_ldy :: emit_amx_ldy_r -inst_amx_stx :: inst_amx_stx_r -emit_amx_stx :: emit_amx_stx_r -inst_amx_sty :: inst_amx_sty_r -emit_amx_sty :: emit_amx_sty_r -inst_amx_ldz :: inst_amx_ldz_r -emit_amx_ldz :: emit_amx_ldz_r -inst_amx_stz :: inst_amx_stz_r -emit_amx_stz :: emit_amx_stz_r -inst_amx_ldzi :: inst_amx_ldzi_r -emit_amx_ldzi :: emit_amx_ldzi_r -inst_amx_stzi :: inst_amx_stzi_r -emit_amx_stzi :: emit_amx_stzi_r -inst_amx_extrx :: inst_amx_extrx_r -emit_amx_extrx :: emit_amx_extrx_r -inst_amx_extry :: inst_amx_extry_r -emit_amx_extry :: emit_amx_extry_r -inst_amx_fma64 :: inst_amx_fma64_r -emit_amx_fma64 :: emit_amx_fma64_r -inst_amx_fms64 :: inst_amx_fms64_r -emit_amx_fms64 :: emit_amx_fms64_r -inst_amx_fma32 :: inst_amx_fma32_r -emit_amx_fma32 :: emit_amx_fma32_r -inst_amx_fms32 :: inst_amx_fms32_r -emit_amx_fms32 :: emit_amx_fms32_r -inst_amx_mac16 :: inst_amx_mac16_r -emit_amx_mac16 :: emit_amx_mac16_r -inst_amx_fma16 :: inst_amx_fma16_r -emit_amx_fma16 :: emit_amx_fma16_r -inst_amx_fms16 :: inst_amx_fms16_r -emit_amx_fms16 :: emit_amx_fms16_r -inst_amx_set :: inst_amx_set_none -emit_amx_set :: emit_amx_set_none -inst_amx_clr :: inst_amx_clr_none -emit_amx_clr :: emit_amx_clr_none -inst_amx_vecint :: inst_amx_vecint_r -emit_amx_vecint :: emit_amx_vecint_r -inst_amx_vecfp :: inst_amx_vecfp_r -emit_amx_vecfp :: emit_amx_vecfp_r -inst_amx_matint :: inst_amx_matint_r -emit_amx_matint :: emit_amx_matint_r -inst_amx_matfp :: inst_amx_matfp_r -emit_amx_matfp :: emit_amx_matfp_r -inst_amx_genlut :: inst_amx_genlut_r -emit_amx_genlut :: emit_amx_genlut_r -inst_cpyp :: inst_cpyp_r_r_r -emit_cpyp :: emit_cpyp_r_r_r -inst_cpym :: inst_cpym_r_r_r -emit_cpym :: emit_cpym_r_r_r -inst_cpye :: inst_cpye_r_r_r -emit_cpye :: emit_cpye_r_r_r -inst_cpyfp :: inst_cpyfp_r_r_r -emit_cpyfp :: emit_cpyfp_r_r_r -inst_cpyfm :: inst_cpyfm_r_r_r -emit_cpyfm :: emit_cpyfm_r_r_r -inst_cpyfe :: inst_cpyfe_r_r_r -emit_cpyfe :: emit_cpyfe_r_r_r -inst_setp :: inst_setp_r_r_r -emit_setp :: emit_setp_r_r_r -inst_setm :: inst_setm_r_r_r -emit_setm :: emit_setm_r_r_r -inst_sete :: inst_sete_r_r_r -emit_sete :: emit_sete_r_r_r -inst_dc_ivac :: inst_dc_ivac_r -emit_dc_ivac :: emit_dc_ivac_r -inst_dc_isw :: inst_dc_isw_r -emit_dc_isw :: emit_dc_isw_r -inst_dc_csw :: inst_dc_csw_r -emit_dc_csw :: emit_dc_csw_r -inst_dc_cisw :: inst_dc_cisw_r -emit_dc_cisw :: emit_dc_cisw_r -inst_dc_zva :: inst_dc_zva_r -emit_dc_zva :: emit_dc_zva_r -inst_dc_cvac :: inst_dc_cvac_r -emit_dc_cvac :: emit_dc_cvac_r -inst_dc_cvau :: inst_dc_cvau_r -emit_dc_cvau :: emit_dc_cvau_r -inst_dc_civac :: inst_dc_civac_r -emit_dc_civac :: emit_dc_civac_r -inst_ic_ialluis :: inst_ic_ialluis_none -emit_ic_ialluis :: emit_ic_ialluis_none -inst_ic_iallu :: inst_ic_iallu_none -emit_ic_iallu :: emit_ic_iallu_none -inst_ic_ivau :: inst_ic_ivau_r -emit_ic_ivau :: emit_ic_ivau_r -inst_at_s1e1r :: inst_at_s1e1r_r -emit_at_s1e1r :: emit_at_s1e1r_r -inst_at_s1e1w :: inst_at_s1e1w_r -emit_at_s1e1w :: emit_at_s1e1w_r -inst_at_s1e0r :: inst_at_s1e0r_r -emit_at_s1e0r :: emit_at_s1e0r_r -inst_at_s1e0w :: inst_at_s1e0w_r -emit_at_s1e0w :: emit_at_s1e0w_r -inst_at_s1e2r :: inst_at_s1e2r_r -emit_at_s1e2r :: emit_at_s1e2r_r -inst_at_s1e2w :: inst_at_s1e2w_r -emit_at_s1e2w :: emit_at_s1e2w_r -inst_at_s1e3r :: inst_at_s1e3r_r -emit_at_s1e3r :: emit_at_s1e3r_r -inst_at_s1e3w :: inst_at_s1e3w_r -emit_at_s1e3w :: emit_at_s1e3w_r -inst_at_s12e1r :: inst_at_s12e1r_r -emit_at_s12e1r :: emit_at_s12e1r_r -inst_at_s12e1w :: inst_at_s12e1w_r -emit_at_s12e1w :: emit_at_s12e1w_r -inst_at_s12e0r :: inst_at_s12e0r_r -emit_at_s12e0r :: emit_at_s12e0r_r -inst_at_s12e0w :: inst_at_s12e0w_r -emit_at_s12e0w :: emit_at_s12e0w_r -inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none -emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none -inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none -emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none -inst_tlbi_vae1 :: inst_tlbi_vae1_r -emit_tlbi_vae1 :: emit_tlbi_vae1_r -inst_tlbi_vae1is :: inst_tlbi_vae1is_r -emit_tlbi_vae1is :: emit_tlbi_vae1is_r -inst_tlbi_aside1 :: inst_tlbi_aside1_r -emit_tlbi_aside1 :: emit_tlbi_aside1_r -inst_tlbi_aside1is :: inst_tlbi_aside1is_r -emit_tlbi_aside1is :: emit_tlbi_aside1is_r -inst_tlbi_vaae1 :: inst_tlbi_vaae1_r -emit_tlbi_vaae1 :: emit_tlbi_vaae1_r -inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r -emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r -inst_tlbi_vale1 :: inst_tlbi_vale1_r -emit_tlbi_vale1 :: emit_tlbi_vale1_r -inst_tlbi_vale1is :: inst_tlbi_vale1is_r -emit_tlbi_vale1is :: emit_tlbi_vale1is_r -inst_tlbi_vaale1 :: inst_tlbi_vaale1_r -emit_tlbi_vaale1 :: emit_tlbi_vaale1_r -inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r -emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r -inst_tlbi_alle1 :: inst_tlbi_alle1_none -emit_tlbi_alle1 :: emit_tlbi_alle1_none -inst_tlbi_alle1is :: inst_tlbi_alle1is_none -emit_tlbi_alle1is :: emit_tlbi_alle1is_none -inst_tlbi_alle2 :: inst_tlbi_alle2_none -emit_tlbi_alle2 :: emit_tlbi_alle2_none -inst_tlbi_alle2is :: inst_tlbi_alle2is_none -emit_tlbi_alle2is :: emit_tlbi_alle2is_none -inst_tlbi_alle3 :: inst_tlbi_alle3_none -emit_tlbi_alle3 :: emit_tlbi_alle3_none -inst_tlbi_alle3is :: inst_tlbi_alle3is_none -emit_tlbi_alle3is :: emit_tlbi_alle3is_none -inst_prfm :: inst_prfm_i_m -emit_prfm :: emit_prfm_i_m -inst_prfum :: inst_prfum_i_m -emit_prfum :: emit_prfum_i_m -inst_prfm_lit :: inst_prfm_lit_i_l -emit_prfm_lit :: emit_prfm_lit_i_l -inst_mov_reg :: inst_mov_reg_r_r -emit_mov_reg :: emit_mov_reg_r_r -inst_mov_bitmask :: inst_mov_bitmask_r_i -emit_mov_bitmask :: emit_mov_bitmask_r_i -inst_mvn :: inst_mvn_r_r -emit_mvn :: emit_mvn_r_r -inst_neg_sr :: inst_neg_sr_r_sh -emit_neg_sr :: emit_neg_sr_r_sh -inst_negs :: inst_negs_r_sh -emit_negs :: emit_negs_r_sh -inst_cmp_sr :: inst_cmp_sr_r_sh -emit_cmp_sr :: emit_cmp_sr_r_sh -inst_cmp_er :: inst_cmp_er_r_ex -emit_cmp_er :: emit_cmp_er_r_ex -inst_cmp_imm :: inst_cmp_imm_r_i -emit_cmp_imm :: emit_cmp_imm_r_i -inst_cmn_sr :: inst_cmn_sr_r_sh -emit_cmn_sr :: emit_cmn_sr_r_sh -inst_cmn_er :: inst_cmn_er_r_ex -emit_cmn_er :: emit_cmn_er_r_ex -inst_cmn_imm :: inst_cmn_imm_r_i -emit_cmn_imm :: emit_cmn_imm_r_i -inst_tst_sr :: inst_tst_sr_r_sh -emit_tst_sr :: emit_tst_sr_r_sh - -// Aliases: redundant SME names -> canonical tile/MOVA builders. -inst_sme_ld1b_za :: inst_sme_ld1b_tile -emit_sme_ld1b_za :: emit_sme_ld1b_tile -inst_sme_ld1h_za :: inst_sme_ld1h_tile -emit_sme_ld1h_za :: emit_sme_ld1h_tile -inst_sme_ld1w_za :: inst_sme_ld1w_tile -emit_sme_ld1w_za :: emit_sme_ld1w_tile -inst_sme_ld1d_za :: inst_sme_ld1d_tile -emit_sme_ld1d_za :: emit_sme_ld1d_tile -inst_sme_ld1q_za :: inst_sme_ld1q_tile -emit_sme_ld1q_za :: emit_sme_ld1q_tile -inst_sme_st1b_za :: inst_sme_st1b_tile -emit_sme_st1b_za :: emit_sme_st1b_tile -inst_sme_st1h_za :: inst_sme_st1h_tile -emit_sme_st1h_za :: emit_sme_st1h_tile -inst_sme_st1w_za :: inst_sme_st1w_tile -emit_sme_st1w_za :: emit_sme_st1w_tile -inst_sme_st1d_za :: inst_sme_st1d_tile -emit_sme_st1d_za :: emit_sme_st1d_tile -inst_sme_st1q_za :: inst_sme_st1q_tile -emit_sme_st1q_za :: emit_sme_st1q_tile -inst_sme_mova_to_z :: inst_sme_mova_z_from_tile -emit_sme_mova_to_z :: emit_sme_mova_z_from_tile -inst_sme_mova_to_za :: inst_sme_mova_tile_from_z -emit_sme_mova_to_za :: emit_sme_mova_tile_from_z +inst_add :: proc{ inst_add_r_r_i, inst_add_r_r_sh, inst_add_r_r_ex, inst_add_r_r_r, inst_add_z_z_z, inst_add_z_p_z_z } +emit_add :: proc{ emit_add_r_r_i, emit_add_r_r_sh, emit_add_r_r_ex, emit_add_r_r_r, emit_add_z_z_z, emit_add_z_p_z_z } +inst_adds :: proc{ inst_adds_r_r_i, inst_adds_r_r_sh, inst_adds_r_r_ex } +emit_adds :: proc{ emit_adds_r_r_i, emit_adds_r_r_sh, emit_adds_r_r_ex } +inst_sub :: proc{ inst_sub_r_r_i, inst_sub_r_r_sh, inst_sub_r_r_ex, inst_sub_r_r_r, inst_sub_z_z_z, inst_sub_z_p_z_z } +emit_sub :: proc{ emit_sub_r_r_i, emit_sub_r_r_sh, emit_sub_r_r_ex, emit_sub_r_r_r, emit_sub_z_z_z, emit_sub_z_p_z_z } +inst_subs :: proc{ inst_subs_r_r_i, inst_subs_r_r_sh, inst_subs_r_r_ex } +emit_subs :: proc{ emit_subs_r_r_i, emit_subs_r_r_sh, emit_subs_r_r_ex } +inst_movz :: inst_movz_r_i_i +emit_movz :: emit_movz_r_i_i +inst_movn :: inst_movn_r_i_i +emit_movn :: emit_movn_r_i_i +inst_movk :: inst_movk_r_i_i +emit_movk :: emit_movk_r_i_i +inst_adr :: inst_adr_r_l +emit_adr :: emit_adr_r_l +inst_adrp :: inst_adrp_r_l +emit_adrp :: emit_adrp_r_l +inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_r_r_r, inst_and_z_p_z_z } +emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_r_r_r, emit_and_z_p_z_z } +inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_p_p_p_p } +emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_p_p_p_p } +inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_r_r_r, inst_orr_z_p_z_z } +emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_r_r_r, emit_orr_z_p_z_z } +inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_r_r_r, inst_eor_z_p_z_z } +emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_r_r_r, emit_eor_z_p_z_z } +inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_r_r_r, inst_bic_z_p_z_z } +emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_r_r_r, emit_bic_z_p_z_z } +inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_p_p_p_p } +emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_p_p_p_p } +inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_r_r_r, inst_orn_p_p_p_p } +emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_r_r_r, emit_orn_p_p_p_p } +inst_eon :: inst_eon_r_r_sh +emit_eon :: emit_eon_r_r_sh +inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_z_p_z_z, inst_lsl_r_r_i } +emit_lsl :: proc{ emit_lsl_r_r_r, emit_lsl_z_p_z_z, emit_lsl_r_r_i } +inst_lsr :: proc{ inst_lsr_r_r_r, inst_lsr_z_p_z_z, inst_lsr_r_r_i } +emit_lsr :: proc{ emit_lsr_r_r_r, emit_lsr_z_p_z_z, emit_lsr_r_r_i } +inst_asr :: proc{ inst_asr_r_r_r, inst_asr_z_p_z_z, inst_asr_r_r_i } +emit_asr :: proc{ emit_asr_r_r_r, emit_asr_z_p_z_z, emit_asr_r_r_i } +inst_ror :: proc{ inst_ror_r_r_r, inst_ror_r_r_i } +emit_ror :: proc{ emit_ror_r_r_r, emit_ror_r_r_i } +inst_udiv :: proc{ inst_udiv_r_r_r, inst_udiv_z_p_z_z } +emit_udiv :: proc{ emit_udiv_r_r_r, emit_udiv_z_p_z_z } +inst_sdiv :: proc{ inst_sdiv_r_r_r, inst_sdiv_z_p_z_z } +emit_sdiv :: proc{ emit_sdiv_r_r_r, emit_sdiv_z_p_z_z } +inst_madd :: inst_madd_r_r_r_r +emit_madd :: emit_madd_r_r_r_r +inst_msub :: inst_msub_r_r_r_r +emit_msub :: emit_msub_r_r_r_r +inst_smaddl :: inst_smaddl_r_r_r_r +emit_smaddl :: emit_smaddl_r_r_r_r +inst_smsubl :: inst_smsubl_r_r_r_r +emit_smsubl :: emit_smsubl_r_r_r_r +inst_umaddl :: inst_umaddl_r_r_r_r +emit_umaddl :: emit_umaddl_r_r_r_r +inst_umsubl :: inst_umsubl_r_r_r_r +emit_umsubl :: emit_umsubl_r_r_r_r +inst_smulh :: proc{ inst_smulh_r_r_r, inst_smulh_z_p_z_z } +emit_smulh :: proc{ emit_smulh_r_r_r, emit_smulh_z_p_z_z } +inst_umulh :: proc{ inst_umulh_r_r_r, inst_umulh_z_p_z_z } +emit_umulh :: proc{ emit_umulh_r_r_r, emit_umulh_z_p_z_z } +inst_clz :: proc{ inst_clz_r_r, inst_clz_z_p_z } +emit_clz :: proc{ emit_clz_r_r, emit_clz_z_p_z } +inst_cls :: proc{ inst_cls_r_r, inst_cls_z_p_z } +emit_cls :: proc{ emit_cls_r_r, emit_cls_z_p_z } +inst_rbit :: inst_rbit_r_r +emit_rbit :: emit_rbit_r_r +inst_rev :: proc{ inst_rev_r_r, inst_rev_z_z } +emit_rev :: proc{ emit_rev_r_r, emit_rev_z_z } +inst_rev16 :: inst_rev16_r_r +emit_rev16 :: emit_rev16_r_r +inst_rev32 :: inst_rev32_r_r +emit_rev32 :: emit_rev32_r_r +inst_csel :: inst_csel_r_r_r_c +emit_csel :: emit_csel_r_r_r_c +inst_csinc :: inst_csinc_r_r_r_c +emit_csinc :: emit_csinc_r_r_r_c +inst_csinv :: inst_csinv_r_r_r_c +emit_csinv :: emit_csinv_r_r_r_c +inst_csneg :: inst_csneg_r_r_r_c +emit_csneg :: emit_csneg_r_r_r_c +inst_ccmp :: proc{ inst_ccmp_r_r_i_c, inst_ccmp_r_i_i_c } +emit_ccmp :: proc{ emit_ccmp_r_r_i_c, emit_ccmp_r_i_i_c } +inst_ccmn :: proc{ inst_ccmn_r_r_i_c, inst_ccmn_r_i_i_c } +emit_ccmn :: proc{ emit_ccmn_r_r_i_c, emit_ccmn_r_i_i_c } +inst_extr :: inst_extr_r_r_r_i +emit_extr :: emit_extr_r_r_r_i +inst_b :: inst_b_l +emit_b :: emit_b_l +inst_bl :: inst_bl_l +emit_bl :: emit_bl_l +inst_br :: inst_br_r +emit_br :: emit_br_r +inst_blr :: inst_blr_r +emit_blr :: emit_blr_r +inst_ret :: proc{ inst_ret_r, inst_ret_none } +emit_ret :: proc{ emit_ret_r, emit_ret_none } +inst_b_cond :: inst_b_cond_c_l +emit_b_cond :: emit_b_cond_c_l +inst_cbz :: inst_cbz_r_l +emit_cbz :: emit_cbz_r_l +inst_cbnz :: inst_cbnz_r_l +emit_cbnz :: emit_cbnz_r_l +inst_tbz :: inst_tbz_r_i_l +emit_tbz :: emit_tbz_r_i_l +inst_tbnz :: inst_tbnz_r_i_l +emit_tbnz :: emit_tbnz_r_i_l +inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_z_m, inst_ldr_i_m } +emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_z_m, emit_ldr_i_m } +inst_str :: proc{ inst_str_r_m, inst_str_z_m, inst_str_i_m } +emit_str :: proc{ emit_str_r_m, emit_str_z_m, emit_str_i_m } +inst_ldrb :: inst_ldrb_r_m +emit_ldrb :: emit_ldrb_r_m +inst_strb :: inst_strb_r_m +emit_strb :: emit_strb_r_m +inst_ldrsb :: inst_ldrsb_r_m +emit_ldrsb :: emit_ldrsb_r_m +inst_ldrh :: inst_ldrh_r_m +emit_ldrh :: emit_ldrh_r_m +inst_strh :: inst_strh_r_m +emit_strh :: emit_strh_r_m +inst_ldrsh :: inst_ldrsh_r_m +emit_ldrsh :: emit_ldrsh_r_m +inst_ldrsw :: inst_ldrsw_r_m +emit_ldrsw :: emit_ldrsw_r_m +inst_ldp :: inst_ldp_r_r_m +emit_ldp :: emit_ldp_r_r_m +inst_stp :: inst_stp_r_r_m +emit_stp :: emit_stp_r_r_m +inst_ldpsw :: inst_ldpsw_r_r_m +emit_ldpsw :: emit_ldpsw_r_r_m +inst_ldar :: inst_ldar_r_m +emit_ldar :: emit_ldar_r_m +inst_stlr :: inst_stlr_r_m +emit_stlr :: emit_stlr_r_m +inst_ldarb :: inst_ldarb_r_m +emit_ldarb :: emit_ldarb_r_m +inst_stlrb :: inst_stlrb_r_m +emit_stlrb :: emit_stlrb_r_m +inst_ldarh :: inst_ldarh_r_m +emit_ldarh :: emit_ldarh_r_m +inst_stlrh :: inst_stlrh_r_m +emit_stlrh :: emit_stlrh_r_m +inst_ldxr :: inst_ldxr_r_m +emit_ldxr :: emit_ldxr_r_m +inst_stxr :: inst_stxr_r_r_m +emit_stxr :: emit_stxr_r_r_m +inst_ldaxr :: inst_ldaxr_r_m +emit_ldaxr :: emit_ldaxr_r_m +inst_stlxr :: inst_stlxr_r_r_m +emit_stlxr :: emit_stlxr_r_r_m +inst_nop :: inst_nop_none +emit_nop :: emit_nop_none +inst_yield :: inst_yield_none +emit_yield :: emit_yield_none +inst_wfe :: inst_wfe_none +emit_wfe :: emit_wfe_none +inst_wfi :: inst_wfi_none +emit_wfi :: emit_wfi_none +inst_sev :: inst_sev_none +emit_sev :: emit_sev_none +inst_sevl :: inst_sevl_none +emit_sevl :: emit_sevl_none +inst_hint :: inst_hint_i +emit_hint :: emit_hint_i +inst_mrs :: inst_mrs_r_i +emit_mrs :: emit_mrs_r_i +inst_msr :: proc{ inst_msr_i_i, inst_msr_i_r } +emit_msr :: proc{ emit_msr_i_i, emit_msr_i_r } +inst_isb :: inst_isb_i +emit_isb :: emit_isb_i +inst_dsb :: inst_dsb_i +emit_dsb :: emit_dsb_i +inst_dmb :: inst_dmb_i +emit_dmb :: emit_dmb_i +inst_svc :: inst_svc_i +emit_svc :: emit_svc_i +inst_hvc :: inst_hvc_i +emit_hvc :: emit_hvc_i +inst_smc :: inst_smc_i +emit_smc :: emit_smc_i +inst_brk :: inst_brk_i +emit_brk :: emit_brk_i +inst_hlt :: inst_hlt_i +emit_hlt :: emit_hlt_i +inst_eret :: inst_eret_none +emit_eret :: emit_eret_none +inst_fmov :: proc{ inst_fmov_r_r, inst_fmov_r_i } +emit_fmov :: proc{ emit_fmov_r_r, emit_fmov_r_i } +inst_fabs :: proc{ inst_fabs_r_r, inst_fabs_z_p_z } +emit_fabs :: proc{ emit_fabs_r_r, emit_fabs_z_p_z } +inst_fneg :: proc{ inst_fneg_r_r, inst_fneg_z_p_z } +emit_fneg :: proc{ emit_fneg_r_r, emit_fneg_z_p_z } +inst_fsqrt :: proc{ inst_fsqrt_r_r, inst_fsqrt_z_p_z } +emit_fsqrt :: proc{ emit_fsqrt_r_r, emit_fsqrt_z_p_z } +inst_fadd :: proc{ inst_fadd_r_r_r, inst_fadd_z_z_z, inst_fadd_z_p_z_z } +emit_fadd :: proc{ emit_fadd_r_r_r, emit_fadd_z_z_z, emit_fadd_z_p_z_z } +inst_fsub :: proc{ inst_fsub_r_r_r, inst_fsub_z_z_z, inst_fsub_z_p_z_z } +emit_fsub :: proc{ emit_fsub_r_r_r, emit_fsub_z_z_z, emit_fsub_z_p_z_z } +inst_fmul :: proc{ inst_fmul_r_r_r, inst_fmul_z_z_z, inst_fmul_z_p_z_z } +emit_fmul :: proc{ emit_fmul_r_r_r, emit_fmul_z_z_z, emit_fmul_z_p_z_z } +inst_fdiv :: proc{ inst_fdiv_r_r_r, inst_fdiv_z_p_z_z } +emit_fdiv :: proc{ emit_fdiv_r_r_r, emit_fdiv_z_p_z_z } +inst_fnmul :: inst_fnmul_r_r_r +emit_fnmul :: emit_fnmul_r_r_r +inst_fmadd :: inst_fmadd_r_r_r_r +emit_fmadd :: emit_fmadd_r_r_r_r +inst_fmsub :: inst_fmsub_r_r_r_r +emit_fmsub :: emit_fmsub_r_r_r_r +inst_fnmadd :: inst_fnmadd_r_r_r_r +emit_fnmadd :: emit_fnmadd_r_r_r_r +inst_fnmsub :: inst_fnmsub_r_r_r_r +emit_fnmsub :: emit_fnmsub_r_r_r_r +inst_fcmp :: inst_fcmp_r_r +emit_fcmp :: emit_fcmp_r_r +inst_fcmpe :: inst_fcmpe_r_r +emit_fcmpe :: emit_fcmpe_r_r +inst_fcsel :: inst_fcsel_r_r_r_c +emit_fcsel :: emit_fcsel_r_r_r_c +inst_fmax :: proc{ inst_fmax_r_r_r, inst_fmax_z_p_z_z } +emit_fmax :: proc{ emit_fmax_r_r_r, emit_fmax_z_p_z_z } +inst_fmin :: proc{ inst_fmin_r_r_r, inst_fmin_z_p_z_z } +emit_fmin :: proc{ emit_fmin_r_r_r, emit_fmin_z_p_z_z } +inst_fmaxnm :: proc{ inst_fmaxnm_r_r_r, inst_fmaxnm_z_p_z_z } +emit_fmaxnm :: proc{ emit_fmaxnm_r_r_r, emit_fmaxnm_z_p_z_z } +inst_fminnm :: proc{ inst_fminnm_r_r_r, inst_fminnm_z_p_z_z } +emit_fminnm :: proc{ emit_fminnm_r_r_r, emit_fminnm_z_p_z_z } +inst_fcvt :: inst_fcvt_r_r +emit_fcvt :: emit_fcvt_r_r +inst_scvtf :: inst_scvtf_r_r +emit_scvtf :: emit_scvtf_r_r +inst_ucvtf :: inst_ucvtf_r_r +emit_ucvtf :: emit_ucvtf_r_r +inst_fcvtzs :: inst_fcvtzs_r_r +emit_fcvtzs :: emit_fcvtzs_r_r +inst_fcvtzu :: inst_fcvtzu_r_r +emit_fcvtzu :: emit_fcvtzu_r_r +inst_fcvtas :: inst_fcvtas_r_r +emit_fcvtas :: emit_fcvtas_r_r +inst_fcvtau :: inst_fcvtau_r_r +emit_fcvtau :: emit_fcvtau_r_r +inst_fcvtns :: inst_fcvtns_r_r +emit_fcvtns :: emit_fcvtns_r_r +inst_fcvtnu :: inst_fcvtnu_r_r +emit_fcvtnu :: emit_fcvtnu_r_r +inst_fcvtps :: inst_fcvtps_r_r +emit_fcvtps :: emit_fcvtps_r_r +inst_fcvtpu :: inst_fcvtpu_r_r +emit_fcvtpu :: emit_fcvtpu_r_r +inst_fcvtms :: inst_fcvtms_r_r +emit_fcvtms :: emit_fcvtms_r_r +inst_fcvtmu :: inst_fcvtmu_r_r +emit_fcvtmu :: emit_fcvtmu_r_r +inst_frinta :: proc{ inst_frinta_r_r, inst_frinta_z_p_z } +emit_frinta :: proc{ emit_frinta_r_r, emit_frinta_z_p_z } +inst_frinti :: proc{ inst_frinti_r_r, inst_frinti_z_p_z } +emit_frinti :: proc{ emit_frinti_r_r, emit_frinti_z_p_z } +inst_frintm :: proc{ inst_frintm_r_r, inst_frintm_z_p_z } +emit_frintm :: proc{ emit_frintm_r_r, emit_frintm_z_p_z } +inst_frintn :: proc{ inst_frintn_r_r, inst_frintn_z_p_z } +emit_frintn :: proc{ emit_frintn_r_r, emit_frintn_z_p_z } +inst_frintp :: proc{ inst_frintp_r_r, inst_frintp_z_p_z } +emit_frintp :: proc{ emit_frintp_r_r, emit_frintp_z_p_z } +inst_frintx :: proc{ inst_frintx_r_r, inst_frintx_z_p_z } +emit_frintx :: proc{ emit_frintx_r_r, emit_frintx_z_p_z } +inst_frintz :: proc{ inst_frintz_r_r, inst_frintz_z_p_z } +emit_frintz :: proc{ emit_frintz_r_r, emit_frintz_z_p_z } +inst_tst :: proc{ inst_tst_r_i, inst_tst_r_sh } +emit_tst :: proc{ emit_tst_r_i, emit_tst_r_sh } +inst_ldur :: inst_ldur_r_m +emit_ldur :: emit_ldur_r_m +inst_stur :: inst_stur_r_m +emit_stur :: emit_stur_r_m +inst_ldurb :: inst_ldurb_r_m +emit_ldurb :: emit_ldurb_r_m +inst_sturb :: inst_sturb_r_m +emit_sturb :: emit_sturb_r_m +inst_ldursb :: inst_ldursb_r_m +emit_ldursb :: emit_ldursb_r_m +inst_ldurh :: inst_ldurh_r_m +emit_ldurh :: emit_ldurh_r_m +inst_sturh :: inst_sturh_r_m +emit_sturh :: emit_sturh_r_m +inst_ldursh :: inst_ldursh_r_m +emit_ldursh :: emit_ldursh_r_m +inst_ldursw :: inst_ldursw_r_m +emit_ldursw :: emit_ldursw_r_m +inst_ldnp :: inst_ldnp_r_r_m +emit_ldnp :: emit_ldnp_r_r_m +inst_stnp :: inst_stnp_r_r_m +emit_stnp :: emit_stnp_r_r_m +inst_ldxp :: inst_ldxp_r_r_m +emit_ldxp :: emit_ldxp_r_r_m +inst_stxp :: inst_stxp_r_r_r_m +emit_stxp :: emit_stxp_r_r_r_m +inst_ldaxp :: inst_ldaxp_r_r_m +emit_ldaxp :: emit_ldaxp_r_r_m +inst_stlxp :: inst_stlxp_r_r_r_m +emit_stlxp :: emit_stlxp_r_r_r_m +inst_ldxrb :: inst_ldxrb_r_m +emit_ldxrb :: emit_ldxrb_r_m +inst_stxrb :: inst_stxrb_r_r_m +emit_stxrb :: emit_stxrb_r_r_m +inst_ldaxrb :: inst_ldaxrb_r_m +emit_ldaxrb :: emit_ldaxrb_r_m +inst_stlxrb :: inst_stlxrb_r_r_m +emit_stlxrb :: emit_stlxrb_r_r_m +inst_ldxrh :: inst_ldxrh_r_m +emit_ldxrh :: emit_ldxrh_r_m +inst_stxrh :: inst_stxrh_r_r_m +emit_stxrh :: emit_stxrh_r_r_m +inst_ldaxrh :: inst_ldaxrh_r_m +emit_ldaxrh :: emit_ldaxrh_r_m +inst_stlxrh :: inst_stlxrh_r_r_m +emit_stlxrh :: emit_stlxrh_r_r_m +inst_ldapr :: inst_ldapr_r_m +emit_ldapr :: emit_ldapr_r_m +inst_ldaprb :: inst_ldaprb_r_m +emit_ldaprb :: emit_ldaprb_r_m +inst_ldaprh :: inst_ldaprh_r_m +emit_ldaprh :: emit_ldaprh_r_m +inst_ldadd :: inst_ldadd_r_r_m +emit_ldadd :: emit_ldadd_r_r_m +inst_ldadda :: inst_ldadda_r_r_m +emit_ldadda :: emit_ldadda_r_r_m +inst_ldaddl :: inst_ldaddl_r_r_m +emit_ldaddl :: emit_ldaddl_r_r_m +inst_ldaddal :: inst_ldaddal_r_r_m +emit_ldaddal :: emit_ldaddal_r_r_m +inst_ldclr :: inst_ldclr_r_r_m +emit_ldclr :: emit_ldclr_r_r_m +inst_ldclra :: inst_ldclra_r_r_m +emit_ldclra :: emit_ldclra_r_r_m +inst_ldclrl :: inst_ldclrl_r_r_m +emit_ldclrl :: emit_ldclrl_r_r_m +inst_ldclral :: inst_ldclral_r_r_m +emit_ldclral :: emit_ldclral_r_r_m +inst_ldeor :: inst_ldeor_r_r_m +emit_ldeor :: emit_ldeor_r_r_m +inst_ldeora :: inst_ldeora_r_r_m +emit_ldeora :: emit_ldeora_r_r_m +inst_ldeorl :: inst_ldeorl_r_r_m +emit_ldeorl :: emit_ldeorl_r_r_m +inst_ldeoral :: inst_ldeoral_r_r_m +emit_ldeoral :: emit_ldeoral_r_r_m +inst_ldset :: inst_ldset_r_r_m +emit_ldset :: emit_ldset_r_r_m +inst_ldseta :: inst_ldseta_r_r_m +emit_ldseta :: emit_ldseta_r_r_m +inst_ldsetl :: inst_ldsetl_r_r_m +emit_ldsetl :: emit_ldsetl_r_r_m +inst_ldsetal :: inst_ldsetal_r_r_m +emit_ldsetal :: emit_ldsetal_r_r_m +inst_ldsmax :: inst_ldsmax_r_r_m +emit_ldsmax :: emit_ldsmax_r_r_m +inst_ldsmaxa :: inst_ldsmaxa_r_r_m +emit_ldsmaxa :: emit_ldsmaxa_r_r_m +inst_ldsmaxl :: inst_ldsmaxl_r_r_m +emit_ldsmaxl :: emit_ldsmaxl_r_r_m +inst_ldsmaxal :: inst_ldsmaxal_r_r_m +emit_ldsmaxal :: emit_ldsmaxal_r_r_m +inst_ldsmin :: inst_ldsmin_r_r_m +emit_ldsmin :: emit_ldsmin_r_r_m +inst_ldsmina :: inst_ldsmina_r_r_m +emit_ldsmina :: emit_ldsmina_r_r_m +inst_ldsminl :: inst_ldsminl_r_r_m +emit_ldsminl :: emit_ldsminl_r_r_m +inst_ldsminal :: inst_ldsminal_r_r_m +emit_ldsminal :: emit_ldsminal_r_r_m +inst_ldumax :: inst_ldumax_r_r_m +emit_ldumax :: emit_ldumax_r_r_m +inst_ldumaxa :: inst_ldumaxa_r_r_m +emit_ldumaxa :: emit_ldumaxa_r_r_m +inst_ldumaxl :: inst_ldumaxl_r_r_m +emit_ldumaxl :: emit_ldumaxl_r_r_m +inst_ldumaxal :: inst_ldumaxal_r_r_m +emit_ldumaxal :: emit_ldumaxal_r_r_m +inst_ldumin :: inst_ldumin_r_r_m +emit_ldumin :: emit_ldumin_r_r_m +inst_ldumina :: inst_ldumina_r_r_m +emit_ldumina :: emit_ldumina_r_r_m +inst_lduminl :: inst_lduminl_r_r_m +emit_lduminl :: emit_lduminl_r_r_m +inst_lduminal :: inst_lduminal_r_r_m +emit_lduminal :: emit_lduminal_r_r_m +inst_swp :: inst_swp_r_r_m +emit_swp :: emit_swp_r_r_m +inst_swpa :: inst_swpa_r_r_m +emit_swpa :: emit_swpa_r_r_m +inst_swpl :: inst_swpl_r_r_m +emit_swpl :: emit_swpl_r_r_m +inst_swpal :: inst_swpal_r_r_m +emit_swpal :: emit_swpal_r_r_m +inst_cas :: inst_cas_r_r_m +emit_cas :: emit_cas_r_r_m +inst_casa :: inst_casa_r_r_m +emit_casa :: emit_casa_r_r_m +inst_casl :: inst_casl_r_r_m +emit_casl :: emit_casl_r_r_m +inst_casal :: inst_casal_r_r_m +emit_casal :: emit_casal_r_r_m +inst_casb :: inst_casb_r_r_m +emit_casb :: emit_casb_r_r_m +inst_casab :: inst_casab_r_r_m +emit_casab :: emit_casab_r_r_m +inst_caslb :: inst_caslb_r_r_m +emit_caslb :: emit_caslb_r_r_m +inst_casalb :: inst_casalb_r_r_m +emit_casalb :: emit_casalb_r_r_m +inst_cash :: inst_cash_r_r_m +emit_cash :: emit_cash_r_r_m +inst_casah :: inst_casah_r_r_m +emit_casah :: emit_casah_r_r_m +inst_caslh :: inst_caslh_r_r_m +emit_caslh :: emit_caslh_r_r_m +inst_casalh :: inst_casalh_r_r_m +emit_casalh :: emit_casalh_r_r_m +inst_casp :: inst_casp_r_r_m +emit_casp :: emit_casp_r_r_m +inst_caspa :: inst_caspa_r_r_m +emit_caspa :: emit_caspa_r_r_m +inst_caspl :: inst_caspl_r_r_m +emit_caspl :: emit_caspl_r_r_m +inst_caspal :: inst_caspal_r_r_m +emit_caspal :: emit_caspal_r_r_m +inst_pacia :: inst_pacia_r_r +emit_pacia :: emit_pacia_r_r +inst_pacib :: inst_pacib_r_r +emit_pacib :: emit_pacib_r_r +inst_pacda :: inst_pacda_r_r +emit_pacda :: emit_pacda_r_r +inst_pacdb :: inst_pacdb_r_r +emit_pacdb :: emit_pacdb_r_r +inst_paciza :: inst_paciza_r +emit_paciza :: emit_paciza_r +inst_pacizb :: inst_pacizb_r +emit_pacizb :: emit_pacizb_r +inst_pacdza :: inst_pacdza_r +emit_pacdza :: emit_pacdza_r +inst_pacdzb :: inst_pacdzb_r +emit_pacdzb :: emit_pacdzb_r +inst_autia :: inst_autia_r_r +emit_autia :: emit_autia_r_r +inst_autib :: inst_autib_r_r +emit_autib :: emit_autib_r_r +inst_autda :: inst_autda_r_r +emit_autda :: emit_autda_r_r +inst_autdb :: inst_autdb_r_r +emit_autdb :: emit_autdb_r_r +inst_autiza :: inst_autiza_r +emit_autiza :: emit_autiza_r +inst_autizb :: inst_autizb_r +emit_autizb :: emit_autizb_r +inst_autdza :: inst_autdza_r +emit_autdza :: emit_autdza_r +inst_autdzb :: inst_autdzb_r +emit_autdzb :: emit_autdzb_r +inst_paciasp :: inst_paciasp_none +emit_paciasp :: emit_paciasp_none +inst_pacibsp :: inst_pacibsp_none +emit_pacibsp :: emit_pacibsp_none +inst_autiasp :: inst_autiasp_none +emit_autiasp :: emit_autiasp_none +inst_autibsp :: inst_autibsp_none +emit_autibsp :: emit_autibsp_none +inst_pacia1716 :: inst_pacia1716_none +emit_pacia1716 :: emit_pacia1716_none +inst_pacib1716 :: inst_pacib1716_none +emit_pacib1716 :: emit_pacib1716_none +inst_autia1716 :: inst_autia1716_none +emit_autia1716 :: emit_autia1716_none +inst_autib1716 :: inst_autib1716_none +emit_autib1716 :: emit_autib1716_none +inst_pacga :: inst_pacga_r_r_r +emit_pacga :: emit_pacga_r_r_r +inst_xpaci :: inst_xpaci_r +emit_xpaci :: emit_xpaci_r +inst_xpacd :: inst_xpacd_r +emit_xpacd :: emit_xpacd_r +inst_xpaclri :: inst_xpaclri_none +emit_xpaclri :: emit_xpaclri_none +inst_retaa :: inst_retaa_none +emit_retaa :: emit_retaa_none +inst_retab :: inst_retab_none +emit_retab :: emit_retab_none +inst_braa :: inst_braa_r_r +emit_braa :: emit_braa_r_r +inst_brab :: inst_brab_r_r +emit_brab :: emit_brab_r_r +inst_braaz :: inst_braaz_r +emit_braaz :: emit_braaz_r +inst_brabz :: inst_brabz_r +emit_brabz :: emit_brabz_r +inst_blraa :: inst_blraa_r_r +emit_blraa :: emit_blraa_r_r +inst_blrab :: inst_blrab_r_r +emit_blrab :: emit_blrab_r_r +inst_blraaz :: inst_blraaz_r +emit_blraaz :: emit_blraaz_r +inst_blrabz :: inst_blrabz_r +emit_blrabz :: emit_blrabz_r +inst_eretaa :: inst_eretaa_none +emit_eretaa :: emit_eretaa_none +inst_eretab :: inst_eretab_none +emit_eretab :: emit_eretab_none +inst_bti :: inst_bti_i +emit_bti :: emit_bti_i +inst_irg :: inst_irg_r_r_r +emit_irg :: emit_irg_r_r_r +inst_addg :: inst_addg_r_r_i_i +emit_addg :: emit_addg_r_r_i_i +inst_subg :: inst_subg_r_r_i_i +emit_subg :: emit_subg_r_r_i_i +inst_gmi :: inst_gmi_r_r_r +emit_gmi :: emit_gmi_r_r_r +inst_subp :: inst_subp_r_r_r +emit_subp :: emit_subp_r_r_r +inst_subps :: inst_subps_r_r_r +emit_subps :: emit_subps_r_r_r +inst_ldg :: inst_ldg_r_m +emit_ldg :: emit_ldg_r_m +inst_stg :: inst_stg_r_m +emit_stg :: emit_stg_r_m +inst_st2g :: inst_st2g_r_m +emit_st2g :: emit_st2g_r_m +inst_stzg :: inst_stzg_r_m +emit_stzg :: emit_stzg_r_m +inst_stz2g :: inst_stz2g_r_m +emit_stz2g :: emit_stz2g_r_m +inst_stgp :: inst_stgp_r_r_m +emit_stgp :: emit_stgp_r_r_m +inst_ldgm :: inst_ldgm_r_m +emit_ldgm :: emit_ldgm_r_m +inst_stgm :: inst_stgm_r_m +emit_stgm :: emit_stgm_r_m +inst_stzgm :: inst_stzgm_r_m +emit_stzgm :: emit_stzgm_r_m +inst_crc32b :: inst_crc32b_r_r_r +emit_crc32b :: emit_crc32b_r_r_r +inst_crc32h :: inst_crc32h_r_r_r +emit_crc32h :: emit_crc32h_r_r_r +inst_crc32w :: inst_crc32w_r_r_r +emit_crc32w :: emit_crc32w_r_r_r +inst_crc32x :: inst_crc32x_r_r_r +emit_crc32x :: emit_crc32x_r_r_r +inst_crc32cb :: inst_crc32cb_r_r_r +emit_crc32cb :: emit_crc32cb_r_r_r +inst_crc32ch :: inst_crc32ch_r_r_r +emit_crc32ch :: emit_crc32ch_r_r_r +inst_crc32cw :: inst_crc32cw_r_r_r +emit_crc32cw :: emit_crc32cw_r_r_r +inst_crc32cx :: inst_crc32cx_r_r_r +emit_crc32cx :: emit_crc32cx_r_r_r +inst_aese :: proc{ inst_aese_r_r, inst_aese_z_z } +emit_aese :: proc{ emit_aese_r_r, emit_aese_z_z } +inst_aesd :: proc{ inst_aesd_r_r, inst_aesd_z_z } +emit_aesd :: proc{ emit_aesd_r_r, emit_aesd_z_z } +inst_aesmc :: proc{ inst_aesmc_r_r, inst_aesmc_z } +emit_aesmc :: proc{ emit_aesmc_r_r, emit_aesmc_z } +inst_aesimc :: proc{ inst_aesimc_r_r, inst_aesimc_z } +emit_aesimc :: proc{ emit_aesimc_r_r, emit_aesimc_z } +inst_sha1h :: inst_sha1h_r_r +emit_sha1h :: emit_sha1h_r_r +inst_sha1c :: inst_sha1c_r_r_r +emit_sha1c :: emit_sha1c_r_r_r +inst_sha1p :: inst_sha1p_r_r_r +emit_sha1p :: emit_sha1p_r_r_r +inst_sha1m :: inst_sha1m_r_r_r +emit_sha1m :: emit_sha1m_r_r_r +inst_sha1su0 :: inst_sha1su0_r_r_r +emit_sha1su0 :: emit_sha1su0_r_r_r +inst_sha1su1 :: inst_sha1su1_r_r +emit_sha1su1 :: emit_sha1su1_r_r +inst_sha256h :: inst_sha256h_r_r_r +emit_sha256h :: emit_sha256h_r_r_r +inst_sha256h2 :: inst_sha256h2_r_r_r +emit_sha256h2 :: emit_sha256h2_r_r_r +inst_sha256su0 :: inst_sha256su0_r_r +emit_sha256su0 :: emit_sha256su0_r_r +inst_sha256su1 :: inst_sha256su1_r_r_r +emit_sha256su1 :: emit_sha256su1_r_r_r +inst_sha512h :: inst_sha512h_r_r_r +emit_sha512h :: emit_sha512h_r_r_r +inst_sha512h2 :: inst_sha512h2_r_r_r +emit_sha512h2 :: emit_sha512h2_r_r_r +inst_sha512su0 :: inst_sha512su0_r_r +emit_sha512su0 :: emit_sha512su0_r_r +inst_sha512su1 :: inst_sha512su1_r_r_r +emit_sha512su1 :: emit_sha512su1_r_r_r +inst_eor3 :: proc{ inst_eor3_r_r_r_r, inst_eor3_z_z_z_z } +emit_eor3 :: proc{ emit_eor3_r_r_r_r, emit_eor3_z_z_z_z } +inst_bcax :: proc{ inst_bcax_r_r_r_r, inst_bcax_z_z_z_z } +emit_bcax :: proc{ emit_bcax_r_r_r_r, emit_bcax_z_z_z_z } +inst_rax1 :: inst_rax1_r_r_r +emit_rax1 :: emit_rax1_r_r_r +inst_xar :: proc{ inst_xar_r_r_r_i, inst_xar_z_z_z_i } +emit_xar :: proc{ emit_xar_r_r_r_i, emit_xar_z_z_z_i } +inst_sm3partw1 :: inst_sm3partw1_r_r_r +emit_sm3partw1 :: emit_sm3partw1_r_r_r +inst_sm3partw2 :: inst_sm3partw2_r_r_r +emit_sm3partw2 :: emit_sm3partw2_r_r_r +inst_sm3ss1 :: inst_sm3ss1_r_r_r_r +emit_sm3ss1 :: emit_sm3ss1_r_r_r_r +inst_sm3tt1a :: inst_sm3tt1a_r_r_r +emit_sm3tt1a :: emit_sm3tt1a_r_r_r +inst_sm3tt1b :: inst_sm3tt1b_r_r_r +emit_sm3tt1b :: emit_sm3tt1b_r_r_r +inst_sm3tt2a :: inst_sm3tt2a_r_r_r +emit_sm3tt2a :: emit_sm3tt2a_r_r_r +inst_sm3tt2b :: inst_sm3tt2b_r_r_r +emit_sm3tt2b :: emit_sm3tt2b_r_r_r +inst_sm4e :: inst_sm4e_r_r +emit_sm4e :: emit_sm4e_r_r +inst_sm4ekey :: inst_sm4ekey_r_r_r +emit_sm4ekey :: emit_sm4ekey_r_r_r +inst_pmull :: inst_pmull_r_r_r +emit_pmull :: emit_pmull_r_r_r +inst_pmull2 :: inst_pmull2_r_r_r +emit_pmull2 :: emit_pmull2_r_r_r +inst_bfcvt :: proc{ inst_bfcvt_r_r, inst_bfcvt_z_p_z } +emit_bfcvt :: proc{ emit_bfcvt_r_r, emit_bfcvt_z_p_z } +inst_bfdot :: inst_bfdot_r_r_r +emit_bfdot :: emit_bfdot_r_r_r +inst_bfmmla :: inst_bfmmla_r_r_r +emit_bfmmla :: emit_bfmmla_r_r_r +inst_bfmlalb :: inst_bfmlalb_r_r_r +emit_bfmlalb :: emit_bfmlalb_r_r_r +inst_bfmlalt :: inst_bfmlalt_r_r_r +emit_bfmlalt :: emit_bfmlalt_r_r_r +inst_bfcvtn :: inst_bfcvtn_r_r +emit_bfcvtn :: emit_bfcvtn_r_r +inst_bfcvtn2 :: inst_bfcvtn2_r_r +emit_bfcvtn2 :: emit_bfcvtn2_r_r +inst_mul :: proc{ inst_mul_r_r_r, inst_mul_z_p_z_z } +emit_mul :: proc{ emit_mul_r_r_r, emit_mul_z_p_z_z } +inst_mla :: inst_mla_r_r_r +emit_mla :: emit_mla_r_r_r +inst_mls :: inst_mls_r_r_r +emit_mls :: emit_mls_r_r_r +inst_neg :: proc{ inst_neg_r_r, inst_neg_z_p_z, inst_neg_r_sh } +emit_neg :: proc{ emit_neg_r_r, emit_neg_z_p_z, emit_neg_r_sh } +inst_abs :: proc{ inst_abs_r_r, inst_abs_z_p_z } +emit_abs :: proc{ emit_abs_r_r, emit_abs_z_p_z } +inst_shadd :: inst_shadd_r_r_r +emit_shadd :: emit_shadd_r_r_r +inst_uhadd :: inst_uhadd_r_r_r +emit_uhadd :: emit_uhadd_r_r_r +inst_shsub :: inst_shsub_r_r_r +emit_shsub :: emit_shsub_r_r_r +inst_uhsub :: inst_uhsub_r_r_r +emit_uhsub :: emit_uhsub_r_r_r +inst_srhadd :: inst_srhadd_r_r_r +emit_srhadd :: emit_srhadd_r_r_r +inst_urhadd :: inst_urhadd_r_r_r +emit_urhadd :: emit_urhadd_r_r_r +inst_sqadd :: proc{ inst_sqadd_r_r_r, inst_sqadd_z_z_z } +emit_sqadd :: proc{ emit_sqadd_r_r_r, emit_sqadd_z_z_z } +inst_uqadd :: proc{ inst_uqadd_r_r_r, inst_uqadd_z_z_z } +emit_uqadd :: proc{ emit_uqadd_r_r_r, emit_uqadd_z_z_z } +inst_sqsub :: proc{ inst_sqsub_r_r_r, inst_sqsub_z_z_z } +emit_sqsub :: proc{ emit_sqsub_r_r_r, emit_sqsub_z_z_z } +inst_uqsub :: proc{ inst_uqsub_r_r_r, inst_uqsub_z_z_z } +emit_uqsub :: proc{ emit_uqsub_r_r_r, emit_uqsub_z_z_z } +inst_smax :: proc{ inst_smax_r_r_r, inst_smax_z_p_z_z } +emit_smax :: proc{ emit_smax_r_r_r, emit_smax_z_p_z_z } +inst_umax :: proc{ inst_umax_r_r_r, inst_umax_z_p_z_z } +emit_umax :: proc{ emit_umax_r_r_r, emit_umax_z_p_z_z } +inst_smin :: proc{ inst_smin_r_r_r, inst_smin_z_p_z_z } +emit_smin :: proc{ emit_smin_r_r_r, emit_smin_z_p_z_z } +inst_umin :: proc{ inst_umin_r_r_r, inst_umin_z_p_z_z } +emit_umin :: proc{ emit_umin_r_r_r, emit_umin_z_p_z_z } +inst_sabd :: proc{ inst_sabd_r_r_r, inst_sabd_z_p_z_z } +emit_sabd :: proc{ emit_sabd_r_r_r, emit_sabd_z_p_z_z } +inst_uabd :: proc{ inst_uabd_r_r_r, inst_uabd_z_p_z_z } +emit_uabd :: proc{ emit_uabd_r_r_r, emit_uabd_z_p_z_z } +inst_saba :: inst_saba_r_r_r +emit_saba :: emit_saba_r_r_r +inst_uaba :: inst_uaba_r_r_r +emit_uaba :: emit_uaba_r_r_r +inst_addp :: inst_addp_r_r_r +emit_addp :: emit_addp_r_r_r +inst_addv :: inst_addv_r_r +emit_addv :: emit_addv_r_r +inst_saddlp :: inst_saddlp_r_r +emit_saddlp :: emit_saddlp_r_r +inst_uaddlp :: inst_uaddlp_r_r +emit_uaddlp :: emit_uaddlp_r_r +inst_sadalp :: inst_sadalp_r_r +emit_sadalp :: emit_sadalp_r_r +inst_uadalp :: inst_uadalp_r_r +emit_uadalp :: emit_uadalp_r_r +inst_saddlv :: inst_saddlv_r_r +emit_saddlv :: emit_saddlv_r_r +inst_uaddlv :: inst_uaddlv_r_r +emit_uaddlv :: emit_uaddlv_r_r +inst_smaxv :: inst_smaxv_r_r +emit_smaxv :: emit_smaxv_r_r +inst_umaxv :: inst_umaxv_r_r +emit_umaxv :: emit_umaxv_r_r +inst_sminv :: inst_sminv_r_r +emit_sminv :: emit_sminv_r_r +inst_uminv :: inst_uminv_r_r +emit_uminv :: emit_uminv_r_r +inst_smaxp :: inst_smaxp_r_r_r +emit_smaxp :: emit_smaxp_r_r_r +inst_umaxp :: inst_umaxp_r_r_r +emit_umaxp :: emit_umaxp_r_r_r +inst_sminp :: inst_sminp_r_r_r +emit_sminp :: emit_sminp_r_r_r +inst_uminp :: inst_uminp_r_r_r +emit_uminp :: emit_uminp_r_r_r +inst_saddl :: inst_saddl_r_r_r +emit_saddl :: emit_saddl_r_r_r +inst_saddl2 :: inst_saddl2_r_r_r +emit_saddl2 :: emit_saddl2_r_r_r +inst_uaddl :: inst_uaddl_r_r_r +emit_uaddl :: emit_uaddl_r_r_r +inst_uaddl2 :: inst_uaddl2_r_r_r +emit_uaddl2 :: emit_uaddl2_r_r_r +inst_ssubl :: inst_ssubl_r_r_r +emit_ssubl :: emit_ssubl_r_r_r +inst_ssubl2 :: inst_ssubl2_r_r_r +emit_ssubl2 :: emit_ssubl2_r_r_r +inst_usubl :: inst_usubl_r_r_r +emit_usubl :: emit_usubl_r_r_r +inst_usubl2 :: inst_usubl2_r_r_r +emit_usubl2 :: emit_usubl2_r_r_r +inst_saddw :: inst_saddw_r_r_r +emit_saddw :: emit_saddw_r_r_r +inst_saddw2 :: inst_saddw2_r_r_r +emit_saddw2 :: emit_saddw2_r_r_r +inst_uaddw :: inst_uaddw_r_r_r +emit_uaddw :: emit_uaddw_r_r_r +inst_uaddw2 :: inst_uaddw2_r_r_r +emit_uaddw2 :: emit_uaddw2_r_r_r +inst_ssubw :: inst_ssubw_r_r_r +emit_ssubw :: emit_ssubw_r_r_r +inst_ssubw2 :: inst_ssubw2_r_r_r +emit_ssubw2 :: emit_ssubw2_r_r_r +inst_usubw :: inst_usubw_r_r_r +emit_usubw :: emit_usubw_r_r_r +inst_usubw2 :: inst_usubw2_r_r_r +emit_usubw2 :: emit_usubw2_r_r_r +inst_raddhn :: inst_raddhn_r_r_r +emit_raddhn :: emit_raddhn_r_r_r +inst_raddhn2 :: inst_raddhn2_r_r_r +emit_raddhn2 :: emit_raddhn2_r_r_r +inst_rsubhn :: inst_rsubhn_r_r_r +emit_rsubhn :: emit_rsubhn_r_r_r +inst_rsubhn2 :: inst_rsubhn2_r_r_r +emit_rsubhn2 :: emit_rsubhn2_r_r_r +inst_addhn :: inst_addhn_r_r_r +emit_addhn :: emit_addhn_r_r_r +inst_addhn2 :: inst_addhn2_r_r_r +emit_addhn2 :: emit_addhn2_r_r_r +inst_subhn :: inst_subhn_r_r_r +emit_subhn :: emit_subhn_r_r_r +inst_subhn2 :: inst_subhn2_r_r_r +emit_subhn2 :: emit_subhn2_r_r_r +inst_xtn :: inst_xtn_r_r +emit_xtn :: emit_xtn_r_r +inst_xtn2 :: inst_xtn2_r_r +emit_xtn2 :: emit_xtn2_r_r +inst_sqxtn :: inst_sqxtn_r_r +emit_sqxtn :: emit_sqxtn_r_r +inst_sqxtn2 :: inst_sqxtn2_r_r +emit_sqxtn2 :: emit_sqxtn2_r_r +inst_uqxtn :: inst_uqxtn_r_r +emit_uqxtn :: emit_uqxtn_r_r +inst_uqxtn2 :: inst_uqxtn2_r_r +emit_uqxtn2 :: emit_uqxtn2_r_r +inst_sqxtun :: inst_sqxtun_r_r +emit_sqxtun :: emit_sqxtun_r_r +inst_sqxtun2 :: inst_sqxtun2_r_r +emit_sqxtun2 :: emit_sqxtun2_r_r +inst_smull :: inst_smull_r_r_r +emit_smull :: emit_smull_r_r_r +inst_smull2 :: inst_smull2_r_r_r +emit_smull2 :: emit_smull2_r_r_r +inst_umull :: inst_umull_r_r_r +emit_umull :: emit_umull_r_r_r +inst_umull2 :: inst_umull2_r_r_r +emit_umull2 :: emit_umull2_r_r_r +inst_smlal :: inst_smlal_r_r_r +emit_smlal :: emit_smlal_r_r_r +inst_smlal2 :: inst_smlal2_r_r_r +emit_smlal2 :: emit_smlal2_r_r_r +inst_umlal :: inst_umlal_r_r_r +emit_umlal :: emit_umlal_r_r_r +inst_umlal2 :: inst_umlal2_r_r_r +emit_umlal2 :: emit_umlal2_r_r_r +inst_smlsl :: inst_smlsl_r_r_r +emit_smlsl :: emit_smlsl_r_r_r +inst_smlsl2 :: inst_smlsl2_r_r_r +emit_smlsl2 :: emit_smlsl2_r_r_r +inst_umlsl :: inst_umlsl_r_r_r +emit_umlsl :: emit_umlsl_r_r_r +inst_umlsl2 :: inst_umlsl2_r_r_r +emit_umlsl2 :: emit_umlsl2_r_r_r +inst_sqdmull :: inst_sqdmull_r_r_r +emit_sqdmull :: emit_sqdmull_r_r_r +inst_sqdmull2 :: inst_sqdmull2_r_r_r +emit_sqdmull2 :: emit_sqdmull2_r_r_r +inst_sqdmlal :: inst_sqdmlal_r_r_r +emit_sqdmlal :: emit_sqdmlal_r_r_r +inst_sqdmlal2 :: inst_sqdmlal2_r_r_r +emit_sqdmlal2 :: emit_sqdmlal2_r_r_r +inst_sqdmlsl :: inst_sqdmlsl_r_r_r +emit_sqdmlsl :: emit_sqdmlsl_r_r_r +inst_sqdmlsl2 :: inst_sqdmlsl2_r_r_r +emit_sqdmlsl2 :: emit_sqdmlsl2_r_r_r +inst_sqdmulh :: inst_sqdmulh_r_r_r +emit_sqdmulh :: emit_sqdmulh_r_r_r +inst_sqrdmulh :: inst_sqrdmulh_r_r_r +emit_sqrdmulh :: emit_sqrdmulh_r_r_r +inst_sdot :: inst_sdot_r_r_r +emit_sdot :: emit_sdot_r_r_r +inst_udot :: inst_udot_r_r_r +emit_udot :: emit_udot_r_r_r +inst_usdot :: inst_usdot_r_r_r +emit_usdot :: emit_usdot_r_r_r +inst_fmla :: proc{ inst_fmla_r_r_r, inst_fmla_z_p_z_z, inst_fmla_z_z_z_i } +emit_fmla :: proc{ emit_fmla_r_r_r, emit_fmla_z_p_z_z, emit_fmla_z_z_z_i } +inst_fmls :: proc{ inst_fmls_r_r_r, inst_fmls_z_p_z_z, inst_fmls_z_z_z_i } +emit_fmls :: proc{ emit_fmls_r_r_r, emit_fmls_z_p_z_z, emit_fmls_z_z_z_i } +inst_fmulx :: inst_fmulx_r_r_r +emit_fmulx :: emit_fmulx_r_r_r +inst_fmaxp :: inst_fmaxp_r_r_r +emit_fmaxp :: emit_fmaxp_r_r_r +inst_fminp :: inst_fminp_r_r_r +emit_fminp :: emit_fminp_r_r_r +inst_fmaxnmp :: inst_fmaxnmp_r_r_r +emit_fmaxnmp :: emit_fmaxnmp_r_r_r +inst_fminnmp :: inst_fminnmp_r_r_r +emit_fminnmp :: emit_fminnmp_r_r_r +inst_fmaxv :: inst_fmaxv_r_r +emit_fmaxv :: emit_fmaxv_r_r +inst_fminv :: inst_fminv_r_r +emit_fminv :: emit_fminv_r_r +inst_fmaxnmv :: inst_fmaxnmv_r_r +emit_fmaxnmv :: emit_fmaxnmv_r_r +inst_fminnmv :: inst_fminnmv_r_r +emit_fminnmv :: emit_fminnmv_r_r +inst_frecpe :: inst_frecpe_r_r +emit_frecpe :: emit_frecpe_r_r +inst_frsqrte :: inst_frsqrte_r_r +emit_frsqrte :: emit_frsqrte_r_r +inst_frecps :: proc{ inst_frecps_r_r_r, inst_frecps_z_z_z } +emit_frecps :: proc{ emit_frecps_r_r_r, emit_frecps_z_z_z } +inst_frsqrts :: proc{ inst_frsqrts_r_r_r, inst_frsqrts_z_z_z } +emit_frsqrts :: proc{ emit_frsqrts_r_r_r, emit_frsqrts_z_z_z } +inst_frecpx :: proc{ inst_frecpx_r_r, inst_frecpx_z_p_z } +emit_frecpx :: proc{ emit_frecpx_r_r, emit_frecpx_z_p_z } +inst_faddp :: inst_faddp_r_r_r +emit_faddp :: emit_faddp_r_r_r +inst_fcvtl :: inst_fcvtl_r_r +emit_fcvtl :: emit_fcvtl_r_r +inst_fcvtl2 :: inst_fcvtl2_r_r +emit_fcvtl2 :: emit_fcvtl2_r_r +inst_fcvtn :: inst_fcvtn_r_r +emit_fcvtn :: emit_fcvtn_r_r +inst_fcvtn2 :: inst_fcvtn2_r_r +emit_fcvtn2 :: emit_fcvtn2_r_r +inst_fcvtxn :: inst_fcvtxn_r_r +emit_fcvtxn :: emit_fcvtxn_r_r +inst_fcvtxn2 :: inst_fcvtxn2_r_r +emit_fcvtxn2 :: emit_fcvtxn2_r_r +inst_fcmeq :: proc{ inst_fcmeq_r_r_r, inst_fcmeq_p_p_z_z } +emit_fcmeq :: proc{ emit_fcmeq_r_r_r, emit_fcmeq_p_p_z_z } +inst_fcmge :: proc{ inst_fcmge_r_r_r, inst_fcmge_p_p_z_z } +emit_fcmge :: proc{ emit_fcmge_r_r_r, emit_fcmge_p_p_z_z } +inst_fcmgt :: proc{ inst_fcmgt_r_r_r, inst_fcmgt_p_p_z_z } +emit_fcmgt :: proc{ emit_fcmgt_r_r_r, emit_fcmgt_p_p_z_z } +inst_fcmle :: proc{ inst_fcmle_r_r, inst_fcmle_p_p_z } +emit_fcmle :: proc{ emit_fcmle_r_r, emit_fcmle_p_p_z } +inst_fcmlt :: proc{ inst_fcmlt_r_r, inst_fcmlt_p_p_z } +emit_fcmlt :: proc{ emit_fcmlt_r_r, emit_fcmlt_p_p_z } +inst_facge :: inst_facge_r_r_r +emit_facge :: emit_facge_r_r_r +inst_facgt :: inst_facgt_r_r_r +emit_facgt :: emit_facgt_r_r_r +inst_cmeq :: inst_cmeq_r_r_r +emit_cmeq :: emit_cmeq_r_r_r +inst_cmge :: inst_cmge_r_r_r +emit_cmge :: emit_cmge_r_r_r +inst_cmgt :: inst_cmgt_r_r_r +emit_cmgt :: emit_cmgt_r_r_r +inst_cmhi :: inst_cmhi_r_r_r +emit_cmhi :: emit_cmhi_r_r_r +inst_cmhs :: inst_cmhs_r_r_r +emit_cmhs :: emit_cmhs_r_r_r +inst_cmle :: inst_cmle_r_r +emit_cmle :: emit_cmle_r_r +inst_cmlt :: inst_cmlt_r_r +emit_cmlt :: emit_cmlt_r_r +inst_cmtst :: inst_cmtst_r_r_r +emit_cmtst :: emit_cmtst_r_r_r +inst_mvn :: inst_mvn_r_r +emit_mvn :: emit_mvn_r_r +inst_bit :: inst_bit_r_r_r +emit_bit :: emit_bit_r_r_r +inst_bif :: inst_bif_r_r_r +emit_bif :: emit_bif_r_r_r +inst_bsl :: proc{ inst_bsl_r_r_r, inst_bsl_z_z_z_z } +emit_bsl :: proc{ emit_bsl_r_r_r, emit_bsl_z_z_z_z } +inst_shl :: inst_shl_r_r_i +emit_shl :: emit_shl_r_r_i +inst_sqshl :: inst_sqshl_r_r_i +emit_sqshl :: emit_sqshl_r_r_i +inst_sqshlu :: inst_sqshlu_r_r_i +emit_sqshlu :: emit_sqshlu_r_r_i +inst_srshl :: inst_srshl_r_r_r +emit_srshl :: emit_srshl_r_r_r +inst_urshl :: inst_urshl_r_r_r +emit_urshl :: emit_urshl_r_r_r +inst_sshr :: inst_sshr_r_r_i +emit_sshr :: emit_sshr_r_r_i +inst_ushr :: inst_ushr_r_r_i +emit_ushr :: emit_ushr_r_r_i +inst_ssra :: inst_ssra_r_r_i +emit_ssra :: emit_ssra_r_r_i +inst_usra :: inst_usra_r_r_i +emit_usra :: emit_usra_r_r_i +inst_srshr :: inst_srshr_r_r_i +emit_srshr :: emit_srshr_r_r_i +inst_urshr :: inst_urshr_r_r_i +emit_urshr :: emit_urshr_r_r_i +inst_srsra :: inst_srsra_r_r_i +emit_srsra :: emit_srsra_r_r_i +inst_ursra :: inst_ursra_r_r_i +emit_ursra :: emit_ursra_r_r_i +inst_sshl :: inst_sshl_r_r_r +emit_sshl :: emit_sshl_r_r_r +inst_ushl :: inst_ushl_r_r_r +emit_ushl :: emit_ushl_r_r_r +inst_sli :: inst_sli_r_r_i +emit_sli :: emit_sli_r_r_i +inst_sri :: inst_sri_r_r_i +emit_sri :: emit_sri_r_r_i +inst_sshll :: inst_sshll_r_r_i +emit_sshll :: emit_sshll_r_r_i +inst_sshll2 :: inst_sshll2_r_r_i +emit_sshll2 :: emit_sshll2_r_r_i +inst_ushll :: inst_ushll_r_r_i +emit_ushll :: emit_ushll_r_r_i +inst_ushll2 :: inst_ushll2_r_r_i +emit_ushll2 :: emit_ushll2_r_r_i +inst_sxtl :: inst_sxtl_r_r +emit_sxtl :: emit_sxtl_r_r +inst_sxtl2 :: inst_sxtl2_r_r +emit_sxtl2 :: emit_sxtl2_r_r +inst_uxtl :: inst_uxtl_r_r +emit_uxtl :: emit_uxtl_r_r +inst_uxtl2 :: inst_uxtl2_r_r +emit_uxtl2 :: emit_uxtl2_r_r +inst_shrn :: inst_shrn_r_r_i +emit_shrn :: emit_shrn_r_r_i +inst_shrn2 :: inst_shrn2_r_r_i +emit_shrn2 :: emit_shrn2_r_r_i +inst_rshrn :: inst_rshrn_r_r_i +emit_rshrn :: emit_rshrn_r_r_i +inst_rshrn2 :: inst_rshrn2_r_r_i +emit_rshrn2 :: emit_rshrn2_r_r_i +inst_sqshrn :: inst_sqshrn_r_r_i +emit_sqshrn :: emit_sqshrn_r_r_i +inst_sqshrn2 :: inst_sqshrn2_r_r_i +emit_sqshrn2 :: emit_sqshrn2_r_r_i +inst_uqshrn :: inst_uqshrn_r_r_i +emit_uqshrn :: emit_uqshrn_r_r_i +inst_uqshrn2 :: inst_uqshrn2_r_r_i +emit_uqshrn2 :: emit_uqshrn2_r_r_i +inst_sqrshrn :: inst_sqrshrn_r_r_i +emit_sqrshrn :: emit_sqrshrn_r_r_i +inst_sqrshrn2 :: inst_sqrshrn2_r_r_i +emit_sqrshrn2 :: emit_sqrshrn2_r_r_i +inst_uqrshrn :: inst_uqrshrn_r_r_i +emit_uqrshrn :: emit_uqrshrn_r_r_i +inst_uqrshrn2 :: inst_uqrshrn2_r_r_i +emit_uqrshrn2 :: emit_uqrshrn2_r_r_i +inst_sqshrun :: inst_sqshrun_r_r_i +emit_sqshrun :: emit_sqshrun_r_r_i +inst_sqshrun2 :: inst_sqshrun2_r_r_i +emit_sqshrun2 :: emit_sqshrun2_r_r_i +inst_sqrshrun :: inst_sqrshrun_r_r_i +emit_sqrshrun :: emit_sqrshrun_r_r_i +inst_sqrshrun2 :: inst_sqrshrun2_r_r_i +emit_sqrshrun2 :: emit_sqrshrun2_r_r_i +inst_dup :: proc{ inst_dup_r_r_i, inst_dup_r_r, inst_dup_z_r } +emit_dup :: proc{ emit_dup_r_r_i, emit_dup_r_r, emit_dup_z_r } +inst_ins :: proc{ inst_ins_r_i_r_i, inst_ins_r_i_r } +emit_ins :: proc{ emit_ins_r_i_r_i, emit_ins_r_i_r } +inst_mov :: proc{ inst_mov_r_r, inst_mov_z_p_z, inst_mov_p_p, inst_mov_r_i } +emit_mov :: proc{ emit_mov_r_r, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } +inst_ext :: proc{ inst_ext_r_r_r_i, inst_ext_z_z_z_i } +emit_ext :: proc{ emit_ext_r_r_r_i, emit_ext_z_z_z_i } +inst_tbl :: proc{ inst_tbl_r_r_r, inst_tbl_z_z_z } +emit_tbl :: proc{ emit_tbl_r_r_r, emit_tbl_z_z_z } +inst_tbx :: proc{ inst_tbx_r_r_r, inst_tbx_z_z_z } +emit_tbx :: proc{ emit_tbx_r_r_r, emit_tbx_z_z_z } +inst_zip1 :: proc{ inst_zip1_r_r_r, inst_zip1_z_z_z } +emit_zip1 :: proc{ emit_zip1_r_r_r, emit_zip1_z_z_z } +inst_zip2 :: proc{ inst_zip2_r_r_r, inst_zip2_z_z_z } +emit_zip2 :: proc{ emit_zip2_r_r_r, emit_zip2_z_z_z } +inst_uzp1 :: proc{ inst_uzp1_r_r_r, inst_uzp1_z_z_z } +emit_uzp1 :: proc{ emit_uzp1_r_r_r, emit_uzp1_z_z_z } +inst_uzp2 :: proc{ inst_uzp2_r_r_r, inst_uzp2_z_z_z } +emit_uzp2 :: proc{ emit_uzp2_r_r_r, emit_uzp2_z_z_z } +inst_trn1 :: proc{ inst_trn1_r_r_r, inst_trn1_z_z_z } +emit_trn1 :: proc{ emit_trn1_r_r_r, emit_trn1_z_z_z } +inst_trn2 :: proc{ inst_trn2_r_r_r, inst_trn2_z_z_z } +emit_trn2 :: proc{ emit_trn2_r_r_r, emit_trn2_z_z_z } +inst_not :: proc{ inst_not_r_r, inst_not_p_p_p } +emit_not :: proc{ emit_not_r_r, emit_not_p_p_p } +inst_rev64 :: inst_rev64_r_r +emit_rev64 :: emit_rev64_r_r +inst_cnt :: proc{ inst_cnt_r_r, inst_cnt_z_p_z } +emit_cnt :: proc{ emit_cnt_r_r, emit_cnt_z_p_z } +inst_urecpe :: inst_urecpe_r_r +emit_urecpe :: emit_urecpe_r_r +inst_ursqrte :: inst_ursqrte_r_r +emit_ursqrte :: emit_ursqrte_r_r +inst_movi :: inst_movi_r_i +emit_movi :: emit_movi_r_i +inst_mvni :: inst_mvni_r_i +emit_mvni :: emit_mvni_r_i +inst_ld1 :: proc{ inst_ld1_r_m, inst_ld1_r_i_m } +emit_ld1 :: proc{ emit_ld1_r_m, emit_ld1_r_i_m } +inst_ld2 :: proc{ inst_ld2_r_m, inst_ld2_r_i_m } +emit_ld2 :: proc{ emit_ld2_r_m, emit_ld2_r_i_m } +inst_ld3 :: proc{ inst_ld3_r_m, inst_ld3_r_i_m } +emit_ld3 :: proc{ emit_ld3_r_m, emit_ld3_r_i_m } +inst_ld4 :: proc{ inst_ld4_r_m, inst_ld4_r_i_m } +emit_ld4 :: proc{ emit_ld4_r_m, emit_ld4_r_i_m } +inst_st1 :: proc{ inst_st1_r_m, inst_st1_r_i_m } +emit_st1 :: proc{ emit_st1_r_m, emit_st1_r_i_m } +inst_st2 :: proc{ inst_st2_r_m, inst_st2_r_i_m } +emit_st2 :: proc{ emit_st2_r_m, emit_st2_r_i_m } +inst_st3 :: proc{ inst_st3_r_m, inst_st3_r_i_m } +emit_st3 :: proc{ emit_st3_r_m, emit_st3_r_i_m } +inst_st4 :: proc{ inst_st4_r_m, inst_st4_r_i_m } +emit_st4 :: proc{ emit_st4_r_m, emit_st4_r_i_m } +inst_ld1r :: inst_ld1r_r_m +emit_ld1r :: emit_ld1r_r_m +inst_ld2r :: inst_ld2r_r_m +emit_ld2r :: emit_ld2r_r_m +inst_ld3r :: inst_ld3r_r_m +emit_ld3r :: emit_ld3r_r_m +inst_ld4r :: inst_ld4r_r_m +emit_ld4r :: emit_ld4r_r_m +inst_subr :: inst_subr_z_p_z_z +emit_subr :: emit_subr_z_p_z_z +inst_asrr :: inst_asrr_z_p_z_z +emit_asrr :: emit_asrr_z_p_z_z +inst_lslr :: inst_lslr_z_p_z_z +emit_lslr :: emit_lslr_z_p_z_z +inst_lsrr :: inst_lsrr_z_p_z_z +emit_lsrr :: emit_lsrr_z_p_z_z +inst_ftsmul :: inst_ftsmul_z_z_z +emit_ftsmul :: emit_ftsmul_z_z_z +inst_fsubr :: inst_fsubr_z_p_z_z +emit_fsubr :: emit_fsubr_z_p_z_z +inst_fdivr :: inst_fdivr_z_p_z_z +emit_fdivr :: emit_fdivr_z_p_z_z +inst_fnmla :: inst_fnmla_z_p_z_z +emit_fnmla :: emit_fnmla_z_p_z_z +inst_fnmls :: inst_fnmls_z_p_z_z +emit_fnmls :: emit_fnmls_z_p_z_z +inst_nand :: inst_nand_p_p_p_p +emit_nand :: emit_nand_p_p_p_p +inst_nor :: inst_nor_p_p_p_p +emit_nor :: emit_nor_p_p_p_p +inst_sel :: inst_sel_p_p_p_p +emit_sel :: emit_sel_p_p_p_p +inst_orrs :: inst_orrs_p_p_p_p +emit_orrs :: emit_orrs_p_p_p_p +inst_eors :: inst_eors_p_p_p_p +emit_eors :: emit_eors_p_p_p_p +inst_nands :: inst_nands_p_p_p_p +emit_nands :: emit_nands_p_p_p_p +inst_nors :: inst_nors_p_p_p_p +emit_nors :: emit_nors_p_p_p_p +inst_orns :: inst_orns_p_p_p_p +emit_orns :: emit_orns_p_p_p_p +inst_movs :: inst_movs_p_p_p +emit_movs :: emit_movs_p_p_p +inst_ptrue :: inst_ptrue_p_i +emit_ptrue :: emit_ptrue_p_i +inst_ptrues :: inst_ptrues_p_i +emit_ptrues :: emit_ptrues_p_i +inst_pfalse :: inst_pfalse_p +emit_pfalse :: emit_pfalse_p +inst_pfirst :: inst_pfirst_p_p_p +emit_pfirst :: emit_pfirst_p_p_p +inst_pnext :: inst_pnext_p_p_p +emit_pnext :: emit_pnext_p_p_p +inst_brka :: inst_brka_p_p_p +emit_brka :: emit_brka_p_p_p +inst_brkb :: inst_brkb_p_p_p +emit_brkb :: emit_brkb_p_p_p +inst_brkas :: inst_brkas_p_p_p +emit_brkas :: emit_brkas_p_p_p +inst_brkbs :: inst_brkbs_p_p_p +emit_brkbs :: emit_brkbs_p_p_p +inst_brkpa :: inst_brkpa_p_p_p_p +emit_brkpa :: emit_brkpa_p_p_p_p +inst_brkpb :: inst_brkpb_p_p_p_p +emit_brkpb :: emit_brkpb_p_p_p_p +inst_brkn :: inst_brkn_p_p_p_p +emit_brkn :: emit_brkn_p_p_p_p +inst_rdffr :: inst_rdffr_p +emit_rdffr :: emit_rdffr_p +inst_wrffr :: inst_wrffr_p +emit_wrffr :: emit_wrffr_p +inst_setffr :: inst_setffr_none +emit_setffr :: emit_setffr_none +inst_cmpeq :: inst_cmpeq_p_p_z_z +emit_cmpeq :: emit_cmpeq_p_p_z_z +inst_cmpne :: inst_cmpne_p_p_z_z +emit_cmpne :: emit_cmpne_p_p_z_z +inst_cmpge :: inst_cmpge_p_p_z_z +emit_cmpge :: emit_cmpge_p_p_z_z +inst_cmpgt :: inst_cmpgt_p_p_z_z +emit_cmpgt :: emit_cmpgt_p_p_z_z +inst_cmple :: inst_cmple_p_p_z_z +emit_cmple :: emit_cmple_p_p_z_z +inst_cmplt :: inst_cmplt_p_p_z_z +emit_cmplt :: emit_cmplt_p_p_z_z +inst_cmphi :: inst_cmphi_p_p_z_z +emit_cmphi :: emit_cmphi_p_p_z_z +inst_cmphs :: inst_cmphs_p_p_z_z +emit_cmphs :: emit_cmphs_p_p_z_z +inst_cmplo :: inst_cmplo_p_p_z_z +emit_cmplo :: emit_cmplo_p_p_z_z +inst_cmpls :: inst_cmpls_p_p_z_z +emit_cmpls :: emit_cmpls_p_p_z_z +inst_fcmne :: inst_fcmne_p_p_z_z +emit_fcmne :: emit_fcmne_p_p_z_z +inst_fcmuo :: inst_fcmuo_p_p_z_z +emit_fcmuo :: emit_fcmuo_p_p_z_z +inst_insr :: inst_insr_z_r +emit_insr :: emit_insr_z_r +inst_cpy :: inst_cpy_z_p_r +emit_cpy :: emit_cpy_z_p_r +inst_compact :: inst_compact_z_p_z +emit_compact :: emit_compact_z_p_z +inst_ld1b :: proc{ inst_ld1b_z_p_m, inst_ld1b_i_p_m } +emit_ld1b :: proc{ emit_ld1b_z_p_m, emit_ld1b_i_p_m } +inst_ld1h :: proc{ inst_ld1h_z_p_m, inst_ld1h_i_p_m } +emit_ld1h :: proc{ emit_ld1h_z_p_m, emit_ld1h_i_p_m } +inst_ld1w :: proc{ inst_ld1w_z_p_m, inst_ld1w_i_p_m } +emit_ld1w :: proc{ emit_ld1w_z_p_m, emit_ld1w_i_p_m } +inst_ld1d :: proc{ inst_ld1d_z_p_m, inst_ld1d_i_p_m } +emit_ld1d :: proc{ emit_ld1d_z_p_m, emit_ld1d_i_p_m } +inst_ld1sb :: inst_ld1sb_z_p_m +emit_ld1sb :: emit_ld1sb_z_p_m +inst_ld1sh :: inst_ld1sh_z_p_m +emit_ld1sh :: emit_ld1sh_z_p_m +inst_ld1sw :: inst_ld1sw_z_p_m +emit_ld1sw :: emit_ld1sw_z_p_m +inst_st1b :: proc{ inst_st1b_z_p_m, inst_st1b_i_p_m } +emit_st1b :: proc{ emit_st1b_z_p_m, emit_st1b_i_p_m } +inst_st1h :: proc{ inst_st1h_z_p_m, inst_st1h_i_p_m } +emit_st1h :: proc{ emit_st1h_z_p_m, emit_st1h_i_p_m } +inst_st1w :: proc{ inst_st1w_z_p_m, inst_st1w_i_p_m } +emit_st1w :: proc{ emit_st1w_z_p_m, emit_st1w_i_p_m } +inst_st1d :: proc{ inst_st1d_z_p_m, inst_st1d_i_p_m } +emit_st1d :: proc{ emit_st1d_z_p_m, emit_st1d_i_p_m } +inst_ldff1b :: inst_ldff1b_z_p_m +emit_ldff1b :: emit_ldff1b_z_p_m +inst_ldff1h :: inst_ldff1h_z_p_m +emit_ldff1h :: emit_ldff1h_z_p_m +inst_ldff1w :: inst_ldff1w_z_p_m +emit_ldff1w :: emit_ldff1w_z_p_m +inst_ldff1d :: inst_ldff1d_z_p_m +emit_ldff1d :: emit_ldff1d_z_p_m +inst_whilege :: inst_whilege_p_r_r +emit_whilege :: emit_whilege_p_r_r +inst_whilegt :: inst_whilegt_p_r_r +emit_whilegt :: emit_whilegt_p_r_r +inst_whilele :: inst_whilele_p_r_r +emit_whilele :: emit_whilele_p_r_r +inst_whilelt :: inst_whilelt_p_r_r +emit_whilelt :: emit_whilelt_p_r_r +inst_whilehi :: inst_whilehi_p_r_r +emit_whilehi :: emit_whilehi_p_r_r +inst_whilehs :: inst_whilehs_p_r_r +emit_whilehs :: emit_whilehs_p_r_r +inst_whilelo :: inst_whilelo_p_r_r +emit_whilelo :: emit_whilelo_p_r_r +inst_whilels :: inst_whilels_p_r_r +emit_whilels :: emit_whilels_p_r_r +inst_sqrdmlah :: inst_sqrdmlah_z_z_z +emit_sqrdmlah :: emit_sqrdmlah_z_z_z +inst_sqrdmlsh :: inst_sqrdmlsh_z_z_z +emit_sqrdmlsh :: emit_sqrdmlsh_z_z_z +inst_adclb :: inst_adclb_z_z_z +emit_adclb :: emit_adclb_z_z_z +inst_adclt :: inst_adclt_z_z_z +emit_adclt :: emit_adclt_z_z_z +inst_sbclb :: inst_sbclb_z_z_z +emit_sbclb :: emit_sbclb_z_z_z +inst_sbclt :: inst_sbclt_z_z_z +emit_sbclt :: emit_sbclt_z_z_z +inst_tbl2 :: inst_tbl2_z_z_z +emit_tbl2 :: emit_tbl2_z_z_z +inst_match :: inst_match_p_p_z_z +emit_match :: emit_match_p_p_z_z +inst_nmatch :: inst_nmatch_p_p_z_z +emit_nmatch :: emit_nmatch_p_p_z_z +inst_histcnt :: inst_histcnt_z_p_z_z +emit_histcnt :: emit_histcnt_z_p_z_z +inst_histseg :: inst_histseg_z_z_z +emit_histseg :: emit_histseg_z_z_z +inst_smstart :: inst_smstart_none +emit_smstart :: emit_smstart_none +inst_smstop :: inst_smstop_none +emit_smstop :: emit_smstop_none +inst_rdsvl :: inst_rdsvl_r_i +emit_rdsvl :: emit_rdsvl_r_i +inst_addha :: inst_addha_i_p_p_z +emit_addha :: emit_addha_i_p_p_z +inst_addva :: inst_addva_i_p_p_z +emit_addva :: emit_addva_i_p_p_z +inst_zero :: inst_zero_i +emit_zero :: emit_zero_i +inst_fmopa :: inst_fmopa_i_p_p_z +emit_fmopa :: emit_fmopa_i_p_p_z +inst_fmops :: inst_fmops_i_p_p_z +emit_fmops :: emit_fmops_i_p_p_z +inst_bfmopa :: inst_bfmopa_i_p_p_z +emit_bfmopa :: emit_bfmopa_i_p_p_z +inst_bfmops :: inst_bfmops_i_p_p_z +emit_bfmops :: emit_bfmops_i_p_p_z +inst_smopa :: inst_smopa_i_p_p_z +emit_smopa :: emit_smopa_i_p_p_z +inst_smops :: inst_smops_i_p_p_z +emit_smops :: emit_smops_i_p_p_z +inst_umopa :: inst_umopa_i_p_p_z +emit_umopa :: emit_umopa_i_p_p_z +inst_umops :: inst_umops_i_p_p_z +emit_umops :: emit_umops_i_p_p_z +inst_usmopa :: inst_usmopa_i_p_p_z +emit_usmopa :: emit_usmopa_i_p_p_z +inst_sumopa :: inst_sumopa_i_p_p_z +emit_sumopa :: emit_sumopa_i_p_p_z +inst_ld1q :: inst_ld1q_i_p_m +emit_ld1q :: emit_ld1q_i_p_m +inst_st1q :: inst_st1q_i_p_m +emit_st1q :: emit_st1q_i_p_m +inst_mova :: proc{ inst_mova_z_p_i, inst_mova_i_p_z } +emit_mova :: proc{ emit_mova_z_p_i, emit_mova_i_p_z } +inst_fcmla :: inst_fcmla_r_r_r_i +emit_fcmla :: emit_fcmla_r_r_r_i +inst_fcadd :: inst_fcadd_r_r_r_i +emit_fcadd :: emit_fcadd_r_r_r_i +inst_prfb :: inst_prfb_i_p_m +emit_prfb :: emit_prfb_i_p_m +inst_prfh :: inst_prfh_i_p_m +emit_prfh :: emit_prfh_i_p_m +inst_prfw :: inst_prfw_i_p_m +emit_prfw :: emit_prfw_i_p_m +inst_prfd :: inst_prfd_i_p_m +emit_prfd :: emit_prfd_i_p_m +inst_ldnt1b :: inst_ldnt1b_z_p_m +emit_ldnt1b :: emit_ldnt1b_z_p_m +inst_ldnt1h :: inst_ldnt1h_z_p_m +emit_ldnt1h :: emit_ldnt1h_z_p_m +inst_ldnt1w :: inst_ldnt1w_z_p_m +emit_ldnt1w :: emit_ldnt1w_z_p_m +inst_ldnt1d :: inst_ldnt1d_z_p_m +emit_ldnt1d :: emit_ldnt1d_z_p_m +inst_stnt1b :: inst_stnt1b_z_p_m +emit_stnt1b :: emit_stnt1b_z_p_m +inst_stnt1h :: inst_stnt1h_z_p_m +emit_stnt1h :: emit_stnt1h_z_p_m +inst_stnt1w :: inst_stnt1w_z_p_m +emit_stnt1w :: emit_stnt1w_z_p_m +inst_stnt1d :: inst_stnt1d_z_p_m +emit_stnt1d :: emit_stnt1d_z_p_m +inst_splice :: inst_splice_z_p_z_z +emit_splice :: emit_splice_z_p_z_z +inst_index :: proc{ inst_index_z_i_i, inst_index_z_i_r, inst_index_z_r_i, inst_index_z_r_r } +emit_index :: proc{ emit_index_z_i_i, emit_index_z_i_r, emit_index_z_r_i, emit_index_z_r_r } +inst_bsl1n :: inst_bsl1n_z_z_z_z +emit_bsl1n :: emit_bsl1n_z_z_z_z +inst_bsl2n :: inst_bsl2n_z_z_z_z +emit_bsl2n :: emit_bsl2n_z_z_z_z +inst_nbsl :: inst_nbsl_z_z_z_z +emit_nbsl :: emit_nbsl_z_z_z_z +inst_pmul :: inst_pmul_z_z_z +emit_pmul :: emit_pmul_z_z_z +inst_pmullb :: inst_pmullb_z_z_z +emit_pmullb :: emit_pmullb_z_z_z +inst_pmullt :: inst_pmullt_z_z_z +emit_pmullt :: emit_pmullt_z_z_z +inst_bfcvtnt :: inst_bfcvtnt_z_p_z +emit_bfcvtnt :: emit_bfcvtnt_z_p_z +inst_ldraa :: inst_ldraa_r_m +emit_ldraa :: emit_ldraa_r_m +inst_ldrab :: inst_ldrab_r_m +emit_ldrab :: emit_ldrab_r_m +inst_tstart :: inst_tstart_r +emit_tstart :: emit_tstart_r +inst_tcommit :: inst_tcommit_none +emit_tcommit :: emit_tcommit_none +inst_tcancel :: inst_tcancel_i +emit_tcancel :: emit_tcancel_i +inst_ttest :: inst_ttest_r +emit_ttest :: emit_ttest_r +inst_wfet :: inst_wfet_r +emit_wfet :: emit_wfet_r +inst_wfit :: inst_wfit_r +emit_wfit :: emit_wfit_r +inst_bc_cond :: inst_bc_cond_c_l +emit_bc_cond :: emit_bc_cond_c_l +inst_uxtb :: inst_uxtb_r_r +emit_uxtb :: emit_uxtb_r_r +inst_uxth :: inst_uxth_r_r +emit_uxth :: emit_uxth_r_r +inst_uxtw :: inst_uxtw_r_r +emit_uxtw :: emit_uxtw_r_r +inst_sxtb :: inst_sxtb_r_r +emit_sxtb :: emit_sxtb_r_r +inst_sxth :: inst_sxth_r_r +emit_sxth :: emit_sxth_r_r +inst_sxtw :: inst_sxtw_r_r +emit_sxtw :: emit_sxtw_r_r +inst_adc :: inst_adc_r_r_r +emit_adc :: emit_adc_r_r_r +inst_adcs :: inst_adcs_r_r_r +emit_adcs :: emit_adcs_r_r_r +inst_sbc :: inst_sbc_r_r_r +emit_sbc :: emit_sbc_r_r_r +inst_sbcs :: inst_sbcs_r_r_r +emit_sbcs :: emit_sbcs_r_r_r +inst_ngc :: inst_ngc_r_r +emit_ngc :: emit_ngc_r_r +inst_ngcs :: inst_ngcs_r_r +emit_ngcs :: emit_ngcs_r_r +inst_ldapur :: inst_ldapur_r_m +emit_ldapur :: emit_ldapur_r_m +inst_stlur :: inst_stlur_r_m +emit_stlur :: emit_stlur_r_m +inst_ldapurb :: inst_ldapurb_r_m +emit_ldapurb :: emit_ldapurb_r_m +inst_stlurb :: inst_stlurb_r_m +emit_stlurb :: emit_stlurb_r_m +inst_ldapurh :: inst_ldapurh_r_m +emit_ldapurh :: emit_ldapurh_r_m +inst_stlurh :: inst_stlurh_r_m +emit_stlurh :: emit_stlurh_r_m +inst_ldapursb :: inst_ldapursb_r_m +emit_ldapursb :: emit_ldapursb_r_m +inst_ldapursh :: inst_ldapursh_r_m +emit_ldapursh :: emit_ldapursh_r_m +inst_ldapursw :: inst_ldapursw_r_m +emit_ldapursw :: emit_ldapursw_r_m +inst_bfadd :: proc{ inst_bfadd_z_p_z_z, inst_bfadd_z_z_z } +emit_bfadd :: proc{ emit_bfadd_z_p_z_z, emit_bfadd_z_z_z } +inst_bfsub :: proc{ inst_bfsub_z_p_z_z, inst_bfsub_z_z_z } +emit_bfsub :: proc{ emit_bfsub_z_p_z_z, emit_bfsub_z_z_z } +inst_bfmul :: proc{ inst_bfmul_z_p_z_z, inst_bfmul_z_z_z } +emit_bfmul :: proc{ emit_bfmul_z_p_z_z, emit_bfmul_z_z_z } +inst_bfmla :: inst_bfmla_z_p_z_z +emit_bfmla :: emit_bfmla_z_p_z_z +inst_bfmls :: inst_bfmls_z_p_z_z +emit_bfmls :: emit_bfmls_z_p_z_z +inst_sb :: inst_sb_none +emit_sb :: emit_sb_none +inst_csdb :: inst_csdb_none +emit_csdb :: emit_csdb_none +inst_dgh :: inst_dgh_none +emit_dgh :: emit_dgh_none +inst_psb_csync :: inst_psb_csync_none +emit_psb_csync :: emit_psb_csync_none +inst_tsb_csync :: inst_tsb_csync_none +emit_tsb_csync :: emit_tsb_csync_none +inst_bti_j :: inst_bti_j_none +emit_bti_j :: emit_bti_j_none +inst_bti_c :: inst_bti_c_none +emit_bti_c :: emit_bti_c_none +inst_bti_jc :: inst_bti_jc_none +emit_bti_jc :: emit_bti_jc_none +inst_bfclamp :: inst_bfclamp_z_z_z +emit_bfclamp :: emit_bfclamp_z_z_z +inst_bfmaxnm :: inst_bfmaxnm_z_p_z_z +emit_bfmaxnm :: emit_bfmaxnm_z_p_z_z +inst_bfminnm :: inst_bfminnm_z_p_z_z +emit_bfminnm :: emit_bfminnm_z_p_z_z +inst_luti2 :: inst_luti2_z_z_z_i +emit_luti2 :: emit_luti2_z_z_z_i +inst_luti4 :: inst_luti4_z_z_z_i +emit_luti4 :: emit_luti4_z_z_z_i +inst_zip :: proc{ inst_zip_z_z_z, inst_zip_z_z } +emit_zip :: proc{ emit_zip_z_z_z, emit_zip_z_z } +inst_uzp :: proc{ inst_uzp_z_z_z, inst_uzp_z_z } +emit_uzp :: proc{ emit_uzp_z_z_z, emit_uzp_z_z } +inst_tlbi_rpalos :: inst_tlbi_rpalos_r +emit_tlbi_rpalos :: emit_tlbi_rpalos_r +inst_tlbi_rpaos :: inst_tlbi_rpaos_r +emit_tlbi_rpaos :: emit_tlbi_rpaos_r +inst_at_s1e1a :: inst_at_s1e1a_r +emit_at_s1e1a :: emit_at_s1e1a_r +inst_dc_cipapa :: inst_dc_cipapa_r +emit_dc_cipapa :: emit_dc_cipapa_r +inst_dc_cigdpapa :: inst_dc_cigdpapa_r +emit_dc_cigdpapa :: emit_dc_cigdpapa_r +inst_tlbi_paall :: inst_tlbi_paall_none +emit_tlbi_paall :: emit_tlbi_paall_none +inst_tlbi_paallos :: inst_tlbi_paallos_none +emit_tlbi_paallos :: emit_tlbi_paallos_none +inst_amx_ldx :: inst_amx_ldx_r +emit_amx_ldx :: emit_amx_ldx_r +inst_amx_ldy :: inst_amx_ldy_r +emit_amx_ldy :: emit_amx_ldy_r +inst_amx_stx :: inst_amx_stx_r +emit_amx_stx :: emit_amx_stx_r +inst_amx_sty :: inst_amx_sty_r +emit_amx_sty :: emit_amx_sty_r +inst_amx_ldz :: inst_amx_ldz_r +emit_amx_ldz :: emit_amx_ldz_r +inst_amx_stz :: inst_amx_stz_r +emit_amx_stz :: emit_amx_stz_r +inst_amx_ldzi :: inst_amx_ldzi_r +emit_amx_ldzi :: emit_amx_ldzi_r +inst_amx_stzi :: inst_amx_stzi_r +emit_amx_stzi :: emit_amx_stzi_r +inst_amx_extrx :: inst_amx_extrx_r +emit_amx_extrx :: emit_amx_extrx_r +inst_amx_extry :: inst_amx_extry_r +emit_amx_extry :: emit_amx_extry_r +inst_amx_fma64 :: inst_amx_fma64_r +emit_amx_fma64 :: emit_amx_fma64_r +inst_amx_fms64 :: inst_amx_fms64_r +emit_amx_fms64 :: emit_amx_fms64_r +inst_amx_fma32 :: inst_amx_fma32_r +emit_amx_fma32 :: emit_amx_fma32_r +inst_amx_fms32 :: inst_amx_fms32_r +emit_amx_fms32 :: emit_amx_fms32_r +inst_amx_mac16 :: inst_amx_mac16_r +emit_amx_mac16 :: emit_amx_mac16_r +inst_amx_fma16 :: inst_amx_fma16_r +emit_amx_fma16 :: emit_amx_fma16_r +inst_amx_fms16 :: inst_amx_fms16_r +emit_amx_fms16 :: emit_amx_fms16_r +inst_amx_set :: inst_amx_set_none +emit_amx_set :: emit_amx_set_none +inst_amx_clr :: inst_amx_clr_none +emit_amx_clr :: emit_amx_clr_none +inst_amx_vecint :: inst_amx_vecint_r +emit_amx_vecint :: emit_amx_vecint_r +inst_amx_vecfp :: inst_amx_vecfp_r +emit_amx_vecfp :: emit_amx_vecfp_r +inst_amx_matint :: inst_amx_matint_r +emit_amx_matint :: emit_amx_matint_r +inst_amx_matfp :: inst_amx_matfp_r +emit_amx_matfp :: emit_amx_matfp_r +inst_amx_genlut :: inst_amx_genlut_r +emit_amx_genlut :: emit_amx_genlut_r +inst_cpyp :: inst_cpyp_r_r_r +emit_cpyp :: emit_cpyp_r_r_r +inst_cpym :: inst_cpym_r_r_r +emit_cpym :: emit_cpym_r_r_r +inst_cpye :: inst_cpye_r_r_r +emit_cpye :: emit_cpye_r_r_r +inst_cpyfp :: inst_cpyfp_r_r_r +emit_cpyfp :: emit_cpyfp_r_r_r +inst_cpyfm :: inst_cpyfm_r_r_r +emit_cpyfm :: emit_cpyfm_r_r_r +inst_cpyfe :: inst_cpyfe_r_r_r +emit_cpyfe :: emit_cpyfe_r_r_r +inst_setp :: inst_setp_r_r_r +emit_setp :: emit_setp_r_r_r +inst_setm :: inst_setm_r_r_r +emit_setm :: emit_setm_r_r_r +inst_sete :: inst_sete_r_r_r +emit_sete :: emit_sete_r_r_r +inst_dc_ivac :: inst_dc_ivac_r +emit_dc_ivac :: emit_dc_ivac_r +inst_dc_isw :: inst_dc_isw_r +emit_dc_isw :: emit_dc_isw_r +inst_dc_csw :: inst_dc_csw_r +emit_dc_csw :: emit_dc_csw_r +inst_dc_cisw :: inst_dc_cisw_r +emit_dc_cisw :: emit_dc_cisw_r +inst_dc_zva :: inst_dc_zva_r +emit_dc_zva :: emit_dc_zva_r +inst_dc_cvac :: inst_dc_cvac_r +emit_dc_cvac :: emit_dc_cvac_r +inst_dc_cvau :: inst_dc_cvau_r +emit_dc_cvau :: emit_dc_cvau_r +inst_dc_civac :: inst_dc_civac_r +emit_dc_civac :: emit_dc_civac_r +inst_ic_ialluis :: inst_ic_ialluis_none +emit_ic_ialluis :: emit_ic_ialluis_none +inst_ic_iallu :: inst_ic_iallu_none +emit_ic_iallu :: emit_ic_iallu_none +inst_ic_ivau :: inst_ic_ivau_r +emit_ic_ivau :: emit_ic_ivau_r +inst_at_s1e1r :: inst_at_s1e1r_r +emit_at_s1e1r :: emit_at_s1e1r_r +inst_at_s1e1w :: inst_at_s1e1w_r +emit_at_s1e1w :: emit_at_s1e1w_r +inst_at_s1e0r :: inst_at_s1e0r_r +emit_at_s1e0r :: emit_at_s1e0r_r +inst_at_s1e0w :: inst_at_s1e0w_r +emit_at_s1e0w :: emit_at_s1e0w_r +inst_at_s1e2r :: inst_at_s1e2r_r +emit_at_s1e2r :: emit_at_s1e2r_r +inst_at_s1e2w :: inst_at_s1e2w_r +emit_at_s1e2w :: emit_at_s1e2w_r +inst_at_s1e3r :: inst_at_s1e3r_r +emit_at_s1e3r :: emit_at_s1e3r_r +inst_at_s1e3w :: inst_at_s1e3w_r +emit_at_s1e3w :: emit_at_s1e3w_r +inst_at_s12e1r :: inst_at_s12e1r_r +emit_at_s12e1r :: emit_at_s12e1r_r +inst_at_s12e1w :: inst_at_s12e1w_r +emit_at_s12e1w :: emit_at_s12e1w_r +inst_at_s12e0r :: inst_at_s12e0r_r +emit_at_s12e0r :: emit_at_s12e0r_r +inst_at_s12e0w :: inst_at_s12e0w_r +emit_at_s12e0w :: emit_at_s12e0w_r +inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none +emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none +inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none +emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none +inst_tlbi_vae1 :: inst_tlbi_vae1_r +emit_tlbi_vae1 :: emit_tlbi_vae1_r +inst_tlbi_vae1is :: inst_tlbi_vae1is_r +emit_tlbi_vae1is :: emit_tlbi_vae1is_r +inst_tlbi_aside1 :: inst_tlbi_aside1_r +emit_tlbi_aside1 :: emit_tlbi_aside1_r +inst_tlbi_aside1is :: inst_tlbi_aside1is_r +emit_tlbi_aside1is :: emit_tlbi_aside1is_r +inst_tlbi_vaae1 :: inst_tlbi_vaae1_r +emit_tlbi_vaae1 :: emit_tlbi_vaae1_r +inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r +emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r +inst_tlbi_vale1 :: inst_tlbi_vale1_r +emit_tlbi_vale1 :: emit_tlbi_vale1_r +inst_tlbi_vale1is :: inst_tlbi_vale1is_r +emit_tlbi_vale1is :: emit_tlbi_vale1is_r +inst_tlbi_vaale1 :: inst_tlbi_vaale1_r +emit_tlbi_vaale1 :: emit_tlbi_vaale1_r +inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r +emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r +inst_tlbi_alle1 :: inst_tlbi_alle1_none +emit_tlbi_alle1 :: emit_tlbi_alle1_none +inst_tlbi_alle1is :: inst_tlbi_alle1is_none +emit_tlbi_alle1is :: emit_tlbi_alle1is_none +inst_tlbi_alle2 :: inst_tlbi_alle2_none +emit_tlbi_alle2 :: emit_tlbi_alle2_none +inst_tlbi_alle2is :: inst_tlbi_alle2is_none +emit_tlbi_alle2is :: emit_tlbi_alle2is_none +inst_tlbi_alle3 :: inst_tlbi_alle3_none +emit_tlbi_alle3 :: emit_tlbi_alle3_none +inst_tlbi_alle3is :: inst_tlbi_alle3is_none +emit_tlbi_alle3is :: emit_tlbi_alle3is_none +inst_prfm :: proc{ inst_prfm_i_m, inst_prfm_i_l } +emit_prfm :: proc{ emit_prfm_i_m, emit_prfm_i_l } +inst_prfum :: inst_prfum_i_m +emit_prfum :: emit_prfum_i_m +inst_negs :: inst_negs_r_sh +emit_negs :: emit_negs_r_sh +inst_cmp :: proc{ inst_cmp_r_sh, inst_cmp_r_ex, inst_cmp_r_i } +emit_cmp :: proc{ emit_cmp_r_sh, emit_cmp_r_ex, emit_cmp_r_i } +inst_cmn :: proc{ inst_cmn_r_sh, inst_cmn_r_ex, inst_cmn_r_i } +emit_cmn :: proc{ emit_cmn_r_sh, emit_cmn_r_ex, emit_cmn_r_i } diff --git a/core/rexcode/isa/arm64/mnemonics.odin b/core/rexcode/isa/arm64/mnemonics.odin index 6eb516613..fa648c572 100644 --- a/core/rexcode/isa/arm64/mnemonics.odin +++ b/core/rexcode/isa/arm64/mnemonics.odin @@ -3,18 +3,25 @@ package rexcode_arm64 // ============================================================================= -// AArch64 MNEMONICS (v1 -- base integer + FP scalar) +// AArch64 MNEMONICS // ============================================================================= // -// This is the v1 cut focused on the base integer ISA + scalar FP. Each -// extension (NEON, LSE atomics, crypto, FP16/BF16, SVE, SVE2, SME, PAC, -// BTI, MTE, ...) lands in a follow-up turn. +// One member per ASSEMBLER mnemonic -- the name an A64 assembler actually +// accepts, and nothing finer. An instruction's variants are not separate +// mnemonics: ADD covers the immediate, shifted-register, extended-register +// and NEON forms, LDR covers every addressing mode, and the encoder picks +// between them by matching the operands against that mnemonic's run of +// forms in INSTRUCTION_TABLE (see tablegen/instruction_table.odin). // -// Some "instructions" that share an opcode with another are real -// aliases at the architectural level (e.g. MOV/MVN are aliases of -// ORR/ORN, NEG of SUB, CMP of SUBS, etc.). For v1 the explicit -// non-alias mnemonic is exposed; aliases can be added later as -// printer hints + encoder builders that lower to the real form. +// The only names holding an underscore are the system instructions an +// assembler writes as two tokens -- `dc zva`, `tlbi vae1`, `at s1e1r`, +// `bti j`, `psb csync` -- plus B_COND / BC_COND, whose condition lives in +// an operand and prints as `b.eq` / `bc.eq`, and the AMX_* pseudo-ops for +// Apple's undocumented coprocessor, which has no assembler spelling. +// +// Architectural aliases that share an encoding (MOV/MVN of ORR/ORN, NEG of +// SUB, CMP of SUBS, TST of ANDS, ...) are listed as the mnemonics they are: +// each is a name assemblers accept, so each gets its own member and forms. Mnemonic :: enum u16 { INVALID = 0, @@ -23,38 +30,31 @@ Mnemonic :: enum u16 { // Data processing -- immediate // ------------------------------------------------------------------------- - ADD_IMM, ADDS_IMM, SUB_IMM, SUBS_IMM, // optional LSL #12 carried in shift field - MOVZ, MOVN, MOVK, // 16-bit imm + 2-bit hw - ADR, ADRP, // PC-relative address + ADD, ADDS, SUB, SUBS, // optional LSL #12 carried in shift field + MOVZ, MOVN, MOVK, // 16-bit imm + 2-bit hw + ADR, ADRP, // PC-relative address // ------------------------------------------------------------------------- // Data processing -- register (shifted register) // ------------------------------------------------------------------------- - ADD_SR, ADDS_SR, SUB_SR, SUBS_SR, - AND_SR, ANDS_SR, ORR_SR, EOR_SR, - BIC_SR, BICS_SR, ORN_SR, EON_SR, - - // ------------------------------------------------------------------------- - // Data processing -- register (extended register) - // ------------------------------------------------------------------------- - - ADD_ER, ADDS_ER, SUB_ER, SUBS_ER, + AND, ANDS, ORR, EOR, + BIC, BICS, ORN, EON, // ------------------------------------------------------------------------- // Data processing -- register (variable shifts / 2-source) // ------------------------------------------------------------------------- - LSLV, LSRV, ASRV, RORV, // also printed as LSL/LSR/ASR/ROR + LSL, LSR, ASR, ROR, // register and immediate forms both UDIV, SDIV, // ------------------------------------------------------------------------- // Data processing -- register (3-source) // ------------------------------------------------------------------------- - MADD, MSUB, // 64x64+64 -> 64 (or 32 variant) - SMADDL, SMSUBL, UMADDL, UMSUBL, // 32x32+64 -> 64 - SMULH, UMULH, // 64x64 -> high 64 + MADD, MSUB, // 64x64+64 -> 64 (or 32 variant) + SMADDL, SMSUBL, UMADDL, UMSUBL, // 32x32+64 -> 64 + SMULH, UMULH, // 64x64 -> high 64 // ------------------------------------------------------------------------- // Data processing -- register (1-source bit-twiddling) @@ -67,7 +67,7 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- CSEL, CSINC, CSINV, CSNEG, - CCMP_REG, CCMP_IMM, CCMN_REG, CCMN_IMM, + CCMP, CCMN, // ------------------------------------------------------------------------- // Extract @@ -79,18 +79,18 @@ Mnemonic :: enum u16 { // Branches // ------------------------------------------------------------------------- - B, BL, // 26-bit PC-rel - BR, BLR, RET, // register indirect - B_COND, // B.cond -- 19-bit PC-rel - CBZ, CBNZ, // 19-bit PC-rel + Rt - TBZ, TBNZ, // 14-bit PC-rel + bit position + B, BL, // 26-bit PC-rel + BR, BLR, RET, // register indirect + B_COND, // B.cond -- 19-bit PC-rel + CBZ, CBNZ, // 19-bit PC-rel + Rt + TBZ, TBNZ, // 14-bit PC-rel + bit position // ------------------------------------------------------------------------- // Loads / stores // ------------------------------------------------------------------------- // Plain (unsigned offset / signed unscaled / pre / post) - LDR, STR, // X/W variants (matched by reg width) + LDR, STR, // X/W variants (matched by reg width) LDRB, STRB, LDRSB, LDRH, STRH, LDRSH, LDRSW, @@ -99,7 +99,6 @@ Mnemonic :: enum u16 { LDP, STP, LDPSW, // PC-relative literal - LDR_LIT, // Acquire / release LDAR, STLR, @@ -114,7 +113,7 @@ Mnemonic :: enum u16 { NOP, YIELD, WFE, WFI, SEV, SEVL, HINT, - MRS, MSR_IMM, MSR_REG, + MRS, MSR, ISB, DSB, DMB, SVC, HVC, SMC, BRK, HLT, ERET, @@ -123,14 +122,14 @@ Mnemonic :: enum u16 { // FP scalar (single / double) // ------------------------------------------------------------------------- - FMOV_REG, FMOV_IMM, FMOV_GEN, // reg-reg / imm / between int/FP + FMOV, // reg-reg / imm / between int/FP FABS, FNEG, FSQRT, FADD, FSUB, FMUL, FDIV, FNMUL, FMADD, FMSUB, FNMADD, FNMSUB, FCMP, FCMPE, FCSEL, FMAX, FMIN, FMAXNM, FMINNM, - FCVT, // between single/double/half + FCVT, // between single/double/half SCVTF, UCVTF, FCVTZS, FCVTZU, FCVTAS, FCVTAU, @@ -142,20 +141,12 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // Logical immediate (bitmask-encoded; N:imms:immr) // ------------------------------------------------------------------------- - AND_IMM, ANDS_IMM, ORR_IMM, EOR_IMM, - TST_IMM, // alias of ANDS_IMM with Rd=ZR; printed separately + TST, // ANDS with Rd=ZR // ------------------------------------------------------------------------- // Additional load/store addressing modes // ------------------------------------------------------------------------- LDUR, STUR, LDURB, STURB, LDURSB, LDURH, STURH, LDURSH, LDURSW, - LDR_PRE, STR_PRE, LDR_POST, STR_POST, - LDRB_PRE, STRB_PRE, LDRB_POST, STRB_POST, - LDRH_PRE, STRH_PRE, LDRH_POST, STRH_POST, - LDR_REG, STR_REG, LDRB_REG, STRB_REG, LDRH_REG, STRH_REG, - LDRSB_REG, LDRSH_REG, LDRSW_REG, - LDP_PRE, STP_PRE, LDP_POST, STP_POST, - LDPSW_PRE, LDPSW_POST, LDNP, STNP, // non-temporal pair LDXP, STXP, LDAXP, STLXP, // exclusive pair LDXRB, STXRB, LDAXRB, STLXRB, // exclusive byte @@ -226,19 +217,6 @@ Mnemonic :: enum u16 { SM4E, SM4EKEY, PMULL, PMULL2, - // ------------------------------------------------------------------------- - // FP scalar half-precision (FP16) - // ------------------------------------------------------------------------- - FABS_H, FNEG_H, FSQRT_H, - FADD_H, FSUB_H, FMUL_H, FDIV_H, FNMUL_H, - FMADD_H, FMSUB_H, FNMADD_H, FNMSUB_H, - FCMP_H, FCMPE_H, FCSEL_H, - FMAX_H, FMIN_H, FMAXNM_H, FMINNM_H, - FCVT_H_S, FCVT_H_D, FCVT_S_H, FCVT_D_H, // half<->single/double cross - FMOV_H, - SCVTF_H, UCVTF_H, - FCVTZS_H, FCVTZU_H, - // ------------------------------------------------------------------------- // BFloat16 (BF16; v8.6-A) // ------------------------------------------------------------------------- @@ -248,18 +226,18 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // NEON Advanced SIMD // ------------------------------------------------------------------------- - // The mnemonics here cover vector forms. Where a name collides with a - // scalar mnemonic above (ADD/SUB/MUL/AND/ORR/EOR/MVN/...) we suffix - // with _V; the printer strips the suffix so the disassembly reads the - // canonical mnemonic (`add v0.16b, ...`). + // Vector forms. A name that also has a scalar form above (ADD/SUB/MUL/ + // AND/ORR/EOR/MVN/...) is the SAME mnemonic -- the vector forms simply + // join that mnemonic's run, selected by the V-register operand types. + // Only names with no scalar counterpart appear below. // 3-same arithmetic - ADD_V, SUB_V, MUL_V, MLA_V, MLS_V, NEG_V, ABS_V, + MUL, MLA, MLS, NEG, ABS, SHADD, UHADD, SHSUB, UHSUB, SRHADD, URHADD, SQADD, UQADD, SQSUB, UQSUB, SMAX, UMAX, SMIN, UMIN, SABD, UABD, SABA, UABA, - ADDP_V, ADDV, + ADDP, ADDV, SADDLP, UADDLP, SADALP, UADALP, SADDLV, UADDLV, SMAXV, UMAXV, SMINV, UMINV, SMAXP, UMAXP, SMINP, UMINP, @@ -274,7 +252,7 @@ Mnemonic :: enum u16 { XTN, XTN2, SQXTN, SQXTN2, UQXTN, UQXTN2, SQXTUN, SQXTUN2, // multiply long / multiply-accumulate long - SMULL_V, SMULL2_V, UMULL_V, UMULL2_V, + SMULL, SMULL2, UMULL, UMULL2, SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2, SQDMULL, SQDMULL2, SQDMLAL, SQDMLAL2, SQDMLSL, SQDMLSL2, @@ -284,18 +262,11 @@ Mnemonic :: enum u16 { SDOT, UDOT, USDOT, // FP vector - FADD_V, FSUB_V, FMUL_V, FDIV_V, FNEG_V, FABS_V, FSQRT_V, - FMLA_V, FMLS_V, FMULX, - FMAX_V, FMIN_V, FMAXNM_V, FMINNM_V, - FMAXP_V, FMINP_V, FMAXNMP, FMINNMP, - FMAXV_V, FMINV_V, FMAXNMV, FMINNMV, + FMLA, FMLS, FMULX, + FMAXP, FMINP, FMAXNMP, FMINNMP, + FMAXV, FMINV, FMAXNMV, FMINNMV, FRECPE, FRSQRTE, FRECPS, FRSQRTS, FRECPX, - FADDP_V, - FRINTA_V, FRINTI_V, FRINTM_V, FRINTN_V, FRINTP_V, FRINTX_V, FRINTZ_V, - SCVTF_V, UCVTF_V, - FCVTAS_V, FCVTAU_V, FCVTMS_V, FCVTMU_V, - FCVTNS_V, FCVTNU_V, FCVTPS_V, FCVTPU_V, - FCVTZS_V, FCVTZU_V, + FADDP, FCVTL, FCVTL2, FCVTN, FCVTN2, FCVTXN, FCVTXN2, // FP compare (vector) @@ -306,11 +277,11 @@ Mnemonic :: enum u16 { CMEQ, CMGE, CMGT, CMHI, CMHS, CMLE, CMLT, CMTST, // Logical (vector) - AND_V, ORR_V, EOR_V, BIC_V, ORN_V, MVN_V, + MVN, BIT, BIF, BSL, // Shifts - SHL_V, SQSHL_V, SQSHLU, SRSHL, URSHL, + SHL, SQSHL, SQSHLU, SRSHL, URSHL, SSHR, USHR, SSRA, USRA, SRSHR, URSHR, SRSRA, URSRA, SSHL, USHL, SLI, SRI, @@ -322,178 +293,132 @@ Mnemonic :: enum u16 { SQSHRUN, SQSHRUN2, SQRSHRUN, SQRSHRUN2, // Misc / permute / bit - DUP_V, INS, MOV_V, - EXT_V, + DUP, INS, MOV, + EXT, TBL, TBX, ZIP1, ZIP2, UZP1, UZP2, TRN1, TRN2, - NOT_V, RBIT_V, REV16_V, REV32_V, REV64, - CLS_V, CLZ_V, CNT, - URECPE_V, URSQRTE_V, + NOT, REV64, + CNT, + URECPE, URSQRTE, // Vector immediate - MOVI, MVNI, FMOV_V_IMM, + MOVI, MVNI, // NEON load/store LD1, LD2, LD3, LD4, // multiple structures ST1, ST2, ST3, ST4, LD1R, LD2R, LD3R, LD4R, // load-and-replicate to all lanes - LD1_LANE, LD2_LANE, LD3_LANE, LD4_LANE, // load single structure to lane - ST1_LANE, ST2_LANE, ST3_LANE, ST4_LANE, // FP/SIMD load/store using V/D/S/H/B/Q registers - LDR_V, STR_V, // imm/literal/pre/post/reg - LDP_V, STP_V, - LDUR_V, STUR_V, // ------------------------------------------------------------------------- // SVE / SVE2 base // ------------------------------------------------------------------------- // - // SVE mnemonics carry a Z/P-relevant suffix on conflicts with base - // integer / NEON names. `_Z` (Z-register), `_PRED` (predicated form - // where there's a separate unpredicated form), `_P` (predicate-only). + // SVE reuses the base integer / NEON mnemonics: `add z0.s, z1.s, z2.s` + // and `add z0.s, p0/m, z0.s, z1.s` are both ADD, and land in ADD's run + // as forms taking Z / predicate operands. Only SVE-only names are listed. // Integer arithmetic (vectors, unpredicated) - SVE_ADD_Z, SVE_SUB_Z, SVE_SQADD_Z, SVE_UQADD_Z, SVE_SQSUB_Z, SVE_UQSUB_Z, // Integer arithmetic (predicated, destructive merging) - SVE_ADD_PRED, SVE_SUB_PRED, SVE_SUBR_PRED, - SVE_MUL_PRED, SVE_SMULH_PRED, SVE_UMULH_PRED, - SVE_SDIV_PRED, SVE_UDIV_PRED, - SVE_SMAX_PRED, SVE_UMAX_PRED, SVE_SMIN_PRED, SVE_UMIN_PRED, - SVE_SABD_PRED, SVE_UABD_PRED, - SVE_AND_PRED, SVE_ORR_PRED, SVE_EOR_PRED, SVE_BIC_PRED, - SVE_ASR_PRED, SVE_LSL_PRED, SVE_LSR_PRED, SVE_ASRR_PRED, SVE_LSLR_PRED, SVE_LSRR_PRED, - SVE_ABS_PRED, SVE_NEG_PRED, - SVE_CLS_PRED, SVE_CLZ_PRED, SVE_CNT_PRED, - SVE_MOV_PRED, + SUBR, + ASRR, LSLR, LSRR, // FP arithmetic (unpredicated) - SVE_FADD_Z, SVE_FSUB_Z, SVE_FMUL_Z, - SVE_FRECPS, SVE_FRSQRTS, SVE_FTSMUL, + FTSMUL, // FP arithmetic (predicated, destructive merging) - SVE_FADD_PRED, SVE_FSUB_PRED, SVE_FSUBR_PRED, - SVE_FMUL_PRED, SVE_FDIV_PRED, SVE_FDIVR_PRED, - SVE_FMAX_PRED, SVE_FMIN_PRED, SVE_FMAXNM_PRED, SVE_FMINNM_PRED, - SVE_FABS_Z, SVE_FNEG_Z, SVE_FSQRT_Z, SVE_FRECPX_Z, - SVE_FRINTN, SVE_FRINTP, SVE_FRINTM, SVE_FRINTZ, SVE_FRINTA, SVE_FRINTX, SVE_FRINTI, - SVE_FMLA, SVE_FMLS, SVE_FNMLA, SVE_FNMLS, + FSUBR, + FDIVR, + FNMLA, FNMLS, // Predicate logical / move - SVE_AND_P, SVE_BIC_P, SVE_ORR_P, SVE_EOR_P, - SVE_NAND_P, SVE_NOR_P, SVE_ORN_P, SVE_SEL_P, - SVE_ANDS_P, SVE_BICS_P, SVE_ORRS_P, SVE_EORS_P, - SVE_NANDS_P, SVE_NORS_P, SVE_ORNS_P, - SVE_NOT_P, SVE_MOV_P, SVE_MOVS_P, - SVE_PTRUE, SVE_PTRUES, SVE_PFALSE, SVE_PFIRST, SVE_PNEXT, - SVE_BRKA, SVE_BRKB, SVE_BRKAS, SVE_BRKBS, - SVE_BRKPA, SVE_BRKPB, SVE_BRKN, - SVE_RDFFR, SVE_WRFFR, SVE_SETFFR, + NAND, NOR, SEL, + ORRS, EORS, + NANDS, NORS, ORNS, + MOVS, + PTRUE, PTRUES, PFALSE, PFIRST, PNEXT, + BRKA, BRKB, BRKAS, BRKBS, + BRKPA, BRKPB, BRKN, + RDFFR, WRFFR, SETFFR, // Integer compare and set predicate - SVE_CMPEQ, SVE_CMPNE, SVE_CMPGE, SVE_CMPGT, SVE_CMPLE, SVE_CMPLT, - SVE_CMPHI, SVE_CMPHS, SVE_CMPLO, SVE_CMPLS, + CMPEQ, CMPNE, CMPGE, CMPGT, CMPLE, CMPLT, + CMPHI, CMPHS, CMPLO, CMPLS, // FP compare and set predicate - SVE_FCMEQ, SVE_FCMNE, SVE_FCMGE, SVE_FCMGT, SVE_FCMLE, SVE_FCMLT, SVE_FCMUO, + FCMNE, FCMUO, // Permute / move / replicate - SVE_DUP_Z, SVE_INSR, SVE_REV_Z, SVE_REV_P, SVE_TBL, - SVE_ZIP1_Z, SVE_ZIP2_Z, SVE_UZP1_Z, SVE_UZP2_Z, SVE_TRN1_Z, SVE_TRN2_Z, - SVE_ZIP1_P, SVE_ZIP2_P, SVE_UZP1_P, SVE_UZP2_P, SVE_TRN1_P, SVE_TRN2_P, - SVE_CPY_Z, SVE_COMPACT, SVE_EXT_Z, + INSR, + CPY, COMPACT, // Loads / stores (contiguous) - SVE_LD1B, SVE_LD1H, SVE_LD1W, SVE_LD1D, - SVE_LD1SB, SVE_LD1SH, SVE_LD1SW, - SVE_ST1B, SVE_ST1H, SVE_ST1W, SVE_ST1D, - SVE_LDR_Z, SVE_STR_Z, SVE_LDR_P, SVE_STR_P, - SVE_LDFF1B, SVE_LDFF1H, SVE_LDFF1W, SVE_LDFF1D, // first-faulting + LD1B, LD1H, LD1W, LD1D, + LD1SB, LD1SH, LD1SW, + ST1B, ST1H, ST1W, ST1D, + LDFF1B, LDFF1H, LDFF1W, LDFF1D, // first-faulting // SVE2 additions - SVE_WHILEGE, SVE_WHILEGT, SVE_WHILELE, SVE_WHILELT, - SVE_WHILEHI, SVE_WHILEHS, SVE_WHILELO, SVE_WHILELS, - SVE_SQRDMLAH, SVE_SQRDMLSH, - SVE_ADCLB, SVE_ADCLT, SVE_SBCLB, SVE_SBCLT, - SVE_TBL2, SVE_TBX, - SVE_AESE, SVE_AESD, SVE_AESMC, SVE_AESIMC, // SVE2 crypto - SVE_BCAX_Z, SVE_XAR_Z, SVE_EOR3_Z, - SVE_MATCH, SVE_NMATCH, - SVE_HISTCNT, SVE_HISTSEG, + WHILEGE, WHILEGT, WHILELE, WHILELT, + WHILEHI, WHILEHS, WHILELO, WHILELS, + SQRDMLAH, SQRDMLSH, + ADCLB, ADCLT, SBCLB, SBCLT, + TBL2, + MATCH, NMATCH, + HISTCNT, HISTSEG, // ------------------------------------------------------------------------- // SME (Scalable Matrix Extension) // ------------------------------------------------------------------------- - SME_SMSTART, SME_SMSTOP, - SME_RDSVL, SME_ADDHA, SME_ADDVA, - SME_ZERO, - SME_FMOPA, SME_FMOPS, - SME_BFMOPA, SME_BFMOPS, - SME_SMOPA, SME_SMOPS, SME_UMOPA, SME_UMOPS, - SME_USMOPA, SME_SUMOPA, - SME_LDR_ZA, SME_STR_ZA, - - // ------------------------------------------------------------------------- - // SVE indexed FMLA / FMLS (lane-broadcast multiply-accumulate) - // ------------------------------------------------------------------------- - SVE_FMLA_IDX_H, SVE_FMLA_IDX_S, SVE_FMLA_IDX_D, - SVE_FMLS_IDX_H, SVE_FMLS_IDX_S, SVE_FMLS_IDX_D, - - // ------------------------------------------------------------------------- - // SVE gather/scatter (the practical 32-bit and 64-bit offset forms) - // ------------------------------------------------------------------------- - SVE_LD1B_GATHER_S, SVE_LD1B_GATHER_D, - SVE_LD1H_GATHER_S, SVE_LD1H_GATHER_D, - SVE_LD1W_GATHER_S, SVE_LD1W_GATHER_D, - SVE_LD1D_GATHER_D, - SVE_LD1SB_GATHER_S, SVE_LD1SB_GATHER_D, - SVE_LD1SH_GATHER_S, SVE_LD1SH_GATHER_D, - SVE_LD1SW_GATHER_D, - SVE_ST1B_SCATTER_S, SVE_ST1B_SCATTER_D, - SVE_ST1H_SCATTER_S, SVE_ST1H_SCATTER_D, - SVE_ST1W_SCATTER_S, SVE_ST1W_SCATTER_D, - SVE_ST1D_SCATTER_D, + SMSTART, SMSTOP, + RDSVL, ADDHA, ADDVA, + ZERO, + FMOPA, FMOPS, + BFMOPA, BFMOPS, + SMOPA, SMOPS, UMOPA, UMOPS, + USMOPA, SUMOPA, // ------------------------------------------------------------------------- // SME tile slice load/store (LD1B/H/W/D/Q to ZA tile slice; ST1 reverse) // ------------------------------------------------------------------------- - SME_LD1B_TILE, SME_LD1H_TILE, SME_LD1W_TILE, SME_LD1D_TILE, SME_LD1Q_TILE, - SME_ST1B_TILE, SME_ST1H_TILE, SME_ST1W_TILE, SME_ST1D_TILE, SME_ST1Q_TILE, + LD1Q, + ST1Q, // MOVA between Z register and tile slice (both directions) - SME_MOVA_Z_FROM_TILE, SME_MOVA_TILE_FROM_Z, + MOVA, // ------------------------------------------------------------------------- // NEON complex FP multiply-add (v8.3-A FCMA extension) // ------------------------------------------------------------------------- - FCMLA_4H, FCMLA_8H, FCMLA_4S, FCMLA_2D, - FCADD_4H, FCADD_8H, FCADD_4S, FCADD_2D, + FCMLA, + FCADD, // ------------------------------------------------------------------------- // SVE prefetch, non-temporal load/store, EXT/SPLICE/INDEX // ------------------------------------------------------------------------- - SVE_PRFB, SVE_PRFH, SVE_PRFW, SVE_PRFD, - SVE_LDNT1B, SVE_LDNT1H, SVE_LDNT1W, SVE_LDNT1D, - SVE_STNT1B, SVE_STNT1H, SVE_STNT1W, SVE_STNT1D, - SVE_EXT, SVE_SPLICE, - SVE_INDEX_II, SVE_INDEX_IR, SVE_INDEX_RI, SVE_INDEX_RR, + PRFB, PRFH, PRFW, PRFD, + LDNT1B, LDNT1H, LDNT1W, LDNT1D, + STNT1B, STNT1H, STNT1W, STNT1D, + SPLICE, + INDEX, // ------------------------------------------------------------------------- // SVE2 bitwise select family + polynomial multiply // ------------------------------------------------------------------------- - SVE_BSL, SVE_BSL1N, SVE_BSL2N, SVE_NBSL, - SVE_PMUL_VEC, SVE_PMULLB, SVE_PMULLT, + BSL1N, BSL2N, NBSL, + PMUL, PMULLB, PMULLT, // ------------------------------------------------------------------------- // SVE BF16 conversions (BFCVT in SVE form) // ------------------------------------------------------------------------- - SVE_BFCVT, SVE_BFCVTNT, + BFCVTNT, // ------------------------------------------------------------------------- // PAC-authenticated loads (v8.3-A) // ------------------------------------------------------------------------- - LDRAA, LDRAB, LDRAA_PRE, LDRAB_PRE, + LDRAA, LDRAB, // ------------------------------------------------------------------------- // Transactional Memory Extension (TME, v9.0-A) @@ -513,85 +438,57 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // Sign/zero extend aliases (canonical names for SBFM/UBFM specific cases) // ------------------------------------------------------------------------- - UXTB, UXTH, UXTW, // unsigned extends (UBFM aliases) - SXTB, SXTH, SXTW, // signed extends (SBFM aliases) + UXTB, UXTH, UXTW, // unsigned extends (UBFM aliases) + SXTB, SXTH, SXTW, // signed extends (SBFM aliases) // ------------------------------------------------------------------------- // Carry arithmetic (add/sub with carry) // ------------------------------------------------------------------------- ADC, ADCS, SBC, SBCS, - NGC, NGCS, // NGC Rd, Rm = SBC Rd, ZR, Rm; NGCS similar + NGC, NGCS, // NGC Rd, Rm = SBC Rd, ZR, Rm; NGCS similar // ------------------------------------------------------------------------- // RCpc / LDAPUR / STLUR (v8.4-A unscaled release-consistency loads/stores) // ------------------------------------------------------------------------- - LDAPUR, STLUR, // 32/64-bit word - LDAPURB, STLURB, LDAPURH, STLURH, // byte / half - LDAPURSB, LDAPURSH, LDAPURSW, // signed extending + LDAPUR, STLUR, // 32/64-bit word + LDAPURB, STLURB, LDAPURH, STLURH, // byte / half + LDAPURSB, LDAPURSH, LDAPURSW, // signed extending // ------------------------------------------------------------------------- // SVE BF16 predicated arithmetic (3-same) // ------------------------------------------------------------------------- - SVE_BFADD, SVE_BFSUB, SVE_BFMUL, - SVE_BFMLA, SVE_BFMLS, + BFADD, BFSUB, BFMUL, + BFMLA, BFMLS, // ------------------------------------------------------------------------- // Speculation / profiling barriers + speculation hints // ------------------------------------------------------------------------- - SB, // Speculation Barrier (v8.0) - CSDB, // Consumption of Speculative Data Barrier - DGH, // Data Gathering Hint (v8.5-A) - PSB_CSYNC, // Profile Synchronization Barrier - TSB_CSYNC, // Trace Synchronization Barrier - BTI_J, BTI_C, BTI_JC,// explicit BTI variants - - // ------------------------------------------------------------------------- - // Random number access (v8.5-A) -- read RNDR / RNDRRS via MRS - // ------------------------------------------------------------------------- - // (sysreg constants are in sysregs.odin; the MRS mnemonic handles it) - - // ------------------------------------------------------------------------- - // More NEON aliases - // ------------------------------------------------------------------------- - MOV_V_ALIAS, // MOV Vd., Vn. = ORR Vd, Vn, Vn (vector copy) - NOT_V_ALIAS, // NOT Vd., Vn. = MVN with Rm=Rn - - // ------------------------------------------------------------------------- - // Shift-by-immediate aliases (UBFM/SBFM specific cases) - // ------------------------------------------------------------------------- - LSL_IMM, // LSL Rd, Rn, #imm = UBFM Rd, Rn, #(-imm % regsize), #(regsize-1-imm) - LSR_IMM, // LSR Rd, Rn, #imm = UBFM Rd, Rn, #imm, #(regsize-1) - ASR_IMM, // ASR Rd, Rn, #imm = SBFM Rd, Rn, #imm, #(regsize-1) - ROR_IMM, // ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm + SB, // Speculation Barrier (v8.0) + CSDB, // Consumption of Speculative Data Barrier + DGH, // Data Gathering Hint (v8.5-A) + PSB_CSYNC, // Profile Synchronization Barrier + TSB_CSYNC, // Trace Synchronization Barrier + BTI_J, BTI_C, BTI_JC, // explicit BTI variants // ------------------------------------------------------------------------- // SVE2.1 / SME2 -- BF16 unpredicated + clamp/min/max + multi-vector // ------------------------------------------------------------------------- - SVE_BFADD_UNPRED, SVE_BFSUB_UNPRED, SVE_BFMUL_UNPRED, - SVE_BFCLAMP, // BFCLAMP Zd.H, Zn.H, Zm.H - SVE_BFMAXNM, SVE_BFMINNM, // BF16 min/max-num predicated + BFCLAMP, // BFCLAMP Zd.H, Zn.H, Zm.H + BFMAXNM, BFMINNM, // BF16 min/max-num predicated // SME2 multi-vector: contiguous LD/ST and select-table lookup - SME2_LUTI2_B, SME2_LUTI4_B, // LUTI2/4 table lookup (byte) - SME2_LD1B_X2, SME2_LD1H_X2, // 2-vector contiguous loads - SME2_LD1W_X2, SME2_LD1D_X2, - SME2_LD1B_X4, SME2_LD1H_X4, // 4-vector contiguous loads - SME2_LD1W_X4, SME2_LD1D_X4, - SME2_ST1B_X2, SME2_ST1H_X2, - SME2_ST1W_X2, SME2_ST1D_X2, - SME2_ST1B_X4, SME2_ST1H_X4, - SME2_ST1W_X4, SME2_ST1D_X4, + LUTI2, LUTI4, // LUTI2/4 table lookup (byte) // SME2 ZIP / UZP multi-way (3-vector and 4-vector forms) - SME2_ZIP_3, SME2_ZIP_4, - SME2_UZP_3, SME2_UZP_4, + ZIP, + UZP, // ------------------------------------------------------------------------- // RME (Realm Management Extension, ARMv9-A) // ------------------------------------------------------------------------- - TLBI_RPALOS, TLBI_RPAOS, // Realm physical address space - AT_S1E1A, // stage-1 translate with implicit authority - DC_CIPAPA, DC_CIGDPAPA, // physical-address cache mgmt + TLBI_RPALOS, TLBI_RPAOS, // Realm physical address space + AT_S1E1A, // stage-1 translate with implicit authority + DC_CIPAPA, DC_CIGDPAPA, // physical-address cache mgmt TLBI_PAALL, TLBI_PAALLOS, // ------------------------------------------------------------------------- @@ -677,22 +574,13 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // Prefetch // ------------------------------------------------------------------------- - PRFM, PRFUM, PRFM_LIT, + PRFM, PRFUM, // ------------------------------------------------------------------------- // Aliases (printed canonically; encode the underlying operation with // Rd=ZR or Rn=ZR fixed). // ------------------------------------------------------------------------- - MOV_REG, // MOV Rd, Rm = ORR Rd, ZR, Rm (shifted-register form) - MOV_BITMASK, // MOV Rd, #imm = ORR Rd, ZR, #bitmask_imm - MVN, // MVN Rd, Rm = ORN Rd, ZR, Rm - NEG_SR, // NEG Rd, Rm{,shift} = SUB Rd, ZR, Rm{,shift} - NEGS, // NEGS Rd, Rm{,shift} = SUBS Rd, ZR, Rm{,shift} - CMP_SR, // CMP Rn, Rm{,shift} = SUBS ZR, Rn, Rm{,shift} - CMP_ER, // CMP Rn, Rm, ext = SUBS ZR, Rn, Rm, ext - CMP_IMM, // CMP Rn, #imm = SUBS ZR, Rn, #imm - CMN_SR, // CMN Rn, Rm{,shift} = ADDS ZR, Rn, Rm{,shift} - CMN_ER, // CMN Rn, Rm, ext = ADDS ZR, Rn, Rm, ext - CMN_IMM, // CMN Rn, #imm = ADDS ZR, Rn, #imm - TST_SR, // TST Rn, Rm{,shift} = ANDS ZR, Rn, Rm{,shift} + NEGS, // NEGS Rd, Rm{,shift} = SUBS Rd, ZR, Rm{,shift} + CMP, // CMP Rn, Rm{,shift} = SUBS ZR, Rn, Rm{,shift} + CMN, // CMN Rn, Rm{,shift} = ADDS ZR, Rn, Rm{,shift} } diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index df7975f0c..1459b062b 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -273,17 +273,19 @@ wprintln :: proc( // Internal writers // ============================================================================= -// write_full_mnemonic handles a few special cases that need transformation: -// * Suffix family mnemonics (ADD_IMM/ADD_SR/ADD_ER) collapse to `add`. -// * B_COND prints as `b.` using the first operand's cond payload. -// * Mov-wide / shifted/extended/imm variants all share the canonical -// ARM ARM mnemonic; the suffix is for our internal disambiguation. +// write_full_mnemonic handles the two mnemonics whose printed spelling is not +// just the enum name: B_COND / BC_COND carry the condition in the mnemonic +// itself (`b.eq`, `bc.ne`) rather than as a printed operand. @(private="file") write_full_mnemonic :: proc(sb: ^strings.Builder, inst: ^Instruction, uppercase: bool) { - // B_COND -> `b.` based on the first operand. - if inst.mnemonic == .B_COND && inst.operand_count >= 1 && inst.ops[0].kind == .COND { - strings.write_string(sb, uppercase ? "B." : "b.") + // B_COND / BC_COND -> `b.` / `bc.` from the first operand. + if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && inst.operand_count >= 1 && inst.ops[0].kind == .COND { + if inst.mnemonic == .BC_COND { + strings.write_string(sb, uppercase ? "BC." : "bc.") + } else { + strings.write_string(sb, uppercase ? "B." : "b.") + } c := inst.ops[0].cond & 0xF cn := COND_NAMES[c] if uppercase { @@ -305,25 +307,26 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { name, ok := reflect.enum_name_from_value(m) if !ok { strings.write_string(sb, ""); return } - // Strip internal disambiguator suffixes -- the user-facing mnemonic - // is just the base name (ADD_IMM -> add, ADD_SR -> add, LDR_LIT -> ldr, - // CCMP_REG -> ccmp, MSR_REG -> msr, FMOV_GEN -> fmov, ...). - n := len(name) - suffixes := []string{ "_IMM", "_SR", "_ER", "_LIT", "_REG", "_COND", "_GEN" } - for s in suffixes { - if n > len(s) { - tail := name[n - len(s):] - if tail == s { - n -= len(s) - break - } + // Enum names are the assembler mnemonics, so this is a straight + // transliteration -- with one exception. The system instructions below + // are written by assemblers as a mnemonic plus an op-name token + // (`dc zva`, `tlbi vae1`, `bti j`), which we store as one enum member, + // so for those the first underscore prints as a space. Every other + // underscore is kept: AMX_LDX is an undocumented Apple coprocessor op + // with no assembler spelling at all, and printing it `amx ldx` would + // imply a two-token syntax that does not exist. + split := -1 + for prefix in ([]string{"DC_", "IC_", "AT_", "TLBI_", "BTI_", "PSB_", "TSB_"}) { + if len(name) > len(prefix) && name[:len(prefix)] == prefix { + split = len(prefix) - 1 + break } } - for i in 0..= 'A' && c <= 'Z' { strings.write_byte(sb, c + 32) } else { diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 95a570f53..c22a72863 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2442]lib.Decode_Entry{ +DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, @@ -33,737 +33,867 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true} }, { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true} }, { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .SME_ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {} }, - { .SME2_ZIP_4, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {} }, - { .SME2_UZP_4, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {} }, - { .SME_ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, - { .SME_ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {} }, - { .SME2_ZIP_3, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {} }, - { .SME2_UZP_3, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {} }, - { .SME2_LUTI2_B, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {} }, - { .SME2_LUTI4_B, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, - { .SME2_LD1B_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1H_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1W_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1D_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, - { .SME2_LD1B_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1H_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1W_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - { .SME2_LD1D_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, - { .SME2_ST1B_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1H_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1W_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1D_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true} }, - { .SME2_ST1B_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1H_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1W_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {} }, - { .SME2_ST1D_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true} }, - { .SME_FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {} }, - { .SME_FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, - { .SME_BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, - { .SME_BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, - { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, - { .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SME_SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, - { .SME_SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, - { .SME_UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, - { .SME_UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .SME_UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, - { .SME_UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, - { .SME_USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, - { .SME_SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - { .SME_MOVA_Z_FROM_TILE, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, - { .SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, - { .SME_LDR_ZA, {.IMM_5,.MEM,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, - { .SME_STR_ZA, {.IMM_5,.MEM,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, - { .SME_LD1B_TILE, {.SME_SLICE_B,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, - { .SME_LD1H_TILE, {.SME_SLICE_H,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {} }, - { .SME_LD1W_TILE, {.SME_SLICE_W,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {} }, - { .SME_LD1D_TILE, {.SME_SLICE_D,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true} }, - { .SME_LD1Q_TILE, {.SME_SLICE_Q,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {} }, - { .SME_ST1B_TILE, {.SME_SLICE_B,.P_REG,.MEM,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {} }, - { .SME_ST1H_TILE, {.SME_SLICE_H,.P_REG,.MEM,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {} }, - { .SME_ST1W_TILE, {.SME_SLICE_W,.P_REG,.MEM,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {} }, - { .SME_ST1D_TILE, {.SME_SLICE_D,.P_REG,.MEM,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true} }, - { .SME_ST1Q_TILE, {.SME_SLICE_Q,.P_REG,.MEM,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {} }, - { .SVE_SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, - { .SVE_PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {} }, - { .SVE_RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {} }, - { .SVE_WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {} }, - { .SVE_AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {} }, - { .SVE_AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {} }, - { .SVE_PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {} }, - { .SVE_PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {} }, - { .SVE_REV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, - { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, - { .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, - { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .SVE_INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .SVE_INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, - { .SVE_INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .SVE_INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, - { .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, - { .SVE_AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, - { .SME_RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, - { .SVE_BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, - { .SVE_BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, - { .SVE_BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, - { .SVE_BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, - { .SVE_BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {} }, - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, - { .SVE_AND_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_ORR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_EOR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_BIC_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_ASRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .SVE_ASRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .SVE_ASRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_ASRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_LSLR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_LSRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .SVE_FSUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FSUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, - { .SVE_FSUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, - { .SVE_FDIVR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, - { .SVE_FDIVR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FDIVR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRECPX_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRECPX_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRECPX_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, - { .SVE_ZIP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, - { .SVE_ZIP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, - { .SVE_UZP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, - { .SVE_UZP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, - { .SVE_TRN1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, - { .SVE_TRN2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_CPY_Z, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, - { .SVE_COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, - { .SVE_COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, - { .SVE_SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, - { .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, - { .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, - { .SVE_TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, - { .SVE_BCAX_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_EOR3_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_FMLA_IDX_S, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FMLA_IDX_D, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FMLS_IDX_S, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, - { .SVE_FMLS_IDX_D, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_INDEX_II, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, - { .SVE_INDEX_IR, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, - { .SVE_INDEX_RI, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, - { .SVE_INDEX_RR, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_PMUL_VEC, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_BFADD_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_BFSUB_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_BFMUL_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, - { .SVE_BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_NANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .SVE_NORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .SVE_ORNS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .SVE_BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, - { .SVE_BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, - { .SVE_WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .SVE_FMLA_IDX_H, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, - { .SVE_FMLS_IDX_H, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, - { .SVE_AND_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .SVE_BIC_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, - { .SVE_ORR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, - { .SVE_EOR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, - { .SVE_NAND_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, - { .SVE_NOR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, - { .SVE_ORN_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, - { .SVE_SEL_P, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, - { .SVE_ANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_BICS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_NOT_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, - { .SVE_MOV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, - { .SVE_MOV_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .SVE_MOVS_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, - { .SVE_LDR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, - { .SVE_STR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .SVE_XAR_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_XAR_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, - { .SVE_XAR_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_XAR_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, - { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, - { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_EXT_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, - { .SVE_LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ST1B, {.Z_REG_B,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, - { .SVE_ST1H, {.Z_REG_H,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_ST1W, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, - { .SVE_ST1D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_LDR_Z, {.Z_REG_B,.MEM,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, - { .SVE_STR_Z, {.Z_REG_B,.MEM,.NONE,.NONE}, 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.FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, + { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, + { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, + { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, + { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, + { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, + { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, + { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, + { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, + { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, + { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, + { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, + { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, + { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, + { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, + { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, + { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, + { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, + { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, + { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, + { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, + { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, + { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, + { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {} }, + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {} }, + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {} }, + { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {} }, + { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, 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0x8800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {} }, + { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {} }, 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{} }, + { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {} }, + { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true} }, + { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, + { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, - { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - { .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, - { .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, - { .ADD_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, - { 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{.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ADDS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .SUB_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true} }, - { .SUB_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {} }, - { .SUBS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .SUBS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .AND_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true} }, - { .AND_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {} }, - { .ANDS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ANDS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .ORR_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {} }, - { .ORR_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true} }, - { .EOR_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true} }, - { .EOR_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {} }, - { .BIC_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {} }, - { .BIC_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true} }, - { .BICS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .BICS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ORN_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true} }, - { .ORN_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {} }, - { .EON_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {} }, - { .EON_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, - { .LD1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, - { .LD2, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {} }, - { .LD3, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {} }, - { .LD4, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {} }, - { .ST1, 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.DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, - { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, - { .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - { .NOT_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {} }, - { .DUP_V, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, - { .DUP_V, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {} }, - { .SHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, - { .SHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {} }, { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {} }, { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {} }, { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {} }, { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {} }, { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {} }, @@ -1120,8 +1123,8 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {} }, { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {} }, { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {} }, { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {} }, @@ -1144,29 +1147,24 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {} }, { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {} }, { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {} }, - { .DUP_V, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, - { .DUP_V, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, - { .FMOV_V_IMM, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, - { .SHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {} }, { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {} }, { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {} }, @@ -1177,14 +1175,14 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {} }, { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {} }, { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {} }, { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {} }, + { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {} }, { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {} }, + { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {} }, { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {} }, { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {} }, { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {} }, { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {} }, { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {} }, @@ -1209,10 +1207,58 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {} }, { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {} }, { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {} }, - { .DUP_V, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP_V, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {} }, { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {} }, { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {} }, @@ -1220,509 +1266,461 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {} }, { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {} }, { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, + { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, - { .ADD_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, - { .MUL_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, - { .MUL_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, - { .MUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {} }, { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {} }, { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {} }, { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {} }, { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {} }, { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {} }, { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {} }, { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {} }, { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {} }, { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {} }, { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {} }, { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {} }, { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {} }, { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {} }, { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {} }, { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {} }, { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {} }, { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {} }, { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {} }, { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {} }, { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {} }, { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {} }, { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {} }, { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, 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{} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {} }, { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {} }, { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {} }, { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {} }, { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, 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{} }, { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {} }, - { .FMAX_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAX_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, - { .FMIN_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMAXP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAXP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {} }, - { .FMINP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMINP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMINP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {} }, { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {} }, { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {} }, { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {} }, { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {} }, { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {} }, { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {} }, { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {} }, { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {} }, { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {} }, { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {} }, - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {} }, { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {} }, { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {} }, - { .FADDP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {} }, - { .FADDP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {} }, - { .FADDP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {} }, { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 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{.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {} }, - { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {} }, { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {} }, - { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {} }, { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {} }, { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {} }, { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {} }, { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {} }, { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {} }, { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {} }, { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {} }, { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {} }, { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {} }, @@ -1743,58 +1741,56 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {} }, { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {} }, { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {} }, { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {} }, { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {} }, { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {} }, { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {} }, { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {} }, { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {} }, { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {} }, { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {} }, - { .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .SHL_V, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, - { .SQSHL_V, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {} }, { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {} }, { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {} }, @@ -1811,35 +1807,35 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, - { .FCADD_4H, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD_8H, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD_4S, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD_2D, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, - { .EXT_V, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .FCMLA_4H, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA_8H, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA_4S, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA_2D, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, - { .EXT_V, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {} }, { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, - { .CMP_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMP_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMN_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true} }, { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true} }, - { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, - { .ADD_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, - { .ADDS_IMM, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .ADDS_IMM, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .SUB_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, - { .SUB_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, - { .SUBS_IMM, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .SUBS_IMM, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {} }, { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {} }, { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {} }, @@ -1848,34 +1844,34 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .TST_IMM, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, - { .MOV_BITMASK, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, - { .TST_IMM, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .MOV_BITMASK, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true} }, { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {} }, - { .ROR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, - { .ROR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, - { .AND_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, - { .ANDS_IMM, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, - { .ORR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, - { .EOR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, - { .LSL_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, - { .LSL_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {} }, { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true} }, - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {} }, { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true} }, - { .AND_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, - { .ANDS_IMM, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .ORR_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, - { .EOR_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, @@ -1891,8 +1887,8 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, - { .SME_SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, - { .SME_SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, + { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, + { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, @@ -1959,7 +1955,7 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true} }, { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true} }, { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {} }, - { .MSR_IMM, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {} }, + { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {} }, { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true} }, { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true} }, { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true} }, @@ -1967,13 +1963,13 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true} }, { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {} }, { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {} }, - { .MSR_REG, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {} }, + { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {} }, { .B_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true} }, { .BC_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true} }, - { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true} }, { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true} }, - { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true} }, + { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true} }, { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true} }, + { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, @@ -1997,173 +1993,173 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true} }, - { .LDAPR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {} }, - { .LDAPR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true} }, - { .LDAPRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {} }, - { .LDAPRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {} }, - { .LDADD, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {} }, - { .LDADD, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDADDA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {} }, - { .LDADDA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDADDL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {} }, - { .LDADDL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDADDAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {} }, - { .LDCLR, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {} }, - { .LDCLR, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDCLRA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDCLRL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDEOR, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDEOR, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {} }, - { .LDEORA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDEORA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {} }, - { .LDEORL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {} }, - { .LDEORL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDEORAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {} }, - { .LDSET, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSET, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {} }, - { .LDSETA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSETA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {} }, - { .LDSETL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSETAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMAX, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMAX, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMAXA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMAXL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMIN, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMIN, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMINL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDSMINAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMAX, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMAXA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMAXL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMIN, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMINL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMINAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .LDUMINAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {} }, - { .SWP, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {} }, - { .SWP, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .SWPA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {} }, - { .SWPA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .SWPL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true} }, - { .SWPL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {} }, - { .SWPAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {} }, - { .SWPAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {} }, + { 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}, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {} }, + { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {} }, + { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {} }, + { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {} }, + { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {} }, + { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true} }, { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true} }, { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true} }, { .PACDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true} }, @@ -2178,8 +2174,8 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true} }, { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true} }, { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {} }, - { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {} }, { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true} }, + { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {} }, { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true} }, { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {} }, { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true} }, @@ -2193,22 +2189,22 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true} }, { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true} }, { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true} }, - { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, + { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, - { .LSLV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, - { .LSLV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, - { .LSRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, - { .LSRV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {} }, - { .ASRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, - { .ASRV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, - { .RORV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, - { .RORV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, - { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {} }, - { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true} }, { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {} }, + { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true} }, { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true} }, { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true} }, { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true} }, @@ -2226,30 +2222,30 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} }, { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, - { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, - { .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - { .CCMP_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMP_IMM, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - { .CCMP_IMM, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - { .CCMN_IMM, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN_IMM, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true} }, { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {} }, { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {} }, { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true} }, - { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {} }, { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true} }, + { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {} }, { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {} }, - { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true} }, + { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true} }, { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {} }, + { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true} }, { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {} }, { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true} }, { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true} }, @@ -2259,119 +2255,133 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true} }, { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true} }, { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true} }, - { .LDUR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {} }, - { .LDUR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {} }, - { .LDUR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {} }, - { .STUR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {} }, - { .STUR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {} }, - { .STUR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {} }, - { .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, - { .STR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, - { .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, - { .FMOV_REG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, - { .FMOV_REG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, - { .FMOV_GEN, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FMOV_GEN, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {} }, - { .FMOV_GEN, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {} }, - { .FMOV_GEN, {.X_REG,.D_REG,.NONE,.NONE}, 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.FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {} }, { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {} }, { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {} }, { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {} }, { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {} }, { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {} }, - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {} }, { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {} }, { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {} }, { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {} }, { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {} }, { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {} }, { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {} }, { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {} }, { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {} }, { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {} }, { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {} }, { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {} }, @@ -2381,45 +2391,40 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {} }, { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {} }, { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {} }, - { .FABS_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {} }, - { .FNEG_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {} }, - { .FSQRT_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {} }, - { .FCMP_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true} }, - { .FCMPE_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true} }, - { .FCVT_H_S, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {} }, - { .FCVT_H_D, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {} }, - { .FCVT_S_H, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {} }, - { .FCVT_D_H, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {} }, - { .FMOV_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {} }, - { .SCVTF_H, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {} }, - { .UCVTF_H, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {} }, - { .FCVTZS_H, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {} }, - { .FCVTZU_H, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {} }, { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {} }, { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {} }, { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FMOV_IMM, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, - { .FMOV_IMM, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, - { .FMOV_IMM, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {} }, { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {} }, - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {} }, { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {} }, { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {} }, { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {} }, { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {} }, - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {} }, { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {} }, { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {} }, { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {} }, @@ -2427,30 +2432,21 @@ DECODE_ENTRIES := [2442]lib.Decode_Entry{ { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {} }, { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {} }, { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {} }, - { .FADD_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, - { .FSUB_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, - { .FMUL_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, - { .FDIV_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, - { .FNMUL_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, - { .FMAX_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, - { .FMIN_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, - { .FMINNM_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {} }, { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {} }, - { .FCSEL_H, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {} }, { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {} }, { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {} }, { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {} }, { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {} }, - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {} }, - { .FMADD_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, - { .FMSUB_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, - { .FNMADD_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, - { .FNMSUB_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {} }, } @(rodata) @@ -2460,14 +2456,14 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x04 = { 573, 76}, 0x05 = { 649, 50}, 0x06 = { 699, 56}, - 0x07 = { 755, 1062}, - 0x08 = {1817, 16}, - 0x09 = {1833, 34}, - 0x0A = {1867, 100}, - 0x0B = {1967, 21}, - 0x0C = {1988, 167}, - 0x0D = {2155, 92}, - 0x0E = {2247, 19}, - 0x0F = {2266, 176}, + 0x07 = { 755, 1058}, + 0x08 = {1813, 16}, + 0x09 = {1829, 34}, + 0x0A = {1863, 100}, + 0x0B = {1963, 21}, + 0x0C = {1984, 167}, + 0x0D = {2151, 92}, + 0x0E = {2243, 19}, + 0x0F = {2262, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 52ed8fa3a..330bd68e0 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,19 +8,62 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2440]lib.Encoding{ - // .ADD_IMM - { .ADD_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, - { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, - // .ADDS_IMM - { .ADDS_IMM, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .ADDS_IMM, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - // .SUB_IMM - { .SUB_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, - { .SUB_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, - // .SUBS_IMM - { .SUBS_IMM, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .SUBS_IMM, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, +ENCODE_FORMS := [2436]lib.Encoding{ + // .ADD + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, + { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {} }, + { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true} }, + { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, + { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, + // .ADDS + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true} }, + { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, + { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} }, + { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, + // .SUB + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, + { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {} }, + { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true} }, + { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {} }, + { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SUBS + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true} }, + { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, + { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true} }, + { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, // .MOVZ { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {} }, { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, @@ -34,72 +77,96 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {} }, // .ADRP { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {} }, - // .ADD_SR - { .ADD_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {} }, - { .ADD_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true} }, - // .ADDS_SR - { .ADDS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ADDS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - // .SUB_SR - { .SUB_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {} }, - { .SUB_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true} }, - // .SUBS_SR - { .SUBS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .SUBS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - // .AND_SR - { .AND_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {} }, - { .AND_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true} }, - // .ANDS_SR - { .ANDS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ANDS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - // .ORR_SR - { .ORR_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {} }, - { .ORR_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true} }, - // .EOR_SR - { .EOR_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {} }, - { .EOR_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true} }, - // .BIC_SR - { .BIC_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {} }, - { .BIC_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true} }, - // .BICS_SR - { .BICS_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true} }, - { .BICS_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - // .ORN_SR - { .ORN_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {} }, - { .ORN_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true} }, - // .EON_SR - { .EON_SR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {} }, - { .EON_SR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, - // .ADD_ER - { .ADD_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, - { .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, - // .ADDS_ER - { .ADDS_ER, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} }, - { .ADDS_ER, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, - // .SUB_ER - { .SUB_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {} }, - { .SUB_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true} }, - // .SUBS_ER - { .SUBS_ER, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true} }, - { .SUBS_ER, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, - // .LSLV - { .LSLV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, - { .LSLV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, - // .LSRV - { .LSRV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {} }, - { .LSRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, - // .ASRV - { .ASRV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, - { .ASRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, - // .RORV - { .RORV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, - { .RORV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, + // .AND + { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {} }, + { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, + // .ANDS + { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true} }, + { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, + { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .ORR + { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {} }, + { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, + // .EOR + { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {} }, + { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, + { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, + // .BIC + { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {} }, + { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, + // .BICS + { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true} }, + { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, + { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .ORN + { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {} }, + { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {} }, + { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, + // .EON + { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {} }, + { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, + // .LSL + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, + // .LSR + { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + // .ASR + { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + // .ROR + { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, // .UDIV { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {} }, { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, // .SDIV { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {} }, { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, // .MADD { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {} }, { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true} }, @@ -116,25 +183,66 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true} }, // .SMULH { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, // .UMULH { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, // .CLZ { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {} }, { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, // .CLS { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {} }, { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true} }, + { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, // .RBIT { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {} }, { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true} }, + { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, + { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, // .REV { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {} }, { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, // .REV16 { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {} }, { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true} }, + { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, + { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, // .REV32 { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true} }, + { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, + { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, + { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, // .CSEL { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {} }, { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true} }, @@ -147,18 +255,16 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .CSNEG { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {} }, { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true} }, - // .CCMP_REG - { .CCMP_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - // .CCMP_IMM - { .CCMP_IMM, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMP_IMM, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - // .CCMN_REG - { .CCMN_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - // .CCMN_IMM - { .CCMN_IMM, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN_IMM, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + // .CCMP + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + // .CCMN + { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, // .EXTR { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {} }, { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true} }, @@ -186,64 +292,124 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .TBNZ { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true} }, // .LDR - { .LDR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {} }, - { .LDR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {} }, + { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {} }, + { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} }, + { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, + { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} }, + { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, + { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, // .STR - { .STR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {} }, - { .STR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true} }, + { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {} }, + { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, + { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, + { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, + { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, + { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, + { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, + { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, // .LDRB - { .LDRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {} }, // .STRB - { .STRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {} }, + { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {} }, + { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {} }, + { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {} }, // .LDRSB - { .LDRSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDRSB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {} }, + { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {} }, + { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDRH - { .LDRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {} }, // .STRH - { .STRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {} }, + { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {} }, + { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {} }, + { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {} }, // .LDRSH - { .LDRSH, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDRSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {} }, + { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {} }, + { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDRSW - { .LDRSW, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - // .LDR_LIT - { .LDR_LIT, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {} }, - { .LDR_LIT, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, // .LDAR - { .LDAR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, - { .LDAR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, // .STLR - { .STLR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {} }, - { .STLR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true} }, // .LDARB - { .LDARB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {} }, + { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {} }, // .STLRB - { .STLRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {} }, // .LDARH - { .LDARH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {} }, + { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {} }, // .STLRH - { .STLRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {} }, // .LDXR - { .LDXR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {} }, - { .LDXR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true} }, // .STXR - { .STXR, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {} }, - { .STXR, {.W_REG,.X_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true} }, // .LDAXR - { .LDAXR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {} }, - { .LDAXR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true} }, // .STLXR - { .STLXR, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {} }, - { .STLXR, {.W_REG,.X_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true} }, // .NOP { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, // .YIELD @@ -260,10 +426,9 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {} }, // .MRS { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {} }, - // .MSR_IMM - { .MSR_IMM, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {} }, - // .MSR_REG - { .MSR_REG, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {} }, + // .MSR + { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {} }, + { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {} }, // .ISB { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {} }, // .DSB @@ -282,98 +447,238 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true} }, // .ERET { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, - // .FMOV_REG - { .FMOV_REG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, - { .FMOV_REG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, - // .FMOV_IMM - { .FMOV_IMM, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, - { .FMOV_IMM, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, - { .FMOV_IMM, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, - // .FMOV_GEN - { .FMOV_GEN, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {} }, - { .FMOV_GEN, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {} }, - { .FMOV_GEN, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FMOV_GEN, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} }, + // .FMOV + { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, + { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, + { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {} }, + { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true} }, + { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, // .FABS { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {} }, { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {} }, + { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {} }, + { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {} }, + { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, // .FNEG { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {} }, { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {} }, + { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {} }, + { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, // .FSQRT { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {} }, { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {} }, + { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {} }, + { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, // .FADD { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, // .FSUB { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {} }, { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, // .FMUL { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, // .FDIV { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, // .FNMUL { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, // .FMADD { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {} }, { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, // .FMSUB { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {} }, { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, // .FNMADD { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {} }, { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, // .FNMSUB { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {} }, { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, // .FCMP { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true} }, { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true} }, + { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true} }, // .FCMPE { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true} }, { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true} }, + { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true} }, // .FCSEL { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {} }, { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, // .FMAX { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {} }, { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, // .FMIN { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {} }, { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, // .FMAXNM { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, // .FMINNM { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {} }, { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, // .FCVT { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {} }, { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {} }, + { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {} }, + { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {} }, + { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {} }, + { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {} }, // .SCVTF { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {} }, { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {} }, { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true} }, { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true} }, + { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {} }, + { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {} }, + { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {} }, + { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {} }, // .UCVTF { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {} }, { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {} }, { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true} }, { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true} }, + { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {} }, + { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {} }, + { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {} }, + { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {} }, // .FCVTZS { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {} }, { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {} }, { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true} }, { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true} }, + { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {} }, // .FCVTZU { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {} }, { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {} }, { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true} }, { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true} }, + { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {} }, + { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {} }, // .FCVTAS { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {} }, { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {} }, @@ -381,6 +686,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {} }, { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {} }, { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {} }, + { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {} }, // .FCVTAU { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {} }, { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {} }, @@ -388,6 +698,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {} }, { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {} }, { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {} }, // .FCVTNS { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {} }, { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {} }, @@ -395,6 +710,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {} }, { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {} }, { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {} }, + { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {} }, // .FCVTNU { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {} }, { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {} }, @@ -402,6 +722,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {} }, { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {} }, { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {} }, // .FCVTPS { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {} }, { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {} }, @@ -409,6 +734,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {} }, { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {} }, { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {} }, + { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {} }, // .FCVTPU { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {} }, @@ -416,6 +746,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {} }, { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {} }, + { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {} }, + { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {} }, // .FCVTMS { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {} }, @@ -423,6 +758,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {} }, { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {} }, + { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {} }, // .FCVTMU { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {} }, { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {} }, @@ -430,326 +770,317 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {} }, { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {} }, { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {} }, + { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {} }, // .FRINTA { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {} }, { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {} }, { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {} }, + { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {} }, + { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {} }, + { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTI { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {} }, { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {} }, { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {} }, + { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTM { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {} }, { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {} }, { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {} }, + { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTN { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {} }, { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {} }, { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {} }, + { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {} }, + { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {} }, + { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTP { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {} }, { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {} }, { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {} }, + { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {} }, + { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTX { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {} }, { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {} }, { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {} }, + { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, // .FRINTZ { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {} }, { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {} }, { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {} }, - // .AND_IMM - { .AND_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, - { .AND_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, - // .ANDS_IMM - { .ANDS_IMM, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, - { .ANDS_IMM, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - // .ORR_IMM - { .ORR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, - { .ORR_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, - // .EOR_IMM - { .EOR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, - { .EOR_IMM, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, - // .TST_IMM - { .TST_IMM, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, - { .TST_IMM, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {} }, + { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .TST + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, // .LDUR - { .LDUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {} }, - { .LDUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {} }, + { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {} }, + { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {} }, + { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {} }, // .STUR - { .STUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {} }, - { .STUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true} }, + { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {} }, + { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {} }, // .LDURB - { .LDURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {} }, + { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {} }, // .STURB - { .STURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {} }, + { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {} }, // .LDURSB - { .LDURSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDURSB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {} }, + { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {} }, // .LDURH - { .LDURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {} }, + { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {} }, // .STURH - { .STURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {} }, + { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {} }, // .LDURSH - { .LDURSH, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDURSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {} }, + { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {} }, // .LDURSW - { .LDURSW, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDR_PRE - { .LDR_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {} }, - { .LDR_PRE, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true} }, - // .STR_PRE - { .STR_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {} }, - { .STR_PRE, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDR_POST - { .LDR_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {} }, - { .LDR_POST, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true} }, - // .STR_POST - { .STR_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {} }, - { .STR_POST, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDRB_PRE - { .LDRB_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {} }, - // .STRB_PRE - { .STRB_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {} }, - // .LDRB_POST - { .LDRB_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {} }, - // .STRB_POST - { .STRB_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {} }, - // .LDRH_PRE - { .LDRH_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {} }, - // .STRH_PRE - { .STRH_PRE, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {} }, - // .LDRH_POST - { .LDRH_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {} }, - // .STRH_POST - { .STRH_POST, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {} }, - // .LDR_REG - { .LDR_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {} }, - { .LDR_REG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true} }, - // .STR_REG - { .STR_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {} }, - { .STR_REG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDRB_REG - { .LDRB_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {} }, - // .STRB_REG - { .STRB_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {} }, - // .LDRH_REG - { .LDRH_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {} }, - // .STRH_REG - { .STRH_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {} }, - // .LDRSB_REG - { .LDRSB_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {} }, - { .LDRSB_REG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDRSH_REG - { .LDRSH_REG, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {} }, - { .LDRSH_REG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDRSW_REG - { .LDRSW_REG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, - // .LDP_PRE - { .LDP_PRE, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP_PRE, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - // .STP_PRE - { .STP_PRE, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .STP_PRE, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - // .LDP_POST - { .LDP_POST, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP_POST, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - // .STP_POST - { .STP_POST, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP_POST, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - // .LDPSW_PRE - { .LDPSW_PRE, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - // .LDPSW_POST - { .LDPSW_POST, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .LDNP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, // .LDXP - { .LDXP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, - { .LDXP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, // .STXP - { .STXP, {.W_REG,.W_REG,.W_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, - { .STXP, {.W_REG,.X_REG,.X_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true} }, + { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true} }, // .LDAXP - { .LDAXP, {.W_REG,.W_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {} }, - { .LDAXP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true} }, // .STLXP - { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, - { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, + { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, // .LDXRB - { .LDXRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {} }, // .STXRB - { .STXRB, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {} }, + { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {} }, // .LDAXRB - { .LDAXRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {} }, // .STLXRB - { .STLXRB, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {} }, // .LDXRH - { .LDXRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {} }, // .STXRH - { .STXRH, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {} }, + { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {} }, // .LDAXRH - { .LDAXRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {} }, // .STLXRH - { .STLXRH, {.W_REG,.W_REG,.MEM,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {} }, // .LDAPR - { .LDAPR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {} }, - { .LDAPR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true} }, // .LDAPRB - { .LDAPRB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {} }, // .LDAPRH - { .LDAPRH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {} }, // .LDADD - { .LDADD, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {} }, - { .LDADD, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDADDA - { .LDADDA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {} }, - { .LDADDA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDADDL - { .LDADDL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {} }, - { .LDADDL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDADDAL - { .LDADDAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDCLR - { .LDCLR, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {} }, - { .LDCLR, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDCLRA - { .LDCLRA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {} }, + { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDCLRL - { .LDCLRL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {} }, + { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDCLRAL - { .LDCLRAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {} }, + { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDEOR - { .LDEOR, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {} }, - { .LDEOR, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {} }, + { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDEORA - { .LDEORA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {} }, - { .LDEORA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {} }, + { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDEORL - { .LDEORL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {} }, - { .LDEORL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {} }, + { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDEORAL - { .LDEORAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {} }, + { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSET - { .LDSET, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {} }, - { .LDSET, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSETA - { .LDSETA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {} }, + { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSETL - { .LDSETL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {} }, - { .LDSETL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {} }, + { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSETAL - { .LDSETAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {} }, + { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMAX - { .LDSMAX, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAX, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {} }, + { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMAXA - { .LDSMAXA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {} }, + { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMAXL - { .LDSMAXL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {} }, + { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMAXAL - { .LDSMAXAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {} }, + { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMIN - { .LDSMIN, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {} }, - { .LDSMIN, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {} }, + { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMINA - { .LDSMINA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {} }, + { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMINL - { .LDSMINL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {} }, + { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDSMINAL - { .LDSMINAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMAX - { .LDUMAX, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {} }, + { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMAXA - { .LDUMAXA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {} }, + { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMAXL - { .LDUMAXL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {} }, + { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMAXAL - { .LDUMAXAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {} }, + { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMIN - { .LDUMIN, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {} }, + { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMINA - { .LDUMINA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {} }, + { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMINL - { .LDUMINL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {} }, + { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true} }, // .LDUMINAL - { .LDUMINAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {} }, + { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true} }, // .SWP - { .SWP, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {} }, - { .SWP, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {} }, + { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true} }, // .SWPA - { .SWPA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {} }, - { .SWPA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true} }, // .SWPL - { .SWPL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {} }, - { .SWPL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {} }, + { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true} }, // .SWPAL - { .SWPAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {} }, - { .SWPAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {} }, + { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true} }, // .CAS - { .CAS, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {} }, - { .CAS, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {} }, + { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASA - { .CASA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {} }, - { .CASA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASL - { .CASL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {} }, - { .CASL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASAL - { .CASAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {} }, - { .CASAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASB - { .CASB, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {} }, + { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {} }, // .CASAB - { .CASAB, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {} }, // .CASLB - { .CASLB, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {} }, // .CASALB - { .CASALB, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {} }, // .CASH - { .CASH, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {} }, + { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {} }, // .CASAH - { .CASAH, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {} }, // .CASLH - { .CASLH, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {} }, // .CASALH - { .CASALH, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {} }, // .CASP - { .CASP, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {} }, - { .CASP, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASPA - { .CASPA, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {} }, - { .CASPA, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASPL - { .CASPL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {} }, - { .CASPL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, // .CASPAL - { .CASPAL, {.W_REG,.W_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {} }, - { .CASPAL, {.X_REG,.X_REG,.MEM,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, // .PACIA { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true} }, // .PACIB @@ -845,23 +1176,23 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .SUBPS { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true} }, // .LDG - { .LDG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true} }, + { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true} }, // .STG - { .STG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true} }, // .ST2G - { .ST2G, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true} }, + { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true} }, // .STZG - { .STZG, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true} }, // .STZ2G - { .STZ2G, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, // .LDGM - { .LDGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, + { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, // .STGM - { .STGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true} }, + { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true} }, // .STZGM - { .STZGM, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} }, // .CRC32B { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {} }, // .CRC32H @@ -880,12 +1211,16 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, // .AESE { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, // .AESD { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, // .AESMC { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {} }, + { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {} }, // .AESIMC { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {} }, + { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {} }, // .SHA1H { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {} }, // .SHA1C @@ -916,12 +1251,18 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {} }, // .EOR3 { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, // .BCAX { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, // .RAX1 { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {} }, // .XAR { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, // .SM3PARTW1 { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {} }, // .SM3PARTW2 @@ -946,64 +1287,9 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .PMULL2 { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - // .FABS_H - { .FABS_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {} }, - // .FNEG_H - { .FNEG_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {} }, - // .FSQRT_H - { .FSQRT_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {} }, - // .FADD_H - { .FADD_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, - // .FSUB_H - { .FSUB_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, - // .FMUL_H - { .FMUL_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, - // .FDIV_H - { .FDIV_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, - // .FNMUL_H - { .FNMUL_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, - // .FMADD_H - { .FMADD_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, - // .FMSUB_H - { .FMSUB_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, - // .FNMADD_H - { .FNMADD_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, - // .FNMSUB_H - { .FNMSUB_H, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, - // .FCMP_H - { .FCMP_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true} }, - // .FCMPE_H - { .FCMPE_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true} }, - // .FCSEL_H - { .FCSEL_H, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, - // .FMAX_H - { .FMAX_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, - // .FMIN_H - { .FMIN_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, - // .FMAXNM_H - { .FMAXNM_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, - // .FMINNM_H - { .FMINNM_H, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, - // .FCVT_H_S - { .FCVT_H_S, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {} }, - // .FCVT_H_D - { .FCVT_H_D, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {} }, - // .FCVT_S_H - { .FCVT_S_H, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {} }, - // .FCVT_D_H - { .FCVT_D_H, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {} }, - // .FMOV_H - { .FMOV_H, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {} }, - // .SCVTF_H - { .SCVTF_H, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {} }, - // .UCVTF_H - { .UCVTF_H, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {} }, - // .FCVTZS_H - { .FCVTZS_H, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {} }, - // .FCVTZU_H - { .FCVTZU_H, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {} }, // .BFCVT { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, // .BFDOT { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, // .BFMMLA @@ -1016,53 +1302,54 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, // .BFCVTN2 { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, - // .ADD_V - { .ADD_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, - // .SUB_V - { .SUB_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, - { .SUB_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, - // .MUL_V - { .MUL_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, - { .MUL_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, - { .MUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, - // .MLA_V - { .MLA_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, - // .MLS_V - { .MLS_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, - // .NEG_V - { .NEG_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {} }, - // .ABS_V - { .ABS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, + // .MUL + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + // .MLA + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, + // .MLS + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, + // .NEG + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + // .ABS + { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, // .SHADD { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {} }, @@ -1113,6 +1400,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {} }, { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, // .UQADD { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {} }, { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {} }, @@ -1121,6 +1412,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {} }, { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {} }, { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, // .SQSUB { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {} }, @@ -1129,6 +1424,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {} }, { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, // .UQSUB { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {} }, @@ -1137,6 +1436,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {} }, { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, // .SMAX { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {} }, { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {} }, @@ -1144,6 +1447,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {} }, { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {} }, { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, // .UMAX { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {} }, @@ -1151,6 +1458,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {} }, { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, // .SMIN { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {} }, { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {} }, @@ -1158,6 +1469,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {} }, { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {} }, { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, // .UMIN { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {} }, { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {} }, @@ -1165,6 +1480,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {} }, { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {} }, { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, // .SABD { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {} }, @@ -1172,6 +1491,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {} }, { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, // .UABD { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {} }, @@ -1179,6 +1502,10 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, // .SABA { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {} }, @@ -1193,14 +1520,14 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {} }, { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {} }, { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {} }, - // .ADDP_V - { .ADDP_V, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {} }, + // .ADDP + { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {} }, // .ADDV { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, @@ -1427,22 +1754,22 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {} }, { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {} }, { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {} }, - // .SMULL_V - { .SMULL_V, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL_V, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {} }, - // .SMULL2_V - { .SMULL2_V, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2_V, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2_V, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {} }, - // .UMULL_V - { .UMULL_V, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL_V, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {} }, - // .UMULL2_V - { .UMULL2_V, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL2_V, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL2_V, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {} }, + // .SMULL + { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {} }, + // .SMULL2 + { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {} }, + // .UMULL + { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {} }, + // .UMULL2 + { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {} }, // .SMLAL { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {} }, { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {} }, @@ -1512,88 +1839,42 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .USDOT { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {} }, { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {} }, - // .FADD_V - { .FADD_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADD_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, - // .FSUB_V - { .FSUB_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, - // .FMUL_V - { .FMUL_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, - // .FDIV_V - { .FDIV_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, - // .FNEG_V - { .FNEG_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FNEG_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {} }, - // .FABS_V - { .FABS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FABS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {} }, - // .FSQRT_V - { .FSQRT_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FSQRT_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {} }, - // .FMLA_V - { .FMLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLA_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {} }, - // .FMLS_V - { .FMLS_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLS_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} }, + // .FMLA + { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, + // .FMLS + { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, // .FMULX { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {} }, { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {} }, { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {} }, { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {} }, { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {} }, - // .FMAX_V - { .FMAX_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAX_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, - // .FMIN_V - { .FMIN_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, - // .FMAXNM_V - { .FMAXNM_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, - // .FMINNM_V - { .FMINNM_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, - // .FMAXP_V - { .FMAXP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAXP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {} }, - // .FMINP_V - { .FMINP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMINP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {} }, + // .FMAXP + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {} }, + // .FMINP + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {} }, // .FMAXNMP { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {} }, { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {} }, @@ -1606,14 +1887,14 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {} }, { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {} }, { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {} }, - // .FMAXV_V - { .FMAXV_V, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {} }, - { .FMAXV_V, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {} }, - { .FMAXV_V, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {} }, - // .FMINV_V - { .FMINV_V, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {} }, - { .FMINV_V, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {} }, - { .FMINV_V, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {} }, + // .FMAXV + { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {} }, + { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {} }, + { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {} }, + // .FMINV + { .FMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {} }, + { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {} }, + { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {} }, // .FMAXNMV { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {} }, { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {} }, @@ -1640,136 +1921,31 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {} }, { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {} }, { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, // .FRSQRTS { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {} }, { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {} }, { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {} }, { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {} }, { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, // .FRECPX { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {} }, { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {} }, { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {} }, - // .FADDP_V - { .FADDP_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP_V, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {} }, - { .FADDP_V, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {} }, - // .FRINTA_V - { .FRINTA_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTA_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {} }, - // .FRINTI_V - { .FRINTI_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTI_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {} }, - // .FRINTM_V - { .FRINTM_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTM_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {} }, - // .FRINTN_V - { .FRINTN_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTN_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {} }, - // .FRINTP_V - { .FRINTP_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {} }, - { .FRINTP_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {} }, - // .FRINTX_V - { .FRINTX_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTX_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {} }, - // .FRINTZ_V - { .FRINTZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTZ_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {} }, - // .SCVTF_V - { .SCVTF_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {} }, - { .SCVTF_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {} }, - // .UCVTF_V - { .UCVTF_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {} }, - { .UCVTF_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {} }, - // .FCVTAS_V - { .FCVTAS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {} }, - { .FCVTAS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {} }, - // .FCVTAU_V - { .FCVTAU_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {} }, - { .FCVTAU_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {} }, - // .FCVTMS_V - { .FCVTMS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {} }, - // .FCVTMU_V - { .FCVTMU_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTMU_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {} }, - // .FCVTNS_V - { .FCVTNS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTNS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {} }, - // .FCVTNU_V - { .FCVTNU_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTNU_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {} }, - // .FCVTPS_V - { .FCVTPS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTPS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {} }, - // .FCVTPU_V - { .FCVTPU_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTPU_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {} }, - // .FCVTZS_V - { .FCVTZS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTZS_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {} }, - // .FCVTZU_V - { .FCVTZU_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU_V, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU_V, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTZU_V, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, + // .FADDP + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {} }, // .FCVTL { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {} }, { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {} }, @@ -1792,30 +1968,45 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {} }, { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {} }, { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, // .FCMGE { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {} }, { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {} }, { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {} }, { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, // .FCMGT { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {} }, { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {} }, { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {} }, { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {} }, { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, // .FCMLE { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {} }, { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {} }, { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {} }, { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {} }, { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, // .FCMLT { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {} }, { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {} }, { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {} }, { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {} }, { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, // .FACGE { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {} }, { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {} }, @@ -1879,41 +2070,34 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {} }, - // .AND_V - { .AND_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, - // .ORR_V - { .ORR_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - // .EOR_V - { .EOR_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} }, - // .BIC_V - { .BIC_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {} }, - // .ORN_V - { .ORN_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {} }, - // .MVN_V - { .MVN_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .MVN_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + // .MVN + { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, + { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, // .BIT { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {} }, // .BIF { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} }, // .BSL { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} }, - // .SHL_V - { .SHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, - { .SHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, - { .SHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL_V, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {} }, - { .SHL_V, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {} }, - { .SHL_V, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, - // .SQSHL_V - { .SQSHL_V, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL_V, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL_V, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL_V, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL_V, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {} }, - { .SQSHL_V, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {} }, - { .SQSHL_V, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .SHL + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, + // .SQSHL + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {} }, + { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, // .SQSHLU { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {} }, @@ -2130,21 +2314,25 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {} }, { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {} }, { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {} }, - // .DUP_V - { .DUP_V, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP_V, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP_V, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, - { .DUP_V, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, - { .DUP_V, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, - { .DUP_V, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, - { .DUP_V, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, - { .DUP_V, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, - { .DUP_V, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, + // .DUP + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, + { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, // .INS { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {} }, @@ -2154,18 +2342,35 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {} }, - // .MOV_V - { .MOV_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - // .EXT_V - { .EXT_V, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .EXT_V, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, + // .MOV + { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, + { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, + { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, + { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, + // .EXT + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, // .TBL { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, // .TBX { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, // .ZIP1 { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {} }, { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {} }, @@ -2174,6 +2379,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {} }, { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {} }, { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, // .ZIP2 { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {} }, @@ -2182,6 +2392,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {} }, { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, // .UZP1 { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {} }, @@ -2190,6 +2405,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {} }, { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {} }, { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, // .UZP2 { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {} }, @@ -2198,6 +2418,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {} }, { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {} }, { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, // .TRN1 { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {} }, @@ -2206,6 +2431,11 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {} }, { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, // .TRN2 { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {} }, @@ -2214,20 +2444,15 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {} }, { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {} }, { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {} }, - // .NOT_V - { .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - // .RBIT_V - { .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, - { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, - // .REV16_V - { .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, - { .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, - // .REV32_V - { .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, + // .NOT + { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, + { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, // .REV64 { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, @@ -2235,29 +2460,19 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, - // .CLS_V - { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, - // .CLZ_V - { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, // .CNT { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, - // .URECPE_V - { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, - // .URSQRTE_V - { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, + // .URECPE + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, + // .URSQRTE + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, // .MOVI { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {} }, @@ -2271,917 +2486,455 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {} }, - // .FMOV_V_IMM - { .FMOV_V_IMM, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV_V_IMM, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, - { .FMOV_V_IMM, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, // .LD1 - { .LD1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, - { .LD1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, - { .LD1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, - { .LD1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {} }, // .LD2 - { .LD2, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {} }, // .LD3 - { .LD3, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {} }, // .LD4 - { .LD4, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {} }, // .ST1 - { .ST1, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} }, - { .ST1, {.V_8H,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, - { .ST1, {.V_4S,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, - { .ST1, {.V_2D,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {} }, // .ST2 - { .ST2, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {} }, // .ST3 - { .ST3, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {} }, // .ST4 - { .ST4, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {} }, // .LD1R - { .LD1R, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {} }, // .LD2R - { .LD2R, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {} }, // .LD3R - { .LD3R, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {} }, // .LD4R - { .LD4R, {.V_16B,.MEM,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {} }, - // .LD1_LANE - { .LD1_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {} }, - { .LD1_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {} }, - { .LD1_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {} }, - { .LD1_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {} }, - // .LD2_LANE - { .LD2_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {} }, - { .LD2_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {} }, - { .LD2_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {} }, - { .LD2_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {} }, - // .LD3_LANE - { .LD3_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {} }, - { .LD3_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {} }, - { .LD3_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {} }, - { .LD3_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {} }, - // .LD4_LANE - { .LD4_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {} }, - { .LD4_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {} }, - { .LD4_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {} }, - { .LD4_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {} }, - // .ST1_LANE - { .ST1_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {} }, - { .ST1_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {} }, - { .ST1_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {} }, - { .ST1_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {} }, - // .ST2_LANE - { .ST2_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, - { .ST2_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {} }, - { .ST2_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {} }, - { .ST2_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {} }, - // .ST3_LANE - { .ST3_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, - { .ST3_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {} }, - { .ST3_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {} }, - { .ST3_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {} }, - // .ST4_LANE - { .ST4_LANE, {.V_ELEM_B,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, - { .ST4_LANE, {.V_ELEM_H,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {} }, - { .ST4_LANE, {.V_ELEM_S,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {} }, - { .ST4_LANE, {.V_ELEM_D,.VEC_INDEX,.MEM,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {} }, - // .LDR_V - { .LDR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} }, - // .STR_V - { .STR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, - // .LDP_V - { .LDP_V, {.S_REG,.S_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP_V, {.D_REG,.D_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP_V, {.Q_REG,.Q_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, - // .STP_V - { .STP_V, {.S_REG,.S_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP_V, {.D_REG,.D_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, - { .STP_V, {.Q_REG,.Q_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, - // .LDUR_V - { .LDUR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {} }, - { .LDUR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {} }, - { .LDUR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {} }, - // .STUR_V - { .STUR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {} }, - { .STUR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {} }, - { .STUR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {} }, - // .SVE_ADD_Z - { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_SUB_Z - { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_SQADD_Z - { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_UQADD_Z - { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_SQSUB_Z - { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_UQSUB_Z - { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_ADD_PRED - { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SUB_PRED - { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SUBR_PRED - { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_MUL_PRED - { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SMULH_PRED - { .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_UMULH_PRED - { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SDIV_PRED - { .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, - { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_UDIV_PRED - { .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, - { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SMAX_PRED - { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_UMAX_PRED - { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SMIN_PRED - { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_UMIN_PRED - { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_SABD_PRED - { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_UABD_PRED - { .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_AND_PRED - { .SVE_AND_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_ORR_PRED - { .SVE_ORR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_EOR_PRED - { .SVE_EOR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_BIC_PRED - { .SVE_BIC_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_ASR_PRED - { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_LSL_PRED - { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_LSR_PRED - { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_ASRR_PRED - { .SVE_ASRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, - { .SVE_ASRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .SVE_ASRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .SVE_ASRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_LSLR_PRED - { .SVE_LSLR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSLR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_LSRR_PRED - { .SVE_LSRR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, - { .SVE_LSRR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_ABS_PRED - { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_NEG_PRED - { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_CLS_PRED - { .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_CLZ_PRED - { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_CNT_PRED - { .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, - { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_MOV_PRED - { .SVE_MOV_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, - { .SVE_MOV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FADD_Z - { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FSUB_Z - { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, - { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FMUL_Z - { .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FRECPS - { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FRSQRTS - { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FTSMUL - { .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FADD_PRED - { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, - { .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FSUB_PRED - { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FSUBR_PRED - { .SVE_FSUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, - { .SVE_FSUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, - { .SVE_FSUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FMUL_PRED - { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FDIV_PRED - { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FDIVR_PRED - { .SVE_FDIVR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, - { .SVE_FDIVR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, - { .SVE_FDIVR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FMAX_PRED - { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FMIN_PRED - { .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FMAXNM_PRED - { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FMINNM_PRED - { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FABS_Z - { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FNEG_Z - { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FSQRT_Z - { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FRECPX_Z - { .SVE_FRECPX_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRECPX_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRECPX_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTN - { .SVE_FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTP - { .SVE_FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTM - { .SVE_FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTZ - { .SVE_FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTA - { .SVE_FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTX - { .SVE_FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FRINTI - { .SVE_FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, - { .SVE_FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_FMLA - { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FMLS - { .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FNMLA - { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_FNMLS - { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_AND_P - { .SVE_AND_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, - // .SVE_BIC_P - { .SVE_BIC_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, - // .SVE_ORR_P - { .SVE_ORR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, - // .SVE_EOR_P - { .SVE_EOR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, - // .SVE_NAND_P - { .SVE_NAND_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, - // .SVE_NOR_P - { .SVE_NOR_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, - // .SVE_ORN_P - { .SVE_ORN_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, - // .SVE_SEL_P - { .SVE_SEL_P, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, - // .SVE_ANDS_P - { .SVE_ANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - // .SVE_BICS_P - { .SVE_BICS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, - // .SVE_ORRS_P - { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, - // .SVE_EORS_P - { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, - // .SVE_NANDS_P - { .SVE_NANDS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, - // .SVE_NORS_P - { .SVE_NORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, - // .SVE_ORNS_P - { .SVE_ORNS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, - // .SVE_NOT_P - { .SVE_NOT_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, - // .SVE_MOV_P - { .SVE_MOV_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .SVE_MOV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, - // .SVE_MOVS_P - { .SVE_MOVS_P, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - // .SVE_PTRUE - { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, - // .SVE_PTRUES - { .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, - // .SVE_PFALSE - { .SVE_PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {} }, - // .SVE_PFIRST - { .SVE_PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {} }, - // .SVE_PNEXT - { .SVE_PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {} }, - // .SVE_BRKA - { .SVE_BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, - // .SVE_BRKB - { .SVE_BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, - // .SVE_BRKAS - { .SVE_BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, - // .SVE_BRKBS - { .SVE_BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, - // .SVE_BRKPA - { .SVE_BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, - // .SVE_BRKPB - { .SVE_BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, - // .SVE_BRKN - { .SVE_BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {} }, - // .SVE_RDFFR - { .SVE_RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {} }, - // .SVE_WRFFR - { .SVE_WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {} }, - // .SVE_SETFFR - { .SVE_SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, - // .SVE_CMPEQ - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPNE - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPGE - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPGT - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPLE - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPLT - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPHI - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPHS - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPLO - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_CMPLS - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - // .SVE_FCMEQ - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - // .SVE_FCMNE - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, - // .SVE_FCMGE - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, - // .SVE_FCMGT - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, - // .SVE_FCMLE - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, - // .SVE_FCMLT - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, - { .SVE_FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, - // .SVE_FCMUO - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, - { .SVE_FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, - // .SVE_DUP_Z - { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, - { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, - // .SVE_INSR - { .SVE_INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .SVE_INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, - { .SVE_INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, - { .SVE_INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, - // .SVE_REV_Z - { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, - // .SVE_REV_P - { .SVE_REV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, - // .SVE_TBL - { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_ZIP1_Z - { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_ZIP2_Z - { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_UZP1_Z - { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_UZP2_Z - { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_TRN1_Z - { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_TRN2_Z - { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_ZIP1_P - { .SVE_ZIP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, - // .SVE_ZIP2_P - { .SVE_ZIP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, - // .SVE_UZP1_P - { .SVE_UZP1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, - // .SVE_UZP2_P - { .SVE_UZP2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, - // .SVE_TRN1_P - { .SVE_TRN1_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, - // .SVE_TRN2_P - { .SVE_TRN2_P, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - // .SVE_CPY_Z - { .SVE_CPY_Z, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, - { .SVE_CPY_Z, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_COMPACT - { .SVE_COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, - { .SVE_COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, - // .SVE_EXT_Z - { .SVE_EXT_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1B - { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1H - { .SVE_LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1W - { .SVE_LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1D - { .SVE_LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_LD1SB - { .SVE_LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1SH - { .SVE_LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, - // .SVE_LD1SW - { .SVE_LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_ST1B - { .SVE_ST1B, {.Z_REG_B,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, - // .SVE_ST1H - { .SVE_ST1H, {.Z_REG_H,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, - // .SVE_ST1W - { .SVE_ST1W, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, - // .SVE_ST1D - { .SVE_ST1D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_LDR_Z - { .SVE_LDR_Z, {.Z_REG_B,.MEM,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, - // .SVE_STR_Z - { .SVE_STR_Z, {.Z_REG_B,.MEM,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDR_P - { .SVE_LDR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, - // .SVE_STR_P - { .SVE_STR_P, {.P_REG,.MEM,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - // .SVE_LDFF1B - { .SVE_LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDFF1H - { .SVE_LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDFF1W - { .SVE_LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDFF1D - { .SVE_LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_WHILEGE - { .SVE_WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILEGT - { .SVE_WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILELE - { .SVE_WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILELT - { .SVE_WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILEHI - { .SVE_WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILEHS - { .SVE_WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILELO - { .SVE_WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_WHILELS - { .SVE_WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - // .SVE_SQRDMLAH - { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_SQRDMLSH - { .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_ADCLB - { .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_ADCLT - { .SVE_ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_SBCLB - { .SVE_SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_SBCLT - { .SVE_SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_TBL2 - { .SVE_TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, - // .SVE_TBX - { .SVE_TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, - // .SVE_AESE - { .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, - // .SVE_AESD - { .SVE_AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, - // .SVE_AESMC - { .SVE_AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {} }, - // .SVE_AESIMC - { .SVE_AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {} }, - // .SVE_BCAX_Z - { .SVE_BCAX_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_XAR_Z - { .SVE_XAR_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_XAR_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_XAR_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .SVE_XAR_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, - // .SVE_EOR3_Z - { .SVE_EOR3_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_MATCH - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - // .SVE_NMATCH - { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - // .SVE_HISTCNT - { .SVE_HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, - { .SVE_HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, - // .SVE_HISTSEG - { .SVE_HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - // .SME_SMSTART - { .SME_SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, - // .SME_SMSTOP - { .SME_SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, - // .SME_RDSVL - { .SME_RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, - // .SME_ADDHA - { .SME_ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, - // .SME_ADDVA - { .SME_ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {} }, - // .SME_ZERO - { .SME_ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {} }, - // .SME_FMOPA - { .SME_FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {} }, - // .SME_FMOPS - { .SME_FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, - // .SME_BFMOPA - { .SME_BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, - // .SME_BFMOPS - { .SME_BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, - // .SME_SMOPA - { .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, - // .SME_SMOPS - { .SME_SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, - { .SME_SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, - // .SME_UMOPA - { .SME_UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, - { .SME_UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - // .SME_UMOPS - { .SME_UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, - { .SME_UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, - // .SME_USMOPA - { .SME_USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, - // .SME_SUMOPA - { .SME_SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - // .SME_LDR_ZA - { .SME_LDR_ZA, {.IMM_5,.MEM,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, - // .SME_STR_ZA - { .SME_STR_ZA, {.IMM_5,.MEM,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, - // .SVE_FMLA_IDX_H - { .SVE_FMLA_IDX_H, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, - // .SVE_FMLA_IDX_S - { .SVE_FMLA_IDX_S, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, - // .SVE_FMLA_IDX_D - { .SVE_FMLA_IDX_D, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_FMLS_IDX_H - { .SVE_FMLS_IDX_H, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, - // .SVE_FMLS_IDX_S - { .SVE_FMLS_IDX_S, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, - // .SVE_FMLS_IDX_D - { .SVE_FMLS_IDX_D, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - // .SVE_LD1B_GATHER_S - { .SVE_LD1B_GATHER_S, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {} }, - // .SVE_LD1B_GATHER_D - { .SVE_LD1B_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1H_GATHER_S - { .SVE_LD1H_GATHER_S, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {} }, - // .SVE_LD1H_GATHER_D - { .SVE_LD1H_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1W_GATHER_S - { .SVE_LD1W_GATHER_S, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {} }, - // .SVE_LD1W_GATHER_D - { .SVE_LD1W_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1D_GATHER_D - { .SVE_LD1D_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1SB_GATHER_S - { .SVE_LD1SB_GATHER_S, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {} }, - // .SVE_LD1SB_GATHER_D - { .SVE_LD1SB_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1SH_GATHER_S - { .SVE_LD1SH_GATHER_S, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {} }, - // .SVE_LD1SH_GATHER_D - { .SVE_LD1SH_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_LD1SW_GATHER_D - { .SVE_LD1SW_GATHER_D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_ST1B_SCATTER_S - { .SVE_ST1B_SCATTER_S, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {} }, - // .SVE_ST1B_SCATTER_D - { .SVE_ST1B_SCATTER_D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_ST1H_SCATTER_S - { .SVE_ST1H_SCATTER_S, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {} }, - // .SVE_ST1H_SCATTER_D - { .SVE_ST1H_SCATTER_D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_ST1W_SCATTER_S - { .SVE_ST1W_SCATTER_S, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {} }, - // .SVE_ST1W_SCATTER_D - { .SVE_ST1W_SCATTER_D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SVE_ST1D_SCATTER_D - { .SVE_ST1D_SCATTER_D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true} }, - // .SME_LD1B_TILE - { .SME_LD1B_TILE, {.SME_SLICE_B,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, - // .SME_LD1H_TILE - { .SME_LD1H_TILE, {.SME_SLICE_H,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {} }, - // .SME_LD1W_TILE - { .SME_LD1W_TILE, {.SME_SLICE_W,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {} }, - // .SME_LD1D_TILE - { .SME_LD1D_TILE, {.SME_SLICE_D,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true} }, - // .SME_LD1Q_TILE - { .SME_LD1Q_TILE, {.SME_SLICE_Q,.P_REG_ZERO,.MEM,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {} }, - // .SME_ST1B_TILE - { .SME_ST1B_TILE, {.SME_SLICE_B,.P_REG,.MEM,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {} }, - // .SME_ST1H_TILE - { .SME_ST1H_TILE, {.SME_SLICE_H,.P_REG,.MEM,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {} }, - // .SME_ST1W_TILE - { .SME_ST1W_TILE, {.SME_SLICE_W,.P_REG,.MEM,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {} }, - // .SME_ST1D_TILE - { .SME_ST1D_TILE, {.SME_SLICE_D,.P_REG,.MEM,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true} }, - // .SME_ST1Q_TILE - { .SME_ST1Q_TILE, {.SME_SLICE_Q,.P_REG,.MEM,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {} }, - // .SME_MOVA_Z_FROM_TILE - { .SME_MOVA_Z_FROM_TILE, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, - // .SME_MOVA_TILE_FROM_Z - { .SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, - // .FCMLA_4H - { .FCMLA_4H, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - // .FCMLA_8H - { .FCMLA_8H, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - // .FCMLA_4S - { .FCMLA_4S, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, - // .FCMLA_2D - { .FCMLA_2D, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, - // .FCADD_4H - { .FCADD_4H, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, - // .FCADD_8H - { .FCADD_8H, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, - // .FCADD_4S - { .FCADD_4S, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - // .FCADD_2D - { .FCADD_2D, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, - // .SVE_PRFB - { .SVE_PRFB, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, - // .SVE_PRFH - { .SVE_PRFH, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, - // .SVE_PRFW - { .SVE_PRFW, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, - // .SVE_PRFD - { .SVE_PRFD, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDNT1B - { .SVE_LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDNT1H - { .SVE_LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDNT1W - { .SVE_LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {} }, - // .SVE_LDNT1D - { .SVE_LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_STNT1B - { .SVE_STNT1B, {.Z_REG_B,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {} }, - // .SVE_STNT1H - { .SVE_STNT1H, {.Z_REG_H,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {} }, - // .SVE_STNT1W - { .SVE_STNT1W, {.Z_REG_S,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {} }, - // .SVE_STNT1D - { .SVE_STNT1D, {.Z_REG_D,.P_REG,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true} }, - // .SVE_EXT - { .SVE_EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, - // .SVE_SPLICE - { .SVE_SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, - // .SVE_INDEX_II - { .SVE_INDEX_II, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, - // .SVE_INDEX_IR - { .SVE_INDEX_IR, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, - // .SVE_INDEX_RI - { .SVE_INDEX_RI, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, - // .SVE_INDEX_RR - { .SVE_INDEX_RR, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, - // .SVE_BSL - { .SVE_BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_BSL1N - { .SVE_BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_BSL2N - { .SVE_BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_NBSL - { .SVE_NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_PMUL_VEC - { .SVE_PMUL_VEC, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - // .SVE_PMULLB - { .SVE_PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_PMULLT - { .SVE_PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - // .SVE_BFCVT - { .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, - // .SVE_BFCVTNT - { .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {} }, + // .SUBR + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, + // .ASRR + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + // .LSLR + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + // .LSRR + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, + // .FTSMUL + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, + // .FSUBR + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, + // .FDIVR + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, + // .FNMLA + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, + // .FNMLS + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, + // .NAND + { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, + // .NOR + { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, + // .SEL + { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, + // .ORRS + { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .EORS + { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .NANDS + { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, + // .NORS + { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, + // .ORNS + { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, + // .MOVS + { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + // .PTRUE + { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, + // .PTRUES + { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, + // .PFALSE + { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {} }, + // .PFIRST + { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {} }, + // .PNEXT + { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {} }, + // .BRKA + { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, + // .BRKB + { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, + // .BRKAS + { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, + // .BRKBS + { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, + // .BRKPA + { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, + // .BRKPB + { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, + // .BRKN + { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {} }, + // .RDFFR + { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {} }, + // .WRFFR + { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {} }, + // .SETFFR + { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, + // .CMPEQ + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + // .CMPNE + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPGE + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPGT + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPLE + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPLT + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPHI + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPHS + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPLO + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .CMPLS + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + // .FCMNE + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, + // .FCMUO + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, + // .INSR + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + // .CPY + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, + // .COMPACT + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, + // .LD1B + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, + { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, + { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, + // .LD1H + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {} }, + { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, + { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, + // .LD1W + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {} }, + { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, + { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, + // .LD1D + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true} }, + { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, + // .LD1SB + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true} }, + // .LD1SH + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true} }, + // .LD1SW + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true} }, + // .ST1B + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {} }, + { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, + { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, + // .ST1H + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {} }, + { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, + { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {} }, + // .ST1W + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {} }, + { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {} }, + { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {} }, + // .ST1D + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true} }, + { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true} }, + { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true} }, + // .LDFF1B + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {} }, + // .LDFF1H + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, + // .LDFF1W + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, + // .LDFF1D + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, + // .WHILEGE + { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILEGT + { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILELE + { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILELT + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILEHI + { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILEHS + { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILELO + { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .WHILELS + { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + // .SQRDMLAH + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .SQRDMLSH + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .ADCLB + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .ADCLT + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .SBCLB + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .SBCLT + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .TBL2 + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, + // .MATCH + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + // .NMATCH + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + // .HISTCNT + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, + // .HISTSEG + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, + // .SMSTART + { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, + // .SMSTOP + { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, + // .RDSVL + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + // .ADDHA + { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, + // .ADDVA + { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {} }, + // .ZERO + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {} }, + // .FMOPA + { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {} }, + // .FMOPS + { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, + // .BFMOPA + { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, + // .BFMOPS + { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, + // .SMOPA + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, + // .SMOPS + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, + // .UMOPA + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, + // .UMOPS + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, + // .USMOPA + { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, + // .SUMOPA + { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, + // .LD1Q + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {} }, + // .ST1Q + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {} }, + // .MOVA + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, + // .FCMLA + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, + // .FCADD + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, + // .PRFB + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, + // .PRFH + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, + // .PRFW + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, + // .PRFD + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {} }, + // .LDNT1B + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {} }, + // .LDNT1H + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {} }, + // .LDNT1W + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {} }, + // .LDNT1D + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true} }, + // .STNT1B + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {} }, + // .STNT1H + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {} }, + // .STNT1W + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {} }, + // .STNT1D + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true} }, + // .SPLICE + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, + // .INDEX + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, + // .BSL1N + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .BSL2N + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .NBSL + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .PMUL + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, + // .PMULLB + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .PMULLT + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + // .BFCVTNT + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, // .LDRAA - { .LDRAA, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true} }, // .LDRAB - { .LDRAB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true} }, - // .LDRAA_PRE - { .LDRAA_PRE, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true} }, - // .LDRAB_PRE - { .LDRAB_PRE, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true} }, // .TSTART { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true} }, // .TCOMMIT @@ -3227,37 +2980,40 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, // .LDAPUR - { .LDAPUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, - { .LDAPUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, + { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, // .STLUR - { .STLUR, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} }, - { .STLUR, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} }, + { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} }, + { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} }, // .LDAPURB - { .LDAPURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} }, + { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} }, // .STLURB - { .STLURB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {} }, + { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {} }, // .LDAPURH - { .LDAPURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {} }, + { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {} }, // .STLURH - { .STLURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {} }, + { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {} }, // .LDAPURSB - { .LDAPURSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDAPURSB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {} }, // .LDAPURSH - { .LDAPURSH, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDAPURSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, // .LDAPURSW - { .LDAPURSW, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, - // .SVE_BFADD - { .SVE_BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {} }, - // .SVE_BFSUB - { .SVE_BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {} }, - // .SVE_BFMUL - { .SVE_BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {} }, - // .SVE_BFMLA - { .SVE_BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {} }, - // .SVE_BFMLS - { .SVE_BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {} }, + { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, + // .BFADD + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, + // .BFSUB + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, + // .BFMUL + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, + // .BFMLA + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {} }, + // .BFMLS + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {} }, // .SB { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, // .CSDB @@ -3274,80 +3030,22 @@ ENCODE_FORMS := [2440]lib.Encoding{ { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, - // .MOV_V_ALIAS - { .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - // .NOT_V_ALIAS - { .NOT_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - // .LSL_IMM - { .LSL_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, - { .LSL_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, - // .LSR_IMM - { .LSR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .LSR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - // .ASR_IMM - { .ASR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - // .ROR_IMM - { .ROR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, - { .ROR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, - // .SVE_BFADD_UNPRED - { .SVE_BFADD_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, - // .SVE_BFSUB_UNPRED - { .SVE_BFSUB_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, - // .SVE_BFMUL_UNPRED - { .SVE_BFMUL_UNPRED, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, - // .SVE_BFCLAMP - { .SVE_BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, - // .SVE_BFMAXNM - { .SVE_BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {} }, - // .SVE_BFMINNM - { .SVE_BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {} }, - // .SME2_LUTI2_B - { .SME2_LUTI2_B, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {} }, - // .SME2_LUTI4_B - { .SME2_LUTI4_B, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, - // .SME2_LD1B_X2 - { .SME2_LD1B_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1H_X2 - { .SME2_LD1H_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1W_X2 - { .SME2_LD1W_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1D_X2 - { .SME2_LD1D_X2, {.Z_PAIR,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, - // .SME2_LD1B_X4 - { .SME2_LD1B_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1H_X4 - { .SME2_LD1H_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1W_X4 - { .SME2_LD1W_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - // .SME2_LD1D_X4 - { .SME2_LD1D_X4, {.Z_QUAD,.P_REG_ZERO,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, - // .SME2_ST1B_X2 - { .SME2_ST1B_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1H_X2 - { .SME2_ST1H_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1W_X2 - { .SME2_ST1W_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1D_X2 - { .SME2_ST1D_X2, {.Z_PAIR,.P_REG,.MEM,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true} }, - // .SME2_ST1B_X4 - { .SME2_ST1B_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1H_X4 - { .SME2_ST1H_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1W_X4 - { .SME2_ST1W_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {} }, - // .SME2_ST1D_X4 - { .SME2_ST1D_X4, {.Z_QUAD,.P_REG,.MEM,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true} }, - // .SME2_ZIP_3 - { .SME2_ZIP_3, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {} }, - // .SME2_ZIP_4 - { .SME2_ZIP_4, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {} }, - // .SME2_UZP_3 - { .SME2_UZP_3, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {} }, - // .SME2_UZP_4 - { .SME2_UZP_4, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {} }, + // .BFCLAMP + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, + // .BFMAXNM + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {} }, + // .BFMINNM + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {} }, + // .LUTI2 + { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {} }, + // .LUTI4 + { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, + // .ZIP + { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {} }, + { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {} }, + // .UZP + { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {} }, + { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {} }, // .TLBI_RPALOS { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true} }, // .TLBI_RPAOS @@ -3511,63 +3209,86 @@ ENCODE_FORMS := [2440]lib.Encoding{ // .TLBI_ALLE3IS { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, // .PRFM - { .PRFM, {.IMM_5,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true} }, // .PRFUM - { .PRFUM, {.IMM_5,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true} }, - // .PRFM_LIT - { .PRFM_LIT, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true} }, - // .MOV_REG - { .MOV_REG, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .MOV_REG, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - // .MOV_BITMASK - { .MOV_BITMASK, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, - { .MOV_BITMASK, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, - // .MVN - { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, - { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - // .NEG_SR - { .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true} }, // .NEGS { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, - // .CMP_SR - { .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - // .CMP_ER - { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - // .CMP_IMM - { .CMP_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMP_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - // .CMN_SR - { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - // .CMN_ER - { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - // .CMN_IMM - { .CMN_IMM, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMN_IMM, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - // .TST_SR - { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + // .CMP + { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + // .CMN + { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, } @(rodata) -CLOBBER_FORMS := [2440]lib.Clobber{ - // .ADD_IMM +CLOBBER_FORMS := [2436]lib.Clobber{ + // .ADD {written={0}, read={1}}, {written={0}, read={1}}, - // .ADDS_IMM + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .ADDS {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - // .SUB_IMM + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + // .SUB {written={0}, read={1}}, {written={0}, read={1}}, - // .SUBS_IMM + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .SUBS {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .MOVZ {written={0}}, {written={0}}, @@ -3581,72 +3302,96 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}}, // .ADRP {written={0}}, - // .ADD_SR + // .AND {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .ADDS_SR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .ANDS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SUB_SR + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .ORR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SUBS_SR + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .EOR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .BIC + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .BICS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .AND_SR + {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, + // .ORN {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .ANDS_SR - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .ORR_SR + {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + // .EON {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .EOR_SR + // .LSL {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .BIC_SR + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .LSR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .BICS_SR - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .ORN_SR + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ASR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .EON_SR - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .ADD_ER - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .ADDS_ER - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SUB_ER - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SUBS_ER - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .LSLV - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .LSRV - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .ASRV - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .RORV + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ROR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .UDIV {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .SDIV {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .MADD {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, @@ -3663,25 +3408,66 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2, 3}}, // .SMULH {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .UMULH {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .CLZ {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .CLS {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .RBIT {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .REV {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .REV16 {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .REV32 {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .CSEL {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, @@ -3694,16 +3480,14 @@ CLOBBER_FORMS := [2440]lib.Clobber{ // .CSNEG {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - // .CCMP_REG + // .CCMP {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - // .CCMP_IMM {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - // .CCMN_REG + // .CCMN {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, - // .CCMN_IMM {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, // .EXTR @@ -3735,36 +3519,96 @@ CLOBBER_FORMS := [2440]lib.Clobber{ // .LDR {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, + {written={0}}, + {written={0}}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {read={1}, reads_mem=true}, // .STR {read={0, 1}, writes_mem=true}, {read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={1}, writes_mem=true}, // .LDRB {written={0}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .STRB {read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .LDRSB {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .LDRH {written={0}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .STRH {read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {written={1}, read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .LDRSH {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .LDRSW {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .LDP {written={0, 1}, read={2}, reads_mem=true}, {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, + {written={0, 1}, read={2}, reads_mem=true}, // .STP {read={0, 1, 2}, writes_mem=true}, {read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + {written={2}, read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, // .LDPSW {written={0, 1}, read={2}, reads_mem=true}, - // .LDR_LIT - {written={0}}, - {written={0}}, + {written={0, 1, 2}, read={2}, reads_mem=true}, + {written={0, 1, 2}, read={2}, reads_mem=true}, // .LDAR {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, @@ -3807,9 +3651,8 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {side_effects={.HINT}}, // .MRS {written={0}, read={1}, side_effects={.PRIVILEGED}}, - // .MSR_IMM + // .MSR {side_effects={.PRIVILEGED}}, - // .MSR_REG {written={0}, read={1}, side_effects={.PRIVILEGED}}, // .ISB {side_effects={.ISYNC}}, @@ -3829,98 +3672,238 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {side_effects={.CONTROL, .TRAP}}, // .ERET {side_effects={.CONTROL, .PRIVILEGED}}, - // .FMOV_REG + // .FMOV {written={0}, read={1}}, {written={0}, read={1}}, - // .FMOV_IMM {written={0}}, {written={0}}, {written={0}}, - // .FMOV_GEN {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, // .FABS {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .FNEG {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .FSQRT {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, // .FADD {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FSUB {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FMUL {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FDIV {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FNMUL {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FMADD {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FMSUB {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FNMADD {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FNMSUB {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FCMP {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, // .FCMPE {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, // .FCSEL {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, // .FMAX {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, // .FMIN {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, // .FMAXNM {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, // .FMINNM {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, // .FCVT {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .SCVTF {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, // .UCVTF {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, // .FCVTZS {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTZU {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTAS {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3928,6 +3911,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTAU {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3935,6 +3923,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTNS {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3942,6 +3935,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTNU {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3949,6 +3947,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTPS {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3956,6 +3959,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTPU {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3963,6 +3971,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTMS {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3970,6 +3983,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTMU {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, @@ -3977,55 +3995,112 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FRINTA {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FRINTI {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, // .FRINTM {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FRINTN {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FRINTP {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FRINTX {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, // .FRINTZ {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, - // .AND_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .ANDS_IMM - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - // .ORR_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .EOR_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .TST_IMM + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + // .TST {read={0}, nzcv_wr={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, + {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, // .LDUR {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .STUR {read={0, 1}, writes_mem=true}, {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .LDURB {written={0}, read={1}, reads_mem=true}, // .STURB @@ -4042,72 +4117,6 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, reads_mem=true}, // .LDURSW {written={0}, read={1}, reads_mem=true}, - // .LDR_PRE - {written={0, 1}, read={1}, reads_mem=true}, - {written={0, 1}, read={1}, reads_mem=true}, - // .STR_PRE - {written={1}, read={0, 1}, writes_mem=true}, - {written={1}, read={0, 1}, writes_mem=true}, - // .LDR_POST - {written={0, 1}, read={1}, reads_mem=true}, - {written={0, 1}, read={1}, reads_mem=true}, - // .STR_POST - {written={1}, read={0, 1}, writes_mem=true}, - {written={1}, read={0, 1}, writes_mem=true}, - // .LDRB_PRE - {written={0, 1}, read={1}, reads_mem=true}, - // .STRB_PRE - {written={1}, read={0, 1}, writes_mem=true}, - // .LDRB_POST - {written={0, 1}, read={1}, reads_mem=true}, - // .STRB_POST - {written={1}, read={0, 1}, writes_mem=true}, - // .LDRH_PRE - {written={0, 1}, read={1}, reads_mem=true}, - // .STRH_PRE - {written={1}, read={0, 1}, writes_mem=true}, - // .LDRH_POST - {written={0, 1}, read={1}, reads_mem=true}, - // .STRH_POST - {written={1}, read={0, 1}, writes_mem=true}, - // .LDR_REG - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - // .STR_REG - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - // .LDRB_REG - {written={0}, read={1}, reads_mem=true}, - // .STRB_REG - {read={0, 1}, writes_mem=true}, - // .LDRH_REG - {written={0}, read={1}, reads_mem=true}, - // .STRH_REG - {read={0, 1}, writes_mem=true}, - // .LDRSB_REG - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - // .LDRSH_REG - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - // .LDRSW_REG - {written={0}, read={1}, reads_mem=true}, - // .LDP_PRE - {written={0, 1, 2}, read={2}, reads_mem=true}, - {written={0, 1, 2}, read={2}, reads_mem=true}, - // .STP_PRE - {written={2}, read={0, 1, 2}, writes_mem=true}, - {written={2}, read={0, 1, 2}, writes_mem=true}, - // .LDP_POST - {written={0, 1, 2}, read={2}, reads_mem=true}, - {written={0, 1, 2}, read={2}, reads_mem=true}, - // .STP_POST - {written={2}, read={0, 1, 2}, writes_mem=true}, - {written={2}, read={0, 1, 2}, writes_mem=true}, - // .LDPSW_PRE - {written={0, 1, 2}, read={2}, reads_mem=true}, - // .LDPSW_POST - {written={0, 1, 2}, read={2}, reads_mem=true}, // .LDNP {written={0, 1}, read={2}, reads_mem=true}, {written={0, 1}, read={2}, reads_mem=true}, @@ -4427,12 +4436,16 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, // .AESE {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, // .AESD {written={0}, read={0, 1}}, + {written={0}, read={0, 1}}, // .AESMC {written={0}, read={0, 1}}, + {written={0}, read={0}}, // .AESIMC {written={0}, read={0, 1}}, + {written={0}, read={0}}, // .SHA1H {written={0}, read={1}}, // .SHA1C @@ -4463,12 +4476,18 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={0, 1, 2}}, // .EOR3 {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .BCAX {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .RAX1 {written={0}, read={1, 2}}, // .XAR {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .SM3PARTW1 {written={0}, read={0, 1, 2}}, // .SM3PARTW2 @@ -4493,64 +4512,9 @@ CLOBBER_FORMS := [2440]lib.Clobber{ // .PMULL2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .FABS_H - {written={0}, read={1}}, - // .FNEG_H - {written={0}, read={1}}, - // .FSQRT_H - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - // .FADD_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FSUB_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMUL_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FDIV_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FNMUL_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMADD_H - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMSUB_H - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FNMADD_H - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FNMSUB_H - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCMP_H - {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - // .FCMPE_H - {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}, - // .FCSEL_H - {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}, - // .FMAX_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMIN_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMAXNM_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMINNM_H - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FCVT_H_S - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCVT_H_D - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCVT_S_H - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCVT_D_H - {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMOV_H - {written={0}, read={1}}, - // .SCVTF_H - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - // .UCVTF_H - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - // .FCVTZS_H - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTZU_H - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .BFCVT {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .BFDOT {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .BFMMLA @@ -4563,38 +4527,29 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .BFCVTN2 {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .ADD_V + // .MUL {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SUB_V - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .MUL_V - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .MLA_V + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + // .MLA {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, - // .MLS_V + // .MLS {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, - // .NEG_V + // .NEG {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -4602,7 +4557,13 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, - // .ABS_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + // .ABS {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -4610,6 +4571,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .SHADD {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4660,6 +4625,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, // .UQADD {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, @@ -4668,6 +4637,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, // .SQSUB {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, @@ -4676,6 +4649,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, // .UQSUB {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, @@ -4684,6 +4661,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, + {written={0}, read={1, 2}, fpsr_wr={.QC}}, // .SMAX {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4691,6 +4672,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .UMAX {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4698,6 +4683,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .SMIN {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4705,6 +4694,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .UMIN {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4712,6 +4705,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .SABD {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4719,6 +4716,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .UABD {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4726,6 +4727,10 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .SABA {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, @@ -4740,7 +4745,7 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, - // .ADDP_V + // .ADDP {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -4974,19 +4979,19 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, - // .SMULL_V + // .SMULL {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SMULL2_V + // .SMULL2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .UMULL_V + // .UMULL {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .UMULL2_V + // .UMULL2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5059,44 +5064,22 @@ CLOBBER_FORMS := [2440]lib.Clobber{ // .USDOT {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, - // .FADD_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FSUB_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMUL_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FDIV_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FNEG_V - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - // .FABS_V - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - // .FSQRT_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - // .FMLA_V + // .FMLA {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMLS_V + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .FMLS + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FMULX @@ -5105,37 +5088,13 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FMAX_V + // .FMAXP {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMIN_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMAXNM_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMINNM_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMAXP_V - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMINP_V + // .FMINP {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, @@ -5153,11 +5112,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMAXV_V + // .FMAXV {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .FMINV_V + // .FMINV {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, @@ -5187,136 +5146,31 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FRSQRTS {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .FRECPX {written={0}, read={1}, reads_fpcr=true}, {written={0}, read={1}, reads_fpcr=true}, {written={0}, read={1}, reads_fpcr=true}, - // .FADDP_V + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + {written={0}, read={1, 2}, reads_fpcr=true}, + // .FADDP {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FRINTA_V - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - // .FRINTI_V - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}, - // .FRINTM_V - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - // .FRINTN_V - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - // .FRINTP_V - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - // .FRINTX_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - // .FRINTZ_V - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - {written={0}, read={1}, fpsr_wr={.IOC}}, - // .SCVTF_V - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - // .UCVTF_V - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}, - // .FCVTAS_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTAU_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTMS_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTMU_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTNS_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTNU_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTPS_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTPU_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTZS_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - // .FCVTZU_V - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, - {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}, // .FCVTL {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, @@ -5339,30 +5193,45 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, // .FCMGE {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, // .FCMGT {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, // .FCMLE {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FCMLT {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, {written={0}, read={1}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, + {written={0}, read={1, 2}, fpsr_wr={.IOC}}, // .FACGE {written={0}, read={1, 2}, fpsr_wr={.IOC}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}, @@ -5426,17 +5295,9 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .AND_V - {written={0}, read={1, 2}}, - // .ORR_V - {written={0}, read={1, 2}}, - // .EOR_V - {written={0}, read={1, 2}}, - // .BIC_V - {written={0}, read={1, 2}}, - // .ORN_V - {written={0}, read={1, 2}}, - // .MVN_V + // .MVN + {written={0}, read={1}}, + {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, // .BIT @@ -5445,7 +5306,8 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={0, 1, 2}}, // .BSL {written={0}, read={0, 1, 2}}, - // .SHL_V + {written={0}, read={0, 1, 2, 3}}, + // .SHL {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -5453,7 +5315,7 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, - // .SQSHL_V + // .SQSHL {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, @@ -5677,7 +5539,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, {written={0}, read={1}, fpsr_wr={.QC}}, - // .DUP_V + // .DUP + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, @@ -5701,18 +5567,35 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={0, 2}}, {written={0}, read={0, 2}}, {written={0}, read={0, 2}}, - // .MOV_V + // .MOV {written={0}, read={1}}, {written={0}, read={1}}, - // .EXT_V + {read={0, 1, 2}}, + {read={0, 1, 2}}, + {read={0, 1, 2}}, + {read={0, 1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}}, + {written={0}}, + // .EXT + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, // .TBL {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .TBX {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, + {written={0}, read={0, 1, 2}}, // .ZIP1 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5721,6 +5604,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .ZIP2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5729,6 +5617,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .UZP1 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5737,6 +5630,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .UZP2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5745,6 +5643,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .TRN1 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5753,6 +5656,11 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .TRN2 {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -5761,20 +5669,15 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .NOT_V - {written={0}, read={1}}, - {written={0}, read={1}}, - // .RBIT_V - {written={0}, read={1}}, - {written={0}, read={1}}, - // .REV16_V - {written={0}, read={1}}, - {written={0}, read={1}}, - // .REV32_V - {written={0}, read={1}}, - {written={0}, read={1}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .NOT {written={0}, read={1}}, {written={0}, read={1}}, + {written={0}, read={1, 2}}, // .REV64 {written={0}, read={1}}, {written={0}, read={1}}, @@ -5782,27 +5685,17 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, - // .CLS_V - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - // .CLZ_V - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, // .CNT {written={0}, read={1}}, {written={0}, read={1}}, - // .URECPE_V + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + // .URECPE {written={0}, read={1}}, {written={0}, read={1}}, - // .URSQRTE_V + // .URSQRTE {written={0}, read={1}}, {written={0}, read={1}}, // .MOVI @@ -5818,34 +5711,60 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}}, {written={0}}, {written={0}}, - // .FMOV_V_IMM - {written={0}}, - {written={0}}, - {written={0}}, - {written={0}}, - {written={0}}, // .LD1 {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, {written={0}, read={1}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, // .LD2 {written={0}, read={1}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, // .LD3 {written={0}, read={1}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, // .LD4 {written={0}, read={1}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, + {written={0}, read={2}, reads_mem=true}, // .ST1 {read={0, 1}, writes_mem=true}, {read={0, 1}, writes_mem=true}, {read={0, 1}, writes_mem=true}, {read={0, 1}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, // .ST2 {read={0, 1}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, // .ST3 {read={0, 1}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, // .ST4 {read={0, 1}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, + {read={0, 2}, writes_mem=true}, // .LD1R {written={0}, read={1}, reads_mem=true}, // .LD2R @@ -5854,880 +5773,392 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, reads_mem=true}, // .LD4R {written={0}, read={1}, reads_mem=true}, - // .LD1_LANE - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - // .LD2_LANE - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - // .LD3_LANE - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - // .LD4_LANE - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - {written={0}, read={2}, reads_mem=true}, - // .ST1_LANE - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - // .ST2_LANE - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - // .ST3_LANE - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - // .ST4_LANE - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - {read={0, 2}, writes_mem=true}, - // .LDR_V - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - // .STR_V - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - // .LDP_V - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - {written={0, 1}, read={2}, reads_mem=true}, - // .STP_V - {read={0, 1, 2}, writes_mem=true}, - {read={0, 1, 2}, writes_mem=true}, - {read={0, 1, 2}, writes_mem=true}, - // .LDUR_V - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - // .STUR_V - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - // .SVE_ADD_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_SUB_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_SQADD_Z - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - // .SVE_UQADD_Z - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - // .SVE_SQSUB_Z - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - // .SVE_UQSUB_Z - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - {written={0}, read={1, 2}, fpsr_wr={.QC}}, - // .SVE_ADD_PRED + // .SUBR {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, - // .SVE_SUB_PRED + // .ASRR {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, - // .SVE_SUBR_PRED + // .LSLR {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, - // .SVE_MUL_PRED + // .LSRR {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, - // .SVE_SMULH_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_UMULH_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_SDIV_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_UDIV_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_SMAX_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_UMAX_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_SMIN_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_UMIN_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_SABD_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_UABD_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_AND_PRED - {written={0}, read={1, 2, 3}}, - // .SVE_ORR_PRED - {written={0}, read={1, 2, 3}}, - // .SVE_EOR_PRED - {written={0}, read={1, 2, 3}}, - // .SVE_BIC_PRED - {written={0}, read={1, 2, 3}}, - // .SVE_ASR_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_LSL_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_LSR_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_ASRR_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_LSLR_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_LSRR_PRED - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - {written={0}, read={1, 2, 3}}, - // .SVE_ABS_PRED - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_NEG_PRED - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_CLS_PRED - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_CLZ_PRED - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_CNT_PRED - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_MOV_PRED - {read={0, 1, 2}}, - {read={0, 1, 2}}, - {read={0, 1, 2}}, - {read={0, 1, 2}}, - // .SVE_FADD_Z + // .FTSMUL {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FSUB_Z - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMUL_Z - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FRECPS - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FRSQRTS - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FTSMUL - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FADD_PRED + // .FSUBR {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FSUB_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FSUBR_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMUL_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FDIV_PRED + // .FDIVR {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FDIVR_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMAX_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .SVE_FMIN_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .SVE_FMAXNM_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .SVE_FMINNM_PRED - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}, - // .SVE_FABS_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_FNEG_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_FSQRT_Z - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FRECPX_Z - {written={0}, read={1, 2}, reads_fpcr=true}, - {written={0}, read={1, 2}, reads_fpcr=true}, - {written={0}, read={1, 2}, reads_fpcr=true}, - // .SVE_FRINTN - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FRINTP - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FRINTM - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FRINTZ - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FRINTA - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FRINTX - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}, - // .SVE_FRINTI - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}, - // .SVE_FMLA - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLS - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FNMLA + // .FNMLA {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SVE_FNMLS + // .FNMLS {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SVE_AND_P + // .NAND {written={0}, read={1, 2, 3}}, - // .SVE_BIC_P + // .NOR {written={0}, read={1, 2, 3}}, - // .SVE_ORR_P + // .SEL {written={0}, read={1, 2, 3}}, - // .SVE_EOR_P - {written={0}, read={1, 2, 3}}, - // .SVE_NAND_P - {written={0}, read={1, 2, 3}}, - // .SVE_NOR_P - {written={0}, read={1, 2, 3}}, - // .SVE_ORN_P - {written={0}, read={1, 2, 3}}, - // .SVE_SEL_P - {written={0}, read={1, 2, 3}}, - // .SVE_ANDS_P + // .ORRS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_BICS_P + // .EORS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_ORRS_P + // .NANDS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_EORS_P + // .NORS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_NANDS_P + // .ORNS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_NORS_P - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_ORNS_P - {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_NOT_P - {written={0}, read={1, 2}}, - // .SVE_MOV_P - {written={0}, read={1, 2}}, - {written={0}, read={1}}, - // .SVE_MOVS_P + // .MOVS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_PTRUE + // .PTRUE {written={0}}, - // .SVE_PTRUES + // .PTRUES {written={0}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_PFALSE + // .PFALSE {written={0}}, - // .SVE_PFIRST + // .PFIRST {written={0}, read={1, 2}}, - // .SVE_PNEXT + // .PNEXT {written={0}, read={1, 2}}, - // .SVE_BRKA + // .BRKA {written={0}, read={1, 2}}, - // .SVE_BRKB + // .BRKB {written={0}, read={1, 2}}, - // .SVE_BRKAS + // .BRKAS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_BRKBS + // .BRKBS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_BRKPA + // .BRKPA {written={0}, read={1, 2, 3}}, - // .SVE_BRKPB + // .BRKPB {written={0}, read={1, 2, 3}}, - // .SVE_BRKN + // .BRKN {written={0}, read={1, 2, 3}}, - // .SVE_RDFFR + // .RDFFR {written={0}, side_effects={.FFR}}, - // .SVE_WRFFR + // .WRFFR {read={0}, side_effects={.FFR}}, - // .SVE_SETFFR + // .SETFFR {side_effects={.FFR}}, - // .SVE_CMPEQ + // .CMPEQ {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPNE + // .CMPNE {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPGE + // .CMPGE {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPGT + // .CMPGT {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPLE + // .CMPLE {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPLT + // .CMPLT {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPHI + // .CMPHI {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPHS + // .CMPHS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPLO + // .CMPLO {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_CMPLS + // .CMPLS {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_FCMEQ + // .FCMNE {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - // .SVE_FCMNE + // .FCMUO {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - // .SVE_FCMGE - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - // .SVE_FCMGT - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - // .SVE_FCMLE - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FCMLT - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2}, fpsr_wr={.IOC}}, - // .SVE_FCMUO - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}, - // .SVE_DUP_Z + // .INSR {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, {written={0}, read={1}}, - // .SVE_INSR - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - // .SVE_REV_Z - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - // .SVE_REV_P - {written={0}, read={1}}, - // .SVE_TBL + // .CPY {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SVE_ZIP1_Z + // .COMPACT {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_ZIP2_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_UZP1_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_UZP2_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_TRN1_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_TRN2_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_ZIP1_P - {written={0}, read={1, 2}}, - // .SVE_ZIP2_P - {written={0}, read={1, 2}}, - // .SVE_UZP1_P - {written={0}, read={1, 2}}, - // .SVE_UZP2_P - {written={0}, read={1, 2}}, - // .SVE_TRN1_P - {written={0}, read={1, 2}}, - // .SVE_TRN2_P - {written={0}, read={1, 2}}, - // .SVE_CPY_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_COMPACT - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_EXT_Z - {written={0}, read={1, 2}}, - // .SVE_LD1B + // .LD1B {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1H {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1W {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1D {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SB {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SH {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SW + // .LD1H {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_ST1B + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .LD1W + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .LD1D + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .LD1SB + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .LD1SH + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .LD1SW + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + // .ST1B {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1H {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1W {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1D {read={0, 1, 2}, writes_mem=true}, - // .SVE_LDR_Z - {written={0}, read={1}, reads_mem=true}, - // .SVE_STR_Z - {read={0, 1}, writes_mem=true}, - // .SVE_LDR_P - {written={0}, read={1}, reads_mem=true}, - // .SVE_STR_P - {read={0, 1}, writes_mem=true}, - // .SVE_LDFF1B + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .ST1H + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .ST1W + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .ST1D + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, + // .LDFF1B {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, - // .SVE_LDFF1H + // .LDFF1H {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, - // .SVE_LDFF1W + // .LDFF1W {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, - // .SVE_LDFF1D + // .LDFF1D {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, - // .SVE_WHILEGE + // .WHILEGE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILEGT + // .WHILEGT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILELE + // .WHILELE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILELT + // .WHILELT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILEHI + // .WHILEHI {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILEHS + // .WHILEHS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILELO + // .WHILELO {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_WHILELS + // .WHILELS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_SQRDMLAH + // .SQRDMLAH {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - // .SVE_SQRDMLSH + // .SQRDMLSH {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, - // .SVE_ADCLB + // .ADCLB {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SVE_ADCLT + // .ADCLT {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SVE_SBCLB + // .SBCLB {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SVE_SBCLT + // .SBCLT {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .SVE_TBL2 + // .TBL2 {written={0}, read={1, 2}}, - // .SVE_TBX - {written={0}, read={0, 1, 2}}, - // .SVE_AESE - {written={0}, read={0, 1}}, - // .SVE_AESD - {written={0}, read={0, 1}}, - // .SVE_AESMC - {written={0}, read={0}}, - // .SVE_AESIMC - {written={0}, read={0}}, - // .SVE_BCAX_Z - {written={0}, read={1, 2, 3}}, - // .SVE_XAR_Z - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - // .SVE_EOR3_Z - {written={0}, read={1, 2, 3}}, - // .SVE_MATCH + // .MATCH {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_NMATCH + // .NMATCH {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, - // .SVE_HISTCNT + // .HISTCNT {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, - // .SVE_HISTSEG + // .HISTSEG {written={0}, read={1, 2}}, - // .SME_SMSTART + // .SMSTART {}, - // .SME_SMSTOP + // .SMSTOP {}, - // .SME_RDSVL + // .RDSVL {written={0}}, - // .SME_ADDHA + // .ADDHA {written={0}, read={0, 1, 2, 3}}, - // .SME_ADDVA + // .ADDVA {written={0}, read={0, 1, 2, 3}}, - // .SME_ZERO + // .ZERO {}, - // .SME_FMOPA + // .FMOPA {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SME_FMOPS + // .FMOPS {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SME_BFMOPA + // .BFMOPA {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SME_BFMOPS + // .BFMOPS {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SME_SMOPA + // .SMOPA {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SME_SMOPS + // .SMOPS {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SME_UMOPA + // .UMOPA {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SME_UMOPS + // .UMOPS {written={0}, read={0, 1, 2, 3}}, {written={0}, read={0, 1, 2, 3}}, - // .SME_USMOPA + // .USMOPA {written={0}, read={0, 1, 2, 3}}, - // .SME_SUMOPA + // .SUMOPA {written={0}, read={0, 1, 2, 3}}, - // .SME_LDR_ZA - {read={1}, reads_mem=true}, - // .SME_STR_ZA - {read={1}, writes_mem=true}, - // .SVE_FMLA_IDX_H - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLA_IDX_S - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLA_IDX_D - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLS_IDX_H - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLS_IDX_S - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_FMLS_IDX_D - {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_LD1B_GATHER_S + // .LD1Q {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1B_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1H_GATHER_S - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1H_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1W_GATHER_S - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1W_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1D_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SB_GATHER_S - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SB_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SH_GATHER_S - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SH_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LD1SW_GATHER_D - {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_ST1B_SCATTER_S + // .ST1Q {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1B_SCATTER_D - {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1H_SCATTER_S - {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1H_SCATTER_D - {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1W_SCATTER_S - {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1W_SCATTER_D - {read={0, 1, 2}, writes_mem=true}, - // .SVE_ST1D_SCATTER_D - {read={0, 1, 2}, writes_mem=true}, - // .SME_LD1B_TILE - {written={0}, read={1, 2}, reads_mem=true}, - // .SME_LD1H_TILE - {written={0}, read={1, 2}, reads_mem=true}, - // .SME_LD1W_TILE - {written={0}, read={1, 2}, reads_mem=true}, - // .SME_LD1D_TILE - {written={0}, read={1, 2}, reads_mem=true}, - // .SME_LD1Q_TILE - {written={0}, read={1, 2}, reads_mem=true}, - // .SME_ST1B_TILE - {read={0, 1, 2}, writes_mem=true}, - // .SME_ST1H_TILE - {read={0, 1, 2}, writes_mem=true}, - // .SME_ST1W_TILE - {read={0, 1, 2}, writes_mem=true}, - // .SME_ST1D_TILE - {read={0, 1, 2}, writes_mem=true}, - // .SME_ST1Q_TILE - {read={0, 1, 2}, writes_mem=true}, - // .SME_MOVA_Z_FROM_TILE + // .MOVA {written={0}, read={1, 2}}, - // .SME_MOVA_TILE_FROM_Z {written={0}, read={1, 2}}, - // .FCMLA_4H + // .FCMLA {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCMLA_8H {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCMLA_4S {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCMLA_2D {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCADD_4H + // .FCADD {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCADD_8H {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCADD_4S {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .FCADD_2D {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_PRFB + // .PRFB {read={1, 2}, side_effects={.HINT}}, - // .SVE_PRFH + // .PRFH {read={1, 2}, side_effects={.HINT}}, - // .SVE_PRFW + // .PRFW {read={1, 2}, side_effects={.HINT}}, - // .SVE_PRFD + // .PRFD {read={1, 2}, side_effects={.HINT}}, - // .SVE_LDNT1B + // .LDNT1B {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LDNT1H + // .LDNT1H {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LDNT1W + // .LDNT1W {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_LDNT1D + // .LDNT1D {written={0}, read={1, 2}, reads_mem=true}, - // .SVE_STNT1B + // .STNT1B {read={0, 1, 2}, writes_mem=true}, - // .SVE_STNT1H + // .STNT1H {read={0, 1, 2}, writes_mem=true}, - // .SVE_STNT1W + // .STNT1W {read={0, 1, 2}, writes_mem=true}, - // .SVE_STNT1D + // .STNT1D {read={0, 1, 2}, writes_mem=true}, - // .SVE_EXT - {written={0}, read={1, 2}}, - // .SVE_SPLICE + // .SPLICE {written={0}, read={1, 2, 3}}, - // .SVE_INDEX_II + // .INDEX {written={0}}, - // .SVE_INDEX_IR {written={0}, read={2}}, - // .SVE_INDEX_RI {written={0}, read={1}}, - // .SVE_INDEX_RR {written={0}, read={1, 2}}, - // .SVE_BSL - {written={0}, read={0, 1, 2, 3}}, - // .SVE_BSL1N + // .BSL1N {written={0}, read={1, 2, 3}}, - // .SVE_BSL2N + // .BSL2N {written={0}, read={1, 2, 3}}, - // .SVE_NBSL + // .NBSL {written={0}, read={1, 2, 3}}, - // .SVE_PMUL_VEC + // .PMUL {written={0}, read={1, 2}}, - // .SVE_PMULLB + // .PMULLB {written={0}, read={1, 2}}, - // .SVE_PMULLT + // .PMULLT {written={0}, read={1, 2}}, - // .SVE_BFCVT - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFCVTNT + // .BFCVTNT {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .LDRAA {written={0}, read={1}, reads_mem=true}, + {written={0, 1}, read={1}, reads_mem=true}, // .LDRAB {written={0}, read={1}, reads_mem=true}, - // .LDRAA_PRE - {written={0, 1}, read={1}, reads_mem=true}, - // .LDRAB_PRE {written={0, 1}, read={1}, reads_mem=true}, // .TSTART {written={0}, side_effects={.NONDETERMINISTIC}}, @@ -6795,15 +6226,18 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, // .LDAPURSW {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}, - // .SVE_BFADD + // .BFADD {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFSUB + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFSUB {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFMUL + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFMUL {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFMLA + {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, + // .BFMLA {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFMLS + // .BFMLS {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, // .SB {side_effects={.FENCE}}, @@ -6821,79 +6255,21 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {side_effects={.BTI}}, // .BTI_JC {side_effects={.BTI}}, - // .MOV_V_ALIAS - {written={0}, read={1}}, - {written={0}, read={1}}, - // .NOT_V_ALIAS - {written={0}, read={1}}, - {written={0}, read={1}}, - // .LSL_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .LSR_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .ASR_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .ROR_IMM - {written={0}, read={1}}, - {written={0}, read={1}}, - // .SVE_BFADD_UNPRED - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFSUB_UNPRED - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFMUL_UNPRED - {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}, - // .SVE_BFCLAMP + // .BFCLAMP {written={0}, read={1, 2}}, - // .SVE_BFMAXNM + // .BFMAXNM {written={0}, read={1, 2, 3}}, - // .SVE_BFMINNM + // .BFMINNM {written={0}, read={1, 2, 3}}, - // .SME2_LUTI2_B + // .LUTI2 {written={0}, read={1}}, - // .SME2_LUTI4_B + // .LUTI4 {written={0}, read={1}}, - // .SME2_LD1B_X2 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1H_X2 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1W_X2 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1D_X2 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1B_X4 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1H_X4 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1W_X4 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_LD1D_X4 - {written={0}, read={1, 2}, reads_mem=true}, - // .SME2_ST1B_X2 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1H_X2 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1W_X2 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1D_X2 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1B_X4 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1H_X4 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1W_X4 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ST1D_X4 - {read={0, 1, 2}, writes_mem=true}, - // .SME2_ZIP_3 + // .ZIP {written={0}, read={1, 2}}, - // .SME2_ZIP_4 {written={0}, read={1, 2}}, - // .SME2_UZP_3 + // .UZP {written={0}, read={1, 2}}, - // .SME2_UZP_4 {written={0}, read={1, 2}}, // .TLBI_RPALOS {read={0}, side_effects={.PRIVILEGED}}, @@ -7059,1152 +6435,814 @@ CLOBBER_FORMS := [2440]lib.Clobber{ {side_effects={.PRIVILEGED}}, // .PRFM {read={1}, side_effects={.HINT}}, + {side_effects={.HINT}}, // .PRFUM {read={1}, side_effects={.HINT}}, - // .PRFM_LIT - {side_effects={.HINT}}, - // .MOV_REG - {written={0}, read={1}}, - {written={0}, read={1}}, - // .MOV_BITMASK - {written={0}}, - {written={0}}, - // .MVN - {written={0}, read={1}}, - {written={0}, read={1}}, - // .NEG_SR - {written={0}, read={1}}, - {written={0}, read={1}}, // .NEGS {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMP_SR + // .CMP {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMP_ER {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMP_IMM {read={0}, nzcv_wr={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMN_SR + // .CMN {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMN_ER {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - // .CMN_IMM {read={0}, nzcv_wr={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}, - // .TST_SR - {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, - {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}, } @(rodata) ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ - .INVALID = { 0, 0}, - .ADD_IMM = { 0, 2}, - .ADDS_IMM = { 2, 2}, - .SUB_IMM = { 4, 2}, - .SUBS_IMM = { 6, 2}, - .MOVZ = { 8, 2}, - .MOVN = { 10, 2}, - .MOVK = { 12, 2}, - .ADR = { 14, 1}, - .ADRP = { 15, 1}, - .ADD_SR = { 16, 2}, - .ADDS_SR = { 18, 2}, - .SUB_SR = { 20, 2}, - .SUBS_SR = { 22, 2}, - .AND_SR = { 24, 2}, - .ANDS_SR = { 26, 2}, - .ORR_SR = { 28, 2}, - .EOR_SR = { 30, 2}, - .BIC_SR = { 32, 2}, - .BICS_SR = { 34, 2}, - .ORN_SR = { 36, 2}, - .EON_SR = { 38, 2}, - .ADD_ER = { 40, 2}, - .ADDS_ER = { 42, 2}, - .SUB_ER = { 44, 2}, - .SUBS_ER = { 46, 2}, - .LSLV = { 48, 2}, - .LSRV = { 50, 2}, - .ASRV = { 52, 2}, - .RORV = { 54, 2}, - .UDIV = { 56, 2}, - .SDIV = { 58, 2}, - .MADD = { 60, 2}, - .MSUB = { 62, 2}, - .SMADDL = { 64, 1}, - .SMSUBL = { 65, 1}, - .UMADDL = { 66, 1}, - .UMSUBL = { 67, 1}, - .SMULH = { 68, 1}, - .UMULH = { 69, 1}, - .CLZ = { 70, 2}, - .CLS = { 72, 2}, - .RBIT = { 74, 2}, - .REV = { 76, 2}, - .REV16 = { 78, 2}, - .REV32 = { 80, 1}, - .CSEL = { 81, 2}, - .CSINC = { 83, 2}, - .CSINV = { 85, 2}, - .CSNEG = { 87, 2}, - .CCMP_REG = { 89, 2}, - .CCMP_IMM = { 91, 2}, - .CCMN_REG = { 93, 2}, - .CCMN_IMM = { 95, 2}, - .EXTR = { 97, 2}, - .B = { 99, 1}, - .BL = { 100, 1}, - .BR = { 101, 1}, - .BLR = { 102, 1}, - .RET = { 103, 2}, - .B_COND = { 105, 1}, - .CBZ = { 106, 2}, - .CBNZ = { 108, 2}, - .TBZ = { 110, 1}, - .TBNZ = { 111, 1}, - .LDR = { 112, 2}, - .STR = { 114, 2}, - .LDRB = { 116, 1}, - .STRB = { 117, 1}, - .LDRSB = { 118, 2}, - .LDRH = { 120, 1}, - .STRH = { 121, 1}, - .LDRSH = { 122, 2}, - .LDRSW = { 124, 1}, - .LDP = { 125, 2}, - .STP = { 127, 2}, - .LDPSW = { 129, 1}, - .LDR_LIT = { 130, 2}, - .LDAR = { 132, 2}, - .STLR = { 134, 2}, - .LDARB = { 136, 1}, - .STLRB = { 137, 1}, - .LDARH = { 138, 1}, - .STLRH = { 139, 1}, - .LDXR = { 140, 2}, - .STXR = { 142, 2}, - .LDAXR = { 144, 2}, - .STLXR = { 146, 2}, - .NOP = { 148, 1}, - .YIELD = { 149, 1}, - .WFE = { 150, 1}, - .WFI = { 151, 1}, - .SEV = { 152, 1}, - .SEVL = { 153, 1}, - .HINT = { 154, 1}, - .MRS = { 155, 1}, - .MSR_IMM = { 156, 1}, - .MSR_REG = { 157, 1}, - .ISB = { 158, 1}, - .DSB = { 159, 1}, - .DMB = { 160, 1}, - .SVC = { 161, 1}, - .HVC = { 162, 1}, - .SMC = { 163, 1}, - .BRK = { 164, 1}, - .HLT = { 165, 1}, - .ERET = { 166, 1}, - .FMOV_REG = { 167, 2}, - .FMOV_IMM = { 169, 3}, - .FMOV_GEN = { 172, 4}, - .FABS = { 176, 2}, - .FNEG = { 178, 2}, - .FSQRT = { 180, 2}, - .FADD = { 182, 2}, - .FSUB = { 184, 2}, - .FMUL = { 186, 2}, - .FDIV = { 188, 2}, - .FNMUL = { 190, 2}, - .FMADD = { 192, 2}, - .FMSUB = { 194, 2}, - .FNMADD = { 196, 2}, - .FNMSUB = { 198, 2}, - .FCMP = { 200, 2}, - .FCMPE = { 202, 2}, - .FCSEL = { 204, 2}, - .FMAX = { 206, 2}, - .FMIN = { 208, 2}, - .FMAXNM = { 210, 2}, - .FMINNM = { 212, 2}, - .FCVT = { 214, 2}, - .SCVTF = { 216, 4}, - .UCVTF = { 220, 4}, - .FCVTZS = { 224, 4}, - .FCVTZU = { 228, 4}, - .FCVTAS = { 232, 6}, - .FCVTAU = { 238, 6}, - .FCVTNS = { 244, 6}, - .FCVTNU = { 250, 6}, - .FCVTPS = { 256, 6}, - .FCVTPU = { 262, 6}, - .FCVTMS = { 268, 6}, - .FCVTMU = { 274, 6}, - .FRINTA = { 280, 3}, - .FRINTI = { 283, 3}, - .FRINTM = { 286, 3}, - .FRINTN = { 289, 3}, - .FRINTP = { 292, 3}, - .FRINTX = { 295, 3}, - .FRINTZ = { 298, 3}, - .AND_IMM = { 301, 2}, - .ANDS_IMM = { 303, 2}, - .ORR_IMM = { 305, 2}, - .EOR_IMM = { 307, 2}, - .TST_IMM = { 309, 2}, - .LDUR = { 311, 2}, - .STUR = { 313, 2}, - .LDURB = { 315, 1}, - .STURB = { 316, 1}, - .LDURSB = { 317, 2}, - .LDURH = { 319, 1}, - .STURH = { 320, 1}, - .LDURSH = { 321, 2}, - .LDURSW = { 323, 1}, - .LDR_PRE = { 324, 2}, - .STR_PRE = { 326, 2}, - .LDR_POST = { 328, 2}, - .STR_POST = { 330, 2}, - .LDRB_PRE = { 332, 1}, - .STRB_PRE = { 333, 1}, - .LDRB_POST = { 334, 1}, - .STRB_POST = { 335, 1}, - .LDRH_PRE = { 336, 1}, - .STRH_PRE = { 337, 1}, - .LDRH_POST = { 338, 1}, - .STRH_POST = { 339, 1}, - .LDR_REG = { 340, 2}, - .STR_REG = { 342, 2}, - .LDRB_REG = { 344, 1}, - .STRB_REG = { 345, 1}, - .LDRH_REG = { 346, 1}, - .STRH_REG = { 347, 1}, - .LDRSB_REG = { 348, 2}, - .LDRSH_REG = { 350, 2}, - .LDRSW_REG = { 352, 1}, - .LDP_PRE = { 353, 2}, - .STP_PRE = { 355, 2}, - .LDP_POST = { 357, 2}, - .STP_POST = { 359, 2}, - .LDPSW_PRE = { 361, 1}, - .LDPSW_POST = { 362, 1}, - .LDNP = { 363, 2}, - .STNP = { 365, 2}, - .LDXP = { 367, 2}, - .STXP = { 369, 2}, - .LDAXP = { 371, 2}, - .STLXP = { 373, 2}, - .LDXRB = { 375, 1}, - .STXRB = { 376, 1}, - .LDAXRB = { 377, 1}, - .STLXRB = { 378, 1}, - .LDXRH = { 379, 1}, - .STXRH = { 380, 1}, - .LDAXRH = { 381, 1}, - .STLXRH = { 382, 1}, - .LDAPR = { 383, 2}, - .LDAPRB = { 385, 1}, - .LDAPRH = { 386, 1}, - .LDADD = { 387, 2}, - .LDADDA = { 389, 2}, - .LDADDL = { 391, 2}, - .LDADDAL = { 393, 2}, - .LDCLR = { 395, 2}, - .LDCLRA = { 397, 2}, - .LDCLRL = { 399, 2}, - .LDCLRAL = { 401, 2}, - .LDEOR = { 403, 2}, - .LDEORA = { 405, 2}, - .LDEORL = { 407, 2}, - .LDEORAL = { 409, 2}, - .LDSET = { 411, 2}, - .LDSETA = { 413, 2}, - .LDSETL = { 415, 2}, - .LDSETAL = { 417, 2}, - .LDSMAX = { 419, 2}, - .LDSMAXA = { 421, 2}, - .LDSMAXL = { 423, 2}, - .LDSMAXAL = { 425, 2}, - .LDSMIN = { 427, 2}, - .LDSMINA = { 429, 2}, - .LDSMINL = { 431, 2}, - .LDSMINAL = { 433, 2}, - .LDUMAX = { 435, 2}, - .LDUMAXA = { 437, 2}, - .LDUMAXL = { 439, 2}, - .LDUMAXAL = { 441, 2}, - .LDUMIN = { 443, 2}, - .LDUMINA = { 445, 2}, - .LDUMINL = { 447, 2}, - .LDUMINAL = { 449, 2}, - .SWP = { 451, 2}, - .SWPA = { 453, 2}, - .SWPL = { 455, 2}, - .SWPAL = { 457, 2}, - .CAS = { 459, 2}, - .CASA = { 461, 2}, - .CASL = { 463, 2}, - .CASAL = { 465, 2}, - .CASB = { 467, 1}, - .CASAB = { 468, 1}, - .CASLB = { 469, 1}, - .CASALB = { 470, 1}, - .CASH = { 471, 1}, - .CASAH = { 472, 1}, - .CASLH = { 473, 1}, - .CASALH = { 474, 1}, - .CASP = { 475, 2}, - .CASPA = { 477, 2}, - .CASPL = { 479, 2}, - .CASPAL = { 481, 2}, - .PACIA = { 483, 1}, - .PACIB = { 484, 1}, - .PACDA = { 485, 1}, - .PACDB = { 486, 1}, - .PACIZA = { 487, 1}, - .PACIZB = { 488, 1}, - .PACDZA = { 489, 1}, - .PACDZB = { 490, 1}, - .AUTIA = { 491, 1}, - .AUTIB = { 492, 1}, - .AUTDA = { 493, 1}, - .AUTDB = { 494, 1}, - .AUTIZA = { 495, 1}, - .AUTIZB = { 496, 1}, - .AUTDZA = { 497, 1}, - .AUTDZB = { 498, 1}, - .PACIASP = { 499, 1}, - .PACIBSP = { 500, 1}, - .AUTIASP = { 501, 1}, - .AUTIBSP = { 502, 1}, - .PACIA1716 = { 503, 1}, - .PACIB1716 = { 504, 1}, - .AUTIA1716 = { 505, 1}, - .AUTIB1716 = { 506, 1}, - .PACGA = { 507, 1}, - .XPACI = { 508, 1}, - .XPACD = { 509, 1}, - .XPACLRI = { 510, 1}, - .RETAA = { 511, 1}, - .RETAB = { 512, 1}, - .BRAA = { 513, 1}, - .BRAB = { 514, 1}, - .BRAAZ = { 515, 1}, - .BRABZ = { 516, 1}, - .BLRAA = { 517, 1}, - .BLRAB = { 518, 1}, - .BLRAAZ = { 519, 1}, - .BLRABZ = { 520, 1}, - .ERETAA = { 521, 1}, - .ERETAB = { 522, 1}, - .BTI = { 523, 1}, - .IRG = { 524, 1}, - .ADDG = { 525, 1}, - .SUBG = { 526, 1}, - .GMI = { 527, 1}, - .SUBP = { 528, 1}, - .SUBPS = { 529, 1}, - .LDG = { 530, 1}, - .STG = { 531, 1}, - .ST2G = { 532, 1}, - .STZG = { 533, 1}, - .STZ2G = { 534, 1}, - .STGP = { 535, 1}, - .LDGM = { 536, 1}, - .STGM = { 537, 1}, - .STZGM = { 538, 1}, - .CRC32B = { 539, 1}, - .CRC32H = { 540, 1}, - .CRC32W = { 541, 1}, - .CRC32X = { 542, 1}, - .CRC32CB = { 543, 1}, - .CRC32CH = { 544, 1}, - .CRC32CW = { 545, 1}, - .CRC32CX = { 546, 1}, - .AESE = { 547, 1}, - .AESD = { 548, 1}, - .AESMC = { 549, 1}, - .AESIMC = { 550, 1}, - .SHA1H = { 551, 1}, - .SHA1C = { 552, 1}, - .SHA1P = { 553, 1}, - .SHA1M = { 554, 1}, - .SHA1SU0 = { 555, 1}, - .SHA1SU1 = { 556, 1}, - .SHA256H = { 557, 1}, - .SHA256H2 = { 558, 1}, - .SHA256SU0 = { 559, 1}, - .SHA256SU1 = { 560, 1}, - .SHA512H = { 561, 1}, - .SHA512H2 = { 562, 1}, - .SHA512SU0 = { 563, 1}, - .SHA512SU1 = { 564, 1}, - .EOR3 = { 565, 1}, - .BCAX = { 566, 1}, - .RAX1 = { 567, 1}, - .XAR = { 568, 1}, - .SM3PARTW1 = { 569, 1}, - .SM3PARTW2 = { 570, 1}, - .SM3SS1 = { 571, 1}, - .SM3TT1A = { 572, 1}, - .SM3TT1B = { 573, 1}, - .SM3TT2A = { 574, 1}, - .SM3TT2B = { 575, 1}, - .SM4E = { 576, 1}, - .SM4EKEY = { 577, 1}, - .PMULL = { 578, 2}, - .PMULL2 = { 580, 2}, - .FABS_H = { 582, 1}, - .FNEG_H = { 583, 1}, - .FSQRT_H = { 584, 1}, - .FADD_H = { 585, 1}, - .FSUB_H = { 586, 1}, - .FMUL_H = { 587, 1}, - .FDIV_H = { 588, 1}, - .FNMUL_H = { 589, 1}, - .FMADD_H = { 590, 1}, - .FMSUB_H = { 591, 1}, - .FNMADD_H = { 592, 1}, - .FNMSUB_H = { 593, 1}, - .FCMP_H = { 594, 1}, - .FCMPE_H = { 595, 1}, - .FCSEL_H = { 596, 1}, - .FMAX_H = { 597, 1}, - .FMIN_H = { 598, 1}, - .FMAXNM_H = { 599, 1}, - .FMINNM_H = { 600, 1}, - .FCVT_H_S = { 601, 1}, - .FCVT_H_D = { 602, 1}, - .FCVT_S_H = { 603, 1}, - .FCVT_D_H = { 604, 1}, - .FMOV_H = { 605, 1}, - .SCVTF_H = { 606, 1}, - .UCVTF_H = { 607, 1}, - .FCVTZS_H = { 608, 1}, - .FCVTZU_H = { 609, 1}, - .BFCVT = { 610, 1}, - .BFDOT = { 611, 1}, - .BFMMLA = { 612, 1}, - .BFMLALB = { 613, 1}, - .BFMLALT = { 614, 1}, - .BFCVTN = { 615, 1}, - .BFCVTN2 = { 616, 1}, - .ADD_V = { 617, 7}, - .SUB_V = { 624, 4}, - .MUL_V = { 628, 3}, - .MLA_V = { 631, 6}, - .MLS_V = { 637, 6}, - .NEG_V = { 643, 7}, - .ABS_V = { 650, 7}, - .SHADD = { 657, 6}, - .UHADD = { 663, 6}, - .SHSUB = { 669, 6}, - .UHSUB = { 675, 6}, - .SRHADD = { 681, 6}, - .URHADD = { 687, 6}, - .SQADD = { 693, 7}, - .UQADD = { 700, 7}, - .SQSUB = { 707, 7}, - .UQSUB = { 714, 7}, - .SMAX = { 721, 6}, - .UMAX = { 727, 6}, - .SMIN = { 733, 6}, - .UMIN = { 739, 6}, - .SABD = { 745, 6}, - .UABD = { 751, 6}, - .SABA = { 757, 6}, - .UABA = { 763, 6}, - .ADDP_V = { 769, 7}, - .ADDV = { 776, 5}, - .SADDLP = { 781, 6}, - .UADDLP = { 787, 6}, - .SADALP = { 793, 6}, - .UADALP = { 799, 6}, - .SADDLV = { 805, 5}, - .UADDLV = { 810, 5}, - .SMAXV = { 815, 5}, - .UMAXV = { 820, 5}, - .SMINV = { 825, 5}, - .UMINV = { 830, 5}, - .SMAXP = { 835, 6}, - .UMAXP = { 841, 6}, - .SMINP = { 847, 6}, - .UMINP = { 853, 6}, - .SADDL = { 859, 3}, - .SADDL2 = { 862, 3}, - .UADDL = { 865, 3}, - .UADDL2 = { 868, 3}, - .SSUBL = { 871, 3}, - .SSUBL2 = { 874, 3}, - .USUBL = { 877, 3}, - .USUBL2 = { 880, 3}, - .SADDW = { 883, 3}, - .SADDW2 = { 886, 3}, - .UADDW = { 889, 3}, - .UADDW2 = { 892, 3}, - .SSUBW = { 895, 3}, - .SSUBW2 = { 898, 3}, - .USUBW = { 901, 3}, - .USUBW2 = { 904, 3}, - .RADDHN = { 907, 3}, - .RADDHN2 = { 910, 3}, - .RSUBHN = { 913, 3}, - .RSUBHN2 = { 916, 3}, - .ADDHN = { 919, 3}, - .ADDHN2 = { 922, 3}, - .SUBHN = { 925, 3}, - .SUBHN2 = { 928, 3}, - .XTN = { 931, 3}, - .XTN2 = { 934, 3}, - .SQXTN = { 937, 3}, - .SQXTN2 = { 940, 3}, - .UQXTN = { 943, 3}, - .UQXTN2 = { 946, 3}, - .SQXTUN = { 949, 3}, - .SQXTUN2 = { 952, 3}, - .SMULL_V = { 955, 3}, - .SMULL2_V = { 958, 3}, - .UMULL_V = { 961, 3}, - .UMULL2_V = { 964, 3}, - .SMLAL = { 967, 3}, - .SMLAL2 = { 970, 3}, - .UMLAL = { 973, 3}, - .UMLAL2 = { 976, 3}, - .SMLSL = { 979, 3}, - .SMLSL2 = { 982, 3}, - .UMLSL = { 985, 3}, - .UMLSL2 = { 988, 3}, - .SQDMULL = { 991, 2}, - .SQDMULL2 = { 993, 2}, - .SQDMLAL = { 995, 2}, - .SQDMLAL2 = { 997, 2}, - .SQDMLSL = { 999, 2}, - .SQDMLSL2 = { 1001, 2}, - .SQDMULH = { 1003, 4}, - .SQRDMULH = { 1007, 4}, - .SDOT = { 1011, 2}, - .UDOT = { 1013, 2}, - .USDOT = { 1015, 2}, - .FADD_V = { 1017, 3}, - .FSUB_V = { 1020, 3}, - .FMUL_V = { 1023, 3}, - .FDIV_V = { 1026, 3}, - .FNEG_V = { 1029, 5}, - .FABS_V = { 1034, 5}, - .FSQRT_V = { 1039, 5}, - .FMLA_V = { 1044, 2}, - .FMLS_V = { 1046, 2}, - .FMULX = { 1048, 5}, - .FMAX_V = { 1053, 5}, - .FMIN_V = { 1058, 5}, - .FMAXNM_V = { 1063, 5}, - .FMINNM_V = { 1068, 5}, - .FMAXP_V = { 1073, 5}, - .FMINP_V = { 1078, 5}, - .FMAXNMP = { 1083, 5}, - .FMINNMP = { 1088, 5}, - .FMAXV_V = { 1093, 3}, - .FMINV_V = { 1096, 3}, - .FMAXNMV = { 1099, 3}, - .FMINNMV = { 1102, 3}, - .FRECPE = { 1105, 5}, - .FRSQRTE = { 1110, 5}, - .FRECPS = { 1115, 5}, - .FRSQRTS = { 1120, 5}, - .FRECPX = { 1125, 3}, - .FADDP_V = { 1128, 5}, - .FRINTA_V = { 1133, 5}, - .FRINTI_V = { 1138, 5}, - .FRINTM_V = { 1143, 5}, - .FRINTN_V = { 1148, 5}, - .FRINTP_V = { 1153, 5}, - .FRINTX_V = { 1158, 5}, - .FRINTZ_V = { 1163, 5}, - .SCVTF_V = { 1168, 5}, - .UCVTF_V = { 1173, 5}, - .FCVTAS_V = { 1178, 5}, - .FCVTAU_V = { 1183, 5}, - .FCVTMS_V = { 1188, 5}, - .FCVTMU_V = { 1193, 5}, - .FCVTNS_V = { 1198, 5}, - .FCVTNU_V = { 1203, 5}, - .FCVTPS_V = { 1208, 5}, - .FCVTPU_V = { 1213, 5}, - .FCVTZS_V = { 1218, 5}, - .FCVTZU_V = { 1223, 5}, - .FCVTL = { 1228, 2}, - .FCVTL2 = { 1230, 2}, - .FCVTN = { 1232, 2}, - .FCVTN2 = { 1234, 2}, - .FCVTXN = { 1236, 1}, - .FCVTXN2 = { 1237, 1}, - .FCMEQ = { 1238, 5}, - .FCMGE = { 1243, 5}, - .FCMGT = { 1248, 5}, - .FCMLE = { 1253, 5}, - .FCMLT = { 1258, 5}, - .FACGE = { 1263, 5}, - .FACGT = { 1268, 5}, - .CMEQ = { 1273, 4}, - .CMGE = { 1277, 7}, - .CMGT = { 1284, 2}, - .CMHI = { 1286, 2}, - .CMHS = { 1288, 7}, - .CMLE = { 1295, 7}, - .CMLT = { 1302, 7}, - .CMTST = { 1309, 7}, - .AND_V = { 1316, 1}, - .ORR_V = { 1317, 1}, - .EOR_V = { 1318, 1}, - .BIC_V = { 1319, 1}, - .ORN_V = { 1320, 1}, - .MVN_V = { 1321, 2}, - .BIT = { 1323, 1}, - .BIF = { 1324, 1}, - .BSL = { 1325, 1}, - .SHL_V = { 1326, 7}, - .SQSHL_V = { 1333, 7}, - .SQSHLU = { 1340, 7}, - .SRSHL = { 1347, 7}, - .URSHL = { 1354, 7}, - .SSHR = { 1361, 7}, - .USHR = { 1368, 7}, - .SSRA = { 1375, 7}, - .USRA = { 1382, 7}, - .SRSHR = { 1389, 7}, - .URSHR = { 1396, 7}, - .SRSRA = { 1403, 7}, - .URSRA = { 1410, 7}, - .SSHL = { 1417, 7}, - .USHL = { 1424, 7}, - .SLI = { 1431, 7}, - .SRI = { 1438, 7}, - .SSHLL = { 1445, 3}, - .SSHLL2 = { 1448, 3}, - .USHLL = { 1451, 3}, - .USHLL2 = { 1454, 3}, - .SXTL = { 1457, 3}, - .SXTL2 = { 1460, 3}, - .UXTL = { 1463, 3}, - .UXTL2 = { 1466, 3}, - .SHRN = { 1469, 3}, - .SHRN2 = { 1472, 3}, - .RSHRN = { 1475, 3}, - .RSHRN2 = { 1478, 3}, - .SQSHRN = { 1481, 3}, - .SQSHRN2 = { 1484, 3}, - .UQSHRN = { 1487, 3}, - .UQSHRN2 = { 1490, 3}, - .SQRSHRN = { 1493, 3}, - .SQRSHRN2 = { 1496, 3}, - .UQRSHRN = { 1499, 3}, - .UQRSHRN2 = { 1502, 3}, - .SQSHRUN = { 1505, 3}, - .SQSHRUN2 = { 1508, 3}, - .SQRSHRUN = { 1511, 3}, - .SQRSHRUN2 = { 1514, 3}, - .DUP_V = { 1517, 14}, - .INS = { 1531, 8}, - .MOV_V = { 1539, 2}, - .EXT_V = { 1541, 2}, - .TBL = { 1543, 2}, - .TBX = { 1545, 2}, - .ZIP1 = { 1547, 7}, - .ZIP2 = { 1554, 7}, - .UZP1 = { 1561, 7}, - .UZP2 = { 1568, 7}, - .TRN1 = { 1575, 7}, - .TRN2 = { 1582, 7}, - .NOT_V = { 1589, 2}, - .RBIT_V = { 1591, 2}, - .REV16_V = { 1593, 2}, - .REV32_V = { 1595, 4}, - .REV64 = { 1599, 6}, - .CLS_V = { 1605, 6}, - .CLZ_V = { 1611, 6}, - .CNT = { 1617, 2}, - .URECPE_V = { 1619, 2}, - .URSQRTE_V = { 1621, 2}, - .MOVI = { 1623, 7}, - .MVNI = { 1630, 4}, - .FMOV_V_IMM = { 1634, 5}, - .LD1 = { 1639, 4}, - .LD2 = { 1643, 1}, - .LD3 = { 1644, 1}, - .LD4 = { 1645, 1}, - .ST1 = { 1646, 4}, - .ST2 = { 1650, 1}, - .ST3 = { 1651, 1}, - .ST4 = { 1652, 1}, - .LD1R = { 1653, 1}, - .LD2R = { 1654, 1}, - .LD3R = { 1655, 1}, - .LD4R = { 1656, 1}, - .LD1_LANE = { 1657, 4}, - .LD2_LANE = { 1661, 4}, - .LD3_LANE = { 1665, 4}, - .LD4_LANE = { 1669, 4}, - .ST1_LANE = { 1673, 4}, - .ST2_LANE = { 1677, 4}, - .ST3_LANE = { 1681, 4}, - .ST4_LANE = { 1685, 4}, - .LDR_V = { 1689, 5}, - .STR_V = { 1694, 5}, - .LDP_V = { 1699, 3}, - .STP_V = { 1702, 3}, - .LDUR_V = { 1705, 3}, - .STUR_V = { 1708, 3}, - .SVE_ADD_Z = { 1711, 4}, - .SVE_SUB_Z = { 1715, 4}, - .SVE_SQADD_Z = { 1719, 4}, - .SVE_UQADD_Z = { 1723, 4}, - .SVE_SQSUB_Z = { 1727, 4}, - .SVE_UQSUB_Z = { 1731, 4}, - .SVE_ADD_PRED = { 1735, 4}, - .SVE_SUB_PRED = { 1739, 4}, - .SVE_SUBR_PRED = { 1743, 4}, - .SVE_MUL_PRED = { 1747, 4}, - .SVE_SMULH_PRED = { 1751, 4}, - .SVE_UMULH_PRED = { 1755, 4}, - .SVE_SDIV_PRED = { 1759, 2}, - .SVE_UDIV_PRED = { 1761, 2}, - .SVE_SMAX_PRED = { 1763, 4}, - .SVE_UMAX_PRED = { 1767, 4}, - .SVE_SMIN_PRED = { 1771, 4}, - .SVE_UMIN_PRED = { 1775, 4}, - .SVE_SABD_PRED = { 1779, 4}, - .SVE_UABD_PRED = { 1783, 4}, - .SVE_AND_PRED = { 1787, 1}, - .SVE_ORR_PRED = { 1788, 1}, - .SVE_EOR_PRED = { 1789, 1}, - .SVE_BIC_PRED = { 1790, 1}, - .SVE_ASR_PRED = { 1791, 4}, - .SVE_LSL_PRED = { 1795, 4}, - .SVE_LSR_PRED = { 1799, 4}, - .SVE_ASRR_PRED = { 1803, 4}, - .SVE_LSLR_PRED = { 1807, 4}, - .SVE_LSRR_PRED = { 1811, 4}, - .SVE_ABS_PRED = { 1815, 4}, - .SVE_NEG_PRED = { 1819, 4}, - .SVE_CLS_PRED = { 1823, 4}, - .SVE_CLZ_PRED = { 1827, 4}, - .SVE_CNT_PRED = { 1831, 4}, - .SVE_MOV_PRED = { 1835, 4}, - .SVE_FADD_Z = { 1839, 3}, - .SVE_FSUB_Z = { 1842, 3}, - .SVE_FMUL_Z = { 1845, 3}, - .SVE_FRECPS = { 1848, 3}, - .SVE_FRSQRTS = { 1851, 3}, - .SVE_FTSMUL = { 1854, 3}, - .SVE_FADD_PRED = { 1857, 3}, - .SVE_FSUB_PRED = { 1860, 3}, - .SVE_FSUBR_PRED = { 1863, 3}, - .SVE_FMUL_PRED = { 1866, 3}, - .SVE_FDIV_PRED = { 1869, 3}, - .SVE_FDIVR_PRED = { 1872, 3}, - .SVE_FMAX_PRED = { 1875, 3}, - .SVE_FMIN_PRED = { 1878, 3}, - .SVE_FMAXNM_PRED = { 1881, 3}, - .SVE_FMINNM_PRED = { 1884, 3}, - .SVE_FABS_Z = { 1887, 3}, - .SVE_FNEG_Z = { 1890, 3}, - .SVE_FSQRT_Z = { 1893, 3}, - .SVE_FRECPX_Z = { 1896, 3}, - .SVE_FRINTN = { 1899, 3}, - .SVE_FRINTP = { 1902, 3}, - .SVE_FRINTM = { 1905, 3}, - .SVE_FRINTZ = { 1908, 3}, - .SVE_FRINTA = { 1911, 3}, - .SVE_FRINTX = { 1914, 3}, - .SVE_FRINTI = { 1917, 3}, - .SVE_FMLA = { 1920, 3}, - .SVE_FMLS = { 1923, 3}, - .SVE_FNMLA = { 1926, 3}, - .SVE_FNMLS = { 1929, 3}, - .SVE_AND_P = { 1932, 1}, - .SVE_BIC_P = { 1933, 1}, - .SVE_ORR_P = { 1934, 1}, - .SVE_EOR_P = { 1935, 1}, - .SVE_NAND_P = { 1936, 1}, - .SVE_NOR_P = { 1937, 1}, - .SVE_ORN_P = { 1938, 1}, - .SVE_SEL_P = { 1939, 1}, - .SVE_ANDS_P = { 1940, 1}, - .SVE_BICS_P = { 1941, 1}, - .SVE_ORRS_P = { 1942, 1}, - .SVE_EORS_P = { 1943, 1}, - .SVE_NANDS_P = { 1944, 1}, - .SVE_NORS_P = { 1945, 1}, - .SVE_ORNS_P = { 1946, 1}, - .SVE_NOT_P = { 1947, 1}, - .SVE_MOV_P = { 1948, 2}, - .SVE_MOVS_P = { 1950, 1}, - .SVE_PTRUE = { 1951, 1}, - .SVE_PTRUES = { 1952, 1}, - .SVE_PFALSE = { 1953, 1}, - .SVE_PFIRST = { 1954, 1}, - .SVE_PNEXT = { 1955, 1}, - .SVE_BRKA = { 1956, 1}, - .SVE_BRKB = { 1957, 1}, - .SVE_BRKAS = { 1958, 1}, - .SVE_BRKBS = { 1959, 1}, - .SVE_BRKPA = { 1960, 1}, - .SVE_BRKPB = { 1961, 1}, - .SVE_BRKN = { 1962, 1}, - .SVE_RDFFR = { 1963, 1}, - .SVE_WRFFR = { 1964, 1}, - .SVE_SETFFR = { 1965, 1}, - .SVE_CMPEQ = { 1966, 4}, - .SVE_CMPNE = { 1970, 4}, - .SVE_CMPGE = { 1974, 4}, - .SVE_CMPGT = { 1978, 4}, - .SVE_CMPLE = { 1982, 4}, - .SVE_CMPLT = { 1986, 4}, - .SVE_CMPHI = { 1990, 4}, - .SVE_CMPHS = { 1994, 4}, - .SVE_CMPLO = { 1998, 4}, - .SVE_CMPLS = { 2002, 4}, - .SVE_FCMEQ = { 2006, 3}, - .SVE_FCMNE = { 2009, 3}, - .SVE_FCMGE = { 2012, 3}, - .SVE_FCMGT = { 2015, 3}, - .SVE_FCMLE = { 2018, 3}, - .SVE_FCMLT = { 2021, 3}, - .SVE_FCMUO = { 2024, 3}, - .SVE_DUP_Z = { 2027, 4}, - .SVE_INSR = { 2031, 4}, - .SVE_REV_Z = { 2035, 4}, - .SVE_REV_P = { 2039, 1}, - .SVE_TBL = { 2040, 4}, - .SVE_ZIP1_Z = { 2044, 4}, - .SVE_ZIP2_Z = { 2048, 4}, - .SVE_UZP1_Z = { 2052, 4}, - .SVE_UZP2_Z = { 2056, 4}, - .SVE_TRN1_Z = { 2060, 4}, - .SVE_TRN2_Z = { 2064, 4}, - .SVE_ZIP1_P = { 2068, 1}, - .SVE_ZIP2_P = { 2069, 1}, - .SVE_UZP1_P = { 2070, 1}, - .SVE_UZP2_P = { 2071, 1}, - .SVE_TRN1_P = { 2072, 1}, - .SVE_TRN2_P = { 2073, 1}, - .SVE_CPY_Z = { 2074, 4}, - .SVE_COMPACT = { 2078, 2}, - .SVE_EXT_Z = { 2080, 1}, - .SVE_LD1B = { 2081, 1}, - .SVE_LD1H = { 2082, 1}, - .SVE_LD1W = { 2083, 1}, - .SVE_LD1D = { 2084, 1}, - .SVE_LD1SB = { 2085, 1}, - .SVE_LD1SH = { 2086, 1}, - .SVE_LD1SW = { 2087, 1}, - .SVE_ST1B = { 2088, 1}, - .SVE_ST1H = { 2089, 1}, - .SVE_ST1W = { 2090, 1}, - .SVE_ST1D = { 2091, 1}, - .SVE_LDR_Z = { 2092, 1}, - .SVE_STR_Z = { 2093, 1}, - .SVE_LDR_P = { 2094, 1}, - .SVE_STR_P = { 2095, 1}, - .SVE_LDFF1B = { 2096, 1}, - .SVE_LDFF1H = { 2097, 1}, - .SVE_LDFF1W = { 2098, 1}, - .SVE_LDFF1D = { 2099, 1}, - .SVE_WHILEGE = { 2100, 1}, - .SVE_WHILEGT = { 2101, 1}, - .SVE_WHILELE = { 2102, 1}, - .SVE_WHILELT = { 2103, 1}, - .SVE_WHILEHI = { 2104, 1}, - .SVE_WHILEHS = { 2105, 1}, - .SVE_WHILELO = { 2106, 1}, - .SVE_WHILELS = { 2107, 1}, - .SVE_SQRDMLAH = { 2108, 4}, - .SVE_SQRDMLSH = { 2112, 4}, - .SVE_ADCLB = { 2116, 2}, - .SVE_ADCLT = { 2118, 2}, - .SVE_SBCLB = { 2120, 2}, - .SVE_SBCLT = { 2122, 2}, - .SVE_TBL2 = { 2124, 1}, - .SVE_TBX = { 2125, 1}, - .SVE_AESE = { 2126, 1}, - .SVE_AESD = { 2127, 1}, - .SVE_AESMC = { 2128, 1}, - .SVE_AESIMC = { 2129, 1}, - .SVE_BCAX_Z = { 2130, 1}, - .SVE_XAR_Z = { 2131, 4}, - .SVE_EOR3_Z = { 2135, 1}, - .SVE_MATCH = { 2136, 2}, - .SVE_NMATCH = { 2138, 2}, - .SVE_HISTCNT = { 2140, 2}, - .SVE_HISTSEG = { 2142, 1}, - .SME_SMSTART = { 2143, 1}, - .SME_SMSTOP = { 2144, 1}, - .SME_RDSVL = { 2145, 1}, - .SME_ADDHA = { 2146, 1}, - .SME_ADDVA = { 2147, 1}, - .SME_ZERO = { 2148, 1}, - .SME_FMOPA = { 2149, 1}, - .SME_FMOPS = { 2150, 1}, - .SME_BFMOPA = { 2151, 1}, - .SME_BFMOPS = { 2152, 1}, - .SME_SMOPA = { 2153, 2}, - .SME_SMOPS = { 2155, 2}, - .SME_UMOPA = { 2157, 2}, - .SME_UMOPS = { 2159, 2}, - .SME_USMOPA = { 2161, 1}, - .SME_SUMOPA = { 2162, 1}, - .SME_LDR_ZA = { 2163, 1}, - .SME_STR_ZA = { 2164, 1}, - .SVE_FMLA_IDX_H = { 2165, 1}, - .SVE_FMLA_IDX_S = { 2166, 1}, - .SVE_FMLA_IDX_D = { 2167, 1}, - .SVE_FMLS_IDX_H = { 2168, 1}, - .SVE_FMLS_IDX_S = { 2169, 1}, - .SVE_FMLS_IDX_D = { 2170, 1}, - .SVE_LD1B_GATHER_S = { 2171, 1}, - .SVE_LD1B_GATHER_D = { 2172, 1}, - .SVE_LD1H_GATHER_S = { 2173, 1}, - .SVE_LD1H_GATHER_D = { 2174, 1}, - .SVE_LD1W_GATHER_S = { 2175, 1}, - .SVE_LD1W_GATHER_D = { 2176, 1}, - .SVE_LD1D_GATHER_D = { 2177, 1}, - .SVE_LD1SB_GATHER_S = { 2178, 1}, - .SVE_LD1SB_GATHER_D = { 2179, 1}, - .SVE_LD1SH_GATHER_S = { 2180, 1}, - .SVE_LD1SH_GATHER_D = { 2181, 1}, - .SVE_LD1SW_GATHER_D = { 2182, 1}, - .SVE_ST1B_SCATTER_S = { 2183, 1}, - .SVE_ST1B_SCATTER_D = { 2184, 1}, - .SVE_ST1H_SCATTER_S = { 2185, 1}, - .SVE_ST1H_SCATTER_D = { 2186, 1}, - .SVE_ST1W_SCATTER_S = { 2187, 1}, - .SVE_ST1W_SCATTER_D = { 2188, 1}, - .SVE_ST1D_SCATTER_D = { 2189, 1}, - .SME_LD1B_TILE = { 2190, 1}, - .SME_LD1H_TILE = { 2191, 1}, - .SME_LD1W_TILE = { 2192, 1}, - .SME_LD1D_TILE = { 2193, 1}, - .SME_LD1Q_TILE = { 2194, 1}, - .SME_ST1B_TILE = { 2195, 1}, - .SME_ST1H_TILE = { 2196, 1}, - .SME_ST1W_TILE = { 2197, 1}, - .SME_ST1D_TILE = { 2198, 1}, - .SME_ST1Q_TILE = { 2199, 1}, - .SME_MOVA_Z_FROM_TILE = { 2200, 1}, - .SME_MOVA_TILE_FROM_Z = { 2201, 1}, - .FCMLA_4H = { 2202, 1}, - .FCMLA_8H = { 2203, 1}, - .FCMLA_4S = { 2204, 1}, - .FCMLA_2D = { 2205, 1}, - .FCADD_4H = { 2206, 1}, - .FCADD_8H = { 2207, 1}, - .FCADD_4S = { 2208, 1}, - .FCADD_2D = { 2209, 1}, - .SVE_PRFB = { 2210, 1}, - .SVE_PRFH = { 2211, 1}, - .SVE_PRFW = { 2212, 1}, - .SVE_PRFD = { 2213, 1}, - .SVE_LDNT1B = { 2214, 1}, - .SVE_LDNT1H = { 2215, 1}, - .SVE_LDNT1W = { 2216, 1}, - .SVE_LDNT1D = { 2217, 1}, - .SVE_STNT1B = { 2218, 1}, - .SVE_STNT1H = { 2219, 1}, - .SVE_STNT1W = { 2220, 1}, - .SVE_STNT1D = { 2221, 1}, - .SVE_EXT = { 2222, 1}, - .SVE_SPLICE = { 2223, 1}, - .SVE_INDEX_II = { 2224, 1}, - .SVE_INDEX_IR = { 2225, 1}, - .SVE_INDEX_RI = { 2226, 1}, - .SVE_INDEX_RR = { 2227, 1}, - .SVE_BSL = { 2228, 1}, - .SVE_BSL1N = { 2229, 1}, - .SVE_BSL2N = { 2230, 1}, - .SVE_NBSL = { 2231, 1}, - .SVE_PMUL_VEC = { 2232, 1}, - .SVE_PMULLB = { 2233, 1}, - .SVE_PMULLT = { 2234, 1}, - .SVE_BFCVT = { 2235, 1}, - .SVE_BFCVTNT = { 2236, 1}, - .LDRAA = { 2237, 1}, - .LDRAB = { 2238, 1}, - .LDRAA_PRE = { 2239, 1}, - .LDRAB_PRE = { 2240, 1}, - .TSTART = { 2241, 1}, - .TCOMMIT = { 2242, 1}, - .TCANCEL = { 2243, 1}, - .TTEST = { 2244, 1}, - .WFET = { 2245, 1}, - .WFIT = { 2246, 1}, - .BC_COND = { 2247, 1}, - .UXTB = { 2248, 1}, - .UXTH = { 2249, 1}, - .UXTW = { 2250, 1}, - .SXTB = { 2251, 1}, - .SXTH = { 2252, 1}, - .SXTW = { 2253, 1}, - .ADC = { 2254, 2}, - .ADCS = { 2256, 2}, - .SBC = { 2258, 2}, - .SBCS = { 2260, 2}, - .NGC = { 2262, 2}, - .NGCS = { 2264, 2}, - .LDAPUR = { 2266, 2}, - .STLUR = { 2268, 2}, - .LDAPURB = { 2270, 1}, - .STLURB = { 2271, 1}, - .LDAPURH = { 2272, 1}, - .STLURH = { 2273, 1}, - .LDAPURSB = { 2274, 2}, - .LDAPURSH = { 2276, 2}, - .LDAPURSW = { 2278, 1}, - .SVE_BFADD = { 2279, 1}, - .SVE_BFSUB = { 2280, 1}, - .SVE_BFMUL = { 2281, 1}, - .SVE_BFMLA = { 2282, 1}, - .SVE_BFMLS = { 2283, 1}, - .SB = { 2284, 1}, - .CSDB = { 2285, 1}, - .DGH = { 2286, 1}, - .PSB_CSYNC = { 2287, 1}, - .TSB_CSYNC = { 2288, 1}, - .BTI_J = { 2289, 1}, - .BTI_C = { 2290, 1}, - .BTI_JC = { 2291, 1}, - .MOV_V_ALIAS = { 2292, 2}, - .NOT_V_ALIAS = { 2294, 2}, - .LSL_IMM = { 2296, 2}, - .LSR_IMM = { 2298, 2}, - .ASR_IMM = { 2300, 2}, - .ROR_IMM = { 2302, 2}, - .SVE_BFADD_UNPRED = { 2304, 1}, - .SVE_BFSUB_UNPRED = { 2305, 1}, - .SVE_BFMUL_UNPRED = { 2306, 1}, - .SVE_BFCLAMP = { 2307, 1}, - .SVE_BFMAXNM = { 2308, 1}, - .SVE_BFMINNM = { 2309, 1}, - .SME2_LUTI2_B = { 2310, 1}, - .SME2_LUTI4_B = { 2311, 1}, - .SME2_LD1B_X2 = { 2312, 1}, - .SME2_LD1H_X2 = { 2313, 1}, - .SME2_LD1W_X2 = { 2314, 1}, - .SME2_LD1D_X2 = { 2315, 1}, - .SME2_LD1B_X4 = { 2316, 1}, - .SME2_LD1H_X4 = { 2317, 1}, - .SME2_LD1W_X4 = { 2318, 1}, - .SME2_LD1D_X4 = { 2319, 1}, - .SME2_ST1B_X2 = { 2320, 1}, - .SME2_ST1H_X2 = { 2321, 1}, - .SME2_ST1W_X2 = { 2322, 1}, - .SME2_ST1D_X2 = { 2323, 1}, - .SME2_ST1B_X4 = { 2324, 1}, - .SME2_ST1H_X4 = { 2325, 1}, - .SME2_ST1W_X4 = { 2326, 1}, - .SME2_ST1D_X4 = { 2327, 1}, - .SME2_ZIP_3 = { 2328, 1}, - .SME2_ZIP_4 = { 2329, 1}, - .SME2_UZP_3 = { 2330, 1}, - .SME2_UZP_4 = { 2331, 1}, - .TLBI_RPALOS = { 2332, 1}, - .TLBI_RPAOS = { 2333, 1}, - .AT_S1E1A = { 2334, 1}, - .DC_CIPAPA = { 2335, 1}, - .DC_CIGDPAPA = { 2336, 1}, - .TLBI_PAALL = { 2337, 1}, - .TLBI_PAALLOS = { 2338, 1}, - .AMX_LDX = { 2339, 1}, - .AMX_LDY = { 2340, 1}, - .AMX_STX = { 2341, 1}, - .AMX_STY = { 2342, 1}, - .AMX_LDZ = { 2343, 1}, - .AMX_STZ = { 2344, 1}, - .AMX_LDZI = { 2345, 1}, - .AMX_STZI = { 2346, 1}, - .AMX_EXTRX = { 2347, 1}, - .AMX_EXTRY = { 2348, 1}, - .AMX_FMA64 = { 2349, 1}, - .AMX_FMS64 = { 2350, 1}, - .AMX_FMA32 = { 2351, 1}, - .AMX_FMS32 = { 2352, 1}, - .AMX_MAC16 = { 2353, 1}, - .AMX_FMA16 = { 2354, 1}, - .AMX_FMS16 = { 2355, 1}, - .AMX_SET = { 2356, 1}, - .AMX_CLR = { 2357, 1}, - .AMX_VECINT = { 2358, 1}, - .AMX_VECFP = { 2359, 1}, - .AMX_MATINT = { 2360, 1}, - .AMX_MATFP = { 2361, 1}, - .AMX_GENLUT = { 2362, 1}, - .CPYP = { 2363, 1}, - .CPYM = { 2364, 1}, - .CPYE = { 2365, 1}, - .CPYFP = { 2366, 1}, - .CPYFM = { 2367, 1}, - .CPYFE = { 2368, 1}, - .SETP = { 2369, 1}, - .SETM = { 2370, 1}, - .SETE = { 2371, 1}, - .DC_IVAC = { 2372, 1}, - .DC_ISW = { 2373, 1}, - .DC_CSW = { 2374, 1}, - .DC_CISW = { 2375, 1}, - .DC_ZVA = { 2376, 1}, - .DC_CVAC = { 2377, 1}, - .DC_CVAU = { 2378, 1}, - .DC_CIVAC = { 2379, 1}, - .IC_IALLUIS = { 2380, 1}, - .IC_IALLU = { 2381, 1}, - .IC_IVAU = { 2382, 1}, - .AT_S1E1R = { 2383, 1}, - .AT_S1E1W = { 2384, 1}, - .AT_S1E0R = { 2385, 1}, - .AT_S1E0W = { 2386, 1}, - .AT_S1E2R = { 2387, 1}, - .AT_S1E2W = { 2388, 1}, - .AT_S1E3R = { 2389, 1}, - .AT_S1E3W = { 2390, 1}, - .AT_S12E1R = { 2391, 1}, - .AT_S12E1W = { 2392, 1}, - .AT_S12E0R = { 2393, 1}, - .AT_S12E0W = { 2394, 1}, - .TLBI_VMALLE1 = { 2395, 1}, - .TLBI_VMALLE1IS = { 2396, 1}, - .TLBI_VAE1 = { 2397, 1}, - .TLBI_VAE1IS = { 2398, 1}, - .TLBI_ASIDE1 = { 2399, 1}, - .TLBI_ASIDE1IS = { 2400, 1}, - .TLBI_VAAE1 = { 2401, 1}, - .TLBI_VAAE1IS = { 2402, 1}, - .TLBI_VALE1 = { 2403, 1}, - .TLBI_VALE1IS = { 2404, 1}, - .TLBI_VAALE1 = { 2405, 1}, - .TLBI_VAALE1IS = { 2406, 1}, - .TLBI_ALLE1 = { 2407, 1}, - .TLBI_ALLE1IS = { 2408, 1}, - .TLBI_ALLE2 = { 2409, 1}, - .TLBI_ALLE2IS = { 2410, 1}, - .TLBI_ALLE3 = { 2411, 1}, - .TLBI_ALLE3IS = { 2412, 1}, - .PRFM = { 2413, 1}, - .PRFUM = { 2414, 1}, - .PRFM_LIT = { 2415, 1}, - .MOV_REG = { 2416, 2}, - .MOV_BITMASK = { 2418, 2}, - .MVN = { 2420, 2}, - .NEG_SR = { 2422, 2}, - .NEGS = { 2424, 2}, - .CMP_SR = { 2426, 2}, - .CMP_ER = { 2428, 2}, - .CMP_IMM = { 2430, 2}, - .CMN_SR = { 2432, 2}, - .CMN_ER = { 2434, 2}, - .CMN_IMM = { 2436, 2}, - .TST_SR = { 2438, 2}, + .INVALID = { 0, 0}, + .ADD = { 0, 21}, + .ADDS = { 21, 6}, + .SUB = { 27, 18}, + .SUBS = { 45, 6}, + .MOVZ = { 51, 2}, + .MOVN = { 53, 2}, + .MOVK = { 55, 2}, + .ADR = { 57, 1}, + .ADRP = { 58, 1}, + .AND = { 59, 7}, + .ANDS = { 66, 5}, + .ORR = { 71, 7}, + .EOR = { 78, 7}, + .BIC = { 85, 5}, + .BICS = { 90, 3}, + .ORN = { 93, 4}, + .EON = { 97, 2}, + .LSL = { 99, 8}, + .LSR = { 107, 8}, + .ASR = { 115, 8}, + .ROR = { 123, 4}, + .UDIV = { 127, 4}, + .SDIV = { 131, 4}, + .MADD = { 135, 2}, + .MSUB = { 137, 2}, + .SMADDL = { 139, 1}, + .SMSUBL = { 140, 1}, + .UMADDL = { 141, 1}, + .UMSUBL = { 142, 1}, + .SMULH = { 143, 5}, + .UMULH = { 148, 5}, + .CLZ = { 153, 12}, + .CLS = { 165, 12}, + .RBIT = { 177, 4}, + .REV = { 181, 7}, + .REV16 = { 188, 4}, + .REV32 = { 192, 5}, + .CSEL = { 197, 2}, + .CSINC = { 199, 2}, + .CSINV = { 201, 2}, + .CSNEG = { 203, 2}, + .CCMP = { 205, 4}, + .CCMN = { 209, 4}, + .EXTR = { 213, 2}, + .B = { 215, 1}, + .BL = { 216, 1}, + .BR = { 217, 1}, + .BLR = { 218, 1}, + .RET = { 219, 2}, + .B_COND = { 221, 1}, + .CBZ = { 222, 2}, + .CBNZ = { 224, 2}, + .TBZ = { 226, 1}, + .TBNZ = { 227, 1}, + .LDR = { 228, 18}, + .STR = { 246, 16}, + .LDRB = { 262, 4}, + .STRB = { 266, 4}, + .LDRSB = { 270, 4}, + .LDRH = { 274, 4}, + .STRH = { 278, 4}, + .LDRSH = { 282, 4}, + .LDRSW = { 286, 2}, + .LDP = { 288, 9}, + .STP = { 297, 9}, + .LDPSW = { 306, 3}, + .LDAR = { 309, 2}, + .STLR = { 311, 2}, + .LDARB = { 313, 1}, + .STLRB = { 314, 1}, + .LDARH = { 315, 1}, + .STLRH = { 316, 1}, + .LDXR = { 317, 2}, + .STXR = { 319, 2}, + .LDAXR = { 321, 2}, + .STLXR = { 323, 2}, + .NOP = { 325, 1}, + .YIELD = { 326, 1}, + .WFE = { 327, 1}, + .WFI = { 328, 1}, + .SEV = { 329, 1}, + .SEVL = { 330, 1}, + .HINT = { 331, 1}, + .MRS = { 332, 1}, + .MSR = { 333, 2}, + .ISB = { 335, 1}, + .DSB = { 336, 1}, + .DMB = { 337, 1}, + .SVC = { 338, 1}, + .HVC = { 339, 1}, + .SMC = { 340, 1}, + .BRK = { 341, 1}, + .HLT = { 342, 1}, + .ERET = { 343, 1}, + .FMOV = { 344, 15}, + .FABS = { 359, 11}, + .FNEG = { 370, 11}, + .FSQRT = { 381, 11}, + .FADD = { 392, 12}, + .FSUB = { 404, 12}, + .FMUL = { 416, 12}, + .FDIV = { 428, 9}, + .FNMUL = { 437, 3}, + .FMADD = { 440, 3}, + .FMSUB = { 443, 3}, + .FNMADD = { 446, 3}, + .FNMSUB = { 449, 3}, + .FCMP = { 452, 3}, + .FCMPE = { 455, 3}, + .FCSEL = { 458, 3}, + .FMAX = { 461, 11}, + .FMIN = { 472, 11}, + .FMAXNM = { 483, 11}, + .FMINNM = { 494, 11}, + .FCVT = { 505, 6}, + .SCVTF = { 511, 10}, + .UCVTF = { 521, 10}, + .FCVTZS = { 531, 10}, + .FCVTZU = { 541, 10}, + .FCVTAS = { 551, 11}, + .FCVTAU = { 562, 11}, + .FCVTNS = { 573, 11}, + .FCVTNU = { 584, 11}, + .FCVTPS = { 595, 11}, + .FCVTPU = { 606, 11}, + .FCVTMS = { 617, 11}, + .FCVTMU = { 628, 11}, + .FRINTA = { 639, 11}, + .FRINTI = { 650, 11}, + .FRINTM = { 661, 11}, + .FRINTN = { 672, 11}, + .FRINTP = { 683, 11}, + .FRINTX = { 694, 11}, + .FRINTZ = { 705, 11}, + .TST = { 716, 4}, + .LDUR = { 720, 5}, + .STUR = { 725, 5}, + .LDURB = { 730, 1}, + .STURB = { 731, 1}, + .LDURSB = { 732, 2}, + .LDURH = { 734, 1}, + .STURH = { 735, 1}, + .LDURSH = { 736, 2}, + .LDURSW = { 738, 1}, + .LDNP = { 739, 2}, + .STNP = { 741, 2}, + .LDXP = { 743, 2}, + .STXP = { 745, 2}, + .LDAXP = { 747, 2}, + .STLXP = { 749, 2}, + .LDXRB = { 751, 1}, + .STXRB = { 752, 1}, + .LDAXRB = { 753, 1}, + .STLXRB = { 754, 1}, + .LDXRH = { 755, 1}, + .STXRH = { 756, 1}, + .LDAXRH = { 757, 1}, + .STLXRH = { 758, 1}, + .LDAPR = { 759, 2}, + .LDAPRB = { 761, 1}, + .LDAPRH = { 762, 1}, + .LDADD = { 763, 2}, + .LDADDA = { 765, 2}, + .LDADDL = { 767, 2}, + .LDADDAL = { 769, 2}, + .LDCLR = { 771, 2}, + .LDCLRA = { 773, 2}, + .LDCLRL = { 775, 2}, + .LDCLRAL = { 777, 2}, + .LDEOR = { 779, 2}, + .LDEORA = { 781, 2}, + .LDEORL = { 783, 2}, + .LDEORAL = { 785, 2}, + .LDSET = { 787, 2}, + .LDSETA = { 789, 2}, + .LDSETL = { 791, 2}, + .LDSETAL = { 793, 2}, + .LDSMAX = { 795, 2}, + .LDSMAXA = { 797, 2}, + .LDSMAXL = { 799, 2}, + .LDSMAXAL = { 801, 2}, + .LDSMIN = { 803, 2}, + .LDSMINA = { 805, 2}, + .LDSMINL = { 807, 2}, + .LDSMINAL = { 809, 2}, + .LDUMAX = { 811, 2}, + .LDUMAXA = { 813, 2}, + .LDUMAXL = { 815, 2}, + .LDUMAXAL = { 817, 2}, + .LDUMIN = { 819, 2}, + .LDUMINA = { 821, 2}, + .LDUMINL = { 823, 2}, + .LDUMINAL = { 825, 2}, + .SWP = { 827, 2}, + .SWPA = { 829, 2}, + .SWPL = { 831, 2}, + .SWPAL = { 833, 2}, + .CAS = { 835, 2}, + .CASA = { 837, 2}, + .CASL = { 839, 2}, + .CASAL = { 841, 2}, + .CASB = { 843, 1}, + .CASAB = { 844, 1}, + .CASLB = { 845, 1}, + .CASALB = { 846, 1}, + .CASH = { 847, 1}, + .CASAH = { 848, 1}, + .CASLH = { 849, 1}, + .CASALH = { 850, 1}, + .CASP = { 851, 2}, + .CASPA = { 853, 2}, + .CASPL = { 855, 2}, + .CASPAL = { 857, 2}, + .PACIA = { 859, 1}, + .PACIB = { 860, 1}, + .PACDA = { 861, 1}, + .PACDB = { 862, 1}, + .PACIZA = { 863, 1}, + .PACIZB = { 864, 1}, + .PACDZA = { 865, 1}, + .PACDZB = { 866, 1}, + .AUTIA = { 867, 1}, + .AUTIB = { 868, 1}, + .AUTDA = { 869, 1}, + .AUTDB = { 870, 1}, + .AUTIZA = { 871, 1}, + .AUTIZB = { 872, 1}, + .AUTDZA = { 873, 1}, + .AUTDZB = { 874, 1}, + .PACIASP = { 875, 1}, + .PACIBSP = { 876, 1}, + .AUTIASP = { 877, 1}, + .AUTIBSP = { 878, 1}, + .PACIA1716 = { 879, 1}, + .PACIB1716 = { 880, 1}, + .AUTIA1716 = { 881, 1}, + .AUTIB1716 = { 882, 1}, + .PACGA = { 883, 1}, + .XPACI = { 884, 1}, + .XPACD = { 885, 1}, + .XPACLRI = { 886, 1}, + .RETAA = { 887, 1}, + .RETAB = { 888, 1}, + .BRAA = { 889, 1}, + .BRAB = { 890, 1}, + .BRAAZ = { 891, 1}, + .BRABZ = { 892, 1}, + .BLRAA = { 893, 1}, + .BLRAB = { 894, 1}, + .BLRAAZ = { 895, 1}, + .BLRABZ = { 896, 1}, + .ERETAA = { 897, 1}, + .ERETAB = { 898, 1}, + .BTI = { 899, 1}, + .IRG = { 900, 1}, + .ADDG = { 901, 1}, + .SUBG = { 902, 1}, + .GMI = { 903, 1}, + .SUBP = { 904, 1}, + .SUBPS = { 905, 1}, + .LDG = { 906, 1}, + .STG = { 907, 1}, + .ST2G = { 908, 1}, + .STZG = { 909, 1}, + .STZ2G = { 910, 1}, + .STGP = { 911, 1}, + .LDGM = { 912, 1}, + .STGM = { 913, 1}, + .STZGM = { 914, 1}, + .CRC32B = { 915, 1}, + .CRC32H = { 916, 1}, + .CRC32W = { 917, 1}, + .CRC32X = { 918, 1}, + .CRC32CB = { 919, 1}, + .CRC32CH = { 920, 1}, + .CRC32CW = { 921, 1}, + .CRC32CX = { 922, 1}, + .AESE = { 923, 2}, + .AESD = { 925, 2}, + .AESMC = { 927, 2}, + .AESIMC = { 929, 2}, + .SHA1H = { 931, 1}, + .SHA1C = { 932, 1}, + .SHA1P = { 933, 1}, + .SHA1M = { 934, 1}, + .SHA1SU0 = { 935, 1}, + .SHA1SU1 = { 936, 1}, + .SHA256H = { 937, 1}, + .SHA256H2 = { 938, 1}, + .SHA256SU0 = { 939, 1}, + .SHA256SU1 = { 940, 1}, + .SHA512H = { 941, 1}, + .SHA512H2 = { 942, 1}, + .SHA512SU0 = { 943, 1}, + .SHA512SU1 = { 944, 1}, + .EOR3 = { 945, 2}, + .BCAX = { 947, 2}, + .RAX1 = { 949, 1}, + .XAR = { 950, 5}, + .SM3PARTW1 = { 955, 1}, + .SM3PARTW2 = { 956, 1}, + .SM3SS1 = { 957, 1}, + .SM3TT1A = { 958, 1}, + .SM3TT1B = { 959, 1}, + .SM3TT2A = { 960, 1}, + .SM3TT2B = { 961, 1}, + .SM4E = { 962, 1}, + .SM4EKEY = { 963, 1}, + .PMULL = { 964, 2}, + .PMULL2 = { 966, 2}, + .BFCVT = { 968, 2}, + .BFDOT = { 970, 1}, + .BFMMLA = { 971, 1}, + .BFMLALB = { 972, 1}, + .BFMLALT = { 973, 1}, + .BFCVTN = { 974, 1}, + .BFCVTN2 = { 975, 1}, + .MUL = { 976, 7}, + .MLA = { 983, 6}, + .MLS = { 989, 6}, + .NEG = { 995, 13}, + .ABS = { 1008, 11}, + .SHADD = { 1019, 6}, + .UHADD = { 1025, 6}, + .SHSUB = { 1031, 6}, + .UHSUB = { 1037, 6}, + .SRHADD = { 1043, 6}, + .URHADD = { 1049, 6}, + .SQADD = { 1055, 11}, + .UQADD = { 1066, 11}, + .SQSUB = { 1077, 11}, + .UQSUB = { 1088, 11}, + .SMAX = { 1099, 10}, + .UMAX = { 1109, 10}, + .SMIN = { 1119, 10}, + .UMIN = { 1129, 10}, + .SABD = { 1139, 10}, + .UABD = { 1149, 10}, + .SABA = { 1159, 6}, + .UABA = { 1165, 6}, + .ADDP = { 1171, 7}, + .ADDV = { 1178, 5}, + .SADDLP = { 1183, 6}, + .UADDLP = { 1189, 6}, + .SADALP = { 1195, 6}, + .UADALP = { 1201, 6}, + .SADDLV = { 1207, 5}, + .UADDLV = { 1212, 5}, + .SMAXV = { 1217, 5}, + .UMAXV = { 1222, 5}, + .SMINV = { 1227, 5}, + .UMINV = { 1232, 5}, + .SMAXP = { 1237, 6}, + .UMAXP = { 1243, 6}, + .SMINP = { 1249, 6}, + .UMINP = { 1255, 6}, + .SADDL = { 1261, 3}, + .SADDL2 = { 1264, 3}, + .UADDL = { 1267, 3}, + .UADDL2 = { 1270, 3}, + .SSUBL = { 1273, 3}, + .SSUBL2 = { 1276, 3}, + .USUBL = { 1279, 3}, + .USUBL2 = { 1282, 3}, + .SADDW = { 1285, 3}, + .SADDW2 = { 1288, 3}, + .UADDW = { 1291, 3}, + .UADDW2 = { 1294, 3}, + .SSUBW = { 1297, 3}, + .SSUBW2 = { 1300, 3}, + .USUBW = { 1303, 3}, + .USUBW2 = { 1306, 3}, + .RADDHN = { 1309, 3}, + .RADDHN2 = { 1312, 3}, + .RSUBHN = { 1315, 3}, + .RSUBHN2 = { 1318, 3}, + .ADDHN = { 1321, 3}, + .ADDHN2 = { 1324, 3}, + .SUBHN = { 1327, 3}, + .SUBHN2 = { 1330, 3}, + .XTN = { 1333, 3}, + .XTN2 = { 1336, 3}, + .SQXTN = { 1339, 3}, + .SQXTN2 = { 1342, 3}, + .UQXTN = { 1345, 3}, + .UQXTN2 = { 1348, 3}, + .SQXTUN = { 1351, 3}, + .SQXTUN2 = { 1354, 3}, + .SMULL = { 1357, 3}, + .SMULL2 = { 1360, 3}, + .UMULL = { 1363, 3}, + .UMULL2 = { 1366, 3}, + .SMLAL = { 1369, 3}, + .SMLAL2 = { 1372, 3}, + .UMLAL = { 1375, 3}, + .UMLAL2 = { 1378, 3}, + .SMLSL = { 1381, 3}, + .SMLSL2 = { 1384, 3}, + .UMLSL = { 1387, 3}, + .UMLSL2 = { 1390, 3}, + .SQDMULL = { 1393, 2}, + .SQDMULL2 = { 1395, 2}, + .SQDMLAL = { 1397, 2}, + .SQDMLAL2 = { 1399, 2}, + .SQDMLSL = { 1401, 2}, + .SQDMLSL2 = { 1403, 2}, + .SQDMULH = { 1405, 4}, + .SQRDMULH = { 1409, 4}, + .SDOT = { 1413, 2}, + .UDOT = { 1415, 2}, + .USDOT = { 1417, 2}, + .FMLA = { 1419, 8}, + .FMLS = { 1427, 8}, + .FMULX = { 1435, 5}, + .FMAXP = { 1440, 5}, + .FMINP = { 1445, 5}, + .FMAXNMP = { 1450, 5}, + .FMINNMP = { 1455, 5}, + .FMAXV = { 1460, 3}, + .FMINV = { 1463, 3}, + .FMAXNMV = { 1466, 3}, + .FMINNMV = { 1469, 3}, + .FRECPE = { 1472, 5}, + .FRSQRTE = { 1477, 5}, + .FRECPS = { 1482, 8}, + .FRSQRTS = { 1490, 8}, + .FRECPX = { 1498, 6}, + .FADDP = { 1504, 5}, + .FCVTL = { 1509, 2}, + .FCVTL2 = { 1511, 2}, + .FCVTN = { 1513, 2}, + .FCVTN2 = { 1515, 2}, + .FCVTXN = { 1517, 1}, + .FCVTXN2 = { 1518, 1}, + .FCMEQ = { 1519, 8}, + .FCMGE = { 1527, 8}, + .FCMGT = { 1535, 8}, + .FCMLE = { 1543, 8}, + .FCMLT = { 1551, 8}, + .FACGE = { 1559, 5}, + .FACGT = { 1564, 5}, + .CMEQ = { 1569, 4}, + .CMGE = { 1573, 7}, + .CMGT = { 1580, 2}, + .CMHI = { 1582, 2}, + .CMHS = { 1584, 7}, + .CMLE = { 1591, 7}, + .CMLT = { 1598, 7}, + .CMTST = { 1605, 7}, + .MVN = { 1612, 4}, + .BIT = { 1616, 1}, + .BIF = { 1617, 1}, + .BSL = { 1618, 2}, + .SHL = { 1620, 7}, + .SQSHL = { 1627, 7}, + .SQSHLU = { 1634, 7}, + .SRSHL = { 1641, 7}, + .URSHL = { 1648, 7}, + .SSHR = { 1655, 7}, + .USHR = { 1662, 7}, + .SSRA = { 1669, 7}, + .USRA = { 1676, 7}, + .SRSHR = { 1683, 7}, + .URSHR = { 1690, 7}, + .SRSRA = { 1697, 7}, + .URSRA = { 1704, 7}, + .SSHL = { 1711, 7}, + .USHL = { 1718, 7}, + .SLI = { 1725, 7}, + .SRI = { 1732, 7}, + .SSHLL = { 1739, 3}, + .SSHLL2 = { 1742, 3}, + .USHLL = { 1745, 3}, + .USHLL2 = { 1748, 3}, + .SXTL = { 1751, 3}, + .SXTL2 = { 1754, 3}, + .UXTL = { 1757, 3}, + .UXTL2 = { 1760, 3}, + .SHRN = { 1763, 3}, + .SHRN2 = { 1766, 3}, + .RSHRN = { 1769, 3}, + .RSHRN2 = { 1772, 3}, + .SQSHRN = { 1775, 3}, + .SQSHRN2 = { 1778, 3}, + .UQSHRN = { 1781, 3}, + .UQSHRN2 = { 1784, 3}, + .SQRSHRN = { 1787, 3}, + .SQRSHRN2 = { 1790, 3}, + .UQRSHRN = { 1793, 3}, + .UQRSHRN2 = { 1796, 3}, + .SQSHRUN = { 1799, 3}, + .SQSHRUN2 = { 1802, 3}, + .SQRSHRUN = { 1805, 3}, + .SQRSHRUN2 = { 1808, 3}, + .DUP = { 1811, 18}, + .INS = { 1829, 8}, + .MOV = { 1837, 12}, + .EXT = { 1849, 4}, + .TBL = { 1853, 6}, + .TBX = { 1859, 3}, + .ZIP1 = { 1862, 12}, + .ZIP2 = { 1874, 12}, + .UZP1 = { 1886, 12}, + .UZP2 = { 1898, 12}, + .TRN1 = { 1910, 12}, + .TRN2 = { 1922, 12}, + .NOT = { 1934, 3}, + .REV64 = { 1937, 6}, + .CNT = { 1943, 6}, + .URECPE = { 1949, 2}, + .URSQRTE = { 1951, 2}, + .MOVI = { 1953, 7}, + .MVNI = { 1960, 4}, + .LD1 = { 1964, 8}, + .LD2 = { 1972, 5}, + .LD3 = { 1977, 5}, + .LD4 = { 1982, 5}, + .ST1 = { 1987, 8}, + .ST2 = { 1995, 5}, + .ST3 = { 2000, 5}, + .ST4 = { 2005, 5}, + .LD1R = { 2010, 1}, + .LD2R = { 2011, 1}, + .LD3R = { 2012, 1}, + .LD4R = { 2013, 1}, + .SUBR = { 2014, 4}, + .ASRR = { 2018, 4}, + .LSLR = { 2022, 4}, + .LSRR = { 2026, 4}, + .FTSMUL = { 2030, 3}, + .FSUBR = { 2033, 3}, + .FDIVR = { 2036, 3}, + .FNMLA = { 2039, 3}, + .FNMLS = { 2042, 3}, + .NAND = { 2045, 1}, + .NOR = { 2046, 1}, + .SEL = { 2047, 1}, + .ORRS = { 2048, 1}, + .EORS = { 2049, 1}, + .NANDS = { 2050, 1}, + .NORS = { 2051, 1}, + .ORNS = { 2052, 1}, + .MOVS = { 2053, 1}, + .PTRUE = { 2054, 1}, + .PTRUES = { 2055, 1}, + .PFALSE = { 2056, 1}, + .PFIRST = { 2057, 1}, + .PNEXT = { 2058, 1}, + .BRKA = { 2059, 1}, + .BRKB = { 2060, 1}, + .BRKAS = { 2061, 1}, + .BRKBS = { 2062, 1}, + .BRKPA = { 2063, 1}, + .BRKPB = { 2064, 1}, + .BRKN = { 2065, 1}, + .RDFFR = { 2066, 1}, + .WRFFR = { 2067, 1}, + .SETFFR = { 2068, 1}, + .CMPEQ = { 2069, 4}, + .CMPNE = { 2073, 4}, + .CMPGE = { 2077, 4}, + .CMPGT = { 2081, 4}, + .CMPLE = { 2085, 4}, + .CMPLT = { 2089, 4}, + .CMPHI = { 2093, 4}, + .CMPHS = { 2097, 4}, + .CMPLO = { 2101, 4}, + .CMPLS = { 2105, 4}, + .FCMNE = { 2109, 3}, + .FCMUO = { 2112, 3}, + .INSR = { 2115, 4}, + .CPY = { 2119, 4}, + .COMPACT = { 2123, 2}, + .LD1B = { 2125, 6}, + .LD1H = { 2131, 6}, + .LD1W = { 2137, 6}, + .LD1D = { 2143, 5}, + .LD1SB = { 2148, 3}, + .LD1SH = { 2151, 3}, + .LD1SW = { 2154, 2}, + .ST1B = { 2156, 6}, + .ST1H = { 2162, 6}, + .ST1W = { 2168, 6}, + .ST1D = { 2174, 5}, + .LDFF1B = { 2179, 1}, + .LDFF1H = { 2180, 1}, + .LDFF1W = { 2181, 1}, + .LDFF1D = { 2182, 1}, + .WHILEGE = { 2183, 1}, + .WHILEGT = { 2184, 1}, + .WHILELE = { 2185, 1}, + .WHILELT = { 2186, 1}, + .WHILEHI = { 2187, 1}, + .WHILEHS = { 2188, 1}, + .WHILELO = { 2189, 1}, + .WHILELS = { 2190, 1}, + .SQRDMLAH = { 2191, 4}, + .SQRDMLSH = { 2195, 4}, + .ADCLB = { 2199, 2}, + .ADCLT = { 2201, 2}, + .SBCLB = { 2203, 2}, + .SBCLT = { 2205, 2}, + .TBL2 = { 2207, 1}, + .MATCH = { 2208, 2}, + .NMATCH = { 2210, 2}, + .HISTCNT = { 2212, 2}, + .HISTSEG = { 2214, 1}, + .SMSTART = { 2215, 1}, + .SMSTOP = { 2216, 1}, + .RDSVL = { 2217, 1}, + .ADDHA = { 2218, 1}, + .ADDVA = { 2219, 1}, + .ZERO = { 2220, 1}, + .FMOPA = { 2221, 1}, + .FMOPS = { 2222, 1}, + .BFMOPA = { 2223, 1}, + .BFMOPS = { 2224, 1}, + .SMOPA = { 2225, 2}, + .SMOPS = { 2227, 2}, + .UMOPA = { 2229, 2}, + .UMOPS = { 2231, 2}, + .USMOPA = { 2233, 1}, + .SUMOPA = { 2234, 1}, + .LD1Q = { 2235, 1}, + .ST1Q = { 2236, 1}, + .MOVA = { 2237, 2}, + .FCMLA = { 2239, 4}, + .FCADD = { 2243, 4}, + .PRFB = { 2247, 1}, + .PRFH = { 2248, 1}, + .PRFW = { 2249, 1}, + .PRFD = { 2250, 1}, + .LDNT1B = { 2251, 1}, + .LDNT1H = { 2252, 1}, + .LDNT1W = { 2253, 1}, + .LDNT1D = { 2254, 1}, + .STNT1B = { 2255, 1}, + .STNT1H = { 2256, 1}, + .STNT1W = { 2257, 1}, + .STNT1D = { 2258, 1}, + .SPLICE = { 2259, 1}, + .INDEX = { 2260, 4}, + .BSL1N = { 2264, 1}, + .BSL2N = { 2265, 1}, + .NBSL = { 2266, 1}, + .PMUL = { 2267, 1}, + .PMULLB = { 2268, 1}, + .PMULLT = { 2269, 1}, + .BFCVTNT = { 2270, 1}, + .LDRAA = { 2271, 2}, + .LDRAB = { 2273, 2}, + .TSTART = { 2275, 1}, + .TCOMMIT = { 2276, 1}, + .TCANCEL = { 2277, 1}, + .TTEST = { 2278, 1}, + .WFET = { 2279, 1}, + .WFIT = { 2280, 1}, + .BC_COND = { 2281, 1}, + .UXTB = { 2282, 1}, + .UXTH = { 2283, 1}, + .UXTW = { 2284, 1}, + .SXTB = { 2285, 1}, + .SXTH = { 2286, 1}, + .SXTW = { 2287, 1}, + .ADC = { 2288, 2}, + .ADCS = { 2290, 2}, + .SBC = { 2292, 2}, + .SBCS = { 2294, 2}, + .NGC = { 2296, 2}, + .NGCS = { 2298, 2}, + .LDAPUR = { 2300, 2}, + .STLUR = { 2302, 2}, + .LDAPURB = { 2304, 1}, + .STLURB = { 2305, 1}, + .LDAPURH = { 2306, 1}, + .STLURH = { 2307, 1}, + .LDAPURSB = { 2308, 2}, + .LDAPURSH = { 2310, 2}, + .LDAPURSW = { 2312, 1}, + .BFADD = { 2313, 2}, + .BFSUB = { 2315, 2}, + .BFMUL = { 2317, 2}, + .BFMLA = { 2319, 1}, + .BFMLS = { 2320, 1}, + .SB = { 2321, 1}, + .CSDB = { 2322, 1}, + .DGH = { 2323, 1}, + .PSB_CSYNC = { 2324, 1}, + .TSB_CSYNC = { 2325, 1}, + .BTI_J = { 2326, 1}, + .BTI_C = { 2327, 1}, + .BTI_JC = { 2328, 1}, + .BFCLAMP = { 2329, 1}, + .BFMAXNM = { 2330, 1}, + .BFMINNM = { 2331, 1}, + .LUTI2 = { 2332, 1}, + .LUTI4 = { 2333, 1}, + .ZIP = { 2334, 2}, + .UZP = { 2336, 2}, + .TLBI_RPALOS = { 2338, 1}, + .TLBI_RPAOS = { 2339, 1}, + .AT_S1E1A = { 2340, 1}, + .DC_CIPAPA = { 2341, 1}, + .DC_CIGDPAPA = { 2342, 1}, + .TLBI_PAALL = { 2343, 1}, + .TLBI_PAALLOS = { 2344, 1}, + .AMX_LDX = { 2345, 1}, + .AMX_LDY = { 2346, 1}, + .AMX_STX = { 2347, 1}, + .AMX_STY = { 2348, 1}, + .AMX_LDZ = { 2349, 1}, + .AMX_STZ = { 2350, 1}, + .AMX_LDZI = { 2351, 1}, + .AMX_STZI = { 2352, 1}, + .AMX_EXTRX = { 2353, 1}, + .AMX_EXTRY = { 2354, 1}, + .AMX_FMA64 = { 2355, 1}, + .AMX_FMS64 = { 2356, 1}, + .AMX_FMA32 = { 2357, 1}, + .AMX_FMS32 = { 2358, 1}, + .AMX_MAC16 = { 2359, 1}, + .AMX_FMA16 = { 2360, 1}, + .AMX_FMS16 = { 2361, 1}, + .AMX_SET = { 2362, 1}, + .AMX_CLR = { 2363, 1}, + .AMX_VECINT = { 2364, 1}, + .AMX_VECFP = { 2365, 1}, + .AMX_MATINT = { 2366, 1}, + .AMX_MATFP = { 2367, 1}, + .AMX_GENLUT = { 2368, 1}, + .CPYP = { 2369, 1}, + .CPYM = { 2370, 1}, + .CPYE = { 2371, 1}, + .CPYFP = { 2372, 1}, + .CPYFM = { 2373, 1}, + .CPYFE = { 2374, 1}, + .SETP = { 2375, 1}, + .SETM = { 2376, 1}, + .SETE = { 2377, 1}, + .DC_IVAC = { 2378, 1}, + .DC_ISW = { 2379, 1}, + .DC_CSW = { 2380, 1}, + .DC_CISW = { 2381, 1}, + .DC_ZVA = { 2382, 1}, + .DC_CVAC = { 2383, 1}, + .DC_CVAU = { 2384, 1}, + .DC_CIVAC = { 2385, 1}, + .IC_IALLUIS = { 2386, 1}, + .IC_IALLU = { 2387, 1}, + .IC_IVAU = { 2388, 1}, + .AT_S1E1R = { 2389, 1}, + .AT_S1E1W = { 2390, 1}, + .AT_S1E0R = { 2391, 1}, + .AT_S1E0W = { 2392, 1}, + .AT_S1E2R = { 2393, 1}, + .AT_S1E2W = { 2394, 1}, + .AT_S1E3R = { 2395, 1}, + .AT_S1E3W = { 2396, 1}, + .AT_S12E1R = { 2397, 1}, + .AT_S12E1W = { 2398, 1}, + .AT_S12E0R = { 2399, 1}, + .AT_S12E0W = { 2400, 1}, + .TLBI_VMALLE1 = { 2401, 1}, + .TLBI_VMALLE1IS = { 2402, 1}, + .TLBI_VAE1 = { 2403, 1}, + .TLBI_VAE1IS = { 2404, 1}, + .TLBI_ASIDE1 = { 2405, 1}, + .TLBI_ASIDE1IS = { 2406, 1}, + .TLBI_VAAE1 = { 2407, 1}, + .TLBI_VAAE1IS = { 2408, 1}, + .TLBI_VALE1 = { 2409, 1}, + .TLBI_VALE1IS = { 2410, 1}, + .TLBI_VAALE1 = { 2411, 1}, + .TLBI_VAALE1IS = { 2412, 1}, + .TLBI_ALLE1 = { 2413, 1}, + .TLBI_ALLE1IS = { 2414, 1}, + .TLBI_ALLE2 = { 2415, 1}, + .TLBI_ALLE2IS = { 2416, 1}, + .TLBI_ALLE3 = { 2417, 1}, + .TLBI_ALLE3IS = { 2418, 1}, + .PRFM = { 2419, 2}, + .PRFUM = { 2421, 1}, + .NEGS = { 2422, 2}, + .CMP = { 2424, 6}, + .CMN = { 2430, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 4f5707b05..ec9f178f9 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -1,10 +1,19 @@ package rexcode_arm64_tablegen // ============================================================================= -// rexcode ยท AArch64 INSTRUCTION_TABLE (v1: base integer + FP scalar) +// rexcode ยท AArch64 INSTRUCTION_TABLE // ============================================================================= // -// One []Form per Mnemonic. A Form fuses an instruction form's Encoding with its +// One []Form per Mnemonic, where a Mnemonic is an ASSEMBLER mnemonic -- so a +// run holds every form that spells that name: ADD carries the immediate, +// shifted-register, extended-register, NEON and SVE forms, LDR carries all +// six addressing modes. The encoder scans the run and takes the first form +// whose operand TYPES match, so order is precedence: list forms in the order +// an assembler resolves them (immediate, then shifted-register, then +// extended-register -- `add w0,w1,w2` is the shifted form, and only the +// extended form can encode SP). +// +// A Form fuses an instruction form's Encoding with its // Clobber, so INSTRUCTION_TABLE[m][i] carries both the bit pattern and the // read/write + side-effect summary for form i of mnemonic m. This replaces the // old pair of index-aligned tables (ENCODING_TABLE[m][i] / CLOBBER_TABLE[m][i]); @@ -95,4650 +104,4010 @@ Form :: struct { INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, - .ADD_IMM = { - {{.ADD_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.ADD_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + .ADD = { + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, - .ADDS_IMM = { - {{.ADDS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + .ADDS = { + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .SUB_IMM = { - {{.SUB_IMM, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.SUB_IMM, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + .SUB = { + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, - .SUBS_IMM = { - {{.SUBS_IMM, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS_IMM, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + .SUBS = { + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, }, - .ADD_SR = { - {{.ADD_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .AND = { + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, - .ADDS_SR = { - {{.ADDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + .ANDS = { + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .SUB_SR = { - {{.SUB_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .ORR = { + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, - .SUBS_SR = { - {{.SUBS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + .EOR = { + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, - .AND_SR = { - {{.AND_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.AND_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .BIC = { + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, - .ANDS_SR = { - {{.ANDS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + .BICS = { + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .ORR_SR = { - {{.ORR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .ORN = { + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, - .EOR_SR = { - {{.EOR_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EOR_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .EON = { + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, }, - .BIC_SR = { - {{.BIC_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.BIC_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .LSL = { + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, - .BICS_SR = { - {{.BICS_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + .LSR = { + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, - .ORN_SR = { - {{.ORN_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORN_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .ASR = { + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, - .EON_SR = { - {{.EON_SR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EON_SR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .ADD_ER = { - {{.ADD_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .ADDS_ER = { - {{.ADDS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SUB_ER = { - {{.SUB_ER, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB_ER, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SUBS_ER = { - {{.SUBS_ER, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS_ER, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .LSLV = { - {{.LSLV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSLV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .LSRV = { - {{.LSRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .ASRV = { - {{.ASRV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ASRV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .RORV = { - {{.RORV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.RORV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + .ROR = { + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, - .CCMP_REG = { - {{.CCMP_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + .CCMP = { + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, - .CCMP_IMM = { - {{.CCMP_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CCMN_REG = { - {{.CCMN_REG, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN_REG, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CCMN_IMM = { - {{.CCMN_IMM, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN_IMM, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + .CCMN = { + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_COND = { - {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - }, - .LDR_LIT = { - {{.LDR_LIT, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, - {{.LDR_LIT, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, - .MSR_IMM = { - {{.MSR_IMM, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .MSR_REG = { - {{.MSR_REG, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + .MSR = { + {{.MSR, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, }, - .FMOV_REG = { - {{.FMOV_REG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV_REG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - }, - .FMOV_IMM = { - {{.FMOV_IMM, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV_IMM, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV_IMM, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, - }, - .FMOV_GEN = { - {{.FMOV_GEN, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV_GEN, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV_GEN, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV_GEN, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + .FMOV = { + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, - .AND_IMM = { - {{.AND_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.AND_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .ANDS_IMM = { - {{.ANDS_IMM, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS_IMM, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .ORR_IMM = { - {{.ORR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ORR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .EOR_IMM = { - {{.EOR_IMM, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.EOR_IMM, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .TST_IMM = { - {{.TST_IMM, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST_IMM, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + .TST = { + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDR_PRE = { - {{.LDR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STR_PRE = { - {{.STR_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDR_POST = { - {{.LDR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STR_POST = { - {{.STR_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR_POST, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDRB_PRE = { - {{.LDRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STRB_PRE = { - {{.STRB_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDRB_POST = { - {{.LDRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STRB_POST = { - {{.STRB_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDRH_PRE = { - {{.LDRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STRH_PRE = { - {{.STRH_PRE, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDRH_POST = { - {{.LDRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .STRH_POST = { - {{.STRH_POST, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - }, - .LDR_REG = { - {{.LDR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .STR_REG = { - {{.STR_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - }, - .LDRB_REG = { - {{.LDRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .STRB_REG = { - {{.STRB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - }, - .LDRH_REG = { - {{.LDRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .STRH_REG = { - {{.STRH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - }, - .LDRSB_REG = { - {{.LDRSB_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDRSH_REG = { - {{.LDRSH_REG, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDRSW_REG = { - {{.LDRSW_REG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDP_PRE = { - {{.LDP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - }, - .STP_PRE = { - {{.STP_PRE, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - }, - .LDP_POST = { - {{.LDP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - }, - .STP_POST = { - {{.STP_POST, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - }, - .LDPSW_PRE = { - {{.LDPSW_PRE, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - }, - .LDPSW_POST = { - {{.LDPSW_POST, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - }, - .FABS_H = { - {{.FABS_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - }, - .FNEG_H = { - {{.FNEG_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - }, - .FSQRT_H = { - {{.FSQRT_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FADD_H = { - {{.FADD_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FSUB_H = { - {{.FSUB_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMUL_H = { - {{.FMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FDIV_H = { - {{.FDIV_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FNMUL_H = { - {{.FNMUL_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMADD_H = { - {{.FMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMSUB_H = { - {{.FMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FNMADD_H = { - {{.FNMADD_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FNMSUB_H = { - {{.FNMSUB_H, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCMP_H = { - {{.FCMP_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - }, - .FCMPE_H = { - {{.FCMPE_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - }, - .FCSEL_H = { - {{.FCSEL_H, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .FMAX_H = { - {{.FMAX_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMIN_H = { - {{.FMIN_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMAXNM_H = { - {{.FMAXNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMINNM_H = { - {{.FMINNM_H, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FCVT_H_S = { - {{.FCVT_H_S, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCVT_H_D = { - {{.FCVT_H_D, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCVT_S_H = { - {{.FCVT_S_H, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCVT_D_H = { - {{.FCVT_D_H, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMOV_H = { - {{.FMOV_H, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - }, - .SCVTF_H = { - {{.SCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - }, - .UCVTF_H = { - {{.UCVTF_H, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - }, - .FCVTZS_H = { - {{.FCVTZS_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTZU_H = { - {{.FCVTZU_H, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, - .ADD_V = { - {{.ADD_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .MUL = { + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, - .SUB_V = { - {{.SUB_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .MLA = { + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, - .MUL_V = { - {{.MUL_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .MLS = { + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, - .MLA_V = { - {{.MLA_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + .NEG = { + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, - .MLS_V = { - {{.MLS_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - }, - .NEG_V = { - {{.NEG_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .ABS_V = { - {{.ABS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + .ABS = { + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, - .ADDP_V = { - {{.ADDP_V, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .ADDP = { + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, - .SMULL_V = { - {{.SMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .SMULL = { + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, - .SMULL2_V = { - {{.SMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .SMULL2 = { + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, - .UMULL_V = { - {{.UMULL_V, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL_V, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL_V, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .UMULL = { + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, - .UMULL2_V = { - {{.UMULL2_V, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2_V, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2_V, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + .UMULL2 = { + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, - .FADD_V = { - {{.FADD_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + .FMLA = { + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, - .FSUB_V = { - {{.FSUB_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMUL_V = { - {{.FMUL_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FDIV_V = { - {{.FDIV_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FNEG_V = { - {{.FNEG_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - }, - .FABS_V = { - {{.FABS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - }, - .FSQRT_V = { - {{.FSQRT_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMLA_V = { - {{.FMLA_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FMLS_V = { - {{.FMLS_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + .FMLS = { + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, - .FMAX_V = { - {{.FMAX_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + .FMAXP = { + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, - .FMIN_V = { - {{.FMIN_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMAXNM_V = { - {{.FMAXNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMINNM_V = { - {{.FMINNM_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMAXP_V = { - {{.FMAXP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .FMINP_V = { - {{.FMINP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + .FMINP = { + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, - .FMAXV_V = { - {{.FMAXV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + .FMAXV = { + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, - .FMINV_V = { - {{.FMINV_V, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV_V, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV_V, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + .FMINV = { + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, }, - .FADDP_V = { - {{.FADDP_V, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP_V, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP_V, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP_V, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP_V, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FRINTA_V = { - {{.FRINTA_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - }, - .FRINTI_V = { - {{.FRINTI_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - }, - .FRINTM_V = { - {{.FRINTM_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - }, - .FRINTN_V = { - {{.FRINTN_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - }, - .FRINTP_V = { - {{.FRINTP_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - }, - .FRINTX_V = { - {{.FRINTX_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - }, - .FRINTZ_V = { - {{.FRINTZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - }, - .SCVTF_V = { - {{.SCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - }, - .UCVTF_V = { - {{.UCVTF_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - }, - .FCVTAS_V = { - {{.FCVTAS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTAU_V = { - {{.FCVTAU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTMS_V = { - {{.FCVTMS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTMU_V = { - {{.FCVTMU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTNS_V = { - {{.FCVTNS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTNU_V = { - {{.FCVTNU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTPS_V = { - {{.FCVTPS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTPU_V = { - {{.FCVTPU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTZS_V = { - {{.FCVTZS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - }, - .FCVTZU_V = { - {{.FCVTZU_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU_V, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU_V, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU_V, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + .FADDP = { + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .AND_V = { - {{.AND_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .ORR_V = { - {{.ORR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .EOR_V = { - {{.EOR_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .BIC_V = { - {{.BIC_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .ORN_V = { - {{.ORN_V, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .MVN_V = { - {{.MVN_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - }, - .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - }, - .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - }, - .SHL_V = { - {{.SHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SQSHL_V = { - {{.SQSHL_V, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL_V, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - }, - .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - }, - .DUP_V = { - {{.DUP_V, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP_V, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, - }, - .MOV_V = { - {{.MOV_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .EXT_V = { - {{.EXT_V, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT_V, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - }, - .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - }, - .NOT_V = { - {{.NOT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .RBIT_V = { - {{.RBIT_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RBIT_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .REV16_V = { - {{.REV16_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV16_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .REV32_V = { - {{.REV32_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .CLS_V = { - {{.CLS_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .CLZ_V = { - {{.CLZ_V, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ_V, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ_V, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ_V, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .URECPE_V = { - {{.URECPE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URECPE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .URSQRTE_V = { - {{.URSQRTE_V, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSQRTE_V, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - }, - .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - }, - .FMOV_V_IMM = { - {{.FMOV_V_IMM, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV_V_IMM, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV_V_IMM, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV_V_IMM, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, - {{.FMOV_V_IMM, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, - }, - .LD1 = { - {{.LD1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD2 = { - {{.LD2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD3 = { - {{.LD3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD4 = { - {{.LD4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .ST1 = { - {{.ST1, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - }, - .ST2 = { - {{.ST2, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - }, - .ST3 = { - {{.ST3, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - }, - .ST4 = { - {{.ST4, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - }, - .LD1R = { - {{.LD1R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD2R = { - {{.LD2R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD3R = { - {{.LD3R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD4R = { - {{.LD4R, {.V_16B, .MEM, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LD1_LANE = { - {{.LD1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - }, - .LD2_LANE = { - {{.LD2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - }, - .LD3_LANE = { - {{.LD3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - }, - .LD4_LANE = { - {{.LD4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - }, - .ST1_LANE = { - {{.ST1_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - }, - .ST2_LANE = { - {{.ST2_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - }, - .ST3_LANE = { - {{.ST3_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - }, - .ST4_LANE = { - {{.ST4_LANE, {.V_ELEM_B, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4_LANE, {.V_ELEM_H, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4_LANE, {.V_ELEM_S, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4_LANE, {.V_ELEM_D, .VEC_INDEX, .MEM, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - }, - .LDR_V = { - {{.LDR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .STR_V = { - {{.STR_V, {.B_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR_V, {.H_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - }, - .LDP_V = { - {{.LDP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - }, - .STP_V = { - {{.STP_V, {.S_REG, .S_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP_V, {.D_REG, .D_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP_V, {.Q_REG, .Q_REG, .MEM, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .LDUR_V = { - {{.LDUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .STUR_V = { - {{.STUR_V, {.S_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR_V, {.D_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR_V, {.Q_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - }, - .SVE_ADD_Z = { - {{.SVE_ADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_SUB_Z = { - {{.SVE_SUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_SUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_SUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_SUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_SQADD_Z = { - {{.SVE_SQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_UQADD_Z = { - {{.SVE_UQADD_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_SQSUB_Z = { - {{.SVE_SQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_UQSUB_Z = { - {{.SVE_UQSUB_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SVE_UQSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_ADD_PRED = { - {{.SVE_ADD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SUB_PRED = { - {{.SVE_SUB_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SUBR_PRED = { - {{.SVE_SUBR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_MUL_PRED = { - {{.SVE_MUL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_MUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_MUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_MUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SMULH_PRED = { - {{.SVE_SMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_UMULH_PRED = { - {{.SVE_UMULH_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMULH_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMULH_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMULH_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SDIV_PRED = { - {{.SVE_SDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_UDIV_PRED = { - {{.SVE_UDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SMAX_PRED = { - {{.SVE_SMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_UMAX_PRED = { - {{.SVE_UMAX_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SMIN_PRED = { - {{.SVE_SMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_UMIN_PRED = { - {{.SVE_UMIN_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SABD_PRED = { - {{.SVE_SABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_SABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_UABD_PRED = { - {{.SVE_UABD_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UABD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UABD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_UABD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_AND_PRED = { - {{.SVE_AND_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ORR_PRED = { - {{.SVE_ORR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_EOR_PRED = { - {{.SVE_EOR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BIC_PRED = { - {{.SVE_BIC_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ASR_PRED = { - {{.SVE_ASR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_LSL_PRED = { - {{.SVE_LSL_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_LSR_PRED = { - {{.SVE_LSR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ASRR_PRED = { - {{.SVE_ASRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_ASRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_LSLR_PRED = { - {{.SVE_LSLR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSLR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSLR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSLR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_LSRR_PRED = { - {{.SVE_LSRR_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSRR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSRR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_LSRR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ABS_PRED = { - {{.SVE_ABS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ABS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ABS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ABS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_NEG_PRED = { - {{.SVE_NEG_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_NEG_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_NEG_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_NEG_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_CLS_PRED = { - {{.SVE_CLS_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLS_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLS_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLS_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_CLZ_PRED = { - {{.SVE_CLZ_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLZ_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLZ_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CLZ_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_CNT_PRED = { - {{.SVE_CNT_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CNT_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CNT_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CNT_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_MOV_PRED = { - {{.SVE_MOV_PRED, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.SVE_MOV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.SVE_MOV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.SVE_MOV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, - }, - .SVE_FADD_Z = { - {{.SVE_FADD_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FADD_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FADD_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FSUB_Z = { - {{.SVE_FSUB_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUB_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUB_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMUL_Z = { - {{.SVE_FMUL_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMUL_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMUL_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FRECPS = { - {{.SVE_FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FRSQRTS = { - {{.SVE_FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FTSMUL = { - {{.SVE_FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FADD_PRED = { - {{.SVE_FADD_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FADD_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FADD_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FSUB_PRED = { - {{.SVE_FSUB_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUB_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUB_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FSUBR_PRED = { - {{.SVE_FSUBR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUBR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSUBR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMUL_PRED = { - {{.SVE_FMUL_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMUL_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMUL_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FDIV_PRED = { - {{.SVE_FDIV_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FDIV_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FDIV_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FDIVR_PRED = { - {{.SVE_FDIVR_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FDIVR_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FDIVR_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMAX_PRED = { - {{.SVE_FMAX_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMAX_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMAX_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMIN_PRED = { - {{.SVE_FMIN_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMIN_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMIN_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMAXNM_PRED = { - {{.SVE_FMAXNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMAXNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMAXNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMINNM_PRED = { - {{.SVE_FMINNM_PRED, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMINNM_PRED, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMINNM_PRED, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FABS_Z = { - {{.SVE_FABS_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_FABS_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_FABS_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_FNEG_Z = { - {{.SVE_FNEG_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_FNEG_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_FNEG_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_FSQRT_Z = { - {{.SVE_FSQRT_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSQRT_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FSQRT_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FRECPX_Z = { - {{.SVE_FRECPX_Z, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.SVE_FRECPX_Z, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.SVE_FRECPX_Z, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - }, - .SVE_FRINTN = { - {{.SVE_FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FRINTP = { - {{.SVE_FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FRINTM = { - {{.SVE_FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FRINTZ = { - {{.SVE_FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FRINTA = { - {{.SVE_FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FRINTX = { - {{.SVE_FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.SVE_FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.SVE_FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - }, - .SVE_FRINTI = { - {{.SVE_FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.SVE_FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.SVE_FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - }, - .SVE_FMLA = { - {{.SVE_FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLS = { - {{.SVE_FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.SVE_FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FNMLA = { - {{.SVE_FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SVE_FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SVE_FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SVE_FNMLS = { - {{.SVE_FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SVE_FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SVE_FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SVE_AND_P = { - {{.SVE_AND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BIC_P = { - {{.SVE_BIC_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ORR_P = { - {{.SVE_ORR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_EOR_P = { - {{.SVE_EOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_NAND_P = { - {{.SVE_NAND_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_NOR_P = { - {{.SVE_NOR_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ORN_P = { - {{.SVE_ORN_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_SEL_P = { - {{.SVE_SEL_P, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_ANDS_P = { - {{.SVE_ANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_BICS_P = { - {{.SVE_BICS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_ORRS_P = { - {{.SVE_ORRS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_EORS_P = { - {{.SVE_EORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_NANDS_P = { - {{.SVE_NANDS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_NORS_P = { - {{.SVE_NORS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_ORNS_P = { - {{.SVE_ORNS_P, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_NOT_P = { - {{.SVE_NOT_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_MOV_P = { - {{.SVE_MOV_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_MOV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, - }, - .SVE_MOVS_P = { - {{.SVE_MOVS_P, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_PTRUE = { - {{.SVE_PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, - }, - .SVE_PTRUES = { - {{.SVE_PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_PFALSE = { - {{.SVE_PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, - }, - .SVE_PFIRST = { - {{.SVE_PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_PNEXT = { - {{.SVE_PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_BRKA = { - {{.SVE_BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_BRKB = { - {{.SVE_BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_BRKAS = { - {{.SVE_BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_BRKBS = { - {{.SVE_BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_BRKPA = { - {{.SVE_BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BRKPB = { - {{.SVE_BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BRKN = { - {{.SVE_BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_RDFFR = { - {{.SVE_RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, - }, - .SVE_WRFFR = { - {{.SVE_WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, - }, - .SVE_SETFFR = { - {{.SVE_SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, - }, - .SVE_CMPEQ = { - {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPNE = { - {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPGE = { - {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPGT = { - {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPLE = { - {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPLT = { - {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPHI = { - {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPHS = { - {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPLO = { - {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_CMPLS = { - {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_FCMEQ = { - {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMNE = { - {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMGE = { - {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMGT = { - {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMLE = { - {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMLT = { - {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.SVE_FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - }, - .SVE_FCMUO = { - {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.SVE_FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - }, - .SVE_DUP_Z = { - {{.SVE_DUP_Z, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_DUP_Z, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_DUP_Z, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_DUP_Z, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - }, - .SVE_INSR = { - {{.SVE_INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - }, - .SVE_REV_Z = { - {{.SVE_REV_Z, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_REV_Z, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_REV_Z, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.SVE_REV_Z, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - }, - .SVE_REV_P = { - {{.SVE_REV_P, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, - }, - .SVE_TBL = { - {{.SVE_TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_ZIP1_Z = { - {{.SVE_ZIP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_ZIP2_Z = { - {{.SVE_ZIP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ZIP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_UZP1_Z = { - {{.SVE_UZP1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_UZP2_Z = { - {{.SVE_UZP2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_UZP2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_TRN1_Z = { - {{.SVE_TRN1_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN1_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN1_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN1_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_TRN2_Z = { - {{.SVE_TRN2_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN2_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN2_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_TRN2_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_ZIP1_P = { - {{.SVE_ZIP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_ZIP2_P = { - {{.SVE_ZIP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_UZP1_P = { - {{.SVE_UZP1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_UZP2_P = { - {{.SVE_UZP2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_TRN1_P = { - {{.SVE_TRN1_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_TRN2_P = { - {{.SVE_TRN2_P, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_CPY_Z = { - {{.SVE_CPY_Z, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CPY_Z, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CPY_Z, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_CPY_Z, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_COMPACT = { - {{.SVE_COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SVE_COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_EXT_Z = { - {{.SVE_EXT_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_LD1B = { - {{.SVE_LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1H = { - {{.SVE_LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1W = { - {{.SVE_LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1D = { - {{.SVE_LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SB = { - {{.SVE_LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SH = { - {{.SVE_LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SW = { - {{.SVE_LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_ST1B = { - {{.SVE_ST1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1H = { - {{.SVE_ST1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1W = { - {{.SVE_ST1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1D = { - {{.SVE_ST1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_LDR_Z = { - {{.SVE_LDR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .SVE_STR_Z = { - {{.SVE_STR_Z, {.Z_REG_B, .MEM, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - }, - .SVE_LDR_P = { - {{.SVE_LDR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - }, - .SVE_STR_P = { - {{.SVE_STR_P, {.P_REG, .MEM, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - }, - .SVE_LDFF1B = { - {{.SVE_LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, - }, - .SVE_LDFF1H = { - {{.SVE_LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, - }, - .SVE_LDFF1W = { - {{.SVE_LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, - }, - .SVE_LDFF1D = { - {{.SVE_LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, - }, - .SVE_WHILEGE = { - {{.SVE_WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILEGT = { - {{.SVE_WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILELE = { - {{.SVE_WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILELT = { - {{.SVE_WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILEHI = { - {{.SVE_WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILEHS = { - {{.SVE_WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILELO = { - {{.SVE_WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_WHILELS = { - {{.SVE_WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_SQRDMLAH = { - {{.SVE_SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_SQRDMLSH = { - {{.SVE_SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SVE_SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - }, - .SVE_ADCLB = { - {{.SVE_ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_ADCLT = { - {{.SVE_ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_SBCLB = { - {{.SVE_SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_SBCLT = { - {{.SVE_SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_TBL2 = { - {{.SVE_TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_TBX = { - {{.SVE_TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, - }, - .SVE_AESE = { - {{.SVE_AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, - }, - .SVE_AESD = { - {{.SVE_AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, - }, - .SVE_AESMC = { - {{.SVE_AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, - }, - .SVE_AESIMC = { - {{.SVE_AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, - }, - .SVE_BCAX_Z = { - {{.SVE_BCAX_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_XAR_Z = { - {{.SVE_XAR_Z, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_XAR_Z, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_XAR_Z, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SVE_XAR_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_EOR3_Z = { - {{.SVE_EOR3_Z, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_MATCH = { - {{.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_NMATCH = { - {{.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SVE_NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .SVE_HISTCNT = { - {{.SVE_HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - {{.SVE_HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_HISTSEG = { - {{.SVE_HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - }, - .SME_SMSTART = { - {{.SME_SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, - }, - .SME_SMSTOP = { - {{.SME_SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, - }, - .SME_RDSVL = { - {{.SME_RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, - }, - .SME_ADDHA = { - {{.SME_ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_ADDVA = { - {{.SME_ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_ZERO = { - {{.SME_ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, - }, - .SME_FMOPA = { - {{.SME_FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SME_FMOPS = { - {{.SME_FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SME_BFMOPA = { - {{.SME_BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SME_BFMOPS = { - {{.SME_BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SME_SMOPA = { - {{.SME_SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SME_SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_SMOPS = { - {{.SME_SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SME_SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_UMOPA = { - {{.SME_UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SME_UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_UMOPS = { - {{.SME_UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SME_UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_USMOPA = { - {{.SME_USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_SUMOPA = { - {{.SME_SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SME_LDR_ZA = { - {{.SME_LDR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, - }, - .SME_STR_ZA = { - {{.SME_STR_ZA, {.IMM_5, .MEM, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, - }, - .SVE_FMLA_IDX_H = { - {{.SVE_FMLA_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLA_IDX_S = { - {{.SVE_FMLA_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLA_IDX_D = { - {{.SVE_FMLA_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLS_IDX_H = { - {{.SVE_FMLS_IDX_H, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLS_IDX_S = { - {{.SVE_FMLS_IDX_S, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_FMLS_IDX_D = { - {{.SVE_FMLS_IDX_D, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_LD1B_GATHER_S = { - {{.SVE_LD1B_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1B_GATHER_D = { - {{.SVE_LD1B_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1H_GATHER_S = { - {{.SVE_LD1H_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1H_GATHER_D = { - {{.SVE_LD1H_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1W_GATHER_S = { - {{.SVE_LD1W_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1W_GATHER_D = { - {{.SVE_LD1W_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1D_GATHER_D = { - {{.SVE_LD1D_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SB_GATHER_S = { - {{.SVE_LD1SB_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SB_GATHER_D = { - {{.SVE_LD1SB_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SH_GATHER_S = { - {{.SVE_LD1SH_GATHER_S, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SH_GATHER_D = { - {{.SVE_LD1SH_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LD1SW_GATHER_D = { - {{.SVE_LD1SW_GATHER_D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_ST1B_SCATTER_S = { - {{.SVE_ST1B_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1B_SCATTER_D = { - {{.SVE_ST1B_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1H_SCATTER_S = { - {{.SVE_ST1H_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1H_SCATTER_D = { - {{.SVE_ST1H_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1W_SCATTER_S = { - {{.SVE_ST1W_SCATTER_S, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1W_SCATTER_D = { - {{.SVE_ST1W_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_ST1D_SCATTER_D = { - {{.SVE_ST1D_SCATTER_D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_LD1B_TILE = { - {{.SME_LD1B_TILE, {.SME_SLICE_B, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME_LD1H_TILE = { - {{.SME_LD1H_TILE, {.SME_SLICE_H, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME_LD1W_TILE = { - {{.SME_LD1W_TILE, {.SME_SLICE_W, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME_LD1D_TILE = { - {{.SME_LD1D_TILE, {.SME_SLICE_D, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME_LD1Q_TILE = { - {{.SME_LD1Q_TILE, {.SME_SLICE_Q, .P_REG_ZERO, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME_ST1B_TILE = { - {{.SME_ST1B_TILE, {.SME_SLICE_B, .P_REG, .MEM, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_ST1H_TILE = { - {{.SME_ST1H_TILE, {.SME_SLICE_H, .P_REG, .MEM, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_ST1W_TILE = { - {{.SME_ST1W_TILE, {.SME_SLICE_W, .P_REG, .MEM, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_ST1D_TILE = { - {{.SME_ST1D_TILE, {.SME_SLICE_D, .P_REG, .MEM, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_ST1Q_TILE = { - {{.SME_ST1Q_TILE, {.SME_SLICE_Q, .P_REG, .MEM, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME_MOVA_Z_FROM_TILE = { - {{.SME_MOVA_Z_FROM_TILE, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .SME_MOVA_TILE_FROM_Z = { - {{.SME_MOVA_TILE_FROM_Z, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .FCMLA_4H = { - {{.FCMLA_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCMLA_8H = { - {{.FCMLA_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCMLA_4S = { - {{.FCMLA_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCMLA_2D = { - {{.FCMLA_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCADD_4H = { - {{.FCADD_4H, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCADD_8H = { - {{.FCADD_8H, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCADD_4S = { - {{.FCADD_4S, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .FCADD_2D = { - {{.FCADD_2D, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_PRFB = { - {{.SVE_PRFB, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, - }, - .SVE_PRFH = { - {{.SVE_PRFH, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, - }, - .SVE_PRFW = { - {{.SVE_PRFW, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, - }, - .SVE_PRFD = { - {{.SVE_PRFD, {.IMM_4, .P_REG_GOV, .MEM, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, - }, - .SVE_LDNT1B = { - {{.SVE_LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LDNT1H = { - {{.SVE_LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LDNT1W = { - {{.SVE_LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_LDNT1D = { - {{.SVE_LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SVE_STNT1B = { - {{.SVE_STNT1B, {.Z_REG_B, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_STNT1H = { - {{.SVE_STNT1H, {.Z_REG_H, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_STNT1W = { - {{.SVE_STNT1W, {.Z_REG_S, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_STNT1D = { - {{.SVE_STNT1D, {.Z_REG_D, .P_REG, .MEM, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SVE_EXT = { - {{.SVE_EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_SPLICE = { - {{.SVE_SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_INDEX_II = { - {{.SVE_INDEX_II, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - }, - .SVE_INDEX_IR = { - {{.SVE_INDEX_IR, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, - }, - .SVE_INDEX_RI = { - {{.SVE_INDEX_RI, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, - }, - .SVE_INDEX_RR = { - {{.SVE_INDEX_RR, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_BSL = { - {{.SVE_BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, - }, - .SVE_BSL1N = { - {{.SVE_BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BSL2N = { - {{.SVE_BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_NBSL = { - {{.SVE_NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_PMUL_VEC = { - {{.SVE_PMUL_VEC, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_PMULLB = { - {{.SVE_PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_PMULLT = { - {{.SVE_PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, - }, - .SVE_BFCVT = { - {{.SVE_BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFCVTNT = { - {{.SVE_BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .LDRAA = { - {{.LDRAA, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDRAB = { - {{.LDRAB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - }, - .LDRAA_PRE = { - {{.LDRAA_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .LDRAB_PRE = { - {{.LDRAB_PRE, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - }, - .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, - }, - .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, - }, - .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, - }, - .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, - }, - .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, - }, - .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, - }, - .BC_COND = { - {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, - }, - .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - }, - .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - }, - .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - }, - .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - }, - .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - }, - .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - }, - .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - }, - .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - }, - .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, - }, - .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - }, - .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .STLUR = { - {{.STLUR, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - }, - .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .STLURB = { - {{.STLURB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - }, - .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .STLURH = { - {{.STLURH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - }, - .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - }, - .SVE_BFADD = { - {{.SVE_BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFSUB = { - {{.SVE_BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFMUL = { - {{.SVE_BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFMLA = { - {{.SVE_BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFMLS = { - {{.SVE_BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, - }, - .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, - }, - .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, - }, - .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, - }, - .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, - }, - .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, - }, - .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, - }, - .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, - }, - .MOV_V_ALIAS = { - {{.MOV_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .NOT_V_ALIAS = { - {{.NOT_V_ALIAS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT_V_ALIAS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - }, - .LSL_IMM = { - {{.LSL_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.LSL_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .LSR_IMM = { - {{.LSR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .ASR_IMM = { - {{.ASR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .ROR_IMM = { - {{.ROR_IMM, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ROR_IMM, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .SVE_BFADD_UNPRED = { - {{.SVE_BFADD_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFSUB_UNPRED = { - {{.SVE_BFSUB_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFMUL_UNPRED = { - {{.SVE_BFMUL_UNPRED, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - }, - .SVE_BFCLAMP = { - {{.SVE_BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - }, - .SVE_BFMAXNM = { - {{.SVE_BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SVE_BFMINNM = { - {{.SVE_BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - }, - .SME2_LUTI2_B = { - {{.SME2_LUTI2_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, - }, - .SME2_LUTI4_B = { - {{.SME2_LUTI4_B, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, - }, - .SME2_LD1B_X2 = { - {{.SME2_LD1B_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1H_X2 = { - {{.SME2_LD1H_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1W_X2 = { - {{.SME2_LD1W_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1D_X2 = { - {{.SME2_LD1D_X2, {.Z_PAIR, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1B_X4 = { - {{.SME2_LD1B_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1H_X4 = { - {{.SME2_LD1H_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1W_X4 = { - {{.SME2_LD1W_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_LD1D_X4 = { - {{.SME2_LD1D_X4, {.Z_QUAD, .P_REG_ZERO, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - }, - .SME2_ST1B_X2 = { - {{.SME2_ST1B_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1H_X2 = { - {{.SME2_ST1H_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1W_X2 = { - {{.SME2_ST1W_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1D_X2 = { - {{.SME2_ST1D_X2, {.Z_PAIR, .P_REG, .MEM, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1B_X4 = { - {{.SME2_ST1B_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1H_X4 = { - {{.SME2_ST1H_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1W_X4 = { - {{.SME2_ST1W_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ST1D_X4 = { - {{.SME2_ST1D_X4, {.Z_QUAD, .P_REG, .MEM, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - }, - .SME2_ZIP_3 = { - {{.SME2_ZIP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .SME2_ZIP_4 = { - {{.SME2_ZIP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .SME2_UZP_3 = { - {{.SME2_UZP_3, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .SME2_UZP_4 = { - {{.SME2_UZP_4, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, - }, - .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, - }, - .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, - }, - .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, - }, - .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, - }, - .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, - }, - .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, - }, - .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, - }, - .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, - }, - .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, - }, - .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, - }, - .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, - }, - .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, - }, - .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, - }, - .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, - }, - .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, - }, - .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - }, - .PRFM = { - {{.PRFM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, - }, - .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, - }, - .PRFM_LIT = { - {{.PRFM_LIT, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, - }, - .MOV_REG = { - {{.MOV_REG, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MOV_REG, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, - }, - .MOV_BITMASK = { - {{.MOV_BITMASK, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, - {{.MOV_BITMASK, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, - .NEG_SR = { - {{.NEG_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, - {{.NEG_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + .BIT = { + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .BIF = { + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + }, + .BSL = { + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SHL = { + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SQSHL = { + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHLU = { + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SRSHL = { + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .URSHL = { + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SSHR = { + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHR = { + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SSRA = { + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .USRA = { + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SRSHR = { + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .URSHR = { + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SRSRA = { + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .URSRA = { + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SSHL = { + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .USHL = { + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + }, + .SLI = { + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SRI = { + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + }, + .SSHLL = { + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SSHLL2 = { + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHLL = { + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .USHLL2 = { + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SXTL = { + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SXTL2 = { + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UXTL = { + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .UXTL2 = { + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SHRN = { + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SHRN2 = { + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .RSHRN = { + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .RSHRN2 = { + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .SQSHRN = { + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRN2 = { + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQSHRN = { + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQSHRN2 = { + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRN = { + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRN2 = { + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQRSHRN = { + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .UQRSHRN2 = { + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRUN = { + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQSHRUN2 = { + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRUN = { + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .SQRSHRUN2 = { + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + }, + .DUP = { + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + }, + .INS = { + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, + }, + .MOV = { + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, + {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + }, + .EXT = { + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .TBL = { + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .TBX = { + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, + }, + .ZIP1 = { + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .ZIP2 = { + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .UZP1 = { + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .UZP2 = { + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .TRN1 = { + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .TRN2 = { + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .NOT = { + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .REV64 = { + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .CNT = { + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .URECPE = { + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .URSQRTE = { + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + }, + .MOVI = { + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + }, + .MVNI = { + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + }, + .LD1 = { + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD2 = { + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD3 = { + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .LD4 = { + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + }, + .ST1 = { + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST2 = { + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST3 = { + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .ST4 = { + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + }, + .LD1R = { + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD2R = { + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD3R = { + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .LD4R = { + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + }, + .SUBR = { + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .ASRR = { + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .LSLR = { + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .LSRR = { + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .FTSMUL = { + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FSUBR = { + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FDIVR = { + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FNMLA = { + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .FNMLS = { + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .NAND = { + {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .NOR = { + {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .SEL = { + {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .ORRS = { + {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .EORS = { + {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .NANDS = { + {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .NORS = { + {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .ORNS = { + {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .MOVS = { + {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .PTRUE = { + {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + }, + .PTRUES = { + {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .PFALSE = { + {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + }, + .PFIRST = { + {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .PNEXT = { + {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .BRKA = { + {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .BRKB = { + {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .BRKAS = { + {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .BRKBS = { + {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .BRKPA = { + {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .BRKPB = { + {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .BRKN = { + {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .RDFFR = { + {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + }, + .WRFFR = { + {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + }, + .SETFFR = { + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, + }, + .CMPEQ = { + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPNE = { + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPGE = { + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPGT = { + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPLE = { + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPLT = { + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPHI = { + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPHS = { + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPLO = { + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .CMPLS = { + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .FCMNE = { + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .FCMUO = { + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + }, + .INSR = { + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + }, + .CPY = { + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .COMPACT = { + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .LD1B = { + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1H = { + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1W = { + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1D = { + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1SB = { + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1SH = { + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LD1SW = { + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .ST1B = { + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .ST1H = { + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .ST1W = { + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .ST1D = { + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .LDFF1B = { + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .LDFF1H = { + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .LDFF1W = { + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .LDFF1D = { + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + }, + .WHILEGE = { + {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILEGT = { + {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILELE = { + {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILELT = { + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILEHI = { + {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILEHS = { + {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILELO = { + {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .WHILELS = { + {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .SQRDMLAH = { + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .SQRDMLSH = { + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + }, + .ADCLB = { + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .ADCLT = { + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SBCLB = { + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .SBCLT = { + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .TBL2 = { + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .MATCH = { + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .NMATCH = { + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + }, + .HISTCNT = { + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .HISTSEG = { + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .SMSTART = { + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, + }, + .SMSTOP = { + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, + }, + .RDSVL = { + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, + }, + .ADDHA = { + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .ADDVA = { + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .ZERO = { + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, + }, + .FMOPA = { + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FMOPS = { + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMOPA = { + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMOPS = { + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SMOPA = { + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SMOPS = { + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .UMOPA = { + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .UMOPS = { + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .USMOPA = { + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .SUMOPA = { + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + }, + .LD1Q = { + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .ST1Q = { + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .MOVA = { + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .FCMLA = { + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .FCADD = { + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .PRFB = { + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .PRFH = { + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .PRFW = { + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .PRFD = { + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + }, + .LDNT1B = { + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LDNT1H = { + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LDNT1W = { + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .LDNT1D = { + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + }, + .STNT1B = { + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .STNT1H = { + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .STNT1W = { + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .STNT1D = { + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + }, + .SPLICE = { + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + }, + .INDEX = { + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + }, + .BSL1N = { + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .BSL2N = { + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .NBSL = { + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + }, + .PMUL = { + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .PMULLB = { + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .PMULLT = { + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + }, + .BFCVTNT = { + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .LDRAA = { + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .LDRAB = { + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + }, + .TSTART = { + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, + }, + .TCOMMIT = { + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, + }, + .TCANCEL = { + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, + }, + .TTEST = { + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, + }, + .WFET = { + {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + }, + .WFIT = { + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + }, + .BC_COND = { + {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + }, + .UXTB = { + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .UXTH = { + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .UXTW = { + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .SXTB = { + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .SXTH = { + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + }, + .SXTW = { + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + }, + .ADC = { + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + }, + .ADCS = { + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .SBC = { + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + }, + .SBCS = { + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .NGC = { + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, + }, + .NGCS = { + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + }, + .LDAPUR = { + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLUR = { + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURB = { + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLURB = { + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURH = { + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .STLURH = { + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSB = { + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSH = { + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .LDAPURSW = { + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + }, + .BFADD = { + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFSUB = { + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMUL = { + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMLA = { + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .BFMLS = { + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + }, + .SB = { + {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .CSDB = { + {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + }, + .DGH = { + {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .PSB_CSYNC = { + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .TSB_CSYNC = { + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + }, + .BTI_J = { + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .BTI_C = { + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .BTI_JC = { + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + }, + .BFCLAMP = { + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + }, + .BFMAXNM = { + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + }, + .BFMINNM = { + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + }, + .LUTI2 = { + {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + }, + .LUTI4 = { + {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + }, + .ZIP = { + {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .UZP = { + {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + }, + .TLBI_RPALOS = { + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_RPAOS = { + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E1A = { + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .DC_CIPAPA = { + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CIGDPAPA = { + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .TLBI_PAALL = { + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_PAALLOS = { + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .AMX_LDX = { + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDY = { + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STX = { + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STY = { + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDZ = { + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STZ = { + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_LDZI = { + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_STZI = { + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_EXTRX = { + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_EXTRY = { + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA64 = { + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS64 = { + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA32 = { + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS32 = { + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MAC16 = { + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMA16 = { + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_FMS16 = { + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_SET = { + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, + }, + .AMX_CLR = { + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, + }, + .AMX_VECINT = { + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_VECFP = { + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MATINT = { + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_MATFP = { + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .AMX_GENLUT = { + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + }, + .CPYP = { + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYM = { + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYE = { + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFP = { + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFM = { + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .CPYFE = { + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + }, + .SETP = { + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .SETM = { + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .SETE = { + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + }, + .DC_IVAC = { + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_ISW = { + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_CSW = { + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_CISW = { + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + }, + .DC_ZVA = { + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, + }, + .DC_CVAC = { + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CVAU = { + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .DC_CIVAC = { + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .IC_IALLUIS = { + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + }, + .IC_IALLU = { + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + }, + .IC_IVAU = { + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + }, + .AT_S1E1R = { + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E1W = { + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E0R = { + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E0W = { + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E2R = { + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E2W = { + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E3R = { + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S1E3W = { + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E1R = { + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E1W = { + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E0R = { + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .AT_S12E0W = { + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VMALLE1 = { + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_VMALLE1IS = { + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAE1 = { + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAE1IS = { + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ASIDE1 = { + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ASIDE1IS = { + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAAE1 = { + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAAE1IS = { + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VALE1 = { + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VALE1IS = { + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAALE1 = { + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_VAALE1IS = { + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE1 = { + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE1IS = { + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE2 = { + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE2IS = { + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE3 = { + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .TLBI_ALLE3IS = { + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + }, + .PRFM = { + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, + }, + .PRFUM = { + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .CMP_SR = { - {{.CMP_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + .CMP = { + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .CMP_ER = { - {{.CMP_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + .CMN = { + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, - .CMP_IMM = { - {{.CMP_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .CMN_SR = { - {{.CMN_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .CMN_ER = { - {{.CMN_ER, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN_ER, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .CMN_IMM = { - {{.CMN_IMM, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN_IMM, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - }, - .TST_SR = { - {{.TST_SR, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST_SR, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - }, -} \ No newline at end of file +} diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index 744c8483bf551557e82b6910f92511eb2ede5f1c..ec29d12a2df77377012d4d8a419371599c05aa2b 100644 GIT binary patch delta 1503 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Distinct operand categories can share a type: a Z register +// and a P register are both passed as `u8`, so `inst_trn2_z_z_z` and +// `inst_trn2_p_p_p` have different names but the same signature. Both are +// still emitted as standalone procedures; only the first of a colliding set +// may join the overload group, since Odin rejects a group holding two +// procedures of identical type. +odin_type_key :: proc(sig: Operand_Signature) -> string { + params := param_list(sig) + defer delete(params) + sb: strings.Builder + strings.builder_init(&sb) + for p in params { + if i := strings.index(p.decl, ": "); i >= 0 { + strings.write_string(&sb, p.decl[i+2:]) + } + strings.write_byte(&sb, ',') + } + return strings.to_string(sb) +} + // Every operand type now maps to a category -- nothing is unsupported, so no // form is ever skipped. operand_category :: proc(t: a.Operand_Type) -> Operand_Category { @@ -105,7 +126,10 @@ operand_category :: proc(t: a.Operand_Type) -> Operand_Category { return .PREG case .REL_26, .REL_19, .REL_14, .REL_PG21: return .REL - case .MEM: + case .MEM_OFFSET, .MEM_PRE, .MEM_POST, .MEM_REG, .MEM_EXT, + .MEM_SVE_SS, .MEM_SVE_SI, .MEM_SVE_VEC, .MEM_SVE_VB: + // All addressing modes take one `Memory` parameter, so they share a + // builder signature: the encoder picks the form from mem.mode. return .MEM case .COND: return .COND @@ -620,8 +644,26 @@ main :: proc() { `) for m in mnemonic_list { - procs := procs_by_mnemonic[m] - if len(procs) == 0 { continue } + all_procs := procs_by_mnemonic[m] + if len(all_procs) == 0 { continue } + + // Only type-distinct forms can be group members (see odin_type_key). + procs: [dynamic]Proc_Entry + defer delete(procs) + { + seen: map[string]bool + defer delete(seen) + for e in all_procs { + key := odin_type_key(e.sig) + if seen[key] { + delete(key) + continue + } + seen[key] = true + append(&procs, e) + } + } + mlow := mnemonic_to_lower(m) // inst_ group @@ -659,21 +701,10 @@ main :: proc() { } } - // Builder aliases for redundant SME enum names that were removed from the - // Mnemonic enum: they are the same instructions as the canonical *_TILE / - // MOVA_*_FROM_* forms, so the convenient *_za / *_to_* names delegate to them. - sme_aliases := [][2]string{ - {"sme_ld1b_za", "sme_ld1b_tile"}, {"sme_ld1h_za", "sme_ld1h_tile"}, - {"sme_ld1w_za", "sme_ld1w_tile"}, {"sme_ld1d_za", "sme_ld1d_tile"}, - {"sme_ld1q_za", "sme_ld1q_tile"}, {"sme_st1b_za", "sme_st1b_tile"}, - {"sme_st1h_za", "sme_st1h_tile"}, {"sme_st1w_za", "sme_st1w_tile"}, - {"sme_st1d_za", "sme_st1d_tile"}, {"sme_st1q_za", "sme_st1q_tile"}, - {"sme_mova_to_z", "sme_mova_z_from_tile"}, {"sme_mova_to_za", "sme_mova_tile_from_z"}, - } - strings.write_string(&sb, "\n// Aliases: redundant SME names -> canonical tile/MOVA builders.\n") - for al in sme_aliases { - fmt.sbprintf(&sb, "inst_%s :: inst_%s\nemit_%s :: emit_%s\n", al[0], al[1], al[0], al[1]) - } + // (The SME *_za / *_to_* builder aliases that used to be appended here are + // gone: SME_LD1B_TILE, SME_MOVA_Z_FROM_TILE and friends now carry their + // assembler names -- LD1B, MOVA -- so inst_ld1b / inst_mova already are + // the canonical builders and no delegating alias is needed.) output := strings.to_string(sb) err := os.write_entire_file(#directory + "/../mnemonic_builders.odin", transmute([]u8)strings.concatenate({GEN_ATTRIB, output})) From dd925287ad52814c1b08b6275ac00c85fecae2f2 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Wed, 26 Aug 2026 18:24:26 -0400 Subject: [PATCH 08/89] rexcode/arm64: fix the encode, decode and print bugs the mnemonic pass exposed Encoder * LSR/ASR by immediate used the generic IMM12 encoding, which writes bits 10-21 -- straight into the imms field the UBFM/SBFM base pattern already fills, so immr stayed 0 and every shift encoded as #0 (`asr x0,x1,#7` gave 9340fc20, not 9347fc20). They need immr alone, since imms is the constant 31/63 fixed in the form: new ENC_SHIFT_IMMR. * LDP/STP and friends borrowed the single-register addressing encodings, which put an UNSCALED 9-bit displacement at bits 20:12 and OR a pre/post marker into bits 11:10. The pair forms want a SCALED 7-bit value at 21:15, and bits 11:10 are part of Rt2 -- so `ldp x0,x1,[x2,#16]!` came back with Rt2=3. New OFFSET_PAIR_4/8/16 (the scale does not follow from the register type: LDPSW pairs X registers but loads words, STGP scales by 16), with the addressing mode read from bits[24:23] where the architecture keeps it. 26 forms retargeted. Decoder * Vector operands came back with size=4 always, so a decoded V register lost its arrangement and disassembly printed a bare `v0` that no assembler would take. Reconstruct it from the form's operand type. * Vd/Vn/Vm/Va hardcoded REG_V, but SVE forms use those same slots with Z_REG_* operands -- `add z0.d, z0.d, z0.d` decoded as a V register. Take the class from the operand type, as every other slot already does. Printer * V/Z registers now print their arrangement (`add v0.4s, v1.4s, v2.4s`, `add z0.d, ...`). Element views (op_v_elem_*) moved from 1/2/4/8 to odd codes 1/3/5/7, because an element-D view and an 8B arrangement were both size 8 and could not be told apart. * MOVZ/MOVN/MOVK print the hw index as `lsl #16`, omitted when zero. * BC_COND folds its condition into the mnemonic like B_COND already did, instead of printing it twice. Table (each bit pattern re-derived from llvm-mc) * BTI_J and BTI_C had each other's encodings. * FCMLA's mask left size bit 22 free, so .4s and .2d were indistinguishable and .2d decoded as .4s. * BFDOT carried the Q=0 pattern for its .4s/.8h form; PMULLB/PMULLT were missing the size field; TLBI PAALL/PAALLOS had the wrong CRm/op2. * RDSVL's imm6 sits at bits 10:5, not where IMM6 puts it: ENC_IMM6_LO. Nine test expectations that asserted the wrong values were corrected. specgen.lua Was already dead before the mnemonic work -- it wrote to encoding_table.odin and spliced a SPECGEN region, neither of which survived the merge into instruction_table.odin. Retargeted, taught the canonical names, and made it emit Form literals (Encoding + Clobber). It can no longer own whole `.MNEM = { ... }` blocks either, since ADD now holds integer, NEON and SVE forms together, so it MERGES: a form is added only when no (bits, mask) match exists, and existing rows are never rewritten -- their hand-maintained Clobber data has to survive a regeneration. Verified: all 11 rexcode suites match HEAD exactly (arm64 461/461); the three generator stages stay idempotent; a 73-case differential against llvm-mc is byte-exact for both encode and decode round-trip. Over the whole decode table, canonical-form disassembly re-assembled by llvm-mc goes from 594 byte-exact / 1818 unassemblable to 1737 / 678. Re-running specgen re-derives 1130 forms from llvm-mc and finds every one already present, which independently confirms those bit patterns. Still open: multi-vector register lists ({z0.b, z1.b}) and lane indices (v0.s[2]) are not modelled, so those forms print without them. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm64/decoder.odin | 93 +++++-- core/rexcode/isa/arm64/encoder.odin | 31 ++- core/rexcode/isa/arm64/encoding_types.odin | 20 ++ core/rexcode/isa/arm64/operands.odin | 15 +- core/rexcode/isa/arm64/printer.odin | 77 +++++- .../tablegen/generated/decode_tables.odin | 228 +++++++++--------- .../tablegen/generated/encode_tables.odin | 84 +++---- .../isa/arm64/tablegen/instruction_table.odin | 84 +++---- core/rexcode/isa/arm64/tablegen/specgen.lua | 198 ++++++++++++--- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 48720 -> 48720 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 48760 -> 48760 bytes .../isa/arm64/tests/pipeline_smoke.odin | 2 +- core/rexcode/isa/arm64/tests/smoke.odin | 22 +- 13 files changed, 582 insertions(+), 272 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 2fb303ab1..10c0eb37e 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -213,7 +213,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- NEON copy/permute index fields ------------------------------------ case .VN_VM_DUP: - return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .NEON_IDX5: // imm5 = index << (markerbit+1) | (1 << markerbit); marker = lowest set bit. imm5 := (word >> 16) & 0x1F @@ -246,7 +246,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .PN_PM_DUP, .PN_PG_PM_DUP: return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .ZD_ZM_DUP: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .SVE_EXT_IMM: v := ((word >> 16) & 0x1F) << 3 | ((word >> 10) & 0x7) return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} @@ -338,6 +338,35 @@ extract_operand_inline :: #force_inline proc "contextless" ( }, kind = .MEMORY, size = 4, } + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7 at 21:15, scaled by the transfer size. The + // addressing mode is bits[24:23] of the word (01 post, 11 pre, + // 10 signed offset / 00 no-allocate), not part of the encoding. + base_hw := u8((word >> 5) & 0x1F) + imm7 := i32((word >> 15) & 0x7F) + if imm7 & (1 << 6) != 0 { + imm7 |= ~i32(0x7F) + } + scale := i32(4) + if en == .OFFSET_PAIR_8 { + scale = 8 + } else if en == .OFFSET_PAIR_16 { + scale = 16 + } + mode := Address_Mode.OFFSET + switch (word >> 23) & 0x3 { + case 0b01: mode = .POST_INDEXED + case 0b11: mode = .PRE_INDEXED + } + return Operand{ + mem = Memory{ + base = Register(REG_X | u16(base_hw)), + index = NONE, + disp = imm7 * scale, + mode = mode, + }, + kind = .MEMORY, size = 4, + } case .OFFSET_REG, .OFFSET_EXT: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) @@ -406,18 +435,17 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64(value), kind = .IMMEDIATE, size = is_64 ? 8 : 4} // ---- NEON / SIMD register slots ---- + // The class comes from the operand TYPE, not from the encoding: SVE forms + // use these same Vd/Vn/Vm slots with Z_REG_* operands, so hardcoding + // REG_V here decoded `add z0.d, z0.d, z0.d` as a V register. case .VD: - hw := u16(word & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 0, ot) case .VN: - hw := u16((word >> 5) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 5, ot) case .VM: - hw := u16((word >> 16) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 16, ot) case .VA: - hw := u16((word >> 10) & 0x1F) - return Operand{reg = Register(REG_V | hw), kind = .REGISTER, size = 4} + return reg_from_field(word, 10, ot) // ---- NEON / SVE indexed/immediate fields ---- case .NEON_IMM8_FMOV: @@ -607,17 +635,24 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .ENC_LSL_IMM_X: imms := (word >> 10) & 0x3F return Operand{immediate = i64((63 - imms) & 0x3F), kind = .IMMEDIATE, size = 1} + case .ENC_IMM6_LO: + v := i32((word >> 5) & 0x3F) + if v & (1 << 5) != 0 { v |= ~i32(0x3F) } // sign-extend from bit 5 + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + case .ENC_SHIFT_IMMR: + // LSR/ASR immediate: the shift is immr verbatim (bits 21:16). + return Operand{immediate = i64((word >> 16) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_DUAL_RN_RM: // Take the Rn slot (9:5) as the source register. return Operand{reg = Register(REG_X | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} case .ENC_ROR_SHIFT: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: - return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM: - return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} } return {} } @@ -656,7 +691,37 @@ reg_from_field :: #force_inline proc "contextless" ( if (ot == .WSP_REG && hw == 31) || (ot == .XSP_REG && hw == 31) { return Operand{reg = Register(cls | 31), kind = .REGISTER, size = 4} } - return Operand{reg = Register(cls | hw), kind = .REGISTER, size = 4} + // Vector operands carry their arrangement / element view in `size`, using + // the same codes op_v_*/op_z_* produce (see operands.odin). Without this a + // decoded V register would come back as a bare `v0` with no `.4s`, so a + // disassembly could not be fed back to an assembler. + return Operand{reg = Register(cls | hw), kind = .REGISTER, size = reg_size_for_type(ot)} +} + +// The `size` marker an operand of this type carries: the NEON arrangement +// (multiples of 8), an element view (odd), or an SVE element width. 4 is the +// neutral "no vector shape" value used by every scalar class. +@(private="file", require_results) +reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .V_8B: return 8 + case .V_16B: return 16 + case .V_4H, .V_4H_FP16: return 24 + case .V_8H, .V_8H_FP16: return 32 + case .V_2S: return 40 + case .V_4S: return 48 + case .V_1D: return 56 + case .V_2D: return 64 + case .V_ELEM_B: return 1 + case .V_ELEM_H: return 3 + case .V_ELEM_S: return 5 + case .V_ELEM_D: return 7 + case .Z_REG_B: return 1 + case .Z_REG_H: return 2 + case .Z_REG_S: return 4 + case .Z_REG_D: return 8 + } + return 4 } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index b8de703d7..304311f25 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -231,14 +231,16 @@ operand_matches_inline :: #force_inline proc "contextless" ( // Element-indexed V views: element size carried in op.size (B=1,H=2,S=4, // D=8) so DUP/INS forms disambiguate. .S also accepts size 0 so a plain // op_reg (as the hand-written SM3TT forms pass) still matches the .S slot. + // Element-view sizes are odd (1/3/5/7) so they can never be confused with + // an arrangement, which is always a multiple of 8 (see op_v_elem_*). case .V_ELEM_B: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 1 case .V_ELEM_H: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 2 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 3 case .V_ELEM_S: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 4 || op.size == 0) + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 5 || op.size == 0) case .V_ELEM_D: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 8 + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && op.size == 7 // SVE Z registers. Element size carried in op.size: B=1, H=2, S=4, D=8. // op.size==0 (legacy / default-constructed) accepts any width. @@ -440,6 +442,19 @@ pack_operand_inline :: #force_inline proc( // Atomic addressing: [Xn] only -- no displacement, no shift. // Used by load/store exclusives, acquire/release, LSE atomics. return (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + case .OFFSET_PAIR_4, .OFFSET_PAIR_8, .OFFSET_PAIR_16: + // LDP/STP: signed imm7, scaled by the transfer size, at bits 21:15. + // The pre/post marker is already in the form's bits, so nothing is + // ORed into bits 11:10 -- those belong to Rt2. + scale := i32(4) + if enc == .OFFSET_PAIR_8 { + scale = 8 + } else if enc == .OFFSET_PAIR_16 { + scale = 16 + } + base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 + imm_bits := u32((i32(op.mem.disp) / scale) & 0x7F) + return base_bits | (imm_bits << 15) case .OFFSET_REG: // [Xn, Xm{, LSL #s}]: option=011, S = shift!=0. base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 @@ -777,6 +792,16 @@ pack_operand_inline :: #force_inline proc( immr := ((~imm + 1) & 0x3F) imms := (63 - imm) & 0x3F return (immr << 16) | (imms << 10) + case .ENC_IMM6_LO: + // Signed 6-bit at bits 10:5 (RDSVL); range -32..31. + return (u32(op.immediate) & 0x3F) << 5 + case .ENC_SHIFT_IMMR: + // LSR/ASR by immediate: immr = shift at bits 21:16. imms is the + // constant 31 / 63 already present in the form's bits, so unlike + // ENC_LSL_IMM_* there is nothing to compute for it. Mask to the + // register width so a W-form shift cannot spill into bit 21. + width := form.flags.is_64 ? u32(0x3F) : u32(0x1F) + return (u32(op.immediate) & width) << 16 case .ENC_DUAL_RN_RM: // Pack the register at both Rn (9:5) AND Rm (20:16) slots // (for ROR Rd, Rn, #imm = EXTR Rd, Rn, Rn, #imm). diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 2b8c2775d..17816ae81 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -215,6 +215,13 @@ Operand_Encoding :: enum u8 { IMM6, // bits 10-15 (shift amount; SHAMT) IMM9, // bits 12-20 (signed 9-bit; LDUR/pre/post) IMM_HW, // bits 21-22 (MOVZ/MOVN/MOVK hw field; value is shift/16) + // LSR/ASR by immediate are UBFM/SBFM Rd, Rn, #shift, #(31|63): the shift + // goes to immr and imms is a constant already fixed in the form's bits, + // so unlike LSL (ENC_LSL_IMM_*) only one field is operand-driven. + ENC_SHIFT_IMMR, // bits 16-21 (immr; LSR/ASR immediate aliases) + // RDSVL / the RDVL family put their signed 6-bit immediate at bits 10:5, + // not where IMM6 (bits 15:10) writes it. + ENC_IMM6_LO, // bits 5-10 (signed 6-bit; RDSVL) IMM_SH12, // bit 22 (ADD/SUB imm: LSL #12 flag) SHIFT_TYPE, // bits 22-23 (LSL/LSR/ASR/ROR for shifted-register) EXT_OPT, // bits 13-15 (extend type for extended-register) @@ -232,6 +239,19 @@ Operand_Encoding :: enum u8 { OFFSET_BASE_PRE, // [Xn, #imm]! signed-9 pre-index OFFSET_BASE_POST, // [Xn], #imm signed-9 post-index OFFSET_BASE_A, // [Xn] no displacement (exclusives, acquire/release, LSE) + // LDP/STP family. Nothing like the single-register modes above: the + // displacement is a signed 7-bit value SCALED by the transfer size at + // bits 21:15 (single-register forms use an unscaled 9-bit at 20:12), and + // bits 11:10 are part of Rt2 here, so the pre/post markers the + // single-register encodings OR in would corrupt the second register. + // The scale cannot be read off the register type -- LDPSW pairs X + // registers but loads words (scale 4), STGP pairs X registers and scales + // by 16 -- so it is spelled out per encoding. The addressing mode lives + // in the form's bits[24:23] (01 post, 10 signed offset, 11 pre), which + // is where the decoder reads it back from. + OFFSET_PAIR_4, // [Xn{, #imm}] / [Xn, #imm]! / [Xn], #imm -- imm7 x 4 + OFFSET_PAIR_8, // imm7 x 8 + OFFSET_PAIR_16, // imm7 x 16 OFFSET_REG, // [Xn, Rm{, LSL #s}] register offset OFFSET_EXT, // [Xn, Wm, SXTW|UXTW|SXTX #s] diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 867da7559..0cb0f3c25 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -211,23 +211,28 @@ op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand { } // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides -// in op.size (1/2/4/8) so the matcher can disambiguate DUP/INS forms; the lane -// index is a separate immediate operand. +// in op.size so the matcher can disambiguate DUP/INS forms; the lane index is +// a separate immediate operand. +// +// The codes are ODD (1/3/5/7) on purpose: arrangement operands above use +// multiples of 8, so a size can never mean both. They used to be 1/2/4/8, +// which made an element-D view indistinguishable from an 8B arrangement -- +// the printer cannot tell `.d` from `.8b` if both are size 8. @(require_results) op_v_elem_b :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 1} } @(require_results) op_v_elem_h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 2} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 3} } @(require_results) op_v_elem_s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 5} } @(require_results) op_v_elem_d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8} + return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 7} } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 1459b062b..ce2015007 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -115,21 +115,35 @@ sbprint :: proc( write_full_mnemonic(sb, inst, opts.uppercase) - // B.cond's condition is encoded into the mnemonic suffix (b.eq), - // so when printing we skip the first operand (it IS the cond). + // B.cond / BC.cond fold the condition into the mnemonic (b.eq), so the + // operand carrying it must not be printed a second time. start_slot := 0 - if inst.mnemonic == .B_COND && inst.operand_count >= 1 && inst.ops[0].kind == .COND { + if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && + inst.operand_count >= 1 && inst.ops[0].kind == .COND { start_slot = 1 } - if int(inst.operand_count) > start_slot { + // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), + // which assemblers write as `lsl #16` and omit entirely when it is zero. + mov_wide := inst.mnemonic == .MOVZ || inst.mnemonic == .MOVN || inst.mnemonic == .MOVK + end_slot := int(inst.operand_count) + if mov_wide && end_slot == 3 && inst.ops[2].kind == .IMMEDIATE && inst.ops[2].immediate == 0 { + end_slot = 2 + } + + if end_slot > start_slot { strings.write_byte(sb, ' ') - for slot in start_slot.. start_slot { strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } - write_operand(sb, &inst.ops[slot], &display, opts) + if mov_wide && slot == 2 { + strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") + write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) + } else { + write_operand(sb, &inst.ops[slot], &display, opts) + } } } strings.write_string(sb, opts.separator) @@ -335,6 +349,56 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { } } +// NEON arrangement (`.4s`), element view (`.d`) or SVE element width (`.s`) +// suffix. Vector operands carry the shape in op.size using the codes +// op_v_*/op_z_* produce and the decoder restores (see operands.odin); +// arrangements are multiples of 8, element views are odd, and the neutral 4 +// that every scalar class uses prints nothing. +// +// NOTE: an element-indexed operand still prints as `v0.s` -- the lane index +// rides in a separate immediate operand, so `v0.s[2]` needs the printer to +// fold that operand into this one, which it does not yet do. +@(private="file") +write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { + shape := "" + switch reg_class(r) { + case REG_V: + switch size { + case 8: shape = "8b" + case 16: shape = "16b" + case 24: shape = "4h" + case 32: shape = "8h" + case 40: shape = "2s" + case 48: shape = "4s" + case 56: shape = "1d" + case 64: shape = "2d" + case 1: shape = "b" + case 3: shape = "h" + case 5: shape = "s" + case 7: shape = "d" + } + case REG_Z: + switch size { + case 1: shape = "b" + case 2: shape = "h" + case 4: shape = "s" + case 8: shape = "d" + } + } + if shape == "" { + return + } + strings.write_byte(sb, '.') + for i in 0..= 'a' && c <= 'z' { + strings.write_byte(sb, c - 32) + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { if r == NONE { strings.write_string(sb, ""); return } @@ -402,6 +466,7 @@ write_operand :: proc( case .REGISTER: write_register(sb, op.reg, opts.uppercase) + write_vector_shape(sb, op.reg, op.size, opts.uppercase) case .IMMEDIATE: strings.write_byte(sb, '#') diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index c22a72863..0557a8304 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -44,12 +44,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, + { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, @@ -64,16 +64,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, @@ -107,16 +107,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, @@ -127,18 +127,18 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, @@ -149,37 +149,37 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, @@ -198,69 +198,69 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, @@ -272,24 +272,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, @@ -318,16 +318,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, @@ -370,8 +370,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, @@ -382,8 +382,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, @@ -449,12 +449,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, @@ -462,13 +462,13 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, @@ -477,24 +477,24 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, @@ -510,9 +510,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, @@ -638,26 +638,26 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, @@ -668,8 +668,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, @@ -758,12 +758,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, @@ -902,9 +902,9 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, @@ -912,14 +912,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {} }, { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {} }, @@ -931,17 +931,17 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {} }, { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {} }, { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {} }, @@ -952,12 +952,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {} }, { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {} }, { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {} }, @@ -975,20 +975,20 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {} }, { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {} }, - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, @@ -1119,8 +1119,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, @@ -1270,7 +1270,7 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, @@ -1706,14 +1706,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, @@ -1807,16 +1807,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, @@ -1844,10 +1844,10 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, @@ -1895,11 +1895,11 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 330bd68e0..c16426c73 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -141,8 +141,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ASR { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -150,8 +150,8 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, // .ROR { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -361,29 +361,29 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_BASE_PRE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_BASE_POST,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, // .LDAR { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, @@ -893,11 +893,11 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .LDURSW { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, // .LDXP { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, @@ -1186,7 +1186,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .STZ2G { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, // .LDGM { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, // .STGM @@ -1291,7 +1291,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, // .BFMMLA { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, // .BFMLALB @@ -2836,7 +2836,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .SMSTOP { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.IMM6,.NONE,.NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, // .ADDHA { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, // .ADDVA @@ -2875,10 +2875,10 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, // .FCADD { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, @@ -2924,9 +2924,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .PMUL { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, // .BFCVTNT { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, // .LDRAA @@ -3025,9 +3025,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .TSB_CSYNC { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, // .BTI_J - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_C - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP @@ -3057,9 +3057,9 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .DC_CIGDPAPA { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true} }, // .TLBI_PAALL - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, // .AMX_LDY diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index ec9f178f9..fb287288e 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -254,8 +254,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ASR = { {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -264,8 +264,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ROR = { {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -519,31 +519,31 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_BASE_PRE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_BASE_POST, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, @@ -1132,12 +1132,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, @@ -1546,7 +1546,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_S9, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, @@ -1697,7 +1697,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3540,7 +3540,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .IMM6, .NONE, .NONE}, 0x04BF5800, 0xFFFFFC00, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, }, .ADDHA = { {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, @@ -3596,10 +3596,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFA0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3665,10 +3665,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45006C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .BFCVTNT = { {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3809,10 +3809,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_JC = { {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, @@ -3856,10 +3856,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E89F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508E81F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, diff --git a/core/rexcode/isa/arm64/tablegen/specgen.lua b/core/rexcode/isa/arm64/tablegen/specgen.lua index 5dbd1d4cf..13197ba8a 100644 --- a/core/rexcode/isa/arm64/tablegen/specgen.lua +++ b/core/rexcode/isa/arm64/tablegen/specgen.lua @@ -7,9 +7,16 @@ -- the differing bits are operand-driven, so mask = ~(bits0 ^ bits31). Per-form -- assembly makes it robust: an arrangement llvm-mc rejects is reported, skipped. -- --- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin --- in place; the hand-written core is untouched. Every bit pattern is therefore --- reproducible and llvm-mc-backed. +-- Output is MERGED into instruction_table.odin: a generated form is inserted +-- into its mnemonic's block only if no form with the same (mnemonic, bits, +-- mask) is there already. Existing rows are never rewritten -- their Clobber +-- data is hand-maintained and must not be clobbered (pun intended) by a +-- regeneration. So this is an "add the forms that are missing" tool, which is +-- what it is actually for. Every bit pattern is llvm-mc-backed. +-- +-- Merging (rather than owning a whole region) is required because a Mnemonic +-- is now an ASSEMBLER mnemonic: ADD holds the integer, NEON and SVE forms in +-- one block, so specgen cannot own `.ADD = { ... }` outright. -- -- Two spec kinds: -- * uniform โ€” every operand shares one arrangement T (iterate ALL_ARR). @@ -21,7 +28,7 @@ local bit = require("bit") local LLVM = "llvm-mc --assemble --arch=aarch64 --mattr=+fullfp16 --show-encoding" local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." -local TABLE = DIR .. "/encoding_table.odin" +local TABLE = DIR .. "/instruction_table.odin" local ARR = { ["8B"]={vt="V_8B",asm="8b"}, ["16B"]={vt="V_16B",asm="16b"}, @@ -53,6 +60,78 @@ local function padded(tokens, n) return "{" .. table.concat(t, ", ") .. "}" end +-- The Mnemonic enum holds assembler mnemonics, so the ISA-namespace prefixes +-- and per-encoding suffixes these specs were written against are gone. +local CANON_PRE = {"SVE2_", "SVE_", "SME2_", "SME_"} +local CANON_SUF = { + "_GATHER_S","_GATHER_D","_SCATTER_S","_SCATTER_D","_FROM_TILE","_TILE_FROM", + "_UNPRED","_BITMASK","_SCALAR","_ALIAS","_PRED","_TILE","_LANE", + "_IDX","_GEN","_LIT","_IMM","_VEC","_PRE","_POST","_REG", + "_4H","_8H","_4S","_2D","_1D","_2S","_8B","_16B", + "_II","_IR","_RI","_RR","_X2","_X4","_SR","_ER","_ZA", + "_Z","_P","_V","_H","_S","_D","_B","_3","_4", +} +local CANON_KEEP = { B_COND=true, BC_COND=true } +local CANON_RENAME = { LSLV="LSL", LSRV="LSR", ASRV="ASR", RORV="ROR" } +local function canon(name) + if CANON_KEEP[name] then return name end + for _, k in ipairs({"DC_","IC_","AT_","TLBI_","BTI_","PSB_","TSB_"}) do + if name:sub(1, #k) == k then return name end + end + local c = CANON_RENAME[name] or name + for _, pre in ipairs(CANON_PRE) do + if c:sub(1, #pre) == pre then c = c:sub(#pre + 1); break end + end + local changed = true + while changed do + changed = false + for _, suf in ipairs(CANON_SUF) do + if #c > #suf and c:sub(-#suf) == suf then + local stem = c:sub(1, #c - #suf) + if #stem > 0 and stem:sub(-1) ~= "_" then c = stem; changed = true; break end + end + end + end + return (#c > 0) and c or name +end + +-- A Form is an Encoding plus a Clobber. For the data-processing shapes this +-- tool emits, slot 0 is the destination and every later register-ish slot is a +-- source (a destination repeated in a later slot -- SVE destructive forms -- +-- is therefore correctly counted as a read too). +local REG_SLOT = { + VD=true, VN=true, VM=true, VA=true, RD=true, RN=true, RM=true, RA=true, + PD=true, PN=true, PM=true, PG=true, PG4=true, PM3=true, RT=true, RT2=true, +} +-- The table aligns the operand tuple at a fixed column; keep generated rows +-- looking like the hand-written ones around them. +local function mnem_field(name) + local s = "{{." .. name .. "," + return s .. string.rep(" ", math.max(1, 28 - #s)) +end + +-- The table also aligns the Clobber at a fixed column. Applied once at merge +-- time so every row formatter stays a plain string.format. +-- The table is not uniformly aligned (166..176 across sections); 169 is the +-- dominant column, so new rows land in the majority style. +local CLOBBER_COL = 169 +local function align_row(row) + local head, tail = row:match("^(.-%}%},) (%{.*)$") + if not head then return row end + return head .. string.rep(" ", math.max(1, CLOBBER_COL - #head)) .. tail +end + +local function clobber_of(enc_str) + local slots = {} + for tok in enc_str:gmatch("%.([%w_]+)") do slots[#slots+1] = tok end + local reads = {} + for i = 2, #slots do + if REG_SLOT[slots[i]] then reads[#reads+1] = tostring(i - 1) end + end + if #reads == 0 then return "{written={0}}" end + return string.format("{written={0}, read={%s}}", table.concat(reads, ", ")) +end + local sections, skips, n_forms, n_mnem = {}, {}, 0, 0 -- Emit one mnemonic's block from a list of arrangement tuples (operand order). @@ -72,8 +151,8 @@ local function emit(mnem, llvm, enc_str, feature, variants) for i, t in ipairs(tup) do ops[i] = "."..tok_vt(t) end local f = feature for _, tk in ipairs(tup) do if ARR[tk] and ARR[tk].feat then f = ARR[tk].feat end end - rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", - mnem, padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + rows[#rows+1] = string.format("\t\t%s%s, %s, 0x%s, 0x%s, .%s, {}}, %s},", + mnem_field(canon(mnem)), padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f, clobber_of(enc_str)) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..table.concat(tup, "/") @@ -81,7 +160,7 @@ local function emit(mnem, llvm, enc_str, feature, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- Compare-against-zero: a 2-register shape whose asm carries a literal #0 @@ -97,8 +176,8 @@ local function emit_cmp0(mnem, llvm, fp, arr) local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) local f = ARR[a].feat or "NEON" rows[#rows+1] = string.format( - "\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - mnem, ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) + "\t\t{{.%s, {.%s, .%s, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + canon(mnem), ARR[a].vt, ARR[a].vt, bit.tohex(w0):upper(), bit.tohex(mask):upper(), f) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a @@ -106,7 +185,7 @@ local function emit_cmp0(mnem, llvm, fp, arr) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end -- ---- Uniform shapes (all operands share one arrangement) ------------------- @@ -311,7 +390,7 @@ local function emit_shift(mnem, llvm, dir, variants) end if #rows == 0 then return nil end n_mnem = n_mnem + 1 - return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) + return string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")) end local SAME_SH = {} for _, a in ipairs({"8B","16B","4H","8H","2S","4S","2D"}) do SAME_SH[#SAME_SH+1] = {a, a} end @@ -366,12 +445,12 @@ local ELEM = { do local blk = {} local function emit_rows(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end local function mkrow(mnem, ops, enc, b0, variants) n_forms = n_forms + 1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .NEON, {}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper()) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .NEON, {}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0, variants)):upper(), clobber_of(enc)) end -- MOV Vd.T, Vn.T (= ORR Vd,Vn,Vn): the single source feeds both Vn and Vm. @@ -467,7 +546,7 @@ end do local blk = {} local function block(mnem, rows) - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end -- scalar FP two-register (FRINTx, FRECPX): Sd, Sn. for _, it in ipairs({ @@ -479,8 +558,8 @@ do local function mk(r) return string.format("%s %s%d, %s%d", it[2], sc[1], r, sc[1], r) end local b0, b31 = word(mk(0)), word(mk(31)) if b0 and b31 then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), sc[2], sc[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{b31})):upper(), sc[3]) n_forms = n_forms + 1 end end @@ -499,8 +578,8 @@ do local bD = word(mk(gp[3], fp[1].."0")) -- Rd field (zero reg) local bN = word(mk(gp[1].."0", fp[1].."31")) -- Rn field if b0 and bD and bN then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}},", - it[1], gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) + rows[#rows+1] = string.format("\t\t%s{.%s, .%s, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x%s, 0x%s, .%s, {}}, {written={0}, read={1}}},", + mnem_field(canon(it[1])), gp[2], fp[2], bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bD,bN})):upper(), fp[3]) n_forms = n_forms + 1 end end @@ -526,12 +605,12 @@ do local function mk(r,v) return string.format("%s v%d.%s, #%s", llvm, r, ARR[a].asm, tostring(v)) end local b0, bR, bI = word(mk(0,"0")), word(mk(31,"0")), word(mk(0,vmax)) if b0 and bR and bI then - rows[#rows+1] = string.format("\t\t{.%s, {.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}},", - mnem, ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) + rows[#rows+1] = string.format("\t\t%s{.%s, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x%s, 0x%s, .NEON, {}}, {written={0}}},", + mnem_field(canon(mnem)), ARR[a].vt, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,{bR,bI})):upper()) n_forms = n_forms + 1 else skips[#skips+1] = mnem.." "..a end end - if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")); n_mnem = n_mnem + 1 end + if #rows > 0 then blk[#blk+1] = string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(rows, "\n")); n_mnem = n_mnem + 1 end end imm8_block("MOVI", "movi", {"8B","16B","4H","8H","2S","4S","2D"}) imm8_block("MVNI", "mvni", {"4H","8H","2S","4S"}) @@ -565,12 +644,12 @@ do local w=sve_word(build(v)); if not w then skips[#skips+1]=mnem..":v"..i; return nil end; vs[#vs+1]=w end n_forms=n_forms+1 - return string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .SVE, {%s}},", - mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags) + return string.format("\t\t%s%s, %s, 0x%s, 0x%s, .SVE, {%s}}, %s},", + mnem_field(canon(mnem)), ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), flags, clobber_of(enc)) end local function block(mnem, rows) local r={}; for _,x in ipairs(rows) do if x then r[#r+1]=x end end - if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(r,"\n")); n_mnem=n_mnem+1 end + if #r>0 then blk[#blk+1]=string.format("\t.%s = {\n%s\n\t},", canon(mnem), table.concat(r,"\n")); n_mnem=n_mnem+1 end end local function g(v, x) if v==0 then return x and "x0" or "w0" else return x and "xzr" or "wzr" end end @@ -690,17 +769,68 @@ do sections[#sections+1] = "\t// SVE predicated / compare / predicate-logical / SVE2.\n" .. table.concat(blk, "\n") end --- ---- splice into the SoT --------------------------------------------------- -local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" +-- ---- merge into the SoT ---------------------------------------------------- +-- +-- Every generated block is `\t.MNEM = {\n\n\t},`. Take it apart, and add +-- each row to that mnemonic's existing block ONLY when no form with the same +-- (mnemonic, bits, mask) is present. Existing rows are left byte-for-byte +-- alone so hand-maintained Clobber data survives a regeneration. local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() -local new, n = src:gsub("\t// SPECGEN:BEGIN.-\t// SPECGEN:END", (region:gsub("%%", "%%%%"))) -if n ~= 1 then - io.stderr:write("FATAL: expected exactly one SPECGEN:BEGIN..END region, found "..n.."\n") - os.exit(1) -end -local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close() -io.write(string.format("specgen: wrote %d mnemonics / %d forms into %s\n", n_mnem, n_forms, TABLE)) +local generated = {} -- ordered list of {mnem=, rows={}} +local by_mnem = {} +for _, sec in ipairs(sections) do + for mnem, body in sec:gmatch("\t%.([%w_]+) = {\n(.-)\n\t},") do + local g = by_mnem[mnem] + if not g then + g = {mnem = mnem, rows = {}} + by_mnem[mnem] = g + generated[#generated+1] = g + end + for row in body:gmatch("[^\n]+") do g.rows[#g.rows+1] = row end + end +end + +local added, present, created = 0, 0, 0 +for _, g in ipairs(generated) do + local head = "\t." .. g.mnem .. " = {\n" + local s, e = src:find(head, 1, true) + local fresh = {} + for _, row in ipairs(g.rows) do + -- (bits, mask) uniquely identify a form within one mnemonic's run. + local bits, mask = row:match("(0x%x+), (0x%x+)") + local dup = false + if s and bits then + local _, blk_end = src:find("\n\t},", e, true) + local block = src:sub(e, blk_end or #src) + dup = block:find(bits .. ", " .. mask, 1, true) ~= nil + end + if dup then present = present + 1 else fresh[#fresh+1] = align_row(row) end + end + if #fresh > 0 then + if s then + -- insert BEFORE the block terminator; splitting inside "\n\t}," would + -- leave its comma stranded after the appended rows. + local term = src:find("\n\t},", e, true) + src = src:sub(1, term - 1) .. "\n" .. table.concat(fresh, "\n") .. src:sub(term) + else + src = src:gsub("\n}%s*$", "\n" .. head .. table.concat(fresh, "\n") .. "\n\t},\n}\n", 1) + created = created + 1 + end + added = added + #fresh + end +end + +local wh = assert(io.open(TABLE, "w")); wh:write(src); wh:close() + +io.write(string.format("specgen: %d forms generated across %d mnemonics\n", n_forms, n_mnem)) +io.write(string.format(" already present: %d added: %d new mnemonic blocks: %d\n", present, added, created)) +io.write(" -> " .. TABLE .. "\n") +if added > 0 then + io.write(" NOTE: added rows carry a derived Clobber (dest = slot 0, later\n") + io.write(" register slots = reads). Review it for anything that also\n") + io.write(" touches NZCV/FPSR/memory before committing.\n") +end if #skips > 0 then io.write(" skipped "..#skips.." invalid arrangement(s)\n") end diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 3c031af32e49af8fdac57442cc1e2e5e34f2833c..0d8f5415c43875fc41b054ff11958565ecf7da08 100644 GIT binary patch literal 48720 zcmZXd3z$_^8TZ%Ob8rsBFl=DNQGwY5Lyk&_ML8LJVb_K*vo?g8wINLAH=EGBRp|U?^TK3)vqfPtzu7X)Z-trP49y$# zC-XZ+n9lENVLHE$(EMiY{H}C%zLKaut~wkZ&gT2lbU;T~)bkB#i2-(sebQ z_c>Kg=i@M#j{^q=##OFibVEbS+*z|->c+&6;`Teh)^b4@`vJC=x5C(?PJCeupq3o! zgoQDv8(=)r;E}7g9!G_|)z;&Vkhj|A{ZzuMK%Rp00Lfhp)Q_G=L%RsGVDvy1QsU@ijwbYne zlIub(HO3>~8ulAC#^Z4Es1c7?=68_wxWM<98)QA+@~m!f_^9Z2IG|A8h-Z9r_z=`+G9%7eZcylK4fvN*4M=K)oOiB zTwkrJFDBnwQ{Mt%THp1;w7y+bANoptLqmP&EA`zN>N{BL8_V?_to4oM`cMb`oqqw0 zePL)guA&b5^Q?4ZIIa%U{&L*kFzqkL{S9-H!+o1_3^Uu&OO)df?XQ~qJ4E}d=Kc;b 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run_pipeline_tests :: proc() { byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) ok("barriers/BTI: encode", success) eq_word("SB", load_le(code[:], 0), 0xD50330FF) - eq_word("BTI j", load_le(code[:], 4), 0xD503245F) + eq_word("BTI j", load_le(code[:], 4), 0xD503249F) eq_word("PSB CSYNC", load_le(code[:], 8), 0xD503223F) } diff --git a/core/rexcode/isa/arm64/tests/smoke.odin b/core/rexcode/isa/arm64/tests/smoke.odin index eafcb39b8..22bece4d5 100644 --- a/core/rexcode/isa/arm64/tests/smoke.odin +++ b/core/rexcode/isa/arm64/tests/smoke.odin @@ -234,7 +234,7 @@ main :: proc() { // ---- SME ---------------------------------------------------------------- check("SME_SMSTART", .SMSTART, 0, 0xD503477F, 0xFFFFFFFF) check("SME_SMSTOP", .SMSTOP, 0, 0xD503467F, 0xFFFFFFFF) - check("SME_RDSVL", .RDSVL, 0, 0x04BF5800, 0xFFFFFC00) + check("SME_RDSVL", .RDSVL, 0, 0x04BF5800, 0xFFFFF800) check("FMOPA S", .FMOPA, 0, 0x80800000, 0xFFE08010) check("SME_BFMOPA", .BFMOPA, 0, 0x81800000, 0xFFE08010) check("SMOPA S", .SMOPA, 0, 0xA0800000, 0xFFE08010) @@ -333,10 +333,10 @@ main :: proc() { check("SME_MOVA_TILE_FROM_Z", .MOVA, 1, 0xC0000000, 0xFFE08010) // ---- NEON FCMLA / FCADD (v8.3-A FCMA) -- verified vs LLVM golden ----- - check("FCMLA_4H", .FCMLA, 0, 0x2E40C400, 0xFFA0CC00) - check("FCMLA_8H", .FCMLA, 1, 0x6E40C400, 0xFFA0CC00) - check("FCMLA_4S", .FCMLA, 2, 0x6E80C400, 0xFFA0CC00) - check("FCMLA_2D", .FCMLA, 3, 0x6EC0C400, 0xFFA0CC00) + check("FCMLA_4H", .FCMLA, 0, 0x2E40C400, 0xFFE0CC00) + check("FCMLA_8H", .FCMLA, 1, 0x6E40C400, 0xFFE0CC00) + check("FCMLA_4S", .FCMLA, 2, 0x6E80C400, 0xFFE0CC00) + check("FCMLA_2D", .FCMLA, 3, 0x6EC0C400, 0xFFE0CC00) check("FCADD_4H", .FCADD, 0, 0x2E40E400, 0xFFA0EC00) check("FCADD_4S", .FCADD, 2, 0x6E80E400, 0xFFA0EC00) @@ -363,8 +363,8 @@ main :: proc() { check("SVE_BSL1N", .BSL1N, 0, 0x04603C00, 0xFFE0FC00) check("SVE_NBSL", .NBSL, 0, 0x04E03C00, 0xFFE0FC00) check("SVE_PMUL_VEC",.PMUL,0,0x04206400, 0xFFE0FC00) - check("SVE_PMULLB", .PMULLB, 0, 0x45006800, 0xFFE0FC00) - check("SVE_PMULLT", .PMULLT, 0, 0x45006C00, 0xFFE0FC00) + check("SVE_PMULLB", .PMULLB, 0, 0x45C06800, 0xFFE0FC00) + check("SVE_PMULLT", .PMULLT, 0, 0x45C06C00, 0xFFE0FC00) // ---- SVE BF16 conversions ------------------------------------------- check("SVE_BFCVT", .BFCVT, 1, 0x658AA000, 0xFFFFE000) @@ -426,8 +426,8 @@ main :: proc() { check("DGH", .DGH, 0, 0xD50320DF, 0xFFFFFFFF) check("PSB CSYNC", .PSB_CSYNC, 0, 0xD503223F, 0xFFFFFFFF) check("TSB CSYNC", .TSB_CSYNC, 0, 0xD503225F, 0xFFFFFFFF) - check("BTI j", .BTI_J, 0, 0xD503245F, 0xFFFFFFFF) - check("BTI c", .BTI_C, 0, 0xD503249F, 0xFFFFFFFF) + check("BTI j", .BTI_J, 0, 0xD503249F, 0xFFFFFFFF) + check("BTI c", .BTI_C, 0, 0xD503245F, 0xFFFFFFFF) check("BTI jc", .BTI_JC, 0, 0xD50324DF, 0xFFFFFFFF) // ---- NEON aliases --------------------------------------------------- @@ -466,8 +466,8 @@ main :: proc() { // ---- RME (Realm Management Extension) ------------------------------- check("TLBI RPALOS", .TLBI_RPALOS, 0, 0xD5084EE0, 0xFFFFFFE0) check("TLBI RPAOS", .TLBI_RPAOS, 0, 0xD5084EA0, 0xFFFFFFE0) - check("TLBI PAALL", .TLBI_PAALL, 0, 0xD508E89F, 0xFFFFFFFF) - check("TLBI PAALLOS", .TLBI_PAALLOS, 0, 0xD508E81F, 0xFFFFFFFF) + check("TLBI PAALL", .TLBI_PAALL, 0, 0xD50E879F, 0xFFFFFFFF) + check("TLBI PAALLOS", .TLBI_PAALLOS, 0, 0xD50E819F, 0xFFFFFFFF) check("AT S1E1A", .AT_S1E1A, 0, 0xD5079140, 0xFFFFFFE0) check("DC CIPAPA", .DC_CIPAPA, 0, 0xD50E7CE0, 0xFFFFFFE0) check("DC CIGDPAPA", .DC_CIGDPAPA, 0, 0xD50E7DE0, 0xFFFFFFE0) From 5cba6402f61540c7a6ec5a65f61f38cf5f09ef1a Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Wed, 26 Aug 2026 20:46:33 -0400 Subject: [PATCH 09/89] rexcode: fix the mnemonic problems in arm32, mips, riscv and mos6502 The arm64 pass turned up the same class of bug elsewhere: mnemonics named after an encoding rather than after what an assembler accepts, and forms that no caller can reach because the thing that tells them apart is not checked. mips * The printer mapped every `_` to `.`, but MSA spells the sign qualifier with an underscore and only the element size with a dot: `adds_s.b`, `max_s.h`, `copy_u.w`. `adds.s.b` is rejected by an assembler. 91 mnemonics were printing text that would not reassemble. The name alone cannot decide it -- MSA's ADDS_S_D and the FP convert CVT_S_D have the same shape and want opposite treatment -- so the family is read off the form's feature. * `encode` now takes `features: Feature_Set = FEATURES_ALL` and skips forms outside it, mirroring `decode`, which has had that parameter all along. That asymmetry was the reason 12 mnemonics carried an ISA-variant suffix: with no way to say which MIPS you were targeting, the pre-R6 and R6 encodings of `mul` had to be two enum members. They are now one mnemonic with two forms. Eight of the twelve did not even need the feature filter -- pre-R6 MADD takes rs,rt while the PS2 MMI MADD takes rd,rs,rt, so operand matching alone separates them. Verified against llvm-mc: pre-R6 `mul` 712a4002, R6 `mul` 012a4098, `madd $t1,$t2` 712a0000. The printer's hand-written override table is gone. arm32 * 20 `*_LANE` mnemonics folded into their base. The lane form differs from the base in an operand TYPE already (DPR_ELEM vs DPR), so the matcher could always tell them apart; the split only cost us the printed name, which was the enum name verbatim -- `vqdmulh_lane`, which no assembler takes. VMOV/VLD1-4/VST1-4 are left alone: their lane forms collide with the base because register lists and lane indices are not modelled. riscv * ZEXT_H and REV8 each carry an RV32 and an RV64 encoding with identical operands, and the forms were already tagged rv32_only / rv64_only -- the encoder just never looked. `encode` now takes `xlen: XLEN = .RV64` and filters, so the RV64 encodings are reachable at all: zext.h 0805c53b and rev8 6b85d513, both confirmed against llvm-mc. mos6502 * SAX_NMOS folded into SAX. The undocumented NMOS store-A&X and the HuC6280 register swap share the mnemonic `sax`; one takes a memory operand and the other takes none, so they are just two form sets. Verified: every rexcode suite matches HEAD exactly, all 13 packages build, and MIPS mnemonics llvm-mc does not recognise drop from 448 to 354. Still open: arm32 has 201 form signatures no caller can select, because the NEON data type (.i8/.i16/.f32) is not an operand -- `inst_vadd(d0,d1,d2)` always yields the first form, and only a decoder-supplied form_id hint can pick another. 38 arm32 mnemonics still carry encoding-shaped names (VPADD_F, VCEQ_Z, VLDRB_GATHER, VMOV_Q_R, ...). Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/mnemonic_builders.odin | 200 ++-- core/rexcode/isa/arm32/mnemonics.odin | 15 +- .../isa/arm32/tablegen/encoding_table.odin | 184 ++-- .../tablegen/generated/decode_tables.odin | 504 +++++----- .../tablegen/generated/encode_tables.odin | 516 +++++------ .../isa/arm32/tables/arm32.bucket_list.bin | Bin 11106 -> 11106 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 35280 -> 35280 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 5064 -> 4904 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 35280 -> 35280 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3360 -> 3360 bytes core/rexcode/isa/arm32/tests/smoke.odin | 34 +- core/rexcode/isa/mips/encoder.odin | 8 +- core/rexcode/isa/mips/mnemonic_builders.odin | 96 +- core/rexcode/isa/mips/mnemonics.odin | 11 +- core/rexcode/isa/mips/printer.odin | 58 +- .../isa/mips/tablegen/encoding_table.odin | 66 +- .../tablegen/generated/decode_tables.odin | 24 +- .../tablegen/generated/encode_tables.odin | 868 +++++++++--------- .../isa/mips/tables/mips.encode_forms.bin | Bin 20580 -> 20580 bytes .../isa/mips/tables/mips.encode_runs.bin | Bin 8240 -> 8168 bytes core/rexcode/isa/mips/tables/mips.entries.bin | Bin 20580 -> 20580 bytes .../isa/mos6502/mnemonic_builders.odin | 10 +- core/rexcode/isa/mos6502/mnemonics.odin | 10 +- core/rexcode/isa/mos6502/printer.odin | 12 +- .../isa/mos6502/tablegen/encoding_table.odin | 18 +- .../tablegen/generated/decode_tables.odin | 8 +- .../tablegen/generated/encode_tables.odin | 298 +++--- .../mos6502/tables/mos6502.encode_forms.bin | Bin 4494 -> 4494 bytes .../mos6502/tables/mos6502.encode_runs.bin | Bin 1160 -> 1152 bytes .../isa/mos6502/tables/mos6502.entries.bin | Bin 3852 -> 3852 bytes core/rexcode/isa/mos6502/tests/smoke.odin | 4 +- core/rexcode/isa/riscv/decoder.odin | 4 +- core/rexcode/isa/riscv/encoder.odin | 7 +- 33 files changed, 1418 insertions(+), 1537 deletions(-) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 1d53fc79e..abc7db354 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -661,13 +661,19 @@ emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]I inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) } inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmul_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) } +emit_vmul_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_d_d_dlane(dst, src, src2, lane)) } inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) } inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmla_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) } +emit_vmla_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_d_d_dlane(dst, src, src2, lane)) } inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmls_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) } +emit_vmls_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_d_d_dlane(dst, src, src2, lane)) } inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) } inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -675,9 +681,13 @@ emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]I inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vfma_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } +emit_vfma_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_d_d_dlane(dst, src, src2, lane)) } inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vfms_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } +emit_vfms_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_d_d_dlane(dst, src, src2, lane)) } inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -779,29 +789,45 @@ emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]I inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) } inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) } +emit_vmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_q_d_dlane(dst, src, src2, lane)) } inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) } +emit_vmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_q_d_dlane(dst, src, src2, lane)) } inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) } +emit_vmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_q_d_dlane(dst, src, src2, lane)) } inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) } +emit_vqdmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_q_d_dlane(dst, src, src2, lane)) } inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) } +emit_vqdmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_q_d_dlane(dst, src, src2, lane)) } inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) } +emit_vqdmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_q_d_dlane(dst, src, src2, lane)) } inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) } +emit_vqdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_d_d_dlane(dst, src, src2, lane)) } inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) } -inst_vqdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_lane_d_d_dlane(dst, src, src2, lane)) } +emit_vqrdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_d_d_dlane(dst, src, src2, lane)) } inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmlah_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) } +emit_vqrdmlah_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_d_d_dlane(dst, src, src2, lane)) } inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmlsh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) } +emit_vqrdmlsh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_d_d_dlane(dst, src, src2, lane)) } inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) } inst_vabal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -1011,13 +1037,13 @@ emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]I inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) } inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vsdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) } +emit_vsdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_d_d_dlane(dst, src, src2, lane)) } inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vudot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) } -inst_vsdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vsdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vudot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vudot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_lane_d_d_dlane(dst, src, src2, lane)) } +emit_vudot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_d_d_dlane(dst, src, src2, lane)) } inst_vcvt_bf16_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT_BF16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vcvt_bf16_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_bf16_d_q(dst, src)) } inst_vdot_bf16_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -1031,11 +1057,11 @@ emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]I inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +inst_vcmla_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } +emit_vcmla_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_d_d_dlane_imm(dst, src, src2, lane, imm)) } inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) } -inst_vcmla_lane_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA_LANE, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } -emit_vcmla_lane_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_lane_d_d_dlane_imm(dst, src, src2, lane, imm)) } inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) } inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -1043,39 +1069,13 @@ emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]I inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) } inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vsudot_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) } +emit_vsudot_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_q_q_dlane(dst, src, src2, lane)) } inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vusdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) } -inst_vsudot_lane_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vsudot_lane_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_lane_q_q_dlane(dst, src, src2, lane)) } -inst_vusdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vusdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vmul_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmul_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vmla_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmla_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vmls_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmls_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_lane_q_d_dlane(dst, src, src2, lane)) } -inst_vfma_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vfma_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vfms_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vfms_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmlah_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmlah_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_lane_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmlsh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmlsh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_lane_d_d_dlane(dst, src, src2, lane)) } +emit_vusdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_d_d_dlane(dst, src, src2, lane)) } inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) } inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -1957,24 +1957,24 @@ inst_vadd :: inst_vadd_s_s_s emit_vadd :: emit_vadd_s_s_s inst_vsub :: inst_vsub_s_s_s emit_vsub :: emit_vsub_s_s_s -inst_vmul :: inst_vmul_s_s_s -emit_vmul :: emit_vmul_s_s_s +inst_vmul :: proc{ inst_vmul_s_s_s, inst_vmul_d_d_dlane } +emit_vmul :: proc{ emit_vmul_s_s_s, emit_vmul_d_d_dlane } inst_vdiv :: inst_vdiv_s_s_s emit_vdiv :: emit_vdiv_s_s_s -inst_vmla :: inst_vmla_s_s_s -emit_vmla :: emit_vmla_s_s_s -inst_vmls :: inst_vmls_s_s_s -emit_vmls :: emit_vmls_s_s_s +inst_vmla :: proc{ inst_vmla_s_s_s, inst_vmla_d_d_dlane } +emit_vmla :: proc{ emit_vmla_s_s_s, emit_vmla_d_d_dlane } +inst_vmls :: proc{ inst_vmls_s_s_s, inst_vmls_d_d_dlane } +emit_vmls :: proc{ emit_vmls_s_s_s, emit_vmls_d_d_dlane } inst_vnmul :: inst_vnmul_s_s_s emit_vnmul :: emit_vnmul_s_s_s inst_vnmla :: inst_vnmla_s_s_s emit_vnmla :: emit_vnmla_s_s_s inst_vnmls :: inst_vnmls_s_s_s emit_vnmls :: emit_vnmls_s_s_s -inst_vfma :: inst_vfma_s_s_s -emit_vfma :: emit_vfma_s_s_s -inst_vfms :: inst_vfms_s_s_s -emit_vfms :: emit_vfms_s_s_s +inst_vfma :: proc{ inst_vfma_s_s_s, inst_vfma_d_d_dlane } +emit_vfma :: proc{ emit_vfma_s_s_s, emit_vfma_d_d_dlane } +inst_vfms :: proc{ inst_vfms_s_s_s, inst_vfms_d_d_dlane } +emit_vfms :: proc{ emit_vfms_s_s_s, emit_vfms_d_d_dlane } inst_vfnma :: inst_vfnma_s_s_s emit_vfnma :: emit_vfnma_s_s_s inst_vfnms :: inst_vfnms_s_s_s @@ -2061,30 +2061,26 @@ inst_vqadd :: inst_vqadd_d_d_d emit_vqadd :: emit_vqadd_d_d_d inst_vqsub :: inst_vqsub_d_d_d emit_vqsub :: emit_vqsub_d_d_d -inst_vmull :: inst_vmull_q_d_d -emit_vmull :: emit_vmull_q_d_d -inst_vmlal :: inst_vmlal_q_d_d -emit_vmlal :: emit_vmlal_q_d_d -inst_vmlsl :: inst_vmlsl_q_d_d -emit_vmlsl :: emit_vmlsl_q_d_d -inst_vqdmull :: inst_vqdmull_q_d_d -emit_vqdmull :: emit_vqdmull_q_d_d -inst_vqdmlal :: inst_vqdmlal_q_d_d -emit_vqdmlal :: emit_vqdmlal_q_d_d -inst_vqdmlsl :: inst_vqdmlsl_q_d_d -emit_vqdmlsl :: emit_vqdmlsl_q_d_d -inst_vqdmulh :: inst_vqdmulh_d_d_d -emit_vqdmulh :: emit_vqdmulh_d_d_d -inst_vqrdmulh :: inst_vqrdmulh_d_d_d -emit_vqrdmulh :: emit_vqrdmulh_d_d_d -inst_vqdmulh_lane :: inst_vqdmulh_lane_d_d_dlane -emit_vqdmulh_lane :: emit_vqdmulh_lane_d_d_dlane -inst_vqrdmulh_lane :: inst_vqrdmulh_lane_d_d_dlane -emit_vqrdmulh_lane :: emit_vqrdmulh_lane_d_d_dlane -inst_vqrdmlah :: inst_vqrdmlah_d_d_d -emit_vqrdmlah :: emit_vqrdmlah_d_d_d -inst_vqrdmlsh :: inst_vqrdmlsh_d_d_d -emit_vqrdmlsh :: emit_vqrdmlsh_d_d_d +inst_vmull :: proc{ inst_vmull_q_d_d, inst_vmull_q_d_dlane } +emit_vmull :: proc{ emit_vmull_q_d_d, emit_vmull_q_d_dlane } +inst_vmlal :: proc{ inst_vmlal_q_d_d, inst_vmlal_q_d_dlane } +emit_vmlal :: proc{ emit_vmlal_q_d_d, emit_vmlal_q_d_dlane } +inst_vmlsl :: proc{ inst_vmlsl_q_d_d, inst_vmlsl_q_d_dlane } +emit_vmlsl :: proc{ emit_vmlsl_q_d_d, emit_vmlsl_q_d_dlane } +inst_vqdmull :: proc{ inst_vqdmull_q_d_d, inst_vqdmull_q_d_dlane } +emit_vqdmull :: proc{ emit_vqdmull_q_d_d, emit_vqdmull_q_d_dlane } +inst_vqdmlal :: proc{ inst_vqdmlal_q_d_d, inst_vqdmlal_q_d_dlane } +emit_vqdmlal :: proc{ emit_vqdmlal_q_d_d, emit_vqdmlal_q_d_dlane } +inst_vqdmlsl :: proc{ inst_vqdmlsl_q_d_d, inst_vqdmlsl_q_d_dlane } +emit_vqdmlsl :: proc{ emit_vqdmlsl_q_d_d, emit_vqdmlsl_q_d_dlane } +inst_vqdmulh :: proc{ inst_vqdmulh_d_d_d, inst_vqdmulh_d_d_dlane } +emit_vqdmulh :: proc{ emit_vqdmulh_d_d_d, emit_vqdmulh_d_d_dlane } +inst_vqrdmulh :: proc{ inst_vqrdmulh_d_d_d, inst_vqrdmulh_d_d_dlane } +emit_vqrdmulh :: proc{ emit_vqrdmulh_d_d_d, emit_vqrdmulh_d_d_dlane } +inst_vqrdmlah :: proc{ inst_vqrdmlah_d_d_d, inst_vqrdmlah_d_d_dlane } +emit_vqrdmlah :: proc{ emit_vqrdmlah_d_d_d, emit_vqrdmlah_d_d_dlane } +inst_vqrdmlsh :: proc{ inst_vqrdmlsh_d_d_d, inst_vqrdmlsh_d_d_dlane } +emit_vqrdmlsh :: proc{ emit_vqrdmlsh_d_d_d, emit_vqrdmlsh_d_d_dlane } inst_vaba :: inst_vaba_d_d_d emit_vaba :: emit_vaba_d_d_d inst_vabal :: inst_vabal_q_d_d @@ -2277,14 +2273,10 @@ inst_sha256su1 :: inst_sha256su1_q_q_q emit_sha256su1 :: emit_sha256su1_q_q_q inst_vjcvt :: inst_vjcvt_s_d emit_vjcvt :: emit_vjcvt_s_d -inst_vsdot :: inst_vsdot_d_d_d -emit_vsdot :: emit_vsdot_d_d_d -inst_vudot :: inst_vudot_d_d_d -emit_vudot :: emit_vudot_d_d_d -inst_vsdot_lane :: inst_vsdot_lane_d_d_dlane -emit_vsdot_lane :: emit_vsdot_lane_d_d_dlane -inst_vudot_lane :: inst_vudot_lane_d_d_dlane -emit_vudot_lane :: emit_vudot_lane_d_d_dlane +inst_vsdot :: proc{ inst_vsdot_d_d_d, inst_vsdot_d_d_dlane } +emit_vsdot :: proc{ emit_vsdot_d_d_d, emit_vsdot_d_d_dlane } +inst_vudot :: proc{ inst_vudot_d_d_d, inst_vudot_d_d_dlane } +emit_vudot :: proc{ emit_vudot_d_d_d, emit_vudot_d_d_dlane } inst_vcvt_bf16 :: inst_vcvt_bf16_d_q emit_vcvt_bf16 :: emit_vcvt_bf16_d_q inst_vdot_bf16 :: inst_vdot_bf16_d_d_d @@ -2297,52 +2289,20 @@ inst_vfmal :: inst_vfmal_d_d_d emit_vfmal :: emit_vfmal_d_d_d inst_vfmsl :: inst_vfmsl_d_d_d emit_vfmsl :: emit_vfmsl_d_d_d -inst_vcmla :: inst_vcmla_d_d_d_imm -emit_vcmla :: emit_vcmla_d_d_d_imm +inst_vcmla :: proc{ inst_vcmla_d_d_d_imm, inst_vcmla_d_d_dlane_imm } +emit_vcmla :: proc{ emit_vcmla_d_d_d_imm, emit_vcmla_d_d_dlane_imm } inst_vcadd :: inst_vcadd_d_d_d_imm emit_vcadd :: emit_vcadd_d_d_d_imm -inst_vcmla_lane :: inst_vcmla_lane_d_d_dlane_imm -emit_vcmla_lane :: emit_vcmla_lane_d_d_dlane_imm inst_vsmmla :: inst_vsmmla_q_q_q emit_vsmmla :: emit_vsmmla_q_q_q inst_vummla :: inst_vummla_q_q_q emit_vummla :: emit_vummla_q_q_q inst_vusmmla :: inst_vusmmla_q_q_q emit_vusmmla :: emit_vusmmla_q_q_q -inst_vsudot :: inst_vsudot_q_q_q -emit_vsudot :: emit_vsudot_q_q_q -inst_vusdot :: inst_vusdot_d_d_d -emit_vusdot :: emit_vusdot_d_d_d -inst_vsudot_lane :: inst_vsudot_lane_q_q_dlane -emit_vsudot_lane :: emit_vsudot_lane_q_q_dlane -inst_vusdot_lane :: inst_vusdot_lane_d_d_dlane -emit_vusdot_lane :: emit_vusdot_lane_d_d_dlane -inst_vmul_lane :: inst_vmul_lane_d_d_dlane -emit_vmul_lane :: emit_vmul_lane_d_d_dlane -inst_vmla_lane :: inst_vmla_lane_d_d_dlane -emit_vmla_lane :: emit_vmla_lane_d_d_dlane -inst_vmls_lane :: inst_vmls_lane_d_d_dlane -emit_vmls_lane :: emit_vmls_lane_d_d_dlane -inst_vmull_lane :: inst_vmull_lane_q_d_dlane -emit_vmull_lane :: emit_vmull_lane_q_d_dlane -inst_vmlal_lane :: inst_vmlal_lane_q_d_dlane -emit_vmlal_lane :: emit_vmlal_lane_q_d_dlane -inst_vmlsl_lane :: inst_vmlsl_lane_q_d_dlane -emit_vmlsl_lane :: emit_vmlsl_lane_q_d_dlane -inst_vqdmull_lane :: inst_vqdmull_lane_q_d_dlane -emit_vqdmull_lane :: emit_vqdmull_lane_q_d_dlane -inst_vqdmlal_lane :: inst_vqdmlal_lane_q_d_dlane -emit_vqdmlal_lane :: emit_vqdmlal_lane_q_d_dlane -inst_vqdmlsl_lane :: inst_vqdmlsl_lane_q_d_dlane -emit_vqdmlsl_lane :: emit_vqdmlsl_lane_q_d_dlane -inst_vfma_lane :: inst_vfma_lane_d_d_dlane -emit_vfma_lane :: emit_vfma_lane_d_d_dlane -inst_vfms_lane :: inst_vfms_lane_d_d_dlane -emit_vfms_lane :: emit_vfms_lane_d_d_dlane -inst_vqrdmlah_lane :: inst_vqrdmlah_lane_d_d_dlane -emit_vqrdmlah_lane :: emit_vqrdmlah_lane_d_d_dlane -inst_vqrdmlsh_lane :: inst_vqrdmlsh_lane_d_d_dlane -emit_vqrdmlsh_lane :: emit_vqrdmlsh_lane_d_d_dlane +inst_vsudot :: proc{ inst_vsudot_q_q_q, inst_vsudot_q_q_dlane } +emit_vsudot :: proc{ emit_vsudot_q_q_q, emit_vsudot_q_q_dlane } +inst_vusdot :: proc{ inst_vusdot_d_d_d, inst_vusdot_d_d_dlane } +emit_vusdot :: proc{ emit_vusdot_d_d_d, emit_vusdot_d_d_dlane } inst_vqabs :: inst_vqabs_q_q emit_vqabs :: emit_vqabs_q_q inst_vqneg :: inst_vqneg_q_q diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index fbe1783ba..5331c2a5d 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -251,7 +251,7 @@ Mnemonic :: enum u16 { VMULL, VMLAL, VMLSL, VQDMULL,VQDMLAL,VQDMLSL, VQDMULH,VQRDMULH, - VQDMULH_LANE, VQRDMULH_LANE, // indexed variants + // indexed variants // ARMv8.1 FEAT_RDM: rounding doubling multiply-accumulate VQRDMLAH, VQRDMLSH, @@ -310,8 +310,6 @@ Mnemonic :: enum u16 { // -- Dot Product (FEAT_DotProd) ------------------------------------------ VSDOT, VUDOT, - VSDOT_LANE, VUDOT_LANE, - // -- BF16 (FEAT_BF16) ---------------------------------------------------- VCVT_BF16, // BF16<->F32 VDOT_BF16, @@ -323,7 +321,7 @@ Mnemonic :: enum u16 { // -- ComplexNum (FEAT_FCMA) ---------------------------------------------- VCMLA, VCADD, - VCMLA_LANE, // VCMLA by indexed scalar + // VCMLA by indexed scalar // -- I8MM (FEAT_I8MM, ARMv8.6) integer matrix multiply + mixed-sign dot -- VSMMLA, // signed-signed 8x8 matrix mul @@ -331,16 +329,7 @@ Mnemonic :: enum u16 { VUSMMLA, // unsigned-signed VSUDOT, // signed-unsigned dot product VUSDOT, // unsigned-signed dot product - VSUDOT_LANE, - VUSDOT_LANE, - // -- Lane-indexed NEON multiply / MAC forms (heavily used in DSP/codec) -- - VMUL_LANE, VMLA_LANE, VMLS_LANE, - VMULL_LANE, VMLAL_LANE, VMLSL_LANE, - VQDMULL_LANE, VQDMLAL_LANE, VQDMLSL_LANE, - VFMA_LANE, VFMS_LANE, - VQRDMLAH_LANE, VQRDMLSH_LANE, - // -- MVE saturating unary ----------------------------------------------- VQABS, VQNEG, diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 030267096..f44fc2b13 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1389,6 +1389,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // MVE FP vector + scalar {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, + {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, }, .VFMS = { {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}}, @@ -1400,6 +1402,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, // MVE FP vector {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, + {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, }, .VFNMS = { {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}}, @@ -1718,6 +1722,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, // VMUL MVE scalar: per LLVM 0xEE05_3E63 -> base 0xEE011E60 {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + // Integer D-form .I16/.I32 + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // Integer Q-form .I16/.I32 (bit 24 = 1) + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // FP .F32 D-form / Q-form (F=1, size=10) + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { @@ -1737,6 +1750,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, // MVE VMLA Qda, Qn, Rm (scalar) {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // FP .F32 (F=1) + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, .VMLS = { {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}}, @@ -1753,6 +1773,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON F32 (bit 21 = 1 distinguishes FMLS from FMLA) {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // FP .F32 + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { @@ -2336,6 +2363,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, // polynomial: U=0, op=10 {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // signed .S16/.S32 + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + // unsigned .U16/.U32 (top byte 0xF3) + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // VMLAL / VMLSL (widening multiply-accumulate) // VMLAL: signed F2800800 / unsigned F3800800; op=1000 (no minus); minus bit at 21 @@ -2346,6 +2379,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, .VMLSL = { // VMLSL: op=1010 (bit 9 = 1) @@ -2355,6 +2392,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // ---- VQDMULH / VQRDMULH (saturating doubling multiply, high half) ---- @@ -2365,12 +2406,20 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, }, .VQRDMULH = { {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, }, // ---- VQRDMLAH / VQRDMLSH (ARMv8.1 FEAT_RDM, rounding doubling MAC) ---- // VQRDMLAH: 1111 0011 0 D size Vn Vd 1011 N Q M 1 Vm (size = 01 .S16 or 10 .S32) @@ -2380,28 +2429,42 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, }, .VQRDMLSH = { {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, }, // VQDMULL: 1111 0010 1 D size Vn Vd 1101 N 0 M 0 Vm .VQDMULL = { {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // VQDMLAL / VQDMLSL (saturating doubling multiply-accumulate long) .VQDMLAL = { // signed: 1111 0010 1 D size Vn Vd 1001 N 0 M 0 Vm {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, .VQDMLSL = { // signed: 1111 0010 1 D size Vn Vd 1011 N 0 M 0 Vm {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, }, // ---- VMOVL / VMOVN / VQMOVN / VQMOVUN (widening/narrowing moves) ---- @@ -2635,21 +2698,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VSDOT.S8 D: 0xFC200D00 {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, + {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, }, // VUDOT (unsigned): bit 4 = 1 distinguishes from VSDOT (bit 4 = 0). // vudot.u8 d0,d1,d2 = 0xFC21_0D12 -> base 0xFC200D10 .VUDOT = { {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, - }, - .VSDOT_LANE = { - {.VSDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, - }, - .VUDOT_LANE = { // vudot.u8 d0,d1,d2[0] = 0xFE21_0D12 -> base 0xFE200D10 (bit 4 = 1 for U) - {.VUDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VUDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, }, // FEAT_FCMA (ARMv8.3): VCMLA / VCADD (complex multiply-add + add) @@ -2659,6 +2718,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}}, }, .VCADD = { // Mask 0xFE800F10 leaves bit 24 variable for rotation operand (90 or 270) @@ -2716,17 +2777,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only) .VSUDOT = { {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, }, .VUSDOT = { {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - }, - .VSUDOT_LANE = { - {.VSUDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - }, - .VUSDOT_LANE = { - {.VUSDOT_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, + {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, }, // ========================================================================= @@ -2738,102 +2795,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VMUL by scalar: opcode bits[11:8] = 1000; Q bit at bit 24 (0=D, 1=Q); // size bits 21:20; F bit at bit 7 (0=integer, 1=FP F32) - .VMUL_LANE = { - // Integer D-form .I16/.I32 - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - // Integer Q-form .I16/.I32 (bit 24 = 1) - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - // FP .F32 D-form / Q-form (F=1, size=10) - {.VMUL_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMLA by scalar: opcode bits[11:8] = 0000 - .VMLA_LANE = { - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - // FP .F32 (F=1) - {.VMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMLS by scalar: opcode bits[11:8] = 0100 - .VMLS_LANE = { - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - // FP .F32 - {.VMLS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMULL by scalar: opcode bits[11:8] = 1010. Long: Q dest from D inputs. - .VMULL_LANE = { - // signed .S16/.S32 - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - // unsigned .U16/.U32 (top byte 0xF3) - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMLAL by scalar: opcode bits[11:8] = 0010 - .VMLAL_LANE = { - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMLSL by scalar: opcode bits[11:8] = 0110 - .VMLSL_LANE = { - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VQDMULL by scalar: opcode bits[11:8] = 1011 (signed only) - .VQDMULL_LANE = { - {.VQDMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VQDMLAL by scalar: opcode bits[11:8] = 0011 - .VQDMLAL_LANE = { - {.VQDMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VQDMLSL by scalar: opcode bits[11:8] = 0111 - .VQDMLSL_LANE = { - {.VQDMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL_LANE, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - }, // VFMA / VFMS by scalar -- FEAT_FCMA adds these as opcode 0001 / 0101 with F=1 - .VFMA_LANE = { - {.VFMA_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMA_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - }, - .VFMS_LANE = { - {.VFMS_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMS_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - }, // VQRDMLAH / VQRDMLSH by scalar (FEAT_RDM): opcode 1110 / 1111, bit 4 = 1 - .VQRDMLAH_LANE = { - {.VQRDMLAH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - }, - .VQRDMLSH_LANE = { - {.VQRDMLSH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - }, // VCMLA by indexed scalar (FEAT_FCMA) - .VCMLA_LANE = { - {.VCMLA_LANE, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA_LANE, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}}, - }, // ========================================================================= // MVE polish (gaps from earlier pass) @@ -3686,18 +3658,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON (saturating) doubling multiply-high by scalar Dm[lane]: // .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5. - .VQDMULH_LANE = { - {.VQDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - }, - .VQRDMULH_LANE = { - {.VQRDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - }, // VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on // the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size. .VMOV_LANE = { diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index cdc61797a..3424fc6b3 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {} }, @@ -215,8 +215,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {} }, @@ -262,13 +262,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, @@ -371,39 +371,39 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {} }, @@ -427,25 +427,25 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMLAH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {} }, @@ -454,30 +454,30 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, - { .VFMA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VQRDMLAH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {} }, { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {} }, @@ -503,8 +503,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {} }, { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {} }, @@ -530,8 +530,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {} }, { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {} }, { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {} }, @@ -585,8 +585,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {} }, @@ -657,152 +657,152 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMLAH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, 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0xF3B00540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {} }, { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {} }, { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} }, { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {} }, @@ -829,46 +829,46 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {} }, { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {} }, @@ -888,8 +888,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {} }, @@ -1059,8 +1059,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, - { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {} }, @@ -1071,19 +1071,19 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {} }, { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {} }, - { .VCMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, - { .VCMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {} }, + { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {} }, @@ -1097,21 +1097,21 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {} }, { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {} }, - { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {} }, { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {} }, { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {} }, - { .VSDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, - { .VUDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, - { .VSDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -1119,13 +1119,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {} }, - { .VSUDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, - { .VUSDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {} }, - { .VUSDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -1137,23 +1137,23 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, + { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {} }, { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {} }, @@ -1164,37 +1164,37 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {} }, + { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {} }, + { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {} }, { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {} }, + { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {} }, { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, @@ -1204,9 +1204,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, @@ -1277,8 +1277,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, @@ -1705,50 +1705,50 @@ DECODE_FORM_IDX := [1680]u16{ 0, 2, 1, 0, 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 14, 9, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, - 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, + 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 25, 22, 21, 23, 0, 0, - 0, 0, 10, 11, 14, 10, 13, 11, 19, 16, 12, 15, 20, 17, 18, 6, - 0, 0, 0, 3, 4, 2, 9, 8, 5, 7, 6, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 22, 25, 23, 21, 0, 0, + 0, 0, 11, 10, 14, 17, 19, 11, 16, 10, 13, 12, 18, 20, 15, 6, + 0, 0, 0, 4, 7, 2, 9, 3, 5, 6, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 5, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 2, 2, 1, 4, 1, 4, 4, 1, 1, 1, 1, 1, 1, - 1, 0, 0, 1, 1, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, - 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 9, 7, + 1, 1, 18, 12, 11, 1, 7, 6, 1, 6, 1, 2, 0, 2, 0, 0, + 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 19, 22, 16, + 13, 12, 15, 7, 6, 8, 2, 7, 2, 2, 7, 1, 3, 3, 1, 1, + 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, + 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, - 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, + 3, 6, 6, 8, 8, 6, 6, 0, 0, 6, 8, 6, 0, 6, 6, 4, 3, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, - 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, + 13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1, - 2, 2, 2, 0, 0, 0, 4, 4, 1, 1, 4, 4, 4, 4, 4, 4, - 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 5, 3, 3, 5, - 5, 5, 5, 5, 5, 5, 5, 5, 3, 5, 3, 5, 3, 3, 3, 3, - 1, 1, 3, 3, 0, 3, 2, 1, 0, 1, 3, 2, 0, 0, 1, 1, - 0, 0, 0, 0, 0, 6, 5, 3, 4, 7, 8, 9, 2, 7, 9, 2, - 6, 8, 3, 5, 4, 1, 0, 0, 1, 2, 3, 5, 2, 0, 1, 4, - 2, 0, 1, 4, 2, 1, 0, 5, 3, 0, 1, 2, 3, 2, 4, 3, - 1, 0, 5, 3, 4, 2, 5, 1, 3, 0, 2, 4, 1, 0, 1, 0, - 1, 0, 2, 3, 2, 4, 0, 3, 5, 1, 3, 2, 5, 0, 1, 4, - 3, 1, 0, 2, 4, 3, 0, 4, 1, 2, 1, 0, 0, 0, 0, 0, + 2, 2, 2, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, + 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, 5, + 5, 5, 5, 5, 23, 21, 15, 17, 14, 16, 8, 7, 10, 5, 5, 9, + 9, 5, 7, 7, 0, 1, 0, 2, 3, 1, 0, 3, 2, 0, 1, 0, + 1, 0, 0, 0, 0, 7, 4, 6, 5, 8, 3, 9, 2, 6, 4, 2, + 5, 3, 7, 8, 9, 1, 0, 2, 1, 0, 4, 5, 3, 1, 2, 0, + 0, 1, 2, 2, 0, 3, 1, 4, 5, 0, 3, 2, 1, 3, 4, 2, + 3, 1, 5, 0, 2, 4, 2, 5, 4, 3, 0, 1, 0, 1, 1, 0, + 2, 1, 0, 3, 0, 5, 3, 4, 1, 2, 2, 5, 3, 1, 4, 0, + 0, 1, 4, 3, 2, 4, 0, 1, 2, 3, 1, 0, 0, 0, 0, 0, 0, 1, 3, 2, 0, 1, 2, 3, 2, 0, 1, 3, 3, 1, 2, 0, - 0, 3, 1, 2, 1, 3, 0, 2, 2, 1, 3, 0, 2, 3, 3, 0, - 3, 0, 3, 2, 3, 0, 1, 2, 1, 0, 1, 0, 0, 1, 3, 0, - 1, 2, 1, 2, 0, 0, 1, 1, 0, 6, 4, 5, 1, 2, 0, 2, - 0, 1, 0, 2, 1, 2, 1, 0, 2, 2, 0, 0, 0, 5, 4, 7, - 6, 2, 1, 0, 2, 0, 1, 0, 2, 1, 2, 1, 0, 0, 0, 2, + 0, 3, 1, 2, 3, 2, 0, 1, 3, 1, 0, 2, 3, 2, 3, 0, + 3, 0, 3, 0, 2, 3, 1, 0, 2, 1, 1, 0, 0, 1, 2, 3, + 1, 0, 2, 1, 0, 1, 0, 1, 0, 6, 5, 4, 1, 2, 0, 2, + 0, 1, 0, 2, 1, 2, 1, 0, 2, 2, 0, 0, 0, 5, 4, 6, + 7, 2, 1, 0, 2, 0, 1, 0, 2, 1, 2, 1, 0, 0, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1758,21 +1758,21 @@ DECODE_FORM_IDX := [1680]u16{ 0, 0, 0, 0, 3, 3, 0, 0, 0, 3, 3, 0, 0, 3, 0, 3, 0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, - 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 1, 0, 4, 2, 1, 1, - 0, 1, 0, 27, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 5, 26, - 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 2, 0, 1, 1, 0, 2, - 2, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 2, 1, 0, - 2, 2, 1, 0, 1, 0, 2, 2, 1, 0, 1, 0, 2, 3, 5, 2, - 3, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, - 0, 1, 0, 1, 0, 2, 1, 0, 9, 7, 6, 8, 3, 2, 4, 0, - 1, 5, 0, 1, 1, 0, 3, 1, 0, 2, 1, 0, 0, 1, 1, 0, - 1, 0, 0, 8, 9, 7, 2, 1, 3, 6, 0, 0, 1, 4, 0, 1, + 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 1, 0, 0, 1, 1, 0, + 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3, + 2, 0, 1, 27, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 5, 26, + 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, 2, + 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 1, 0, 2, 2, 1, 0, + 2, 2, 1, 0, 1, 0, 2, 2, 0, 1, 0, 1, 5, 3, 2, 3, + 2, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 1, + 0, 1, 0, 0, 1, 2, 0, 1, 9, 6, 5, 7, 3, 1, 0, 2, + 4, 8, 0, 1, 0, 1, 3, 0, 1, 2, 0, 1, 1, 0, 1, 0, + 0, 1, 0, 8, 9, 7, 2, 1, 3, 6, 0, 4, 0, 1, 0, 1, 4, 5, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 6, 7, 6, 7, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, @@ -1839,41 +1839,41 @@ DECODE_BUCKET_LIST := [5553]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 363, 365, - 364, 366, 367, 368, 369, 371, 370, 374, 372, 382, 380, 377, 381, 375, 379, 373, - 376, 378, 384, 383, 385, 386, 388, 394, 392, 389, 387, 391, 393, 390, 395, 632, - 396, 633, 397, 398, 399, 634, 400, 635, 636, 401, 402, 637, 403, 638, 639, 404, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 365, 361, 363, 362, + 364, 366, 367, 368, 369, 370, 371, 377, 374, 378, 380, 376, 381, 379, 375, 373, + 382, 372, 384, 383, 385, 386, 391, 392, 393, 387, 394, 388, 390, 389, 395, 632, + 633, 396, 397, 398, 634, 399, 635, 400, 636, 401, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 410, 411, 412, 413, 414, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, + 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, 430, 429, 431, 432, 433, 434, 435, 436, 632, 395, 396, 633, 397, 398, 399, 634, 635, 400, 401, - 636, 402, 637, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, - 409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 449, 450, - 451, 452, 454, 453, 455, 456, 458, 457, 459, 460, 461, 462, 463, 464, 465, 466, - 467, 468, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 637, 402, - 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, 409, 469, 395, - 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, 637, 402, 403, 638, 639, - 404, 405, 640, 406, 641, 642, 407, 408, 643, 644, 409, 470, 471, 472, 469, 358, + 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 642, 407, 408, 643, 644, + 409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 448, 447, 449, 450, + 451, 452, 453, 454, 455, 456, 458, 457, 459, 460, 461, 462, 464, 463, 465, 466, + 467, 468, 632, 395, 396, 633, 397, 398, 399, 634, 400, 635, 636, 401, 402, 637, + 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, 469, 395, + 632, 396, 633, 397, 398, 634, 399, 400, 635, 636, 401, 637, 402, 403, 638, 639, + 404, 405, 640, 641, 406, 642, 407, 408, 643, 644, 409, 470, 471, 472, 469, 358, 359, 360, 365, 364, 363, 362, 361, 366, 367, 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, 375, 383, 384, 385, 386, 394, 393, 392, 391, - 389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, + 389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, 409, - 473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, - 426, 427, 428, 429, 430, 431, 432, 433, 434, 435, 436, 395, 632, 396, 633, 397, - 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 641, + 473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 424, 423, 426, + 425, 427, 428, 430, 429, 432, 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, + 398, 634, 399, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, 409, 474, 473, 438, 439, 440, 441, 442, 443, 444, - 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 456, 455, 458, 457, 459, 460, - 461, 462, 463, 464, 465, 466, 467, 468, 395, 632, 396, 633, 397, 398, 634, 399, - 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, - 408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 636, + 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 456, 455, 457, 458, 459, 460, + 462, 461, 463, 464, 465, 466, 467, 468, 395, 632, 396, 633, 397, 398, 634, 399, + 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, + 408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 641, 406, 407, 642, 408, 643, 644, - 409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 484, 483, 485, 486, 487, + 409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 577, 576, 578, 579, 580, 581, 582, 583, - 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, + 584, 585, 586, 587, 588, 589, 591, 590, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 616, 477, 478, 479, 480, 481, 482, 484, 483, 485, 486, 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, @@ -1885,21 +1885,21 @@ DECODE_BUCKET_LIST := [5553]u16{ 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 619, 620, 621, 622, 365, 364, 363, 361, 362, 623, 624, 625, 626, 370, 371, 382, 380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 627, 628, 629, 394, 393, 390, - 391, 392, 389, 388, 387, 630, 631, 632, 395, 396, 633, 397, 398, 399, 634, 400, - 635, 401, 636, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, + 391, 392, 389, 388, 387, 630, 631, 632, 395, 633, 396, 397, 398, 399, 634, 400, + 635, 401, 636, 637, 402, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, - 658, 659, 660, 661, 662, 663, 664, 665, 630, 631, 632, 395, 396, 633, 397, 398, + 658, 659, 661, 660, 662, 663, 664, 665, 630, 631, 395, 632, 633, 396, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, - 675, 676, 677, 678, 679, 680, 682, 681, 684, 683, 685, 686, 687, 688, 689, 690, - 691, 630, 631, 395, 632, 633, 396, 397, 398, 399, 634, 635, 400, 636, 401, 402, + 675, 676, 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, + 691, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 692, - 696, 694, 695, 693, 697, 700, 698, 699, 701, 702, 703, 704, 705, 706, 707, 708, + 696, 694, 695, 693, 697, 700, 699, 698, 701, 702, 703, 704, 705, 706, 707, 708, 716, 709, 714, 711, 713, 710, 712, 715, 717, 719, 722, 718, 720, 721, 724, 723, - 726, 725, 727, 728, 729, 733, 732, 734, 730, 735, 731, 738, 736, 737, 739, 744, + 726, 725, 729, 727, 728, 733, 735, 730, 734, 732, 731, 738, 736, 737, 739, 744, 741, 743, 742, 740, 748, 746, 745, 747, 749, 751, 750, 756, 755, 757, 753, 754, 752, 759, 763, 758, 761, 760, 762, 765, 764, 766, 767, 768, 770, 769, 771, 777, - 776, 773, 774, 775, 772, 780, 778, 782, 781, 783, 779, 788, 786, 787, 784, 785, + 776, 773, 774, 775, 772, 780, 778, 782, 781, 783, 779, 788, 786, 787, 785, 784, 792, 790, 791, 793, 789, 794, 795, 796, 797, 798, 799, 800, 801, 802, 803, 807, 804, 806, 805, 810, 811, 809, 808, 812, 815, 813, 814, 816, 819, 817, 818, 823, 821, 822, 820, 827, 825, 824, 826, 829, 828, 630, 631, 395, 632, 396, 633, 397, @@ -1909,11 +1909,11 @@ DECODE_BUCKET_LIST := [5553]u16{ 377, 381, 627, 628, 629, 394, 392, 393, 391, 390, 387, 388, 389, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 831, 646, 647, 648, 649, - 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, + 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 663, 662, 664, 665, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 832, 831, - 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 680, 681, 682, - 684, 683, 685, 686, 687, 688, 689, 690, 691, 630, 631, 395, 632, 396, 633, 397, + 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 679, 678, 680, 681, 682, + 683, 685, 684, 687, 686, 688, 689, 690, 691, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 833, 695, 696, 693, 694, 700, 698, 697, 699, 701, 702, 703, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715, @@ -2026,9 +2026,9 @@ DECODE_BUCKET_LIST := [5553]u16{ 1212, 1213, 1216, 1230, 1231, 1230, 1229, 1227, 1223, 1229, 1227, 1231, 1230, 1231, 1209, 1230, 1231, 1230, 1231, 1230, 1244, 1243, 1236, 1244, 1243, 1250, 1250, 1232, 1233, 1234, 1235, 1241, 1240, 1249, 1232, 1233, 1234, 1235, 1240, 1241, 1249, 1242, 1242, 1245, 1237, 1245, 1239, 1247, - 1247, 1248, 1248, 1238, 1246, 1246, 1261, 1268, 1269, 1261, 1265, 1267, 1264, 1266, 1261, 1268, - 1269, 1251, 1252, 1253, 1254, 1261, 1265, 1267, 1264, 1266, 1268, 1269, 1265, 1267, 1264, 1266, - 1268, 1269, 1265, 1267, 1264, 1266, 1251, 1252, 1253, 1254, 1258, 1259, 1260, 1263, 1255, 1256, + 1247, 1248, 1248, 1238, 1246, 1246, 1261, 1269, 1268, 1261, 1265, 1267, 1264, 1266, 1261, 1269, + 1268, 1251, 1252, 1253, 1254, 1261, 1265, 1267, 1264, 1266, 1269, 1268, 1265, 1267, 1264, 1266, + 1269, 1268, 1265, 1267, 1264, 1266, 1251, 1252, 1253, 1254, 1258, 1259, 1260, 1263, 1255, 1256, 1257, 1262, 1258, 1259, 1260, 1263, 1255, 1256, 1257, 1262, 1288, 1292, 1293, 1305, 1306, 1308, 1309, 1310, 1321, 1322, 1325, 1328, 1329, 1332, 1333, 1334, 1335, 1336, 1337, 1346, 1347, 1348, 1349, 1372, 1288, 1292, 1293, 1305, 1307, 1308, 1309, 1310, 1322, 1325, 1328, 1329, 1332, 1333, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index b6b8063c3..71b9197e5 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -929,6 +929,12 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true} }, { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, // .VDIV { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -946,6 +952,12 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, // .VMLS { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -958,6 +970,12 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, // .VNMUL { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -975,6 +993,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, // .VFMS { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, @@ -982,6 +1002,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, // .VFNMA { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {} }, @@ -1239,6 +1261,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, // .VMLAL { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {} }, @@ -1246,6 +1272,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, // .VMLSL { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {} }, @@ -1253,45 +1283,61 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, // .VQDMULL { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, // .VQDMLAL { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, // .VQDMLSL { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, // .VQDMULH { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {} }, { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {} }, { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, // .VQRDMULH { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {} }, { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {} }, { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {} }, { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {} }, - // .VQDMULH_LANE - { .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, - // .VQRDMULH_LANE - { .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, // .VQRDMLAH { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {} }, { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {} }, // .VQRDMLSH { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {} }, { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {} }, // .VABA { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {} }, { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {} }, @@ -1794,15 +1840,13 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VSDOT { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {} }, { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, // .VUDOT { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {} }, { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {} }, - // .VSDOT_LANE - { .VSDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VSDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, - // .VUDOT_LANE - { .VUDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, // .VCVT_BF16 { .VCVT_BF16, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, // .VDOT_BF16 @@ -1821,12 +1865,11 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VCMLA { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, // .VCADD { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, - // .VCMLA_LANE - { .VCMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, - { .VCMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, // .VSMMLA { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {} }, // .VUMMLA @@ -1835,75 +1878,12 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {} }, // .VSUDOT { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, // .VUSDOT { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {} }, - // .VSUDOT_LANE - { .VSUDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, - // .VUSDOT_LANE - { .VUSDOT_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, - { .VUSDOT_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, - // .VMUL_LANE - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, - // .VMLA_LANE - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, - // .VMLS_LANE - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, - // .VMULL_LANE - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, - // .VMLAL_LANE - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, - // .VMLSL_LANE - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, - // .VQDMULL_LANE - { .VQDMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, - // .VQDMLAL_LANE - { .VQDMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, - // .VQDMLSL_LANE - { .VQDMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, - // .VFMA_LANE - { .VFMA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - // .VFMS_LANE - { .VFMS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - // .VQRDMLAH_LANE - { .VQRDMLAH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {} }, - // .VQRDMLSH_LANE - { .VQRDMLSH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, // .VQABS { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true} }, // .VQNEG @@ -2577,199 +2557,179 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .CRC32CW = { 611, 1}, .VADD = { 612, 18}, .VSUB = { 630, 18}, - .VMUL = { 648, 18}, - .VDIV = { 666, 3}, - .VMLA = { 669, 12}, - .VMLS = { 681, 11}, - .VNMUL = { 692, 2}, - .VNMLA = { 694, 2}, - .VNMLS = { 696, 2}, - .VFMA = { 698, 7}, - .VFMS = { 705, 6}, - .VFNMA = { 711, 3}, - .VFNMS = { 714, 3}, - .VABS = { 717, 12}, - .VNEG = { 729, 12}, - .VSQRT = { 741, 3}, - .VCMP = { 744, 8}, - .VCMPE = { 752, 4}, - .VCVT = { 756, 10}, - .VCVTB = { 766, 2}, - .VCVTT = { 768, 2}, - .VCVTA = { 770, 2}, - .VCVTN = { 772, 2}, - .VCVTP = { 774, 2}, - .VCVTM = { 776, 2}, - .VCVTR = { 778, 4}, - .VMOV = { 782, 28}, - .VMRS = { 810, 1}, - .VMSR = { 811, 1}, - .VLDR = { 812, 2}, - .VSTR = { 814, 2}, - .VLDM = { 816, 2}, - .VSTM = { 818, 2}, - .VPUSH = { 820, 2}, - .VPOP = { 822, 2}, - .VSEL = { 824, 2}, - .VMAXNM = { 826, 2}, - .VMINNM = { 828, 2}, - .VRINTA = { 830, 3}, - .VRINTN = { 833, 3}, - .VRINTP = { 836, 3}, - .VRINTM = { 839, 3}, - .VRINTR = { 842, 2}, - .VRINTZ = { 844, 3}, - .VRINTX = { 847, 3}, - .VADDL = { 850, 6}, - .VADDW = { 856, 6}, - .VSUBL = { 862, 6}, - .VSUBW = { 868, 6}, - .VHADD = { 874, 9}, - .VHSUB = { 883, 9}, - .VRHADD = { 892, 3}, - .VQADD = { 895, 11}, - .VQSUB = { 906, 11}, - .VMULL = { 917, 7}, - .VMLAL = { 924, 6}, - .VMLSL = { 930, 6}, - .VQDMULL = { 936, 2}, - .VQDMLAL = { 938, 2}, - .VQDMLSL = { 940, 2}, - .VQDMULH = { 942, 4}, - .VQRDMULH = { 946, 4}, - .VQDMULH_LANE = { 950, 4}, - .VQRDMULH_LANE = { 954, 4}, - .VQRDMLAH = { 958, 4}, - .VQRDMLSH = { 962, 4}, - .VABA = { 966, 8}, - .VABAL = { 974, 6}, - .VABD = { 980, 10}, - .VABDL = { 990, 6}, - .VAND = { 996, 3}, - .VBIC = { 999, 3}, - .VORR = { 1002, 3}, - .VORN = { 1005, 3}, - .VEOR = { 1008, 3}, - .VBSL = { 1011, 2}, - .VBIT = { 1013, 2}, - .VBIF = { 1015, 2}, - .VMVN = { 1017, 13}, - .VMOVN = { 1030, 3}, - .VQMOVN = { 1033, 6}, - .VQMOVUN = { 1039, 3}, - .VMOVL = { 1042, 6}, - .VTST = { 1048, 6}, - .VCEQ = { 1054, 10}, - .VCGE = { 1064, 12}, - .VCGT = { 1076, 12}, - .VCLE = { 1088, 14}, - .VCLT = { 1102, 14}, - .VACGE = { 1116, 2}, - .VACGT = { 1118, 2}, - .VACLE = { 1120, 2}, - .VACLT = { 1122, 2}, - .VMAX = { 1124, 13}, - .VMIN = { 1137, 13}, - .VPMAX = { 1150, 5}, - .VPMIN = { 1155, 5}, - .VPADD = { 1160, 4}, - .VPADDL = { 1164, 6}, - .VPADAL = { 1170, 4}, - .VRECPE = { 1174, 4}, - .VRECPS = { 1178, 2}, - .VRSQRTE = { 1180, 4}, - .VRSQRTS = { 1184, 2}, - .VSHL = { 1186, 9}, - .VSHR = { 1195, 5}, - .VSRA = { 1200, 5}, - .VRSHL = { 1205, 5}, - .VRSHR = { 1210, 5}, - .VRSRA = { 1215, 2}, - .VSLI = { 1217, 2}, - .VSRI = { 1219, 2}, - .VQSHL = { 1221, 7}, - .VQSHRN = { 1228, 2}, - .VQSHRUN = { 1230, 1}, - .VQRSHL = { 1231, 16}, - .VQRSHRN = { 1247, 2}, - .VQRSHRUN = { 1249, 1}, - .VSHRN = { 1250, 1}, - .VRSHRN = { 1251, 1}, - .VSHLL = { 1252, 5}, - .VCLS = { 1257, 6}, - .VCLZ = { 1263, 6}, - .VCNT = { 1269, 2}, - .VPADD_F = { 1271, 2}, - .VRECPE_F = { 1273, 2}, - .VRSQRTE_F = { 1275, 2}, - .VREV16 = { 1277, 2}, - .VREV32 = { 1279, 4}, - .VREV64 = { 1283, 6}, - .VEXT = { 1289, 2}, - .VTBL = { 1291, 4}, - .VTBX = { 1295, 4}, - .VTRN = { 1299, 6}, - .VUZP = { 1305, 5}, - .VZIP = { 1310, 5}, - .VDUP = { 1315, 5}, - .VSWP = { 1320, 2}, - .VMOV_LANE = { 1322, 3}, - .VLD1 = { 1325, 8}, - .VLD2 = { 1333, 3}, - .VLD3 = { 1336, 2}, - .VLD4 = { 1338, 2}, - .VST1 = { 1340, 7}, - .VST2 = { 1347, 3}, - .VST3 = { 1350, 2}, - .VST4 = { 1352, 2}, - .AESE = { 1354, 1}, - .AESD = { 1355, 1}, - .AESMC = { 1356, 1}, - .AESIMC = { 1357, 1}, - .SHA1H = { 1358, 1}, - .SHA1SU0 = { 1359, 1}, - .SHA1SU1 = { 1360, 1}, - .SHA1C = { 1361, 1}, - .SHA1M = { 1362, 1}, - .SHA1P = { 1363, 1}, - .SHA256H = { 1364, 1}, - .SHA256H2 = { 1365, 1}, - .SHA256SU0 = { 1366, 1}, - .SHA256SU1 = { 1367, 1}, - .VJCVT = { 1368, 1}, - .VSDOT = { 1369, 2}, - .VUDOT = { 1371, 2}, - .VSDOT_LANE = { 1373, 2}, - .VUDOT_LANE = { 1375, 2}, - .VCVT_BF16 = { 1377, 1}, - .VDOT_BF16 = { 1378, 2}, - .VFMA_BF16 = { 1380, 1}, - .VMMLA_BF16 = { 1381, 1}, - .VFMAL = { 1382, 2}, - .VFMSL = { 1384, 2}, - .VCMLA = { 1386, 2}, - .VCADD = { 1388, 2}, - .VCMLA_LANE = { 1390, 2}, - .VSMMLA = { 1392, 1}, - .VUMMLA = { 1393, 1}, - .VUSMMLA = { 1394, 1}, - .VSUDOT = { 1395, 1}, - .VUSDOT = { 1396, 2}, - .VSUDOT_LANE = { 1398, 1}, - .VUSDOT_LANE = { 1399, 2}, - .VMUL_LANE = { 1401, 6}, - .VMLA_LANE = { 1407, 6}, - .VMLS_LANE = { 1413, 6}, - .VMULL_LANE = { 1419, 4}, - .VMLAL_LANE = { 1423, 4}, - .VMLSL_LANE = { 1427, 4}, - .VQDMULL_LANE = { 1431, 2}, - .VQDMLAL_LANE = { 1433, 2}, - .VQDMLSL_LANE = { 1435, 2}, - .VFMA_LANE = { 1437, 2}, - .VFMS_LANE = { 1439, 2}, - .VQRDMLAH_LANE = { 1441, 4}, - .VQRDMLSH_LANE = { 1445, 4}, + .VMUL = { 648, 24}, + .VDIV = { 672, 3}, + .VMLA = { 675, 18}, + .VMLS = { 693, 17}, + .VNMUL = { 710, 2}, + .VNMLA = { 712, 2}, + .VNMLS = { 714, 2}, + .VFMA = { 716, 9}, + .VFMS = { 725, 8}, + .VFNMA = { 733, 3}, + .VFNMS = { 736, 3}, + .VABS = { 739, 12}, + .VNEG = { 751, 12}, + .VSQRT = { 763, 3}, + .VCMP = { 766, 8}, + .VCMPE = { 774, 4}, + .VCVT = { 778, 10}, + .VCVTB = { 788, 2}, + .VCVTT = { 790, 2}, + .VCVTA = { 792, 2}, + .VCVTN = { 794, 2}, + .VCVTP = { 796, 2}, + .VCVTM = { 798, 2}, + .VCVTR = { 800, 4}, + .VMOV = { 804, 28}, + .VMRS = { 832, 1}, + .VMSR = { 833, 1}, + .VLDR = { 834, 2}, + .VSTR = { 836, 2}, + .VLDM = { 838, 2}, + .VSTM = { 840, 2}, + .VPUSH = { 842, 2}, + .VPOP = { 844, 2}, + .VSEL = { 846, 2}, + .VMAXNM = { 848, 2}, + .VMINNM = { 850, 2}, + .VRINTA = { 852, 3}, + .VRINTN = { 855, 3}, + .VRINTP = { 858, 3}, + .VRINTM = { 861, 3}, + .VRINTR = { 864, 2}, + .VRINTZ = { 866, 3}, + .VRINTX = { 869, 3}, + .VADDL = { 872, 6}, + .VADDW = { 878, 6}, + .VSUBL = { 884, 6}, + .VSUBW = { 890, 6}, + .VHADD = { 896, 9}, + .VHSUB = { 905, 9}, + .VRHADD = { 914, 3}, + .VQADD = { 917, 11}, + .VQSUB = { 928, 11}, + .VMULL = { 939, 11}, + .VMLAL = { 950, 10}, + .VMLSL = { 960, 10}, + .VQDMULL = { 970, 4}, + .VQDMLAL = { 974, 4}, + .VQDMLSL = { 978, 4}, + .VQDMULH = { 982, 8}, + .VQRDMULH = { 990, 8}, + .VQRDMLAH = { 998, 8}, + .VQRDMLSH = { 1006, 8}, + .VABA = { 1014, 8}, + .VABAL = { 1022, 6}, + .VABD = { 1028, 10}, + .VABDL = { 1038, 6}, + .VAND = { 1044, 3}, + .VBIC = { 1047, 3}, + .VORR = { 1050, 3}, + .VORN = { 1053, 3}, + .VEOR = { 1056, 3}, + .VBSL = { 1059, 2}, + .VBIT = { 1061, 2}, + .VBIF = { 1063, 2}, + .VMVN = { 1065, 13}, + .VMOVN = { 1078, 3}, + .VQMOVN = { 1081, 6}, + .VQMOVUN = { 1087, 3}, + .VMOVL = { 1090, 6}, + .VTST = { 1096, 6}, + .VCEQ = { 1102, 10}, + .VCGE = { 1112, 12}, + .VCGT = { 1124, 12}, + .VCLE = { 1136, 14}, + .VCLT = { 1150, 14}, + .VACGE = { 1164, 2}, + .VACGT = { 1166, 2}, + .VACLE = { 1168, 2}, + .VACLT = { 1170, 2}, + .VMAX = { 1172, 13}, + .VMIN = { 1185, 13}, + .VPMAX = { 1198, 5}, + .VPMIN = { 1203, 5}, + .VPADD = { 1208, 4}, + .VPADDL = { 1212, 6}, + .VPADAL = { 1218, 4}, + .VRECPE = { 1222, 4}, + .VRECPS = { 1226, 2}, + .VRSQRTE = { 1228, 4}, + .VRSQRTS = { 1232, 2}, + .VSHL = { 1234, 9}, + .VSHR = { 1243, 5}, + .VSRA = { 1248, 5}, + .VRSHL = { 1253, 5}, + .VRSHR = { 1258, 5}, + .VRSRA = { 1263, 2}, + .VSLI = { 1265, 2}, + .VSRI = { 1267, 2}, + .VQSHL = { 1269, 7}, + .VQSHRN = { 1276, 2}, + .VQSHRUN = { 1278, 1}, + .VQRSHL = { 1279, 16}, + .VQRSHRN = { 1295, 2}, + .VQRSHRUN = { 1297, 1}, + .VSHRN = { 1298, 1}, + .VRSHRN = { 1299, 1}, + .VSHLL = { 1300, 5}, + .VCLS = { 1305, 6}, + .VCLZ = { 1311, 6}, + .VCNT = { 1317, 2}, + .VPADD_F = { 1319, 2}, + .VRECPE_F = { 1321, 2}, + .VRSQRTE_F = { 1323, 2}, + .VREV16 = { 1325, 2}, + .VREV32 = { 1327, 4}, + .VREV64 = { 1331, 6}, + .VEXT = { 1337, 2}, + .VTBL = { 1339, 4}, + .VTBX = { 1343, 4}, + .VTRN = { 1347, 6}, + .VUZP = { 1353, 5}, + .VZIP = { 1358, 5}, + .VDUP = { 1363, 5}, + .VSWP = { 1368, 2}, + .VMOV_LANE = { 1370, 3}, + .VLD1 = { 1373, 8}, + .VLD2 = { 1381, 3}, + .VLD3 = { 1384, 2}, + .VLD4 = { 1386, 2}, + .VST1 = { 1388, 7}, + .VST2 = { 1395, 3}, + .VST3 = { 1398, 2}, + .VST4 = { 1400, 2}, + .AESE = { 1402, 1}, + .AESD = { 1403, 1}, + .AESMC = { 1404, 1}, + .AESIMC = { 1405, 1}, + .SHA1H = { 1406, 1}, + .SHA1SU0 = { 1407, 1}, + .SHA1SU1 = { 1408, 1}, + .SHA1C = { 1409, 1}, + .SHA1M = { 1410, 1}, + .SHA1P = { 1411, 1}, + .SHA256H = { 1412, 1}, + .SHA256H2 = { 1413, 1}, + .SHA256SU0 = { 1414, 1}, + .SHA256SU1 = { 1415, 1}, + .VJCVT = { 1416, 1}, + .VSDOT = { 1417, 4}, + .VUDOT = { 1421, 4}, + .VCVT_BF16 = { 1425, 1}, + .VDOT_BF16 = { 1426, 2}, + .VFMA_BF16 = { 1428, 1}, + .VMMLA_BF16 = { 1429, 1}, + .VFMAL = { 1430, 2}, + .VFMSL = { 1432, 2}, + .VCMLA = { 1434, 4}, + .VCADD = { 1438, 2}, + .VSMMLA = { 1440, 1}, + .VUMMLA = { 1441, 1}, + .VUSMMLA = { 1442, 1}, + .VSUDOT = { 1443, 2}, + .VUSDOT = { 1445, 4}, .VQABS = { 1449, 1}, .VQNEG = { 1450, 1}, .VMOVX = { 1451, 1}, diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 024825fd42d1c4a1422b6f5acb353015e09ffc75..8363b7f377027192626f4d2ed963e77f83b1cb74 100644 GIT binary patch delta 505 zcmX|+OK(g87>4tFb7sz%(_@C2%A_V}v=&xvgv3GwiG@h*CN_RRi@LUYzZmLLI`r#> z#GZ#=r6*O>=CK_qxFvmE~2@;&-2rV3?l`5&0Q=F!a8c9+sXV8#$ zvzca)VTN>vw^%p&B6`ugsOT0q8Ra&2xXV56^MElPGR`9&Gr=TJdBQWEGsO!B+e*8) zK+A(6UTV_Jjn>Io>ZKi}K^molPMV}yy3j4YGQD8tXiH$3e)8olPSM8z{my{2JAn)% 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zXm~#He!~li4;fxeOo?Khml7Ya$jgcM8D2@;YIqf~YNx!3n#FHwe3eM>rNpY8f^)DGNRW}7oV%1K;_YhO|m4ZEDHJ*YWChi?Zarwn-bDoIHFxxlb=ZLFp+1#0y_gEI% z#9+9F*f%_gSQ?H5!q7XRACvBu#Q(J)IkVOyfe^ z@Z-de;U|cN;obHpW)I=tFXPW(v+y6;206%dx!FOT0Bc#ry(^T*7ZmwDSJ} DcqDYM diff --git a/core/rexcode/isa/arm32/tables/arm32.form_idx.bin b/core/rexcode/isa/arm32/tables/arm32.form_idx.bin index f511e5628bae011195e69a8259821fe8f5f42643..d7d7b273f9cc9081e808b8d180781314206f17c6 100644 GIT binary patch delta 925 zcmYjPJ5B>J5FM|*Yj46P5LiA*jgV+45IvlL0#T(-g%IKdDWIi5riYdeiGpiz1H=)y z0OGwFELh9-?0nw5XZvaTG<~^sGcT=paS||{@av?;fImOFnM?QAeSUZQU63J?DkOMm za;)aQM#`ePI@y#R*^*w1xeR3>BUzJmSgWu*S&@ls$XJ@+oFEZMY+S>aa_P8d^wP)UBU*sJwEjb+kDYe;1PI3; z!tvuy#{6T{=fmdcv}iCzRK`gfHj7qLF_l`YHhqPJ=&gkO*6iUn;_GK~=DJd#dtRn~ zjU-H!9o;N{#s0FEsRCI(8_Uu3V6x~zG=HW(f2VYA$H28! q@)4O<%_maot&_23l+#w;CLgFhO5P{@dEVaLKTPs*+9W%>426|+OS;}(c6k5ya}dnvVc7_jSa*8+%Rf% zSg??XD?R0Vv?zE_4I8Ab;#xJ08|^=fKegzvv2A+5=n#gj&y7QO?G)Ee6!E%C$RHSX z%P}n&JoX%=XQwg9B342+9c9QiSlk|=@io51=lB#~AR6o!Ur(Ap#G5o;;$vLny=g;a zB^#ssnq*;jz)^-18#X8IfcP+dp zbI;rl%hcN^03Gi0{teGh*#M(*x#C|QD}LAjK`kYA0mbZjHP9E+lS1GGn0O& zPgpOWH922&C0@d_HD+k`W}o_N!&y$g<1I;iOC8`n^p)xHUgrP8olSg7jO_6M&MH0a z3_+XQkcGOB)H2*A0Jj2AJ5##nSOO0HW(lYttu7^r92NTB=|i_ATvc#aGx-@uN~Hwz zGwxI3{`HQOtGO_2K@qRdoKFOIQF@kV0lDNE=frX!(zBT-a?J_lthx@CZJV`{!?g7g z?;s8M;IFsuA>RPpf!w{^w0x_$DLhig^Nh{(_j&ad2fqz@!&8q(xa#|PU1EJ)3w>kX z?UQz~Q{9$7$(YioVB{iyX{Y5J2|`+Ic%ACVql`S*|=b8_aKcQS!y{uDF2 S{J&Ivi7;23J^#I$H^xt9SP&`z diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index 72d1536f2..904e2f5fa 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -382,7 +382,7 @@ run_smoke :: proc() { // ---- Extensions: Dot product / FCMA / FHM / BF16 ---- check("VSDOT D", .VSDOT, 0, 0xFC200D00, 0xFFB00F10) check("VUDOT Q", .VUDOT, 1, 0xFC200D50, 0xFFB00F50) - check("VSDOT_LANE D", .VSDOT_LANE, 0, 0xFE200D00, 0xFFB00F10) + check("VSDOT lane D", .VSDOT, 2, 0xFE200D00, 0xFFB00F10) check("VCMLA D", .VCMLA, 0, 0xFC200800, 0xFC800F10) check("VCADD Q", .VCADD, 1, 0xFC800840, 0xFE800F50) check("VFMAL D", .VFMAL, 0, 0xFC200810, 0xFFB00F10) @@ -500,24 +500,24 @@ run_smoke :: proc() { check("VUMMLA", .VUMMLA, 0, 0xFC200C50, 0xFFB00F50) check("VUSMMLA", .VUSMMLA, 0, 0xFCA00C40, 0xFFB00F50) check("VUSDOT D", .VUSDOT, 0, 0xFCA00D00, 0xFFB00F10) - check("VSUDOT_LANE", .VSUDOT_LANE, 0, 0xFE800D50, 0xFFB00F50) + check("VSUDOT lane", .VSUDOT, 1, 0xFE800D50, 0xFFB00F50) // ---- Lane-indexed NEON ---- - check("VMUL_LANE D .S16", .VMUL_LANE, 0, 0xF2900840, 0xFFB00F50) - check("VMUL_LANE Q .S32", .VMUL_LANE, 3, 0xF3A00840, 0xFFB00F50) - check("VMLA_LANE D", .VMLA_LANE, 0, 0xF2900040, 0xFFB00F50) - check("VMLS_LANE Q", .VMLS_LANE, 2, 0xF3900440, 0xFFB00F50) - check("VMULL_LANE .S16", .VMULL_LANE, 0, 0xF2900A40, 0xFFB00F50) - check("VMLAL_LANE .S32", .VMLAL_LANE, 1, 0xF2A00240, 0xFFB00F50) - check("VMLSL_LANE .S16", .VMLSL_LANE, 0, 0xF2900640, 0xFFB00F50) - check("VQDMULL_LANE .S16",.VQDMULL_LANE, 0, 0xF2900B40, 0xFFB00F50) - check("VQDMLAL_LANE .S32",.VQDMLAL_LANE, 1, 0xF2A00340, 0xFFB00F50) - check("VQDMLSL_LANE", .VQDMLSL_LANE, 0, 0xF2900740, 0xFFB00F50) - check("VFMA_LANE D", .VFMA_LANE, 0, 0xF2A000C0, 0xFFB00F50) - check("VFMS_LANE Q", .VFMS_LANE, 1, 0xF3A004C0, 0xFFB00F50) - check("VQRDMLAH_LANE", .VQRDMLAH_LANE, 0, 0xF2900E40, 0xFFB00F50) - check("VQRDMLSH_LANE", .VQRDMLSH_LANE, 0, 0xF2900F40, 0xFFB00F50) - check("VCMLA_LANE D", .VCMLA_LANE, 0, 0xFE000800, 0xFFB00F10) + check("VMUL lane D .S16", .VMUL, 18, 0xF2900840, 0xFFB00F50) + check("VMUL lane Q .S32", .VMUL, 21, 0xF3A00840, 0xFFB00F50) + check("VMLA lane D", .VMLA, 12, 0xF2900040, 0xFFB00F50) + check("VMLS lane Q", .VMLS, 13, 0xF3900440, 0xFFB00F50) + check("VMULL lane .S16", .VMULL, 7, 0xF2900A40, 0xFFB00F50) + check("VMLAL lane .S32", .VMLAL, 7, 0xF2A00240, 0xFFB00F50) + check("VMLSL lane .S16", .VMLSL, 6, 0xF2900640, 0xFFB00F50) + check("VQDMULL lane .S16",.VQDMULL, 2, 0xF2900B40, 0xFFB00F50) + check("VQDMLAL lane .S32",.VQDMLAL, 3, 0xF2A00340, 0xFFB00F50) + check("VQDMLSL lane", .VQDMLSL, 2, 0xF2900740, 0xFFB00F50) + check("VFMA lane D", .VFMA, 7, 0xF2A000C0, 0xFFB00F50) + check("VFMS lane Q", .VFMS, 7, 0xF3A004C0, 0xFFB00F50) + check("VQRDMLAH lane", .VQRDMLAH, 4, 0xF2900E40, 0xFFB00F50) + check("VQRDMLSH lane", .VQRDMLSH, 4, 0xF2900F40, 0xFFB00F50) + check("VCMLA lane D", .VCMLA, 2, 0xFE000800, 0xFFB00F10) // ---- MVE polish ---- check("VQABS", .VQABS, 0, 0xFFB00740, 0xFFB30FD1) diff --git a/core/rexcode/isa/mips/encoder.odin b/core/rexcode/isa/mips/encoder.odin index 80492d030..154194baf 100644 --- a/core/rexcode/isa/mips/encoder.odin +++ b/core/rexcode/isa/mips/encoder.odin @@ -86,6 +86,7 @@ encode :: proc( endianness: Endianness = .BIG, resolve: bool = true, base_address: u64 = 0, + features: Feature_Set = FEATURES_ALL, ) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { @@ -99,7 +100,7 @@ encode :: proc( // ---- PASS 1 ------------------------------------------------------------ for i in 0.. (word: u32, ok: bool) { if inst.mnemonic == .INVALID { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) @@ -164,8 +166,12 @@ encode_one_inline :: #force_inline proc( } // Find a matching form. Most mnemonics have exactly one. + // Mirror of the decoder's filter: several MIPS variants reuse a mnemonic + // for different encodings (pre-R6 MUL vs R6 MUL, MADD vs the PS2 MMI + // MADD), and only the target's feature set tells them apart. form: ^Encoding for &f in forms { + if f.feature not_in features { continue } if encoding_matches_inline(inst, &f) { form = &f break diff --git a/core/rexcode/isa/mips/mnemonic_builders.odin b/core/rexcode/isa/mips/mnemonic_builders.odin index dd610e283..530a901f9 100644 --- a/core/rexcode/isa/mips/mnemonic_builders.odin +++ b/core/rexcode/isa/mips/mnemonic_builders.odin @@ -41,9 +41,13 @@ emit_mult_r_r :: #force_inline proc(instructions: ^[dynamic]Instruc inst_multu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MULTU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } emit_multu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_multu_r_r(dst, src)) } inst_div_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DIV, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_div_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DIV, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_div_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_div_r_r(dst, src)) } +emit_div_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_div_r_r_r(dst, src, src2)) } inst_divu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DIVU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_divu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DIVU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_divu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_divu_r_r(dst, src)) } +emit_divu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_divu_r_r_r(dst, src, src2)) } inst_mfhi_r :: #force_inline proc "contextless" (dst: GPR) -> Instruction { return Instruction{mnemonic = .MFHI, operand_count = 1, length = 4, ops = {op_gpr(dst), {}, {}, {}}} } emit_mfhi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR) { append(instructions, inst_mfhi_r(dst)) } inst_mflo_r :: #force_inline proc "contextless" (dst: GPR) -> Instruction { return Instruction{mnemonic = .MFLO, operand_count = 1, length = 4, ops = {op_gpr(dst), {}, {}, {}}} } @@ -209,9 +213,13 @@ emit_dmult_r_r :: #force_inline proc(instructions: ^[dynamic]Instruc inst_dmultu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DMULTU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } emit_dmultu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_dmultu_r_r(dst, src)) } inst_ddiv_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DDIV, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_ddiv_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DDIV, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_ddiv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_ddiv_r_r(dst, src)) } +emit_ddiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_ddiv_r_r_r(dst, src, src2)) } inst_ddivu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DDIVU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_ddivu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DDIVU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_ddivu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_ddivu_r_r(dst, src)) } +emit_ddivu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_ddivu_r_r_r(dst, src, src2)) } inst_dsll_r_r_i5 :: #force_inline proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction { return Instruction{mnemonic = .DSLL, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_imm(imm, 1), {}}} } emit_dsll_r_r_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, imm: i64) { append(instructions, inst_dsll_r_r_i5(dst, src, imm)) } inst_dsrl_r_r_i5 :: #force_inline proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction { return Instruction{mnemonic = .DSRL, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_imm(imm, 1), {}}} } @@ -279,13 +287,21 @@ emit_dclo_r_r :: #force_inline proc(instructions: ^[dynamic]Instruc inst_mul_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } inst_madd_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MADD, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_madd_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MADD, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_madd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_madd_r_r(dst, src)) } +emit_madd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_madd_r_r_r(dst, src, src2)) } inst_maddu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MADDU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_maddu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MADDU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_maddu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_maddu_r_r(dst, src)) } +emit_maddu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_maddu_r_r_r(dst, src, src2)) } inst_msub_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MSUB, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_msub_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MSUB, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_msub_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_msub_r_r(dst, src)) } +emit_msub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_msub_r_r_r(dst, src, src2)) } inst_msubu_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MSUBU, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } +inst_msubu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MSUBU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_msubu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_msubu_r_r(dst, src)) } +emit_msubu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_msubu_r_r_r(dst, src, src2)) } inst_sdbbp_i20 :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SDBBP, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } emit_sdbbp_i20 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sdbbp_i20(imm)) } inst_ssnop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SSNOP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } @@ -396,20 +412,16 @@ inst_mod_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: G emit_mod_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_mod_r_r_r(dst, src, src2)) } inst_modu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MODU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_modu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_modu_r_r_r(dst, src, src2)) } -inst_dmul_r6_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMUL_R6, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_dmul_r6_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmul_r6_r_r_r(dst, src, src2)) } +inst_dmul_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMUL, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } +emit_dmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmul_r_r_r(dst, src, src2)) } inst_dmuh_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMUH, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_dmuh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmuh_r_r_r(dst, src, src2)) } inst_dmulu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMULU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_dmulu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmulu_r_r_r(dst, src, src2)) } inst_dmuhu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMUHU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_dmuhu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmuhu_r_r_r(dst, src, src2)) } -inst_ddiv_r6_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DDIV_R6, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_ddiv_r6_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_ddiv_r6_r_r_r(dst, src, src2)) } inst_dmod_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMOD, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_dmod_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmod_r_r_r(dst, src, src2)) } -inst_ddivu_r6_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DDIVU_R6, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_ddivu_r6_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_ddivu_r6_r_r_r(dst, src, src2)) } inst_dmodu_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .DMODU, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } emit_dmodu_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_dmodu_r_r_r(dst, src, src2)) } inst_aui_r_r_u16 :: #force_inline proc "contextless" (dst: GPR, src: GPR, imm: i64) -> Instruction { return Instruction{mnemonic = .AUI, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_imm(imm, 2), {}}} } @@ -830,14 +842,14 @@ inst_avsz3_none :: #force_inline proc "contextless" () -> Instruction emit_avsz3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_avsz3_none()) } inst_avsz4_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AVSZ4, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } emit_avsz4_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_avsz4_none()) } -inst_op_gte_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .OP_GTE, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } -emit_op_gte_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_op_gte_none()) } +inst_op_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .OP, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } +emit_op_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_op_none()) } inst_gpf_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .GPF, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } emit_gpf_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_gpf_none()) } inst_gpl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .GPL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } emit_gpl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_gpl_none()) } -inst_sqr_gte_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SQR_GTE, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } -emit_sqr_gte_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sqr_gte_none()) } +inst_sqr_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SQR, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } +emit_sqr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sqr_none()) } inst_dcpl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPL, operand_count = 0, length = 4, ops = {{}, {}, {}, {}}} } emit_dcpl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcpl_none()) } inst_lq_r_m :: #force_inline proc "contextless" (dst: GPR, mem: Memory) -> Instruction { return Instruction{mnemonic = .LQ, operand_count = 2, length = 4, ops = {op_gpr(dst), op_mem(mem, 4), {}, {}}} } @@ -864,14 +876,6 @@ inst_div1_r_r :: #force_inline proc "contextless" (dst: GPR, src: G emit_div1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_div1_r_r(dst, src)) } inst_divu1_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .DIVU1, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } emit_divu1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_divu1_r_r(dst, src)) } -inst_madd_ee_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MADD_EE, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_madd_ee_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_madd_ee_r_r_r(dst, src, src2)) } -inst_maddu_ee_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MADDU_EE, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_maddu_ee_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_maddu_ee_r_r_r(dst, src, src2)) } -inst_msub_ee_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MSUB_EE, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_msub_ee_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_msub_ee_r_r_r(dst, src, src2)) } -inst_msubu_ee_r_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR, src2: GPR) -> Instruction { return Instruction{mnemonic = .MSUBU_EE, operand_count = 3, length = 4, ops = {op_gpr(dst), op_gpr(src), op_gpr(src2), {}}} } -emit_msubu_ee_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR, src2: GPR) { append(instructions, inst_msubu_ee_r_r_r(dst, src, src2)) } inst_madd1_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MADD1, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } emit_madd1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR, src: GPR) { append(instructions, inst_madd1_r_r(dst, src)) } inst_maddu1_r_r :: #force_inline proc "contextless" (dst: GPR, src: GPR) -> Instruction { return Instruction{mnemonic = .MADDU1, operand_count = 2, length = 4, ops = {op_gpr(dst), op_gpr(src), {}, {}}} } @@ -2097,10 +2101,10 @@ inst_mult :: inst_mult_r_r emit_mult :: emit_mult_r_r inst_multu :: inst_multu_r_r emit_multu :: emit_multu_r_r -inst_div :: inst_div_r_r -emit_div :: emit_div_r_r -inst_divu :: inst_divu_r_r -emit_divu :: emit_divu_r_r +inst_div :: proc{ inst_div_r_r, inst_div_r_r_r } +emit_div :: proc{ emit_div_r_r, emit_div_r_r_r } +inst_divu :: proc{ inst_divu_r_r, inst_divu_r_r_r } +emit_divu :: proc{ emit_divu_r_r, emit_divu_r_r_r } inst_mfhi :: inst_mfhi_r emit_mfhi :: emit_mfhi_r inst_mflo :: inst_mflo_r @@ -2265,10 +2269,10 @@ inst_dmult :: inst_dmult_r_r emit_dmult :: emit_dmult_r_r inst_dmultu :: inst_dmultu_r_r emit_dmultu :: emit_dmultu_r_r -inst_ddiv :: inst_ddiv_r_r -emit_ddiv :: emit_ddiv_r_r -inst_ddivu :: inst_ddivu_r_r -emit_ddivu :: emit_ddivu_r_r +inst_ddiv :: proc{ inst_ddiv_r_r, inst_ddiv_r_r_r } +emit_ddiv :: proc{ emit_ddiv_r_r, emit_ddiv_r_r_r } +inst_ddivu :: proc{ inst_ddivu_r_r, inst_ddivu_r_r_r } +emit_ddivu :: proc{ emit_ddivu_r_r, emit_ddivu_r_r_r } inst_dsll :: inst_dsll_r_r_i5 emit_dsll :: emit_dsll_r_r_i5 inst_dsrl :: inst_dsrl_r_r_i5 @@ -2335,14 +2339,14 @@ inst_dclo :: inst_dclo_r_r emit_dclo :: emit_dclo_r_r inst_mul :: inst_mul_r_r_r emit_mul :: emit_mul_r_r_r -inst_madd :: inst_madd_r_r -emit_madd :: emit_madd_r_r -inst_maddu :: inst_maddu_r_r -emit_maddu :: emit_maddu_r_r -inst_msub :: inst_msub_r_r -emit_msub :: emit_msub_r_r -inst_msubu :: inst_msubu_r_r -emit_msubu :: emit_msubu_r_r +inst_madd :: proc{ inst_madd_r_r, inst_madd_r_r_r } +emit_madd :: proc{ emit_madd_r_r, emit_madd_r_r_r } +inst_maddu :: proc{ inst_maddu_r_r, inst_maddu_r_r_r } +emit_maddu :: proc{ emit_maddu_r_r, emit_maddu_r_r_r } +inst_msub :: proc{ inst_msub_r_r, inst_msub_r_r_r } +emit_msub :: proc{ emit_msub_r_r, emit_msub_r_r_r } +inst_msubu :: proc{ inst_msubu_r_r, inst_msubu_r_r_r } +emit_msubu :: proc{ emit_msubu_r_r, emit_msubu_r_r_r } inst_sdbbp :: inst_sdbbp_i20 emit_sdbbp :: emit_sdbbp_i20 inst_ssnop :: inst_ssnop_none @@ -2453,20 +2457,16 @@ inst_mod :: inst_mod_r_r_r emit_mod :: emit_mod_r_r_r inst_modu :: inst_modu_r_r_r emit_modu :: emit_modu_r_r_r -inst_dmul_r6 :: inst_dmul_r6_r_r_r -emit_dmul_r6 :: emit_dmul_r6_r_r_r +inst_dmul :: inst_dmul_r_r_r +emit_dmul :: emit_dmul_r_r_r inst_dmuh :: inst_dmuh_r_r_r emit_dmuh :: emit_dmuh_r_r_r inst_dmulu :: inst_dmulu_r_r_r emit_dmulu :: emit_dmulu_r_r_r inst_dmuhu :: inst_dmuhu_r_r_r emit_dmuhu :: emit_dmuhu_r_r_r -inst_ddiv_r6 :: inst_ddiv_r6_r_r_r -emit_ddiv_r6 :: emit_ddiv_r6_r_r_r inst_dmod :: inst_dmod_r_r_r emit_dmod :: emit_dmod_r_r_r -inst_ddivu_r6 :: inst_ddivu_r6_r_r_r -emit_ddivu_r6 :: emit_ddivu_r6_r_r_r inst_dmodu :: inst_dmodu_r_r_r emit_dmodu :: emit_dmodu_r_r_r inst_aui :: inst_aui_r_r_u16 @@ -2887,14 +2887,14 @@ inst_avsz3 :: inst_avsz3_none emit_avsz3 :: emit_avsz3_none inst_avsz4 :: inst_avsz4_none emit_avsz4 :: emit_avsz4_none -inst_op_gte :: inst_op_gte_none -emit_op_gte :: emit_op_gte_none +inst_op :: inst_op_none +emit_op :: emit_op_none inst_gpf :: inst_gpf_none emit_gpf :: emit_gpf_none inst_gpl :: inst_gpl_none emit_gpl :: emit_gpl_none -inst_sqr_gte :: inst_sqr_gte_none -emit_sqr_gte :: emit_sqr_gte_none +inst_sqr :: inst_sqr_none +emit_sqr :: emit_sqr_none inst_dcpl :: inst_dcpl_none emit_dcpl :: emit_dcpl_none inst_lq :: inst_lq_r_m @@ -2921,14 +2921,6 @@ inst_div1 :: inst_div1_r_r emit_div1 :: emit_div1_r_r inst_divu1 :: inst_divu1_r_r emit_divu1 :: emit_divu1_r_r -inst_madd_ee :: inst_madd_ee_r_r_r -emit_madd_ee :: emit_madd_ee_r_r_r -inst_maddu_ee :: inst_maddu_ee_r_r_r -emit_maddu_ee :: emit_maddu_ee_r_r_r -inst_msub_ee :: inst_msub_ee_r_r_r -emit_msub_ee :: emit_msub_ee_r_r_r -inst_msubu_ee :: inst_msubu_ee_r_r_r -emit_msubu_ee :: emit_msubu_ee_r_r_r inst_madd1 :: inst_madd1_r_r emit_madd1 :: emit_madd1_r_r inst_maddu1 :: inst_maddu1_r_r diff --git a/core/rexcode/isa/mips/mnemonics.odin b/core/rexcode/isa/mips/mnemonics.odin index 3a3356587..72e984964 100644 --- a/core/rexcode/isa/mips/mnemonics.odin +++ b/core/rexcode/isa/mips/mnemonics.odin @@ -138,9 +138,9 @@ Mnemonic :: enum u16 { JIC, JIALC, // R6 mul/div (replaces MULT/MULTU/DIV/DIVU; results in single GPR) - MUL_R6, MUH, MULU, MUHU, DIV_R6, MOD, DIVU_R6, MODU, - DMUL_R6, DMUH, DMULU, DMUHU, - DDIV_R6, DMOD, DDIVU_R6, DMODU, + MUH, MULU, MUHU, MOD, MODU, + DMUL, DMUH, DMULU, DMUHU, + DMOD, DMODU, // R6 PC-relative immediates AUI, AUIPC, ALUIPC, DAUI, DAHI, DATI, @@ -263,9 +263,9 @@ Mnemonic :: enum u16 { CDP, CC, NCLIP, AVSZ3, AVSZ4, - OP_GTE, // "OP" (cross product) โ€” disambiguated from MIPS R6 OP + OP, // "OP" (cross product) โ€” disambiguated from MIPS R6 OP GPF, GPL, - SQR_GTE, // "SQR" โ€” disambiguated from generic + SQR, // "SQR" โ€” disambiguated from generic DCPL, // depth-cue per light // ------------------------------------------------------------------------- @@ -281,7 +281,6 @@ Mnemonic :: enum u16 { // Second HI/LO pair (R5900 dual MAC) MFHI1, MFLO1, MTHI1, MTLO1, MULT1, MULTU1, DIV1, DIVU1, - MADD_EE, MADDU_EE, MSUB_EE, MSUBU_EE, MADD1, MADDU1, MSUB1, MSUBU1, // Packed pack/unpack HI:LO diff --git a/core/rexcode/isa/mips/printer.odin b/core/rexcode/isa/mips/printer.odin index 3fb1f2114..e8946a65f 100644 --- a/core/rexcode/isa/mips/printer.odin +++ b/core/rexcode/isa/mips/printer.odin @@ -48,8 +48,8 @@ GPR_NAMES_ABI := [32]string{ // Public string accessors // ============================================================================= -// Canonical mnemonic spelling (lowercase, with `_` mapped to `.`). -// The few enum names that carry a disambiguator suffix get a hand mapping. +// Canonical mnemonic spelling (lowercase; `_` maps to `.`, except in MSA). +// Canonical mnemonic spelling (lowercase; `_` maps to `.`, except in MSA). mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := context.temp_allocator) -> string { sb := strings.builder_make(allocator) write_mnemonic(&sb, m, !lowercase) @@ -314,32 +314,35 @@ wprintln :: proc( @(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { - // Disambiguator-suffix overrides: enum names like DMUL_R6, OP_GTE, - // MADD_EE carry a disambiguator that should NOT appear in the printed - // mnemonic (the canonical assembly form is just `dmul`, `op`, `madd`). - name: string - #partial switch m { - case .DMUL_R6: name = "DMUL" - case .DDIV_R6: name = "DDIV" - case .DDIVU_R6: name = "DDIVU" - case .OP_GTE: name = "OP" - case .SQR_GTE: name = "SQR" - case .MADD_EE: name = "MADD" - case .MADDU_EE: name = "MADDU" - case .MSUB_EE: name = "MSUB" - case .MSUBU_EE: name = "MSUBU" - case: - n, ok := reflect.enum_name_from_value(m) - if !ok { - strings.write_string(sb, "") - return + // No disambiguator overrides any more: the enum holds assembler + // mnemonics, and the ISA-variant encodings that used to need a suffix + // (pre-R6 vs R6 MUL, the PS2 MMI MADD, the PS1 GTE OP) are now forms of + // one mnemonic, picked by operand shape or by the caller's Feature_Set. + name, ok := reflect.enum_name_from_value(m) + if !ok { + strings.write_string(sb, "") + return + } + // Underscores become dots -- except in MSA, which spells the sign + // qualifier with an underscore and only the element size with a dot: + // `adds_s.b`, `max_s.h`, `copy_u.w`. An assembler rejects `adds.s.b`. + // Nothing in the NAME distinguishes the two: MSA's ADDS_S_D and the FP + // convert CVT_S_D have the same shape and need opposite treatment, so + // the family has to come from the form's feature. Only the LAST + // underscore is a dot for MSA; every underscore is a dot elsewhere. + dot_only_last := is_msa(m) + last_underscore := -1 + if dot_only_last { + for i in 0..= 'A' && c <= 'Z' { strings.write_byte(sb, c + 32) } else { @@ -348,6 +351,15 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { } } +// Is this mnemonic an MSA (MIPS SIMD) instruction? Read off the form table +// rather than the name, which cannot tell MSA apart from the FP converts. +@(private="file", require_results) +is_msa :: proc(m: Mnemonic) -> bool { + r := ENCODE_RUNS[u16(m)] + if r.count == 0 { return false } + return ENCODE_FORMS[r.start].feature == .MSA +} + @(private="file") write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { if r == NONE { diff --git a/core/rexcode/isa/mips/tablegen/encoding_table.odin b/core/rexcode/isa/mips/tablegen/encoding_table.odin index d3ca71fb1..0a32ce1d8 100644 --- a/core/rexcode/isa/mips/tablegen/encoding_table.odin +++ b/core/rexcode/isa/mips/tablegen/encoding_table.odin @@ -54,8 +54,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // mask = OPCODE | RD | SHAMT | FUNCT = 0xFC00FFFF .MULT = { {.MULT, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x00000018, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}} }, .MULTU = { {.MULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x00000019, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}} }, - .DIV = { {.DIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001A, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}} }, - .DIVU = { {.DIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001B, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}} }, + .DIV = { + {.DIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001A, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}}, + {.DIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {}}, + }, + .DIVU = { + {.DIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001B, 0xFC00FFFF, .MIPS_I, {writes_hilo=true}}, + {.DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {}}, + }, // ---- HI/LO move ---------------------------------------------------------- // MF*: only rd is operand; mask = OPCODE | RS | RT | SHAMT | FUNCT = 0xFFFF07FF @@ -214,8 +220,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Doubleword multiply/divide. .DMULT = { {.DMULT, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001C, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}} }, .DMULTU = { {.DMULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001D, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}} }, - .DDIV = { {.DDIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001E, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}} }, - .DDIVU = { {.DDIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001F, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}} }, + .DDIV = { + {.DDIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001E, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}}, + {.DDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true}}, + }, + .DDIVU = { + {.DDIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001F, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true}}, + {.DDIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true}}, + }, // Doubleword shifts by constant. .DSLL = { {.DSLL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x00000038, 0xFFE0003F, .MIPS_III, {only_64=true}} }, @@ -273,11 +285,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // SPECIAL2 (opcode 0x1C) โ€” common shape: bits = (0x1C<<26) | funct = 0x70000000 | f. // mask = OPCODE | SHAMT | FUNCT = 0xFC0007FF (shamt=0 fixed). - .MADD = { {.MADD, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000000, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}} }, - .MADDU = { {.MADDU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000001, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}} }, - .MUL = { {.MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000002, 0xFC0007FF, .MIPS32_R1, {}} }, - .MSUB = { {.MSUB, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000004, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}} }, - .MSUBU = { {.MSUBU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000005, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}} }, + .MADD = { + {.MADD, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000000, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}}, + {.MADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}}, + }, + .MADDU = { + {.MADDU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000001, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}}, + {.MADDU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}}, + }, + .MUL = { + {.MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000002, 0xFC0007FF, .MIPS32_R1, {}}, + {.MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {}}, + }, + .MSUB = { + {.MSUB, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000004, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}}, + {.MSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}}, + }, + .MSUBU = { + {.MSUBU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000005, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true}}, + {.MSUBU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}}, + }, .CLZ = { {.CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x70000020, 0xFC1F07FF, .MIPS32_R1, {}} }, .CLO = { {.CLO, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x70000021, 0xFC1F07FF, .MIPS32_R1, {}} }, .DCLZ = { {.DCLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x70000024, 0xFC1F07FF, .MIPS64_R1, {only_64=true}} }, @@ -535,7 +562,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .RTPS = { {.RTPS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000001, 0xFE00003F, .GTE_PS1, {}} }, .NCLIP = { {.NCLIP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000006, 0xFE00003F, .GTE_PS1, {}} }, - .OP_GTE = { {.OP_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {}} }, .DPCS = { {.DPCS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000010, 0xFE00003F, .GTE_PS1, {}} }, .INTPL = { {.INTPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000011, 0xFE00003F, .GTE_PS1, {}} }, .MVMVA = { {.MVMVA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000012, 0xFE00003F, .GTE_PS1, {}} }, @@ -546,7 +572,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .CC = { {.CC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00001C, 0xFE00003F, .GTE_PS1, {}} }, .NCS = { {.NCS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00001E, 0xFE00003F, .GTE_PS1, {}} }, .NCT = { {.NCT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000020, 0xFE00003F, .GTE_PS1, {}} }, - .SQR_GTE = { {.SQR_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {}} }, .DCPL = { {.DCPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000029, 0xFE00003F, .GTE_PS1, {}} }, .DPCT = { {.DPCT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002A, 0xFE00003F, .GTE_PS1, {}} }, .AVSZ3 = { {.AVSZ3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002D, 0xFE00003F, .GTE_PS1, {}} }, @@ -596,10 +621,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // R5900 three-operand multiply-accumulate (writes Rd as well as HI/LO). // Same SPECIAL2 funcs as the MIPS32 two-operand MADD/MADDU/MSUB/MSUBU; the // Rd != 0 form is selected by the less-specific mask after those match. - .MADD_EE = { {.MADD_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}} }, - .MADDU_EE = { {.MADDU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}} }, - .MSUB_EE = { {.MSUB_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}} }, - .MSUBU_EE = { {.MSUBU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true}} }, // Pack/unpack HI:LO (PMFHL with 5-bit sub-op in sa slot). .PMFHL_LW = { {.PMFHL_LW, {.GPR,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x70000030, 0xFFFF07FF, .MMI_PS2, {}} }, @@ -753,22 +774,16 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // R6 mul/div: reuse SPECIAL functs 0x18-0x1F (which were MULT/MULTU/ // DIV/DIVU in pre-R6) with shamt distinguishing low half (0x02) from // high half (0x03). Results land in rd, not HI/LO. - .MUL_R6 = { {.MUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {}} }, .MUH = { {.MUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D8, 0xFC0007FF, .MIPS32_R6, {}} }, .MULU = { {.MULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000099, 0xFC0007FF, .MIPS32_R6, {}} }, .MUHU = { {.MUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D9, 0xFC0007FF, .MIPS32_R6, {}} }, - .DIV_R6 = { {.DIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {}} }, .MOD = { {.MOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DA, 0xFC0007FF, .MIPS32_R6, {}} }, - .DIVU_R6 = { {.DIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {}} }, .MODU = { {.MODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DB, 0xFC0007FF, .MIPS32_R6, {}} }, // 64-bit R6 mul/div (functs 0x1C-0x1F). - .DMUL_R6 = { {.DMUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, .DMUH = { {.DMUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DC, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, .DMULU = { {.DMULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009D, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, .DMUHU = { {.DMUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DD, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, - .DDIV_R6 = { {.DDIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, .DMOD = { {.DMOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DE, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, - .DDIVU_R6 = { {.DDIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, .DMODU = { {.DMODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DF, 0xFC0007FF, .MIPS64_R6, {only_64=true}} }, // LSA / DLSA (load shifted add): SPECIAL funct=0x05/0x15 with sa=imm2. @@ -1723,4 +1738,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .LWUPC = { {.LWUPC, {.GPR,.REL19,.NONE,.NONE}, {.RS,.BRANCH_19,.NONE,.NONE}, 0xEC100000, 0xFC180000, .MIPS64_R6, {}} }, .LDPC = { {.LDPC, {.GPR,.REL18,.NONE,.NONE}, {.RS,.BRANCH_18,.NONE,.NONE}, 0xEC180000, 0xFC1C0000, .MIPS64_R6, {}} }, // SPECGEN:END + .OP = { + {.OP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {}}, + }, + .SQR = { + {.SQR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {}}, + }, + .DMUL = { + {.DMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true}}, + }, } diff --git a/core/rexcode/isa/mips/tablegen/generated/decode_tables.odin b/core/rexcode/isa/mips/tablegen/generated/decode_tables.odin index 5251ef669..08a494482 100644 --- a/core/rexcode/isa/mips/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/mips/tablegen/generated/decode_tables.odin @@ -41,28 +41,28 @@ DECODE_ENTRIES := [1029]lib.Decode_Entry{ { .DROTRV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RT,.RS,.NONE}, 0x00000056, 0xFC0007FF, .MIPS64_R2, {only_64=true} }, { .DSRAV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RT,.RS,.NONE}, 0x00000017, 0xFC0007FF, .MIPS_III, {only_64=true} }, { .MULT, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x00000018, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, - { .MUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {} }, { .MUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D8, 0xFC0007FF, .MIPS32_R6, {} }, { .MULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x00000019, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, { .MULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000099, 0xFC0007FF, .MIPS32_R6, {} }, { .MUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D9, 0xFC0007FF, .MIPS32_R6, {} }, { .DIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001A, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, - { .DIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {} }, + { .DIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {} }, { .MOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DA, 0xFC0007FF, .MIPS32_R6, {} }, { .DIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001B, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, - { .DIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {} }, + { .DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {} }, { .MODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DB, 0xFC0007FF, .MIPS32_R6, {} }, { .DMULT, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001C, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, - { .DMUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, + { .DMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DMUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DC, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DMULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001D, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, { .DMULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009D, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DMUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DD, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DDIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001E, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, - { .DDIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, + { .DDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DMOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DE, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DDIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001F, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, - { .DDIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, + { .DDIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .DMODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DF, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000020, 0xFC0007FF, .MIPS_I, {} }, { .ADDU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000021, 0xFC0007FF, .MIPS_I, {} }, @@ -318,10 +318,10 @@ DECODE_ENTRIES := [1029]lib.Decode_Entry{ { .NCLIP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000006, 0xFE00003F, .GTE_PS1, {} }, { .AVSZ3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002D, 0xFE00003F, .GTE_PS1, {} }, { .AVSZ4, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002E, 0xFE00003F, .GTE_PS1, {} }, - { .OP_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {} }, + { .OP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {} }, { .GPF, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00003D, 0xFE00003F, .GTE_PS1, {} }, { .GPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00003E, 0xFE00003F, .GTE_PS1, {} }, - { .SQR_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {} }, + { .SQR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {} }, { .DCPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000029, 0xFE00003F, .GTE_PS1, {} }, { .BVF, {.IMM5,.REL16,.NONE,.NONE}, {.VFPU_CC3,.BRANCH_16,.NONE,.NONE}, 0x49000000, 0xFFE30000, .VFPU_PSP, {delay_slot=true} }, { .BVT, {.IMM5,.REL16,.NONE,.NONE}, {.VFPU_CC3,.BRANCH_16,.NONE,.NONE}, 0x49010000, 0xFFE30000, .VFPU_PSP, {delay_slot=true} }, @@ -404,15 +404,15 @@ DECODE_ENTRIES := [1029]lib.Decode_Entry{ { .VMAX_Q, {.VFPU_Q,.VFPU_Q,.VFPU_Q,.NONE}, {.VFPU_VD,.VFPU_VS,.VFPU_VT,.NONE}, 0x6D808080, 0xFF808080, .VFPU_PSP, {} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE,.NONE,.NONE}, 0x6C000000, 0xFC000000, .MIPS_III, {only_64=true} }, { .MADD, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000000, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, - { .MADD_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, + { .MADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, { .MADDU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000001, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, - { .MADDU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, + { .MADDU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000002, 0xFC0007FF, .MIPS32_R1, {} }, { .MSUB, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000004, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, { .PLZCW, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x70000004, 0xFC1F07FF, .MMI_PS2, {} }, - { .MSUB_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, + { .MSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, { .MSUBU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000005, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, - { .MSUBU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, + { .MSUBU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, { .PADDB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000208, 0xFC0007FF, .MMI_PS2, {} }, { .PADDH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000108, 0xFC0007FF, .MMI_PS2, {} }, { .PADDW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000008, 0xFC0007FF, .MMI_PS2, {} }, diff --git a/core/rexcode/isa/mips/tablegen/generated/encode_tables.odin b/core/rexcode/isa/mips/tablegen/generated/encode_tables.odin index d30194688..f65dbe824 100644 --- a/core/rexcode/isa/mips/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/mips/tablegen/generated/encode_tables.odin @@ -23,8 +23,10 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .MULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x00000019, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, // .DIV { .DIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001A, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, + { .DIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {} }, // .DIVU { .DIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001B, 0xFC00FFFF, .MIPS_I, {writes_hilo=true} }, + { .DIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {} }, // .MFHI { .MFHI, {.GPR,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x00000010, 0xFFFF07FF, .MIPS_I, {} }, // .MFLO @@ -191,8 +193,10 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .DMULTU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001D, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, // .DDIV { .DDIV, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001E, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, + { .DDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DDIVU { .DDIVU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x0000001F, 0xFC00FFFF, .MIPS_III, {only_64=true, writes_hilo=true} }, + { .DDIVU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DSLL { .DSLL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x00000038, 0xFFE0003F, .MIPS_III, {only_64=true} }, // .DSRL @@ -259,14 +263,19 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .DCLO, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RS,.NONE,.NONE}, 0x70000025, 0xFC1F07FF, .MIPS64_R1, {only_64=true} }, // .MUL { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000002, 0xFC0007FF, .MIPS32_R1, {} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {} }, // .MADD { .MADD, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000000, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, + { .MADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, // .MADDU { .MADDU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000001, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, + { .MADDU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, // .MSUB { .MSUB, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000004, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, + { .MSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, // .MSUBU { .MSUBU, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000005, 0xFC00FFFF, .MIPS32_R1, {writes_hilo=true} }, + { .MSUBU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, // .SDBBP { .SDBBP, {.IMM20,.NONE,.NONE,.NONE}, {.IMM_20,.NONE,.NONE,.NONE}, 0x7000003F, 0xFC00003F, .MIPS32_R1, {} }, // .SSNOP @@ -367,36 +376,26 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .JIC, {.GPR,.IMM16S,.NONE,.NONE}, {.RT,.IMM_16,.NONE,.NONE}, 0xD8000000, 0xFFE00000, .MIPS32_R6, {compact=true} }, // .JIALC { .JIALC, {.GPR,.IMM16S,.NONE,.NONE}, {.RT,.IMM_16,.NONE,.NONE}, 0xF8000000, 0xFFE00000, .MIPS32_R6, {compact=true} }, - // .MUL_R6 - { .MUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000098, 0xFC0007FF, .MIPS32_R6, {} }, // .MUH { .MUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D8, 0xFC0007FF, .MIPS32_R6, {} }, // .MULU { .MULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000099, 0xFC0007FF, .MIPS32_R6, {} }, // .MUHU { .MUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000D9, 0xFC0007FF, .MIPS32_R6, {} }, - // .DIV_R6 - { .DIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009A, 0xFC0007FF, .MIPS32_R6, {} }, // .MOD { .MOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DA, 0xFC0007FF, .MIPS32_R6, {} }, - // .DIVU_R6 - { .DIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009B, 0xFC0007FF, .MIPS32_R6, {} }, // .MODU { .MODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DB, 0xFC0007FF, .MIPS32_R6, {} }, - // .DMUL_R6 - { .DMUL_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, + // .DMUL + { .DMUL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009C, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DMUH { .DMUH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DC, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DMULU { .DMULU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009D, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DMUHU { .DMUHU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DD, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, - // .DDIV_R6 - { .DDIV_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009E, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DMOD { .DMOD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DE, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, - // .DDIVU_R6 - { .DDIVU_R6, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x0000009F, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .DMODU { .DMODU, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x000000DF, 0xFC0007FF, .MIPS64_R6, {only_64=true} }, // .AUI @@ -817,14 +816,14 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .AVSZ3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002D, 0xFE00003F, .GTE_PS1, {} }, // .AVSZ4 { .AVSZ4, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00002E, 0xFE00003F, .GTE_PS1, {} }, - // .OP_GTE - { .OP_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {} }, + // .OP + { .OP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00000C, 0xFE00003F, .GTE_PS1, {} }, // .GPF { .GPF, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00003D, 0xFE00003F, .GTE_PS1, {} }, // .GPL { .GPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A00003E, 0xFE00003F, .GTE_PS1, {} }, - // .SQR_GTE - { .SQR_GTE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {} }, + // .SQR + { .SQR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000028, 0xFE00003F, .GTE_PS1, {} }, // .DCPL { .DCPL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x4A000029, 0xFE00003F, .GTE_PS1, {} }, // .LQ @@ -851,14 +850,6 @@ ENCODE_FORMS := [1029]lib.Encoding{ { .DIV1, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x7000001A, 0xFC00FFFF, .MMI_PS2, {writes_hilo=true} }, // .DIVU1 { .DIVU1, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x7000001B, 0xFC00FFFF, .MMI_PS2, {writes_hilo=true} }, - // .MADD_EE - { .MADD_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000000, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, - // .MADDU_EE - { .MADDU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000001, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, - // .MSUB_EE - { .MSUB_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000004, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, - // .MSUBU_EE - { .MSUBU_EE, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x70000005, 0xFC0007FF, .MMI_PS2, {writes_hilo=true} }, // .MADD1 { .MADD1, {.GPR,.GPR,.NONE,.NONE}, {.RS,.RT,.NONE,.NONE}, 0x70000020, 0xFC00FFFF, .MMI_PS2, {writes_hilo=true} }, // .MADDU1 @@ -2078,425 +2069,416 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .SUBU = { 3, 1}, .MULT = { 4, 1}, .MULTU = { 5, 1}, - .DIV = { 6, 1}, - .DIVU = { 7, 1}, - .MFHI = { 8, 1}, - .MFLO = { 9, 1}, - .MTHI = { 10, 1}, - .MTLO = { 11, 1}, - .AND = { 12, 1}, - .OR = { 13, 1}, - .XOR = { 14, 1}, - .NOR = { 15, 1}, - .SLT = { 16, 1}, - .SLTU = { 17, 1}, - .SLL = { 18, 1}, - .SRL = { 19, 1}, - .SRA = { 20, 1}, - .SLLV = { 21, 1}, - .SRLV = { 22, 1}, - .SRAV = { 23, 1}, - .ADDI = { 24, 1}, - .ADDIU = { 25, 1}, - .SLTI = { 26, 1}, - .SLTIU = { 27, 1}, - .ANDI = { 28, 1}, - .ORI = { 29, 1}, - .XORI = { 30, 1}, - .LUI = { 31, 1}, - .BEQ = { 32, 1}, - .BNE = { 33, 1}, - .BLEZ = { 34, 1}, - .BGTZ = { 35, 1}, - .BLTZ = { 36, 1}, - .BGEZ = { 37, 1}, - .BLTZAL = { 38, 1}, - .BGEZAL = { 39, 1}, - .J = { 40, 1}, - .JAL = { 41, 1}, - .JR = { 42, 1}, - .JALR = { 43, 1}, - .LB = { 44, 1}, - .LH = { 45, 1}, - .LW = { 46, 1}, - .LBU = { 47, 1}, - .LHU = { 48, 1}, - .LWL = { 49, 1}, - .LWR = { 50, 1}, - .SB = { 51, 1}, - .SH = { 52, 1}, - .SW = { 53, 1}, - .SWL = { 54, 1}, - .SWR = { 55, 1}, - .SYSCALL = { 56, 1}, - .BREAK = { 57, 1}, - .NOP = { 58, 1}, - .LL = { 59, 1}, - .SC = { 60, 1}, - .SYNC = { 61, 1}, - .TGEI = { 62, 1}, - .TGEIU = { 63, 1}, - .TLTI = { 64, 1}, - .TLTIU = { 65, 1}, - .TEQI = { 66, 1}, - .TNEI = { 67, 1}, - .TGE = { 68, 1}, - .TGEU = { 69, 1}, - .TLT = { 70, 1}, - .TLTU = { 71, 1}, - .TEQ = { 72, 1}, - .TNE = { 73, 1}, - .BEQL = { 74, 1}, - .BNEL = { 75, 1}, - .BLEZL = { 76, 1}, - .BGTZL = { 77, 1}, - .BLTZL = { 78, 1}, - .BGEZL = { 79, 1}, - .BLTZALL = { 80, 1}, - .BGEZALL = { 81, 1}, - .DADD = { 82, 1}, - .DADDU = { 83, 1}, - .DSUB = { 84, 1}, - .DSUBU = { 85, 1}, - .DADDI = { 86, 1}, - .DADDIU = { 87, 1}, - .DMULT = { 88, 1}, - .DMULTU = { 89, 1}, - .DDIV = { 90, 1}, - .DDIVU = { 91, 1}, - .DSLL = { 92, 1}, - .DSRL = { 93, 1}, - .DSRA = { 94, 1}, - .DSLLV = { 95, 1}, - .DSRLV = { 96, 1}, - .DSRAV = { 97, 1}, - .DSLL32 = { 98, 1}, - .DSRL32 = { 99, 1}, - .DSRA32 = { 100, 1}, - .LD = { 101, 1}, - .LDL = { 102, 1}, - .LDR = { 103, 1}, - .LWU = { 104, 1}, - .SD = { 105, 1}, - .SDL = { 106, 1}, - .SDR = { 107, 1}, - .LLD = { 108, 1}, - .SCD = { 109, 1}, - .MOVN = { 110, 1}, - .MOVZ = { 111, 1}, - .MOVF = { 112, 1}, - .MOVT = { 113, 1}, - .PREF = { 114, 1}, - .PREFX = { 115, 1}, - .LWXC1 = { 116, 1}, - .SWXC1 = { 117, 1}, - .LDXC1 = { 118, 1}, - .SDXC1 = { 119, 1}, - .CLZ = { 120, 1}, - .CLO = { 121, 1}, - .DCLZ = { 122, 1}, - .DCLO = { 123, 1}, - .MUL = { 124, 1}, - .MADD = { 125, 1}, - .MADDU = { 126, 1}, - .MSUB = { 127, 1}, - .MSUBU = { 128, 1}, - .SDBBP = { 129, 1}, - .SSNOP = { 130, 1}, - .EHB = { 131, 1}, - .PAUSE = { 132, 1}, - .EXT = { 133, 1}, - .INS = { 134, 1}, - .DEXT = { 135, 1}, - .DEXTM = { 136, 1}, - .DEXTU = { 137, 1}, - .DINS = { 138, 1}, - .DINSM = { 139, 1}, - .DINSU = { 140, 1}, - .ROTR = { 141, 1}, - .ROTRV = { 142, 1}, - .DROTR = { 143, 1}, - .DROTRV = { 144, 1}, - .DROTR32 = { 145, 1}, - .WSBH = { 146, 1}, - .DSBH = { 147, 1}, - .DSHD = { 148, 1}, - .SEB = { 149, 1}, - .SEH = { 150, 1}, - .RDHWR = { 151, 1}, - .RDPGPR = { 152, 1}, - .WRPGPR = { 153, 1}, - .DI = { 154, 1}, - .EI = { 155, 1}, - .ERET = { 156, 1}, - .DERET = { 157, 1}, - .WAIT = { 158, 1}, - .BC = { 159, 1}, - .BALC = { 160, 1}, - .BEQC = { 161, 1}, - .BNEC = { 162, 1}, - .BLTC = { 163, 1}, - .BGEC = { 164, 1}, - .BLTUC = { 165, 1}, - .BGEUC = { 166, 1}, - .BLEZC = { 167, 1}, - .BGEZC = { 168, 1}, - .BGTZC = { 169, 1}, - .BLTZC = { 170, 1}, - .BEQZC = { 171, 1}, - .BNEZC = { 172, 1}, - .BC1EQZ = { 173, 1}, - .BC1NEZ = { 174, 1}, - .BC2EQZ = { 175, 1}, - .BC2NEZ = { 176, 1}, - .JIC = { 177, 1}, - .JIALC = { 178, 1}, - .MUL_R6 = { 179, 1}, - .MUH = { 180, 1}, - .MULU = { 181, 1}, - .MUHU = { 182, 1}, - .DIV_R6 = { 183, 1}, - .MOD = { 184, 1}, - .DIVU_R6 = { 185, 1}, - .MODU = { 186, 1}, - .DMUL_R6 = { 187, 1}, - .DMUH = { 188, 1}, - .DMULU = { 189, 1}, - .DMUHU = { 190, 1}, - .DDIV_R6 = { 191, 1}, - .DMOD = { 192, 1}, - .DDIVU_R6 = { 193, 1}, - .DMODU = { 194, 1}, - .AUI = { 195, 1}, - .AUIPC = { 196, 1}, - .ALUIPC = { 197, 1}, - .DAUI = { 198, 1}, - .DAHI = { 199, 1}, - .DATI = { 200, 1}, - .ALIGN = { 201, 1}, - .DALIGN = { 202, 1}, - .BITSWAP = { 203, 1}, - .DBITSWAP = { 204, 1}, - .LSA = { 205, 1}, - .DLSA = { 206, 1}, - .LWPC = { 207, 1}, - .LWUPC = { 208, 1}, - .LDPC = { 209, 1}, - .SELEQZ = { 210, 1}, - .SELNEZ = { 211, 1}, - .CRC32B = { 212, 1}, - .CRC32H = { 213, 1}, - .CRC32W = { 214, 1}, - .CRC32D = { 215, 1}, - .CRC32CB = { 216, 1}, - .CRC32CH = { 217, 1}, - .CRC32CW = { 218, 1}, - .CRC32CD = { 219, 1}, - .SIGRIE = { 220, 1}, - .MFC1 = { 221, 1}, - .MTC1 = { 222, 1}, - .DMFC1 = { 223, 1}, - .DMTC1 = { 224, 1}, - .CFC1 = { 225, 1}, - .CTC1 = { 226, 1}, - .MFHC1 = { 227, 1}, - .MTHC1 = { 228, 1}, - .LWC1 = { 229, 1}, - .SWC1 = { 230, 1}, - .LDC1 = { 231, 1}, - .SDC1 = { 232, 1}, - .ADD_S = { 233, 1}, - .ADD_D = { 234, 1}, - .ADD_PS = { 235, 1}, - .SUB_S = { 236, 1}, - .SUB_D = { 237, 1}, - .SUB_PS = { 238, 1}, - .MUL_S = { 239, 1}, - .MUL_D = { 240, 1}, - .MUL_PS = { 241, 1}, - .DIV_S = { 242, 1}, - .DIV_D = { 243, 1}, - .SQRT_S = { 244, 1}, - .SQRT_D = { 245, 1}, - .ABS_S = { 246, 1}, - .ABS_D = { 247, 1}, - .ABS_PS = { 248, 1}, - .NEG_S = { 249, 1}, - .NEG_D = { 250, 1}, - .NEG_PS = { 251, 1}, - .MOV_S = { 252, 1}, - .MOV_D = { 253, 1}, - .MOV_PS = { 254, 1}, - .RECIP_S = { 255, 1}, - .RECIP_D = { 256, 1}, - .RSQRT_S = { 257, 1}, - .RSQRT_D = { 258, 1}, - .MADD_S = { 259, 1}, - .MADD_D = { 260, 1}, - .MADD_PS = { 261, 1}, - .MSUB_S = { 262, 1}, - .MSUB_D = { 263, 1}, - .MSUB_PS = { 264, 1}, - .NMADD_S = { 265, 1}, - .NMADD_D = { 266, 1}, - .NMADD_PS = { 267, 1}, - .NMSUB_S = { 268, 1}, - .NMSUB_D = { 269, 1}, - .NMSUB_PS = { 270, 1}, - .MOVN_S = { 271, 1}, - .MOVN_D = { 272, 1}, - .MOVN_PS = { 273, 1}, - .MOVZ_S = { 274, 1}, - .MOVZ_D = { 275, 1}, - .MOVZ_PS = { 276, 1}, - .MOVF_S = { 277, 1}, - .MOVF_D = { 278, 1}, - .MOVF_PS = { 279, 1}, - .MOVT_S = { 280, 1}, - .MOVT_D = { 281, 1}, - .MOVT_PS = { 282, 1}, - .CVT_S_D = { 283, 1}, - .CVT_S_W = { 284, 1}, - .CVT_S_L = { 285, 1}, - .CVT_D_S = { 286, 1}, - .CVT_D_W = { 287, 1}, - .CVT_D_L = { 288, 1}, - .CVT_W_S = { 289, 1}, - .CVT_W_D = { 290, 1}, - .CVT_L_S = { 291, 1}, - .CVT_L_D = { 292, 1}, - .CVT_PS_S = { 293, 1}, - .CVT_S_PU = { 294, 1}, - .CVT_S_PL = { 295, 1}, - .PLL_PS = { 296, 1}, - .PLU_PS = { 297, 1}, - .PUL_PS = { 298, 1}, - .PUU_PS = { 299, 1}, - .ROUND_W_S = { 300, 1}, - .ROUND_W_D = { 301, 1}, - .ROUND_L_S = { 302, 1}, - .ROUND_L_D = { 303, 1}, - .TRUNC_W_S = { 304, 1}, - .TRUNC_W_D = { 305, 1}, - .TRUNC_L_S = { 306, 1}, - .TRUNC_L_D = { 307, 1}, - .CEIL_W_S = { 308, 1}, - .CEIL_W_D = { 309, 1}, - .CEIL_L_S = { 310, 1}, - .CEIL_L_D = { 311, 1}, - .FLOOR_W_S = { 312, 1}, - .FLOOR_W_D = { 313, 1}, - .FLOOR_L_S = { 314, 1}, - .FLOOR_L_D = { 315, 1}, - .C_F_S = { 316, 1}, - .C_F_D = { 317, 1}, - .C_F_PS = { 318, 1}, - .C_UN_S = { 319, 1}, - .C_UN_D = { 320, 1}, - .C_UN_PS = { 321, 1}, - .C_EQ_S = { 322, 1}, - .C_EQ_D = { 323, 1}, - .C_EQ_PS = { 324, 1}, - .C_UEQ_S = { 325, 1}, - .C_UEQ_D = { 326, 1}, - .C_UEQ_PS = { 327, 1}, - .C_OLT_S = { 328, 1}, - .C_OLT_D = { 329, 1}, - .C_OLT_PS = { 330, 1}, - .C_ULT_S = { 331, 1}, - .C_ULT_D = { 332, 1}, - .C_ULT_PS = { 333, 1}, - .C_OLE_S = { 334, 1}, - .C_OLE_D = { 335, 1}, - .C_OLE_PS = { 336, 1}, - .C_ULE_S = { 337, 1}, - .C_ULE_D = { 338, 1}, - .C_ULE_PS = { 339, 1}, - .C_SF_S = { 340, 1}, - .C_SF_D = { 341, 1}, - .C_SF_PS = { 342, 1}, - .C_NGLE_S = { 343, 1}, - .C_NGLE_D = { 344, 1}, - .C_NGLE_PS = { 345, 1}, - .C_SEQ_S = { 346, 1}, - .C_SEQ_D = { 347, 1}, - .C_SEQ_PS = { 348, 1}, - .C_NGL_S = { 349, 1}, - .C_NGL_D = { 350, 1}, - .C_NGL_PS = { 351, 1}, - .C_LT_S = { 352, 1}, - .C_LT_D = { 353, 1}, - .C_LT_PS = { 354, 1}, - .C_NGE_S = { 355, 1}, - .C_NGE_D = { 356, 1}, - .C_NGE_PS = { 357, 1}, - .C_LE_S = { 358, 1}, - .C_LE_D = { 359, 1}, - .C_LE_PS = { 360, 1}, - .C_NGT_S = { 361, 1}, - .C_NGT_D = { 362, 1}, - .C_NGT_PS = { 363, 1}, - .BC1F = { 364, 1}, - .BC1T = { 365, 1}, - .BC1FL = { 366, 1}, - .BC1TL = { 367, 1}, - .MFC0 = { 368, 1}, - .MTC0 = { 369, 1}, - .DMFC0 = { 370, 1}, - .DMTC0 = { 371, 1}, - .MFHC0 = { 372, 1}, - .MTHC0 = { 373, 1}, - .TLBP = { 374, 1}, - .TLBR = { 375, 1}, - .TLBWI = { 376, 1}, - .TLBWR = { 377, 1}, - .CACHE = { 378, 1}, - .MFC2 = { 379, 1}, - .MTC2 = { 380, 1}, - .CFC2 = { 381, 1}, - .CTC2 = { 382, 1}, - .LWC2 = { 383, 1}, - .SWC2 = { 384, 1}, - .LDC2 = { 385, 1}, - .SDC2 = { 386, 1}, - .RTPS = { 387, 1}, - .RTPT = { 388, 1}, - .DPCS = { 389, 1}, - .DPCT = { 390, 1}, - .INTPL = { 391, 1}, - .MVMVA = { 392, 1}, - .NCDS = { 393, 1}, - .NCDT = { 394, 1}, - .NCCS = { 395, 1}, - .NCCT = { 396, 1}, - .NCS = { 397, 1}, - .NCT = { 398, 1}, - .CDP = { 399, 1}, - .CC = { 400, 1}, - .NCLIP = { 401, 1}, - .AVSZ3 = { 402, 1}, - .AVSZ4 = { 403, 1}, - .OP_GTE = { 404, 1}, - .GPF = { 405, 1}, - .GPL = { 406, 1}, - .SQR_GTE = { 407, 1}, - .DCPL = { 408, 1}, - .LQ = { 409, 1}, - .SQ = { 410, 1}, - .LQC2 = { 411, 1}, - .SQC2 = { 412, 1}, - .MFHI1 = { 413, 1}, - .MFLO1 = { 414, 1}, - .MTHI1 = { 415, 1}, - .MTLO1 = { 416, 1}, - .MULT1 = { 417, 1}, - .MULTU1 = { 418, 1}, - .DIV1 = { 419, 1}, - .DIVU1 = { 420, 1}, - .MADD_EE = { 421, 1}, - .MADDU_EE = { 422, 1}, - .MSUB_EE = { 423, 1}, - .MSUBU_EE = { 424, 1}, + .DIV = { 6, 2}, + .DIVU = { 8, 2}, + .MFHI = { 10, 1}, + .MFLO = { 11, 1}, + .MTHI = { 12, 1}, + .MTLO = { 13, 1}, + .AND = { 14, 1}, + .OR = { 15, 1}, + .XOR = { 16, 1}, + .NOR = { 17, 1}, + .SLT = { 18, 1}, + .SLTU = { 19, 1}, + .SLL = { 20, 1}, + .SRL = { 21, 1}, + .SRA = { 22, 1}, + .SLLV = { 23, 1}, + .SRLV = { 24, 1}, + .SRAV = { 25, 1}, + .ADDI = { 26, 1}, + .ADDIU = { 27, 1}, + .SLTI = { 28, 1}, + .SLTIU = { 29, 1}, + .ANDI = { 30, 1}, + .ORI = { 31, 1}, + .XORI = { 32, 1}, + .LUI = { 33, 1}, + .BEQ = { 34, 1}, + .BNE = { 35, 1}, + .BLEZ = { 36, 1}, + .BGTZ = { 37, 1}, + .BLTZ = { 38, 1}, + .BGEZ = { 39, 1}, + .BLTZAL = { 40, 1}, + .BGEZAL = { 41, 1}, + .J = { 42, 1}, + .JAL = { 43, 1}, + .JR = { 44, 1}, + .JALR = { 45, 1}, + .LB = { 46, 1}, + .LH = { 47, 1}, + .LW = { 48, 1}, + .LBU = { 49, 1}, + .LHU = { 50, 1}, + .LWL = { 51, 1}, + .LWR = { 52, 1}, + .SB = { 53, 1}, + .SH = { 54, 1}, + .SW = { 55, 1}, + .SWL = { 56, 1}, + .SWR = { 57, 1}, + .SYSCALL = { 58, 1}, + .BREAK = { 59, 1}, + .NOP = { 60, 1}, + .LL = { 61, 1}, + .SC = { 62, 1}, + .SYNC = { 63, 1}, + .TGEI = { 64, 1}, + .TGEIU = { 65, 1}, + .TLTI = { 66, 1}, + .TLTIU = { 67, 1}, + .TEQI = { 68, 1}, + .TNEI = { 69, 1}, + .TGE = { 70, 1}, + .TGEU = { 71, 1}, + .TLT = { 72, 1}, + .TLTU = { 73, 1}, + .TEQ = { 74, 1}, + .TNE = { 75, 1}, + .BEQL = { 76, 1}, + .BNEL = { 77, 1}, + .BLEZL = { 78, 1}, + .BGTZL = { 79, 1}, + .BLTZL = { 80, 1}, + .BGEZL = { 81, 1}, + .BLTZALL = { 82, 1}, + .BGEZALL = { 83, 1}, + .DADD = { 84, 1}, + .DADDU = { 85, 1}, + .DSUB = { 86, 1}, + .DSUBU = { 87, 1}, + .DADDI = { 88, 1}, + .DADDIU = { 89, 1}, + .DMULT = { 90, 1}, + .DMULTU = { 91, 1}, + .DDIV = { 92, 2}, + .DDIVU = { 94, 2}, + .DSLL = { 96, 1}, + .DSRL = { 97, 1}, + .DSRA = { 98, 1}, + .DSLLV = { 99, 1}, + .DSRLV = { 100, 1}, + .DSRAV = { 101, 1}, + .DSLL32 = { 102, 1}, + .DSRL32 = { 103, 1}, + .DSRA32 = { 104, 1}, + .LD = { 105, 1}, + .LDL = { 106, 1}, + .LDR = { 107, 1}, + .LWU = { 108, 1}, + .SD = { 109, 1}, + .SDL = { 110, 1}, + .SDR = { 111, 1}, + .LLD = { 112, 1}, + .SCD = { 113, 1}, + .MOVN = { 114, 1}, + .MOVZ = { 115, 1}, + .MOVF = { 116, 1}, + .MOVT = { 117, 1}, + .PREF = { 118, 1}, + .PREFX = { 119, 1}, + .LWXC1 = { 120, 1}, + .SWXC1 = { 121, 1}, + .LDXC1 = { 122, 1}, + .SDXC1 = { 123, 1}, + .CLZ = { 124, 1}, + .CLO = { 125, 1}, + .DCLZ = { 126, 1}, + .DCLO = { 127, 1}, + .MUL = { 128, 2}, + .MADD = { 130, 2}, + .MADDU = { 132, 2}, + .MSUB = { 134, 2}, + .MSUBU = { 136, 2}, + .SDBBP = { 138, 1}, + .SSNOP = { 139, 1}, + .EHB = { 140, 1}, + .PAUSE = { 141, 1}, + .EXT = { 142, 1}, + .INS = { 143, 1}, + .DEXT = { 144, 1}, + .DEXTM = { 145, 1}, + .DEXTU = { 146, 1}, + .DINS = { 147, 1}, + .DINSM = { 148, 1}, + .DINSU = { 149, 1}, + .ROTR = { 150, 1}, + .ROTRV = { 151, 1}, + .DROTR = { 152, 1}, + .DROTRV = { 153, 1}, + .DROTR32 = { 154, 1}, + .WSBH = { 155, 1}, + .DSBH = { 156, 1}, + .DSHD = { 157, 1}, + .SEB = { 158, 1}, + .SEH = { 159, 1}, + .RDHWR = { 160, 1}, + .RDPGPR = { 161, 1}, + .WRPGPR = { 162, 1}, + .DI = { 163, 1}, + .EI = { 164, 1}, + .ERET = { 165, 1}, + .DERET = { 166, 1}, + .WAIT = { 167, 1}, + .BC = { 168, 1}, + .BALC = { 169, 1}, + .BEQC = { 170, 1}, + .BNEC = { 171, 1}, + .BLTC = { 172, 1}, + .BGEC = { 173, 1}, + .BLTUC = { 174, 1}, + .BGEUC = { 175, 1}, + .BLEZC = { 176, 1}, + .BGEZC = { 177, 1}, + .BGTZC = { 178, 1}, + .BLTZC = { 179, 1}, + .BEQZC = { 180, 1}, + .BNEZC = { 181, 1}, + .BC1EQZ = { 182, 1}, + .BC1NEZ = { 183, 1}, + .BC2EQZ = { 184, 1}, + .BC2NEZ = { 185, 1}, + .JIC = { 186, 1}, + .JIALC = { 187, 1}, + .MUH = { 188, 1}, + .MULU = { 189, 1}, + .MUHU = { 190, 1}, + .MOD = { 191, 1}, + .MODU = { 192, 1}, + .DMUL = { 193, 1}, + .DMUH = { 194, 1}, + .DMULU = { 195, 1}, + .DMUHU = { 196, 1}, + .DMOD = { 197, 1}, + .DMODU = { 198, 1}, + .AUI = { 199, 1}, + .AUIPC = { 200, 1}, + .ALUIPC = { 201, 1}, + .DAUI = { 202, 1}, + .DAHI = { 203, 1}, + .DATI = { 204, 1}, + .ALIGN = { 205, 1}, + .DALIGN = { 206, 1}, + .BITSWAP = { 207, 1}, + .DBITSWAP = { 208, 1}, + .LSA = { 209, 1}, + .DLSA = { 210, 1}, + .LWPC = { 211, 1}, + .LWUPC = { 212, 1}, + .LDPC = { 213, 1}, + .SELEQZ = { 214, 1}, + .SELNEZ = { 215, 1}, + .CRC32B = { 216, 1}, + .CRC32H = { 217, 1}, + .CRC32W = { 218, 1}, + .CRC32D = { 219, 1}, + .CRC32CB = { 220, 1}, + .CRC32CH = { 221, 1}, + .CRC32CW = { 222, 1}, + .CRC32CD = { 223, 1}, + .SIGRIE = { 224, 1}, + .MFC1 = { 225, 1}, + .MTC1 = { 226, 1}, + .DMFC1 = { 227, 1}, + .DMTC1 = { 228, 1}, + .CFC1 = { 229, 1}, + .CTC1 = { 230, 1}, + .MFHC1 = { 231, 1}, + .MTHC1 = { 232, 1}, + .LWC1 = { 233, 1}, + .SWC1 = { 234, 1}, + .LDC1 = { 235, 1}, + .SDC1 = { 236, 1}, + .ADD_S = { 237, 1}, + .ADD_D = { 238, 1}, + .ADD_PS = { 239, 1}, + .SUB_S = { 240, 1}, + .SUB_D = { 241, 1}, + .SUB_PS = { 242, 1}, + .MUL_S = { 243, 1}, + .MUL_D = { 244, 1}, + .MUL_PS = { 245, 1}, + .DIV_S = { 246, 1}, + .DIV_D = { 247, 1}, + .SQRT_S = { 248, 1}, + .SQRT_D = { 249, 1}, + .ABS_S = { 250, 1}, + .ABS_D = { 251, 1}, + .ABS_PS = { 252, 1}, + .NEG_S = { 253, 1}, + .NEG_D = { 254, 1}, + .NEG_PS = { 255, 1}, + .MOV_S = { 256, 1}, + .MOV_D = { 257, 1}, + .MOV_PS = { 258, 1}, + .RECIP_S = { 259, 1}, + .RECIP_D = { 260, 1}, + .RSQRT_S = { 261, 1}, + .RSQRT_D = { 262, 1}, + .MADD_S = { 263, 1}, + .MADD_D = { 264, 1}, + .MADD_PS = { 265, 1}, + .MSUB_S = { 266, 1}, + .MSUB_D = { 267, 1}, + .MSUB_PS = { 268, 1}, + .NMADD_S = { 269, 1}, + .NMADD_D = { 270, 1}, + .NMADD_PS = { 271, 1}, + .NMSUB_S = { 272, 1}, + .NMSUB_D = { 273, 1}, + .NMSUB_PS = { 274, 1}, + .MOVN_S = { 275, 1}, + .MOVN_D = { 276, 1}, + .MOVN_PS = { 277, 1}, + .MOVZ_S = { 278, 1}, + .MOVZ_D = { 279, 1}, + .MOVZ_PS = { 280, 1}, + .MOVF_S = { 281, 1}, + .MOVF_D = { 282, 1}, + .MOVF_PS = { 283, 1}, + .MOVT_S = { 284, 1}, + .MOVT_D = { 285, 1}, + .MOVT_PS = { 286, 1}, + .CVT_S_D = { 287, 1}, + .CVT_S_W = { 288, 1}, + .CVT_S_L = { 289, 1}, + .CVT_D_S = { 290, 1}, + .CVT_D_W = { 291, 1}, + .CVT_D_L = { 292, 1}, + .CVT_W_S = { 293, 1}, + .CVT_W_D = { 294, 1}, + .CVT_L_S = { 295, 1}, + .CVT_L_D = { 296, 1}, + .CVT_PS_S = { 297, 1}, + .CVT_S_PU = { 298, 1}, + .CVT_S_PL = { 299, 1}, + .PLL_PS = { 300, 1}, + .PLU_PS = { 301, 1}, + .PUL_PS = { 302, 1}, + .PUU_PS = { 303, 1}, + .ROUND_W_S = { 304, 1}, + .ROUND_W_D = { 305, 1}, + .ROUND_L_S = { 306, 1}, + .ROUND_L_D = { 307, 1}, + .TRUNC_W_S = { 308, 1}, + .TRUNC_W_D = { 309, 1}, + .TRUNC_L_S = { 310, 1}, + .TRUNC_L_D = { 311, 1}, + .CEIL_W_S = { 312, 1}, + .CEIL_W_D = { 313, 1}, + .CEIL_L_S = { 314, 1}, + .CEIL_L_D = { 315, 1}, + .FLOOR_W_S = { 316, 1}, + .FLOOR_W_D = { 317, 1}, + .FLOOR_L_S = { 318, 1}, + .FLOOR_L_D = { 319, 1}, + .C_F_S = { 320, 1}, + .C_F_D = { 321, 1}, + .C_F_PS = { 322, 1}, + .C_UN_S = { 323, 1}, + .C_UN_D = { 324, 1}, + .C_UN_PS = { 325, 1}, + .C_EQ_S = { 326, 1}, + .C_EQ_D = { 327, 1}, + .C_EQ_PS = { 328, 1}, + .C_UEQ_S = { 329, 1}, + .C_UEQ_D = { 330, 1}, + .C_UEQ_PS = { 331, 1}, + .C_OLT_S = { 332, 1}, + .C_OLT_D = { 333, 1}, + .C_OLT_PS = { 334, 1}, + .C_ULT_S = { 335, 1}, + .C_ULT_D = { 336, 1}, + .C_ULT_PS = { 337, 1}, + .C_OLE_S = { 338, 1}, + .C_OLE_D = { 339, 1}, + .C_OLE_PS = { 340, 1}, + .C_ULE_S = { 341, 1}, + .C_ULE_D = { 342, 1}, + .C_ULE_PS = { 343, 1}, + .C_SF_S = { 344, 1}, + .C_SF_D = { 345, 1}, + .C_SF_PS = { 346, 1}, + .C_NGLE_S = { 347, 1}, + .C_NGLE_D = { 348, 1}, + .C_NGLE_PS = { 349, 1}, + .C_SEQ_S = { 350, 1}, + .C_SEQ_D = { 351, 1}, + .C_SEQ_PS = { 352, 1}, + .C_NGL_S = { 353, 1}, + .C_NGL_D = { 354, 1}, + .C_NGL_PS = { 355, 1}, + .C_LT_S = { 356, 1}, + .C_LT_D = { 357, 1}, + .C_LT_PS = { 358, 1}, + .C_NGE_S = { 359, 1}, + .C_NGE_D = { 360, 1}, + .C_NGE_PS = { 361, 1}, + .C_LE_S = { 362, 1}, + .C_LE_D = { 363, 1}, + .C_LE_PS = { 364, 1}, + .C_NGT_S = { 365, 1}, + .C_NGT_D = { 366, 1}, + .C_NGT_PS = { 367, 1}, + .BC1F = { 368, 1}, + .BC1T = { 369, 1}, + .BC1FL = { 370, 1}, + .BC1TL = { 371, 1}, + .MFC0 = { 372, 1}, + .MTC0 = { 373, 1}, + .DMFC0 = { 374, 1}, + .DMTC0 = { 375, 1}, + .MFHC0 = { 376, 1}, + .MTHC0 = { 377, 1}, + .TLBP = { 378, 1}, + .TLBR = { 379, 1}, + .TLBWI = { 380, 1}, + .TLBWR = { 381, 1}, + .CACHE = { 382, 1}, + .MFC2 = { 383, 1}, + .MTC2 = { 384, 1}, + .CFC2 = { 385, 1}, + .CTC2 = { 386, 1}, + .LWC2 = { 387, 1}, + .SWC2 = { 388, 1}, + .LDC2 = { 389, 1}, + .SDC2 = { 390, 1}, + .RTPS = { 391, 1}, + .RTPT = { 392, 1}, + .DPCS = { 393, 1}, + .DPCT = { 394, 1}, + .INTPL = { 395, 1}, + .MVMVA = { 396, 1}, + .NCDS = { 397, 1}, + .NCDT = { 398, 1}, + .NCCS = { 399, 1}, + .NCCT = { 400, 1}, + .NCS = { 401, 1}, + .NCT = { 402, 1}, + .CDP = { 403, 1}, + .CC = { 404, 1}, + .NCLIP = { 405, 1}, + .AVSZ3 = { 406, 1}, + .AVSZ4 = { 407, 1}, + .OP = { 408, 1}, + .GPF = { 409, 1}, + .GPL = { 410, 1}, + .SQR = { 411, 1}, + .DCPL = { 412, 1}, + .LQ = { 413, 1}, + .SQ = { 414, 1}, + .LQC2 = { 415, 1}, + .SQC2 = { 416, 1}, + .MFHI1 = { 417, 1}, + .MFLO1 = { 418, 1}, + .MTHI1 = { 419, 1}, + .MTLO1 = { 420, 1}, + .MULT1 = { 421, 1}, + .MULTU1 = { 422, 1}, + .DIV1 = { 423, 1}, + .DIVU1 = { 424, 1}, .MADD1 = { 425, 1}, .MADDU1 = { 426, 1}, .MSUB1 = { 427, 1}, diff --git a/core/rexcode/isa/mips/tables/mips.encode_forms.bin b/core/rexcode/isa/mips/tables/mips.encode_forms.bin index 270eeb81fdcec8b930c724c59fa4151b1628705c..249d2b18d00dce2f90af2bbac044863ab4494989 100644 GIT binary patch literal 20580 zcmZwP2bdJa)&}6}>DkD#JDVg5v#=l_=n@1}V8?`D1k8ENSutZCvluaFU2|5gq6qk%^+n#8Jv*jWOjav%;7Zt&JAb z2GG*9fwT&kF(_wxS}UVobtSDAt%}zBzs&dLN~u?Esu|aZan^j?Rg9}KXx7B|%{W8L zrk2)3>*mbHHd-t9$MM$DnrYqHM!UL~Ec8re$cW&>CsOXic`*5Y!b zfd*kFa$$A}Vt%7`ZGF8B(uU!(af6jbVyh_2hz(KJC^i%$V@x;OJA*}Q$0{18tUHBArvp%%aPkUQP+u0^xc>1}QN zDfubm$6$#>S&mE5AU84-O_ZgTjI&8Nll&Mr;Gdn#%jF1FvFwds_SJ4KBa>5BBessR zTCsJNbrV}pS)JJW%Id{7aC2_=NqchGeKInWX(MSH(nisy&_>gy((H-l>up3EOWPR6 z^Jp4)MHFwMZA)*Psx@x5wdY3^Z>DWWZ<{Mi`D2TxDT~FXD{B&)p{!YK3-rbB?Za)K zaXm_b9q?OxuCh@4w9V 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zv9gHT0eDYPBHtJvHBj#`0RqZWfZE9~DYgc>6*b-{* z8tbL@p0Op>-Z$1q?E_=$s{L$^cZAw6FJ93@t! zRdJ3qt{mb%#yQeB+9xKTXueNPzF?o3e8E09`GS36@)b1SmnL7ZuS~vRUz>cvzA^cV zn(teaFW7e`U$E~@zFF|cv z@6{H^I2}n`IoLljPDc_)+ee}T*TnfqiuHMB+yrxLBDRIESiyUIFJ>J^oY4h)^^!?8Lt|KSU80)9DKq8!<2siuq7pq`> z7B|RziSR{Zly{bc^+MTKjpe;H$Rn`}aX&vQ%W=QpQieWwGGW`4zkA Instruction { return emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_none(.NOP)) } inst_lax_m :: #force_inline proc "contextless" (m: Memory) -> Instruction { return inst_m(.LAX, m) } emit_lax_m :: #force_inline proc(instructions: ^[dynamic]Instruction, m: Memory) { append(instructions, inst_m(.LAX, m)) } -inst_sax_nmos_m :: #force_inline proc "contextless" (m: Memory) -> Instruction { return inst_m(.SAX_NMOS, m) } -emit_sax_nmos_m :: #force_inline proc(instructions: ^[dynamic]Instruction, m: Memory) { append(instructions, inst_m(.SAX_NMOS, m)) } inst_dcp_m :: #force_inline proc "contextless" (m: Memory) -> Instruction { return inst_m(.DCP, m) } emit_dcp_m :: #force_inline proc(instructions: ^[dynamic]Instruction, m: Memory) { append(instructions, inst_m(.DCP, m)) } inst_isc_m :: #force_inline proc "contextless" (m: Memory) -> Instruction { return inst_m(.ISC, m) } @@ -309,7 +307,9 @@ emit_bbs7_zp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, zp: inst_sxy_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SXY) } emit_sxy_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_none(.SXY)) } inst_sax_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SAX) } +inst_sax_m :: #force_inline proc "contextless" (m: Memory) -> Instruction { return inst_m(.SAX, m) } emit_sax_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_none(.SAX)) } +emit_sax_m :: #force_inline proc(instructions: ^[dynamic]Instruction, m: Memory) { append(instructions, inst_m(.SAX, m)) } inst_say_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SAY) } emit_say_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_none(.SAY)) } inst_cla_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CLA) } @@ -467,8 +467,6 @@ inst_nop :: inst_nop_none emit_nop :: emit_nop_none inst_lax :: inst_lax_m emit_lax :: emit_lax_m -inst_sax_nmos :: inst_sax_nmos_m -emit_sax_nmos :: emit_sax_nmos_m inst_dcp :: inst_dcp_m emit_dcp :: emit_dcp_m inst_isc :: inst_isc_m @@ -601,8 +599,8 @@ inst_bbs7 :: inst_bbs7_zp_rel emit_bbs7 :: emit_bbs7_zp_rel inst_sxy :: inst_sxy_none emit_sxy :: emit_sxy_none -inst_sax :: inst_sax_none -emit_sax :: emit_sax_none +inst_sax :: proc{ inst_sax_none, inst_sax_m } +emit_sax :: proc{ emit_sax_none, emit_sax_m } inst_say :: inst_say_none emit_say :: emit_say_none inst_cla :: inst_cla_none diff --git a/core/rexcode/isa/mos6502/mnemonics.odin b/core/rexcode/isa/mos6502/mnemonics.odin index db88cdc11..76b0ba7c6 100644 --- a/core/rexcode/isa/mos6502/mnemonics.odin +++ b/core/rexcode/isa/mos6502/mnemonics.odin @@ -12,9 +12,10 @@ package rexcode_mos6502 // - 65C02 additions (Rockwell/WDC), incl. RMB/SMB/BBR/BBS bit ops // - HuC6280 (PC Engine) additions: block xfer, swap regs, MMR ops // -// The undocumented NMOS SAX (store A&X) collides in mnemonic with the -// HuC6280 SAX (swap A,X). To keep both, the NMOS undocumented form is -// named `SAX_NMOS` (sometimes written as AAX or SAX-undoc elsewhere). +// The undocumented NMOS SAX (store A&X) and the HuC6280 SAX (swap A,X) +// share the assembler mnemonic `sax`. They are one Mnemonic with two sets +// of forms: the NMOS one takes a memory operand and the HuC6280 one takes +// none, so the operand shape alone picks the right encoding. Mnemonic :: enum u16 { INVALID = 0, @@ -62,7 +63,6 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- LAX, // LDA + LDX (load A and X from memory) - SAX_NMOS, // store A AND X to memory (also called AAX / AXS-undoc) DCP, // DEC + CMP (memory) ISC, // INC + SBC (also ISB) RLA, // ROL + AND @@ -109,7 +109,7 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- SXY, // swap X, Y - SAX, // swap A, X (NB: distinct from undocumented NMOS SAX_NMOS) + SAX, // swap A,X (HuC6280) / store A AND X (NMOS undocumented) SAY, // swap A, Y CLA, CLX, CLY, // clear A / X / Y CSH, CSL, // CPU speed high / low (7.16 MHz vs 1.79 MHz) diff --git a/core/rexcode/isa/mos6502/printer.odin b/core/rexcode/isa/mos6502/printer.odin index 8786420e1..3c1d3dcc8 100644 --- a/core/rexcode/isa/mos6502/printer.odin +++ b/core/rexcode/isa/mos6502/printer.odin @@ -252,16 +252,8 @@ wprintln :: proc( @(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { - // SAX_NMOS prints as "sax" in conventional disassembly (the suffix is - // just our internal disambiguator vs the HuC6280 SAX). - name: string - #partial switch m { - case .SAX_NMOS: name = "SAX" - case: - n, ok := reflect.enum_name_from_value(m) - if !ok { strings.write_string(sb, ""); return } - name = n - } + name, ok := reflect.enum_name_from_value(m) + if !ok { strings.write_string(sb, ""); return } for i in 0..= 'A' && c <= 'Z' { diff --git a/core/rexcode/isa/mos6502/tablegen/encoding_table.odin b/core/rexcode/isa/mos6502/tablegen/encoding_table.odin index 84c1344a2..ee5909bfb 100644 --- a/core/rexcode/isa/mos6502/tablegen/encoding_table.odin +++ b/core/rexcode/isa/mos6502/tablegen/encoding_table.odin @@ -302,13 +302,6 @@ ENCODING_TABLE:= #partial [Mnemonic][]Encoding{ {.LAX, {.MEM_IND_Y, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0xB3, 2, .NMOS_UNDOC, {page_cross=true}}, }, - // SAX_NMOS (A & X -> mem) - .SAX_NMOS = { - {.SAX_NMOS, {.MEM_ZP, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x87, 2, .NMOS_UNDOC, {}}, - {.SAX_NMOS, {.MEM_ZP_Y, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x97, 2, .NMOS_UNDOC, {}}, - {.SAX_NMOS, {.MEM_ABS, .NONE, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE, .NONE}, 0x8F, 3, .NMOS_UNDOC, {}}, - {.SAX_NMOS, {.MEM_IND_X, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x83, 2, .NMOS_UNDOC, {}}, - }, // DCP (DEC + CMP) .DCP = { @@ -502,7 +495,16 @@ ENCODING_TABLE:= #partial [Mnemonic][]Encoding{ // Register swap / clear .SXY = { {.SXY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x02, 1, .HUC6280, {}} }, - .SAX = { {.SAX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x22, 1, .HUC6280, {}} }, + // SAX: the HuC6280 register swap (no operand) and the NMOS undocumented + // store-A&X (memory operand). One assembler mnemonic; the operand shape + // picks the form. + .SAX = { + {.SAX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x22, 1, .HUC6280, {}}, + {.SAX, {.MEM_ZP, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x87, 2, .NMOS_UNDOC, {}}, + {.SAX, {.MEM_ZP_Y, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x97, 2, .NMOS_UNDOC, {}}, + {.SAX, {.MEM_ABS, .NONE, .NONE, .NONE}, {.WORD_1_ADDR, .NONE, .NONE, .NONE}, 0x8F, 3, .NMOS_UNDOC, {}}, + {.SAX, {.MEM_IND_X, .NONE, .NONE, .NONE}, {.BYTE_1_ADDR, .NONE, .NONE, .NONE}, 0x83, 2, .NMOS_UNDOC, {}}, + }, .SAY = { {.SAY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x42, 1, .HUC6280, {}} }, .CLA = { {.CLA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x62, 1, .HUC6280, {}} }, .CLX = { {.CLX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x82, 1, .HUC6280, {}} }, diff --git a/core/rexcode/isa/mos6502/tablegen/generated/decode_tables.odin b/core/rexcode/isa/mos6502/tablegen/generated/decode_tables.odin index 2093f88d6..e6cc3551a 100644 --- a/core/rexcode/isa/mos6502/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/mos6502/tablegen/generated/decode_tables.odin @@ -176,12 +176,12 @@ DECODE_ENTRIES := [321]lib.Decode_Entry{ { .BRA, {.REL,.NONE,.NONE}, {.BYTE_1_REL,.NONE,.NONE}, 0x80, 2, .CMOS_65C02, {branch=true} }, { .STA, {.MEM_IND_X,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x81, 2, .NMOS, {} }, { .CLX, {.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE}, 0x82, 1, .HUC6280, {} }, - { .SAX_NMOS, {.MEM_IND_X,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x83, 2, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_IND_X,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x83, 2, .NMOS_UNDOC, {} }, { .TST, {.IMM_8,.MEM_ZP,.NONE}, {.BYTE_1_IMM,.BYTE_2_ADDR,.NONE}, 0x83, 3, .HUC6280, {} }, { .STY, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x84, 2, .NMOS, {} }, { .STA, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x85, 2, .NMOS, {} }, { .STX, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x86, 2, .NMOS, {} }, - { .SAX_NMOS, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x87, 2, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x87, 2, .NMOS_UNDOC, {} }, { .SMB0, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x87, 2, .CMOS_65C02, {} }, { .DEY, {.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE}, 0x88, 1, .NMOS, {} }, { .BIT, {.IMM_8,.NONE,.NONE}, {.BYTE_1_IMM,.NONE,.NONE}, 0x89, 2, .CMOS_65C02, {} }, @@ -190,7 +190,7 @@ DECODE_ENTRIES := [321]lib.Decode_Entry{ { .STY, {.MEM_ABS,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x8C, 3, .NMOS, {} }, { .STA, {.MEM_ABS,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x8D, 3, .NMOS, {} }, { .STX, {.MEM_ABS,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x8E, 3, .NMOS, {} }, - { .SAX_NMOS, {.MEM_ABS,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x8F, 3, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_ABS,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x8F, 3, .NMOS_UNDOC, {} }, { .BBS0, {.MEM_ZP,.REL,.NONE}, {.BYTE_1_ADDR,.BYTE_2_REL,.NONE}, 0x8F, 3, .CMOS_65C02, {cond_branch=true} }, { .BCC, {.REL,.NONE,.NONE}, {.BYTE_1_REL,.NONE,.NONE}, 0x90, 2, .NMOS, {cond_branch=true} }, { .STA, {.MEM_IND_Y,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x91, 2, .NMOS, {} }, @@ -201,7 +201,7 @@ DECODE_ENTRIES := [321]lib.Decode_Entry{ { .STY, {.MEM_ZP_X,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x94, 2, .NMOS, {} }, { .STA, {.MEM_ZP_X,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x95, 2, .NMOS, {} }, { .STX, {.MEM_ZP_Y,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x96, 2, .NMOS, {} }, - { .SAX_NMOS, {.MEM_ZP_Y,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x97, 2, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_ZP_Y,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x97, 2, .NMOS_UNDOC, {} }, { .SMB1, {.MEM_ZP,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE}, 0x97, 2, .CMOS_65C02, {} }, { .TYA, {.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE}, 0x98, 1, .NMOS, {} }, { .STA, {.MEM_ABS_Y,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE}, 0x99, 3, .NMOS, {} }, diff --git a/core/rexcode/isa/mos6502/tablegen/generated/encode_tables.odin b/core/rexcode/isa/mos6502/tablegen/generated/encode_tables.odin index 576d83f49..dcacfa75b 100644 --- a/core/rexcode/isa/mos6502/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/mos6502/tablegen/generated/encode_tables.odin @@ -237,11 +237,6 @@ ENCODE_FORMS := [321]lib.Encoding{ { .LAX, {.MEM_ABS_Y,.NONE,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE,.NONE}, 0xBF, 3, .NMOS_UNDOC, {page_cross=true} }, { .LAX, {.MEM_IND_X,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0xA3, 2, .NMOS_UNDOC, {} }, { .LAX, {.MEM_IND_Y,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0xB3, 2, .NMOS_UNDOC, {page_cross=true} }, - // .SAX_NMOS - { .SAX_NMOS, {.MEM_ZP,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x87, 2, .NMOS_UNDOC, {} }, - { .SAX_NMOS, {.MEM_ZP_Y,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x97, 2, .NMOS_UNDOC, {} }, - { .SAX_NMOS, {.MEM_ABS,.NONE,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE,.NONE}, 0x8F, 3, .NMOS_UNDOC, {} }, - { .SAX_NMOS, {.MEM_IND_X,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x83, 2, .NMOS_UNDOC, {} }, // .DCP { .DCP, {.MEM_ZP,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0xC7, 2, .NMOS_UNDOC, {} }, { .DCP, {.MEM_ZP_X,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0xD7, 2, .NMOS_UNDOC, {} }, @@ -433,6 +428,10 @@ ENCODE_FORMS := [321]lib.Encoding{ { .SXY, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x02, 1, .HUC6280, {} }, // .SAX { .SAX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x22, 1, .HUC6280, {} }, + { .SAX, {.MEM_ZP,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x87, 2, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_ZP_Y,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x97, 2, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_ABS,.NONE,.NONE,.NONE}, {.WORD_1_ADDR,.NONE,.NONE,.NONE}, 0x8F, 3, .NMOS_UNDOC, {} }, + { .SAX, {.MEM_IND_X,.NONE,.NONE,.NONE}, {.BYTE_1_ADDR,.NONE,.NONE,.NONE}, 0x83, 2, .NMOS_UNDOC, {} }, // .SAY { .SAY, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x42, 1, .HUC6280, {} }, // .CLA @@ -478,149 +477,148 @@ ENCODE_FORMS := [321]lib.Encoding{ @(rodata) ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ - .INVALID = { 0, 0}, - .ADC = { 0, 9}, - .AND = { 9, 9}, - .ASL = { 18, 5}, - .BIT = { 23, 5}, - .CMP = { 28, 9}, - .CPX = { 37, 3}, - .CPY = { 40, 3}, - .DEC = { 43, 5}, - .DEX = { 48, 1}, - .DEY = { 49, 1}, - .EOR = { 50, 9}, - .INC = { 59, 5}, - .INX = { 64, 1}, - .INY = { 65, 1}, - .LSR = { 66, 5}, - .ORA = { 71, 9}, - .ROL = { 80, 5}, - .ROR = { 85, 5}, - .SBC = { 90, 9}, - .BCC = { 99, 1}, - .BCS = { 100, 1}, - .BEQ = { 101, 1}, - .BMI = { 102, 1}, - .BNE = { 103, 1}, - .BPL = { 104, 1}, - .BVC = { 105, 1}, - .BVS = { 106, 1}, - .JMP = { 107, 3}, - .JSR = { 110, 1}, - .RTI = { 111, 1}, - .RTS = { 112, 1}, - .BRK = { 113, 1}, - .CLC = { 114, 1}, - .CLD = { 115, 1}, - .CLI = { 116, 1}, - .CLV = { 117, 1}, - .SEC = { 118, 1}, - .SED = { 119, 1}, - .SEI = { 120, 1}, - .LDA = { 121, 9}, - .LDX = { 130, 5}, - .LDY = { 135, 5}, - .STA = { 140, 8}, - .STX = { 148, 3}, - .STY = { 151, 3}, - .PHA = { 154, 1}, - .PHP = { 155, 1}, - .PLA = { 156, 1}, - .PLP = { 157, 1}, - .TAX = { 158, 1}, - .TAY = { 159, 1}, - .TSX = { 160, 1}, - .TXA = { 161, 1}, - .TXS = { 162, 1}, - .TYA = { 163, 1}, - .NOP = { 164, 1}, - .LAX = { 165, 6}, - .SAX_NMOS = { 171, 4}, - .DCP = { 175, 7}, - .ISC = { 182, 7}, - .RLA = { 189, 7}, - .RRA = { 196, 7}, - .SLO = { 203, 7}, - .SRE = { 210, 7}, - .ALR = { 217, 1}, - .ANC = { 218, 2}, - .ARR = { 220, 1}, - .AXS = { 221, 1}, - .LAS = { 222, 1}, - .ANE = { 223, 1}, - .LXA = { 224, 1}, - .SHA = { 225, 2}, - .SHX = { 227, 1}, - .SHY = { 228, 1}, - .TAS = { 229, 1}, - .JAM = { 230, 12}, - .USBC = { 242, 1}, - .DOP = { 243, 3}, - .TOP = { 246, 2}, - .BRA = { 248, 1}, - .INA = { 249, 1}, - .DEA = { 250, 1}, - .PHX = { 251, 1}, - .PHY = { 252, 1}, - .PLX = { 253, 1}, - .PLY = { 254, 1}, - .STZ = { 255, 4}, - .TRB = { 259, 2}, - .TSB = { 261, 2}, - .STP = { 263, 1}, - .WAI = { 264, 1}, - .RMB0 = { 265, 1}, - .RMB1 = { 266, 1}, - .RMB2 = { 267, 1}, - .RMB3 = { 268, 1}, - .RMB4 = { 269, 1}, - .RMB5 = { 270, 1}, - .RMB6 = { 271, 1}, - .RMB7 = { 272, 1}, - .SMB0 = { 273, 1}, - .SMB1 = { 274, 1}, - .SMB2 = { 275, 1}, - .SMB3 = { 276, 1}, - .SMB4 = { 277, 1}, - .SMB5 = { 278, 1}, - .SMB6 = { 279, 1}, - .SMB7 = { 280, 1}, - .BBR0 = { 281, 1}, - .BBR1 = { 282, 1}, - .BBR2 = { 283, 1}, - .BBR3 = { 284, 1}, - .BBR4 = { 285, 1}, - .BBR5 = { 286, 1}, - .BBR6 = { 287, 1}, - .BBR7 = { 288, 1}, - .BBS0 = { 289, 1}, - .BBS1 = { 290, 1}, - .BBS2 = { 291, 1}, - .BBS3 = { 292, 1}, - .BBS4 = { 293, 1}, - .BBS5 = { 294, 1}, - .BBS6 = { 295, 1}, - .BBS7 = { 296, 1}, - .SXY = { 297, 1}, - .SAX = { 298, 1}, - .SAY = { 299, 1}, - .CLA = { 300, 1}, - .CLX = { 301, 1}, - .CLY = { 302, 1}, - .CSH = { 303, 1}, - .CSL = { 304, 1}, - .SET = { 305, 1}, - .ST0 = { 306, 1}, - .ST1 = { 307, 1}, - .ST2 = { 308, 1}, - .TAM = { 309, 1}, - .TMA = { 310, 1}, - .TST = { 311, 4}, - .BSR = { 315, 1}, - .TII = { 316, 1}, - .TDD = { 317, 1}, - .TIN = { 318, 1}, - .TIA = { 319, 1}, - .TAI = { 320, 1}, + .INVALID = { 0, 0}, + .ADC = { 0, 9}, + .AND = { 9, 9}, + .ASL = { 18, 5}, + .BIT = { 23, 5}, + .CMP = { 28, 9}, + .CPX = { 37, 3}, + .CPY = { 40, 3}, + .DEC = { 43, 5}, + .DEX = { 48, 1}, + .DEY = { 49, 1}, + .EOR = { 50, 9}, + .INC = { 59, 5}, + .INX = { 64, 1}, + .INY = { 65, 1}, + .LSR = { 66, 5}, + .ORA = { 71, 9}, + .ROL = { 80, 5}, + .ROR = { 85, 5}, + .SBC = { 90, 9}, + .BCC = { 99, 1}, + .BCS = { 100, 1}, + .BEQ = { 101, 1}, + .BMI = { 102, 1}, + .BNE = { 103, 1}, + .BPL = { 104, 1}, + .BVC = { 105, 1}, + .BVS = { 106, 1}, + .JMP = { 107, 3}, + .JSR = { 110, 1}, + .RTI = { 111, 1}, + .RTS = { 112, 1}, + .BRK = { 113, 1}, + .CLC = { 114, 1}, + .CLD = { 115, 1}, + .CLI = { 116, 1}, + .CLV = { 117, 1}, + .SEC = { 118, 1}, + .SED = { 119, 1}, + .SEI = { 120, 1}, + .LDA = { 121, 9}, + .LDX = { 130, 5}, + .LDY = { 135, 5}, + .STA = { 140, 8}, + .STX = { 148, 3}, + .STY = { 151, 3}, + .PHA = { 154, 1}, + .PHP = { 155, 1}, + .PLA = { 156, 1}, + .PLP = { 157, 1}, + .TAX = { 158, 1}, + .TAY = { 159, 1}, + .TSX = { 160, 1}, + .TXA = { 161, 1}, + .TXS = { 162, 1}, + .TYA = { 163, 1}, + .NOP = { 164, 1}, + .LAX = { 165, 6}, + .DCP = { 171, 7}, + .ISC = { 178, 7}, + .RLA = { 185, 7}, + .RRA = { 192, 7}, + .SLO = { 199, 7}, + .SRE = { 206, 7}, + .ALR = { 213, 1}, + .ANC = { 214, 2}, + .ARR = { 216, 1}, + .AXS = { 217, 1}, + .LAS = { 218, 1}, + .ANE = { 219, 1}, + .LXA = { 220, 1}, + .SHA = { 221, 2}, + .SHX = { 223, 1}, + .SHY = { 224, 1}, + .TAS = { 225, 1}, + .JAM = { 226, 12}, + .USBC = { 238, 1}, + .DOP = { 239, 3}, + .TOP = { 242, 2}, + .BRA = { 244, 1}, + .INA = { 245, 1}, + .DEA = { 246, 1}, + .PHX = { 247, 1}, + .PHY = { 248, 1}, + .PLX = { 249, 1}, + .PLY = { 250, 1}, + .STZ = { 251, 4}, + .TRB = { 255, 2}, + .TSB = { 257, 2}, + .STP = { 259, 1}, + .WAI = { 260, 1}, + .RMB0 = { 261, 1}, + .RMB1 = { 262, 1}, + .RMB2 = { 263, 1}, + .RMB3 = { 264, 1}, + .RMB4 = { 265, 1}, + .RMB5 = { 266, 1}, + .RMB6 = { 267, 1}, + .RMB7 = { 268, 1}, + .SMB0 = { 269, 1}, + .SMB1 = { 270, 1}, + .SMB2 = { 271, 1}, + .SMB3 = { 272, 1}, + .SMB4 = { 273, 1}, + .SMB5 = { 274, 1}, + .SMB6 = { 275, 1}, + .SMB7 = { 276, 1}, + .BBR0 = { 277, 1}, + .BBR1 = { 278, 1}, + .BBR2 = { 279, 1}, + .BBR3 = { 280, 1}, + .BBR4 = { 281, 1}, + .BBR5 = { 282, 1}, + .BBR6 = { 283, 1}, + .BBR7 = { 284, 1}, + .BBS0 = { 285, 1}, + .BBS1 = { 286, 1}, + .BBS2 = { 287, 1}, + .BBS3 = { 288, 1}, + .BBS4 = { 289, 1}, + .BBS5 = { 290, 1}, + .BBS6 = { 291, 1}, + .BBS7 = { 292, 1}, + .SXY = { 293, 1}, + .SAX = { 294, 5}, + .SAY = { 299, 1}, + .CLA = { 300, 1}, + .CLX = { 301, 1}, + .CLY = { 302, 1}, + .CSH = { 303, 1}, + .CSL = { 304, 1}, + .SET = { 305, 1}, + .ST0 = { 306, 1}, + .ST1 = { 307, 1}, + .ST2 = { 308, 1}, + .TAM = { 309, 1}, + .TMA = { 310, 1}, + .TST = { 311, 4}, + .BSR = { 315, 1}, + .TII = { 316, 1}, + .TDD = { 317, 1}, + .TIN = { 318, 1}, + .TIA = { 319, 1}, + .TAI = { 320, 1}, } diff --git a/core/rexcode/isa/mos6502/tables/mos6502.encode_forms.bin b/core/rexcode/isa/mos6502/tables/mos6502.encode_forms.bin index 0b656fdb96b7525d9b0a262a48c7cfdb4deb3739..fe9a672e42d168af6db18021296168ca3afe7d67 100644 GIT binary patch literal 4494 zcmY+{2XItX6b9h8_w8l_8`vaEClE-0bV7%O6bL1>&>;b&m(W8GC6GXX(4(MYK~Pb# zqo86(MMXtLK}BU09aQWns8~kve`j<4VKWnkZ*TeUJ@=K3%QBWFzq5?xa#?Q3#_x2I zr$$RfUdZ`mp6&DuuhDATvRziK8m$odAZM1zGA^P<3yssWPK_2B<1$Q7!ZHlgTZ=Tk zvq;m^FtK5Jwrv^1^bC=vx0G?3-X39w=^gNYYy)d?erw|&o9ST~XUk5VJv0z$dR=^E zGrc+F=D1eq>9(|Is&`w@9w_IwF#UiN%dq&?q8&v3TA zj<#^_{Ued~d{=sEB|aDFsbu2%aIUN1&s+Gow!+#3`M8$;nA69+J|eBzD3RtBAi>9) zjYpMytl1cm)~u(D)0z!K&3vrcaMUbIZ;vSN*hbX4E!MG^yp^He<+af)Rd&q&JIm>L!63tm= zU|ck3Stin1=F2$U!x|{SN_>asQh>93Ez(N-F49?k!b2j!wfu{xTY#1LOQe{4q_G7B&Y?2197*c8sSvpsE?s|st9UD zJq@*{xF)60Qou}APxB2VlET&;;bv1dejVt2_n zJ+a4e?I!ZX4&mBOV*1_anZ)$_L}4}QPl+`BQKTm^??vP#bCx^NGnup8Bho!QA<|hM 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proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, + xlen: XLEN = .RV64, ) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { @@ -75,7 +76,7 @@ encode :: proc( for i in 0.. (word: u32, ilen: u8, ok: bool) { if inst.mnemonic == .INVALID { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) @@ -143,6 +145,9 @@ encode_one_inline :: #force_inline proc( form: ^Encoding for &f in forms { + // ZEXT_H and REV8 have one RV32 and one RV64 encoding with identical + // operands; without this the RV64 form was unreachable. + if !xlen_accepts(xlen, f.flags) { continue } if encoding_matches_inline(inst, &f) { form = &f break From b8c391e9e158d6613ec8bec9f0e7c0697399c2c6 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Wed, 26 Aug 2026 23:21:57 -0400 Subject: [PATCH 10/89] rexcode/arm32: take the encoding-shaped names down to what assemblers spell Of the 38 mnemonics still carrying an encoding-shaped name, 24 were simply names no assembler accepts, and arm32's printer emits the enum name verbatim -- so `vldrb_gather`, `vceq_z`, `vmov_q_r` and friends were the printed output. Judged against llvm-mc in every case: renamed (base name was free) BFI_BR -> BFX the V8.1M Branch Future indeXed, not a bitfield insert; llvm assembles `bfx .L, r0` to F060E001, which is exactly the bit pattern this entry held. VDOT_BF16 -> VDOT `vdot.bf16 d0, d1, d2` VMMLA_BF16 -> VMMLA `vmmla.bf16 q0, q1, q2` merged into the base mnemonic (21) VCEQ_Z/VCGE_Z/VCGT_Z/VCLE_Z/VCLT_Z -> the compare-against-zero forms are the same mnemonic with a literal `#0`: `vceq.i8 d0, d1, #0`. VCVT_FIXED, VCVT_BF16 -> VCVT `vcvt.s16.f32 s0, s0, #4` VFMA_BF16 -> VFMA VLDR{B,H,W,D}_GATHER, VSTR{B,H,W,D}_SCATTER -> VLDR*/VSTR*: an MVE gather is spelled `vldrb.u8 q0, [r0, q1]`; the vector offset is an operand, not part of the mnemonic. VMOV_Q_R, VMOV_R_Q, VMOV_2GPR_Q -> VMOV VHCADD_SAT -> VHCADD, VCMLA_MVE -> VCMLA kept, but printed properly (2) PSB_CSYNC / TSB_CSYNC are written as two tokens, `psb csync`, the same shape as arm64's DC/AT/TLBI. The underscore now prints as a space; no other arm32 mnemonic has one. Every merged form had an operand signature the matcher could already tell apart from the base's, so nothing became unreachable. 631 -> 590 mnemonics, underscore-bearing names 58 -> 14. Test indices were re-derived by matching (bits, mask) against the rebuilt table rather than by computing offsets -- every index the tests reference was found, which is a check that the merge dropped no form. Still blocked, and for the two reasons already known: VPADD_F, VRECPE_F, VRSQRTE_F -- collide with their base because the NEON data type (.f32 vs .i8/.u32) is not an operand. VMOV_LANE, VLD1-4_LANE, VST1-4_LANE -- register lists and lane indices are not modelled. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/mnemonic_builders.odin | 5232 ++++++++--------- core/rexcode/isa/arm32/mnemonics.odin | 26 +- core/rexcode/isa/arm32/printer.odin | 21 +- .../isa/arm32/tablegen/encoding_table.odin | 174 +- .../tablegen/generated/decode_tables.odin | 710 +-- .../tablegen/generated/encode_tables.odin | 1330 ++--- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 11106 -> 11106 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 35280 -> 35280 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4904 -> 4736 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 35280 -> 35280 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3360 -> 3360 bytes core/rexcode/isa/arm32/tests/smoke.odin | 38 +- 12 files changed, 3701 insertions(+), 3830 deletions(-) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index abc7db354..e2932de71 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -26,2650 +26,2598 @@ package rexcode_arm32 // Individual Typed Builder Procedures // ============================================================================= -inst_and_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_and_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_and_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_and_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_and_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_immm(dst, src, imm)) } -emit_and_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_and_r_r_rsh(dst, src, src2, shift, amount)) } -emit_and_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_and_r_r_rsr(dst, src, src2, shift, rs)) } -emit_and_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_and_rlo_rlo(dst, src)) } -inst_eor_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_eor_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_eor_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_eor_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_eor_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_immm(dst, src, imm)) } -emit_eor_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_eor_r_r_rsh(dst, src, src2, shift, amount)) } -emit_eor_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_eor_r_r_rsr(dst, src, src2, shift, rs)) } -emit_eor_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_eor_rlo_rlo(dst, src)) } -inst_sub_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_sub_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_sub_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_sub_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_sub_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_sub_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_immm(dst, src, imm)) } -emit_sub_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sub_r_r_rsh(dst, src, src2, shift, amount)) } -emit_sub_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sub_r_r_rsr(dst, src, src2, shift, rs)) } -emit_sub_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_rlo_rlo_rlo(dst, src, src2)) } -emit_sub_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sub_rlo_imm8(dst, imm)) } -inst_rsb_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_rsb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_rsb_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -emit_rsb_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsb_r_r_immm(dst, src, imm)) } -emit_rsb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsb_r_r_rsh(dst, src, src2, shift, amount)) } -emit_rsb_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsb_r_r_rsr(dst, src, src2, shift, rs)) } -inst_add_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_add_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_add_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_add_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_add_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_add_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_add_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_immm(dst, src, imm)) } -emit_add_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_add_r_r_rsh(dst, src, src2, shift, amount)) } -emit_add_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_add_r_r_rsr(dst, src, src2, shift, rs)) } -emit_add_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_rlo_rlo_rlo(dst, src, src2)) } -emit_add_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_add_rlo_imm8(dst, imm)) } -emit_add_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_add_r_r(dst, src)) } -inst_adc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_adc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_adc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_adc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_adc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adc_r_r_immm(dst, src, imm)) } -emit_adc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_adc_r_r_rsh(dst, src, src2, shift, amount)) } -emit_adc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_adc_r_r_rsr(dst, src, src2, shift, rs)) } -emit_adc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_adc_rlo_rlo(dst, src)) } -inst_sbc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_sbc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_sbc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_sbc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sbc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sbc_r_r_immm(dst, src, imm)) } -emit_sbc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sbc_r_r_rsh(dst, src, src2, shift, amount)) } -emit_sbc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sbc_r_r_rsr(dst, src, src2, shift, rs)) } -emit_sbc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sbc_rlo_rlo(dst, src)) } -inst_rsc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_rsc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_rsc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -emit_rsc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsc_r_r_immm(dst, src, imm)) } -emit_rsc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsc_r_r_rsh(dst, src, src2, shift, amount)) } -emit_rsc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsc_r_r_rsr(dst, src, src2, shift, rs)) } -inst_tst_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_tst_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_tst_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -inst_tst_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tst_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_immm(dst, imm)) } -emit_tst_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_tst_r_rsh(dst, src, shift, amount)) } -emit_tst_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_tst_r_rsr(dst, src, shift, rs)) } -emit_tst_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tst_rlo_rlo(dst, src)) } -inst_teq_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_teq_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_teq_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -emit_teq_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_teq_r_immm(dst, imm)) } -emit_teq_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_teq_r_rsh(dst, src, shift, amount)) } -emit_teq_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_teq_r_rsr(dst, src, shift, rs)) } -inst_cmp_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_cmp_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_cmp_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -inst_cmp_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_cmp_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_immm(dst, imm)) } -emit_cmp_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmp_r_rsh(dst, src, shift, amount)) } -emit_cmp_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmp_r_rsr(dst, src, shift, rs)) } -emit_cmp_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmp_rlo_rlo(dst, src)) } -inst_cmn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_cmn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_cmn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -inst_cmn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_cmn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_immm(dst, imm)) } -emit_cmn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmn_r_rsh(dst, src, shift, amount)) } -emit_cmn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmn_r_rsr(dst, src, shift, rs)) } -emit_cmn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmn_rlo_rlo(dst, src)) } -inst_orr_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_orr_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_orr_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_orr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_orr_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_immm(dst, src, imm)) } -emit_orr_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_orr_r_r_rsh(dst, src, src2, shift, amount)) } -emit_orr_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_orr_r_r_rsr(dst, src, src2, shift, rs)) } -emit_orr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_orr_rlo_rlo(dst, src)) } -inst_mov_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_mov_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_mov_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mov_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_immm(dst, imm)) } -emit_mov_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mov_r_rsh(dst, src, shift, amount)) } -emit_mov_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mov_r_rsr(dst, src, shift, rs)) } -emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } -inst_bic_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_bic_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -inst_bic_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } -inst_bic_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_bic_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bic_r_r_immm(dst, src, imm)) } -emit_bic_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_bic_r_r_rsh(dst, src, src2, shift, amount)) } -emit_bic_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_bic_r_r_rsr(dst, src, src2, shift, rs)) } -emit_bic_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bic_rlo_rlo(dst, src)) } -inst_mvn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_mvn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } -inst_mvn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } -inst_mvn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mvn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvn_r_immm(dst, imm)) } -emit_mvn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mvn_r_rsh(dst, src, shift, amount)) } -emit_mvn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mvn_r_rsr(dst, src, shift, rs)) } -emit_mvn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_rlo_rlo(dst, src)) } -inst_lsl_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_lsl_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_lsl_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_imm5(dst, src, imm)) } -emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } -emit_lsl_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsl_rlo_rlo(dst, src)) } -inst_lsr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_lsr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_lsr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_imm5(dst, src, imm)) } -emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } -emit_lsr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsr_rlo_rlo(dst, src)) } -inst_asr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_asr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_asr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_imm5(dst, src, imm)) } -emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } -emit_asr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_asr_rlo_rlo(dst, src)) } -inst_ror_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_ror_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ror_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_imm5(dst, src, imm)) } -emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } -emit_ror_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ror_rlo_rlo(dst, src)) } -inst_rrx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RRX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rrx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rrx_r_r(dst, src)) } -inst_adr_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_adr_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_adr_rlo_rel(dst, offset)) } -inst_neg_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_neg_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_rlo_rlo(dst, src)) } -inst_movw_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVW, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_movw_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movw_r_imm16(dst, imm)) } -inst_movt_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_movt_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movt_r_imm16(dst, imm)) } -inst_bfc_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_imm(imm2), {}}} } -emit_bfc_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_bfc_r_imm5_imm5w(dst, imm, imm2)) } -inst_bfi_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFI, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_bfi_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_bfi_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_sbfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_sbfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sbfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_ubfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_ubfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_ubfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } -inst_sxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb16_r_r(dst, src)) } -inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } -inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } -inst_uxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb16_r_r(dst, src)) } -inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } -inst_sxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab_r_r_r(dst, src, src2)) } -inst_sxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab16_r_r_r(dst, src, src2)) } -inst_sxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtah_r_r_r(dst, src, src2)) } -inst_uxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab_r_r_r(dst, src, src2)) } -inst_uxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab16_r_r_r(dst, src, src2)) } -inst_uxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtah_r_r_r(dst, src, src2)) } -inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } -inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } -inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } -inst_revsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REVSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_revsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_revsh_r_r(dst, src)) } -inst_sel_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sel_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sel_r_r_r(dst, src, src2)) } -inst_pkhbt_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -emit_pkhbt_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhbt_r_r_rsh(dst, src, src2, shift, amount)) } -inst_pkhtb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } -emit_pkhtb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhtb_r_r_rsh(dst, src, src2, shift, amount)) } -inst_usad8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usad8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usad8_r_r_r(dst, src, src2)) } -inst_usada8_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .USADA8, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_usada8_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_usada8_r_r_r_r(dst, src, src2, src3)) } -inst_ssat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SSAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } -emit_ssat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_ssat_r_imm4s_rsh(dst, imm, src, shift, amount)) } -inst_usat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .USAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } -emit_usat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_usat_r_imm4s_rsh(dst, imm, src, shift, amount)) } -inst_ssat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SSAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } -emit_ssat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ssat16_r_imm4s_r(dst, imm, src)) } -inst_usat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .USAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } -emit_usat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_usat16_r_imm4s_r(dst, imm, src)) } -inst_qadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd_r_r_r(dst, src, src2)) } -inst_qsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub_r_r_r(dst, src, src2)) } -inst_qdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdadd_r_r_r(dst, src, src2)) } -inst_qdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdsub_r_r_r(dst, src, src2)) } -inst_sadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd8_r_r_r(dst, src, src2)) } -inst_sadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd16_r_r_r(dst, src, src2)) } -inst_sasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sasx_r_r_r(dst, src, src2)) } -inst_ssax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssax_r_r_r(dst, src, src2)) } -inst_ssub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub8_r_r_r(dst, src, src2)) } -inst_ssub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub16_r_r_r(dst, src, src2)) } -inst_uadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd8_r_r_r(dst, src, src2)) } -inst_uadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd16_r_r_r(dst, src, src2)) } -inst_uasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uasx_r_r_r(dst, src, src2)) } -inst_usax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usax_r_r_r(dst, src, src2)) } -inst_usub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub8_r_r_r(dst, src, src2)) } -inst_usub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub16_r_r_r(dst, src, src2)) } -inst_qadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd8_r_r_r(dst, src, src2)) } -inst_qadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd16_r_r_r(dst, src, src2)) } -inst_qasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qasx_r_r_r(dst, src, src2)) } -inst_qsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsax_r_r_r(dst, src, src2)) } -inst_qsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub8_r_r_r(dst, src, src2)) } -inst_qsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub16_r_r_r(dst, src, src2)) } -inst_uqadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd8_r_r_r(dst, src, src2)) } -inst_uqadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd16_r_r_r(dst, src, src2)) } -inst_uqasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqasx_r_r_r(dst, src, src2)) } -inst_uqsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsax_r_r_r(dst, src, src2)) } -inst_uqsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub8_r_r_r(dst, src, src2)) } -inst_uqsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub16_r_r_r(dst, src, src2)) } -inst_shadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd8_r_r_r(dst, src, src2)) } -inst_shadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd16_r_r_r(dst, src, src2)) } -inst_shasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shasx_r_r_r(dst, src, src2)) } -inst_shsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsax_r_r_r(dst, src, src2)) } -inst_shsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub8_r_r_r(dst, src, src2)) } -inst_shsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub16_r_r_r(dst, src, src2)) } -inst_uhadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd8_r_r_r(dst, src, src2)) } -inst_uhadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd16_r_r_r(dst, src, src2)) } -inst_uhasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhasx_r_r_r(dst, src, src2)) } -inst_uhsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsax_r_r_r(dst, src, src2)) } -inst_uhsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub8_r_r_r(dst, src, src2)) } -inst_uhsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub16_r_r_r(dst, src, src2)) } -inst_smuad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUAD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smuad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuad_r_r_r(dst, src, src2)) } -inst_smuadx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUADX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smuadx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuadx_r_r_r(dst, src, src2)) } -inst_smusd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smusd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusd_r_r_r(dst, src, src2)) } -inst_smusdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSDX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smusdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusdx_r_r_r(dst, src, src2)) } -inst_smlad_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlad_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlad_r_r_r_r(dst, src, src2, src3)) } -inst_smladx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLADX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smladx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smladx_r_r_r_r(dst, src, src2, src3)) } -inst_smlsd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsd_r_r_r_r(dst, src, src2, src3)) } -inst_smlsdx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsdx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsdx_r_r_r_r(dst, src, src2, src3)) } -inst_smlald_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlald_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlald_r_r_r_r(dst, src, src2, src3)) } -inst_smlaldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaldx_r_r_r_r(dst, src, src2, src3)) } -inst_smlsld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsld_r_r_r_r(dst, src, src2, src3)) } -inst_smlsldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsldx_r_r_r_r(dst, src, src2, src3)) } -inst_smmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmul_r_r_r(dst, src, src2)) } -inst_smmulr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMULR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smmulr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmulr_r_r_r(dst, src, src2)) } -inst_smmla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmla_r_r_r_r(dst, src, src2, src3)) } -inst_smmlar_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLAR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmlar_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlar_r_r_r_r(dst, src, src2, src3)) } -inst_smmls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmls_r_r_r_r(dst, src, src2, src3)) } -inst_smmlsr_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLSR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmlsr_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlsr_r_r_r_r(dst, src, src2, src3)) } -inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_mul_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } -emit_mul_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mul_rlo_rlo(dst, src)) } -inst_mla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_mla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mla_r_r_r_r(dst, src, src2, src3)) } -inst_mls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_mls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mls_r_r_r_r(dst, src, src2, src3)) } -inst_umull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umull_r_r_r_r(dst, src, src2, src3)) } -inst_umlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umlal_r_r_r_r(dst, src, src2, src3)) } -inst_smull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smull_r_r_r_r(dst, src, src2, src3)) } -inst_smlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlal_r_r_r_r(dst, src, src2, src3)) } -inst_umaal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMAAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umaal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaal_r_r_r_r(dst, src, src2, src3)) } -inst_smlabb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlabb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabb_r_r_r_r(dst, src, src2, src3)) } -inst_smlabt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlabt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabt_r_r_r_r(dst, src, src2, src3)) } -inst_smlatb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlatb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatb_r_r_r_r(dst, src, src2, src3)) } -inst_smlatt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlatt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatt_r_r_r_r(dst, src, src2, src3)) } -inst_smlawb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlawb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawb_r_r_r_r(dst, src, src2, src3)) } -inst_smlawt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlawt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawt_r_r_r_r(dst, src, src2, src3)) } -inst_smulbb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulbb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbb_r_r_r(dst, src, src2)) } -inst_smulbt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulbt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbt_r_r_r(dst, src, src2)) } -inst_smultb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smultb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultb_r_r_r(dst, src, src2)) } -inst_smultt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smultt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultt_r_r_r(dst, src, src2)) } -inst_smulwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwb_r_r_r(dst, src, src2)) } -inst_smulwt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulwt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwt_r_r_r(dst, src, src2)) } -inst_smlalbb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlalbb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbb_r_r_r_r(dst, src, src2, src3)) } -inst_smlalbt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlalbt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbt_r_r_r_r(dst, src, src2, src3)) } -inst_smlaltb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaltb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltb_r_r_r_r(dst, src, src2, src3)) } -inst_smlaltt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaltt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltt_r_r_r_r(dst, src, src2, src3)) } -inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -inst_b_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -inst_b_rel_cond :: #force_inline proc "contextless" (offset: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_rel_offset(offset), op_imm(imm), {}, {}}} } -emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_b_rel(offset)) } -emit_b_rel_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, imm: i64) { append(instructions, inst_b_rel_cond(offset, imm)) } -inst_bl_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_bl_rel(offset)) } -inst_bx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_bx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bx_r(dst)) } -inst_blx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -inst_blx_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_blx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blx_r(dst)) } -emit_blx_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_blx_rel(offset)) } -inst_bxj_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXJ, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_bxj_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxj_r(dst)) } -inst_cbz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_cbz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbz_rlo_rel(dst, offset)) } -inst_cbnz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_cbnz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbnz_rlo_rel(dst, offset)) } -inst_tbb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tbb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbb_r_r(dst, src)) } -inst_tbh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tbh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbh_r_r(dst, src)) } -inst_msr_psr_immm :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } -inst_msr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} } -emit_msr_psr_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_psr_immm(imm, imm2)) } -emit_msr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_psr_r(imm, src)) } -inst_mrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_mrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_psr(dst, imm)) } -inst_cps_ifl :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .CPS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_cps_ifl :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_cps_ifl(imm)) } -inst_setend_end :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETEND, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_setend_end :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setend_end(imm)) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } -inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .YIELD, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } -inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFE, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } -inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFI, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } -inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEV, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } -inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEVL, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_dbg_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DBG, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_dbg_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dbg_hint(imm)) } -inst_hint_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_hint_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_hint(imm)) } -inst_dmb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_dmb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_barr(imm)) } -inst_dsb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_dsb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_barr(imm)) } -inst_isb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_isb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_barr(imm)) } -inst_clrex_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CLREX, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_clrex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clrex_none()) } -inst_pld_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pld_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pld_mem(dst)) } -inst_pldw_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLDW, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pldw_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pldw_mem(dst)) } -inst_pli_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pli_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pli_mem(dst)) } -inst_hlt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_hlt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_imm(imm)) } -inst_dcps1_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS1, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_dcps1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps1_none()) } -inst_dcps2_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS2, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_dcps2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps2_none()) } -inst_dcps3_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS3, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_dcps3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps3_none()) } -inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ERET, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } -inst_esb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ESB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_esb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_esb_none()) } -inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } -inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } -inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CSDB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } -inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } -inst_setpan_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETPAN, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_setpan_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setpan_hint(imm)) } -inst_svc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_svc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_imm(imm)) } -inst_bkpt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BKPT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_bkpt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bkpt_imm(imm)) } -inst_hvc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_hvc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_imm(imm)) } -inst_smc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_smc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_imm(imm)) } -inst_udf_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .UDF, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_udf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_udf_imm(imm)) } -inst_ldr_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldr_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldr_r_mem(dst, src)) } -inst_str_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_str_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_str_r_mem(dst, src)) } -inst_ldrb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrb_r_mem(dst, src)) } -inst_strb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strb_r_mem(dst, src)) } -inst_ldrh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrh_r_mem(dst, src)) } -inst_strh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strh_r_mem(dst, src)) } -inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) } -inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) } -inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) } -emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) } -inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) } -emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) } -inst_ldrt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrt_r_mem(dst, src)) } -inst_strt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strt_r_mem(dst, src)) } -inst_ldrbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrbt_r_mem(dst, src)) } -inst_strbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strbt_r_mem(dst, src)) } -inst_ldrht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrht_r_mem(dst, src)) } -inst_strht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strht_r_mem(dst, src)) } -inst_ldrsbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsbt_r_mem(dst, src)) } -inst_ldrsht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsht_r_mem(dst, src)) } -inst_lda_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_lda_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_lda_r_mem(dst, src)) } -inst_stl_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stl_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stl_r_mem(dst, src)) } -inst_ldab_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldab_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldab_r_mem(dst, src)) } -inst_stlb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stlb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlb_r_mem(dst, src)) } -inst_ldah_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldah_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldah_r_mem(dst, src)) } -inst_stlh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stlh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlh_r_mem(dst, src)) } -inst_ldrex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrex_r_mem(dst, src)) } -inst_strex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strex_r_r_mem(dst, src, src2)) } -inst_ldrexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexb_r_mem(dst, src)) } -inst_strexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexb_r_r_mem(dst, src, src2)) } -inst_ldrexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexh_r_mem(dst, src)) } -inst_strexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexh_r_r_mem(dst, src, src2)) } -inst_ldrexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_ldrexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldrexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexd_r_mem(dst, src)) } -emit_ldrexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrexd_r_r_mem(dst, src, src2)) } -inst_strexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -inst_strexd_r_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(src3)}} } -emit_strexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexd_r_r_mem(dst, src, src2)) } -emit_strexd_r_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Memory) { append(instructions, inst_strexd_r_r_r_mem(dst, src, src2, src3)) } -inst_ldaex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaex_r_mem(dst, src)) } -inst_stlex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlex_r_r_mem(dst, src, src2)) } -inst_ldaexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexb_r_mem(dst, src)) } -inst_stlexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexb_r_r_mem(dst, src, src2)) } -inst_ldaexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexh_r_mem(dst, src)) } -inst_stlexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexh_r_r_mem(dst, src, src2)) } -inst_ldaexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexd_r_mem(dst, src)) } -inst_stlexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexd_r_r_mem(dst, src, src2)) } -inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } -emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) } -inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } -emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) } -inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } -emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) } -inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } -emit_pop_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_pop_list(regs)) } -inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWP, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } -inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } -inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } -inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } -inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) } -inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_cdp2_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp2_cpn_cpop_crd_crd(dst, imm, src, src2)) } -inst_mcr_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mcr_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr_cpn_cpop_r_crd(dst, imm, src, src2)) } -inst_mcr2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mcr2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr2_cpn_cpop_r_crd(dst, imm, src, src2)) } -inst_mrc_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mrc_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc_cpn_cpop_r_crd(dst, imm, src, src2)) } -inst_mrc2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mrc2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc2_cpn_cpop_r_crd(dst, imm, src, src2)) } -inst_mcrr_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mcrr_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr_cpn_cpop_r_r(dst, imm, src, src2)) } -inst_mcrr2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mcrr2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr2_cpn_cpop_r_r(dst, imm, src, src2)) } -inst_mrrc_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mrrc_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc_cpn_cpop_r_r(dst, imm, src, src2)) } -inst_mrrc2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } -emit_mrrc2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc2_cpn_cpop_r_r(dst, imm, src, src2)) } -inst_ldc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc_cpn_crd_mem(dst, src, src2)) } -inst_ldc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc2_cpn_crd_mem(dst, src, src2)) } -inst_stc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc_cpn_crd_mem(dst, src, src2)) } -inst_stc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc2_cpn_crd_mem(dst, src, src2)) } -inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32B, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } -inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } -inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32W, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } -inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } -inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } -inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } -inst_vadd_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadd_s_s_s(dst, src, src2)) } -inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) } -inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmul_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) } -emit_vmul_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_d_d_dlane(dst, src, src2, lane)) } -inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) } -inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmla_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) } -emit_vmla_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_d_d_dlane(dst, src, src2, lane)) } -inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmls_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) } -emit_vmls_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_d_d_dlane(dst, src, src2, lane)) } -inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) } -inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmla_s_s_s(dst, src, src2)) } -inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } -inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vfma_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } -emit_vfma_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_d_d_dlane(dst, src, src2, lane)) } -inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vfms_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } -emit_vfms_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_d_d_dlane(dst, src, src2, lane)) } -inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } -inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) } -inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) } -inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vneg_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vneg_s_s(dst, src)) } -inst_vsqrt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSQRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vsqrt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsqrt_s_s(dst, src)) } -inst_vcmp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vcmp_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vcmp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmp_s_s(dst, src)) } -emit_vcmp_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmp_s(dst)) } -inst_vcmpe_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vcmpe_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vcmpe_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmpe_s_s(dst, src)) } -emit_vcmpe_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmpe_s(dst)) } -inst_vcvt_d_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvt_d_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_d_s(dst, src)) } -inst_vcvtb_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtb_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtb_s_s(dst, src)) } -inst_vcvtt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtt_s_s(dst, src)) } -inst_vcvta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvta_s_s(dst, src)) } -inst_vcvtn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtn_s_s(dst, src)) } -inst_vcvtp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtp_s_s(dst, src)) } -inst_vcvtm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtm_s_s(dst, src)) } -inst_vcvtr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtr_s_s(dst, src)) } -inst_vmov_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } -inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } -emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } -emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } -emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } -emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } -emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } -emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) } -inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } -inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } -inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } -inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) } -inst_vldm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } -emit_vldm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldm_r_slist(dst, regs)) } -inst_vstm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } -emit_vstm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstm_r_slist(dst, regs)) } -inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } -emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) } -inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } -emit_vpop_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpop_slist(regs)) } -inst_vsel_s_s_s_cond :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vsel_s_s_s_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsel_s_s_s_cond(dst, src, src2, imm)) } -inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) } -inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vminnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminnm_s_s_s(dst, src, src2)) } -inst_vrinta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrinta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrinta_s_s(dst, src)) } -inst_vrintn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintn_s_s(dst, src)) } -inst_vrintp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintp_s_s(dst, src)) } -inst_vrintm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintm_s_s(dst, src)) } -inst_vrintr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintr_s_s(dst, src)) } -inst_vrintz_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintz_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintz_s_s(dst, src)) } -inst_vrintx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintx_s_s(dst, src)) } -inst_vaddl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddl_q_d_d(dst, src, src2)) } -inst_vaddw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddw_q_q_d(dst, src, src2)) } -inst_vsubl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsubl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubl_q_d_d(dst, src, src2)) } -inst_vsubw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsubw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubw_q_q_d(dst, src, src2)) } -inst_vhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhadd_d_d_d(dst, src, src2)) } -inst_vhsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhsub_d_d_d(dst, src, src2)) } -inst_vrhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrhadd_d_d_d(dst, src, src2)) } -inst_vqadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqadd_d_d_d(dst, src, src2)) } -inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) } -inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) } -emit_vmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_q_d_dlane(dst, src, src2, lane)) } -inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) } -emit_vmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_q_d_dlane(dst, src, src2, lane)) } -inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) } -emit_vmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqdmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) } -emit_vqdmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqdmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) } -emit_vqdmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqdmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) } -emit_vqdmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_q_d_dlane(dst, src, src2, lane)) } -inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) } -emit_vqdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqrdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) } -emit_vqrdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqrdmlah_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) } -emit_vqrdmlah_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_d_d_dlane(dst, src, src2, lane)) } -inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqrdmlsh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) } -emit_vqrdmlsh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_d_d_dlane(dst, src, src2, lane)) } -inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) } -inst_vabal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabal_q_d_d(dst, src, src2)) } -inst_vabd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabd_d_d_d(dst, src, src2)) } -inst_vabdl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabdl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabdl_q_d_d(dst, src, src2)) } -inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } -inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } -inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } -inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } -inst_veor_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_veor_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veor_d_d_d(dst, src, src2)) } -inst_vbsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbsl_d_d_d(dst, src, src2)) } -inst_vbit_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbit_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbit_d_d_d(dst, src, src2)) } -inst_vbif_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIF, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbif_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbif_d_d_d(dst, src, src2)) } -inst_vmvn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vmvn_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_vmvn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmvn_d_d(dst, src)) } -emit_vmvn_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmvn_d_imm(dst, imm)) } -inst_vmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovn_d_q(dst, src)) } -inst_vqmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovn_d_q(dst, src)) } -inst_vqmovun_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovun_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovun_d_q(dst, src)) } -inst_vmovl_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovl_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovl_q_d(dst, src)) } -inst_vtst_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTST, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vtst_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtst_d_d_d(dst, src, src2)) } -inst_vceq_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vceq_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vceq_d_d_d(dst, src, src2)) } -inst_vcge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcge_d_d_d(dst, src, src2)) } -inst_vcgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcgt_d_d_d(dst, src, src2)) } -inst_vcle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcle_d_d_d(dst, src, src2)) } -inst_vclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclt_d_d_d(dst, src, src2)) } -inst_vacge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vacge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacge_d_d_d(dst, src, src2)) } -inst_vacgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vacgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacgt_d_d_d(dst, src, src2)) } -inst_vacle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vacle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacle_d_d_d(dst, src, src2)) } -inst_vaclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaclt_d_d_d(dst, src, src2)) } -inst_vmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmax_d_d_d(dst, src, src2)) } -inst_vmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmin_d_d_d(dst, src, src2)) } -inst_vpmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmax_d_d_d(dst, src, src2)) } -inst_vpmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmin_d_d_d(dst, src, src2)) } -inst_vpadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_d_d_d(dst, src, src2)) } -inst_vpaddl_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADDL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vpaddl_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpaddl_d_d(dst, src)) } -inst_vpadal_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADAL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vpadal_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpadal_d_d(dst, src)) } -inst_vrecpe_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrecpe_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_d_d(dst, src)) } -inst_vrecps_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRECPS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrecps_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrecps_d_d_d(dst, src, src2)) } -inst_vrsqrte_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrsqrte_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_d_d(dst, src)) } -inst_vrsqrts_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrsqrts_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrsqrts_d_d_d(dst, src, src2)) } -inst_vshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshl_d_d_d(dst, src, src2)) } -inst_vshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshr_d_d_imm(dst, src, imm)) } -inst_vsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsra_d_d_imm(dst, src, imm)) } -inst_vrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrshl_d_d_d(dst, src, src2)) } -inst_vrshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshr_d_d_imm(dst, src, imm)) } -inst_vrsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrsra_d_d_imm(dst, src, imm)) } -inst_vsli_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsli_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsli_d_d_imm(dst, src, imm)) } -inst_vsri_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsri_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsri_d_d_imm(dst, src, imm)) } -inst_vqshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqshl_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqshl_d_d_d(dst, src, src2)) } -emit_vqshl_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshl_d_d_imm(dst, src, imm)) } -inst_vqshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrn_d_q_imm(dst, src, imm)) } -inst_vqshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrun_d_q_imm(dst, src, imm)) } -inst_vqrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrshl_d_d_d(dst, src, src2)) } -inst_vqrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrn_d_q_imm(dst, src, imm)) } -inst_vqrshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrun_d_q_imm(dst, src, imm)) } -inst_vshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrn_d_q_imm(dst, src, imm)) } -inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) } -inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) } -emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) } -inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) } -inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) } -inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) } -inst_vpadd_f_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD_F, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpadd_f_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_f_d_d_d(dst, src, src2)) } -inst_vrecpe_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrecpe_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_f_d_d(dst, src)) } -inst_vrsqrte_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrsqrte_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_f_d_d(dst, src)) } -inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) } -inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev32_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev32_d_d(dst, src)) } -inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV64, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } -inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } -inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } -emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) } -inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } -emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) } -inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } -inst_vuzp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUZP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vuzp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vuzp_d_d(dst, src)) } -inst_vzip_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VZIP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vzip_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vzip_d_d(dst, src)) } -inst_vdup_d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vdup_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } -emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vdup_d_r(dst, src)) } -emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) } -inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } -inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } -emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) } -inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) } -emit_vld1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_dlane_mem(dst, lane, src)) } -inst_vld2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_dlist_mem(regs, src)) } -inst_vld3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_dlist_mem(regs, src)) } -inst_vld4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_dlist_mem(regs, src)) } -inst_vst1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -inst_vst1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vst1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst1_dlist_mem(regs, src)) } -emit_vst1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_dlane_mem(dst, lane, src)) } -inst_vst2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_dlist_mem(regs, src)) } -inst_vst3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_dlist_mem(regs, src)) } -inst_vst4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_dlist_mem(regs, src)) } -inst_aese_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aese_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_q_q(dst, src)) } -inst_aesd_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesd_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_q_q(dst, src)) } -inst_aesmc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesmc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_q_q(dst, src)) } -inst_aesimc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesimc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_q_q(dst, src)) } -inst_sha1h_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1H, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha1h_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_q_q(dst, src)) } -inst_sha1su0_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1su0_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_q_q_q(dst, src, src2)) } -inst_sha1su1_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha1su1_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_q_q(dst, src)) } -inst_sha1c_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1c_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_q_q_q(dst, src, src2)) } -inst_sha1m_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1m_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_q_q_q(dst, src, src2)) } -inst_sha1p_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1p_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_q_q_q(dst, src, src2)) } -inst_sha256h_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256h_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_q_q_q(dst, src, src2)) } -inst_sha256h2_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256h2_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_q_q_q(dst, src, src2)) } -inst_sha256su0_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha256su0_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_q_q(dst, src)) } -inst_sha256su1_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_q_q_q(dst, src, src2)) } -inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) } -inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vsdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) } -emit_vsdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_d_d_dlane(dst, src, src2, lane)) } -inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vudot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) } -emit_vudot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_d_d_dlane(dst, src, src2, lane)) } -inst_vcvt_bf16_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT_BF16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvt_bf16_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_bf16_d_q(dst, src)) } -inst_vdot_bf16_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vdot_bf16_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_bf16_d_d_d(dst, src, src2)) } -inst_vfma_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfma_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_bf16_q_q_q(dst, src, src2)) } -inst_vmmla_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmmla_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_bf16_q_q_q(dst, src, src2)) } -inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) } -inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } -inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -inst_vcmla_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } -emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } -emit_vcmla_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_d_d_dlane_imm(dst, src, src2, lane, imm)) } -inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) } -inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) } -inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) } -inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) } -inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vsudot_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) } -emit_vsudot_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_q_q_dlane(dst, src, src2, lane)) } -inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vusdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } -emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) } -emit_vusdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_d_d_dlane(dst, src, src2, lane)) } -inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) } -inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqneg_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqneg_q_q(dst, src)) } -inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) } -inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) } -inst_vldrb_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRB_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrb_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrb_gather_q_mem_q(dst, src, src2)) } -inst_vldrh_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRH_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrh_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrh_gather_q_mem_q(dst, src, src2)) } -inst_vldrw_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRW_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrw_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrw_gather_q_mem_q(dst, src, src2)) } -inst_vldrd_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRD_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrd_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrd_gather_q_mem_q(dst, src, src2)) } -inst_vstrb_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRB_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrb_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrb_scatter_q_mem_q(dst, src, src2)) } -inst_vstrh_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRH_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrh_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrh_scatter_q_mem_q(dst, src, src2)) } -inst_vstrw_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRW_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrw_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrw_scatter_q_mem_q(dst, src, src2)) } -inst_vstrd_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRD_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrd_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrd_scatter_q_mem_q(dst, src, src2)) } -inst_vceq_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCEQ_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vceq_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vceq_z_d_d(dst, src)) } -inst_vcge_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcge_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcge_z_d_d(dst, src)) } -inst_vcgt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcgt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcgt_z_d_d(dst, src)) } -inst_vcle_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcle_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcle_z_d_d(dst, src)) } -inst_vclt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vclt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclt_z_d_d(dst, src)) } -inst_vld2r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld2r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2r_dlist_mem(regs, src)) } -inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) } -inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) } -inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) } -inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) } -inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) } -inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) } -inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) } -inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) } -inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) } -inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) } -inst_vcvt_fixed_s_s_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCVT_FIXED, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vcvt_fixed_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcvt_fixed_s_s_imm(dst, src, imm)) } -inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } -emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) } -inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tt_r_r(dst, src)) } -inst_ttt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ttt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttt_r_r(dst, src)) } -inst_tta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tta_r_r(dst, src)) } -inst_ttat_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTAT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ttat_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttat_r_r(dst, src)) } -inst_sg_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SG, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sg_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sg_none()) } -inst_bxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } -emit_bxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxns_r(dst)) } -inst_blxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } -emit_blxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blxns_r(dst)) } -inst_pac_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PAC, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_pac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pac_none()) } -inst_pacbti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PACBTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_pacbti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacbti_none()) } -inst_aut_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AUT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_aut_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_aut_none()) } -inst_autg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AUTG, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_autg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_autg_r_r_r(dst, src, src2)) } -inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } -inst_wls_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_wls_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wls_r_rel(dst, offset)) } -inst_wlstp_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLSTP, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_wlstp_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wlstp_r_rel(dst, offset)) } -inst_dls_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLS, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_dls_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dls_r(dst)) } -inst_dlstp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLSTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_dlstp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dlstp_r(dst)) } -inst_le_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LE, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_le_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_le_rel(offset)) } -inst_letp_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LETP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) } -inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) } -inst_bf_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BF, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } -emit_bf_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bf_rel_rel(offset, offset2)) } -inst_bfi_br_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFI_BR, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } -emit_bfi_br_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bfi_br_rel_r(offset, src)) } -inst_bfl_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BFL, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } -emit_bfl_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bfl_rel_rel(offset, offset2)) } -inst_bflx_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFLX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } -emit_bflx_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bflx_rel_r(offset, src)) } -inst_bfcsel_rel_rel_imm4 :: #force_inline proc "contextless" (offset: i64, offset2: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .BFCSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), op_imm(imm), {}}} } -emit_bfcsel_rel_rel_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64, imm: i64) { append(instructions, inst_bfcsel_rel_rel_imm4(offset, offset2, imm)) } -inst_cx1_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_cx1_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) } -inst_cx1a_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_cx1a_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1a_cp_r_imm(imm, src, imm2)) } -inst_cx1d_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1D, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_cx1d_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1d_cp_r_imm(imm, src, imm2)) } -inst_cx1da_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1DA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_cx1da_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1da_cp_r_imm(imm, src, imm2)) } -inst_cx2_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_cx2_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2_cp_r_r_imm(imm, src, src2, imm2)) } -inst_cx2a_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_cx2a_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2a_cp_r_r_imm(imm, src, src2, imm2)) } -inst_cx2d_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_cx2d_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2d_cp_r_r_imm(imm, src, src2, imm2)) } -inst_cx2da_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_cx2da_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2da_cp_r_r_imm(imm, src, src2, imm2)) } -inst_cx3_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_cx3_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3_cp_r_r_r(imm, src, src2, src3)) } -inst_cx3a_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_cx3a_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3a_cp_r_r_r(imm, src, src2, src3)) } -inst_cx3d_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_cx3d_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3d_cp_r_r_r(imm, src, src2, src3)) } -inst_cx3da_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_cx3da_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3da_cp_r_r_r(imm, src, src2, src3)) } -inst_vcx1_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_vcx1_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1_cp_s_imm(imm, src, imm2)) } -inst_vcx1a_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } -emit_vcx1a_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1a_cp_s_imm(imm, src, imm2)) } -inst_vcx2_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_vcx2_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2_cp_s_s_imm(imm, src, src2, imm2)) } -inst_vcx2a_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } -emit_vcx2a_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2a_cp_s_s_imm(imm, src, src2, imm2)) } -inst_vcx3_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vcx3_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3_cp_s_s_s(imm, src, src2, src3)) } -inst_vcx3a_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vcx3a_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3a_cp_s_s_s(imm, src, src2, src3)) } -inst_vpt_vpt_cond_q_q :: #force_inline proc "contextless" (imm: i64, imm2: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), op_reg(src), op_reg(src2)}} } -emit_vpt_vpt_cond_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64, src: Register, src2: Register) { append(instructions, inst_vpt_vpt_cond_q_q(imm, imm2, src, src2)) } -inst_vpst_vpt :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .VPST, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_vpst_vpt :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_vpst_vpt(imm)) } -inst_vpsel_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpsel_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpsel_q_q_q(dst, src, src2)) } -inst_vpnot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .VPNOT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_vpnot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vpnot_none()) } -inst_vctp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vctp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vctp_r(dst)) } -inst_vaddv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vaddv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddv_r_q(dst, src)) } -inst_vaddva_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDVA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vaddva_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddva_r_q(dst, src)) } -inst_vaddlv_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddlv_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlv_r_r_q(dst, src, src2)) } -inst_vaddlva_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddlva_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlva_r_r_q(dst, src, src2)) } -inst_vmaxv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxv_r_q(dst, src)) } -inst_vmaxav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxav_r_q(dst, src)) } -inst_vminv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminv_r_q(dst, src)) } -inst_vminav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminav_r_q(dst, src)) } -inst_vmaxnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmv_r_q(dst, src)) } -inst_vmaxnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmav_r_q(dst, src)) } -inst_vminnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmv_r_q(dst, src)) } -inst_vminnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmav_r_q(dst, src)) } -inst_vabav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabav_r_q_q(dst, src, src2)) } -inst_vmladav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladav_r_q_q(dst, src, src2)) } -inst_vmladava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladava_r_q_q(dst, src, src2)) } -inst_vmladavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavx_r_q_q(dst, src, src2)) } -inst_vmladavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavax_r_q_q(dst, src, src2)) } -inst_vmlaldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldav_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldava_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavx_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavax_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsdav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdav_r_q_q(dst, src, src2)) } -inst_vmlsdava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdava_r_q_q(dst, src, src2)) } -inst_vmlsdavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavx_r_q_q(dst, src, src2)) } -inst_vmlsdavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavax_r_q_q(dst, src, src2)) } -inst_vmlsldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldav_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldava_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavx_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavax_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavh_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavha_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhx_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhax_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavh_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavha_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhx_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhax_r_r_q_q(dst, src, src2, src3)) } -inst_vmlav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlav_r_q_q(dst, src, src2)) } -inst_vmlava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlava_r_q_q(dst, src, src2)) } -inst_vmlsv_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsv_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsv_r_q_q(dst, src, src2)) } -inst_vmlsva_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsva_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsva_r_q_q(dst, src, src2)) } -inst_vcmul_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMUL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcmul_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmul_q_q_q(dst, src, src2)) } -inst_vhcadd_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhcadd_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhcadd_q_q_q(dst, src, src2)) } -inst_vbrsr_q_q_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBRSR, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbrsr_q_q_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbrsr_q_q_r(dst, src, src2)) } -inst_vshlc_q_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLC, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshlc_q_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshlc_q_r_imm5(dst, src, imm)) } -inst_vddup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vddup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vddup_q_r_imm(dst, src, imm)) } -inst_vidup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vidup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vidup_q_r_imm(dst, src, imm)) } -inst_vdwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vdwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vdwdup_q_r_r_imm(dst, src, src2, imm)) } -inst_viwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_viwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_viwdup_q_r_r_imm(dst, src, src2, imm)) } -inst_vmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnb_q_q(dst, src)) } -inst_vmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnt_q_q(dst, src)) } -inst_vqmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnb_q_q(dst, src)) } -inst_vqmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnt_q_q(dst, src)) } -inst_vqmovunb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovunb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunb_q_q(dst, src)) } -inst_vqmovunt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovunt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunt_q_q(dst, src)) } -inst_vshllb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshllb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllb_q_q_imm5(dst, src, imm)) } -inst_vshllt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshllt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllt_q_q_imm5(dst, src, imm)) } -inst_vmullb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmullb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullb_q_q_q(dst, src, src2)) } -inst_vmullt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmullt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullt_q_q_q(dst, src, src2)) } -inst_vmlalb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlalb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalb_q_q_q(dst, src, src2)) } -inst_vmlalt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlalt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalt_q_q_q(dst, src, src2)) } -inst_vmlslb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlslb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslb_q_q_q(dst, src, src2)) } -inst_vmlslt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlslt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslt_q_q_q(dst, src, src2)) } -inst_vshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnb_q_q_imm5(dst, src, imm)) } -inst_vshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnt_q_q_imm5(dst, src, imm)) } -inst_vrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnb_q_q_imm5(dst, src, imm)) } -inst_vrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnt_q_q_imm5(dst, src, imm)) } -inst_vqshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnb_q_q_imm5(dst, src, imm)) } -inst_vqshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnt_q_q_imm5(dst, src, imm)) } -inst_vqrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnb_q_q_imm5(dst, src, imm)) } -inst_vqrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnt_q_q_imm5(dst, src, imm)) } -inst_vqshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunb_q_q_imm5(dst, src, imm)) } -inst_vqshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunt_q_q_imm5(dst, src, imm)) } -inst_vqrshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunb_q_q_imm5(dst, src, imm)) } -inst_vqrshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunt_q_q_imm5(dst, src, imm)) } -inst_vmov_q_r_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_Q_R, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} } -emit_vmov_q_r_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_q_r_qlane_r(dst, lane, src)) } -inst_vmov_r_q_r_qlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV_R_Q, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_qpr_lane(src, lane), {}, {}}} } -emit_vmov_r_q_r_qlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_q_r_qlane(dst, src, lane)) } -inst_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV_2GPR_Q, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} } -emit_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_2gpr_q_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } -inst_vqdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladh_q_q_q(dst, src, src2)) } -inst_vqdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladhx_q_q_q(dst, src, src2)) } -inst_vqdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdh_q_q_q(dst, src, src2)) } -inst_vqdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdhx_q_q_q(dst, src, src2)) } -inst_vqrdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladh_q_q_q(dst, src, src2)) } -inst_vqrdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladhx_q_q_q(dst, src, src2)) } -inst_vqrdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdh_q_q_q(dst, src, src2)) } -inst_vqrdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdhx_q_q_q(dst, src, src2)) } -inst_vhcadd_sat_q_q_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VHCADD_SAT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vhcadd_sat_q_q_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vhcadd_sat_q_q_q_imm(dst, src, src2, imm)) } -inst_vcmla_mve_q_q_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA_MVE, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vcmla_mve_q_q_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_mve_q_q_q_imm(dst, src, src2, imm)) } -inst_vldrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrb_q_mem(dst, src)) } -inst_vldrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrh_q_mem(dst, src)) } -inst_vldrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrw_q_mem(dst, src)) } -inst_vldrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrd_q_mem(dst, src)) } -inst_vstrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrb_q_mem(dst, src)) } -inst_vstrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrh_q_mem(dst, src)) } -inst_vstrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrw_q_mem(dst, src)) } -inst_vstrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrd_q_mem(dst, src)) } -inst_vld20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld20_qlist_mem(regs, src)) } -inst_vld21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld21_qlist_mem(regs, src)) } -inst_vld40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld40_qlist_mem(regs, src)) } -inst_vld41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld41_qlist_mem(regs, src)) } -inst_vld42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld42_qlist_mem(regs, src)) } -inst_vld43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld43_qlist_mem(regs, src)) } -inst_vst20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst20_qlist_mem(regs, src)) } -inst_vst21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst21_qlist_mem(regs, src)) } -inst_vst40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst40_qlist_mem(regs, src)) } -inst_vst41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst41_qlist_mem(regs, src)) } -inst_vst42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst42_qlist_mem(regs, src)) } -inst_vst43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst43_qlist_mem(regs, src)) } +inst_and_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_and_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_and_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_and_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_and_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_immm(dst, src, imm)) } +emit_and_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_and_r_r_rsh(dst, src, src2, shift, amount)) } +emit_and_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_and_r_r_rsr(dst, src, src2, shift, rs)) } +emit_and_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_and_rlo_rlo(dst, src)) } +inst_eor_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_eor_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_eor_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_eor_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_eor_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_immm(dst, src, imm)) } +emit_eor_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_eor_r_r_rsh(dst, src, src2, shift, amount)) } +emit_eor_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_eor_r_r_rsr(dst, src, src2, shift, rs)) } +emit_eor_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_eor_rlo_rlo(dst, src)) } +inst_sub_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_sub_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_sub_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_sub_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_sub_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_sub_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_immm(dst, src, imm)) } +emit_sub_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sub_r_r_rsh(dst, src, src2, shift, amount)) } +emit_sub_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sub_r_r_rsr(dst, src, src2, shift, rs)) } +emit_sub_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_rlo_rlo_rlo(dst, src, src2)) } +emit_sub_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sub_rlo_imm8(dst, imm)) } +inst_rsb_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_rsb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_rsb_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +emit_rsb_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsb_r_r_immm(dst, src, imm)) } +emit_rsb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsb_r_r_rsh(dst, src, src2, shift, amount)) } +emit_rsb_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsb_r_r_rsr(dst, src, src2, shift, rs)) } +inst_add_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_add_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_add_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_add_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_add_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_add_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_add_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_immm(dst, src, imm)) } +emit_add_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_add_r_r_rsh(dst, src, src2, shift, amount)) } +emit_add_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_add_r_r_rsr(dst, src, src2, shift, rs)) } +emit_add_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_rlo_rlo_rlo(dst, src, src2)) } +emit_add_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_add_rlo_imm8(dst, imm)) } +emit_add_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_add_r_r(dst, src)) } +inst_adc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_adc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_adc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_adc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_adc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adc_r_r_immm(dst, src, imm)) } +emit_adc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_adc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_adc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_adc_r_r_rsr(dst, src, src2, shift, rs)) } +emit_adc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_adc_rlo_rlo(dst, src)) } +inst_sbc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_sbc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_sbc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_sbc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sbc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sbc_r_r_immm(dst, src, imm)) } +emit_sbc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sbc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_sbc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sbc_r_r_rsr(dst, src, src2, shift, rs)) } +emit_sbc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sbc_rlo_rlo(dst, src)) } +inst_rsc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_rsc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_rsc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +emit_rsc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsc_r_r_immm(dst, src, imm)) } +emit_rsc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_rsc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsc_r_r_rsr(dst, src, src2, shift, rs)) } +inst_tst_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_tst_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_tst_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_tst_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tst_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_immm(dst, imm)) } +emit_tst_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_tst_r_rsh(dst, src, shift, amount)) } +emit_tst_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_tst_r_rsr(dst, src, shift, rs)) } +emit_tst_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tst_rlo_rlo(dst, src)) } +inst_teq_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_teq_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_teq_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +emit_teq_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_teq_r_immm(dst, imm)) } +emit_teq_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_teq_r_rsh(dst, src, shift, amount)) } +emit_teq_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_teq_r_rsr(dst, src, shift, rs)) } +inst_cmp_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_cmp_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_cmp_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_cmp_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_cmp_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_immm(dst, imm)) } +emit_cmp_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmp_r_rsh(dst, src, shift, amount)) } +emit_cmp_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmp_r_rsr(dst, src, shift, rs)) } +emit_cmp_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmp_rlo_rlo(dst, src)) } +inst_cmn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_cmn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_cmn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_cmn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_cmn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_immm(dst, imm)) } +emit_cmn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmn_r_rsh(dst, src, shift, amount)) } +emit_cmn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmn_r_rsr(dst, src, shift, rs)) } +emit_cmn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmn_rlo_rlo(dst, src)) } +inst_orr_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_orr_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_orr_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_orr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_orr_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_immm(dst, src, imm)) } +emit_orr_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_orr_r_r_rsh(dst, src, src2, shift, amount)) } +emit_orr_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_orr_r_r_rsr(dst, src, src2, shift, rs)) } +emit_orr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_orr_rlo_rlo(dst, src)) } +inst_mov_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_mov_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_mov_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mov_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_immm(dst, imm)) } +emit_mov_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mov_r_rsh(dst, src, shift, amount)) } +emit_mov_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mov_r_rsr(dst, src, shift, rs)) } +emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } +inst_bic_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_bic_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_bic_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_bic_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_bic_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bic_r_r_immm(dst, src, imm)) } +emit_bic_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_bic_r_r_rsh(dst, src, src2, shift, amount)) } +emit_bic_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_bic_r_r_rsr(dst, src, src2, shift, rs)) } +emit_bic_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bic_rlo_rlo(dst, src)) } +inst_mvn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_mvn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_mvn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_mvn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mvn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvn_r_immm(dst, imm)) } +emit_mvn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mvn_r_rsh(dst, src, shift, amount)) } +emit_mvn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mvn_r_rsr(dst, src, shift, rs)) } +emit_mvn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_rlo_rlo(dst, src)) } +inst_lsl_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_lsl_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_lsl_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_imm5(dst, src, imm)) } +emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } +emit_lsl_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsl_rlo_rlo(dst, src)) } +inst_lsr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_lsr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_lsr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_imm5(dst, src, imm)) } +emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } +emit_lsr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsr_rlo_rlo(dst, src)) } +inst_asr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_asr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_asr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_imm5(dst, src, imm)) } +emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } +emit_asr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_asr_rlo_rlo(dst, src)) } +inst_ror_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_ror_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ror_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_imm5(dst, src, imm)) } +emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } +emit_ror_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ror_rlo_rlo(dst, src)) } +inst_rrx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RRX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rrx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rrx_r_r(dst, src)) } +inst_adr_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_adr_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_adr_rlo_rel(dst, offset)) } +inst_neg_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_neg_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_rlo_rlo(dst, src)) } +inst_movw_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVW, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_movw_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movw_r_imm16(dst, imm)) } +inst_movt_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_movt_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movt_r_imm16(dst, imm)) } +inst_bfc_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_imm(imm2), {}}} } +emit_bfc_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_bfc_r_imm5_imm5w(dst, imm, imm2)) } +inst_bfi_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFI, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_bfi_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_bfi_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_sbfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_sbfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sbfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_ubfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_ubfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_ubfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } +inst_sxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb16_r_r(dst, src)) } +inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } +inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } +inst_uxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb16_r_r(dst, src)) } +inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } +inst_sxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab_r_r_r(dst, src, src2)) } +inst_sxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab16_r_r_r(dst, src, src2)) } +inst_sxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtah_r_r_r(dst, src, src2)) } +inst_uxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab_r_r_r(dst, src, src2)) } +inst_uxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab16_r_r_r(dst, src, src2)) } +inst_uxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtah_r_r_r(dst, src, src2)) } +inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } +inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } +inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } +inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } +inst_revsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REVSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_revsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_revsh_r_r(dst, src)) } +inst_sel_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sel_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sel_r_r_r(dst, src, src2)) } +inst_pkhbt_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +emit_pkhbt_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhbt_r_r_rsh(dst, src, src2, shift, amount)) } +inst_pkhtb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +emit_pkhtb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhtb_r_r_rsh(dst, src, src2, shift, amount)) } +inst_usad8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usad8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usad8_r_r_r(dst, src, src2)) } +inst_usada8_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .USADA8, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_usada8_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_usada8_r_r_r_r(dst, src, src2, src3)) } +inst_ssat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SSAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } +emit_ssat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_ssat_r_imm4s_rsh(dst, imm, src, shift, amount)) } +inst_usat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .USAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } +emit_usat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_usat_r_imm4s_rsh(dst, imm, src, shift, amount)) } +inst_ssat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SSAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } +emit_ssat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ssat16_r_imm4s_r(dst, imm, src)) } +inst_usat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .USAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } +emit_usat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_usat16_r_imm4s_r(dst, imm, src)) } +inst_qadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd_r_r_r(dst, src, src2)) } +inst_qsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub_r_r_r(dst, src, src2)) } +inst_qdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdadd_r_r_r(dst, src, src2)) } +inst_qdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdsub_r_r_r(dst, src, src2)) } +inst_sadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd8_r_r_r(dst, src, src2)) } +inst_sadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd16_r_r_r(dst, src, src2)) } +inst_sasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sasx_r_r_r(dst, src, src2)) } +inst_ssax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssax_r_r_r(dst, src, src2)) } +inst_ssub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub8_r_r_r(dst, src, src2)) } +inst_ssub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub16_r_r_r(dst, src, src2)) } +inst_uadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd8_r_r_r(dst, src, src2)) } +inst_uadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd16_r_r_r(dst, src, src2)) } +inst_uasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uasx_r_r_r(dst, src, src2)) } +inst_usax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usax_r_r_r(dst, src, src2)) } +inst_usub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub8_r_r_r(dst, src, src2)) } +inst_usub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub16_r_r_r(dst, src, src2)) } +inst_qadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd8_r_r_r(dst, src, src2)) } +inst_qadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd16_r_r_r(dst, src, src2)) } +inst_qasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qasx_r_r_r(dst, src, src2)) } +inst_qsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsax_r_r_r(dst, src, src2)) } +inst_qsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub8_r_r_r(dst, src, src2)) } +inst_qsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub16_r_r_r(dst, src, src2)) } +inst_uqadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd8_r_r_r(dst, src, src2)) } +inst_uqadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd16_r_r_r(dst, src, src2)) } +inst_uqasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqasx_r_r_r(dst, src, src2)) } +inst_uqsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsax_r_r_r(dst, src, src2)) } +inst_uqsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub8_r_r_r(dst, src, src2)) } +inst_uqsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub16_r_r_r(dst, src, src2)) } +inst_shadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd8_r_r_r(dst, src, src2)) } +inst_shadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd16_r_r_r(dst, src, src2)) } +inst_shasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shasx_r_r_r(dst, src, src2)) } +inst_shsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsax_r_r_r(dst, src, src2)) } +inst_shsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub8_r_r_r(dst, src, src2)) } +inst_shsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub16_r_r_r(dst, src, src2)) } +inst_uhadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd8_r_r_r(dst, src, src2)) } +inst_uhadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd16_r_r_r(dst, src, src2)) } +inst_uhasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhasx_r_r_r(dst, src, src2)) } +inst_uhsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsax_r_r_r(dst, src, src2)) } +inst_uhsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub8_r_r_r(dst, src, src2)) } +inst_uhsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub16_r_r_r(dst, src, src2)) } +inst_smuad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUAD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smuad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuad_r_r_r(dst, src, src2)) } +inst_smuadx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUADX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smuadx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuadx_r_r_r(dst, src, src2)) } +inst_smusd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smusd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusd_r_r_r(dst, src, src2)) } +inst_smusdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSDX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smusdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusdx_r_r_r(dst, src, src2)) } +inst_smlad_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlad_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlad_r_r_r_r(dst, src, src2, src3)) } +inst_smladx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLADX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smladx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smladx_r_r_r_r(dst, src, src2, src3)) } +inst_smlsd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsd_r_r_r_r(dst, src, src2, src3)) } +inst_smlsdx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsdx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsdx_r_r_r_r(dst, src, src2, src3)) } +inst_smlald_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlald_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlald_r_r_r_r(dst, src, src2, src3)) } +inst_smlaldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaldx_r_r_r_r(dst, src, src2, src3)) } +inst_smlsld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsld_r_r_r_r(dst, src, src2, src3)) } +inst_smlsldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsldx_r_r_r_r(dst, src, src2, src3)) } +inst_smmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmul_r_r_r(dst, src, src2)) } +inst_smmulr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMULR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smmulr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmulr_r_r_r(dst, src, src2)) } +inst_smmla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmla_r_r_r_r(dst, src, src2, src3)) } +inst_smmlar_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLAR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmlar_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlar_r_r_r_r(dst, src, src2, src3)) } +inst_smmls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmls_r_r_r_r(dst, src, src2, src3)) } +inst_smmlsr_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLSR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmlsr_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlsr_r_r_r_r(dst, src, src2, src3)) } +inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_mul_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } +emit_mul_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mul_rlo_rlo(dst, src)) } +inst_mla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_mla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mla_r_r_r_r(dst, src, src2, src3)) } +inst_mls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_mls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mls_r_r_r_r(dst, src, src2, src3)) } +inst_umull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umull_r_r_r_r(dst, src, src2, src3)) } +inst_umlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umlal_r_r_r_r(dst, src, src2, src3)) } +inst_smull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smull_r_r_r_r(dst, src, src2, src3)) } +inst_smlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlal_r_r_r_r(dst, src, src2, src3)) } +inst_umaal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMAAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umaal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaal_r_r_r_r(dst, src, src2, src3)) } +inst_smlabb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlabb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabb_r_r_r_r(dst, src, src2, src3)) } +inst_smlabt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlabt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabt_r_r_r_r(dst, src, src2, src3)) } +inst_smlatb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlatb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatb_r_r_r_r(dst, src, src2, src3)) } +inst_smlatt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlatt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatt_r_r_r_r(dst, src, src2, src3)) } +inst_smlawb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlawb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawb_r_r_r_r(dst, src, src2, src3)) } +inst_smlawt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlawt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawt_r_r_r_r(dst, src, src2, src3)) } +inst_smulbb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulbb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbb_r_r_r(dst, src, src2)) } +inst_smulbt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulbt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbt_r_r_r(dst, src, src2)) } +inst_smultb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smultb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultb_r_r_r(dst, src, src2)) } +inst_smultt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smultt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultt_r_r_r(dst, src, src2)) } +inst_smulwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwb_r_r_r(dst, src, src2)) } +inst_smulwt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulwt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwt_r_r_r(dst, src, src2)) } +inst_smlalbb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlalbb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbb_r_r_r_r(dst, src, src2, src3)) } +inst_smlalbt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlalbt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbt_r_r_r_r(dst, src, src2, src3)) } +inst_smlaltb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaltb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltb_r_r_r_r(dst, src, src2, src3)) } +inst_smlaltt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaltt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltt_r_r_r_r(dst, src, src2, src3)) } +inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } +inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } +inst_b_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +inst_b_rel_cond :: #force_inline proc "contextless" (offset: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_rel_offset(offset), op_imm(imm), {}, {}}} } +emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_b_rel(offset)) } +emit_b_rel_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, imm: i64) { append(instructions, inst_b_rel_cond(offset, imm)) } +inst_bl_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_bl_rel(offset)) } +inst_bx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_bx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bx_r(dst)) } +inst_blx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +inst_blx_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_blx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blx_r(dst)) } +emit_blx_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_blx_rel(offset)) } +inst_bxj_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXJ, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_bxj_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxj_r(dst)) } +inst_cbz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_cbz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbz_rlo_rel(dst, offset)) } +inst_cbnz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_cbnz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbnz_rlo_rel(dst, offset)) } +inst_tbb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tbb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbb_r_r(dst, src)) } +inst_tbh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tbh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbh_r_r(dst, src)) } +inst_msr_psr_immm :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } +inst_msr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} } +emit_msr_psr_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_psr_immm(imm, imm2)) } +emit_msr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_psr_r(imm, src)) } +inst_mrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_mrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_psr(dst, imm)) } +inst_cps_ifl :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .CPS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_cps_ifl :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_cps_ifl(imm)) } +inst_setend_end :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETEND, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_setend_end :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setend_end(imm)) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } +inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .YIELD, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } +inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFE, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } +inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFI, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } +inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEV, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } +inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEVL, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } +inst_dbg_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DBG, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dbg_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dbg_hint(imm)) } +inst_hint_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hint_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_hint(imm)) } +inst_dmb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dmb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_barr(imm)) } +inst_dsb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dsb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_barr(imm)) } +inst_isb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_isb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_barr(imm)) } +inst_clrex_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CLREX, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_clrex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clrex_none()) } +inst_pld_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pld_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pld_mem(dst)) } +inst_pldw_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLDW, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pldw_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pldw_mem(dst)) } +inst_pli_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pli_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pli_mem(dst)) } +inst_hlt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hlt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_imm(imm)) } +inst_dcps1_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS1, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_dcps1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps1_none()) } +inst_dcps2_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS2, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_dcps2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps2_none()) } +inst_dcps3_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .DCPS3, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_dcps3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dcps3_none()) } +inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ERET, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } +inst_esb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ESB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_esb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_esb_none()) } +inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } +inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } +inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CSDB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } +inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } +inst_setpan_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETPAN, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_setpan_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setpan_hint(imm)) } +inst_svc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_svc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_imm(imm)) } +inst_bkpt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BKPT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_bkpt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bkpt_imm(imm)) } +inst_hvc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hvc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_imm(imm)) } +inst_smc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_smc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_imm(imm)) } +inst_udf_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .UDF, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_udf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_udf_imm(imm)) } +inst_ldr_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldr_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldr_r_mem(dst, src)) } +inst_str_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_str_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_str_r_mem(dst, src)) } +inst_ldrb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrb_r_mem(dst, src)) } +inst_strb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strb_r_mem(dst, src)) } +inst_ldrh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrh_r_mem(dst, src)) } +inst_strh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strh_r_mem(dst, src)) } +inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) } +inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) } +inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) } +emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) } +inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) } +emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) } +inst_ldrt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrt_r_mem(dst, src)) } +inst_strt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strt_r_mem(dst, src)) } +inst_ldrbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrbt_r_mem(dst, src)) } +inst_strbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strbt_r_mem(dst, src)) } +inst_ldrht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrht_r_mem(dst, src)) } +inst_strht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strht_r_mem(dst, src)) } +inst_ldrsbt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSBT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsbt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsbt_r_mem(dst, src)) } +inst_ldrsht_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSHT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsht_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsht_r_mem(dst, src)) } +inst_lda_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_lda_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_lda_r_mem(dst, src)) } +inst_stl_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stl_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stl_r_mem(dst, src)) } +inst_ldab_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldab_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldab_r_mem(dst, src)) } +inst_stlb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stlb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlb_r_mem(dst, src)) } +inst_ldah_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldah_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldah_r_mem(dst, src)) } +inst_stlh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stlh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlh_r_mem(dst, src)) } +inst_ldrex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrex_r_mem(dst, src)) } +inst_strex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strex_r_r_mem(dst, src, src2)) } +inst_ldrexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexb_r_mem(dst, src)) } +inst_strexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexb_r_r_mem(dst, src, src2)) } +inst_ldrexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexh_r_mem(dst, src)) } +inst_strexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexh_r_r_mem(dst, src, src2)) } +inst_ldrexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_ldrexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldrexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexd_r_mem(dst, src)) } +emit_ldrexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrexd_r_r_mem(dst, src, src2)) } +inst_strexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +inst_strexd_r_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(src3)}} } +emit_strexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexd_r_r_mem(dst, src, src2)) } +emit_strexd_r_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Memory) { append(instructions, inst_strexd_r_r_r_mem(dst, src, src2, src3)) } +inst_ldaex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaex_r_mem(dst, src)) } +inst_stlex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlex_r_r_mem(dst, src, src2)) } +inst_ldaexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexb_r_mem(dst, src)) } +inst_stlexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexb_r_r_mem(dst, src, src2)) } +inst_ldaexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexh_r_mem(dst, src)) } +inst_stlexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexh_r_r_mem(dst, src, src2)) } +inst_ldaexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexd_r_mem(dst, src)) } +inst_stlexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexd_r_r_mem(dst, src, src2)) } +inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) } +inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) } +inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) } +inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_pop_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_pop_list(regs)) } +inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWP, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } +inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } +inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } +inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } +inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) } +inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_cdp2_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp2_cpn_cpop_crd_crd(dst, imm, src, src2)) } +inst_mcr_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcr_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mcr2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcr2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr2_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mrc_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrc_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mrc2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrc2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc2_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mcrr_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcrr_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mcrr2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcrr2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr2_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mrrc_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrrc_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mrrc2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrrc2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc2_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_ldc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc_cpn_crd_mem(dst, src, src2)) } +inst_ldc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc2_cpn_crd_mem(dst, src, src2)) } +inst_stc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc_cpn_crd_mem(dst, src, src2)) } +inst_stc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc2_cpn_crd_mem(dst, src, src2)) } +inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32B, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } +inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } +inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32W, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } +inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } +inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } +inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } +inst_vadd_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadd_s_s_s(dst, src, src2)) } +inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) } +inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmul_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) } +emit_vmul_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_d_d_dlane(dst, src, src2, lane)) } +inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) } +inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmla_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) } +emit_vmla_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_d_d_dlane(dst, src, src2, lane)) } +inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmls_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) } +emit_vmls_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_d_d_dlane(dst, src, src2, lane)) } +inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) } +inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmla_s_s_s(dst, src, src2)) } +inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } +inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vfma_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } +emit_vfma_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_d_d_dlane(dst, src, src2, lane)) } +inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vfms_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } +emit_vfms_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_d_d_dlane(dst, src, src2, lane)) } +inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } +inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) } +inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) } +inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vneg_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vneg_s_s(dst, src)) } +inst_vsqrt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSQRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vsqrt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsqrt_s_s(dst, src)) } +inst_vcmp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vcmp_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vcmp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmp_s_s(dst, src)) } +emit_vcmp_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmp_s(dst)) } +inst_vcmpe_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vcmpe_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vcmpe_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmpe_s_s(dst, src)) } +emit_vcmpe_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmpe_s(dst)) } +inst_vcvt_d_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vcvt_s_s_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vcvt_d_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_d_s(dst, src)) } +emit_vcvt_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcvt_s_s_imm(dst, src, imm)) } +inst_vcvtb_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtb_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtb_s_s(dst, src)) } +inst_vcvtt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtt_s_s(dst, src)) } +inst_vcvta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvta_s_s(dst, src)) } +inst_vcvtn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtn_s_s(dst, src)) } +inst_vcvtp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtp_s_s(dst, src)) } +inst_vcvtm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtm_s_s(dst, src)) } +inst_vcvtr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtr_s_s(dst, src)) } +inst_vmov_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } +inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } +inst_vmov_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} } +emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } +emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } +emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } +emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } +emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } +emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) } +emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } +inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } +inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } +inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } +inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) } +inst_vldm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_vldm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldm_r_slist(dst, regs)) } +inst_vstm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_vstm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstm_r_slist(dst, regs)) } +inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) } +inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_vpop_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpop_slist(regs)) } +inst_vsel_s_s_s_cond :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vsel_s_s_s_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsel_s_s_s_cond(dst, src, src2, imm)) } +inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) } +inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vminnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminnm_s_s_s(dst, src, src2)) } +inst_vrinta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrinta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrinta_s_s(dst, src)) } +inst_vrintn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintn_s_s(dst, src)) } +inst_vrintp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintp_s_s(dst, src)) } +inst_vrintm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintm_s_s(dst, src)) } +inst_vrintr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintr_s_s(dst, src)) } +inst_vrintz_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintz_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintz_s_s(dst, src)) } +inst_vrintx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintx_s_s(dst, src)) } +inst_vaddl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddl_q_d_d(dst, src, src2)) } +inst_vaddw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddw_q_q_d(dst, src, src2)) } +inst_vsubl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsubl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubl_q_d_d(dst, src, src2)) } +inst_vsubw_q_q_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUBW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsubw_q_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsubw_q_q_d(dst, src, src2)) } +inst_vhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhadd_d_d_d(dst, src, src2)) } +inst_vhsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vhsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhsub_d_d_d(dst, src, src2)) } +inst_vrhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrhadd_d_d_d(dst, src, src2)) } +inst_vqadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqadd_d_d_d(dst, src, src2)) } +inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) } +inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) } +emit_vmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_q_d_dlane(dst, src, src2, lane)) } +inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) } +emit_vmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_q_d_dlane(dst, src, src2, lane)) } +inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) } +emit_vmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmull_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) } +emit_vqdmull_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmlal_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) } +emit_vqdmlal_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmlsl_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) } +emit_vqdmlsl_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) } +emit_vqdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_d_d_dlane(dst, src, src2, lane)) } +inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmulh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) } +emit_vqrdmulh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_d_d_dlane(dst, src, src2, lane)) } +inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmlah_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) } +emit_vqrdmlah_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_d_d_dlane(dst, src, src2, lane)) } +inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqrdmlsh_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) } +emit_vqrdmlsh_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_d_d_dlane(dst, src, src2, lane)) } +inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) } +inst_vabal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabal_q_d_d(dst, src, src2)) } +inst_vabd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabd_d_d_d(dst, src, src2)) } +inst_vabdl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABDL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabdl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabdl_q_d_d(dst, src, src2)) } +inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } +inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } +inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } +inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } +inst_veor_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_veor_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veor_d_d_d(dst, src, src2)) } +inst_vbsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbsl_d_d_d(dst, src, src2)) } +inst_vbit_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbit_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbit_d_d_d(dst, src, src2)) } +inst_vbif_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIF, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbif_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbif_d_d_d(dst, src, src2)) } +inst_vmvn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vmvn_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_vmvn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmvn_d_d(dst, src)) } +emit_vmvn_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmvn_d_imm(dst, imm)) } +inst_vmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovn_d_q(dst, src)) } +inst_vqmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovn_d_q(dst, src)) } +inst_vqmovun_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovun_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovun_d_q(dst, src)) } +inst_vmovl_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovl_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovl_q_d(dst, src)) } +inst_vtst_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTST, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vtst_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtst_d_d_d(dst, src, src2)) } +inst_vceq_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vceq_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vceq_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vceq_d_d_d(dst, src, src2)) } +emit_vceq_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vceq_d_d(dst, src)) } +inst_vcge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vcge_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcge_d_d_d(dst, src, src2)) } +emit_vcge_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcge_d_d(dst, src)) } +inst_vcgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vcgt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcgt_d_d_d(dst, src, src2)) } +emit_vcgt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcgt_d_d(dst, src)) } +inst_vcle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vcle_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcle_d_d_d(dst, src, src2)) } +emit_vcle_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcle_d_d(dst, src)) } +inst_vclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vclt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vclt_d_d_d(dst, src, src2)) } +emit_vclt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclt_d_d(dst, src)) } +inst_vacge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vacge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacge_d_d_d(dst, src, src2)) } +inst_vacgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vacgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacgt_d_d_d(dst, src, src2)) } +inst_vacle_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vacle_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacle_d_d_d(dst, src, src2)) } +inst_vaclt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACLT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaclt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaclt_d_d_d(dst, src, src2)) } +inst_vmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmax_d_d_d(dst, src, src2)) } +inst_vmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmin_d_d_d(dst, src, src2)) } +inst_vpmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmax_d_d_d(dst, src, src2)) } +inst_vpmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmin_d_d_d(dst, src, src2)) } +inst_vpadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_d_d_d(dst, src, src2)) } +inst_vpaddl_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADDL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vpaddl_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpaddl_d_d(dst, src)) } +inst_vpadal_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADAL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vpadal_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpadal_d_d(dst, src)) } +inst_vrecpe_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrecpe_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_d_d(dst, src)) } +inst_vrecps_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRECPS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrecps_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrecps_d_d_d(dst, src, src2)) } +inst_vrsqrte_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrsqrte_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_d_d(dst, src)) } +inst_vrsqrts_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrsqrts_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrsqrts_d_d_d(dst, src, src2)) } +inst_vshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshl_d_d_d(dst, src, src2)) } +inst_vshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshr_d_d_imm(dst, src, imm)) } +inst_vsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsra_d_d_imm(dst, src, imm)) } +inst_vrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrshl_d_d_d(dst, src, src2)) } +inst_vrshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshr_d_d_imm(dst, src, imm)) } +inst_vrsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrsra_d_d_imm(dst, src, imm)) } +inst_vsli_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsli_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsli_d_d_imm(dst, src, imm)) } +inst_vsri_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsri_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsri_d_d_imm(dst, src, imm)) } +inst_vqshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqshl_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqshl_d_d_d(dst, src, src2)) } +emit_vqshl_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshl_d_d_imm(dst, src, imm)) } +inst_vqshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrn_d_q_imm(dst, src, imm)) } +inst_vqshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrun_d_q_imm(dst, src, imm)) } +inst_vqrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrshl_d_d_d(dst, src, src2)) } +inst_vqrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrn_d_q_imm(dst, src, imm)) } +inst_vqrshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrun_d_q_imm(dst, src, imm)) } +inst_vshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrn_d_q_imm(dst, src, imm)) } +inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) } +inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) } +emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) } +inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) } +inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) } +inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) } +inst_vpadd_f_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD_F, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpadd_f_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_f_d_d_d(dst, src, src2)) } +inst_vrecpe_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrecpe_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_f_d_d(dst, src)) } +inst_vrsqrte_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrsqrte_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_f_d_d(dst, src)) } +inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) } +inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev32_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev32_d_d(dst, src)) } +inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV64, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } +inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } +inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } +emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } +emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) } +inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } +emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } +emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) } +inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } +inst_vuzp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUZP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vuzp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vuzp_d_d(dst, src)) } +inst_vzip_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VZIP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vzip_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vzip_d_d(dst, src)) } +inst_vdup_d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vdup_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } +emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vdup_d_r(dst, src)) } +emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) } +inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } +inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } +emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) } +inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) } +emit_vld1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_dlane_mem(dst, lane, src)) } +inst_vld2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_dlist_mem(regs, src)) } +inst_vld3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_dlist_mem(regs, src)) } +inst_vld4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_dlist_mem(regs, src)) } +inst_vst1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +inst_vst1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vst1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst1_dlist_mem(regs, src)) } +emit_vst1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_dlane_mem(dst, lane, src)) } +inst_vst2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_dlist_mem(regs, src)) } +inst_vst3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_dlist_mem(regs, src)) } +inst_vst4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_dlist_mem(regs, src)) } +inst_aese_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aese_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_q_q(dst, src)) } +inst_aesd_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesd_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_q_q(dst, src)) } +inst_aesmc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesmc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_q_q(dst, src)) } +inst_aesimc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesimc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_q_q(dst, src)) } +inst_sha1h_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1H, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha1h_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_q_q(dst, src)) } +inst_sha1su0_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1su0_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_q_q_q(dst, src, src2)) } +inst_sha1su1_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha1su1_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_q_q(dst, src)) } +inst_sha1c_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1c_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_q_q_q(dst, src, src2)) } +inst_sha1m_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1m_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_q_q_q(dst, src, src2)) } +inst_sha1p_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1p_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_q_q_q(dst, src, src2)) } +inst_sha256h_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256h_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_q_q_q(dst, src, src2)) } +inst_sha256h2_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256h2_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_q_q_q(dst, src, src2)) } +inst_sha256su0_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha256su0_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_q_q(dst, src)) } +inst_sha256su1_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_q_q_q(dst, src, src2)) } +inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) } +inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vsdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) } +emit_vsdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_d_d_dlane(dst, src, src2, lane)) } +inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vudot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) } +emit_vudot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_d_d_dlane(dst, src, src2, lane)) } +inst_vdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_d_d_d(dst, src, src2)) } +inst_vmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_q_q_q(dst, src, src2)) } +inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) } +inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } +inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +inst_vcmla_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } +emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } +emit_vcmla_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_d_d_dlane_imm(dst, src, src2, lane, imm)) } +inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) } +inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) } +inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) } +inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) } +inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vsudot_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) } +emit_vsudot_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_q_q_dlane(dst, src, src2, lane)) } +inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vusdot_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) } +emit_vusdot_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_d_d_dlane(dst, src, src2, lane)) } +inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) } +inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqneg_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqneg_q_q(dst, src)) } +inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) } +inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) } +inst_vld2r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2r_dlist_mem(regs, src)) } +inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) } +inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) } +inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) } +inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) } +inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) } +inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) } +inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) } +inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) } +inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) } +inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) } +inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } +emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) } +inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tt_r_r(dst, src)) } +inst_ttt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ttt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttt_r_r(dst, src)) } +inst_tta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tta_r_r(dst, src)) } +inst_ttat_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTAT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ttat_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttat_r_r(dst, src)) } +inst_sg_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SG, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sg_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sg_none()) } +inst_bxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } +emit_bxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxns_r(dst)) } +inst_blxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } +emit_blxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blxns_r(dst)) } +inst_pac_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PAC, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_pac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pac_none()) } +inst_pacbti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PACBTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_pacbti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacbti_none()) } +inst_aut_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AUT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_aut_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_aut_none()) } +inst_autg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AUTG, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_autg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_autg_r_r_r(dst, src, src2)) } +inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } +inst_wls_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_wls_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wls_r_rel(dst, offset)) } +inst_wlstp_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLSTP, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_wlstp_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wlstp_r_rel(dst, offset)) } +inst_dls_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLS, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_dls_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dls_r(dst)) } +inst_dlstp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLSTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_dlstp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dlstp_r(dst)) } +inst_le_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LE, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_le_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_le_rel(offset)) } +inst_letp_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LETP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) } +inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) } +inst_bf_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BF, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } +emit_bf_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bf_rel_rel(offset, offset2)) } +inst_bfx_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } +emit_bfx_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bfx_rel_r(offset, src)) } +inst_bfl_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BFL, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } +emit_bfl_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bfl_rel_rel(offset, offset2)) } +inst_bflx_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFLX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } +emit_bflx_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bflx_rel_r(offset, src)) } +inst_bfcsel_rel_rel_imm4 :: #force_inline proc "contextless" (offset: i64, offset2: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .BFCSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), op_imm(imm), {}}} } +emit_bfcsel_rel_rel_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64, imm: i64) { append(instructions, inst_bfcsel_rel_rel_imm4(offset, offset2, imm)) } +inst_cx1_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) } +inst_cx1a_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1a_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1a_cp_r_imm(imm, src, imm2)) } +inst_cx1d_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1D, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1d_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1d_cp_r_imm(imm, src, imm2)) } +inst_cx1da_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1DA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1da_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1da_cp_r_imm(imm, src, imm2)) } +inst_cx2_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2a_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2a_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2a_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2d_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2d_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2d_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2da_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2da_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2da_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx3_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3a_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3a_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3a_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3d_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3d_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3d_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3da_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3da_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3da_cp_r_r_r(imm, src, src2, src3)) } +inst_vcx1_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_vcx1_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1_cp_s_imm(imm, src, imm2)) } +inst_vcx1a_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_vcx1a_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1a_cp_s_imm(imm, src, imm2)) } +inst_vcx2_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_vcx2_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2_cp_s_s_imm(imm, src, src2, imm2)) } +inst_vcx2a_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_vcx2a_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2a_cp_s_s_imm(imm, src, src2, imm2)) } +inst_vcx3_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vcx3_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3_cp_s_s_s(imm, src, src2, src3)) } +inst_vcx3a_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vcx3a_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3a_cp_s_s_s(imm, src, src2, src3)) } +inst_vpt_vpt_cond_q_q :: #force_inline proc "contextless" (imm: i64, imm2: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), op_reg(src), op_reg(src2)}} } +emit_vpt_vpt_cond_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64, src: Register, src2: Register) { append(instructions, inst_vpt_vpt_cond_q_q(imm, imm2, src, src2)) } +inst_vpst_vpt :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .VPST, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_vpst_vpt :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_vpst_vpt(imm)) } +inst_vpsel_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpsel_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpsel_q_q_q(dst, src, src2)) } +inst_vpnot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .VPNOT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_vpnot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vpnot_none()) } +inst_vctp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vctp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vctp_r(dst)) } +inst_vaddv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vaddv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddv_r_q(dst, src)) } +inst_vaddva_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDVA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vaddva_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddva_r_q(dst, src)) } +inst_vaddlv_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddlv_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlv_r_r_q(dst, src, src2)) } +inst_vaddlva_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddlva_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlva_r_r_q(dst, src, src2)) } +inst_vmaxv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxv_r_q(dst, src)) } +inst_vmaxav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxav_r_q(dst, src)) } +inst_vminv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminv_r_q(dst, src)) } +inst_vminav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminav_r_q(dst, src)) } +inst_vmaxnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmv_r_q(dst, src)) } +inst_vmaxnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmav_r_q(dst, src)) } +inst_vminnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmv_r_q(dst, src)) } +inst_vminnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmav_r_q(dst, src)) } +inst_vabav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabav_r_q_q(dst, src, src2)) } +inst_vmladav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladav_r_q_q(dst, src, src2)) } +inst_vmladava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladava_r_q_q(dst, src, src2)) } +inst_vmladavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavx_r_q_q(dst, src, src2)) } +inst_vmladavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavax_r_q_q(dst, src, src2)) } +inst_vmlaldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldav_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldava_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavx_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavax_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsdav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdav_r_q_q(dst, src, src2)) } +inst_vmlsdava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdava_r_q_q(dst, src, src2)) } +inst_vmlsdavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavx_r_q_q(dst, src, src2)) } +inst_vmlsdavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavax_r_q_q(dst, src, src2)) } +inst_vmlsldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldav_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldava_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavx_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavax_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavh_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavha_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhx_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhax_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavh_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavha_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhx_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhax_r_r_q_q(dst, src, src2, src3)) } +inst_vmlav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlav_r_q_q(dst, src, src2)) } +inst_vmlava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlava_r_q_q(dst, src, src2)) } +inst_vmlsv_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsv_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsv_r_q_q(dst, src, src2)) } +inst_vmlsva_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsva_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsva_r_q_q(dst, src, src2)) } +inst_vcmul_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMUL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vcmul_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmul_q_q_q(dst, src, src2)) } +inst_vhcadd_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vhcadd_q_q_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vhcadd_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhcadd_q_q_q(dst, src, src2)) } +emit_vhcadd_q_q_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vhcadd_q_q_q_imm(dst, src, src2, imm)) } +inst_vbrsr_q_q_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBRSR, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbrsr_q_q_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbrsr_q_q_r(dst, src, src2)) } +inst_vshlc_q_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLC, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshlc_q_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshlc_q_r_imm5(dst, src, imm)) } +inst_vddup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vddup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vddup_q_r_imm(dst, src, imm)) } +inst_vidup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vidup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vidup_q_r_imm(dst, src, imm)) } +inst_vdwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vdwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vdwdup_q_r_r_imm(dst, src, src2, imm)) } +inst_viwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_viwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_viwdup_q_r_r_imm(dst, src, src2, imm)) } +inst_vmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnb_q_q(dst, src)) } +inst_vmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnt_q_q(dst, src)) } +inst_vqmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnb_q_q(dst, src)) } +inst_vqmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnt_q_q(dst, src)) } +inst_vqmovunb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovunb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunb_q_q(dst, src)) } +inst_vqmovunt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovunt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunt_q_q(dst, src)) } +inst_vshllb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshllb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllb_q_q_imm5(dst, src, imm)) } +inst_vshllt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshllt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllt_q_q_imm5(dst, src, imm)) } +inst_vmullb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmullb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullb_q_q_q(dst, src, src2)) } +inst_vmullt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmullt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullt_q_q_q(dst, src, src2)) } +inst_vmlalb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlalb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalb_q_q_q(dst, src, src2)) } +inst_vmlalt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlalt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalt_q_q_q(dst, src, src2)) } +inst_vmlslb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlslb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslb_q_q_q(dst, src, src2)) } +inst_vmlslt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlslt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslt_q_q_q(dst, src, src2)) } +inst_vshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnb_q_q_imm5(dst, src, imm)) } +inst_vshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnt_q_q_imm5(dst, src, imm)) } +inst_vrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnb_q_q_imm5(dst, src, imm)) } +inst_vrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnt_q_q_imm5(dst, src, imm)) } +inst_vqshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnb_q_q_imm5(dst, src, imm)) } +inst_vqshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnt_q_q_imm5(dst, src, imm)) } +inst_vqrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnb_q_q_imm5(dst, src, imm)) } +inst_vqrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnt_q_q_imm5(dst, src, imm)) } +inst_vqshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunb_q_q_imm5(dst, src, imm)) } +inst_vqshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunt_q_q_imm5(dst, src, imm)) } +inst_vqrshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunb_q_q_imm5(dst, src, imm)) } +inst_vqrshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunt_q_q_imm5(dst, src, imm)) } +inst_vqdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladh_q_q_q(dst, src, src2)) } +inst_vqdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladhx_q_q_q(dst, src, src2)) } +inst_vqdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdh_q_q_q(dst, src, src2)) } +inst_vqdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdhx_q_q_q(dst, src, src2)) } +inst_vqrdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladh_q_q_q(dst, src, src2)) } +inst_vqrdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladhx_q_q_q(dst, src, src2)) } +inst_vqrdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdh_q_q_q(dst, src, src2)) } +inst_vqrdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdhx_q_q_q(dst, src, src2)) } +inst_vldrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vldrb_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrb_q_mem(dst, src)) } +emit_vldrb_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrb_q_mem_q(dst, src, src2)) } +inst_vldrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vldrh_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrh_q_mem(dst, src)) } +emit_vldrh_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrh_q_mem_q(dst, src, src2)) } +inst_vldrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vldrw_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrw_q_mem(dst, src)) } +emit_vldrw_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrw_q_mem_q(dst, src, src2)) } +inst_vldrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vldrd_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrd_q_mem(dst, src)) } +emit_vldrd_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrd_q_mem_q(dst, src, src2)) } +inst_vstrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vstrb_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrb_q_mem(dst, src)) } +emit_vstrb_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrb_q_mem_q(dst, src, src2)) } +inst_vstrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vstrh_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrh_q_mem(dst, src)) } +emit_vstrh_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrh_q_mem_q(dst, src, src2)) } +inst_vstrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vstrw_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrw_q_mem(dst, src)) } +emit_vstrw_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrw_q_mem_q(dst, src, src2)) } +inst_vstrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_vstrd_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrd_q_mem(dst, src)) } +emit_vstrd_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrd_q_mem_q(dst, src, src2)) } +inst_vld20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld20_qlist_mem(regs, src)) } +inst_vld21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld21_qlist_mem(regs, src)) } +inst_vld40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld40_qlist_mem(regs, src)) } +inst_vld41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld41_qlist_mem(regs, src)) } +inst_vld42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld42_qlist_mem(regs, src)) } +inst_vld43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld43_qlist_mem(regs, src)) } +inst_vst20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst20_qlist_mem(regs, src)) } +inst_vst21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst21_qlist_mem(regs, src)) } +inst_vst40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst40_qlist_mem(regs, src)) } +inst_vst41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst41_qlist_mem(regs, src)) } +inst_vst42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst42_qlist_mem(regs, src)) } +inst_vst43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst43_qlist_mem(regs, src)) } // ============================================================================= // Overload Groups // ============================================================================= -inst_and :: proc{ inst_and_r_r_immm, inst_and_r_r_rsh, inst_and_r_r_rsr, inst_and_rlo_rlo } -emit_and :: proc{ emit_and_r_r_immm, emit_and_r_r_rsh, emit_and_r_r_rsr, emit_and_rlo_rlo } -inst_eor :: proc{ inst_eor_r_r_immm, inst_eor_r_r_rsh, inst_eor_r_r_rsr, inst_eor_rlo_rlo } -emit_eor :: proc{ emit_eor_r_r_immm, emit_eor_r_r_rsh, emit_eor_r_r_rsr, emit_eor_rlo_rlo } -inst_sub :: proc{ inst_sub_r_r_immm, inst_sub_r_r_rsh, inst_sub_r_r_rsr, inst_sub_rlo_rlo_rlo, inst_sub_rlo_imm8 } -emit_sub :: proc{ emit_sub_r_r_immm, emit_sub_r_r_rsh, emit_sub_r_r_rsr, emit_sub_rlo_rlo_rlo, emit_sub_rlo_imm8 } -inst_rsb :: proc{ inst_rsb_r_r_immm, inst_rsb_r_r_rsh, inst_rsb_r_r_rsr } -emit_rsb :: proc{ emit_rsb_r_r_immm, emit_rsb_r_r_rsh, emit_rsb_r_r_rsr } -inst_add :: proc{ inst_add_r_r_immm, inst_add_r_r_rsh, inst_add_r_r_rsr, inst_add_rlo_rlo_rlo, inst_add_rlo_imm8, inst_add_r_r } -emit_add :: proc{ emit_add_r_r_immm, emit_add_r_r_rsh, emit_add_r_r_rsr, emit_add_rlo_rlo_rlo, emit_add_rlo_imm8, emit_add_r_r } -inst_adc :: proc{ inst_adc_r_r_immm, inst_adc_r_r_rsh, inst_adc_r_r_rsr, inst_adc_rlo_rlo } -emit_adc :: proc{ emit_adc_r_r_immm, emit_adc_r_r_rsh, emit_adc_r_r_rsr, emit_adc_rlo_rlo } -inst_sbc :: proc{ inst_sbc_r_r_immm, inst_sbc_r_r_rsh, inst_sbc_r_r_rsr, inst_sbc_rlo_rlo } -emit_sbc :: proc{ emit_sbc_r_r_immm, emit_sbc_r_r_rsh, emit_sbc_r_r_rsr, emit_sbc_rlo_rlo } -inst_rsc :: proc{ inst_rsc_r_r_immm, inst_rsc_r_r_rsh, inst_rsc_r_r_rsr } -emit_rsc :: proc{ emit_rsc_r_r_immm, emit_rsc_r_r_rsh, emit_rsc_r_r_rsr } -inst_tst :: proc{ inst_tst_r_immm, inst_tst_r_rsh, inst_tst_r_rsr, inst_tst_rlo_rlo } -emit_tst :: proc{ emit_tst_r_immm, emit_tst_r_rsh, emit_tst_r_rsr, emit_tst_rlo_rlo } -inst_teq :: proc{ inst_teq_r_immm, inst_teq_r_rsh, inst_teq_r_rsr } -emit_teq :: proc{ emit_teq_r_immm, emit_teq_r_rsh, emit_teq_r_rsr } -inst_cmp :: proc{ inst_cmp_r_immm, inst_cmp_r_rsh, inst_cmp_r_rsr, inst_cmp_rlo_rlo } -emit_cmp :: proc{ emit_cmp_r_immm, emit_cmp_r_rsh, emit_cmp_r_rsr, emit_cmp_rlo_rlo } -inst_cmn :: proc{ inst_cmn_r_immm, inst_cmn_r_rsh, inst_cmn_r_rsr, inst_cmn_rlo_rlo } -emit_cmn :: proc{ emit_cmn_r_immm, emit_cmn_r_rsh, emit_cmn_r_rsr, emit_cmn_rlo_rlo } -inst_orr :: proc{ inst_orr_r_r_immm, inst_orr_r_r_rsh, inst_orr_r_r_rsr, inst_orr_rlo_rlo } -emit_orr :: proc{ emit_orr_r_r_immm, emit_orr_r_r_rsh, emit_orr_r_r_rsr, emit_orr_rlo_rlo } -inst_mov :: proc{ inst_mov_r_immm, inst_mov_r_rsh, inst_mov_r_rsr, inst_mov_r_r } -emit_mov :: proc{ emit_mov_r_immm, emit_mov_r_rsh, emit_mov_r_rsr, emit_mov_r_r } -inst_bic :: proc{ inst_bic_r_r_immm, inst_bic_r_r_rsh, inst_bic_r_r_rsr, inst_bic_rlo_rlo } -emit_bic :: proc{ emit_bic_r_r_immm, emit_bic_r_r_rsh, emit_bic_r_r_rsr, emit_bic_rlo_rlo } -inst_mvn :: proc{ inst_mvn_r_immm, inst_mvn_r_rsh, inst_mvn_r_rsr, inst_mvn_rlo_rlo } -emit_mvn :: proc{ emit_mvn_r_immm, emit_mvn_r_rsh, emit_mvn_r_rsr, emit_mvn_rlo_rlo } -inst_lsl :: proc{ inst_lsl_r_r_imm5, inst_lsl_r_r_r, inst_lsl_rlo_rlo } -emit_lsl :: proc{ emit_lsl_r_r_imm5, emit_lsl_r_r_r, emit_lsl_rlo_rlo } -inst_lsr :: proc{ inst_lsr_r_r_imm5, inst_lsr_r_r_r, inst_lsr_rlo_rlo } -emit_lsr :: proc{ emit_lsr_r_r_imm5, emit_lsr_r_r_r, emit_lsr_rlo_rlo } -inst_asr :: proc{ inst_asr_r_r_imm5, inst_asr_r_r_r, inst_asr_rlo_rlo } -emit_asr :: proc{ emit_asr_r_r_imm5, emit_asr_r_r_r, emit_asr_rlo_rlo } -inst_ror :: proc{ inst_ror_r_r_imm5, inst_ror_r_r_r, inst_ror_rlo_rlo } -emit_ror :: proc{ emit_ror_r_r_imm5, emit_ror_r_r_r, emit_ror_rlo_rlo } -inst_rrx :: inst_rrx_r_r -emit_rrx :: emit_rrx_r_r -inst_adr :: inst_adr_rlo_rel -emit_adr :: emit_adr_rlo_rel -inst_neg :: inst_neg_rlo_rlo -emit_neg :: emit_neg_rlo_rlo -inst_movw :: inst_movw_r_imm16 -emit_movw :: emit_movw_r_imm16 -inst_movt :: inst_movt_r_imm16 -emit_movt :: emit_movt_r_imm16 -inst_bfc :: inst_bfc_r_imm5_imm5w -emit_bfc :: emit_bfc_r_imm5_imm5w -inst_bfi :: inst_bfi_r_r_imm5_imm5w -emit_bfi :: emit_bfi_r_r_imm5_imm5w -inst_sbfx :: inst_sbfx_r_r_imm5_imm5w -emit_sbfx :: emit_sbfx_r_r_imm5_imm5w -inst_ubfx :: inst_ubfx_r_r_imm5_imm5w -emit_ubfx :: emit_ubfx_r_r_imm5_imm5w -inst_sxtb :: inst_sxtb_r_r -emit_sxtb :: emit_sxtb_r_r -inst_sxtb16 :: inst_sxtb16_r_r -emit_sxtb16 :: emit_sxtb16_r_r -inst_sxth :: inst_sxth_r_r -emit_sxth :: emit_sxth_r_r -inst_uxtb :: inst_uxtb_r_r -emit_uxtb :: emit_uxtb_r_r -inst_uxtb16 :: inst_uxtb16_r_r -emit_uxtb16 :: emit_uxtb16_r_r -inst_uxth :: inst_uxth_r_r -emit_uxth :: emit_uxth_r_r -inst_sxtab :: inst_sxtab_r_r_r -emit_sxtab :: emit_sxtab_r_r_r -inst_sxtab16 :: inst_sxtab16_r_r_r -emit_sxtab16 :: emit_sxtab16_r_r_r -inst_sxtah :: inst_sxtah_r_r_r -emit_sxtah :: emit_sxtah_r_r_r -inst_uxtab :: inst_uxtab_r_r_r -emit_uxtab :: emit_uxtab_r_r_r -inst_uxtab16 :: inst_uxtab16_r_r_r -emit_uxtab16 :: emit_uxtab16_r_r_r -inst_uxtah :: inst_uxtah_r_r_r -emit_uxtah :: emit_uxtah_r_r_r -inst_clz :: inst_clz_r_r -emit_clz :: emit_clz_r_r -inst_rbit :: inst_rbit_r_r -emit_rbit :: emit_rbit_r_r -inst_rev :: inst_rev_r_r -emit_rev :: emit_rev_r_r -inst_rev16 :: inst_rev16_r_r -emit_rev16 :: emit_rev16_r_r -inst_revsh :: inst_revsh_r_r -emit_revsh :: emit_revsh_r_r -inst_sel :: inst_sel_r_r_r -emit_sel :: emit_sel_r_r_r -inst_pkhbt :: inst_pkhbt_r_r_rsh -emit_pkhbt :: emit_pkhbt_r_r_rsh -inst_pkhtb :: inst_pkhtb_r_r_rsh -emit_pkhtb :: emit_pkhtb_r_r_rsh -inst_usad8 :: inst_usad8_r_r_r -emit_usad8 :: emit_usad8_r_r_r -inst_usada8 :: inst_usada8_r_r_r_r -emit_usada8 :: emit_usada8_r_r_r_r -inst_ssat :: inst_ssat_r_imm4s_rsh -emit_ssat :: emit_ssat_r_imm4s_rsh -inst_usat :: inst_usat_r_imm4s_rsh -emit_usat :: emit_usat_r_imm4s_rsh -inst_ssat16 :: inst_ssat16_r_imm4s_r -emit_ssat16 :: emit_ssat16_r_imm4s_r -inst_usat16 :: inst_usat16_r_imm4s_r -emit_usat16 :: emit_usat16_r_imm4s_r -inst_qadd :: inst_qadd_r_r_r -emit_qadd :: emit_qadd_r_r_r -inst_qsub :: inst_qsub_r_r_r -emit_qsub :: emit_qsub_r_r_r -inst_qdadd :: inst_qdadd_r_r_r -emit_qdadd :: emit_qdadd_r_r_r -inst_qdsub :: inst_qdsub_r_r_r -emit_qdsub :: emit_qdsub_r_r_r -inst_sadd8 :: inst_sadd8_r_r_r -emit_sadd8 :: emit_sadd8_r_r_r -inst_sadd16 :: inst_sadd16_r_r_r -emit_sadd16 :: emit_sadd16_r_r_r -inst_sasx :: inst_sasx_r_r_r -emit_sasx :: emit_sasx_r_r_r -inst_ssax :: inst_ssax_r_r_r -emit_ssax :: emit_ssax_r_r_r -inst_ssub8 :: inst_ssub8_r_r_r -emit_ssub8 :: emit_ssub8_r_r_r -inst_ssub16 :: inst_ssub16_r_r_r -emit_ssub16 :: emit_ssub16_r_r_r -inst_uadd8 :: inst_uadd8_r_r_r -emit_uadd8 :: emit_uadd8_r_r_r -inst_uadd16 :: inst_uadd16_r_r_r -emit_uadd16 :: emit_uadd16_r_r_r -inst_uasx :: inst_uasx_r_r_r -emit_uasx :: emit_uasx_r_r_r -inst_usax :: inst_usax_r_r_r -emit_usax :: emit_usax_r_r_r -inst_usub8 :: inst_usub8_r_r_r -emit_usub8 :: emit_usub8_r_r_r -inst_usub16 :: inst_usub16_r_r_r -emit_usub16 :: emit_usub16_r_r_r -inst_qadd8 :: inst_qadd8_r_r_r -emit_qadd8 :: emit_qadd8_r_r_r -inst_qadd16 :: inst_qadd16_r_r_r -emit_qadd16 :: emit_qadd16_r_r_r -inst_qasx :: inst_qasx_r_r_r -emit_qasx :: emit_qasx_r_r_r -inst_qsax :: inst_qsax_r_r_r -emit_qsax :: emit_qsax_r_r_r -inst_qsub8 :: inst_qsub8_r_r_r -emit_qsub8 :: emit_qsub8_r_r_r -inst_qsub16 :: inst_qsub16_r_r_r -emit_qsub16 :: emit_qsub16_r_r_r -inst_uqadd8 :: inst_uqadd8_r_r_r -emit_uqadd8 :: emit_uqadd8_r_r_r -inst_uqadd16 :: inst_uqadd16_r_r_r -emit_uqadd16 :: emit_uqadd16_r_r_r -inst_uqasx :: inst_uqasx_r_r_r -emit_uqasx :: emit_uqasx_r_r_r -inst_uqsax :: inst_uqsax_r_r_r -emit_uqsax :: emit_uqsax_r_r_r -inst_uqsub8 :: inst_uqsub8_r_r_r -emit_uqsub8 :: emit_uqsub8_r_r_r -inst_uqsub16 :: inst_uqsub16_r_r_r -emit_uqsub16 :: emit_uqsub16_r_r_r -inst_shadd8 :: inst_shadd8_r_r_r -emit_shadd8 :: emit_shadd8_r_r_r -inst_shadd16 :: inst_shadd16_r_r_r -emit_shadd16 :: emit_shadd16_r_r_r -inst_shasx :: inst_shasx_r_r_r -emit_shasx :: emit_shasx_r_r_r -inst_shsax :: inst_shsax_r_r_r -emit_shsax :: emit_shsax_r_r_r -inst_shsub8 :: inst_shsub8_r_r_r -emit_shsub8 :: emit_shsub8_r_r_r -inst_shsub16 :: inst_shsub16_r_r_r -emit_shsub16 :: emit_shsub16_r_r_r -inst_uhadd8 :: inst_uhadd8_r_r_r -emit_uhadd8 :: emit_uhadd8_r_r_r -inst_uhadd16 :: inst_uhadd16_r_r_r -emit_uhadd16 :: emit_uhadd16_r_r_r -inst_uhasx :: inst_uhasx_r_r_r -emit_uhasx :: emit_uhasx_r_r_r -inst_uhsax :: inst_uhsax_r_r_r -emit_uhsax :: emit_uhsax_r_r_r -inst_uhsub8 :: inst_uhsub8_r_r_r -emit_uhsub8 :: emit_uhsub8_r_r_r -inst_uhsub16 :: inst_uhsub16_r_r_r -emit_uhsub16 :: emit_uhsub16_r_r_r -inst_smuad :: inst_smuad_r_r_r -emit_smuad :: emit_smuad_r_r_r -inst_smuadx :: inst_smuadx_r_r_r -emit_smuadx :: emit_smuadx_r_r_r -inst_smusd :: inst_smusd_r_r_r -emit_smusd :: emit_smusd_r_r_r -inst_smusdx :: inst_smusdx_r_r_r -emit_smusdx :: emit_smusdx_r_r_r -inst_smlad :: inst_smlad_r_r_r_r -emit_smlad :: emit_smlad_r_r_r_r -inst_smladx :: inst_smladx_r_r_r_r -emit_smladx :: emit_smladx_r_r_r_r -inst_smlsd :: inst_smlsd_r_r_r_r -emit_smlsd :: emit_smlsd_r_r_r_r -inst_smlsdx :: inst_smlsdx_r_r_r_r -emit_smlsdx :: emit_smlsdx_r_r_r_r -inst_smlald :: inst_smlald_r_r_r_r -emit_smlald :: emit_smlald_r_r_r_r -inst_smlaldx :: inst_smlaldx_r_r_r_r -emit_smlaldx :: emit_smlaldx_r_r_r_r -inst_smlsld :: inst_smlsld_r_r_r_r -emit_smlsld :: emit_smlsld_r_r_r_r -inst_smlsldx :: inst_smlsldx_r_r_r_r -emit_smlsldx :: emit_smlsldx_r_r_r_r -inst_smmul :: inst_smmul_r_r_r -emit_smmul :: emit_smmul_r_r_r -inst_smmulr :: inst_smmulr_r_r_r -emit_smmulr :: emit_smmulr_r_r_r -inst_smmla :: inst_smmla_r_r_r_r -emit_smmla :: emit_smmla_r_r_r_r -inst_smmlar :: inst_smmlar_r_r_r_r -emit_smmlar :: emit_smmlar_r_r_r_r -inst_smmls :: inst_smmls_r_r_r_r -emit_smmls :: emit_smmls_r_r_r_r -inst_smmlsr :: inst_smmlsr_r_r_r_r -emit_smmlsr :: emit_smmlsr_r_r_r_r -inst_mul :: proc{ inst_mul_r_r_r, inst_mul_rlo_rlo } -emit_mul :: proc{ emit_mul_r_r_r, emit_mul_rlo_rlo } -inst_mla :: inst_mla_r_r_r_r -emit_mla :: emit_mla_r_r_r_r -inst_mls :: inst_mls_r_r_r_r -emit_mls :: emit_mls_r_r_r_r -inst_umull :: inst_umull_r_r_r_r -emit_umull :: emit_umull_r_r_r_r -inst_umlal :: inst_umlal_r_r_r_r -emit_umlal :: emit_umlal_r_r_r_r -inst_smull :: inst_smull_r_r_r_r -emit_smull :: emit_smull_r_r_r_r -inst_smlal :: inst_smlal_r_r_r_r -emit_smlal :: emit_smlal_r_r_r_r -inst_umaal :: inst_umaal_r_r_r_r -emit_umaal :: emit_umaal_r_r_r_r -inst_smlabb :: inst_smlabb_r_r_r_r -emit_smlabb :: emit_smlabb_r_r_r_r -inst_smlabt :: inst_smlabt_r_r_r_r -emit_smlabt :: emit_smlabt_r_r_r_r -inst_smlatb :: inst_smlatb_r_r_r_r -emit_smlatb :: emit_smlatb_r_r_r_r -inst_smlatt :: inst_smlatt_r_r_r_r -emit_smlatt :: emit_smlatt_r_r_r_r -inst_smlawb :: inst_smlawb_r_r_r_r -emit_smlawb :: emit_smlawb_r_r_r_r -inst_smlawt :: inst_smlawt_r_r_r_r -emit_smlawt :: emit_smlawt_r_r_r_r -inst_smulbb :: inst_smulbb_r_r_r -emit_smulbb :: emit_smulbb_r_r_r -inst_smulbt :: inst_smulbt_r_r_r -emit_smulbt :: emit_smulbt_r_r_r -inst_smultb :: inst_smultb_r_r_r -emit_smultb :: emit_smultb_r_r_r -inst_smultt :: inst_smultt_r_r_r -emit_smultt :: emit_smultt_r_r_r -inst_smulwb :: inst_smulwb_r_r_r -emit_smulwb :: emit_smulwb_r_r_r -inst_smulwt :: inst_smulwt_r_r_r -emit_smulwt :: emit_smulwt_r_r_r -inst_smlalbb :: inst_smlalbb_r_r_r_r -emit_smlalbb :: emit_smlalbb_r_r_r_r -inst_smlalbt :: inst_smlalbt_r_r_r_r -emit_smlalbt :: emit_smlalbt_r_r_r_r -inst_smlaltb :: inst_smlaltb_r_r_r_r -emit_smlaltb :: emit_smlaltb_r_r_r_r -inst_smlaltt :: inst_smlaltt_r_r_r_r -emit_smlaltt :: emit_smlaltt_r_r_r_r -inst_sdiv :: inst_sdiv_r_r_r -emit_sdiv :: emit_sdiv_r_r_r -inst_udiv :: inst_udiv_r_r_r -emit_udiv :: emit_udiv_r_r_r -inst_b :: proc{ inst_b_rel, inst_b_rel_cond } -emit_b :: proc{ emit_b_rel, emit_b_rel_cond } -inst_bl :: inst_bl_rel -emit_bl :: emit_bl_rel -inst_bx :: inst_bx_r -emit_bx :: emit_bx_r -inst_blx :: proc{ inst_blx_r, inst_blx_rel } -emit_blx :: proc{ emit_blx_r, emit_blx_rel } -inst_bxj :: inst_bxj_r -emit_bxj :: emit_bxj_r -inst_cbz :: inst_cbz_rlo_rel -emit_cbz :: emit_cbz_rlo_rel -inst_cbnz :: inst_cbnz_rlo_rel -emit_cbnz :: emit_cbnz_rlo_rel -inst_tbb :: inst_tbb_r_r -emit_tbb :: emit_tbb_r_r -inst_tbh :: inst_tbh_r_r -emit_tbh :: emit_tbh_r_r -inst_msr :: proc{ inst_msr_psr_immm, inst_msr_psr_r } -emit_msr :: proc{ emit_msr_psr_immm, emit_msr_psr_r } -inst_mrs :: inst_mrs_r_psr -emit_mrs :: emit_mrs_r_psr -inst_cps :: inst_cps_ifl -emit_cps :: emit_cps_ifl -inst_setend :: inst_setend_end -emit_setend :: emit_setend_end -inst_nop :: inst_nop_none -emit_nop :: emit_nop_none -inst_yield :: inst_yield_none -emit_yield :: emit_yield_none -inst_wfe :: inst_wfe_none -emit_wfe :: emit_wfe_none -inst_wfi :: inst_wfi_none -emit_wfi :: emit_wfi_none -inst_sev :: inst_sev_none -emit_sev :: emit_sev_none -inst_sevl :: inst_sevl_none -emit_sevl :: emit_sevl_none -inst_dbg :: inst_dbg_hint -emit_dbg :: emit_dbg_hint -inst_hint :: inst_hint_hint -emit_hint :: emit_hint_hint -inst_dmb :: inst_dmb_barr -emit_dmb :: emit_dmb_barr -inst_dsb :: inst_dsb_barr -emit_dsb :: emit_dsb_barr -inst_isb :: inst_isb_barr -emit_isb :: emit_isb_barr -inst_clrex :: inst_clrex_none -emit_clrex :: emit_clrex_none -inst_pld :: inst_pld_mem -emit_pld :: emit_pld_mem -inst_pldw :: inst_pldw_mem -emit_pldw :: emit_pldw_mem -inst_pli :: inst_pli_mem -emit_pli :: emit_pli_mem -inst_hlt :: inst_hlt_imm -emit_hlt :: emit_hlt_imm -inst_dcps1 :: inst_dcps1_none -emit_dcps1 :: emit_dcps1_none -inst_dcps2 :: inst_dcps2_none -emit_dcps2 :: emit_dcps2_none -inst_dcps3 :: inst_dcps3_none -emit_dcps3 :: emit_dcps3_none -inst_eret :: inst_eret_none -emit_eret :: emit_eret_none -inst_esb :: inst_esb_none -emit_esb :: emit_esb_none -inst_psb_csync :: inst_psb_csync_none -emit_psb_csync :: emit_psb_csync_none -inst_tsb_csync :: inst_tsb_csync_none -emit_tsb_csync :: emit_tsb_csync_none -inst_csdb :: inst_csdb_none -emit_csdb :: emit_csdb_none -inst_sb :: inst_sb_none -emit_sb :: emit_sb_none -inst_setpan :: inst_setpan_hint -emit_setpan :: emit_setpan_hint -inst_svc :: inst_svc_imm -emit_svc :: emit_svc_imm -inst_bkpt :: inst_bkpt_imm -emit_bkpt :: emit_bkpt_imm -inst_hvc :: inst_hvc_imm -emit_hvc :: emit_hvc_imm -inst_smc :: inst_smc_imm -emit_smc :: emit_smc_imm -inst_udf :: inst_udf_imm -emit_udf :: emit_udf_imm -inst_ldr :: inst_ldr_r_mem -emit_ldr :: emit_ldr_r_mem -inst_str :: inst_str_r_mem -emit_str :: emit_str_r_mem -inst_ldrb :: inst_ldrb_r_mem -emit_ldrb :: emit_ldrb_r_mem -inst_strb :: inst_strb_r_mem -emit_strb :: emit_strb_r_mem -inst_ldrh :: inst_ldrh_r_mem -emit_ldrh :: emit_ldrh_r_mem -inst_strh :: inst_strh_r_mem -emit_strh :: emit_strh_r_mem -inst_ldrsb :: inst_ldrsb_r_mem -emit_ldrsb :: emit_ldrsb_r_mem -inst_ldrsh :: inst_ldrsh_r_mem -emit_ldrsh :: emit_ldrsh_r_mem -inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem } -emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem } -inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem } -emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem } -inst_ldrt :: inst_ldrt_r_mem -emit_ldrt :: emit_ldrt_r_mem -inst_strt :: inst_strt_r_mem -emit_strt :: emit_strt_r_mem -inst_ldrbt :: inst_ldrbt_r_mem -emit_ldrbt :: emit_ldrbt_r_mem -inst_strbt :: inst_strbt_r_mem -emit_strbt :: emit_strbt_r_mem -inst_ldrht :: inst_ldrht_r_mem -emit_ldrht :: emit_ldrht_r_mem -inst_strht :: inst_strht_r_mem -emit_strht :: emit_strht_r_mem -inst_ldrsbt :: inst_ldrsbt_r_mem -emit_ldrsbt :: emit_ldrsbt_r_mem -inst_ldrsht :: inst_ldrsht_r_mem -emit_ldrsht :: emit_ldrsht_r_mem -inst_lda :: inst_lda_r_mem -emit_lda :: emit_lda_r_mem -inst_stl :: inst_stl_r_mem -emit_stl :: emit_stl_r_mem -inst_ldab :: inst_ldab_r_mem -emit_ldab :: emit_ldab_r_mem -inst_stlb :: inst_stlb_r_mem -emit_stlb :: emit_stlb_r_mem -inst_ldah :: inst_ldah_r_mem -emit_ldah :: emit_ldah_r_mem -inst_stlh :: inst_stlh_r_mem -emit_stlh :: emit_stlh_r_mem -inst_ldrex :: inst_ldrex_r_mem -emit_ldrex :: emit_ldrex_r_mem -inst_strex :: inst_strex_r_r_mem -emit_strex :: emit_strex_r_r_mem -inst_ldrexb :: inst_ldrexb_r_mem -emit_ldrexb :: emit_ldrexb_r_mem -inst_strexb :: inst_strexb_r_r_mem -emit_strexb :: emit_strexb_r_r_mem -inst_ldrexh :: inst_ldrexh_r_mem -emit_ldrexh :: emit_ldrexh_r_mem -inst_strexh :: inst_strexh_r_r_mem -emit_strexh :: emit_strexh_r_r_mem -inst_ldrexd :: proc{ inst_ldrexd_r_mem, inst_ldrexd_r_r_mem } -emit_ldrexd :: proc{ emit_ldrexd_r_mem, emit_ldrexd_r_r_mem } -inst_strexd :: proc{ inst_strexd_r_r_mem, inst_strexd_r_r_r_mem } -emit_strexd :: proc{ emit_strexd_r_r_mem, emit_strexd_r_r_r_mem } -inst_ldaex :: inst_ldaex_r_mem -emit_ldaex :: emit_ldaex_r_mem -inst_stlex :: inst_stlex_r_r_mem -emit_stlex :: emit_stlex_r_r_mem -inst_ldaexb :: inst_ldaexb_r_mem -emit_ldaexb :: emit_ldaexb_r_mem -inst_stlexb :: inst_stlexb_r_r_mem -emit_stlexb :: emit_stlexb_r_r_mem -inst_ldaexh :: inst_ldaexh_r_mem -emit_ldaexh :: emit_ldaexh_r_mem -inst_stlexh :: inst_stlexh_r_r_mem -emit_stlexh :: emit_stlexh_r_r_mem -inst_ldaexd :: inst_ldaexd_r_mem -emit_ldaexd :: emit_ldaexd_r_mem -inst_stlexd :: inst_stlexd_r_r_mem -emit_stlexd :: emit_stlexd_r_r_mem -inst_ldm :: inst_ldm_r_list -emit_ldm :: emit_ldm_r_list -inst_stm :: inst_stm_r_list -emit_stm :: emit_stm_r_list -inst_push :: inst_push_list -emit_push :: emit_push_list -inst_pop :: inst_pop_list -emit_pop :: emit_pop_list -inst_swp :: inst_swp_r_r_r -emit_swp :: emit_swp_r_r_r -inst_swpb :: inst_swpb_r_r_r -emit_swpb :: emit_swpb_r_r_r -inst_rfe :: inst_rfe_r -emit_rfe :: emit_rfe_r -inst_srs :: inst_srs_imm -emit_srs :: emit_srs_imm -inst_cdp :: inst_cdp_cpn_cpop_crd_crd -emit_cdp :: emit_cdp_cpn_cpop_crd_crd -inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd -emit_cdp2 :: emit_cdp2_cpn_cpop_crd_crd -inst_mcr :: inst_mcr_cpn_cpop_r_crd -emit_mcr :: emit_mcr_cpn_cpop_r_crd -inst_mcr2 :: inst_mcr2_cpn_cpop_r_crd -emit_mcr2 :: emit_mcr2_cpn_cpop_r_crd -inst_mrc :: inst_mrc_cpn_cpop_r_crd -emit_mrc :: emit_mrc_cpn_cpop_r_crd -inst_mrc2 :: inst_mrc2_cpn_cpop_r_crd -emit_mrc2 :: emit_mrc2_cpn_cpop_r_crd -inst_mcrr :: inst_mcrr_cpn_cpop_r_r -emit_mcrr :: emit_mcrr_cpn_cpop_r_r -inst_mcrr2 :: inst_mcrr2_cpn_cpop_r_r -emit_mcrr2 :: emit_mcrr2_cpn_cpop_r_r -inst_mrrc :: inst_mrrc_cpn_cpop_r_r -emit_mrrc :: emit_mrrc_cpn_cpop_r_r -inst_mrrc2 :: inst_mrrc2_cpn_cpop_r_r -emit_mrrc2 :: emit_mrrc2_cpn_cpop_r_r -inst_ldc :: inst_ldc_cpn_crd_mem -emit_ldc :: emit_ldc_cpn_crd_mem -inst_ldc2 :: inst_ldc2_cpn_crd_mem -emit_ldc2 :: emit_ldc2_cpn_crd_mem -inst_stc :: inst_stc_cpn_crd_mem -emit_stc :: emit_stc_cpn_crd_mem -inst_stc2 :: inst_stc2_cpn_crd_mem -emit_stc2 :: emit_stc2_cpn_crd_mem -inst_crc32b :: inst_crc32b_r_r_r -emit_crc32b :: emit_crc32b_r_r_r -inst_crc32h :: inst_crc32h_r_r_r -emit_crc32h :: emit_crc32h_r_r_r -inst_crc32w :: inst_crc32w_r_r_r -emit_crc32w :: emit_crc32w_r_r_r -inst_crc32cb :: inst_crc32cb_r_r_r -emit_crc32cb :: emit_crc32cb_r_r_r -inst_crc32ch :: inst_crc32ch_r_r_r -emit_crc32ch :: emit_crc32ch_r_r_r -inst_crc32cw :: inst_crc32cw_r_r_r -emit_crc32cw :: emit_crc32cw_r_r_r -inst_vadd :: inst_vadd_s_s_s -emit_vadd :: emit_vadd_s_s_s -inst_vsub :: inst_vsub_s_s_s -emit_vsub :: emit_vsub_s_s_s -inst_vmul :: proc{ inst_vmul_s_s_s, inst_vmul_d_d_dlane } -emit_vmul :: proc{ emit_vmul_s_s_s, emit_vmul_d_d_dlane } -inst_vdiv :: inst_vdiv_s_s_s -emit_vdiv :: emit_vdiv_s_s_s -inst_vmla :: proc{ inst_vmla_s_s_s, inst_vmla_d_d_dlane } -emit_vmla :: proc{ emit_vmla_s_s_s, emit_vmla_d_d_dlane } -inst_vmls :: proc{ inst_vmls_s_s_s, inst_vmls_d_d_dlane } -emit_vmls :: proc{ emit_vmls_s_s_s, emit_vmls_d_d_dlane } -inst_vnmul :: inst_vnmul_s_s_s -emit_vnmul :: emit_vnmul_s_s_s -inst_vnmla :: inst_vnmla_s_s_s -emit_vnmla :: emit_vnmla_s_s_s -inst_vnmls :: inst_vnmls_s_s_s -emit_vnmls :: emit_vnmls_s_s_s -inst_vfma :: proc{ inst_vfma_s_s_s, inst_vfma_d_d_dlane } -emit_vfma :: proc{ emit_vfma_s_s_s, emit_vfma_d_d_dlane } -inst_vfms :: proc{ inst_vfms_s_s_s, inst_vfms_d_d_dlane } -emit_vfms :: proc{ emit_vfms_s_s_s, emit_vfms_d_d_dlane } -inst_vfnma :: inst_vfnma_s_s_s -emit_vfnma :: emit_vfnma_s_s_s -inst_vfnms :: inst_vfnms_s_s_s -emit_vfnms :: emit_vfnms_s_s_s -inst_vabs :: inst_vabs_s_s -emit_vabs :: emit_vabs_s_s -inst_vneg :: inst_vneg_s_s -emit_vneg :: emit_vneg_s_s -inst_vsqrt :: inst_vsqrt_s_s -emit_vsqrt :: emit_vsqrt_s_s -inst_vcmp :: proc{ inst_vcmp_s_s, inst_vcmp_s } -emit_vcmp :: proc{ emit_vcmp_s_s, emit_vcmp_s } -inst_vcmpe :: proc{ inst_vcmpe_s_s, inst_vcmpe_s } -emit_vcmpe :: proc{ emit_vcmpe_s_s, emit_vcmpe_s } -inst_vcvt :: inst_vcvt_d_s -emit_vcvt :: emit_vcvt_d_s -inst_vcvtb :: inst_vcvtb_s_s -emit_vcvtb :: emit_vcvtb_s_s -inst_vcvtt :: inst_vcvtt_s_s -emit_vcvtt :: emit_vcvtt_s_s -inst_vcvta :: inst_vcvta_s_s -emit_vcvta :: emit_vcvta_s_s -inst_vcvtn :: inst_vcvtn_s_s -emit_vcvtn :: emit_vcvtn_s_s -inst_vcvtp :: inst_vcvtp_s_s -emit_vcvtp :: emit_vcvtp_s_s -inst_vcvtm :: inst_vcvtm_s_s -emit_vcvtm :: emit_vcvtm_s_s -inst_vcvtr :: inst_vcvtr_s_s -emit_vcvtr :: emit_vcvtr_s_s -inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r } -emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r } -inst_vmrs :: inst_vmrs_r -emit_vmrs :: emit_vmrs_r -inst_vmsr :: inst_vmsr_r -emit_vmsr :: emit_vmsr_r -inst_vldr :: inst_vldr_s_mem -emit_vldr :: emit_vldr_s_mem -inst_vstr :: inst_vstr_s_mem -emit_vstr :: emit_vstr_s_mem -inst_vldm :: inst_vldm_r_slist -emit_vldm :: emit_vldm_r_slist -inst_vstm :: inst_vstm_r_slist -emit_vstm :: emit_vstm_r_slist -inst_vpush :: inst_vpush_slist -emit_vpush :: emit_vpush_slist -inst_vpop :: inst_vpop_slist -emit_vpop :: emit_vpop_slist -inst_vsel :: inst_vsel_s_s_s_cond -emit_vsel :: emit_vsel_s_s_s_cond -inst_vmaxnm :: inst_vmaxnm_s_s_s -emit_vmaxnm :: emit_vmaxnm_s_s_s -inst_vminnm :: inst_vminnm_s_s_s -emit_vminnm :: emit_vminnm_s_s_s -inst_vrinta :: inst_vrinta_s_s -emit_vrinta :: emit_vrinta_s_s -inst_vrintn :: inst_vrintn_s_s -emit_vrintn :: emit_vrintn_s_s -inst_vrintp :: inst_vrintp_s_s -emit_vrintp :: emit_vrintp_s_s -inst_vrintm :: inst_vrintm_s_s -emit_vrintm :: emit_vrintm_s_s -inst_vrintr :: inst_vrintr_s_s -emit_vrintr :: emit_vrintr_s_s -inst_vrintz :: inst_vrintz_s_s -emit_vrintz :: emit_vrintz_s_s -inst_vrintx :: inst_vrintx_s_s -emit_vrintx :: emit_vrintx_s_s -inst_vaddl :: inst_vaddl_q_d_d -emit_vaddl :: emit_vaddl_q_d_d -inst_vaddw :: inst_vaddw_q_q_d -emit_vaddw :: emit_vaddw_q_q_d -inst_vsubl :: inst_vsubl_q_d_d -emit_vsubl :: emit_vsubl_q_d_d -inst_vsubw :: inst_vsubw_q_q_d -emit_vsubw :: emit_vsubw_q_q_d -inst_vhadd :: inst_vhadd_d_d_d -emit_vhadd :: emit_vhadd_d_d_d -inst_vhsub :: inst_vhsub_d_d_d -emit_vhsub :: emit_vhsub_d_d_d -inst_vrhadd :: inst_vrhadd_d_d_d -emit_vrhadd :: emit_vrhadd_d_d_d -inst_vqadd :: inst_vqadd_d_d_d -emit_vqadd :: emit_vqadd_d_d_d -inst_vqsub :: inst_vqsub_d_d_d -emit_vqsub :: emit_vqsub_d_d_d -inst_vmull :: proc{ inst_vmull_q_d_d, inst_vmull_q_d_dlane } -emit_vmull :: proc{ emit_vmull_q_d_d, emit_vmull_q_d_dlane } -inst_vmlal :: proc{ inst_vmlal_q_d_d, inst_vmlal_q_d_dlane } -emit_vmlal :: proc{ emit_vmlal_q_d_d, emit_vmlal_q_d_dlane } -inst_vmlsl :: proc{ inst_vmlsl_q_d_d, inst_vmlsl_q_d_dlane } -emit_vmlsl :: proc{ emit_vmlsl_q_d_d, emit_vmlsl_q_d_dlane } -inst_vqdmull :: proc{ inst_vqdmull_q_d_d, inst_vqdmull_q_d_dlane } -emit_vqdmull :: proc{ emit_vqdmull_q_d_d, emit_vqdmull_q_d_dlane } -inst_vqdmlal :: proc{ inst_vqdmlal_q_d_d, inst_vqdmlal_q_d_dlane } -emit_vqdmlal :: proc{ emit_vqdmlal_q_d_d, emit_vqdmlal_q_d_dlane } -inst_vqdmlsl :: proc{ inst_vqdmlsl_q_d_d, inst_vqdmlsl_q_d_dlane } -emit_vqdmlsl :: proc{ emit_vqdmlsl_q_d_d, emit_vqdmlsl_q_d_dlane } -inst_vqdmulh :: proc{ inst_vqdmulh_d_d_d, inst_vqdmulh_d_d_dlane } -emit_vqdmulh :: proc{ emit_vqdmulh_d_d_d, emit_vqdmulh_d_d_dlane } -inst_vqrdmulh :: proc{ inst_vqrdmulh_d_d_d, inst_vqrdmulh_d_d_dlane } -emit_vqrdmulh :: proc{ emit_vqrdmulh_d_d_d, emit_vqrdmulh_d_d_dlane } -inst_vqrdmlah :: proc{ inst_vqrdmlah_d_d_d, inst_vqrdmlah_d_d_dlane } -emit_vqrdmlah :: proc{ emit_vqrdmlah_d_d_d, emit_vqrdmlah_d_d_dlane } -inst_vqrdmlsh :: proc{ inst_vqrdmlsh_d_d_d, inst_vqrdmlsh_d_d_dlane } -emit_vqrdmlsh :: proc{ emit_vqrdmlsh_d_d_d, emit_vqrdmlsh_d_d_dlane } -inst_vaba :: inst_vaba_d_d_d -emit_vaba :: emit_vaba_d_d_d -inst_vabal :: inst_vabal_q_d_d -emit_vabal :: emit_vabal_q_d_d -inst_vabd :: inst_vabd_d_d_d -emit_vabd :: emit_vabd_d_d_d -inst_vabdl :: inst_vabdl_q_d_d -emit_vabdl :: emit_vabdl_q_d_d -inst_vand :: inst_vand_d_d_d -emit_vand :: emit_vand_d_d_d -inst_vbic :: inst_vbic_d_d_d -emit_vbic :: emit_vbic_d_d_d -inst_vorr :: inst_vorr_d_d_d -emit_vorr :: emit_vorr_d_d_d -inst_vorn :: inst_vorn_d_d_d -emit_vorn :: emit_vorn_d_d_d -inst_veor :: inst_veor_d_d_d -emit_veor :: emit_veor_d_d_d -inst_vbsl :: inst_vbsl_d_d_d -emit_vbsl :: emit_vbsl_d_d_d -inst_vbit :: inst_vbit_d_d_d -emit_vbit :: emit_vbit_d_d_d -inst_vbif :: inst_vbif_d_d_d -emit_vbif :: emit_vbif_d_d_d -inst_vmvn :: proc{ inst_vmvn_d_d, inst_vmvn_d_imm } -emit_vmvn :: proc{ emit_vmvn_d_d, emit_vmvn_d_imm } -inst_vmovn :: inst_vmovn_d_q -emit_vmovn :: emit_vmovn_d_q -inst_vqmovn :: inst_vqmovn_d_q -emit_vqmovn :: emit_vqmovn_d_q -inst_vqmovun :: inst_vqmovun_d_q -emit_vqmovun :: emit_vqmovun_d_q -inst_vmovl :: inst_vmovl_q_d -emit_vmovl :: emit_vmovl_q_d -inst_vtst :: inst_vtst_d_d_d -emit_vtst :: emit_vtst_d_d_d -inst_vceq :: inst_vceq_d_d_d -emit_vceq :: emit_vceq_d_d_d -inst_vcge :: inst_vcge_d_d_d -emit_vcge :: emit_vcge_d_d_d -inst_vcgt :: inst_vcgt_d_d_d -emit_vcgt :: emit_vcgt_d_d_d -inst_vcle :: inst_vcle_d_d_d -emit_vcle :: emit_vcle_d_d_d -inst_vclt :: inst_vclt_d_d_d -emit_vclt :: emit_vclt_d_d_d -inst_vacge :: inst_vacge_d_d_d -emit_vacge :: emit_vacge_d_d_d -inst_vacgt :: inst_vacgt_d_d_d -emit_vacgt :: emit_vacgt_d_d_d -inst_vacle :: inst_vacle_d_d_d -emit_vacle :: emit_vacle_d_d_d -inst_vaclt :: inst_vaclt_d_d_d -emit_vaclt :: emit_vaclt_d_d_d -inst_vmax :: inst_vmax_d_d_d -emit_vmax :: emit_vmax_d_d_d -inst_vmin :: inst_vmin_d_d_d -emit_vmin :: emit_vmin_d_d_d -inst_vpmax :: inst_vpmax_d_d_d -emit_vpmax :: emit_vpmax_d_d_d -inst_vpmin :: inst_vpmin_d_d_d -emit_vpmin :: emit_vpmin_d_d_d -inst_vpadd :: inst_vpadd_d_d_d -emit_vpadd :: emit_vpadd_d_d_d -inst_vpaddl :: inst_vpaddl_d_d -emit_vpaddl :: emit_vpaddl_d_d -inst_vpadal :: inst_vpadal_d_d -emit_vpadal :: emit_vpadal_d_d -inst_vrecpe :: inst_vrecpe_d_d -emit_vrecpe :: emit_vrecpe_d_d -inst_vrecps :: inst_vrecps_d_d_d -emit_vrecps :: emit_vrecps_d_d_d -inst_vrsqrte :: inst_vrsqrte_d_d -emit_vrsqrte :: emit_vrsqrte_d_d -inst_vrsqrts :: inst_vrsqrts_d_d_d -emit_vrsqrts :: emit_vrsqrts_d_d_d -inst_vshl :: inst_vshl_d_d_d -emit_vshl :: emit_vshl_d_d_d -inst_vshr :: inst_vshr_d_d_imm -emit_vshr :: emit_vshr_d_d_imm -inst_vsra :: inst_vsra_d_d_imm -emit_vsra :: emit_vsra_d_d_imm -inst_vrshl :: inst_vrshl_d_d_d -emit_vrshl :: emit_vrshl_d_d_d -inst_vrshr :: inst_vrshr_d_d_imm -emit_vrshr :: emit_vrshr_d_d_imm -inst_vrsra :: inst_vrsra_d_d_imm -emit_vrsra :: emit_vrsra_d_d_imm -inst_vsli :: inst_vsli_d_d_imm -emit_vsli :: emit_vsli_d_d_imm -inst_vsri :: inst_vsri_d_d_imm -emit_vsri :: emit_vsri_d_d_imm -inst_vqshl :: proc{ inst_vqshl_d_d_d, inst_vqshl_d_d_imm } -emit_vqshl :: proc{ emit_vqshl_d_d_d, emit_vqshl_d_d_imm } -inst_vqshrn :: inst_vqshrn_d_q_imm -emit_vqshrn :: emit_vqshrn_d_q_imm -inst_vqshrun :: inst_vqshrun_d_q_imm -emit_vqshrun :: emit_vqshrun_d_q_imm -inst_vqrshl :: inst_vqrshl_d_d_d -emit_vqrshl :: emit_vqrshl_d_d_d -inst_vqrshrn :: inst_vqrshrn_d_q_imm -emit_vqrshrn :: emit_vqrshrn_d_q_imm -inst_vqrshrun :: inst_vqrshrun_d_q_imm -emit_vqrshrun :: emit_vqrshrun_d_q_imm -inst_vshrn :: inst_vshrn_d_q_imm -emit_vshrn :: emit_vshrn_d_q_imm -inst_vrshrn :: inst_vrshrn_d_q_imm -emit_vrshrn :: emit_vrshrn_d_q_imm -inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d } -emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d } -inst_vcls :: inst_vcls_d_d -emit_vcls :: emit_vcls_d_d -inst_vclz :: inst_vclz_d_d -emit_vclz :: emit_vclz_d_d -inst_vcnt :: inst_vcnt_d_d -emit_vcnt :: emit_vcnt_d_d -inst_vpadd_f :: inst_vpadd_f_d_d_d -emit_vpadd_f :: emit_vpadd_f_d_d_d -inst_vrecpe_f :: inst_vrecpe_f_d_d -emit_vrecpe_f :: emit_vrecpe_f_d_d -inst_vrsqrte_f :: inst_vrsqrte_f_d_d -emit_vrsqrte_f :: emit_vrsqrte_f_d_d -inst_vrev16 :: inst_vrev16_d_d -emit_vrev16 :: emit_vrev16_d_d -inst_vrev32 :: inst_vrev32_d_d -emit_vrev32 :: emit_vrev32_d_d -inst_vrev64 :: inst_vrev64_d_d -emit_vrev64 :: emit_vrev64_d_d -inst_vext :: inst_vext_d_d_d_imm4 -emit_vext :: emit_vext_d_d_d_imm4 -inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d } -emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d } -inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d } -emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d } -inst_vtrn :: inst_vtrn_d_d -emit_vtrn :: emit_vtrn_d_d -inst_vuzp :: inst_vuzp_d_d -emit_vuzp :: emit_vuzp_d_d -inst_vzip :: inst_vzip_d_d -emit_vzip :: emit_vzip_d_d -inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane } -emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane } -inst_vswp :: inst_vswp_d_d -emit_vswp :: emit_vswp_d_d -inst_vmov_lane :: inst_vmov_lane_dlane_r -emit_vmov_lane :: emit_vmov_lane_dlane_r -inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem } -emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem } -inst_vld2 :: inst_vld2_dlist_mem -emit_vld2 :: emit_vld2_dlist_mem -inst_vld3 :: inst_vld3_dlist_mem -emit_vld3 :: emit_vld3_dlist_mem -inst_vld4 :: inst_vld4_dlist_mem -emit_vld4 :: emit_vld4_dlist_mem -inst_vst1 :: proc{ inst_vst1_dlist_mem, inst_vst1_dlane_mem } -emit_vst1 :: proc{ emit_vst1_dlist_mem, emit_vst1_dlane_mem } -inst_vst2 :: inst_vst2_dlist_mem -emit_vst2 :: emit_vst2_dlist_mem -inst_vst3 :: inst_vst3_dlist_mem -emit_vst3 :: emit_vst3_dlist_mem -inst_vst4 :: inst_vst4_dlist_mem -emit_vst4 :: emit_vst4_dlist_mem -inst_aese :: inst_aese_q_q -emit_aese :: emit_aese_q_q -inst_aesd :: inst_aesd_q_q -emit_aesd :: emit_aesd_q_q -inst_aesmc :: inst_aesmc_q_q -emit_aesmc :: emit_aesmc_q_q -inst_aesimc :: inst_aesimc_q_q -emit_aesimc :: emit_aesimc_q_q -inst_sha1h :: inst_sha1h_q_q -emit_sha1h :: emit_sha1h_q_q -inst_sha1su0 :: inst_sha1su0_q_q_q -emit_sha1su0 :: emit_sha1su0_q_q_q -inst_sha1su1 :: inst_sha1su1_q_q -emit_sha1su1 :: emit_sha1su1_q_q -inst_sha1c :: inst_sha1c_q_q_q -emit_sha1c :: emit_sha1c_q_q_q -inst_sha1m :: inst_sha1m_q_q_q -emit_sha1m :: emit_sha1m_q_q_q -inst_sha1p :: inst_sha1p_q_q_q -emit_sha1p :: emit_sha1p_q_q_q -inst_sha256h :: inst_sha256h_q_q_q -emit_sha256h :: emit_sha256h_q_q_q -inst_sha256h2 :: inst_sha256h2_q_q_q -emit_sha256h2 :: emit_sha256h2_q_q_q -inst_sha256su0 :: inst_sha256su0_q_q -emit_sha256su0 :: emit_sha256su0_q_q -inst_sha256su1 :: inst_sha256su1_q_q_q -emit_sha256su1 :: emit_sha256su1_q_q_q -inst_vjcvt :: inst_vjcvt_s_d -emit_vjcvt :: emit_vjcvt_s_d -inst_vsdot :: proc{ inst_vsdot_d_d_d, inst_vsdot_d_d_dlane } -emit_vsdot :: proc{ emit_vsdot_d_d_d, emit_vsdot_d_d_dlane } -inst_vudot :: proc{ inst_vudot_d_d_d, inst_vudot_d_d_dlane } -emit_vudot :: proc{ emit_vudot_d_d_d, emit_vudot_d_d_dlane } -inst_vcvt_bf16 :: inst_vcvt_bf16_d_q -emit_vcvt_bf16 :: emit_vcvt_bf16_d_q -inst_vdot_bf16 :: inst_vdot_bf16_d_d_d -emit_vdot_bf16 :: emit_vdot_bf16_d_d_d -inst_vfma_bf16 :: inst_vfma_bf16_q_q_q -emit_vfma_bf16 :: emit_vfma_bf16_q_q_q -inst_vmmla_bf16 :: inst_vmmla_bf16_q_q_q -emit_vmmla_bf16 :: emit_vmmla_bf16_q_q_q -inst_vfmal :: inst_vfmal_d_d_d -emit_vfmal :: emit_vfmal_d_d_d -inst_vfmsl :: inst_vfmsl_d_d_d -emit_vfmsl :: emit_vfmsl_d_d_d -inst_vcmla :: proc{ inst_vcmla_d_d_d_imm, inst_vcmla_d_d_dlane_imm } -emit_vcmla :: proc{ emit_vcmla_d_d_d_imm, emit_vcmla_d_d_dlane_imm } -inst_vcadd :: inst_vcadd_d_d_d_imm -emit_vcadd :: emit_vcadd_d_d_d_imm -inst_vsmmla :: inst_vsmmla_q_q_q -emit_vsmmla :: emit_vsmmla_q_q_q -inst_vummla :: inst_vummla_q_q_q -emit_vummla :: emit_vummla_q_q_q -inst_vusmmla :: inst_vusmmla_q_q_q -emit_vusmmla :: emit_vusmmla_q_q_q -inst_vsudot :: proc{ inst_vsudot_q_q_q, inst_vsudot_q_q_dlane } -emit_vsudot :: proc{ emit_vsudot_q_q_q, emit_vsudot_q_q_dlane } -inst_vusdot :: proc{ inst_vusdot_d_d_d, inst_vusdot_d_d_dlane } -emit_vusdot :: proc{ emit_vusdot_d_d_d, emit_vusdot_d_d_dlane } -inst_vqabs :: inst_vqabs_q_q -emit_vqabs :: emit_vqabs_q_q -inst_vqneg :: inst_vqneg_q_q -emit_vqneg :: emit_vqneg_q_q -inst_vmovx :: inst_vmovx_s_s -emit_vmovx :: emit_vmovx_s_s -inst_vins :: inst_vins_s_s -emit_vins :: emit_vins_s_s -inst_vldrb_gather :: inst_vldrb_gather_q_mem_q -emit_vldrb_gather :: emit_vldrb_gather_q_mem_q -inst_vldrh_gather :: inst_vldrh_gather_q_mem_q -emit_vldrh_gather :: emit_vldrh_gather_q_mem_q -inst_vldrw_gather :: inst_vldrw_gather_q_mem_q -emit_vldrw_gather :: emit_vldrw_gather_q_mem_q -inst_vldrd_gather :: inst_vldrd_gather_q_mem_q -emit_vldrd_gather :: emit_vldrd_gather_q_mem_q -inst_vstrb_scatter :: inst_vstrb_scatter_q_mem_q -emit_vstrb_scatter :: emit_vstrb_scatter_q_mem_q -inst_vstrh_scatter :: inst_vstrh_scatter_q_mem_q -emit_vstrh_scatter :: emit_vstrh_scatter_q_mem_q -inst_vstrw_scatter :: inst_vstrw_scatter_q_mem_q -emit_vstrw_scatter :: emit_vstrw_scatter_q_mem_q -inst_vstrd_scatter :: inst_vstrd_scatter_q_mem_q -emit_vstrd_scatter :: emit_vstrd_scatter_q_mem_q -inst_vceq_z :: inst_vceq_z_d_d -emit_vceq_z :: emit_vceq_z_d_d -inst_vcge_z :: inst_vcge_z_d_d -emit_vcge_z :: emit_vcge_z_d_d -inst_vcgt_z :: inst_vcgt_z_d_d -emit_vcgt_z :: emit_vcgt_z_d_d -inst_vcle_z :: inst_vcle_z_d_d -emit_vcle_z :: emit_vcle_z_d_d -inst_vclt_z :: inst_vclt_z_d_d -emit_vclt_z :: emit_vclt_z_d_d -inst_vld2r :: inst_vld2r_dlist_mem -emit_vld2r :: emit_vld2r_dlist_mem -inst_vld3r :: inst_vld3r_dlist_mem -emit_vld3r :: emit_vld3r_dlist_mem -inst_vld4r :: inst_vld4r_dlist_mem -emit_vld4r :: emit_vld4r_dlist_mem -inst_vld1_lane :: inst_vld1_lane_dlane_mem -emit_vld1_lane :: emit_vld1_lane_dlane_mem -inst_vld2_lane :: inst_vld2_lane_dlist_mem -emit_vld2_lane :: emit_vld2_lane_dlist_mem -inst_vld3_lane :: inst_vld3_lane_dlist_mem -emit_vld3_lane :: emit_vld3_lane_dlist_mem -inst_vld4_lane :: inst_vld4_lane_dlist_mem -emit_vld4_lane :: emit_vld4_lane_dlist_mem -inst_vst1_lane :: inst_vst1_lane_dlane_mem -emit_vst1_lane :: emit_vst1_lane_dlane_mem -inst_vst2_lane :: inst_vst2_lane_dlist_mem -emit_vst2_lane :: emit_vst2_lane_dlist_mem -inst_vst3_lane :: inst_vst3_lane_dlist_mem -emit_vst3_lane :: emit_vst3_lane_dlist_mem -inst_vst4_lane :: inst_vst4_lane_dlist_mem -emit_vst4_lane :: emit_vst4_lane_dlist_mem -inst_vcvt_fixed :: inst_vcvt_fixed_s_s_imm -emit_vcvt_fixed :: emit_vcvt_fixed_s_s_imm -inst_it :: inst_it_cond_imm4 -emit_it :: emit_it_cond_imm4 -inst_tt :: inst_tt_r_r -emit_tt :: emit_tt_r_r -inst_ttt :: inst_ttt_r_r -emit_ttt :: emit_ttt_r_r -inst_tta :: inst_tta_r_r -emit_tta :: emit_tta_r_r -inst_ttat :: inst_ttat_r_r -emit_ttat :: emit_ttat_r_r -inst_sg :: inst_sg_none -emit_sg :: emit_sg_none -inst_bxns :: inst_bxns_r -emit_bxns :: emit_bxns_r -inst_blxns :: inst_blxns_r -emit_blxns :: emit_blxns_r -inst_pac :: inst_pac_none -emit_pac :: emit_pac_none -inst_pacbti :: inst_pacbti_none -emit_pacbti :: emit_pacbti_none -inst_aut :: inst_aut_none -emit_aut :: emit_aut_none -inst_autg :: inst_autg_r_r_r -emit_autg :: emit_autg_r_r_r -inst_bti :: inst_bti_none -emit_bti :: emit_bti_none -inst_wls :: inst_wls_r_rel -emit_wls :: emit_wls_r_rel -inst_wlstp :: inst_wlstp_r_rel -emit_wlstp :: emit_wlstp_r_rel -inst_dls :: inst_dls_r -emit_dls :: emit_dls_r -inst_dlstp :: inst_dlstp_r -emit_dlstp :: emit_dlstp_r -inst_le :: inst_le_rel -emit_le :: emit_le_rel -inst_letp :: inst_letp_rel -emit_letp :: emit_letp_rel -inst_lctp :: inst_lctp_none -emit_lctp :: emit_lctp_none -inst_bf :: inst_bf_rel_rel -emit_bf :: emit_bf_rel_rel -inst_bfi_br :: inst_bfi_br_rel_r -emit_bfi_br :: emit_bfi_br_rel_r -inst_bfl :: inst_bfl_rel_rel -emit_bfl :: emit_bfl_rel_rel -inst_bflx :: inst_bflx_rel_r -emit_bflx :: emit_bflx_rel_r -inst_bfcsel :: inst_bfcsel_rel_rel_imm4 -emit_bfcsel :: emit_bfcsel_rel_rel_imm4 -inst_cx1 :: inst_cx1_cp_r_imm -emit_cx1 :: emit_cx1_cp_r_imm -inst_cx1a :: inst_cx1a_cp_r_imm -emit_cx1a :: emit_cx1a_cp_r_imm -inst_cx1d :: inst_cx1d_cp_r_imm -emit_cx1d :: emit_cx1d_cp_r_imm -inst_cx1da :: inst_cx1da_cp_r_imm -emit_cx1da :: emit_cx1da_cp_r_imm -inst_cx2 :: inst_cx2_cp_r_r_imm -emit_cx2 :: emit_cx2_cp_r_r_imm -inst_cx2a :: inst_cx2a_cp_r_r_imm -emit_cx2a :: emit_cx2a_cp_r_r_imm -inst_cx2d :: inst_cx2d_cp_r_r_imm -emit_cx2d :: emit_cx2d_cp_r_r_imm -inst_cx2da :: inst_cx2da_cp_r_r_imm -emit_cx2da :: emit_cx2da_cp_r_r_imm -inst_cx3 :: inst_cx3_cp_r_r_r -emit_cx3 :: emit_cx3_cp_r_r_r -inst_cx3a :: inst_cx3a_cp_r_r_r -emit_cx3a :: emit_cx3a_cp_r_r_r -inst_cx3d :: inst_cx3d_cp_r_r_r -emit_cx3d :: emit_cx3d_cp_r_r_r -inst_cx3da :: inst_cx3da_cp_r_r_r -emit_cx3da :: emit_cx3da_cp_r_r_r -inst_vcx1 :: inst_vcx1_cp_s_imm -emit_vcx1 :: emit_vcx1_cp_s_imm -inst_vcx1a :: inst_vcx1a_cp_s_imm -emit_vcx1a :: emit_vcx1a_cp_s_imm -inst_vcx2 :: inst_vcx2_cp_s_s_imm -emit_vcx2 :: emit_vcx2_cp_s_s_imm -inst_vcx2a :: inst_vcx2a_cp_s_s_imm -emit_vcx2a :: emit_vcx2a_cp_s_s_imm -inst_vcx3 :: inst_vcx3_cp_s_s_s -emit_vcx3 :: emit_vcx3_cp_s_s_s -inst_vcx3a :: inst_vcx3a_cp_s_s_s -emit_vcx3a :: emit_vcx3a_cp_s_s_s -inst_vpt :: inst_vpt_vpt_cond_q_q -emit_vpt :: emit_vpt_vpt_cond_q_q -inst_vpst :: inst_vpst_vpt -emit_vpst :: emit_vpst_vpt -inst_vpsel :: inst_vpsel_q_q_q -emit_vpsel :: emit_vpsel_q_q_q -inst_vpnot :: inst_vpnot_none -emit_vpnot :: emit_vpnot_none -inst_vctp :: inst_vctp_r -emit_vctp :: emit_vctp_r -inst_vaddv :: inst_vaddv_r_q -emit_vaddv :: emit_vaddv_r_q -inst_vaddva :: inst_vaddva_r_q -emit_vaddva :: emit_vaddva_r_q -inst_vaddlv :: inst_vaddlv_r_r_q -emit_vaddlv :: emit_vaddlv_r_r_q -inst_vaddlva :: inst_vaddlva_r_r_q -emit_vaddlva :: emit_vaddlva_r_r_q -inst_vmaxv :: inst_vmaxv_r_q -emit_vmaxv :: emit_vmaxv_r_q -inst_vmaxav :: inst_vmaxav_r_q -emit_vmaxav :: emit_vmaxav_r_q -inst_vminv :: inst_vminv_r_q -emit_vminv :: emit_vminv_r_q -inst_vminav :: inst_vminav_r_q -emit_vminav :: emit_vminav_r_q -inst_vmaxnmv :: inst_vmaxnmv_r_q -emit_vmaxnmv :: emit_vmaxnmv_r_q -inst_vmaxnmav :: inst_vmaxnmav_r_q -emit_vmaxnmav :: emit_vmaxnmav_r_q -inst_vminnmv :: inst_vminnmv_r_q -emit_vminnmv :: emit_vminnmv_r_q -inst_vminnmav :: inst_vminnmav_r_q -emit_vminnmav :: emit_vminnmav_r_q -inst_vabav :: inst_vabav_r_q_q -emit_vabav :: emit_vabav_r_q_q -inst_vmladav :: inst_vmladav_r_q_q -emit_vmladav :: emit_vmladav_r_q_q -inst_vmladava :: inst_vmladava_r_q_q -emit_vmladava :: emit_vmladava_r_q_q -inst_vmladavx :: inst_vmladavx_r_q_q -emit_vmladavx :: emit_vmladavx_r_q_q -inst_vmladavax :: inst_vmladavax_r_q_q -emit_vmladavax :: emit_vmladavax_r_q_q -inst_vmlaldav :: inst_vmlaldav_r_r_q_q -emit_vmlaldav :: emit_vmlaldav_r_r_q_q -inst_vmlaldava :: inst_vmlaldava_r_r_q_q -emit_vmlaldava :: emit_vmlaldava_r_r_q_q -inst_vmlaldavx :: inst_vmlaldavx_r_r_q_q -emit_vmlaldavx :: emit_vmlaldavx_r_r_q_q -inst_vmlaldavax :: inst_vmlaldavax_r_r_q_q -emit_vmlaldavax :: emit_vmlaldavax_r_r_q_q -inst_vmlsdav :: inst_vmlsdav_r_q_q -emit_vmlsdav :: emit_vmlsdav_r_q_q -inst_vmlsdava :: inst_vmlsdava_r_q_q -emit_vmlsdava :: emit_vmlsdava_r_q_q -inst_vmlsdavx :: inst_vmlsdavx_r_q_q -emit_vmlsdavx :: emit_vmlsdavx_r_q_q -inst_vmlsdavax :: inst_vmlsdavax_r_q_q -emit_vmlsdavax :: emit_vmlsdavax_r_q_q -inst_vmlsldav :: inst_vmlsldav_r_r_q_q -emit_vmlsldav :: emit_vmlsldav_r_r_q_q -inst_vmlsldava :: inst_vmlsldava_r_r_q_q -emit_vmlsldava :: emit_vmlsldava_r_r_q_q -inst_vmlsldavx :: inst_vmlsldavx_r_r_q_q -emit_vmlsldavx :: emit_vmlsldavx_r_r_q_q -inst_vmlsldavax :: inst_vmlsldavax_r_r_q_q -emit_vmlsldavax :: emit_vmlsldavax_r_r_q_q -inst_vrmlaldavh :: inst_vrmlaldavh_r_r_q_q -emit_vrmlaldavh :: emit_vrmlaldavh_r_r_q_q -inst_vrmlaldavha :: inst_vrmlaldavha_r_r_q_q -emit_vrmlaldavha :: emit_vrmlaldavha_r_r_q_q -inst_vrmlaldavhx :: inst_vrmlaldavhx_r_r_q_q -emit_vrmlaldavhx :: emit_vrmlaldavhx_r_r_q_q -inst_vrmlaldavhax :: inst_vrmlaldavhax_r_r_q_q -emit_vrmlaldavhax :: emit_vrmlaldavhax_r_r_q_q -inst_vrmlsldavh :: inst_vrmlsldavh_r_r_q_q -emit_vrmlsldavh :: emit_vrmlsldavh_r_r_q_q -inst_vrmlsldavha :: inst_vrmlsldavha_r_r_q_q -emit_vrmlsldavha :: emit_vrmlsldavha_r_r_q_q -inst_vrmlsldavhx :: inst_vrmlsldavhx_r_r_q_q -emit_vrmlsldavhx :: emit_vrmlsldavhx_r_r_q_q -inst_vrmlsldavhax :: inst_vrmlsldavhax_r_r_q_q -emit_vrmlsldavhax :: emit_vrmlsldavhax_r_r_q_q -inst_vmlav :: inst_vmlav_r_q_q -emit_vmlav :: emit_vmlav_r_q_q -inst_vmlava :: inst_vmlava_r_q_q -emit_vmlava :: emit_vmlava_r_q_q -inst_vmlsv :: inst_vmlsv_r_q_q -emit_vmlsv :: emit_vmlsv_r_q_q -inst_vmlsva :: inst_vmlsva_r_q_q -emit_vmlsva :: emit_vmlsva_r_q_q -inst_vcmul :: inst_vcmul_q_q_q -emit_vcmul :: emit_vcmul_q_q_q -inst_vhcadd :: inst_vhcadd_q_q_q -emit_vhcadd :: emit_vhcadd_q_q_q -inst_vbrsr :: inst_vbrsr_q_q_r -emit_vbrsr :: emit_vbrsr_q_q_r -inst_vshlc :: inst_vshlc_q_r_imm5 -emit_vshlc :: emit_vshlc_q_r_imm5 -inst_vddup :: inst_vddup_q_r_imm -emit_vddup :: emit_vddup_q_r_imm -inst_vidup :: inst_vidup_q_r_imm -emit_vidup :: emit_vidup_q_r_imm -inst_vdwdup :: inst_vdwdup_q_r_r_imm -emit_vdwdup :: emit_vdwdup_q_r_r_imm -inst_viwdup :: inst_viwdup_q_r_r_imm -emit_viwdup :: emit_viwdup_q_r_r_imm -inst_vmovnb :: inst_vmovnb_q_q -emit_vmovnb :: emit_vmovnb_q_q -inst_vmovnt :: inst_vmovnt_q_q -emit_vmovnt :: emit_vmovnt_q_q -inst_vqmovnb :: inst_vqmovnb_q_q -emit_vqmovnb :: emit_vqmovnb_q_q -inst_vqmovnt :: inst_vqmovnt_q_q -emit_vqmovnt :: emit_vqmovnt_q_q -inst_vqmovunb :: inst_vqmovunb_q_q -emit_vqmovunb :: emit_vqmovunb_q_q -inst_vqmovunt :: inst_vqmovunt_q_q -emit_vqmovunt :: emit_vqmovunt_q_q -inst_vshllb :: inst_vshllb_q_q_imm5 -emit_vshllb :: emit_vshllb_q_q_imm5 -inst_vshllt :: inst_vshllt_q_q_imm5 -emit_vshllt :: emit_vshllt_q_q_imm5 -inst_vmullb :: inst_vmullb_q_q_q -emit_vmullb :: emit_vmullb_q_q_q -inst_vmullt :: inst_vmullt_q_q_q -emit_vmullt :: emit_vmullt_q_q_q -inst_vmlalb :: inst_vmlalb_q_q_q -emit_vmlalb :: emit_vmlalb_q_q_q -inst_vmlalt :: inst_vmlalt_q_q_q -emit_vmlalt :: emit_vmlalt_q_q_q -inst_vmlslb :: inst_vmlslb_q_q_q -emit_vmlslb :: emit_vmlslb_q_q_q -inst_vmlslt :: inst_vmlslt_q_q_q -emit_vmlslt :: emit_vmlslt_q_q_q -inst_vshrnb :: inst_vshrnb_q_q_imm5 -emit_vshrnb :: emit_vshrnb_q_q_imm5 -inst_vshrnt :: inst_vshrnt_q_q_imm5 -emit_vshrnt :: emit_vshrnt_q_q_imm5 -inst_vrshrnb :: inst_vrshrnb_q_q_imm5 -emit_vrshrnb :: emit_vrshrnb_q_q_imm5 -inst_vrshrnt :: inst_vrshrnt_q_q_imm5 -emit_vrshrnt :: emit_vrshrnt_q_q_imm5 -inst_vqshrnb :: inst_vqshrnb_q_q_imm5 -emit_vqshrnb :: emit_vqshrnb_q_q_imm5 -inst_vqshrnt :: inst_vqshrnt_q_q_imm5 -emit_vqshrnt :: emit_vqshrnt_q_q_imm5 -inst_vqrshrnb :: inst_vqrshrnb_q_q_imm5 -emit_vqrshrnb :: emit_vqrshrnb_q_q_imm5 -inst_vqrshrnt :: inst_vqrshrnt_q_q_imm5 -emit_vqrshrnt :: emit_vqrshrnt_q_q_imm5 -inst_vqshrunb :: inst_vqshrunb_q_q_imm5 -emit_vqshrunb :: emit_vqshrunb_q_q_imm5 -inst_vqshrunt :: inst_vqshrunt_q_q_imm5 -emit_vqshrunt :: emit_vqshrunt_q_q_imm5 -inst_vqrshrunb :: inst_vqrshrunb_q_q_imm5 -emit_vqrshrunb :: emit_vqrshrunb_q_q_imm5 -inst_vqrshrunt :: inst_vqrshrunt_q_q_imm5 -emit_vqrshrunt :: emit_vqrshrunt_q_q_imm5 -inst_vmov_q_r :: inst_vmov_q_r_qlane_r -emit_vmov_q_r :: emit_vmov_q_r_qlane_r -inst_vmov_r_q :: inst_vmov_r_q_r_qlane -emit_vmov_r_q :: emit_vmov_r_q_r_qlane -inst_vmov_2gpr_q :: inst_vmov_2gpr_q_qlane_qlane_r_r -emit_vmov_2gpr_q :: emit_vmov_2gpr_q_qlane_qlane_r_r -inst_vqdmladh :: inst_vqdmladh_q_q_q -emit_vqdmladh :: emit_vqdmladh_q_q_q -inst_vqdmladhx :: inst_vqdmladhx_q_q_q -emit_vqdmladhx :: emit_vqdmladhx_q_q_q -inst_vqdmlsdh :: inst_vqdmlsdh_q_q_q -emit_vqdmlsdh :: emit_vqdmlsdh_q_q_q -inst_vqdmlsdhx :: inst_vqdmlsdhx_q_q_q -emit_vqdmlsdhx :: emit_vqdmlsdhx_q_q_q -inst_vqrdmladh :: inst_vqrdmladh_q_q_q -emit_vqrdmladh :: emit_vqrdmladh_q_q_q -inst_vqrdmladhx :: inst_vqrdmladhx_q_q_q -emit_vqrdmladhx :: emit_vqrdmladhx_q_q_q -inst_vqrdmlsdh :: inst_vqrdmlsdh_q_q_q -emit_vqrdmlsdh :: emit_vqrdmlsdh_q_q_q -inst_vqrdmlsdhx :: inst_vqrdmlsdhx_q_q_q -emit_vqrdmlsdhx :: emit_vqrdmlsdhx_q_q_q -inst_vhcadd_sat :: inst_vhcadd_sat_q_q_q_imm -emit_vhcadd_sat :: emit_vhcadd_sat_q_q_q_imm -inst_vcmla_mve :: inst_vcmla_mve_q_q_q_imm -emit_vcmla_mve :: emit_vcmla_mve_q_q_q_imm -inst_vldrb :: inst_vldrb_q_mem -emit_vldrb :: emit_vldrb_q_mem -inst_vldrh :: inst_vldrh_q_mem -emit_vldrh :: emit_vldrh_q_mem -inst_vldrw :: inst_vldrw_q_mem -emit_vldrw :: emit_vldrw_q_mem -inst_vldrd :: inst_vldrd_q_mem -emit_vldrd :: emit_vldrd_q_mem -inst_vstrb :: inst_vstrb_q_mem -emit_vstrb :: emit_vstrb_q_mem -inst_vstrh :: inst_vstrh_q_mem -emit_vstrh :: emit_vstrh_q_mem -inst_vstrw :: inst_vstrw_q_mem -emit_vstrw :: emit_vstrw_q_mem -inst_vstrd :: inst_vstrd_q_mem -emit_vstrd :: emit_vstrd_q_mem -inst_vld20 :: inst_vld20_qlist_mem -emit_vld20 :: emit_vld20_qlist_mem -inst_vld21 :: inst_vld21_qlist_mem -emit_vld21 :: emit_vld21_qlist_mem -inst_vld40 :: inst_vld40_qlist_mem -emit_vld40 :: emit_vld40_qlist_mem -inst_vld41 :: inst_vld41_qlist_mem -emit_vld41 :: emit_vld41_qlist_mem -inst_vld42 :: inst_vld42_qlist_mem -emit_vld42 :: emit_vld42_qlist_mem -inst_vld43 :: inst_vld43_qlist_mem -emit_vld43 :: emit_vld43_qlist_mem -inst_vst20 :: inst_vst20_qlist_mem -emit_vst20 :: emit_vst20_qlist_mem -inst_vst21 :: inst_vst21_qlist_mem -emit_vst21 :: emit_vst21_qlist_mem -inst_vst40 :: inst_vst40_qlist_mem -emit_vst40 :: emit_vst40_qlist_mem -inst_vst41 :: inst_vst41_qlist_mem -emit_vst41 :: emit_vst41_qlist_mem -inst_vst42 :: inst_vst42_qlist_mem -emit_vst42 :: emit_vst42_qlist_mem -inst_vst43 :: inst_vst43_qlist_mem -emit_vst43 :: emit_vst43_qlist_mem +inst_and :: proc{ inst_and_r_r_immm, inst_and_r_r_rsh, inst_and_r_r_rsr, inst_and_rlo_rlo } +emit_and :: proc{ emit_and_r_r_immm, emit_and_r_r_rsh, emit_and_r_r_rsr, emit_and_rlo_rlo } +inst_eor :: proc{ inst_eor_r_r_immm, inst_eor_r_r_rsh, inst_eor_r_r_rsr, inst_eor_rlo_rlo } +emit_eor :: proc{ emit_eor_r_r_immm, emit_eor_r_r_rsh, emit_eor_r_r_rsr, emit_eor_rlo_rlo } +inst_sub :: proc{ inst_sub_r_r_immm, inst_sub_r_r_rsh, inst_sub_r_r_rsr, inst_sub_rlo_rlo_rlo, inst_sub_rlo_imm8 } +emit_sub :: proc{ emit_sub_r_r_immm, emit_sub_r_r_rsh, emit_sub_r_r_rsr, emit_sub_rlo_rlo_rlo, emit_sub_rlo_imm8 } +inst_rsb :: proc{ inst_rsb_r_r_immm, inst_rsb_r_r_rsh, inst_rsb_r_r_rsr } +emit_rsb :: proc{ emit_rsb_r_r_immm, emit_rsb_r_r_rsh, emit_rsb_r_r_rsr } +inst_add :: proc{ inst_add_r_r_immm, inst_add_r_r_rsh, inst_add_r_r_rsr, inst_add_rlo_rlo_rlo, inst_add_rlo_imm8, inst_add_r_r } +emit_add :: proc{ emit_add_r_r_immm, emit_add_r_r_rsh, emit_add_r_r_rsr, emit_add_rlo_rlo_rlo, emit_add_rlo_imm8, emit_add_r_r } +inst_adc :: proc{ inst_adc_r_r_immm, inst_adc_r_r_rsh, inst_adc_r_r_rsr, inst_adc_rlo_rlo } +emit_adc :: proc{ emit_adc_r_r_immm, emit_adc_r_r_rsh, emit_adc_r_r_rsr, emit_adc_rlo_rlo } +inst_sbc :: proc{ inst_sbc_r_r_immm, inst_sbc_r_r_rsh, inst_sbc_r_r_rsr, inst_sbc_rlo_rlo } +emit_sbc :: proc{ emit_sbc_r_r_immm, emit_sbc_r_r_rsh, emit_sbc_r_r_rsr, emit_sbc_rlo_rlo } +inst_rsc :: proc{ inst_rsc_r_r_immm, inst_rsc_r_r_rsh, inst_rsc_r_r_rsr } +emit_rsc :: proc{ emit_rsc_r_r_immm, emit_rsc_r_r_rsh, emit_rsc_r_r_rsr } +inst_tst :: proc{ inst_tst_r_immm, inst_tst_r_rsh, inst_tst_r_rsr, inst_tst_rlo_rlo } +emit_tst :: proc{ emit_tst_r_immm, emit_tst_r_rsh, emit_tst_r_rsr, emit_tst_rlo_rlo } +inst_teq :: proc{ inst_teq_r_immm, inst_teq_r_rsh, inst_teq_r_rsr } +emit_teq :: proc{ emit_teq_r_immm, emit_teq_r_rsh, emit_teq_r_rsr } +inst_cmp :: proc{ inst_cmp_r_immm, inst_cmp_r_rsh, inst_cmp_r_rsr, inst_cmp_rlo_rlo } +emit_cmp :: proc{ emit_cmp_r_immm, emit_cmp_r_rsh, emit_cmp_r_rsr, emit_cmp_rlo_rlo } +inst_cmn :: proc{ inst_cmn_r_immm, inst_cmn_r_rsh, inst_cmn_r_rsr, inst_cmn_rlo_rlo } +emit_cmn :: proc{ emit_cmn_r_immm, emit_cmn_r_rsh, emit_cmn_r_rsr, emit_cmn_rlo_rlo } +inst_orr :: proc{ inst_orr_r_r_immm, inst_orr_r_r_rsh, inst_orr_r_r_rsr, inst_orr_rlo_rlo } +emit_orr :: proc{ emit_orr_r_r_immm, emit_orr_r_r_rsh, emit_orr_r_r_rsr, emit_orr_rlo_rlo } +inst_mov :: proc{ inst_mov_r_immm, inst_mov_r_rsh, inst_mov_r_rsr, inst_mov_r_r } +emit_mov :: proc{ emit_mov_r_immm, emit_mov_r_rsh, emit_mov_r_rsr, emit_mov_r_r } +inst_bic :: proc{ inst_bic_r_r_immm, inst_bic_r_r_rsh, inst_bic_r_r_rsr, inst_bic_rlo_rlo } +emit_bic :: proc{ emit_bic_r_r_immm, emit_bic_r_r_rsh, emit_bic_r_r_rsr, emit_bic_rlo_rlo } +inst_mvn :: proc{ inst_mvn_r_immm, inst_mvn_r_rsh, inst_mvn_r_rsr, inst_mvn_rlo_rlo } +emit_mvn :: proc{ emit_mvn_r_immm, emit_mvn_r_rsh, emit_mvn_r_rsr, emit_mvn_rlo_rlo } +inst_lsl :: proc{ inst_lsl_r_r_imm5, inst_lsl_r_r_r, inst_lsl_rlo_rlo } +emit_lsl :: proc{ emit_lsl_r_r_imm5, emit_lsl_r_r_r, emit_lsl_rlo_rlo } +inst_lsr :: proc{ inst_lsr_r_r_imm5, inst_lsr_r_r_r, inst_lsr_rlo_rlo } +emit_lsr :: proc{ emit_lsr_r_r_imm5, emit_lsr_r_r_r, emit_lsr_rlo_rlo } +inst_asr :: proc{ inst_asr_r_r_imm5, inst_asr_r_r_r, inst_asr_rlo_rlo } +emit_asr :: proc{ emit_asr_r_r_imm5, emit_asr_r_r_r, emit_asr_rlo_rlo } +inst_ror :: proc{ inst_ror_r_r_imm5, inst_ror_r_r_r, inst_ror_rlo_rlo } +emit_ror :: proc{ emit_ror_r_r_imm5, emit_ror_r_r_r, emit_ror_rlo_rlo } +inst_rrx :: inst_rrx_r_r +emit_rrx :: emit_rrx_r_r +inst_adr :: inst_adr_rlo_rel +emit_adr :: emit_adr_rlo_rel +inst_neg :: inst_neg_rlo_rlo +emit_neg :: emit_neg_rlo_rlo +inst_movw :: inst_movw_r_imm16 +emit_movw :: emit_movw_r_imm16 +inst_movt :: inst_movt_r_imm16 +emit_movt :: emit_movt_r_imm16 +inst_bfc :: inst_bfc_r_imm5_imm5w +emit_bfc :: emit_bfc_r_imm5_imm5w +inst_bfi :: inst_bfi_r_r_imm5_imm5w +emit_bfi :: emit_bfi_r_r_imm5_imm5w +inst_sbfx :: inst_sbfx_r_r_imm5_imm5w +emit_sbfx :: emit_sbfx_r_r_imm5_imm5w +inst_ubfx :: inst_ubfx_r_r_imm5_imm5w +emit_ubfx :: emit_ubfx_r_r_imm5_imm5w +inst_sxtb :: inst_sxtb_r_r +emit_sxtb :: emit_sxtb_r_r +inst_sxtb16 :: inst_sxtb16_r_r +emit_sxtb16 :: emit_sxtb16_r_r +inst_sxth :: inst_sxth_r_r +emit_sxth :: emit_sxth_r_r +inst_uxtb :: inst_uxtb_r_r +emit_uxtb :: emit_uxtb_r_r +inst_uxtb16 :: inst_uxtb16_r_r +emit_uxtb16 :: emit_uxtb16_r_r +inst_uxth :: inst_uxth_r_r +emit_uxth :: emit_uxth_r_r +inst_sxtab :: inst_sxtab_r_r_r +emit_sxtab :: emit_sxtab_r_r_r +inst_sxtab16 :: inst_sxtab16_r_r_r +emit_sxtab16 :: emit_sxtab16_r_r_r +inst_sxtah :: inst_sxtah_r_r_r +emit_sxtah :: emit_sxtah_r_r_r +inst_uxtab :: inst_uxtab_r_r_r +emit_uxtab :: emit_uxtab_r_r_r +inst_uxtab16 :: inst_uxtab16_r_r_r +emit_uxtab16 :: emit_uxtab16_r_r_r +inst_uxtah :: inst_uxtah_r_r_r +emit_uxtah :: emit_uxtah_r_r_r +inst_clz :: inst_clz_r_r +emit_clz :: emit_clz_r_r +inst_rbit :: inst_rbit_r_r +emit_rbit :: emit_rbit_r_r +inst_rev :: inst_rev_r_r +emit_rev :: emit_rev_r_r +inst_rev16 :: inst_rev16_r_r +emit_rev16 :: emit_rev16_r_r +inst_revsh :: inst_revsh_r_r +emit_revsh :: emit_revsh_r_r +inst_sel :: inst_sel_r_r_r +emit_sel :: emit_sel_r_r_r +inst_pkhbt :: inst_pkhbt_r_r_rsh +emit_pkhbt :: emit_pkhbt_r_r_rsh +inst_pkhtb :: inst_pkhtb_r_r_rsh +emit_pkhtb :: emit_pkhtb_r_r_rsh +inst_usad8 :: inst_usad8_r_r_r +emit_usad8 :: emit_usad8_r_r_r +inst_usada8 :: inst_usada8_r_r_r_r +emit_usada8 :: emit_usada8_r_r_r_r +inst_ssat :: inst_ssat_r_imm4s_rsh +emit_ssat :: emit_ssat_r_imm4s_rsh +inst_usat :: inst_usat_r_imm4s_rsh +emit_usat :: emit_usat_r_imm4s_rsh +inst_ssat16 :: inst_ssat16_r_imm4s_r +emit_ssat16 :: emit_ssat16_r_imm4s_r +inst_usat16 :: inst_usat16_r_imm4s_r +emit_usat16 :: emit_usat16_r_imm4s_r +inst_qadd :: inst_qadd_r_r_r +emit_qadd :: emit_qadd_r_r_r +inst_qsub :: inst_qsub_r_r_r +emit_qsub :: emit_qsub_r_r_r +inst_qdadd :: inst_qdadd_r_r_r +emit_qdadd :: emit_qdadd_r_r_r +inst_qdsub :: inst_qdsub_r_r_r +emit_qdsub :: emit_qdsub_r_r_r +inst_sadd8 :: inst_sadd8_r_r_r +emit_sadd8 :: emit_sadd8_r_r_r +inst_sadd16 :: inst_sadd16_r_r_r +emit_sadd16 :: emit_sadd16_r_r_r +inst_sasx :: inst_sasx_r_r_r +emit_sasx :: emit_sasx_r_r_r +inst_ssax :: inst_ssax_r_r_r +emit_ssax :: emit_ssax_r_r_r +inst_ssub8 :: inst_ssub8_r_r_r +emit_ssub8 :: emit_ssub8_r_r_r +inst_ssub16 :: inst_ssub16_r_r_r +emit_ssub16 :: emit_ssub16_r_r_r +inst_uadd8 :: inst_uadd8_r_r_r +emit_uadd8 :: emit_uadd8_r_r_r +inst_uadd16 :: inst_uadd16_r_r_r +emit_uadd16 :: emit_uadd16_r_r_r +inst_uasx :: inst_uasx_r_r_r +emit_uasx :: emit_uasx_r_r_r +inst_usax :: inst_usax_r_r_r +emit_usax :: emit_usax_r_r_r +inst_usub8 :: inst_usub8_r_r_r +emit_usub8 :: emit_usub8_r_r_r +inst_usub16 :: inst_usub16_r_r_r +emit_usub16 :: emit_usub16_r_r_r +inst_qadd8 :: inst_qadd8_r_r_r +emit_qadd8 :: emit_qadd8_r_r_r +inst_qadd16 :: inst_qadd16_r_r_r +emit_qadd16 :: emit_qadd16_r_r_r +inst_qasx :: inst_qasx_r_r_r +emit_qasx :: emit_qasx_r_r_r +inst_qsax :: inst_qsax_r_r_r +emit_qsax :: emit_qsax_r_r_r +inst_qsub8 :: inst_qsub8_r_r_r +emit_qsub8 :: emit_qsub8_r_r_r +inst_qsub16 :: inst_qsub16_r_r_r +emit_qsub16 :: emit_qsub16_r_r_r +inst_uqadd8 :: inst_uqadd8_r_r_r +emit_uqadd8 :: emit_uqadd8_r_r_r +inst_uqadd16 :: inst_uqadd16_r_r_r +emit_uqadd16 :: emit_uqadd16_r_r_r +inst_uqasx :: inst_uqasx_r_r_r +emit_uqasx :: emit_uqasx_r_r_r +inst_uqsax :: inst_uqsax_r_r_r +emit_uqsax :: emit_uqsax_r_r_r +inst_uqsub8 :: inst_uqsub8_r_r_r +emit_uqsub8 :: emit_uqsub8_r_r_r +inst_uqsub16 :: inst_uqsub16_r_r_r +emit_uqsub16 :: emit_uqsub16_r_r_r +inst_shadd8 :: inst_shadd8_r_r_r +emit_shadd8 :: emit_shadd8_r_r_r +inst_shadd16 :: inst_shadd16_r_r_r +emit_shadd16 :: emit_shadd16_r_r_r +inst_shasx :: inst_shasx_r_r_r +emit_shasx :: emit_shasx_r_r_r +inst_shsax :: inst_shsax_r_r_r +emit_shsax :: emit_shsax_r_r_r +inst_shsub8 :: inst_shsub8_r_r_r +emit_shsub8 :: emit_shsub8_r_r_r +inst_shsub16 :: inst_shsub16_r_r_r +emit_shsub16 :: emit_shsub16_r_r_r +inst_uhadd8 :: inst_uhadd8_r_r_r +emit_uhadd8 :: emit_uhadd8_r_r_r +inst_uhadd16 :: inst_uhadd16_r_r_r +emit_uhadd16 :: emit_uhadd16_r_r_r +inst_uhasx :: inst_uhasx_r_r_r +emit_uhasx :: emit_uhasx_r_r_r +inst_uhsax :: inst_uhsax_r_r_r +emit_uhsax :: emit_uhsax_r_r_r +inst_uhsub8 :: inst_uhsub8_r_r_r +emit_uhsub8 :: emit_uhsub8_r_r_r +inst_uhsub16 :: inst_uhsub16_r_r_r +emit_uhsub16 :: emit_uhsub16_r_r_r +inst_smuad :: inst_smuad_r_r_r +emit_smuad :: emit_smuad_r_r_r +inst_smuadx :: inst_smuadx_r_r_r +emit_smuadx :: emit_smuadx_r_r_r +inst_smusd :: inst_smusd_r_r_r +emit_smusd :: emit_smusd_r_r_r +inst_smusdx :: inst_smusdx_r_r_r +emit_smusdx :: emit_smusdx_r_r_r +inst_smlad :: inst_smlad_r_r_r_r +emit_smlad :: emit_smlad_r_r_r_r +inst_smladx :: inst_smladx_r_r_r_r +emit_smladx :: emit_smladx_r_r_r_r +inst_smlsd :: inst_smlsd_r_r_r_r +emit_smlsd :: emit_smlsd_r_r_r_r +inst_smlsdx :: inst_smlsdx_r_r_r_r +emit_smlsdx :: emit_smlsdx_r_r_r_r +inst_smlald :: inst_smlald_r_r_r_r +emit_smlald :: emit_smlald_r_r_r_r +inst_smlaldx :: inst_smlaldx_r_r_r_r +emit_smlaldx :: emit_smlaldx_r_r_r_r +inst_smlsld :: inst_smlsld_r_r_r_r +emit_smlsld :: emit_smlsld_r_r_r_r +inst_smlsldx :: inst_smlsldx_r_r_r_r +emit_smlsldx :: emit_smlsldx_r_r_r_r +inst_smmul :: inst_smmul_r_r_r +emit_smmul :: emit_smmul_r_r_r +inst_smmulr :: inst_smmulr_r_r_r +emit_smmulr :: emit_smmulr_r_r_r +inst_smmla :: inst_smmla_r_r_r_r +emit_smmla :: emit_smmla_r_r_r_r +inst_smmlar :: inst_smmlar_r_r_r_r +emit_smmlar :: emit_smmlar_r_r_r_r +inst_smmls :: inst_smmls_r_r_r_r +emit_smmls :: emit_smmls_r_r_r_r +inst_smmlsr :: inst_smmlsr_r_r_r_r +emit_smmlsr :: emit_smmlsr_r_r_r_r +inst_mul :: proc{ inst_mul_r_r_r, inst_mul_rlo_rlo } +emit_mul :: proc{ emit_mul_r_r_r, emit_mul_rlo_rlo } +inst_mla :: inst_mla_r_r_r_r +emit_mla :: emit_mla_r_r_r_r +inst_mls :: inst_mls_r_r_r_r +emit_mls :: emit_mls_r_r_r_r +inst_umull :: inst_umull_r_r_r_r +emit_umull :: emit_umull_r_r_r_r +inst_umlal :: inst_umlal_r_r_r_r +emit_umlal :: emit_umlal_r_r_r_r +inst_smull :: inst_smull_r_r_r_r +emit_smull :: emit_smull_r_r_r_r +inst_smlal :: inst_smlal_r_r_r_r +emit_smlal :: emit_smlal_r_r_r_r +inst_umaal :: inst_umaal_r_r_r_r +emit_umaal :: emit_umaal_r_r_r_r +inst_smlabb :: inst_smlabb_r_r_r_r +emit_smlabb :: emit_smlabb_r_r_r_r +inst_smlabt :: inst_smlabt_r_r_r_r +emit_smlabt :: emit_smlabt_r_r_r_r +inst_smlatb :: inst_smlatb_r_r_r_r +emit_smlatb :: emit_smlatb_r_r_r_r +inst_smlatt :: inst_smlatt_r_r_r_r +emit_smlatt :: emit_smlatt_r_r_r_r +inst_smlawb :: inst_smlawb_r_r_r_r +emit_smlawb :: emit_smlawb_r_r_r_r +inst_smlawt :: inst_smlawt_r_r_r_r +emit_smlawt :: emit_smlawt_r_r_r_r +inst_smulbb :: inst_smulbb_r_r_r +emit_smulbb :: emit_smulbb_r_r_r +inst_smulbt :: inst_smulbt_r_r_r +emit_smulbt :: emit_smulbt_r_r_r +inst_smultb :: inst_smultb_r_r_r +emit_smultb :: emit_smultb_r_r_r +inst_smultt :: inst_smultt_r_r_r +emit_smultt :: emit_smultt_r_r_r +inst_smulwb :: inst_smulwb_r_r_r +emit_smulwb :: emit_smulwb_r_r_r +inst_smulwt :: inst_smulwt_r_r_r +emit_smulwt :: emit_smulwt_r_r_r +inst_smlalbb :: inst_smlalbb_r_r_r_r +emit_smlalbb :: emit_smlalbb_r_r_r_r +inst_smlalbt :: inst_smlalbt_r_r_r_r +emit_smlalbt :: emit_smlalbt_r_r_r_r +inst_smlaltb :: inst_smlaltb_r_r_r_r +emit_smlaltb :: emit_smlaltb_r_r_r_r +inst_smlaltt :: inst_smlaltt_r_r_r_r +emit_smlaltt :: emit_smlaltt_r_r_r_r +inst_sdiv :: inst_sdiv_r_r_r +emit_sdiv :: emit_sdiv_r_r_r +inst_udiv :: inst_udiv_r_r_r +emit_udiv :: emit_udiv_r_r_r +inst_b :: proc{ inst_b_rel, inst_b_rel_cond } +emit_b :: proc{ emit_b_rel, emit_b_rel_cond } +inst_bl :: inst_bl_rel +emit_bl :: emit_bl_rel +inst_bx :: inst_bx_r +emit_bx :: emit_bx_r +inst_blx :: proc{ inst_blx_r, inst_blx_rel } +emit_blx :: proc{ emit_blx_r, emit_blx_rel } +inst_bxj :: inst_bxj_r +emit_bxj :: emit_bxj_r +inst_cbz :: inst_cbz_rlo_rel +emit_cbz :: emit_cbz_rlo_rel +inst_cbnz :: inst_cbnz_rlo_rel +emit_cbnz :: emit_cbnz_rlo_rel +inst_tbb :: inst_tbb_r_r +emit_tbb :: emit_tbb_r_r +inst_tbh :: inst_tbh_r_r +emit_tbh :: emit_tbh_r_r +inst_msr :: proc{ inst_msr_psr_immm, inst_msr_psr_r } +emit_msr :: proc{ emit_msr_psr_immm, emit_msr_psr_r } +inst_mrs :: inst_mrs_r_psr +emit_mrs :: emit_mrs_r_psr +inst_cps :: inst_cps_ifl +emit_cps :: emit_cps_ifl +inst_setend :: inst_setend_end +emit_setend :: emit_setend_end +inst_nop :: inst_nop_none +emit_nop :: emit_nop_none +inst_yield :: inst_yield_none +emit_yield :: emit_yield_none +inst_wfe :: inst_wfe_none +emit_wfe :: emit_wfe_none +inst_wfi :: inst_wfi_none +emit_wfi :: emit_wfi_none +inst_sev :: inst_sev_none +emit_sev :: emit_sev_none +inst_sevl :: inst_sevl_none +emit_sevl :: emit_sevl_none +inst_dbg :: inst_dbg_hint +emit_dbg :: emit_dbg_hint +inst_hint :: inst_hint_hint +emit_hint :: emit_hint_hint +inst_dmb :: inst_dmb_barr +emit_dmb :: emit_dmb_barr +inst_dsb :: inst_dsb_barr +emit_dsb :: emit_dsb_barr +inst_isb :: inst_isb_barr +emit_isb :: emit_isb_barr +inst_clrex :: inst_clrex_none +emit_clrex :: emit_clrex_none +inst_pld :: inst_pld_mem +emit_pld :: emit_pld_mem +inst_pldw :: inst_pldw_mem +emit_pldw :: emit_pldw_mem +inst_pli :: inst_pli_mem +emit_pli :: emit_pli_mem +inst_hlt :: inst_hlt_imm +emit_hlt :: emit_hlt_imm +inst_dcps1 :: inst_dcps1_none +emit_dcps1 :: emit_dcps1_none +inst_dcps2 :: inst_dcps2_none +emit_dcps2 :: emit_dcps2_none +inst_dcps3 :: inst_dcps3_none +emit_dcps3 :: emit_dcps3_none +inst_eret :: inst_eret_none +emit_eret :: emit_eret_none +inst_esb :: inst_esb_none +emit_esb :: emit_esb_none +inst_psb_csync :: inst_psb_csync_none +emit_psb_csync :: emit_psb_csync_none +inst_tsb_csync :: inst_tsb_csync_none +emit_tsb_csync :: emit_tsb_csync_none +inst_csdb :: inst_csdb_none +emit_csdb :: emit_csdb_none +inst_sb :: inst_sb_none +emit_sb :: emit_sb_none +inst_setpan :: inst_setpan_hint +emit_setpan :: emit_setpan_hint +inst_svc :: inst_svc_imm +emit_svc :: emit_svc_imm +inst_bkpt :: inst_bkpt_imm +emit_bkpt :: emit_bkpt_imm +inst_hvc :: inst_hvc_imm +emit_hvc :: emit_hvc_imm +inst_smc :: inst_smc_imm +emit_smc :: emit_smc_imm +inst_udf :: inst_udf_imm +emit_udf :: emit_udf_imm +inst_ldr :: inst_ldr_r_mem +emit_ldr :: emit_ldr_r_mem +inst_str :: inst_str_r_mem +emit_str :: emit_str_r_mem +inst_ldrb :: inst_ldrb_r_mem +emit_ldrb :: emit_ldrb_r_mem +inst_strb :: inst_strb_r_mem +emit_strb :: emit_strb_r_mem +inst_ldrh :: inst_ldrh_r_mem +emit_ldrh :: emit_ldrh_r_mem +inst_strh :: inst_strh_r_mem +emit_strh :: emit_strh_r_mem +inst_ldrsb :: inst_ldrsb_r_mem +emit_ldrsb :: emit_ldrsb_r_mem +inst_ldrsh :: inst_ldrsh_r_mem +emit_ldrsh :: emit_ldrsh_r_mem +inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem } +emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem } +inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem } +emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem } +inst_ldrt :: inst_ldrt_r_mem +emit_ldrt :: emit_ldrt_r_mem +inst_strt :: inst_strt_r_mem +emit_strt :: emit_strt_r_mem +inst_ldrbt :: inst_ldrbt_r_mem +emit_ldrbt :: emit_ldrbt_r_mem +inst_strbt :: inst_strbt_r_mem +emit_strbt :: emit_strbt_r_mem +inst_ldrht :: inst_ldrht_r_mem +emit_ldrht :: emit_ldrht_r_mem +inst_strht :: inst_strht_r_mem +emit_strht :: emit_strht_r_mem +inst_ldrsbt :: inst_ldrsbt_r_mem +emit_ldrsbt :: emit_ldrsbt_r_mem +inst_ldrsht :: inst_ldrsht_r_mem +emit_ldrsht :: emit_ldrsht_r_mem +inst_lda :: inst_lda_r_mem +emit_lda :: emit_lda_r_mem +inst_stl :: inst_stl_r_mem +emit_stl :: emit_stl_r_mem +inst_ldab :: inst_ldab_r_mem +emit_ldab :: emit_ldab_r_mem +inst_stlb :: inst_stlb_r_mem +emit_stlb :: emit_stlb_r_mem +inst_ldah :: inst_ldah_r_mem +emit_ldah :: emit_ldah_r_mem +inst_stlh :: inst_stlh_r_mem +emit_stlh :: emit_stlh_r_mem +inst_ldrex :: inst_ldrex_r_mem +emit_ldrex :: emit_ldrex_r_mem +inst_strex :: inst_strex_r_r_mem +emit_strex :: emit_strex_r_r_mem +inst_ldrexb :: inst_ldrexb_r_mem +emit_ldrexb :: emit_ldrexb_r_mem +inst_strexb :: inst_strexb_r_r_mem +emit_strexb :: emit_strexb_r_r_mem +inst_ldrexh :: inst_ldrexh_r_mem +emit_ldrexh :: emit_ldrexh_r_mem +inst_strexh :: inst_strexh_r_r_mem +emit_strexh :: emit_strexh_r_r_mem +inst_ldrexd :: proc{ inst_ldrexd_r_mem, inst_ldrexd_r_r_mem } +emit_ldrexd :: proc{ emit_ldrexd_r_mem, emit_ldrexd_r_r_mem } +inst_strexd :: proc{ inst_strexd_r_r_mem, inst_strexd_r_r_r_mem } +emit_strexd :: proc{ emit_strexd_r_r_mem, emit_strexd_r_r_r_mem } +inst_ldaex :: inst_ldaex_r_mem +emit_ldaex :: emit_ldaex_r_mem +inst_stlex :: inst_stlex_r_r_mem +emit_stlex :: emit_stlex_r_r_mem +inst_ldaexb :: inst_ldaexb_r_mem +emit_ldaexb :: emit_ldaexb_r_mem +inst_stlexb :: inst_stlexb_r_r_mem +emit_stlexb :: emit_stlexb_r_r_mem +inst_ldaexh :: inst_ldaexh_r_mem +emit_ldaexh :: emit_ldaexh_r_mem +inst_stlexh :: inst_stlexh_r_r_mem +emit_stlexh :: emit_stlexh_r_r_mem +inst_ldaexd :: inst_ldaexd_r_mem +emit_ldaexd :: emit_ldaexd_r_mem +inst_stlexd :: inst_stlexd_r_r_mem +emit_stlexd :: emit_stlexd_r_r_mem +inst_ldm :: inst_ldm_r_list +emit_ldm :: emit_ldm_r_list +inst_stm :: inst_stm_r_list +emit_stm :: emit_stm_r_list +inst_push :: inst_push_list +emit_push :: emit_push_list +inst_pop :: inst_pop_list +emit_pop :: emit_pop_list +inst_swp :: inst_swp_r_r_r +emit_swp :: emit_swp_r_r_r +inst_swpb :: inst_swpb_r_r_r +emit_swpb :: emit_swpb_r_r_r +inst_rfe :: inst_rfe_r +emit_rfe :: emit_rfe_r +inst_srs :: inst_srs_imm +emit_srs :: emit_srs_imm +inst_cdp :: inst_cdp_cpn_cpop_crd_crd +emit_cdp :: emit_cdp_cpn_cpop_crd_crd +inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd +emit_cdp2 :: emit_cdp2_cpn_cpop_crd_crd +inst_mcr :: inst_mcr_cpn_cpop_r_crd +emit_mcr :: emit_mcr_cpn_cpop_r_crd +inst_mcr2 :: inst_mcr2_cpn_cpop_r_crd +emit_mcr2 :: emit_mcr2_cpn_cpop_r_crd +inst_mrc :: inst_mrc_cpn_cpop_r_crd +emit_mrc :: emit_mrc_cpn_cpop_r_crd +inst_mrc2 :: inst_mrc2_cpn_cpop_r_crd +emit_mrc2 :: emit_mrc2_cpn_cpop_r_crd +inst_mcrr :: inst_mcrr_cpn_cpop_r_r +emit_mcrr :: emit_mcrr_cpn_cpop_r_r +inst_mcrr2 :: inst_mcrr2_cpn_cpop_r_r +emit_mcrr2 :: emit_mcrr2_cpn_cpop_r_r +inst_mrrc :: inst_mrrc_cpn_cpop_r_r +emit_mrrc :: emit_mrrc_cpn_cpop_r_r +inst_mrrc2 :: inst_mrrc2_cpn_cpop_r_r +emit_mrrc2 :: emit_mrrc2_cpn_cpop_r_r +inst_ldc :: inst_ldc_cpn_crd_mem +emit_ldc :: emit_ldc_cpn_crd_mem +inst_ldc2 :: inst_ldc2_cpn_crd_mem +emit_ldc2 :: emit_ldc2_cpn_crd_mem +inst_stc :: inst_stc_cpn_crd_mem +emit_stc :: emit_stc_cpn_crd_mem +inst_stc2 :: inst_stc2_cpn_crd_mem +emit_stc2 :: emit_stc2_cpn_crd_mem +inst_crc32b :: inst_crc32b_r_r_r +emit_crc32b :: emit_crc32b_r_r_r +inst_crc32h :: inst_crc32h_r_r_r +emit_crc32h :: emit_crc32h_r_r_r +inst_crc32w :: inst_crc32w_r_r_r +emit_crc32w :: emit_crc32w_r_r_r +inst_crc32cb :: inst_crc32cb_r_r_r +emit_crc32cb :: emit_crc32cb_r_r_r +inst_crc32ch :: inst_crc32ch_r_r_r +emit_crc32ch :: emit_crc32ch_r_r_r +inst_crc32cw :: inst_crc32cw_r_r_r +emit_crc32cw :: emit_crc32cw_r_r_r +inst_vadd :: inst_vadd_s_s_s +emit_vadd :: emit_vadd_s_s_s +inst_vsub :: inst_vsub_s_s_s +emit_vsub :: emit_vsub_s_s_s +inst_vmul :: proc{ inst_vmul_s_s_s, inst_vmul_d_d_dlane } +emit_vmul :: proc{ emit_vmul_s_s_s, emit_vmul_d_d_dlane } +inst_vdiv :: inst_vdiv_s_s_s +emit_vdiv :: emit_vdiv_s_s_s +inst_vmla :: proc{ inst_vmla_s_s_s, inst_vmla_d_d_dlane } +emit_vmla :: proc{ emit_vmla_s_s_s, emit_vmla_d_d_dlane } +inst_vmls :: proc{ inst_vmls_s_s_s, inst_vmls_d_d_dlane } +emit_vmls :: proc{ emit_vmls_s_s_s, emit_vmls_d_d_dlane } +inst_vnmul :: inst_vnmul_s_s_s +emit_vnmul :: emit_vnmul_s_s_s +inst_vnmla :: inst_vnmla_s_s_s +emit_vnmla :: emit_vnmla_s_s_s +inst_vnmls :: inst_vnmls_s_s_s +emit_vnmls :: emit_vnmls_s_s_s +inst_vfma :: proc{ inst_vfma_s_s_s, inst_vfma_d_d_dlane } +emit_vfma :: proc{ emit_vfma_s_s_s, emit_vfma_d_d_dlane } +inst_vfms :: proc{ inst_vfms_s_s_s, inst_vfms_d_d_dlane } +emit_vfms :: proc{ emit_vfms_s_s_s, emit_vfms_d_d_dlane } +inst_vfnma :: inst_vfnma_s_s_s +emit_vfnma :: emit_vfnma_s_s_s +inst_vfnms :: inst_vfnms_s_s_s +emit_vfnms :: emit_vfnms_s_s_s +inst_vabs :: inst_vabs_s_s +emit_vabs :: emit_vabs_s_s +inst_vneg :: inst_vneg_s_s +emit_vneg :: emit_vneg_s_s +inst_vsqrt :: inst_vsqrt_s_s +emit_vsqrt :: emit_vsqrt_s_s +inst_vcmp :: proc{ inst_vcmp_s_s, inst_vcmp_s } +emit_vcmp :: proc{ emit_vcmp_s_s, emit_vcmp_s } +inst_vcmpe :: proc{ inst_vcmpe_s_s, inst_vcmpe_s } +emit_vcmpe :: proc{ emit_vcmpe_s_s, emit_vcmpe_s } +inst_vcvt :: proc{ inst_vcvt_d_s, inst_vcvt_s_s_imm } +emit_vcvt :: proc{ emit_vcvt_d_s, emit_vcvt_s_s_imm } +inst_vcvtb :: inst_vcvtb_s_s +emit_vcvtb :: emit_vcvtb_s_s +inst_vcvtt :: inst_vcvtt_s_s +emit_vcvtt :: emit_vcvtt_s_s +inst_vcvta :: inst_vcvta_s_s +emit_vcvta :: emit_vcvta_s_s +inst_vcvtn :: inst_vcvtn_s_s +emit_vcvtn :: emit_vcvtn_s_s +inst_vcvtp :: inst_vcvtp_s_s +emit_vcvtp :: emit_vcvtp_s_s +inst_vcvtm :: inst_vcvtm_s_s +emit_vcvtm :: emit_vcvtm_s_s +inst_vcvtr :: inst_vcvtr_s_s +emit_vcvtr :: emit_vcvtr_s_s +inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r, inst_vmov_qlane_qlane_r_r } +emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r, emit_vmov_qlane_qlane_r_r } +inst_vmrs :: inst_vmrs_r +emit_vmrs :: emit_vmrs_r +inst_vmsr :: inst_vmsr_r +emit_vmsr :: emit_vmsr_r +inst_vldr :: inst_vldr_s_mem +emit_vldr :: emit_vldr_s_mem +inst_vstr :: inst_vstr_s_mem +emit_vstr :: emit_vstr_s_mem +inst_vldm :: inst_vldm_r_slist +emit_vldm :: emit_vldm_r_slist +inst_vstm :: inst_vstm_r_slist +emit_vstm :: emit_vstm_r_slist +inst_vpush :: inst_vpush_slist +emit_vpush :: emit_vpush_slist +inst_vpop :: inst_vpop_slist +emit_vpop :: emit_vpop_slist +inst_vsel :: inst_vsel_s_s_s_cond +emit_vsel :: emit_vsel_s_s_s_cond +inst_vmaxnm :: inst_vmaxnm_s_s_s +emit_vmaxnm :: emit_vmaxnm_s_s_s +inst_vminnm :: inst_vminnm_s_s_s +emit_vminnm :: emit_vminnm_s_s_s +inst_vrinta :: inst_vrinta_s_s +emit_vrinta :: emit_vrinta_s_s +inst_vrintn :: inst_vrintn_s_s +emit_vrintn :: emit_vrintn_s_s +inst_vrintp :: inst_vrintp_s_s +emit_vrintp :: emit_vrintp_s_s +inst_vrintm :: inst_vrintm_s_s +emit_vrintm :: emit_vrintm_s_s +inst_vrintr :: inst_vrintr_s_s +emit_vrintr :: emit_vrintr_s_s +inst_vrintz :: inst_vrintz_s_s +emit_vrintz :: emit_vrintz_s_s +inst_vrintx :: inst_vrintx_s_s +emit_vrintx :: emit_vrintx_s_s +inst_vaddl :: inst_vaddl_q_d_d +emit_vaddl :: emit_vaddl_q_d_d +inst_vaddw :: inst_vaddw_q_q_d +emit_vaddw :: emit_vaddw_q_q_d +inst_vsubl :: inst_vsubl_q_d_d +emit_vsubl :: emit_vsubl_q_d_d +inst_vsubw :: inst_vsubw_q_q_d +emit_vsubw :: emit_vsubw_q_q_d +inst_vhadd :: inst_vhadd_d_d_d +emit_vhadd :: emit_vhadd_d_d_d +inst_vhsub :: inst_vhsub_d_d_d +emit_vhsub :: emit_vhsub_d_d_d +inst_vrhadd :: inst_vrhadd_d_d_d +emit_vrhadd :: emit_vrhadd_d_d_d +inst_vqadd :: inst_vqadd_d_d_d +emit_vqadd :: emit_vqadd_d_d_d +inst_vqsub :: inst_vqsub_d_d_d +emit_vqsub :: emit_vqsub_d_d_d +inst_vmull :: proc{ inst_vmull_q_d_d, inst_vmull_q_d_dlane } +emit_vmull :: proc{ emit_vmull_q_d_d, emit_vmull_q_d_dlane } +inst_vmlal :: proc{ inst_vmlal_q_d_d, inst_vmlal_q_d_dlane } +emit_vmlal :: proc{ emit_vmlal_q_d_d, emit_vmlal_q_d_dlane } +inst_vmlsl :: proc{ inst_vmlsl_q_d_d, inst_vmlsl_q_d_dlane } +emit_vmlsl :: proc{ emit_vmlsl_q_d_d, emit_vmlsl_q_d_dlane } +inst_vqdmull :: proc{ inst_vqdmull_q_d_d, inst_vqdmull_q_d_dlane } +emit_vqdmull :: proc{ emit_vqdmull_q_d_d, emit_vqdmull_q_d_dlane } +inst_vqdmlal :: proc{ inst_vqdmlal_q_d_d, inst_vqdmlal_q_d_dlane } +emit_vqdmlal :: proc{ emit_vqdmlal_q_d_d, emit_vqdmlal_q_d_dlane } +inst_vqdmlsl :: proc{ inst_vqdmlsl_q_d_d, inst_vqdmlsl_q_d_dlane } +emit_vqdmlsl :: proc{ emit_vqdmlsl_q_d_d, emit_vqdmlsl_q_d_dlane } +inst_vqdmulh :: proc{ inst_vqdmulh_d_d_d, inst_vqdmulh_d_d_dlane } +emit_vqdmulh :: proc{ emit_vqdmulh_d_d_d, emit_vqdmulh_d_d_dlane } +inst_vqrdmulh :: proc{ inst_vqrdmulh_d_d_d, inst_vqrdmulh_d_d_dlane } +emit_vqrdmulh :: proc{ emit_vqrdmulh_d_d_d, emit_vqrdmulh_d_d_dlane } +inst_vqrdmlah :: proc{ inst_vqrdmlah_d_d_d, inst_vqrdmlah_d_d_dlane } +emit_vqrdmlah :: proc{ emit_vqrdmlah_d_d_d, emit_vqrdmlah_d_d_dlane } +inst_vqrdmlsh :: proc{ inst_vqrdmlsh_d_d_d, inst_vqrdmlsh_d_d_dlane } +emit_vqrdmlsh :: proc{ emit_vqrdmlsh_d_d_d, emit_vqrdmlsh_d_d_dlane } +inst_vaba :: inst_vaba_d_d_d +emit_vaba :: emit_vaba_d_d_d +inst_vabal :: inst_vabal_q_d_d +emit_vabal :: emit_vabal_q_d_d +inst_vabd :: inst_vabd_d_d_d +emit_vabd :: emit_vabd_d_d_d +inst_vabdl :: inst_vabdl_q_d_d +emit_vabdl :: emit_vabdl_q_d_d +inst_vand :: inst_vand_d_d_d +emit_vand :: emit_vand_d_d_d +inst_vbic :: inst_vbic_d_d_d +emit_vbic :: emit_vbic_d_d_d +inst_vorr :: inst_vorr_d_d_d +emit_vorr :: emit_vorr_d_d_d +inst_vorn :: inst_vorn_d_d_d +emit_vorn :: emit_vorn_d_d_d +inst_veor :: inst_veor_d_d_d +emit_veor :: emit_veor_d_d_d +inst_vbsl :: inst_vbsl_d_d_d +emit_vbsl :: emit_vbsl_d_d_d +inst_vbit :: inst_vbit_d_d_d +emit_vbit :: emit_vbit_d_d_d +inst_vbif :: inst_vbif_d_d_d +emit_vbif :: emit_vbif_d_d_d +inst_vmvn :: proc{ inst_vmvn_d_d, inst_vmvn_d_imm } +emit_vmvn :: proc{ emit_vmvn_d_d, emit_vmvn_d_imm } +inst_vmovn :: inst_vmovn_d_q +emit_vmovn :: emit_vmovn_d_q +inst_vqmovn :: inst_vqmovn_d_q +emit_vqmovn :: emit_vqmovn_d_q +inst_vqmovun :: inst_vqmovun_d_q +emit_vqmovun :: emit_vqmovun_d_q +inst_vmovl :: inst_vmovl_q_d +emit_vmovl :: emit_vmovl_q_d +inst_vtst :: inst_vtst_d_d_d +emit_vtst :: emit_vtst_d_d_d +inst_vceq :: proc{ inst_vceq_d_d_d, inst_vceq_d_d } +emit_vceq :: proc{ emit_vceq_d_d_d, emit_vceq_d_d } +inst_vcge :: proc{ inst_vcge_d_d_d, inst_vcge_d_d } +emit_vcge :: proc{ emit_vcge_d_d_d, emit_vcge_d_d } +inst_vcgt :: proc{ inst_vcgt_d_d_d, inst_vcgt_d_d } +emit_vcgt :: proc{ emit_vcgt_d_d_d, emit_vcgt_d_d } +inst_vcle :: proc{ inst_vcle_d_d_d, inst_vcle_d_d } +emit_vcle :: proc{ emit_vcle_d_d_d, emit_vcle_d_d } +inst_vclt :: proc{ inst_vclt_d_d_d, inst_vclt_d_d } +emit_vclt :: proc{ emit_vclt_d_d_d, emit_vclt_d_d } +inst_vacge :: inst_vacge_d_d_d +emit_vacge :: emit_vacge_d_d_d +inst_vacgt :: inst_vacgt_d_d_d +emit_vacgt :: emit_vacgt_d_d_d +inst_vacle :: inst_vacle_d_d_d +emit_vacle :: emit_vacle_d_d_d +inst_vaclt :: inst_vaclt_d_d_d +emit_vaclt :: emit_vaclt_d_d_d +inst_vmax :: inst_vmax_d_d_d +emit_vmax :: emit_vmax_d_d_d +inst_vmin :: inst_vmin_d_d_d +emit_vmin :: emit_vmin_d_d_d +inst_vpmax :: inst_vpmax_d_d_d +emit_vpmax :: emit_vpmax_d_d_d +inst_vpmin :: inst_vpmin_d_d_d +emit_vpmin :: emit_vpmin_d_d_d +inst_vpadd :: inst_vpadd_d_d_d +emit_vpadd :: emit_vpadd_d_d_d +inst_vpaddl :: inst_vpaddl_d_d +emit_vpaddl :: emit_vpaddl_d_d +inst_vpadal :: inst_vpadal_d_d +emit_vpadal :: emit_vpadal_d_d +inst_vrecpe :: inst_vrecpe_d_d +emit_vrecpe :: emit_vrecpe_d_d +inst_vrecps :: inst_vrecps_d_d_d +emit_vrecps :: emit_vrecps_d_d_d +inst_vrsqrte :: inst_vrsqrte_d_d +emit_vrsqrte :: emit_vrsqrte_d_d +inst_vrsqrts :: inst_vrsqrts_d_d_d +emit_vrsqrts :: emit_vrsqrts_d_d_d +inst_vshl :: inst_vshl_d_d_d +emit_vshl :: emit_vshl_d_d_d +inst_vshr :: inst_vshr_d_d_imm +emit_vshr :: emit_vshr_d_d_imm +inst_vsra :: inst_vsra_d_d_imm +emit_vsra :: emit_vsra_d_d_imm +inst_vrshl :: inst_vrshl_d_d_d +emit_vrshl :: emit_vrshl_d_d_d +inst_vrshr :: inst_vrshr_d_d_imm +emit_vrshr :: emit_vrshr_d_d_imm +inst_vrsra :: inst_vrsra_d_d_imm +emit_vrsra :: emit_vrsra_d_d_imm +inst_vsli :: inst_vsli_d_d_imm +emit_vsli :: emit_vsli_d_d_imm +inst_vsri :: inst_vsri_d_d_imm +emit_vsri :: emit_vsri_d_d_imm +inst_vqshl :: proc{ inst_vqshl_d_d_d, inst_vqshl_d_d_imm } +emit_vqshl :: proc{ emit_vqshl_d_d_d, emit_vqshl_d_d_imm } +inst_vqshrn :: inst_vqshrn_d_q_imm +emit_vqshrn :: emit_vqshrn_d_q_imm +inst_vqshrun :: inst_vqshrun_d_q_imm +emit_vqshrun :: emit_vqshrun_d_q_imm +inst_vqrshl :: inst_vqrshl_d_d_d +emit_vqrshl :: emit_vqrshl_d_d_d +inst_vqrshrn :: inst_vqrshrn_d_q_imm +emit_vqrshrn :: emit_vqrshrn_d_q_imm +inst_vqrshrun :: inst_vqrshrun_d_q_imm +emit_vqrshrun :: emit_vqrshrun_d_q_imm +inst_vshrn :: inst_vshrn_d_q_imm +emit_vshrn :: emit_vshrn_d_q_imm +inst_vrshrn :: inst_vrshrn_d_q_imm +emit_vrshrn :: emit_vrshrn_d_q_imm +inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d } +emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d } +inst_vcls :: inst_vcls_d_d +emit_vcls :: emit_vcls_d_d +inst_vclz :: inst_vclz_d_d +emit_vclz :: emit_vclz_d_d +inst_vcnt :: inst_vcnt_d_d +emit_vcnt :: emit_vcnt_d_d +inst_vpadd_f :: inst_vpadd_f_d_d_d +emit_vpadd_f :: emit_vpadd_f_d_d_d +inst_vrecpe_f :: inst_vrecpe_f_d_d +emit_vrecpe_f :: emit_vrecpe_f_d_d +inst_vrsqrte_f :: inst_vrsqrte_f_d_d +emit_vrsqrte_f :: emit_vrsqrte_f_d_d +inst_vrev16 :: inst_vrev16_d_d +emit_vrev16 :: emit_vrev16_d_d +inst_vrev32 :: inst_vrev32_d_d +emit_vrev32 :: emit_vrev32_d_d +inst_vrev64 :: inst_vrev64_d_d +emit_vrev64 :: emit_vrev64_d_d +inst_vext :: inst_vext_d_d_d_imm4 +emit_vext :: emit_vext_d_d_d_imm4 +inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d } +emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d } +inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d } +emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d } +inst_vtrn :: inst_vtrn_d_d +emit_vtrn :: emit_vtrn_d_d +inst_vuzp :: inst_vuzp_d_d +emit_vuzp :: emit_vuzp_d_d +inst_vzip :: inst_vzip_d_d +emit_vzip :: emit_vzip_d_d +inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane } +emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane } +inst_vswp :: inst_vswp_d_d +emit_vswp :: emit_vswp_d_d +inst_vmov_lane :: inst_vmov_lane_dlane_r +emit_vmov_lane :: emit_vmov_lane_dlane_r +inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem } +emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem } +inst_vld2 :: inst_vld2_dlist_mem +emit_vld2 :: emit_vld2_dlist_mem +inst_vld3 :: inst_vld3_dlist_mem +emit_vld3 :: emit_vld3_dlist_mem +inst_vld4 :: inst_vld4_dlist_mem +emit_vld4 :: emit_vld4_dlist_mem +inst_vst1 :: proc{ inst_vst1_dlist_mem, inst_vst1_dlane_mem } +emit_vst1 :: proc{ emit_vst1_dlist_mem, emit_vst1_dlane_mem } +inst_vst2 :: inst_vst2_dlist_mem +emit_vst2 :: emit_vst2_dlist_mem +inst_vst3 :: inst_vst3_dlist_mem +emit_vst3 :: emit_vst3_dlist_mem +inst_vst4 :: inst_vst4_dlist_mem +emit_vst4 :: emit_vst4_dlist_mem +inst_aese :: inst_aese_q_q +emit_aese :: emit_aese_q_q +inst_aesd :: inst_aesd_q_q +emit_aesd :: emit_aesd_q_q +inst_aesmc :: inst_aesmc_q_q +emit_aesmc :: emit_aesmc_q_q +inst_aesimc :: inst_aesimc_q_q +emit_aesimc :: emit_aesimc_q_q +inst_sha1h :: inst_sha1h_q_q +emit_sha1h :: emit_sha1h_q_q +inst_sha1su0 :: inst_sha1su0_q_q_q +emit_sha1su0 :: emit_sha1su0_q_q_q +inst_sha1su1 :: inst_sha1su1_q_q +emit_sha1su1 :: emit_sha1su1_q_q +inst_sha1c :: inst_sha1c_q_q_q +emit_sha1c :: emit_sha1c_q_q_q +inst_sha1m :: inst_sha1m_q_q_q +emit_sha1m :: emit_sha1m_q_q_q +inst_sha1p :: inst_sha1p_q_q_q +emit_sha1p :: emit_sha1p_q_q_q +inst_sha256h :: inst_sha256h_q_q_q +emit_sha256h :: emit_sha256h_q_q_q +inst_sha256h2 :: inst_sha256h2_q_q_q +emit_sha256h2 :: emit_sha256h2_q_q_q +inst_sha256su0 :: inst_sha256su0_q_q +emit_sha256su0 :: emit_sha256su0_q_q +inst_sha256su1 :: inst_sha256su1_q_q_q +emit_sha256su1 :: emit_sha256su1_q_q_q +inst_vjcvt :: inst_vjcvt_s_d +emit_vjcvt :: emit_vjcvt_s_d +inst_vsdot :: proc{ inst_vsdot_d_d_d, inst_vsdot_d_d_dlane } +emit_vsdot :: proc{ emit_vsdot_d_d_d, emit_vsdot_d_d_dlane } +inst_vudot :: proc{ inst_vudot_d_d_d, inst_vudot_d_d_dlane } +emit_vudot :: proc{ emit_vudot_d_d_d, emit_vudot_d_d_dlane } +inst_vdot :: inst_vdot_d_d_d +emit_vdot :: emit_vdot_d_d_d +inst_vmmla :: inst_vmmla_q_q_q +emit_vmmla :: emit_vmmla_q_q_q +inst_vfmal :: inst_vfmal_d_d_d +emit_vfmal :: emit_vfmal_d_d_d +inst_vfmsl :: inst_vfmsl_d_d_d +emit_vfmsl :: emit_vfmsl_d_d_d +inst_vcmla :: proc{ inst_vcmla_d_d_d_imm, inst_vcmla_d_d_dlane_imm } +emit_vcmla :: proc{ emit_vcmla_d_d_d_imm, emit_vcmla_d_d_dlane_imm } +inst_vcadd :: inst_vcadd_d_d_d_imm +emit_vcadd :: emit_vcadd_d_d_d_imm +inst_vsmmla :: inst_vsmmla_q_q_q +emit_vsmmla :: emit_vsmmla_q_q_q +inst_vummla :: inst_vummla_q_q_q +emit_vummla :: emit_vummla_q_q_q +inst_vusmmla :: inst_vusmmla_q_q_q +emit_vusmmla :: emit_vusmmla_q_q_q +inst_vsudot :: proc{ inst_vsudot_q_q_q, inst_vsudot_q_q_dlane } +emit_vsudot :: proc{ emit_vsudot_q_q_q, emit_vsudot_q_q_dlane } +inst_vusdot :: proc{ inst_vusdot_d_d_d, inst_vusdot_d_d_dlane } +emit_vusdot :: proc{ emit_vusdot_d_d_d, emit_vusdot_d_d_dlane } +inst_vqabs :: inst_vqabs_q_q +emit_vqabs :: emit_vqabs_q_q +inst_vqneg :: inst_vqneg_q_q +emit_vqneg :: emit_vqneg_q_q +inst_vmovx :: inst_vmovx_s_s +emit_vmovx :: emit_vmovx_s_s +inst_vins :: inst_vins_s_s +emit_vins :: emit_vins_s_s +inst_vld2r :: inst_vld2r_dlist_mem +emit_vld2r :: emit_vld2r_dlist_mem +inst_vld3r :: inst_vld3r_dlist_mem +emit_vld3r :: emit_vld3r_dlist_mem +inst_vld4r :: inst_vld4r_dlist_mem +emit_vld4r :: emit_vld4r_dlist_mem +inst_vld1_lane :: inst_vld1_lane_dlane_mem +emit_vld1_lane :: emit_vld1_lane_dlane_mem +inst_vld2_lane :: inst_vld2_lane_dlist_mem +emit_vld2_lane :: emit_vld2_lane_dlist_mem +inst_vld3_lane :: inst_vld3_lane_dlist_mem +emit_vld3_lane :: emit_vld3_lane_dlist_mem +inst_vld4_lane :: inst_vld4_lane_dlist_mem +emit_vld4_lane :: emit_vld4_lane_dlist_mem +inst_vst1_lane :: inst_vst1_lane_dlane_mem +emit_vst1_lane :: emit_vst1_lane_dlane_mem +inst_vst2_lane :: inst_vst2_lane_dlist_mem +emit_vst2_lane :: emit_vst2_lane_dlist_mem +inst_vst3_lane :: inst_vst3_lane_dlist_mem +emit_vst3_lane :: emit_vst3_lane_dlist_mem +inst_vst4_lane :: inst_vst4_lane_dlist_mem +emit_vst4_lane :: emit_vst4_lane_dlist_mem +inst_it :: inst_it_cond_imm4 +emit_it :: emit_it_cond_imm4 +inst_tt :: inst_tt_r_r +emit_tt :: emit_tt_r_r +inst_ttt :: inst_ttt_r_r +emit_ttt :: emit_ttt_r_r +inst_tta :: inst_tta_r_r +emit_tta :: emit_tta_r_r +inst_ttat :: inst_ttat_r_r +emit_ttat :: emit_ttat_r_r +inst_sg :: inst_sg_none +emit_sg :: emit_sg_none +inst_bxns :: inst_bxns_r +emit_bxns :: emit_bxns_r +inst_blxns :: inst_blxns_r +emit_blxns :: emit_blxns_r +inst_pac :: inst_pac_none +emit_pac :: emit_pac_none +inst_pacbti :: inst_pacbti_none +emit_pacbti :: emit_pacbti_none +inst_aut :: inst_aut_none +emit_aut :: emit_aut_none +inst_autg :: inst_autg_r_r_r +emit_autg :: emit_autg_r_r_r +inst_bti :: inst_bti_none +emit_bti :: emit_bti_none +inst_wls :: inst_wls_r_rel +emit_wls :: emit_wls_r_rel +inst_wlstp :: inst_wlstp_r_rel +emit_wlstp :: emit_wlstp_r_rel +inst_dls :: inst_dls_r +emit_dls :: emit_dls_r +inst_dlstp :: inst_dlstp_r +emit_dlstp :: emit_dlstp_r +inst_le :: inst_le_rel +emit_le :: emit_le_rel +inst_letp :: inst_letp_rel +emit_letp :: emit_letp_rel +inst_lctp :: inst_lctp_none +emit_lctp :: emit_lctp_none +inst_bf :: inst_bf_rel_rel +emit_bf :: emit_bf_rel_rel +inst_bfx :: inst_bfx_rel_r +emit_bfx :: emit_bfx_rel_r +inst_bfl :: inst_bfl_rel_rel +emit_bfl :: emit_bfl_rel_rel +inst_bflx :: inst_bflx_rel_r +emit_bflx :: emit_bflx_rel_r +inst_bfcsel :: inst_bfcsel_rel_rel_imm4 +emit_bfcsel :: emit_bfcsel_rel_rel_imm4 +inst_cx1 :: inst_cx1_cp_r_imm +emit_cx1 :: emit_cx1_cp_r_imm +inst_cx1a :: inst_cx1a_cp_r_imm +emit_cx1a :: emit_cx1a_cp_r_imm +inst_cx1d :: inst_cx1d_cp_r_imm +emit_cx1d :: emit_cx1d_cp_r_imm +inst_cx1da :: inst_cx1da_cp_r_imm +emit_cx1da :: emit_cx1da_cp_r_imm +inst_cx2 :: inst_cx2_cp_r_r_imm +emit_cx2 :: emit_cx2_cp_r_r_imm +inst_cx2a :: inst_cx2a_cp_r_r_imm +emit_cx2a :: emit_cx2a_cp_r_r_imm +inst_cx2d :: inst_cx2d_cp_r_r_imm +emit_cx2d :: emit_cx2d_cp_r_r_imm +inst_cx2da :: inst_cx2da_cp_r_r_imm +emit_cx2da :: emit_cx2da_cp_r_r_imm +inst_cx3 :: inst_cx3_cp_r_r_r +emit_cx3 :: emit_cx3_cp_r_r_r +inst_cx3a :: inst_cx3a_cp_r_r_r +emit_cx3a :: emit_cx3a_cp_r_r_r +inst_cx3d :: inst_cx3d_cp_r_r_r +emit_cx3d :: emit_cx3d_cp_r_r_r +inst_cx3da :: inst_cx3da_cp_r_r_r +emit_cx3da :: emit_cx3da_cp_r_r_r +inst_vcx1 :: inst_vcx1_cp_s_imm +emit_vcx1 :: emit_vcx1_cp_s_imm +inst_vcx1a :: inst_vcx1a_cp_s_imm +emit_vcx1a :: emit_vcx1a_cp_s_imm +inst_vcx2 :: inst_vcx2_cp_s_s_imm +emit_vcx2 :: emit_vcx2_cp_s_s_imm +inst_vcx2a :: inst_vcx2a_cp_s_s_imm +emit_vcx2a :: emit_vcx2a_cp_s_s_imm +inst_vcx3 :: inst_vcx3_cp_s_s_s +emit_vcx3 :: emit_vcx3_cp_s_s_s +inst_vcx3a :: inst_vcx3a_cp_s_s_s +emit_vcx3a :: emit_vcx3a_cp_s_s_s +inst_vpt :: inst_vpt_vpt_cond_q_q +emit_vpt :: emit_vpt_vpt_cond_q_q +inst_vpst :: inst_vpst_vpt +emit_vpst :: emit_vpst_vpt +inst_vpsel :: inst_vpsel_q_q_q +emit_vpsel :: emit_vpsel_q_q_q +inst_vpnot :: inst_vpnot_none +emit_vpnot :: emit_vpnot_none +inst_vctp :: inst_vctp_r +emit_vctp :: emit_vctp_r +inst_vaddv :: inst_vaddv_r_q +emit_vaddv :: emit_vaddv_r_q +inst_vaddva :: inst_vaddva_r_q +emit_vaddva :: emit_vaddva_r_q +inst_vaddlv :: inst_vaddlv_r_r_q +emit_vaddlv :: emit_vaddlv_r_r_q +inst_vaddlva :: inst_vaddlva_r_r_q +emit_vaddlva :: emit_vaddlva_r_r_q +inst_vmaxv :: inst_vmaxv_r_q +emit_vmaxv :: emit_vmaxv_r_q +inst_vmaxav :: inst_vmaxav_r_q +emit_vmaxav :: emit_vmaxav_r_q +inst_vminv :: inst_vminv_r_q +emit_vminv :: emit_vminv_r_q +inst_vminav :: inst_vminav_r_q +emit_vminav :: emit_vminav_r_q +inst_vmaxnmv :: inst_vmaxnmv_r_q +emit_vmaxnmv :: emit_vmaxnmv_r_q +inst_vmaxnmav :: inst_vmaxnmav_r_q +emit_vmaxnmav :: emit_vmaxnmav_r_q +inst_vminnmv :: inst_vminnmv_r_q +emit_vminnmv :: emit_vminnmv_r_q +inst_vminnmav :: inst_vminnmav_r_q +emit_vminnmav :: emit_vminnmav_r_q +inst_vabav :: inst_vabav_r_q_q +emit_vabav :: emit_vabav_r_q_q +inst_vmladav :: inst_vmladav_r_q_q +emit_vmladav :: emit_vmladav_r_q_q +inst_vmladava :: inst_vmladava_r_q_q +emit_vmladava :: emit_vmladava_r_q_q +inst_vmladavx :: inst_vmladavx_r_q_q +emit_vmladavx :: emit_vmladavx_r_q_q +inst_vmladavax :: inst_vmladavax_r_q_q +emit_vmladavax :: emit_vmladavax_r_q_q +inst_vmlaldav :: inst_vmlaldav_r_r_q_q +emit_vmlaldav :: emit_vmlaldav_r_r_q_q +inst_vmlaldava :: inst_vmlaldava_r_r_q_q +emit_vmlaldava :: emit_vmlaldava_r_r_q_q +inst_vmlaldavx :: inst_vmlaldavx_r_r_q_q +emit_vmlaldavx :: emit_vmlaldavx_r_r_q_q +inst_vmlaldavax :: inst_vmlaldavax_r_r_q_q +emit_vmlaldavax :: emit_vmlaldavax_r_r_q_q +inst_vmlsdav :: inst_vmlsdav_r_q_q +emit_vmlsdav :: emit_vmlsdav_r_q_q +inst_vmlsdava :: inst_vmlsdava_r_q_q +emit_vmlsdava :: emit_vmlsdava_r_q_q +inst_vmlsdavx :: inst_vmlsdavx_r_q_q +emit_vmlsdavx :: emit_vmlsdavx_r_q_q +inst_vmlsdavax :: inst_vmlsdavax_r_q_q +emit_vmlsdavax :: emit_vmlsdavax_r_q_q +inst_vmlsldav :: inst_vmlsldav_r_r_q_q +emit_vmlsldav :: emit_vmlsldav_r_r_q_q +inst_vmlsldava :: inst_vmlsldava_r_r_q_q +emit_vmlsldava :: emit_vmlsldava_r_r_q_q +inst_vmlsldavx :: inst_vmlsldavx_r_r_q_q +emit_vmlsldavx :: emit_vmlsldavx_r_r_q_q +inst_vmlsldavax :: inst_vmlsldavax_r_r_q_q +emit_vmlsldavax :: emit_vmlsldavax_r_r_q_q +inst_vrmlaldavh :: inst_vrmlaldavh_r_r_q_q +emit_vrmlaldavh :: emit_vrmlaldavh_r_r_q_q +inst_vrmlaldavha :: inst_vrmlaldavha_r_r_q_q +emit_vrmlaldavha :: emit_vrmlaldavha_r_r_q_q +inst_vrmlaldavhx :: inst_vrmlaldavhx_r_r_q_q +emit_vrmlaldavhx :: emit_vrmlaldavhx_r_r_q_q +inst_vrmlaldavhax :: inst_vrmlaldavhax_r_r_q_q +emit_vrmlaldavhax :: emit_vrmlaldavhax_r_r_q_q +inst_vrmlsldavh :: inst_vrmlsldavh_r_r_q_q +emit_vrmlsldavh :: emit_vrmlsldavh_r_r_q_q +inst_vrmlsldavha :: inst_vrmlsldavha_r_r_q_q +emit_vrmlsldavha :: emit_vrmlsldavha_r_r_q_q +inst_vrmlsldavhx :: inst_vrmlsldavhx_r_r_q_q +emit_vrmlsldavhx :: emit_vrmlsldavhx_r_r_q_q +inst_vrmlsldavhax :: inst_vrmlsldavhax_r_r_q_q +emit_vrmlsldavhax :: emit_vrmlsldavhax_r_r_q_q +inst_vmlav :: inst_vmlav_r_q_q +emit_vmlav :: emit_vmlav_r_q_q +inst_vmlava :: inst_vmlava_r_q_q +emit_vmlava :: emit_vmlava_r_q_q +inst_vmlsv :: inst_vmlsv_r_q_q +emit_vmlsv :: emit_vmlsv_r_q_q +inst_vmlsva :: inst_vmlsva_r_q_q +emit_vmlsva :: emit_vmlsva_r_q_q +inst_vcmul :: inst_vcmul_q_q_q +emit_vcmul :: emit_vcmul_q_q_q +inst_vhcadd :: proc{ inst_vhcadd_q_q_q, inst_vhcadd_q_q_q_imm } +emit_vhcadd :: proc{ emit_vhcadd_q_q_q, emit_vhcadd_q_q_q_imm } +inst_vbrsr :: inst_vbrsr_q_q_r +emit_vbrsr :: emit_vbrsr_q_q_r +inst_vshlc :: inst_vshlc_q_r_imm5 +emit_vshlc :: emit_vshlc_q_r_imm5 +inst_vddup :: inst_vddup_q_r_imm +emit_vddup :: emit_vddup_q_r_imm +inst_vidup :: inst_vidup_q_r_imm +emit_vidup :: emit_vidup_q_r_imm +inst_vdwdup :: inst_vdwdup_q_r_r_imm +emit_vdwdup :: emit_vdwdup_q_r_r_imm +inst_viwdup :: inst_viwdup_q_r_r_imm +emit_viwdup :: emit_viwdup_q_r_r_imm +inst_vmovnb :: inst_vmovnb_q_q +emit_vmovnb :: emit_vmovnb_q_q +inst_vmovnt :: inst_vmovnt_q_q +emit_vmovnt :: emit_vmovnt_q_q +inst_vqmovnb :: inst_vqmovnb_q_q +emit_vqmovnb :: emit_vqmovnb_q_q +inst_vqmovnt :: inst_vqmovnt_q_q +emit_vqmovnt :: emit_vqmovnt_q_q +inst_vqmovunb :: inst_vqmovunb_q_q +emit_vqmovunb :: emit_vqmovunb_q_q +inst_vqmovunt :: inst_vqmovunt_q_q +emit_vqmovunt :: emit_vqmovunt_q_q +inst_vshllb :: inst_vshllb_q_q_imm5 +emit_vshllb :: emit_vshllb_q_q_imm5 +inst_vshllt :: inst_vshllt_q_q_imm5 +emit_vshllt :: emit_vshllt_q_q_imm5 +inst_vmullb :: inst_vmullb_q_q_q +emit_vmullb :: emit_vmullb_q_q_q +inst_vmullt :: inst_vmullt_q_q_q +emit_vmullt :: emit_vmullt_q_q_q +inst_vmlalb :: inst_vmlalb_q_q_q +emit_vmlalb :: emit_vmlalb_q_q_q +inst_vmlalt :: inst_vmlalt_q_q_q +emit_vmlalt :: emit_vmlalt_q_q_q +inst_vmlslb :: inst_vmlslb_q_q_q +emit_vmlslb :: emit_vmlslb_q_q_q +inst_vmlslt :: inst_vmlslt_q_q_q +emit_vmlslt :: emit_vmlslt_q_q_q +inst_vshrnb :: inst_vshrnb_q_q_imm5 +emit_vshrnb :: emit_vshrnb_q_q_imm5 +inst_vshrnt :: inst_vshrnt_q_q_imm5 +emit_vshrnt :: emit_vshrnt_q_q_imm5 +inst_vrshrnb :: inst_vrshrnb_q_q_imm5 +emit_vrshrnb :: emit_vrshrnb_q_q_imm5 +inst_vrshrnt :: inst_vrshrnt_q_q_imm5 +emit_vrshrnt :: emit_vrshrnt_q_q_imm5 +inst_vqshrnb :: inst_vqshrnb_q_q_imm5 +emit_vqshrnb :: emit_vqshrnb_q_q_imm5 +inst_vqshrnt :: inst_vqshrnt_q_q_imm5 +emit_vqshrnt :: emit_vqshrnt_q_q_imm5 +inst_vqrshrnb :: inst_vqrshrnb_q_q_imm5 +emit_vqrshrnb :: emit_vqrshrnb_q_q_imm5 +inst_vqrshrnt :: inst_vqrshrnt_q_q_imm5 +emit_vqrshrnt :: emit_vqrshrnt_q_q_imm5 +inst_vqshrunb :: inst_vqshrunb_q_q_imm5 +emit_vqshrunb :: emit_vqshrunb_q_q_imm5 +inst_vqshrunt :: inst_vqshrunt_q_q_imm5 +emit_vqshrunt :: emit_vqshrunt_q_q_imm5 +inst_vqrshrunb :: inst_vqrshrunb_q_q_imm5 +emit_vqrshrunb :: emit_vqrshrunb_q_q_imm5 +inst_vqrshrunt :: inst_vqrshrunt_q_q_imm5 +emit_vqrshrunt :: emit_vqrshrunt_q_q_imm5 +inst_vqdmladh :: inst_vqdmladh_q_q_q +emit_vqdmladh :: emit_vqdmladh_q_q_q +inst_vqdmladhx :: inst_vqdmladhx_q_q_q +emit_vqdmladhx :: emit_vqdmladhx_q_q_q +inst_vqdmlsdh :: inst_vqdmlsdh_q_q_q +emit_vqdmlsdh :: emit_vqdmlsdh_q_q_q +inst_vqdmlsdhx :: inst_vqdmlsdhx_q_q_q +emit_vqdmlsdhx :: emit_vqdmlsdhx_q_q_q +inst_vqrdmladh :: inst_vqrdmladh_q_q_q +emit_vqrdmladh :: emit_vqrdmladh_q_q_q +inst_vqrdmladhx :: inst_vqrdmladhx_q_q_q +emit_vqrdmladhx :: emit_vqrdmladhx_q_q_q +inst_vqrdmlsdh :: inst_vqrdmlsdh_q_q_q +emit_vqrdmlsdh :: emit_vqrdmlsdh_q_q_q +inst_vqrdmlsdhx :: inst_vqrdmlsdhx_q_q_q +emit_vqrdmlsdhx :: emit_vqrdmlsdhx_q_q_q +inst_vldrb :: proc{ inst_vldrb_q_mem, inst_vldrb_q_mem_q } +emit_vldrb :: proc{ emit_vldrb_q_mem, emit_vldrb_q_mem_q } +inst_vldrh :: proc{ inst_vldrh_q_mem, inst_vldrh_q_mem_q } +emit_vldrh :: proc{ emit_vldrh_q_mem, emit_vldrh_q_mem_q } +inst_vldrw :: proc{ inst_vldrw_q_mem, inst_vldrw_q_mem_q } +emit_vldrw :: proc{ emit_vldrw_q_mem, emit_vldrw_q_mem_q } +inst_vldrd :: proc{ inst_vldrd_q_mem, inst_vldrd_q_mem_q } +emit_vldrd :: proc{ emit_vldrd_q_mem, emit_vldrd_q_mem_q } +inst_vstrb :: proc{ inst_vstrb_q_mem, inst_vstrb_q_mem_q } +emit_vstrb :: proc{ emit_vstrb_q_mem, emit_vstrb_q_mem_q } +inst_vstrh :: proc{ inst_vstrh_q_mem, inst_vstrh_q_mem_q } +emit_vstrh :: proc{ emit_vstrh_q_mem, emit_vstrh_q_mem_q } +inst_vstrw :: proc{ inst_vstrw_q_mem, inst_vstrw_q_mem_q } +emit_vstrw :: proc{ emit_vstrw_q_mem, emit_vstrw_q_mem_q } +inst_vstrd :: proc{ inst_vstrd_q_mem, inst_vstrd_q_mem_q } +emit_vstrd :: proc{ emit_vstrd_q_mem, emit_vstrd_q_mem_q } +inst_vld20 :: inst_vld20_qlist_mem +emit_vld20 :: emit_vld20_qlist_mem +inst_vld21 :: inst_vld21_qlist_mem +emit_vld21 :: emit_vld21_qlist_mem +inst_vld40 :: inst_vld40_qlist_mem +emit_vld40 :: emit_vld40_qlist_mem +inst_vld41 :: inst_vld41_qlist_mem +emit_vld41 :: emit_vld41_qlist_mem +inst_vld42 :: inst_vld42_qlist_mem +emit_vld42 :: emit_vld42_qlist_mem +inst_vld43 :: inst_vld43_qlist_mem +emit_vld43 :: emit_vld43_qlist_mem +inst_vst20 :: inst_vst20_qlist_mem +emit_vst20 :: emit_vst20_qlist_mem +inst_vst21 :: inst_vst21_qlist_mem +emit_vst21 :: emit_vst21_qlist_mem +inst_vst40 :: inst_vst40_qlist_mem +emit_vst40 :: emit_vst40_qlist_mem +inst_vst41 :: inst_vst41_qlist_mem +emit_vst41 :: emit_vst41_qlist_mem +inst_vst42 :: inst_vst42_qlist_mem +emit_vst42 :: emit_vst42_qlist_mem +inst_vst43 :: inst_vst43_qlist_mem +emit_vst43 :: emit_vst43_qlist_mem diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index 5331c2a5d..13342b0b8 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -311,10 +311,9 @@ Mnemonic :: enum u16 { // -- Dot Product (FEAT_DotProd) ------------------------------------------ VSDOT, VUDOT, // -- BF16 (FEAT_BF16) ---------------------------------------------------- - VCVT_BF16, // BF16<->F32 - VDOT_BF16, - VFMA_BF16, - VMMLA_BF16, + // BF16<->F32 + VDOT, + VMMLA, // -- FHM (FEAT_FHM) FP16 matrix mul/acc ---------------------------------- VFMAL, VFMSL, // F16 fused multiply-add long @@ -338,12 +337,7 @@ Mnemonic :: enum u16 { VINS, // insert F16 into high lane of S-reg // -- MVE gather/scatter (vector offset addressing) ---------------------- - VLDRB_GATHER, VLDRH_GATHER, VLDRW_GATHER, VLDRD_GATHER, - VSTRB_SCATTER, VSTRH_SCATTER, VSTRW_SCATTER, VSTRD_SCATTER, - // -- NEON compare-with-zero (distinct encodings from reg-vs-reg) -------- - VCEQ_Z, VCGE_Z, VCGT_Z, VCLE_Z, VCLT_Z, - // -- NEON replicate loads (broadcast one element to all lanes) ---------- // VLD1R already covered in VLD1; these are the 2/3/4 variants. VLD2R, VLD3R, VLD4R, @@ -353,7 +347,7 @@ Mnemonic :: enum u16 { VST1_LANE, VST2_LANE, VST3_LANE, VST4_LANE, // -- VFP fixed-point conversions (with #fbits operand) ------------------ - VCVT_FIXED, // VCVT.

Sd, Sd, #fbits family + // VCVT.
Sd, Sd, #fbits family // ------------------------------------------------------------------------- // Thumb-only mnemonics (extra ones not shared with A32) @@ -400,7 +394,7 @@ Mnemonic :: enum u16 { // use a register target Rm at hw0[3:0]; BFCSEL adds a 4-bit condition at // hw0[5:2] (its else-target is the implicit fall-through). Byte-exact vs llvm-mc. BF, // branch future - BFI_BR, // branch future indirect (bfx) + BFX, // branch future indirect (bfx) BFL, // branch future and link BFLX, // branch future link and exchange BFCSEL, // branch future conditional select @@ -483,9 +477,9 @@ Mnemonic :: enum u16 { VQRSHRUNB, VQRSHRUNT, // Move between Qd-lane and GPR (MVE-specific 4-element split forms) - VMOV_Q_R, // VMOV Qd[i], Rt -- single lane to GPR - VMOV_R_Q, // VMOV Rt, Qd[i] - VMOV_2GPR_Q, // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair + // VMOV Qd[i], Rt -- single lane to GPR + // VMOV Rt, Qd[i] + // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair // Saturating doubling MAC reductions VQDMLADH, VQDMLADHX, @@ -494,8 +488,8 @@ Mnemonic :: enum u16 { VQRDMLSDH, VQRDMLSDHX, // Misc - VHCADD_SAT, // (rarely used) - VCMLA_MVE, // (MVE form; VCMLA already exists) + // (rarely used) + // (MVE form; VCMLA already exists) // MVE load/store (mostly reuses VLDR/VSTR but distinct forms exist): VLDRB, VLDRH, VLDRW, VLDRD, // MVE contiguous load (B/H/W/D) diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 375260224..21c374197 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -394,12 +394,21 @@ wprintln :: proc( @(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, cond: u8, sets_flags: bool, uppercase: bool) { name, _ := reflect.enum_name_from_value(m) - if uppercase { - strings.write_string(sb, name) - } else { - for r in name { - if r >= 'A' && r <= 'Z' { strings.write_byte(sb, u8(r - 'A' + 'a')) } - else { strings.write_rune(sb, r) } + // PSB_CSYNC / TSB_CSYNC are the only names left holding an underscore: + // assemblers write them as a mnemonic plus an operand token, `psb csync`, + // so that underscore is a space. No other mnemonic has one. + split := -1 + if len(name) > 4 && (name[:4] == "PSB_" || name[:4] == "TSB_") { + split = 3 + } + for i in 0..= 'A' && c <= 'Z' { + strings.write_byte(sb, c - 'A' + 'a') + } else { + strings.write_byte(sb, c) } } if sets_flags { diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index f44fc2b13..105a7ba47 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1391,6 +1391,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, }, .VFMS = { {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}}, @@ -1482,6 +1483,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 32-bit lane move (.32): {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}}, {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}}, + // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] + {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + // VMOV. Rt, Qd[i] + {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move + {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, // ---- VMVN NEON modified immediate (op=1 form) ---- // bit 5 = 1 distinguishes VMVN from VMOV @@ -1552,6 +1559,27 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, // VCVT.F64.U32 Dd, Sm {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + // VCVT.BF16.F32 D, Q + // vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600 + {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}}, + // VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + // VCVT.U32.F32 Sd, Sd, #fbits + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + // VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + // VCVT.F32.U32 Sd, Sd, #fbits + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + // VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point) + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + // VCVT.F32.S16 Sd, Sd, #fbits + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + // F64 variants (sz=1): change cp to 1011 (bit 8 = 1) + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + // F16 variants (cp=1001, FEAT_FP16) + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, }, .VCVTB = { // VCVTB.F32.F16 / .F16.F32 @@ -1878,6 +1906,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON F16 {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + // Integer: 0xF3B10100 base for .I8, opc=000 + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + // Float: 0xF3B90500 base (.F32, opc=010) + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 @@ -1896,6 +1930,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 @@ -1913,6 +1951,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { @@ -2720,6 +2762,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}}, {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}}, {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, }, .VCADD = { // Mask 0xFE800F10 leaves bit 24 variable for rotation operand (90 or 270) @@ -2738,21 +2781,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // FEAT_BF16 (ARMv8.6): BFloat16 arithmetic and conversion - .VCVT_BF16 = { - // VCVT.BF16.F32 D, Q - // vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600 - {.VCVT_BF16, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}}, - }, - .VDOT_BF16 = { + .VDOT = { // VDOT.BF16 D, D, D - {.VDOT_BF16, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}}, - {.VDOT_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}}, + {.VDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, }, - .VFMA_BF16 = { - {.VFMA_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, - }, - .VMMLA_BF16 = { - {.VMMLA_BF16, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + .VMMLA = { + {.VMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, }, // ========================================================================= @@ -2837,32 +2872,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vldrh.u16 q,[r,q] = 0xFC92_2E96 -> base 0xFC900E90 // vldrw.u32 q,[r,q] = 0xFC92_2F46 -> base 0xFC900F40 // vldrd.u64 q,[r,q] = 0xFC92_2FD6 -> base 0xFC900FD0 - .VLDRB_GATHER = { - {.VLDRB_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VLDRH_GATHER = { - {.VLDRH_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VLDRW_GATHER = { - {.VLDRW_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VLDRD_GATHER = { - {.VLDRD_GATHER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, // VSTR scatter (LLVM-verified): top byte 0xEC (vs 0xFC for VLDR gather). // vstrb.8 q1,[r2,q3] = 0xEC82_2E06 -> base 0xEC600E00 - .VSTRB_SCATTER = { - {.VSTRB_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VSTRH_SCATTER = { - {.VSTRH_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VSTRW_SCATTER = { - {.VSTRW_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VSTRD_SCATTER = { - {.VSTRD_SCATTER, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, // ========================================================================= // VFP fixed-point conversions (VCVT with #fbits) -- ARMv7 VFPv3 / FP16 @@ -2874,64 +2885,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // sf = 0 (.16) / 1 (.32) // sx = same as sf (size selector for output) // sz = 0 (F32) / 1 (F64) - .VCVT_FIXED = { - // VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - // VCVT.U32.F32 Sd, Sd, #fbits - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - // VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - // VCVT.F32.U32 Sd, Sd, #fbits - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - // VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point) - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, - // VCVT.F32.S16 Sd, Sd, #fbits - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, - // F64 variants (sz=1): change cp to 1011 (bit 8 = 1) - {.VCVT_FIXED, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT_FIXED, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - // F16 variants (cp=1001, FEAT_FP16) - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT_FIXED, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - }, // ========================================================================= // NEON compare-with-zero (single-operand, distinct encoding from reg form) // ========================================================================= // 1111 0011 1011 size 01 Vd op 0 0 0 Q M 0 Vm (integer) // 1111 0011 1011 size 10 Vd op 0 0 1 Q M 0 Vm (float; op selects EQ/GE/GT/LE/LT) - .VCEQ_Z = { - // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - }, - .VCGE_Z = { - {.VCGE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - }, - .VCGT_Z = { - {.VCGT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - }, - .VCLE_Z = { - {.VCLE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - }, - .VCLT_Z = { - {.VCLT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT_Z, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT_Z, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - }, // ========================================================================= // NEON replicate loads (broadcast single element to all lanes) @@ -3093,7 +3052,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, }, - // BF / BFL / BFLX / BFI_BR (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1. + // BF / BFL / BFLX / BFX (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1. // bf-point: imm4 = (label-(PC+4))/2 at hw0[10:7]; branch target: val = // (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target // is a register Rm at hw0[3:0]. (BFCSEL has an extra else-target + condition.) @@ -3106,8 +3065,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .BFLX = { {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, }, - .BFI_BR = { - {.BFI_BR, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + .BFX = { + {.BFX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, }, // BFCSEL: bf-point + true-target (hw1, like BF) + 4-bit condition at hw0[5:2]; // hw0[1] is a static marker. The else-target is the architectural fall-through @@ -3381,6 +3340,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .VHCADD = { {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, // ---- MVE shifts (specialized) --------------------------------------------- @@ -3504,18 +3464,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // ---- MVE Q-lane GPR move --------------------------------------------------- - .VMOV_Q_R = { - // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] - {.VMOV_Q_R, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VMOV_R_Q = { - // VMOV. Rt, Qd[i] - {.VMOV_R_Q, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, - .VMOV_2GPR_Q = { - // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move - {.VMOV_2GPR_Q, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - }, // MVE saturating doubling MAC (LLVM-verified for .S8 sizes): // vqdmladh.s8 q1,q2,q3 = 0xEE04_2E06 -> base 0xEE000E00 @@ -3555,27 +3503,35 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vstrb.8 q1, [r2] = 0xED82_3E00 -> base 0xED801E00 .VLDRB = { {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VLDRH = { {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VLDRW = { {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VLDRD = { {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VSTRB = { {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VSTRH = { {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VSTRW = { {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, .VSTRD = { {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, }, // Interleaved load/store -- 2-vector .VLD20 = { @@ -3671,8 +3627,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // complex ops carry a rotation immediate (degrees). // One form per mnemonic with the element-size bits left variable in the // mask (the MVE convention); the complex ops encode the rotation immediate. - .VHCADD_SAT = { {.VHCADD_SAT, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, - .VCMLA_MVE = { {.VCMLA_MVE, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}} }, // MVE multiply-subtract reduce (Rd at 15:12, Qn at 19:17, Qm at 3:1 -- the // proper 3-bit MVE Q fields, .s16 form). VMLSVA accumulates (bit 5). .VMLSV = { {.VMLSV, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, @@ -3742,6 +3696,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, }, .VCLT = { {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, @@ -3758,6 +3716,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, }, .VACLE = { {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 3424fc6b3..c2a2a77e5 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {} }, @@ -215,8 +215,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {} }, @@ -262,8 +262,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, @@ -370,40 +370,40 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {} }, @@ -432,14 +432,14 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, @@ -454,24 +454,24 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, @@ -486,14 +486,14 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {} }, { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {} }, { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {} }, @@ -519,8 +519,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {} }, @@ -530,8 +530,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {} }, { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {} }, { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {} }, @@ -599,8 +599,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {} }, @@ -667,12 +667,12 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, @@ -685,16 +685,16 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, @@ -702,13 +702,14 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {} }, + { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, @@ -717,191 +718,190 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, - { .VCVT_BF16, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, 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{.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {} }, @@ -1031,9 +1031,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true} }, { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, - { .VDOT_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, - { .VMMLA_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, - { .VDOT_BF16, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, + { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, + { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, + { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, { .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {} }, { .STC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {} }, { .LDC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {} }, @@ -1048,29 +1048,29 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {} }, - { .VFMA_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {} }, { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {} }, { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, - { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {} }, - { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {} }, { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {} }, { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {} }, { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {} }, - { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {} }, @@ -1082,8 +1082,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {} }, { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {} }, + { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {} }, @@ -1123,8 +1123,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {} }, - { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {} }, + { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {} }, @@ -1133,60 +1133,68 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {} }, + { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {} }, { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {} }, @@ -1196,21 +1204,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {} }, @@ -1260,23 +1260,23 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, - { .VSTRH_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRW_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRD_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRB_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV_2GPR_Q, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, @@ -1297,13 +1297,15 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMAXAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, { .VMINV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, { .VMINAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, - { .VHCADD_SAT, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true} }, { .VMLSLDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, { .VMLSLDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, @@ -1315,8 +1317,6 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VRMLALDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, { .VRMLALDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, { .VSHLC, {.QPR,.GPR,.IMM5,.NONE}, {.VD_Q,.RM_T32,.A32_IMM_SHIFT,.NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV_Q_R, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV_R_Q, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, { .VADD, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, { .VSUB, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, @@ -1387,7 +1387,7 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} }, { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true} }, { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} }, - { .BFI_BR, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, @@ -1551,17 +1551,17 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VST41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, { .VST42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, { .VST43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRH_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRW_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRD_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - { .VCMLA_MVE, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, - { .VLDRB_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, + { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, @@ -1705,50 +1705,50 @@ DECODE_FORM_IDX := [1680]u16{ 0, 2, 1, 0, 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 14, 9, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 22, 25, 23, 21, 0, 0, - 0, 0, 11, 10, 14, 17, 19, 11, 16, 10, 13, 12, 18, 20, 15, 6, - 0, 0, 0, 4, 7, 2, 9, 3, 5, 6, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 23, 25, 0, 0, + 0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 18, 16, 14, 12, 10, 6, + 0, 0, 0, 7, 5, 6, 8, 9, 4, 2, 3, 0, 0, 0, 0, 0, 1, 1, 1, 1, 5, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, - 1, 1, 18, 12, 11, 1, 7, 6, 1, 6, 1, 2, 0, 2, 0, 0, - 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 19, 22, 16, - 13, 12, 15, 7, 6, 8, 2, 7, 2, 2, 7, 1, 3, 3, 1, 1, - 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, - 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, - 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, - 3, 6, 6, 8, 8, 6, 6, 0, 0, 6, 8, 6, 0, 6, 6, 4, + 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 0, 2, 0, + 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, + 16, 12, 15, 7, 6, 2, 8, 2, 7, 2, 7, 3, 1, 1, 3, 1, + 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, + 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, + 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, + 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, - 13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, + 13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1, 2, 2, 2, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, - 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, 5, - 5, 5, 5, 5, 23, 21, 15, 17, 14, 16, 8, 7, 10, 5, 5, 9, - 9, 5, 7, 7, 0, 1, 0, 2, 3, 1, 0, 3, 2, 0, 1, 0, - 1, 0, 0, 0, 0, 7, 4, 6, 5, 8, 3, 9, 2, 6, 4, 2, - 5, 3, 7, 8, 9, 1, 0, 2, 1, 0, 4, 5, 3, 1, 2, 0, - 0, 1, 2, 2, 0, 3, 1, 4, 5, 0, 3, 2, 1, 3, 4, 2, - 3, 1, 5, 0, 2, 4, 2, 5, 4, 3, 0, 1, 0, 1, 1, 0, - 2, 1, 0, 3, 0, 5, 3, 4, 1, 2, 2, 5, 3, 1, 4, 0, - 0, 1, 4, 3, 2, 4, 0, 1, 2, 3, 1, 0, 0, 0, 0, 0, - 0, 1, 3, 2, 0, 1, 2, 3, 2, 0, 1, 3, 3, 1, 2, 0, - 0, 3, 1, 2, 3, 2, 0, 1, 3, 1, 0, 2, 3, 2, 3, 0, - 3, 0, 3, 0, 2, 3, 1, 0, 2, 1, 1, 0, 0, 1, 2, 3, - 1, 0, 2, 1, 0, 1, 0, 1, 0, 6, 5, 4, 1, 2, 0, 2, - 0, 1, 0, 2, 1, 2, 1, 0, 2, 2, 0, 0, 0, 5, 4, 6, - 7, 2, 1, 0, 2, 0, 1, 0, 2, 1, 2, 1, 0, 0, 0, 2, + 14, 13, 4, 9, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, + 5, 5, 5, 5, 21, 23, 15, 17, 16, 14, 8, 7, 5, 10, 5, 9, + 9, 5, 7, 7, 0, 10, 3, 2, 1, 0, 3, 0, 1, 2, 0, 1, + 0, 1, 0, 0, 0, 9, 8, 3, 5, 4, 7, 6, 2, 8, 9, 4, + 2, 5, 6, 3, 7, 1, 0, 1, 0, 2, 3, 1, 5, 2, 0, 4, + 2, 1, 0, 13, 11, 10, 12, 13, 12, 15, 14, 15, 14, 13, 12, 15, + 17, 14, 16, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1, + 3, 2, 4, 3, 5, 1, 3, 0, 2, 4, 2, 1, 4, 5, 0, 3, + 0, 1, 1, 0, 3, 1, 2, 0, 5, 0, 3, 1, 4, 2, 5, 0, + 4, 3, 1, 2, 3, 1, 0, 2, 4, 2, 1, 3, 0, 4, 0, 1, + 0, 0, 0, 0, 3, 1, 0, 2, 3, 0, 2, 1, 2, 3, 3, 0, + 3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 0, 3, + 2, 1, 1, 0, 2, 0, 1, 1, 0, 4, 6, 5, 0, 2, 1, 2, + 1, 0, 2, 1, 0, 0, 2, 1, 2, 2, 0, 0, 0, 7, 6, 5, + 4, 2, 1, 0, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1757,24 +1757,24 @@ DECODE_FORM_IDX := [1680]u16{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 0, 0, 0, 3, 3, 0, 0, 3, 0, 3, 0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0, - 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, - 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 1, 0, 0, 1, 1, 0, - 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3, - 2, 0, 1, 27, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 5, 26, + 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9, + 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, + 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3, + 2, 1, 0, 27, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 5, 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, 2, - 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 1, 0, 2, 2, 1, 0, - 2, 2, 1, 0, 1, 0, 2, 2, 0, 1, 0, 1, 5, 3, 2, 3, - 2, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 1, - 0, 1, 0, 0, 1, 2, 0, 1, 9, 6, 5, 7, 3, 1, 0, 2, - 4, 8, 0, 1, 0, 1, 3, 0, 1, 2, 0, 1, 1, 0, 1, 0, - 0, 1, 0, 8, 9, 7, 2, 1, 3, 6, 0, 4, 0, 1, 0, 1, - 4, 5, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, + 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 0, 1, 2, 2, 1, 0, + 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 2, 3, 5, 3, + 2, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 1, + 0, 0, 1, 0, 1, 1, 2, 0, 20, 18, 19, 17, 11, 9, 8, 12, + 5, 4, 6, 2, 0, 1, 3, 7, 13, 14, 0, 1, 1, 0, 3, 2, + 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 4, 1, 0, 1, 0, + 16, 15, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 6, 7, 6, 7, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, - 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 2, - 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, + 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, 0, + 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, 29, + 28, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, @@ -1789,8 +1789,8 @@ DECODE_FORM_IDX := [1680]u16{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, - 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, + 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, 0, + 1, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, @@ -1839,35 +1839,35 @@ DECODE_BUCKET_LIST := [5553]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 365, 361, 363, 362, - 364, 366, 367, 368, 369, 370, 371, 377, 374, 378, 380, 376, 381, 379, 375, 373, - 382, 372, 384, 383, 385, 386, 391, 392, 393, 387, 394, 388, 390, 389, 395, 632, - 633, 396, 397, 398, 634, 399, 635, 400, 636, 401, 402, 637, 403, 638, 639, 404, - 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 410, 411, 412, 413, 414, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, 430, 429, 431, - 432, 433, 434, 435, 436, 632, 395, 396, 633, 397, 398, 399, 634, 635, 400, 401, - 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 642, 407, 408, 643, 644, - 409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 448, 447, 449, 450, - 451, 452, 453, 454, 455, 456, 458, 457, 459, 460, 461, 462, 464, 463, 465, 466, - 467, 468, 632, 395, 396, 633, 397, 398, 399, 634, 400, 635, 636, 401, 402, 637, - 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, 469, 395, - 632, 396, 633, 397, 398, 634, 399, 400, 635, 636, 401, 637, 402, 403, 638, 639, - 404, 405, 640, 641, 406, 642, 407, 408, 643, 644, 409, 470, 471, 472, 469, 358, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 363, 365, + 364, 366, 367, 368, 369, 370, 371, 379, 380, 373, 375, 381, 377, 378, 382, 374, + 376, 372, 384, 383, 385, 386, 391, 388, 394, 392, 389, 390, 387, 393, 395, 632, + 396, 633, 397, 398, 399, 634, 635, 400, 401, 636, 637, 402, 403, 638, 639, 404, + 405, 640, 406, 641, 642, 407, 408, 643, 644, 409, 410, 411, 412, 413, 414, 415, + 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 430, 429, 432, + 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, + 636, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, + 409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 450, 449, + 451, 452, 453, 454, 456, 455, 458, 457, 459, 460, 462, 461, 464, 463, 465, 466, + 467, 468, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 637, 402, + 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 469, 395, + 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, 402, 637, 403, 638, 639, + 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 470, 471, 472, 469, 358, 359, 360, 365, 364, 363, 362, 361, 366, 367, 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, 375, 383, 384, 385, 386, 394, 393, 392, 391, - 389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, - 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, 409, - 473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 424, 423, 426, - 425, 427, 428, 430, 429, 432, 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, - 398, 634, 399, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 641, + 389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, + 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, + 473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 422, 421, 424, 423, 426, + 425, 428, 427, 429, 430, 432, 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, + 398, 634, 399, 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 407, 642, 408, 643, 644, 409, 474, 473, 438, 439, 440, 441, 442, 443, 444, - 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 456, 455, 457, 458, 459, 460, + 445, 446, 447, 448, 449, 450, 451, 452, 454, 453, 455, 456, 458, 457, 459, 460, 462, 461, 463, 464, 465, 466, 467, 468, 395, 632, 396, 633, 397, 398, 634, 399, - 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, - 408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, - 401, 402, 637, 403, 638, 639, 404, 405, 640, 641, 406, 407, 642, 408, 643, 644, - 409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 483, 484, 485, 486, 487, - 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, + 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, + 408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 636, + 401, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, + 409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 484, 483, 485, 486, 487, + 488, 489, 490, 491, 492, 493, 494, 495, 496, 498, 497, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, @@ -1885,23 +1885,23 @@ DECODE_BUCKET_LIST := [5553]u16{ 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, 619, 620, 621, 622, 365, 364, 363, 361, 362, 623, 624, 625, 626, 370, 371, 382, 380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 627, 628, 629, 394, 393, 390, - 391, 392, 389, 388, 387, 630, 631, 632, 395, 633, 396, 397, 398, 399, 634, 400, - 635, 401, 636, 637, 402, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, + 391, 392, 389, 388, 387, 630, 631, 632, 395, 633, 396, 397, 398, 399, 634, 635, + 400, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, - 658, 659, 661, 660, 662, 663, 664, 665, 630, 631, 395, 632, 633, 396, 397, 398, - 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, - 407, 642, 408, 643, 644, 409, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, + 658, 659, 661, 660, 662, 663, 664, 665, 630, 631, 632, 395, 633, 396, 397, 398, + 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, + 642, 407, 408, 643, 644, 409, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, - 691, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 402, + 691, 630, 631, 395, 632, 633, 396, 397, 398, 634, 399, 400, 635, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 692, - 696, 694, 695, 693, 697, 700, 699, 698, 701, 702, 703, 704, 705, 706, 707, 708, - 716, 709, 714, 711, 713, 710, 712, 715, 717, 719, 722, 718, 720, 721, 724, 723, - 726, 725, 729, 727, 728, 733, 735, 730, 734, 732, 731, 738, 736, 737, 739, 744, - 741, 743, 742, 740, 748, 746, 745, 747, 749, 751, 750, 756, 755, 757, 753, 754, - 752, 759, 763, 758, 761, 760, 762, 765, 764, 766, 767, 768, 770, 769, 771, 777, - 776, 773, 774, 775, 772, 780, 778, 782, 781, 783, 779, 788, 786, 787, 785, 784, - 792, 790, 791, 793, 789, 794, 795, 796, 797, 798, 799, 800, 801, 802, 803, 807, - 804, 806, 805, 810, 811, 809, 808, 812, 815, 813, 814, 816, 819, 817, 818, 823, + 693, 696, 694, 695, 697, 698, 700, 699, 701, 702, 703, 705, 704, 706, 707, 708, + 716, 709, 711, 713, 714, 710, 712, 715, 719, 722, 723, 717, 721, 718, 724, 720, + 726, 725, 729, 727, 728, 733, 731, 735, 730, 734, 732, 738, 736, 737, 739, 741, + 742, 740, 745, 746, 743, 744, 748, 750, 749, 747, 754, 753, 752, 751, 758, 755, + 756, 757, 761, 762, 759, 763, 760, 764, 766, 768, 767, 765, 769, 771, 770, 774, + 776, 777, 775, 772, 773, 783, 779, 782, 778, 781, 780, 785, 784, 787, 786, 790, + 789, 791, 788, 796, 793, 792, 794, 795, 797, 801, 800, 799, 803, 798, 802, 807, + 804, 806, 805, 808, 810, 809, 812, 811, 813, 815, 814, 816, 817, 818, 819, 823, 821, 822, 820, 827, 825, 824, 826, 829, 828, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 830, 692, 620, 621, 622, 365, 364, 363, 361, @@ -1915,15 +1915,15 @@ DECODE_BUCKET_LIST := [5553]u16{ 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 679, 678, 680, 681, 682, 683, 685, 684, 687, 686, 688, 689, 690, 691, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, - 641, 407, 642, 408, 643, 644, 409, 833, 695, 696, 693, 694, 700, 698, 697, 699, - 701, 702, 703, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715, + 641, 407, 642, 408, 643, 644, 409, 833, 693, 695, 696, 697, 694, 701, 700, 698, + 699, 703, 702, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715, 724, 722, 721, 719, 717, 718, 720, 723, 726, 725, 729, 727, 728, 733, 734, 735, - 731, 732, 730, 737, 738, 736, 743, 742, 740, 739, 741, 744, 747, 748, 746, 745, - 751, 750, 749, 754, 755, 756, 752, 753, 757, 762, 763, 760, 761, 759, 758, 765, - 764, 766, 767, 770, 768, 769, 771, 777, 776, 774, 772, 773, 775, 781, 782, 780, - 779, 778, 783, 788, 786, 787, 785, 784, 789, 790, 791, 793, 792, 794, 795, 796, - 797, 798, 799, 800, 802, 801, 803, 806, 807, 804, 805, 808, 811, 810, 809, 814, - 813, 815, 812, 817, 816, 819, 818, 822, 821, 820, 823, 825, 824, 826, 827, 828, + 731, 732, 730, 737, 738, 736, 742, 740, 739, 741, 746, 745, 743, 744, 750, 747, + 748, 749, 754, 752, 753, 751, 758, 755, 756, 757, 762, 763, 764, 760, 761, 759, + 768, 765, 766, 767, 770, 769, 771, 777, 776, 774, 772, 773, 775, 781, 782, 780, + 779, 778, 783, 785, 784, 786, 787, 788, 789, 790, 791, 796, 797, 794, 795, 793, + 792, 799, 800, 801, 802, 803, 798, 805, 806, 804, 808, 807, 813, 811, 810, 812, + 809, 814, 815, 816, 817, 818, 819, 822, 821, 820, 823, 825, 824, 826, 827, 828, 829, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, 834, 833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 872, 873, 846, 847, @@ -1949,38 +1949,38 @@ DECODE_BUCKET_LIST := [5553]u16{ 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1019, 1021, 1022, 1023, 1024, 1037, 1038, 1025, 1026, 1037, 1038, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1025, 1026, 1039, 1037, 1038, - 1027, 1028, 1022, 1023, 1024, 1041, 1040, 1037, 1042, 1038, 1025, 1043, 1026, 1044, 1045, 1037, + 1027, 1028, 1022, 1023, 1024, 1040, 1041, 1037, 1042, 1038, 1025, 1043, 1026, 1044, 1045, 1037, 1046, 1038, 1027, 1047, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1025, 1026, 1039, 1037, 1038, 1027, 1028, 1048, 1049, 1051, 1050, 1025, 1026, 1048, 1049, 1052, 1053, - 1027, 1028, 1054, 1055, 1056, 1057, 1058, 1059, 1048, 1049, 1051, 1050, 1025, 1026, 1060, 1061, - 1048, 1049, 1052, 1053, 1027, 1028, 1048, 1049, 1051, 1050, 1025, 1026, 1048, 1049, 1053, 1052, + 1027, 1028, 1054, 1055, 1056, 1057, 1058, 1059, 1048, 1049, 1050, 1051, 1025, 1026, 1060, 1061, + 1048, 1049, 1053, 1052, 1027, 1028, 1048, 1049, 1051, 1050, 1025, 1026, 1048, 1049, 1053, 1052, 1027, 1028, 1054, 1055, 1056, 1057, 1058, 1059, 1048, 1049, 1051, 1050, 1025, 1026, 1048, 1049, - 1052, 1053, 1027, 1028, 1037, 1038, 1062, 1063, 1037, 1038, 1065, 1064, 1066, 1067, 1037, 1038, + 1053, 1052, 1027, 1028, 1037, 1038, 1062, 1063, 1037, 1038, 1065, 1064, 1066, 1067, 1037, 1038, 1037, 1038, 1037, 1038, 1063, 1062, 1037, 1038, 1065, 1064, 1037, 1038, 1037, 1038, 1048, 1049, - 1063, 1062, 1048, 1049, 1064, 1065, 1048, 1049, 1048, 1049, 1048, 1049, 1063, 1062, 1048, 1049, - 1065, 1064, 1048, 1049, 1048, 1049, 1068, 1069, 1070, 1071, 1072, 1073, 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1073, 1075, 1098, 1037, 1099, 1100, 1101, 1102, 1038, 1082, 1083, 1084, 1085, 1074, 1073, 1087, - 1103, 1104, 1037, 1106, 1105, 1107, 1108, 1038, 1092, 1083, 1093, 1085, 1110, 1111, 1112, 1113, - 1114, 1115, 1116, 1075, 1117, 1119, 1118, 1082, 1083, 1084, 1085, 1087, 1120, 1121, 1123, 1122, - 1124, 1125, 1092, 1083, 1093, 1085, 1075, 1126, 1127, 1129, 1128, 1130, 1131, 1082, 1083, 1084, - 1085, 1134, 1133, 1132, 1136, 1135, 1137, 1138, 1139, 1140, 1142, 1141, 1144, 1143, 1145, 1146, - 1147, 1148, 1149, 1150, 1152, 1151, 1154, 1153, 1156, 1155, 1157, 1159, 1158, 1163, 1162, 1167, - 1160, 1168, 1161, 1164, 1169, 1165, 1166, 1170, 1171, 1173, 1172, 1177, 1174, 1175, 1176, 1179, - 1178, 1181, 1180, 1182, 1183, 1185, 1184, 1186, 1188, 1190, 1192, 1187, 1194, 1191, 1193, 1189, + 1037, 1088, 1089, 1091, 1090, 1038, 1092, 1083, 1093, 1085, 1094, 1095, 1109, 1096, 1097, 1074, + 1073, 1075, 1098, 1037, 1100, 1099, 1101, 1102, 1038, 1082, 1083, 1084, 1085, 1074, 1073, 1087, + 1103, 1104, 1037, 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1134, 1132, 1133, 1135, 1136, 1137, 1138, 1139, 1140, 1142, 1141, 1144, 1143, 1145, 1146, 1147, 1148, 1150, 1149, 1152, 1151, 1153, 1154, 1156, 1155, - 1157, 1158, 1159, 1169, 1168, 1166, 1165, 1163, 1160, 1161, 1162, 1164, 1167, 1170, 1171, 1172, - 1173, 1177, 1175, 1176, 1174, 1178, 1179, 1180, 1181, 1182, 1183, 1185, 1184, 1186, 1194, 1190, - 1193, 1188, 1189, 1192, 1191, 1187, 1197, 1195, 1196, 1199, 1198, 1201, 1200, 1203, 1202, 1087, + 1157, 1158, 1159, 1170, 1171, 1169, 1168, 1166, 1165, 1163, 1160, 1161, 1175, 1176, 1174, 1177, + 1173, 1162, 1164, 1167, 1172, 1178, 1179, 1180, 1181, 1185, 1184, 1182, 1183, 1186, 1187, 1189, + 1188, 1190, 1191, 1193, 1192, 1194, 1197, 1195, 1196, 1199, 1198, 1201, 1200, 1203, 1202, 1087, 1092, 1083, 1093, 1085, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1037, 1038, 1208, 1208, 1208, 1208, 1208, 1208, 1208, 1208, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215, 1216, 1217, 1218, 1219, 1220, @@ -2009,7 +2009,7 @@ DECODE_BUCKET_LIST := [5553]u16{ 1532, 1533, 1534, 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1546, 1548, 1547, 1550, 1549, 1552, 1551, 1553, 1554, 1270, 1271, 1272, 1273, 1274, 1275, 1555, 1556, 1557, 1558, 1559, 1560, 1561, 1562, 1563, 1564, 1565, 1566, 1567, 1568, 1569, 1282, 1283, 1284, 1285, - 1286, 1287, 1570, 1571, 1572, 1292, 1293, 1294, 1573, 1299, 1300, 1301, 1302, 1303, 1304, 1308, + 1286, 1287, 1570, 1571, 1572, 1292, 1293, 1294, 1573, 1301, 1302, 1303, 1304, 1305, 1306, 1308, 1309, 1574, 1310, 1311, 1575, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1576, 1577, 1578, 1579, 1580, 1581, 1582, 1583, 1323, 1584, 1324, 1325, 1326, 1327, 1585, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, @@ -2026,54 +2026,54 @@ DECODE_BUCKET_LIST := [5553]u16{ 1212, 1213, 1216, 1230, 1231, 1230, 1229, 1227, 1223, 1229, 1227, 1231, 1230, 1231, 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1357, 1358, 1359, 1360, 1361, 1298, 1323, 1326, 1350, 1351, 1352, 1353, 1354, 1355, + 1356, 1357, 1358, 1359, 1360, 1361, 1299, 1324, 1327, 1350, 1351, 1352, 1353, 1354, 1355, 1356, + 1357, 1358, 1359, 1360, 1361, 1300, 1324, 1327, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, + 1358, 1359, 1360, 1361, 1297, 1323, 1326, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, + 1359, 1360, 1361, 1298, 1323, 1326, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, + 1360, 1361, 1299, 1324, 1327, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, + 1361, 1300, 1324, 1327, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1364, 1365, 1366, 1374, 1376, 1377, 1380, 1384, 1392, 1393, 1394, 1395, 1403, 1402, 1404, 1376, 1377, 1381, 1385, 1392, 1393, 1394, 1395, 1402, 1403, 1404, 1376, 1377, 1392, 1393, 1401, 1403, 1402, 1404, 1376, 1377, 1392, 1393, 1401, 1402, 1403, 1404, 1375, - 1382, 1383, 1390, 1389, 1400, 1402, 1403, 1404, 1389, 1390, 1400, 1403, 1402, 1404, 1378, 1391, - 1402, 1403, 1404, 1379, 1391, 1403, 1402, 1404, 1384, 1393, 1396, 1403, 1402, 1404, 1386, 1393, - 1396, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1383, 1402, 1403, 1404, - 1403, 1402, 1404, 1378, 1403, 1402, 1404, 1379, 1403, 1402, 1404, 1377, 1384, 1392, 1393, 1403, + 1382, 1383, 1390, 1389, 1400, 1403, 1402, 1404, 1389, 1390, 1400, 1403, 1402, 1404, 1378, 1391, + 1403, 1402, 1404, 1379, 1391, 1402, 1403, 1404, 1384, 1393, 1396, 1403, 1402, 1404, 1386, 1393, + 1396, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1383, 1402, 1403, 1404, + 1403, 1402, 1404, 1378, 1402, 1403, 1404, 1379, 1402, 1403, 1404, 1377, 1384, 1392, 1393, 1403, 1402, 1404, 1377, 1388, 1392, 1393, 1402, 1403, 1404, 1377, 1392, 1393, 1403, 1402, 1404, 1377, 1392, 1393, 1402, 1403, 1404, 1383, 1398, 1403, 1402, 1404, 1398, 1402, 1403, 1404, 1378, 1399, - 1403, 1402, 1404, 1379, 1399, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1403, 1402, - 1404, 1393, 1403, 1402, 1404, 1387, 1393, 1402, 1403, 1404, 1383, 1397, 1403, 1402, 1404, 1397, - 1402, 1403, 1404, 1378, 1402, 1403, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, - 1393, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1383, 1433, 1402, 1403, - 1404, 1402, 1403, 1404, 1378, 1403, 1402, 1404, 1379, 1403, 1402, 1404, 1384, 1393, 1402, 1403, + 1402, 1403, 1404, 1379, 1399, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1403, 1402, + 1404, 1393, 1402, 1403, 1404, 1387, 1393, 1402, 1403, 1404, 1383, 1397, 1403, 1402, 1404, 1397, + 1403, 1402, 1404, 1378, 1403, 1402, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, + 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1383, 1433, 1402, 1403, + 1404, 1402, 1403, 1404, 1378, 1403, 1402, 1404, 1379, 1403, 1402, 1404, 1384, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1383, 1434, 1402, 1403, 1404, 1402, 1403, 1404, 1378, 1402, 1403, 1404, 1379, 1402, 1403, 1404, 1384, 1431, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1425, 1431, 1393, 1402, 1403, 1404, 1393, 1402, 1403, @@ -2081,8 +2081,8 @@ DECODE_BUCKET_LIST := [5553]u16{ 1402, 1403, 1404, 1424, 1384, 1432, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1411, 1412, 1413, 1414, 1416, 1417, 1418, 1419, 1426, 1432, 1393, 1403, 1402, 1404, 1410, 1415, 1421, 1422, 1423, 1393, 1403, 1402, 1404, 1383, 1430, 1402, 1403, 1404, 1403, - 1402, 1404, 1420, 1378, 1403, 1402, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1394, 1395, 1403, - 1402, 1404, 1385, 1393, 1394, 1395, 1402, 1403, 1404, 1393, 1401, 1402, 1403, 1404, 1393, 1401, + 1402, 1404, 1420, 1378, 1403, 1402, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1395, 1394, 1403, + 1402, 1404, 1385, 1393, 1395, 1394, 1402, 1403, 1404, 1393, 1401, 1402, 1403, 1404, 1393, 1401, 1403, 1402, 1404, 1383, 1390, 1389, 1400, 1403, 1402, 1404, 1389, 1390, 1400, 1403, 1402, 1404, 1378, 1391, 1402, 1403, 1404, 1379, 1391, 1402, 1403, 1404, 1384, 1393, 1396, 1403, 1402, 1404, 1386, 1393, 1396, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1383, 1402, @@ -2091,12 +2091,12 @@ DECODE_BUCKET_LIST := [5553]u16{ 1398, 1402, 1403, 1404, 1398, 1403, 1402, 1404, 1378, 1399, 1403, 1402, 1404, 1379, 1399, 1403, 1402, 1404, 1384, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1387, 1393, 1402, 1403, 1404, 1383, 1397, 1403, 1402, 1404, 1397, 1403, 1402, 1404, 1378, 1403, 1402, - 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1393, 1403, - 1402, 1404, 1393, 1402, 1403, 1404, 1383, 1433, 1403, 1402, 1404, 1402, 1403, 1404, 1378, 1403, - 1402, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1393, - 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1383, 1434, 1403, 1402, 1404, 1402, 1403, 1404, 1378, - 1402, 1403, 1404, 1379, 1403, 1402, 1404, 1384, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, - 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1383, 1403, 1402, 1404, 1403, 1402, 1404, 1378, + 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1403, 1402, 1404, 1393, 1402, + 1403, 1404, 1393, 1402, 1403, 1404, 1383, 1433, 1403, 1402, 1404, 1402, 1403, 1404, 1378, 1403, + 1402, 1404, 1379, 1402, 1403, 1404, 1384, 1393, 1402, 1403, 1404, 1393, 1402, 1403, 1404, 1393, + 1403, 1402, 1404, 1393, 1402, 1403, 1404, 1383, 1434, 1403, 1402, 1404, 1403, 1402, 1404, 1378, + 1403, 1402, 1404, 1379, 1403, 1402, 1404, 1384, 1393, 1403, 1402, 1404, 1393, 1402, 1403, 1404, + 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1383, 1403, 1402, 1404, 1403, 1402, 1404, 1378, 1402, 1403, 1404, 1379, 1402, 1403, 1404, 1435, 1436, 1437, 1384, 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1393, 1403, 1402, 1404, 1383, 1402, 1403, 1404, 1403, 1402, 1404, 1378, 1402, 1403, 1404, 1379, 1438, 1403, 1402, 1404, 1442, 1441, 1444, 1443, 1448, @@ -2105,11 +2105,11 @@ DECODE_BUCKET_LIST := [5553]u16{ 1516, 1521, 1517, 1517, 1470, 1471, 1472, 1473, 1474, 1480, 1486, 1492, 1498, 1504, 1466, 1467, 1468, 1469, 1475, 1481, 1487, 1493, 1499, 1505, 1476, 1482, 1488, 1494, 1500, 1506, 1465, 1478, 1484, 1490, 1496, 1502, 1508, 1479, 1485, 1491, 1497, 1503, 1509, 1477, 1483, 1489, 1495, 1501, - 1507, 1510, 1524, 1525, 1513, 1528, 1511, 1526, 1512, 1529, 1527, 1552, 1551, 1545, 1548, 1549, - 1545, 1547, 1550, 1552, 1551, 1548, 1549, 1547, 1550, 1536, 1537, 1538, 1539, 1540, 1541, 1552, - 1530, 1531, 1532, 1533, 1534, 1535, 1542, 1543, 1544, 1546, 1551, 1545, 1548, 1549, 1545, 1547, - 1550, 1536, 1537, 1538, 1539, 1540, 1541, 1552, 1530, 1531, 1532, 1533, 1534, 1535, 1551, 1548, - 1549, 1547, 1550, 1545, 1545, 1542, 1543, 1544, 1546, 1545, 1545, 1569, 1292, 1293, 1308, 1309, + 1507, 1510, 1524, 1525, 1513, 1528, 1511, 1526, 1512, 1529, 1527, 1551, 1552, 1542, 1548, 1550, + 1542, 1547, 1549, 1551, 1552, 1548, 1550, 1547, 1549, 1536, 1537, 1538, 1539, 1540, 1541, 1551, + 1530, 1531, 1532, 1533, 1534, 1535, 1543, 1544, 1545, 1546, 1552, 1542, 1548, 1550, 1542, 1547, + 1549, 1536, 1537, 1538, 1539, 1540, 1541, 1551, 1530, 1531, 1532, 1533, 1534, 1535, 1552, 1548, + 1550, 1547, 1549, 1542, 1542, 1543, 1544, 1545, 1546, 1542, 1542, 1569, 1292, 1293, 1308, 1309, 1310, 1575, 1321, 1322, 1580, 1581, 1582, 1583, 1325, 1585, 1328, 1329, 1332, 1333, 1334, 1335, 1336, 1337, 1346, 1347, 1348, 1349, 1598, 1292, 1293, 1308, 1309, 1310, 1575, 1322, 1580, 1581, 1582, 1583, 1325, 1585, 1328, 1329, 1332, 1333, 1334, 1335, 1336, 1337, 1346, 1347, 1348, 1349, @@ -2124,17 +2124,17 @@ DECODE_BUCKET_LIST := [5553]u16{ 1328, 1329, 1332, 1333, 1334, 1335, 1336, 1337, 1346, 1347, 1348, 1349, 1594, 1598, 1553, 1563, 1564, 1292, 1293, 1294, 1308, 1309, 1310, 1311, 1575, 1320, 1322, 1580, 1581, 1582, 1583, 1325, 1585, 1328, 1329, 1332, 1333, 1334, 1335, 1336, 1337, 1346, 1347, 1348, 1349, 1594, 1598, 1270, - 1271, 1301, 1302, 1303, 1304, 1314, 1315, 1316, 1317, 1576, 1577, 1578, 1579, 1585, 1330, 1331, + 1271, 1303, 1304, 1305, 1306, 1314, 1315, 1316, 1317, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1590, 1591, 1592, 1593, 1367, 1596, 1599, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1596, 1599, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1596, - 1599, 1561, 1562, 1299, 1300, 1312, 1313, 1318, 1319, 1576, 1577, 1578, 1579, 1585, 1330, 1331, - 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1586, 1587, 1588, 1589, 1596, 1599, 1301, 1302, - 1303, 1304, 1314, 1315, 1316, 1317, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, + 1599, 1561, 1562, 1301, 1302, 1312, 1313, 1318, 1319, 1576, 1577, 1578, 1579, 1585, 1330, 1331, + 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1586, 1587, 1588, 1589, 1596, 1599, 1303, 1304, + 1305, 1306, 1314, 1315, 1316, 1317, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1590, 1591, 1592, 1593, 1367, 1595, 1597, 1599, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1595, 1597, 1599, 1272, 1273, 1274, 1275, 1284, 1285, 1286, 1287, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, - 1340, 1341, 1342, 1343, 1344, 1345, 1595, 1597, 1599, 1561, 1562, 1282, 1283, 1299, 1300, 1312, + 1340, 1341, 1342, 1343, 1344, 1345, 1595, 1597, 1599, 1561, 1562, 1282, 1283, 1301, 1302, 1312, 1313, 1318, 1319, 1576, 1577, 1578, 1579, 1585, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1586, 1587, 1588, 1589, 1595, 1597, 1599, 1573, 1574, 1575, 1323, 1584, 1326, 1585, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1574, 1575, 1323, 1584, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 71b9197e5..f41e57c92 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -995,6 +995,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, // .VFMS { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, @@ -1067,6 +1068,17 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, // .VCVTB { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, @@ -1119,6 +1131,9 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, // .VMRS { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {} }, // .VMSR @@ -1455,6 +1470,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, // .VCGE { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {} }, @@ -1468,6 +1487,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, // .VCGT { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {} }, @@ -1481,6 +1504,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, // .VCLE { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {} }, @@ -1496,6 +1523,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, // .VCLT { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {} }, @@ -1511,6 +1542,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, // .VACGE { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {} }, @@ -1847,15 +1882,11 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {} }, { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, - // .VCVT_BF16 - { .VCVT_BF16, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, - // .VDOT_BF16 - { .VDOT_BF16, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, - { .VDOT_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, - // .VFMA_BF16 - { .VFMA_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, - // .VMMLA_BF16 - { .VMMLA_BF16, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, + // .VDOT + { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, + { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, + // .VMMLA + { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, // .VFMAL { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {} }, { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {} }, @@ -1867,6 +1898,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, // .VCADD { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, @@ -1892,47 +1924,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, // .VINS { .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, - // .VLDRB_GATHER - { .VLDRB_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, - // .VLDRH_GATHER - { .VLDRH_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VLDRW_GATHER - { .VLDRW_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VLDRD_GATHER - { .VLDRD_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VSTRB_SCATTER - { .VSTRB_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, - // .VSTRH_SCATTER - { .VSTRH_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VSTRW_SCATTER - { .VSTRW_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VSTRD_SCATTER - { .VSTRD_SCATTER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VCEQ_Z - { .VCEQ_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, - // .VCGE_Z - { .VCGE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, - // .VCGT_Z - { .VCGT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, - // .VCLE_Z - { .VCLE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, - // .VCLT_Z - { .VCLT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, // .VLD2R { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {} }, // .VLD3R @@ -1971,17 +1962,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {} }, - // .VCVT_FIXED - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, // .IT { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {} }, // .TT @@ -2024,8 +2004,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, // .BF { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, - // .BFI_BR - { .BFI_BR, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + // .BFX + { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, // .BFL { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, // .BFLX @@ -2170,6 +2150,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VCMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, // .VHCADD { .VHCADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, // .VBRSR { .VBRSR, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true} }, // .VSHLC @@ -2234,12 +2215,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQRSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, // .VQRSHRUNT { .VQRSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, - // .VMOV_Q_R - { .VMOV_Q_R, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - // .VMOV_R_Q - { .VMOV_R_Q, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - // .VMOV_2GPR_Q - { .VMOV_2GPR_Q, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, // .VQDMLADH { .VQDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, // .VQDMLADHX @@ -2256,26 +2231,30 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQRDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, // .VQRDMLSDHX { .VQRDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, - // .VHCADD_SAT - { .VHCADD_SAT, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, - // .VCMLA_MVE - { .VCMLA_MVE, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, // .VLDRB { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, // .VLDRH { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VLDRW { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VLDRD { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VSTRB { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, // .VSTRH { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VSTRW { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VSTRD { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, // .VLD20 { .VLD20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, // .VLD21 @@ -2303,617 +2282,596 @@ ENCODE_FORMS := [1680]lib.Encoding{ } ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ - .INVALID = { 0, 0}, - .AND = { 0, 11}, - .EOR = { 11, 9}, - .SUB = { 20, 10}, - .RSB = { 30, 8}, - .ADD = { 38, 12}, - .ADC = { 50, 9}, - .SBC = { 59, 9}, - .RSC = { 68, 6}, - .TST = { 74, 6}, - .TEQ = { 80, 5}, - .CMP = { 85, 8}, - .CMN = { 93, 6}, - .ORR = { 99, 9}, - .MOV = { 108, 12}, - .BIC = { 120, 9}, - .MVN = { 129, 9}, - .LSL = { 138, 6}, - .LSR = { 144, 6}, - .ASR = { 150, 6}, - .ROR = { 156, 5}, - .RRX = { 161, 1}, - .ADR = { 162, 1}, - .NEG = { 163, 1}, - .MOVW = { 164, 2}, - .MOVT = { 166, 2}, - .BFC = { 168, 2}, - .BFI = { 170, 2}, - .SBFX = { 172, 2}, - .UBFX = { 174, 2}, - .SXTB = { 176, 3}, - .SXTB16 = { 179, 2}, - .SXTH = { 181, 3}, - .UXTB = { 184, 3}, - .UXTB16 = { 187, 2}, - .UXTH = { 189, 3}, - .SXTAB = { 192, 2}, - .SXTAB16 = { 194, 2}, - .SXTAH = { 196, 2}, - .UXTAB = { 198, 2}, - .UXTAB16 = { 200, 2}, - .UXTAH = { 202, 2}, - .CLZ = { 204, 2}, - .RBIT = { 206, 2}, - .REV = { 208, 3}, - .REV16 = { 211, 3}, - .REVSH = { 214, 3}, - .SEL = { 217, 1}, - .PKHBT = { 218, 1}, - .PKHTB = { 219, 1}, - .USAD8 = { 220, 1}, - .USADA8 = { 221, 1}, - .SSAT = { 222, 2}, - .USAT = { 224, 2}, - .SSAT16 = { 226, 2}, - .USAT16 = { 228, 2}, - .QADD = { 230, 2}, - .QSUB = { 232, 2}, - .QDADD = { 234, 2}, - .QDSUB = { 236, 2}, - .SADD8 = { 238, 2}, - .SADD16 = { 240, 2}, - .SASX = { 242, 2}, - .SSAX = { 244, 2}, - .SSUB8 = { 246, 2}, - .SSUB16 = { 248, 2}, - .UADD8 = { 250, 2}, - .UADD16 = { 252, 2}, - .UASX = { 254, 2}, - .USAX = { 256, 2}, - .USUB8 = { 258, 2}, - .USUB16 = { 260, 2}, - .QADD8 = { 262, 2}, - .QADD16 = { 264, 2}, - .QASX = { 266, 2}, - .QSAX = { 268, 2}, - .QSUB8 = { 270, 2}, - .QSUB16 = { 272, 2}, - .UQADD8 = { 274, 2}, - .UQADD16 = { 276, 2}, - .UQASX = { 278, 2}, - .UQSAX = { 280, 2}, - .UQSUB8 = { 282, 2}, - .UQSUB16 = { 284, 2}, - .SHADD8 = { 286, 2}, - .SHADD16 = { 288, 2}, - .SHASX = { 290, 2}, - .SHSAX = { 292, 2}, - .SHSUB8 = { 294, 2}, - .SHSUB16 = { 296, 2}, - .UHADD8 = { 298, 2}, - .UHADD16 = { 300, 2}, - .UHASX = { 302, 2}, - .UHSAX = { 304, 2}, - .UHSUB8 = { 306, 2}, - .UHSUB16 = { 308, 2}, - .SMUAD = { 310, 1}, - .SMUADX = { 311, 1}, - .SMUSD = { 312, 1}, - .SMUSDX = { 313, 1}, - .SMLAD = { 314, 1}, - .SMLADX = { 315, 1}, - .SMLSD = { 316, 1}, - .SMLSDX = { 317, 1}, - .SMLALD = { 318, 1}, - .SMLALDX = { 319, 1}, - .SMLSLD = { 320, 1}, - .SMLSLDX = { 321, 1}, - .SMMUL = { 322, 1}, - .SMMULR = { 323, 1}, - .SMMLA = { 324, 1}, - .SMMLAR = { 325, 1}, - .SMMLS = { 326, 1}, - .SMMLSR = { 327, 1}, - .MUL = { 328, 4}, - .MLA = { 332, 3}, - .MLS = { 335, 2}, - .UMULL = { 337, 3}, - .UMLAL = { 340, 3}, - .SMULL = { 343, 3}, - .SMLAL = { 346, 3}, - .UMAAL = { 349, 1}, - .SMLABB = { 350, 1}, - .SMLABT = { 351, 1}, - .SMLATB = { 352, 1}, - .SMLATT = { 353, 1}, - .SMLAWB = { 354, 1}, - .SMLAWT = { 355, 1}, - .SMULBB = { 356, 1}, - .SMULBT = { 357, 1}, - .SMULTB = { 358, 1}, - .SMULTT = { 359, 1}, - .SMULWB = { 360, 1}, - .SMULWT = { 361, 1}, - .SMLALBB = { 362, 1}, - .SMLALBT = { 363, 1}, - .SMLALTB = { 364, 1}, - .SMLALTT = { 365, 1}, - .SDIV = { 366, 2}, - .UDIV = { 368, 2}, - .B = { 370, 5}, - .BL = { 375, 2}, - .BX = { 377, 2}, - .BLX = { 379, 3}, - .BXJ = { 382, 1}, - .CBZ = { 383, 1}, - .CBNZ = { 384, 1}, - .TBB = { 385, 1}, - .TBH = { 386, 1}, - .MSR = { 387, 3}, - .MRS = { 390, 2}, - .CPS = { 392, 1}, - .SETEND = { 393, 1}, - .NOP = { 394, 3}, - .YIELD = { 397, 3}, - .WFE = { 400, 3}, - .WFI = { 403, 3}, - .SEV = { 406, 3}, - .SEVL = { 409, 1}, - .DBG = { 410, 1}, - .HINT = { 411, 1}, - .DMB = { 412, 2}, - .DSB = { 414, 2}, - .ISB = { 416, 2}, - .CLREX = { 418, 2}, - .PLD = { 420, 2}, - .PLDW = { 422, 2}, - .PLI = { 424, 2}, - .HLT = { 426, 1}, - .DCPS1 = { 427, 1}, - .DCPS2 = { 428, 1}, - .DCPS3 = { 429, 1}, - .ERET = { 430, 1}, - .ESB = { 431, 2}, - .PSB_CSYNC = { 433, 2}, - .TSB_CSYNC = { 435, 2}, - .CSDB = { 437, 2}, - .SB = { 439, 2}, - .SETPAN = { 441, 2}, - .SVC = { 443, 2}, - .BKPT = { 445, 2}, - .HVC = { 447, 1}, - .SMC = { 448, 1}, - .UDF = { 449, 3}, - .LDR = { 452, 11}, - .STR = { 463, 9}, - .LDRB = { 472, 8}, - .STRB = { 480, 8}, - .LDRH = { 488, 8}, - .STRH = { 496, 8}, - .LDRSB = { 504, 7}, - .LDRSH = { 511, 7}, - .LDRD = { 518, 5}, - .STRD = { 523, 5}, - .LDRT = { 528, 1}, - .STRT = { 529, 1}, - .LDRBT = { 530, 1}, - .STRBT = { 531, 1}, - .LDRHT = { 532, 1}, - .STRHT = { 533, 1}, - .LDRSBT = { 534, 1}, - .LDRSHT = { 535, 1}, - .LDA = { 536, 1}, - .STL = { 537, 1}, - .LDAB = { 538, 1}, - .STLB = { 539, 1}, - .LDAH = { 540, 1}, - .STLH = { 541, 1}, - .LDREX = { 542, 2}, - .STREX = { 544, 2}, - .LDREXB = { 546, 2}, - .STREXB = { 548, 2}, - .LDREXH = { 550, 2}, - .STREXH = { 552, 2}, - .LDREXD = { 554, 2}, - .STREXD = { 556, 2}, - .LDAEX = { 558, 1}, - .STLEX = { 559, 1}, - .LDAEXB = { 560, 1}, - .STLEXB = { 561, 1}, - .LDAEXH = { 562, 1}, - .STLEXH = { 563, 1}, - .LDAEXD = { 564, 1}, - .STLEXD = { 565, 1}, - .LDM = { 566, 8}, - .STM = { 574, 8}, - .PUSH = { 582, 3}, - .POP = { 585, 3}, - .SWP = { 588, 1}, - .SWPB = { 589, 1}, - .RFE = { 590, 1}, - .SRS = { 591, 1}, - .CDP = { 592, 1}, - .CDP2 = { 593, 1}, - .MCR = { 594, 1}, - .MCR2 = { 595, 1}, - .MRC = { 596, 1}, - .MRC2 = { 597, 1}, - .MCRR = { 598, 1}, - .MCRR2 = { 599, 1}, - .MRRC = { 600, 1}, - .MRRC2 = { 601, 1}, - .LDC = { 602, 1}, - .LDC2 = { 603, 1}, - .STC = { 604, 1}, - .STC2 = { 605, 1}, - .CRC32B = { 606, 1}, - .CRC32H = { 607, 1}, - .CRC32W = { 608, 1}, - .CRC32CB = { 609, 1}, - .CRC32CH = { 610, 1}, - .CRC32CW = { 611, 1}, - .VADD = { 612, 18}, - .VSUB = { 630, 18}, - .VMUL = { 648, 24}, - .VDIV = { 672, 3}, - .VMLA = { 675, 18}, - .VMLS = { 693, 17}, - .VNMUL = { 710, 2}, - .VNMLA = { 712, 2}, - .VNMLS = { 714, 2}, - .VFMA = { 716, 9}, - .VFMS = { 725, 8}, - .VFNMA = { 733, 3}, - .VFNMS = { 736, 3}, - .VABS = { 739, 12}, - .VNEG = { 751, 12}, - .VSQRT = { 763, 3}, - .VCMP = { 766, 8}, - .VCMPE = { 774, 4}, - .VCVT = { 778, 10}, - .VCVTB = { 788, 2}, - .VCVTT = { 790, 2}, - .VCVTA = { 792, 2}, - .VCVTN = { 794, 2}, - .VCVTP = { 796, 2}, - .VCVTM = { 798, 2}, - .VCVTR = { 800, 4}, - .VMOV = { 804, 28}, - .VMRS = { 832, 1}, - .VMSR = { 833, 1}, - .VLDR = { 834, 2}, - .VSTR = { 836, 2}, - .VLDM = { 838, 2}, - .VSTM = { 840, 2}, - .VPUSH = { 842, 2}, - .VPOP = { 844, 2}, - .VSEL = { 846, 2}, - .VMAXNM = { 848, 2}, - .VMINNM = { 850, 2}, - .VRINTA = { 852, 3}, - .VRINTN = { 855, 3}, - .VRINTP = { 858, 3}, - .VRINTM = { 861, 3}, - .VRINTR = { 864, 2}, - .VRINTZ = { 866, 3}, - .VRINTX = { 869, 3}, - .VADDL = { 872, 6}, - .VADDW = { 878, 6}, - .VSUBL = { 884, 6}, - .VSUBW = { 890, 6}, - .VHADD = { 896, 9}, - .VHSUB = { 905, 9}, - .VRHADD = { 914, 3}, - .VQADD = { 917, 11}, - .VQSUB = { 928, 11}, - .VMULL = { 939, 11}, - .VMLAL = { 950, 10}, - .VMLSL = { 960, 10}, - .VQDMULL = { 970, 4}, - .VQDMLAL = { 974, 4}, - .VQDMLSL = { 978, 4}, - .VQDMULH = { 982, 8}, - .VQRDMULH = { 990, 8}, - .VQRDMLAH = { 998, 8}, - .VQRDMLSH = { 1006, 8}, - .VABA = { 1014, 8}, - .VABAL = { 1022, 6}, - .VABD = { 1028, 10}, - .VABDL = { 1038, 6}, - .VAND = { 1044, 3}, - .VBIC = { 1047, 3}, - .VORR = { 1050, 3}, - .VORN = { 1053, 3}, - .VEOR = { 1056, 3}, - .VBSL = { 1059, 2}, - .VBIT = { 1061, 2}, - .VBIF = { 1063, 2}, - .VMVN = { 1065, 13}, - .VMOVN = { 1078, 3}, - .VQMOVN = { 1081, 6}, - .VQMOVUN = { 1087, 3}, - .VMOVL = { 1090, 6}, - .VTST = { 1096, 6}, - .VCEQ = { 1102, 10}, - .VCGE = { 1112, 12}, - .VCGT = { 1124, 12}, - .VCLE = { 1136, 14}, - .VCLT = { 1150, 14}, - .VACGE = { 1164, 2}, - .VACGT = { 1166, 2}, - .VACLE = { 1168, 2}, - .VACLT = { 1170, 2}, - .VMAX = { 1172, 13}, - .VMIN = { 1185, 13}, - .VPMAX = { 1198, 5}, - .VPMIN = { 1203, 5}, - .VPADD = { 1208, 4}, - .VPADDL = { 1212, 6}, - .VPADAL = { 1218, 4}, - .VRECPE = { 1222, 4}, - .VRECPS = { 1226, 2}, - .VRSQRTE = { 1228, 4}, - .VRSQRTS = { 1232, 2}, - .VSHL = { 1234, 9}, - .VSHR = { 1243, 5}, - .VSRA = { 1248, 5}, - .VRSHL = { 1253, 5}, - .VRSHR = { 1258, 5}, - .VRSRA = { 1263, 2}, - .VSLI = { 1265, 2}, - .VSRI = { 1267, 2}, - .VQSHL = { 1269, 7}, - .VQSHRN = { 1276, 2}, - .VQSHRUN = { 1278, 1}, - .VQRSHL = { 1279, 16}, - .VQRSHRN = { 1295, 2}, - .VQRSHRUN = { 1297, 1}, - .VSHRN = { 1298, 1}, - .VRSHRN = { 1299, 1}, - .VSHLL = { 1300, 5}, - .VCLS = { 1305, 6}, - .VCLZ = { 1311, 6}, - .VCNT = { 1317, 2}, - .VPADD_F = { 1319, 2}, - .VRECPE_F = { 1321, 2}, - .VRSQRTE_F = { 1323, 2}, - .VREV16 = { 1325, 2}, - .VREV32 = { 1327, 4}, - .VREV64 = { 1331, 6}, - .VEXT = { 1337, 2}, - .VTBL = { 1339, 4}, - .VTBX = { 1343, 4}, - .VTRN = { 1347, 6}, - .VUZP = { 1353, 5}, - .VZIP = { 1358, 5}, - .VDUP = { 1363, 5}, - .VSWP = { 1368, 2}, - .VMOV_LANE = { 1370, 3}, - .VLD1 = { 1373, 8}, - .VLD2 = { 1381, 3}, - .VLD3 = { 1384, 2}, - .VLD4 = { 1386, 2}, - .VST1 = { 1388, 7}, - .VST2 = { 1395, 3}, - .VST3 = { 1398, 2}, - .VST4 = { 1400, 2}, - .AESE = { 1402, 1}, - .AESD = { 1403, 1}, - .AESMC = { 1404, 1}, - .AESIMC = { 1405, 1}, - .SHA1H = { 1406, 1}, - .SHA1SU0 = { 1407, 1}, - .SHA1SU1 = { 1408, 1}, - .SHA1C = { 1409, 1}, - .SHA1M = { 1410, 1}, - .SHA1P = { 1411, 1}, - .SHA256H = { 1412, 1}, - .SHA256H2 = { 1413, 1}, - .SHA256SU0 = { 1414, 1}, - .SHA256SU1 = { 1415, 1}, - .VJCVT = { 1416, 1}, - .VSDOT = { 1417, 4}, - .VUDOT = { 1421, 4}, - .VCVT_BF16 = { 1425, 1}, - .VDOT_BF16 = { 1426, 2}, - .VFMA_BF16 = { 1428, 1}, - .VMMLA_BF16 = { 1429, 1}, - .VFMAL = { 1430, 2}, - .VFMSL = { 1432, 2}, - .VCMLA = { 1434, 4}, - .VCADD = { 1438, 2}, - .VSMMLA = { 1440, 1}, - .VUMMLA = { 1441, 1}, - .VUSMMLA = { 1442, 1}, - .VSUDOT = { 1443, 2}, - .VUSDOT = { 1445, 4}, - .VQABS = { 1449, 1}, - .VQNEG = { 1450, 1}, - .VMOVX = { 1451, 1}, - .VINS = { 1452, 1}, - .VLDRB_GATHER = { 1453, 1}, - .VLDRH_GATHER = { 1454, 1}, - .VLDRW_GATHER = { 1455, 1}, - .VLDRD_GATHER = { 1456, 1}, - .VSTRB_SCATTER = { 1457, 1}, - .VSTRH_SCATTER = { 1458, 1}, - .VSTRW_SCATTER = { 1459, 1}, - .VSTRD_SCATTER = { 1460, 1}, - .VCEQ_Z = { 1461, 4}, - .VCGE_Z = { 1465, 4}, - .VCGT_Z = { 1469, 4}, - .VCLE_Z = { 1473, 4}, - .VCLT_Z = { 1477, 4}, - .VLD2R = { 1481, 1}, - .VLD3R = { 1482, 1}, - .VLD4R = { 1483, 1}, - .VLD1_LANE = { 1484, 3}, - .VLD2_LANE = { 1487, 3}, - .VLD3_LANE = { 1490, 3}, - .VLD4_LANE = { 1493, 3}, - .VST1_LANE = { 1496, 3}, - .VST2_LANE = { 1499, 3}, - .VST3_LANE = { 1502, 3}, - .VST4_LANE = { 1505, 3}, - .VCVT_FIXED = { 1508, 10}, - .IT = { 1518, 1}, - .TT = { 1519, 1}, - .TTT = { 1520, 1}, - .TTA = { 1521, 1}, - .TTAT = { 1522, 1}, - .SG = { 1523, 1}, - .BXNS = { 1524, 1}, - .BLXNS = { 1525, 1}, - .PAC = { 1526, 1}, - .PACBTI = { 1527, 1}, - .AUT = { 1528, 1}, - .AUTG = { 1529, 1}, - .BTI = { 1530, 1}, - .WLS = { 1531, 1}, - .WLSTP = { 1532, 1}, - .DLS = { 1533, 1}, - .DLSTP = { 1534, 1}, - .LE = { 1535, 1}, - .LETP = { 1536, 1}, - .LCTP = { 1537, 1}, - .BF = { 1538, 1}, - .BFI_BR = { 1539, 1}, - .BFL = { 1540, 1}, - .BFLX = { 1541, 1}, - .BFCSEL = { 1542, 1}, - .CX1 = { 1543, 1}, - .CX1A = { 1544, 1}, - .CX1D = { 1545, 1}, - .CX1DA = { 1546, 1}, - .CX2 = { 1547, 1}, - .CX2A = { 1548, 1}, - .CX2D = { 1549, 1}, - .CX2DA = { 1550, 1}, - .CX3 = { 1551, 1}, - .CX3A = { 1552, 1}, - .CX3D = { 1553, 1}, - .CX3DA = { 1554, 1}, - .VCX1 = { 1555, 2}, - .VCX1A = { 1557, 2}, - .VCX2 = { 1559, 2}, - .VCX2A = { 1561, 2}, - .VCX3 = { 1563, 2}, - .VCX3A = { 1565, 2}, - .VPT = { 1567, 1}, - .VPST = { 1568, 1}, - .VPSEL = { 1569, 1}, - .VPNOT = { 1570, 1}, - .VCTP = { 1571, 1}, - .VADDV = { 1572, 1}, - .VADDVA = { 1573, 1}, - .VADDLV = { 1574, 1}, - .VADDLVA = { 1575, 1}, - .VMAXV = { 1576, 1}, - .VMAXAV = { 1577, 1}, - .VMINV = { 1578, 1}, - .VMINAV = { 1579, 1}, - .VMAXNMV = { 1580, 1}, - .VMAXNMAV = { 1581, 1}, - .VMINNMV = { 1582, 1}, - .VMINNMAV = { 1583, 1}, - .VABAV = { 1584, 1}, - .VMLADAV = { 1585, 1}, - .VMLADAVA = { 1586, 1}, - .VMLADAVX = { 1587, 1}, - .VMLADAVAX = { 1588, 1}, - .VMLALDAV = { 1589, 1}, - .VMLALDAVA = { 1590, 1}, - .VMLALDAVX = { 1591, 1}, - .VMLALDAVAX = { 1592, 1}, - .VMLSDAV = { 1593, 1}, - .VMLSDAVA = { 1594, 1}, - .VMLSDAVX = { 1595, 1}, - .VMLSDAVAX = { 1596, 1}, - .VMLSLDAV = { 1597, 1}, - .VMLSLDAVA = { 1598, 1}, - .VMLSLDAVX = { 1599, 1}, - .VMLSLDAVAX = { 1600, 1}, - .VRMLALDAVH = { 1601, 1}, - .VRMLALDAVHA = { 1602, 1}, - .VRMLALDAVHX = { 1603, 1}, - .VRMLALDAVHAX = { 1604, 1}, - .VRMLSLDAVH = { 1605, 1}, - .VRMLSLDAVHA = { 1606, 1}, - .VRMLSLDAVHX = { 1607, 1}, - .VRMLSLDAVHAX = { 1608, 1}, - .VMLAV = { 1609, 1}, - .VMLAVA = { 1610, 1}, - .VMLSV = { 1611, 1}, - .VMLSVA = { 1612, 1}, - .VCMUL = { 1613, 1}, - .VHCADD = { 1614, 1}, - .VBRSR = { 1615, 1}, - .VSHLC = { 1616, 1}, - .VDDUP = { 1617, 1}, - .VIDUP = { 1618, 1}, - .VDWDUP = { 1619, 1}, - .VIWDUP = { 1620, 1}, - .VMOVNB = { 1621, 1}, - .VMOVNT = { 1622, 1}, - .VQMOVNB = { 1623, 1}, - .VQMOVNT = { 1624, 1}, - .VQMOVUNB = { 1625, 1}, - .VQMOVUNT = { 1626, 1}, - .VSHLLB = { 1627, 1}, - .VSHLLT = { 1628, 1}, - .VMULLB = { 1629, 1}, - .VMULLT = { 1630, 1}, - .VMLALB = { 1631, 1}, - .VMLALT = { 1632, 1}, - .VMLSLB = { 1633, 1}, - .VMLSLT = { 1634, 1}, - .VSHRNB = { 1635, 1}, - .VSHRNT = { 1636, 1}, - .VRSHRNB = { 1637, 1}, - .VRSHRNT = { 1638, 1}, - .VQSHRNB = { 1639, 1}, - .VQSHRNT = { 1640, 1}, - .VQRSHRNB = { 1641, 1}, - .VQRSHRNT = { 1642, 1}, - .VQSHRUNB = { 1643, 1}, - .VQSHRUNT = { 1644, 1}, - .VQRSHRUNB = { 1645, 1}, - .VQRSHRUNT = { 1646, 1}, - .VMOV_Q_R = { 1647, 1}, - .VMOV_R_Q = { 1648, 1}, - .VMOV_2GPR_Q = { 1649, 1}, - .VQDMLADH = { 1650, 1}, - .VQDMLADHX = { 1651, 1}, - .VQDMLSDH = { 1652, 1}, - .VQDMLSDHX = { 1653, 1}, - .VQRDMLADH = { 1654, 1}, - .VQRDMLADHX = { 1655, 1}, - .VQRDMLSDH = { 1656, 1}, - .VQRDMLSDHX = { 1657, 1}, - .VHCADD_SAT = { 1658, 1}, - .VCMLA_MVE = { 1659, 1}, - .VLDRB = { 1660, 1}, - .VLDRH = { 1661, 1}, - .VLDRW = { 1662, 1}, - .VLDRD = { 1663, 1}, - .VSTRB = { 1664, 1}, - .VSTRH = { 1665, 1}, - .VSTRW = { 1666, 1}, - .VSTRD = { 1667, 1}, - .VLD20 = { 1668, 1}, - .VLD21 = { 1669, 1}, - .VLD40 = { 1670, 1}, - .VLD41 = { 1671, 1}, - .VLD42 = { 1672, 1}, - .VLD43 = { 1673, 1}, - .VST20 = { 1674, 1}, - .VST21 = { 1675, 1}, - .VST40 = { 1676, 1}, - .VST41 = { 1677, 1}, - .VST42 = { 1678, 1}, - .VST43 = { 1679, 1}, - ._COUNT = { 1680, 0}, + .INVALID = { 0, 0}, + .AND = { 0, 11}, + .EOR = { 11, 9}, + .SUB = { 20, 10}, + .RSB = { 30, 8}, + .ADD = { 38, 12}, + .ADC = { 50, 9}, + .SBC = { 59, 9}, + .RSC = { 68, 6}, + .TST = { 74, 6}, + .TEQ = { 80, 5}, + .CMP = { 85, 8}, + .CMN = { 93, 6}, + .ORR = { 99, 9}, + .MOV = { 108, 12}, + .BIC = { 120, 9}, + .MVN = { 129, 9}, + .LSL = { 138, 6}, + .LSR = { 144, 6}, + .ASR = { 150, 6}, + .ROR = { 156, 5}, + .RRX = { 161, 1}, + .ADR = { 162, 1}, + .NEG = { 163, 1}, + .MOVW = { 164, 2}, + .MOVT = { 166, 2}, + .BFC = { 168, 2}, + .BFI = { 170, 2}, + .SBFX = { 172, 2}, + .UBFX = { 174, 2}, + .SXTB = { 176, 3}, + .SXTB16 = { 179, 2}, + .SXTH = { 181, 3}, + .UXTB = { 184, 3}, + .UXTB16 = { 187, 2}, + .UXTH = { 189, 3}, + .SXTAB = { 192, 2}, + .SXTAB16 = { 194, 2}, + .SXTAH = { 196, 2}, + .UXTAB = { 198, 2}, + .UXTAB16 = { 200, 2}, + .UXTAH = { 202, 2}, + .CLZ = { 204, 2}, + .RBIT = { 206, 2}, + .REV = { 208, 3}, + .REV16 = { 211, 3}, + .REVSH = { 214, 3}, + .SEL = { 217, 1}, + .PKHBT = { 218, 1}, + .PKHTB = { 219, 1}, + .USAD8 = { 220, 1}, + .USADA8 = { 221, 1}, + .SSAT = { 222, 2}, + .USAT = { 224, 2}, + .SSAT16 = { 226, 2}, + .USAT16 = { 228, 2}, + .QADD = { 230, 2}, + .QSUB = { 232, 2}, + .QDADD = { 234, 2}, + .QDSUB = { 236, 2}, + .SADD8 = { 238, 2}, + .SADD16 = { 240, 2}, + .SASX = { 242, 2}, + .SSAX = { 244, 2}, + .SSUB8 = { 246, 2}, + .SSUB16 = { 248, 2}, + .UADD8 = { 250, 2}, + .UADD16 = { 252, 2}, + .UASX = { 254, 2}, + .USAX = { 256, 2}, + .USUB8 = { 258, 2}, + .USUB16 = { 260, 2}, + .QADD8 = { 262, 2}, + .QADD16 = { 264, 2}, + .QASX = { 266, 2}, + .QSAX = { 268, 2}, + .QSUB8 = { 270, 2}, + .QSUB16 = { 272, 2}, + .UQADD8 = { 274, 2}, + .UQADD16 = { 276, 2}, + .UQASX = { 278, 2}, + .UQSAX = { 280, 2}, + .UQSUB8 = { 282, 2}, + .UQSUB16 = { 284, 2}, + .SHADD8 = { 286, 2}, + .SHADD16 = { 288, 2}, + .SHASX = { 290, 2}, + .SHSAX = { 292, 2}, + .SHSUB8 = { 294, 2}, + .SHSUB16 = { 296, 2}, + .UHADD8 = { 298, 2}, + .UHADD16 = { 300, 2}, + .UHASX = { 302, 2}, + .UHSAX = { 304, 2}, + .UHSUB8 = { 306, 2}, + .UHSUB16 = { 308, 2}, + .SMUAD = { 310, 1}, + .SMUADX = { 311, 1}, + .SMUSD = { 312, 1}, + .SMUSDX = { 313, 1}, + .SMLAD = { 314, 1}, + .SMLADX = { 315, 1}, + .SMLSD = { 316, 1}, + .SMLSDX = { 317, 1}, + .SMLALD = { 318, 1}, + .SMLALDX = { 319, 1}, + .SMLSLD = { 320, 1}, + .SMLSLDX = { 321, 1}, + .SMMUL = { 322, 1}, + .SMMULR = { 323, 1}, + .SMMLA = { 324, 1}, + .SMMLAR = { 325, 1}, + .SMMLS = { 326, 1}, + .SMMLSR = { 327, 1}, + .MUL = { 328, 4}, + .MLA = { 332, 3}, + .MLS = { 335, 2}, + .UMULL = { 337, 3}, + .UMLAL = { 340, 3}, + .SMULL = { 343, 3}, + .SMLAL = { 346, 3}, + .UMAAL = { 349, 1}, + .SMLABB = { 350, 1}, + .SMLABT = { 351, 1}, + .SMLATB = { 352, 1}, + .SMLATT = { 353, 1}, + .SMLAWB = { 354, 1}, + .SMLAWT = { 355, 1}, + .SMULBB = { 356, 1}, + .SMULBT = { 357, 1}, + .SMULTB = { 358, 1}, + .SMULTT = { 359, 1}, + .SMULWB = { 360, 1}, + .SMULWT = { 361, 1}, + .SMLALBB = { 362, 1}, + .SMLALBT = { 363, 1}, + .SMLALTB = { 364, 1}, + .SMLALTT = { 365, 1}, + .SDIV = { 366, 2}, + .UDIV = { 368, 2}, + .B = { 370, 5}, + .BL = { 375, 2}, + .BX = { 377, 2}, + .BLX = { 379, 3}, + .BXJ = { 382, 1}, + .CBZ = { 383, 1}, + .CBNZ = { 384, 1}, + .TBB = { 385, 1}, + .TBH = { 386, 1}, + .MSR = { 387, 3}, + .MRS = { 390, 2}, + .CPS = { 392, 1}, + .SETEND = { 393, 1}, + .NOP = { 394, 3}, + .YIELD = { 397, 3}, + .WFE = { 400, 3}, + .WFI = { 403, 3}, + .SEV = { 406, 3}, + .SEVL = { 409, 1}, + .DBG = { 410, 1}, + .HINT = { 411, 1}, + .DMB = { 412, 2}, + .DSB = { 414, 2}, + .ISB = { 416, 2}, + .CLREX = { 418, 2}, + .PLD = { 420, 2}, + .PLDW = { 422, 2}, + .PLI = { 424, 2}, + .HLT = { 426, 1}, + .DCPS1 = { 427, 1}, + .DCPS2 = { 428, 1}, + .DCPS3 = { 429, 1}, + .ERET = { 430, 1}, + .ESB = { 431, 2}, + .PSB_CSYNC = { 433, 2}, + .TSB_CSYNC = { 435, 2}, + .CSDB = { 437, 2}, + .SB = { 439, 2}, + .SETPAN = { 441, 2}, + .SVC = { 443, 2}, + .BKPT = { 445, 2}, + .HVC = { 447, 1}, + .SMC = { 448, 1}, + .UDF = { 449, 3}, + .LDR = { 452, 11}, + .STR = { 463, 9}, + .LDRB = { 472, 8}, + .STRB = { 480, 8}, + .LDRH = { 488, 8}, + .STRH = { 496, 8}, + .LDRSB = { 504, 7}, + .LDRSH = { 511, 7}, + .LDRD = { 518, 5}, + .STRD = { 523, 5}, + .LDRT = { 528, 1}, + .STRT = { 529, 1}, + .LDRBT = { 530, 1}, + .STRBT = { 531, 1}, + .LDRHT = { 532, 1}, + .STRHT = { 533, 1}, + .LDRSBT = { 534, 1}, + .LDRSHT = { 535, 1}, + .LDA = { 536, 1}, + .STL = { 537, 1}, + .LDAB = { 538, 1}, + .STLB = { 539, 1}, + .LDAH = { 540, 1}, + .STLH = { 541, 1}, + .LDREX = { 542, 2}, + .STREX = { 544, 2}, + .LDREXB = { 546, 2}, + .STREXB = { 548, 2}, + .LDREXH = { 550, 2}, + .STREXH = { 552, 2}, + .LDREXD = { 554, 2}, + .STREXD = { 556, 2}, + .LDAEX = { 558, 1}, + .STLEX = { 559, 1}, + .LDAEXB = { 560, 1}, + .STLEXB = { 561, 1}, + .LDAEXH = { 562, 1}, + .STLEXH = { 563, 1}, + .LDAEXD = { 564, 1}, + .STLEXD = { 565, 1}, + .LDM = { 566, 8}, + .STM = { 574, 8}, + .PUSH = { 582, 3}, + .POP = { 585, 3}, + .SWP = { 588, 1}, + .SWPB = { 589, 1}, + .RFE = { 590, 1}, + .SRS = { 591, 1}, + .CDP = { 592, 1}, + .CDP2 = { 593, 1}, + .MCR = { 594, 1}, + .MCR2 = { 595, 1}, + .MRC = { 596, 1}, + .MRC2 = { 597, 1}, + .MCRR = { 598, 1}, + .MCRR2 = { 599, 1}, + .MRRC = { 600, 1}, + .MRRC2 = { 601, 1}, + .LDC = { 602, 1}, + .LDC2 = { 603, 1}, + .STC = { 604, 1}, + .STC2 = { 605, 1}, + .CRC32B = { 606, 1}, + .CRC32H = { 607, 1}, + .CRC32W = { 608, 1}, + .CRC32CB = { 609, 1}, + .CRC32CH = { 610, 1}, + .CRC32CW = { 611, 1}, + .VADD = { 612, 18}, + .VSUB = { 630, 18}, + .VMUL = { 648, 24}, + .VDIV = { 672, 3}, + .VMLA = { 675, 18}, + .VMLS = { 693, 17}, + .VNMUL = { 710, 2}, + .VNMLA = { 712, 2}, + .VNMLS = { 714, 2}, + .VFMA = { 716, 10}, + .VFMS = { 726, 8}, + .VFNMA = { 734, 3}, + .VFNMS = { 737, 3}, + .VABS = { 740, 12}, + .VNEG = { 752, 12}, + .VSQRT = { 764, 3}, + .VCMP = { 767, 8}, + .VCMPE = { 775, 4}, + .VCVT = { 779, 21}, + .VCVTB = { 800, 2}, + .VCVTT = { 802, 2}, + .VCVTA = { 804, 2}, + .VCVTN = { 806, 2}, + .VCVTP = { 808, 2}, + .VCVTM = { 810, 2}, + .VCVTR = { 812, 4}, + .VMOV = { 816, 31}, + .VMRS = { 847, 1}, + .VMSR = { 848, 1}, + .VLDR = { 849, 2}, + .VSTR = { 851, 2}, + .VLDM = { 853, 2}, + .VSTM = { 855, 2}, + .VPUSH = { 857, 2}, + .VPOP = { 859, 2}, + .VSEL = { 861, 2}, + .VMAXNM = { 863, 2}, + .VMINNM = { 865, 2}, + .VRINTA = { 867, 3}, + .VRINTN = { 870, 3}, + .VRINTP = { 873, 3}, + .VRINTM = { 876, 3}, + .VRINTR = { 879, 2}, + .VRINTZ = { 881, 3}, + .VRINTX = { 884, 3}, + .VADDL = { 887, 6}, + .VADDW = { 893, 6}, + .VSUBL = { 899, 6}, + .VSUBW = { 905, 6}, + .VHADD = { 911, 9}, + .VHSUB = { 920, 9}, + .VRHADD = { 929, 3}, + .VQADD = { 932, 11}, + .VQSUB = { 943, 11}, + .VMULL = { 954, 11}, + .VMLAL = { 965, 10}, + .VMLSL = { 975, 10}, + .VQDMULL = { 985, 4}, + .VQDMLAL = { 989, 4}, + .VQDMLSL = { 993, 4}, + .VQDMULH = { 997, 8}, + .VQRDMULH = { 1005, 8}, + .VQRDMLAH = { 1013, 8}, + .VQRDMLSH = { 1021, 8}, + .VABA = { 1029, 8}, + .VABAL = { 1037, 6}, + .VABD = { 1043, 10}, + .VABDL = { 1053, 6}, + .VAND = { 1059, 3}, + .VBIC = { 1062, 3}, + .VORR = { 1065, 3}, + .VORN = { 1068, 3}, + .VEOR = { 1071, 3}, + .VBSL = { 1074, 2}, + .VBIT = { 1076, 2}, + .VBIF = { 1078, 2}, + .VMVN = { 1080, 13}, + .VMOVN = { 1093, 3}, + .VQMOVN = { 1096, 6}, + .VQMOVUN = { 1102, 3}, + .VMOVL = { 1105, 6}, + .VTST = { 1111, 6}, + .VCEQ = { 1117, 14}, + .VCGE = { 1131, 16}, + .VCGT = { 1147, 16}, + .VCLE = { 1163, 18}, + .VCLT = { 1181, 18}, + .VACGE = { 1199, 2}, + .VACGT = { 1201, 2}, + .VACLE = { 1203, 2}, + .VACLT = { 1205, 2}, + .VMAX = { 1207, 13}, + .VMIN = { 1220, 13}, + .VPMAX = { 1233, 5}, + .VPMIN = { 1238, 5}, + .VPADD = { 1243, 4}, + .VPADDL = { 1247, 6}, + .VPADAL = { 1253, 4}, + .VRECPE = { 1257, 4}, + .VRECPS = { 1261, 2}, + .VRSQRTE = { 1263, 4}, + .VRSQRTS = { 1267, 2}, + .VSHL = { 1269, 9}, + .VSHR = { 1278, 5}, + .VSRA = { 1283, 5}, + .VRSHL = { 1288, 5}, + .VRSHR = { 1293, 5}, + .VRSRA = { 1298, 2}, + .VSLI = { 1300, 2}, + .VSRI = { 1302, 2}, + .VQSHL = { 1304, 7}, + .VQSHRN = { 1311, 2}, + .VQSHRUN = { 1313, 1}, + .VQRSHL = { 1314, 16}, + .VQRSHRN = { 1330, 2}, + .VQRSHRUN = { 1332, 1}, + .VSHRN = { 1333, 1}, + .VRSHRN = { 1334, 1}, + .VSHLL = { 1335, 5}, + .VCLS = { 1340, 6}, + .VCLZ = { 1346, 6}, + .VCNT = { 1352, 2}, + .VPADD_F = { 1354, 2}, + .VRECPE_F = { 1356, 2}, + .VRSQRTE_F = { 1358, 2}, + .VREV16 = { 1360, 2}, + .VREV32 = { 1362, 4}, + .VREV64 = { 1366, 6}, + .VEXT = { 1372, 2}, + .VTBL = { 1374, 4}, + .VTBX = { 1378, 4}, + .VTRN = { 1382, 6}, + .VUZP = { 1388, 5}, + .VZIP = { 1393, 5}, + .VDUP = { 1398, 5}, + .VSWP = { 1403, 2}, + .VMOV_LANE = { 1405, 3}, + .VLD1 = { 1408, 8}, + .VLD2 = { 1416, 3}, + .VLD3 = { 1419, 2}, + .VLD4 = { 1421, 2}, + .VST1 = { 1423, 7}, + .VST2 = { 1430, 3}, + .VST3 = { 1433, 2}, + .VST4 = { 1435, 2}, + .AESE = { 1437, 1}, + .AESD = { 1438, 1}, + .AESMC = { 1439, 1}, + .AESIMC = { 1440, 1}, + .SHA1H = { 1441, 1}, + .SHA1SU0 = { 1442, 1}, + .SHA1SU1 = { 1443, 1}, + .SHA1C = { 1444, 1}, + .SHA1M = { 1445, 1}, + .SHA1P = { 1446, 1}, + .SHA256H = { 1447, 1}, + .SHA256H2 = { 1448, 1}, + .SHA256SU0 = { 1449, 1}, + .SHA256SU1 = { 1450, 1}, + .VJCVT = { 1451, 1}, + .VSDOT = { 1452, 4}, + .VUDOT = { 1456, 4}, + .VDOT = { 1460, 2}, + .VMMLA = { 1462, 1}, + .VFMAL = { 1463, 2}, + .VFMSL = { 1465, 2}, + .VCMLA = { 1467, 5}, + .VCADD = { 1472, 2}, + .VSMMLA = { 1474, 1}, + .VUMMLA = { 1475, 1}, + .VUSMMLA = { 1476, 1}, + .VSUDOT = { 1477, 2}, + .VUSDOT = { 1479, 4}, + .VQABS = { 1483, 1}, + .VQNEG = { 1484, 1}, + .VMOVX = { 1485, 1}, + .VINS = { 1486, 1}, + .VLD2R = { 1487, 1}, + .VLD3R = { 1488, 1}, + .VLD4R = { 1489, 1}, + .VLD1_LANE = { 1490, 3}, + .VLD2_LANE = { 1493, 3}, + .VLD3_LANE = { 1496, 3}, + .VLD4_LANE = { 1499, 3}, + .VST1_LANE = { 1502, 3}, + .VST2_LANE = { 1505, 3}, + .VST3_LANE = { 1508, 3}, + .VST4_LANE = { 1511, 3}, + .IT = { 1514, 1}, + .TT = { 1515, 1}, + .TTT = { 1516, 1}, + .TTA = { 1517, 1}, + .TTAT = { 1518, 1}, + .SG = { 1519, 1}, + .BXNS = { 1520, 1}, + .BLXNS = { 1521, 1}, + .PAC = { 1522, 1}, + .PACBTI = { 1523, 1}, + .AUT = { 1524, 1}, + .AUTG = { 1525, 1}, + .BTI = { 1526, 1}, + .WLS = { 1527, 1}, + .WLSTP = { 1528, 1}, + .DLS = { 1529, 1}, + .DLSTP = { 1530, 1}, + .LE = { 1531, 1}, + .LETP = { 1532, 1}, + .LCTP = { 1533, 1}, + .BF = { 1534, 1}, + .BFX = { 1535, 1}, + .BFL = { 1536, 1}, + .BFLX = { 1537, 1}, + .BFCSEL = { 1538, 1}, + .CX1 = { 1539, 1}, + .CX1A = { 1540, 1}, + .CX1D = { 1541, 1}, + .CX1DA = { 1542, 1}, + .CX2 = { 1543, 1}, + .CX2A = { 1544, 1}, + .CX2D = { 1545, 1}, + .CX2DA = { 1546, 1}, + .CX3 = { 1547, 1}, + .CX3A = { 1548, 1}, + .CX3D = { 1549, 1}, + .CX3DA = { 1550, 1}, + .VCX1 = { 1551, 2}, + .VCX1A = { 1553, 2}, + .VCX2 = { 1555, 2}, + .VCX2A = { 1557, 2}, + .VCX3 = { 1559, 2}, + .VCX3A = { 1561, 2}, + .VPT = { 1563, 1}, + .VPST = { 1564, 1}, + .VPSEL = { 1565, 1}, + .VPNOT = { 1566, 1}, + .VCTP = { 1567, 1}, + .VADDV = { 1568, 1}, + .VADDVA = { 1569, 1}, + .VADDLV = { 1570, 1}, + .VADDLVA = { 1571, 1}, + .VMAXV = { 1572, 1}, + .VMAXAV = { 1573, 1}, + .VMINV = { 1574, 1}, + .VMINAV = { 1575, 1}, + .VMAXNMV = { 1576, 1}, + .VMAXNMAV = { 1577, 1}, + .VMINNMV = { 1578, 1}, + .VMINNMAV = { 1579, 1}, + .VABAV = { 1580, 1}, + .VMLADAV = { 1581, 1}, + .VMLADAVA = { 1582, 1}, + .VMLADAVX = { 1583, 1}, + .VMLADAVAX = { 1584, 1}, + .VMLALDAV = { 1585, 1}, + .VMLALDAVA = { 1586, 1}, + .VMLALDAVX = { 1587, 1}, + .VMLALDAVAX = { 1588, 1}, + .VMLSDAV = { 1589, 1}, + .VMLSDAVA = { 1590, 1}, + .VMLSDAVX = { 1591, 1}, + .VMLSDAVAX = { 1592, 1}, + .VMLSLDAV = { 1593, 1}, + .VMLSLDAVA = { 1594, 1}, + .VMLSLDAVX = { 1595, 1}, + .VMLSLDAVAX = { 1596, 1}, + .VRMLALDAVH = { 1597, 1}, + .VRMLALDAVHA = { 1598, 1}, + .VRMLALDAVHX = { 1599, 1}, + .VRMLALDAVHAX = { 1600, 1}, + .VRMLSLDAVH = { 1601, 1}, + .VRMLSLDAVHA = { 1602, 1}, + .VRMLSLDAVHX = { 1603, 1}, + .VRMLSLDAVHAX = { 1604, 1}, + .VMLAV = { 1605, 1}, + .VMLAVA = { 1606, 1}, + .VMLSV = { 1607, 1}, + .VMLSVA = { 1608, 1}, + .VCMUL = { 1609, 1}, + .VHCADD = { 1610, 2}, + .VBRSR = { 1612, 1}, + .VSHLC = { 1613, 1}, + .VDDUP = { 1614, 1}, + .VIDUP = { 1615, 1}, + .VDWDUP = { 1616, 1}, + .VIWDUP = { 1617, 1}, + .VMOVNB = { 1618, 1}, + .VMOVNT = { 1619, 1}, + .VQMOVNB = { 1620, 1}, + .VQMOVNT = { 1621, 1}, + .VQMOVUNB = { 1622, 1}, + .VQMOVUNT = { 1623, 1}, + .VSHLLB = { 1624, 1}, + .VSHLLT = { 1625, 1}, + .VMULLB = { 1626, 1}, + .VMULLT = { 1627, 1}, + .VMLALB = { 1628, 1}, + .VMLALT = { 1629, 1}, + .VMLSLB = { 1630, 1}, + .VMLSLT = { 1631, 1}, + .VSHRNB = { 1632, 1}, + .VSHRNT = { 1633, 1}, + .VRSHRNB = { 1634, 1}, + .VRSHRNT = { 1635, 1}, + .VQSHRNB = { 1636, 1}, + .VQSHRNT = { 1637, 1}, + .VQRSHRNB = { 1638, 1}, + .VQRSHRNT = { 1639, 1}, + .VQSHRUNB = { 1640, 1}, + .VQSHRUNT = { 1641, 1}, + .VQRSHRUNB = { 1642, 1}, + .VQRSHRUNT = { 1643, 1}, + .VQDMLADH = { 1644, 1}, + .VQDMLADHX = { 1645, 1}, + .VQDMLSDH = { 1646, 1}, + .VQDMLSDHX = { 1647, 1}, + .VQRDMLADH = { 1648, 1}, + .VQRDMLADHX = { 1649, 1}, + .VQRDMLSDH = { 1650, 1}, + .VQRDMLSDHX = { 1651, 1}, + .VLDRB = { 1652, 2}, + .VLDRH = { 1654, 2}, + .VLDRW = { 1656, 2}, + .VLDRD = { 1658, 2}, + .VSTRB = { 1660, 2}, + .VSTRH = { 1662, 2}, + .VSTRW = { 1664, 2}, + .VSTRD = { 1666, 2}, + .VLD20 = { 1668, 1}, + .VLD21 = { 1669, 1}, + .VLD40 = { 1670, 1}, + .VLD41 = { 1671, 1}, + .VLD42 = { 1672, 1}, + .VLD43 = { 1673, 1}, + .VST20 = { 1674, 1}, + .VST21 = { 1675, 1}, + .VST40 = { 1676, 1}, + .VST41 = { 1677, 1}, + .VST42 = { 1678, 1}, + .VST43 = { 1679, 1}, + ._COUNT = { 1680, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 8363b7f377027192626f4d2ed963e77f83b1cb74..6af2948ae8ef2e51c1f951f667b0b5cdd631ebf3 100644 GIT binary patch delta 1731 zcmaiycWl&U7{__W`@8n8Z`FdXus07k-SD1=43|D1$uA$LUZG1z3m`ATSn-a0bkTaX1Uc;{==yb6_G)!nsfh^W-HJD`-iR zt%g(VMu03);csq%t*{-o!4B97yI?o$g*~tz_Q3(DfkSW*YT+;(funE?jz9P90xXB7 zw-*Jv;DnS}!X(w=lm@F^vW@p8H89}c=S~^njw)CN%b^-p!V35jR>5jmBmNeTEVbCB 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zcmd6p*_N9y5JVe1w!!O6X0rePf2OX=6@l%XJme+P0kwMHB&Zr|(A?Hb)dSqI9eU0? zO4gbTnLiq(S|d2`?%zmzWbGWC)^XOo+yi&cO)>BH_JN3*%Ms3dFM|(nr$brlff5Ys zrRJJyR|nzoWzZUEQ~QQP>qdO0BE>i>SKAxDAy%(l+f6H6Hjes5HfLGD9-77mVSjEA zHF~L|o>77u`M47t->X5qryK6@n>L6Wjax}yWMyj6u}6n#bORWxO@Ab7lvuWcfzDvE;yEMECK1=7P z`lxHu1`8I(<`)*0nN3c%R@Hc&pHK$rI!W^&9Xq{w91$YUyz8C_y}rxO*XGN$NfI|+ z@FvT21S@$Zn^^6U(m!N#kk_-KJBf=dv2(WI0Nynkvf$lyL`VhCH~o`h#twt{f!q_$ z^se~@75(JX8N*v@dz1{FfYe6&j6t~dDGS9b9*{ZSsVdz9?zT?4p`Zq8u8H zY;CpMH_P}R@}| z=tHz||HN|F2o9ax0cf*+*AcB~WCzs|XmcC%sH1^qi2TMsL!Dx)>~m^aqt|yTs=F;m zjT{d-vY$v92Zy#xgT^!#u5(h|69qpN1$XEtaC>f6R$I3tYyrz zj?@|824VP4h^Fv+UA`?v&tN50|M}GFwth&oTg7v{OI4|<;bhd$b$P|FRMlb@o@O|IdMq2U!05NN1;O?62REKB~eVuGXlUKlZ~l z?0;CTlT49C{vPOn Date: Thu, 27 Aug 2026 00:24:19 -0400 Subject: [PATCH 11/89] rexcode/arm32: make the NEON data type an instruction field NEON reuses one operand shape across every element width, so `vadd.i8` and `vadd.f32` are both DPR,DPR,DPR and only the type separates their encodings. The type existed nowhere in the data: the encoder could reach the first form of a shape and no other, and the printer reconstructed a suffix from the bit pattern at print time. 489 of 1680 forms -- 29% of the table -- were unreachable, and `inst_vadd(d0,d1,d2)` could only ever produce VFP vadd.f64. Add `Data_Type` and carry `dt: [2]Data_Type` on Instruction, Encoding and Decode_Entry. Two slots because the convert family names both ends (`vcvt.s32.f32`); everything else leaves the second .NONE. In A64 the arrangement belongs to each operand (`add v0.4s, v1.4s, v2.4s`); in A32 it belongs to the instruction, which is why it goes here and not on Operand. Instruction does not grow: it lands in bytes that were already padding, so 88 stays 88. Encoding and Decode_Entry go 21 -> 23, which is +3,360 B per table, +6.7 KB in all. The per-form type is derived from llvm-mc rather than hand-written: assemble each form's canonical word, disassemble it, take the suffix. 942 forms carry one, 38 carry two. (`.w` is the Thumb wide qualifier, not a type, and is excluded.) Effect: of 202 shape groups holding more than one form, 168 are now separated by the type -- 429 of the 489 unreachable forms become selectable. `dt` left at .NONE means "unspecified" and still takes the first matching form, so every existing caller behaves exactly as before. It also fixes printing. The old inference could only ever produce one type, so the whole convert family printed `vcvt.f32` -- 13 forms sharing one string that no assembler accepts. They now print `vcvt.f32.s32`, `vcvt.f64.f32`, `vcvta.u32.f64`, and so on. Verified: vadd.i8/i16/i32/i64/f32 encode to f2010802 / f2110802 / f2210802 / f2310802 / f2010d02, matching llvm-mc exactly; all 11 rexcode suites are identical to baseline. Still unreachable, 60 forms in 34 groups: register lists (VLD2-4/VST2-4), LDM/STM addressing modes, and a few lane-indexed and fixed-point convert forms whose element size is not captured by the type alone. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/decoder.odin | 3 + core/rexcode/isa/arm32/encoder.odin | 6 + core/rexcode/isa/arm32/encoding_types.odin | 27 +- core/rexcode/isa/arm32/instructions.odin | 8 +- core/rexcode/isa/arm32/printer.odin | 46 +- .../isa/arm32/tablegen/encoding_table.odin | 3360 ++++++++--------- core/rexcode/isa/arm32/tablegen/gen.odin | 16 +- .../tablegen/generated/decode_tables.odin | 3360 ++++++++--------- .../tablegen/generated/encode_tables.odin | 3360 ++++++++--------- core/rexcode/isa/arm32/tables.odin | 3 +- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 35280 -> 38640 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 35280 -> 38640 bytes 12 files changed, 5134 insertions(+), 5055 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index e975455c4..3347c3cf7 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -152,6 +152,9 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in // back to the index within ENCODING_TABLE[mnemonic]. Stored as // (form_idx + 1) so a zero hint means "not set". inst.form_id = DECODE_FORM_IDX[entry_idx] + 1 + // Carry the `.i32` suffix out with the instruction, so a decoded + // instruction re-encodes to the same form without needing form_id. + inst.dt = e.dt // Cond: A32 entries with bits[31:28] variable in mask take cond from word if mode == .A32 && (e.mask >> 28) == 0 { diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 065213e6d..80a699c8a 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -160,6 +160,7 @@ encode_one_inline :: #force_inline proc( if inst.form_id != 0 && int(inst.form_id) - 1 < len(forms) { f := &forms[inst.form_id - 1] if f.mode == inst.mode && + (inst.dt[0] == .NONE || f.dt == inst.dt) && (want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) && encoding_matches_inline(inst, f) && inst.flags.sets_flags == f.flags.sets_flags && @@ -170,6 +171,11 @@ encode_one_inline :: #force_inline proc( if form == nil { for &f in forms { if f.mode != inst.mode { continue } + // The `.i32` / `.s32.f32` suffix. NEON reuses one operand shape + // across every element width, so without this the scan can only + // ever reach the first form of a shape. .NONE means the caller did + // not say, and every form of the shape stays eligible. + if inst.dt[0] != .NONE && f.dt != inst.dt { continue } if want_len > 0 && inst_size_from_bits(f.bits, f.mode) != want_len { continue } if !encoding_matches_inline(inst, &f) { continue } if inst.flags.sets_flags && !f.flags.sets_flags { continue } diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 671389265..f0563547f 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -397,6 +397,30 @@ Operand_Encoding :: enum u8 { // ---- Encoding struct ------------------------------------------------------- +// The data type an A32 mnemonic carries as a suffix: `vadd.i32`, `vcvt.s32.f32`, +// `vstrb.8`. Unlike A64 -- where the arrangement belongs to each operand +// (`add v0.4s, v1.4s, v2.4s`) -- in A32 it belongs to the INSTRUCTION, which is +// why it lives here and on Instruction rather than on Operand. +// +// It is not decoration: NEON reuses one operand shape across every element +// width, so `vadd.i8` and `vadd.f32` are both DPR,DPR,DPR and the type is the +// only thing that separates their encodings. Without it the encoder can only +// ever reach the first form of each shape. +Data_Type :: enum u8 { + NONE, + S8, S16, S32, S64, // signed integer + U8, U16, U32, U64, // unsigned integer + I8, I16, I32, I64, // sign-agnostic integer + F16, F32, F64, // floating point + P8, P16, // polynomial + BF16, // bfloat16 + SZ8, SZ16, SZ32, SZ64, // bare element size (`vmov.32`, `vstrb.8`) +} + +// Two slots because the convert family names both ends: `vcvt.s32.f32`. +// Everything else leaves dt[1] as .NONE. +Data_Types :: [2]Data_Type + Encoding :: struct #packed { mnemonic: Mnemonic, // 2 ops: [4]Operand_Type, // 4 @@ -406,8 +430,9 @@ Encoding :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 } -#assert(size_of(Encoding) == 21) +#assert(size_of(Encoding) == 23) // ---- Length introspection -------------------------------------------------- // diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 1c343d583..192513a70 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -35,7 +35,13 @@ Instruction :: struct #packed { // bits). User-constructed instructions leave it at 0; the encoder then // falls back to first-shape-match. Stored as u16 over the two padding bytes. form_id: u16, - _: [7]u8, + // The `.i32` / `.s32.f32` suffix. Zero (.NONE) means "unspecified": the + // encoder then takes the first form of the matching shape, which is what + // every instruction did before this field existed. Set it and the encoder + // picks the encoding for that type. Fits in what was already padding, so + // Instruction does not grow. + dt: Data_Types, + _: [5]u8, } #assert(size_of(Instruction) == 88) diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 21c374197..8428dc513 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -108,21 +108,26 @@ sbprint :: proc( strings.write_string(sb, " ") - // Compute the .
suffix from the matched decoder entry (if any) - // and from the operand kinds when no entry is available. + // The `.
` suffix. It is data on the instruction now, so there is + // nothing to reconstruct: read it straight off. This is also what + // makes the convert family print correctly -- `vcvt.s32.f32` names + // both ends, and the old bit-pattern inference only ever produced one. dt_suffix := "" - if i < len(inst_info) { + dt := inst.dt + if dt[0] == .NONE && i < len(inst_info) { de_idx := int(inst_info[i].decode_entry) if de_idx < len(DECODE_ENTRIES) { - dt_suffix = infer_dt_suffix(&DECODE_ENTRIES[de_idx], inst) + dt = DECODE_ENTRIES[de_idx].dt } } - if dt_suffix == "" { + if dt[0] == .NONE { dt_suffix = infer_dt_suffix_from_inst(inst) } write_mnemonic(sb, inst.mnemonic, inst.cond, inst.flags.sets_flags, opts.uppercase) - if dt_suffix != "" { + if dt[0] != .NONE { + write_data_type(sb, dt, opts.uppercase) + } else if dt_suffix != "" { strings.write_string(sb, dt_suffix) } @@ -391,6 +396,35 @@ wprintln :: proc( // Writers // ============================================================================= +// `.i32`, `.s32.f32`, `.8`. Both slots print when the second is set. +@(private="file") +write_data_type :: proc(sb: ^strings.Builder, dt: Data_Types, uppercase: bool) { + for d in dt { + if d == .NONE { continue } + strings.write_byte(sb, '.') + name := DATA_TYPE_NAMES[d] + for i in 0 ..< len(name) { + c := name[i] + if uppercase && c >= 'a' && c <= 'z' { + strings.write_byte(sb, c - 'a' + 'A') + } else { + strings.write_byte(sb, c) + } + } + } +} + +@(rodata, private="file") +DATA_TYPE_NAMES := [Data_Type]string{ + .NONE = "", + .S8 = "s8", .S16 = "s16", .S32 = "s32", .S64 = "s64", + .U8 = "u8", .U16 = "u16", .U32 = "u32", .U64 = "u64", + .I8 = "i8", .I16 = "i16", .I32 = "i32", .I64 = "i64", + .F16 = "f16", .F32 = "f32", .F64 = "f64", + .P8 = "p8", .P16 = "p16", .BF16 = "bf16", + .SZ8 = "8", .SZ16 = "16", .SZ32 = "32", .SZ64 = "64", +} + @(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, cond: u8, sets_flags: bool, uppercase: bool) { name, _ := reflect.enum_name_from_value(m) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 105a7ba47..bcaf0a76f 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -71,233 +71,233 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---------- ADD ---------- .ADD = { // ADD imm: cond 0010 0100 S Rn Rd imm12_mod - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {}}, // ADD reg: cond 0000 0100 S Rn Rd shift_imm shift_type 0 Rm - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}, {}}, // ADD rsr: cond 0000 0100 S Rn Rd Rs 0 shift_type 1 Rm - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}, {}}, // ADDS variants - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 2 ADD reg (3-reg): 00011 00 Rm Rn Rd - {.ADD, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 2 ADD imm3: 00011 10 imm3 Rn Rd - {.ADD, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 3 ADD imm8: 00110 Rd imm8 - {.ADD, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg ADD: 010001 00 H1 H2 Rm Rd - {.ADD, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 12 ADD SP+imm: 10101 Rd imm8 (ADD Rd, SP, #imm8 << 2) - {.ADD, {.GPR_LOW, .GPR, .IMM8, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR, .IMM8, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 13 ADD SP, #imm7: 10110000 0 imm7 - {.ADD, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}, {}}, }, .ADC = { - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 ADC: 010000 0101 Rm Rd - {.ADC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ADC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ADC imm/reg (op=1010) - {.ADC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ADC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SUB = { - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 2 SUB reg (3-reg): 00011 01 Rm Rn Rd - {.SUB, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 2 SUB imm3: 00011 11 imm3 Rn Rd - {.SUB, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 3 SUB imm8: 00111 Rd imm8 - {.SUB, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 13 SUB SP, #imm7: 10110000 1 imm7 - {.SUB, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}, {}}, }, .SBC = { - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 SBC: 010000 0110 Rm Rd - {.SBC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.SBC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 SBC imm/reg (op=1011) - {.SBC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SBC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RSB = { - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T32 RSB imm/reg (op=1110) - {.RSB, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.RSB, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RSC = { - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, }, .AND = { - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 AND: 010000 0000 Rm Rd - {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 AND imm12: high=11110 i 0 0000 S Rn low=0 imm3 Rd imm8 - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 AND reg: high=11101 01 0000 S Rn low=imm3 Rd imm2 type Rm - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .EOR = { - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 EOR: 010000 0001 Rm Rd - {.EOR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.EOR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 EOR imm/reg - {.EOR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.EOR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ORR = { - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 ORR: 010000 1100 Rm Rd - {.ORR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ORR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ORR imm/reg (op=0010) - {.ORR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ORR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BIC = { - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 BIC: 010000 1110 Rm Rd - {.BIC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.BIC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 BIC imm/reg (op=0001) - {.BIC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BIC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // MOV and MVN have Rn unused (encoded as 0). The MOV-immediate form // additionally has ARMv6T2 MOVW (low half, no shift) and MOVT (high half). .MOV = { - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, + {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 3 MOV imm8: 00100 Rd imm8 - {.MOV, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.MOV, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg MOV: 010001 10 H1 H2 Rm Rd - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MOV imm12-mod (encoding T2): high=11110 i 0 0010 S 1111 low=0 imm3 Rd imm8 - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 MOV reg (encoding T3): high=11101 01 0010 S 1111 low=0 imm3 Rd imm2 00 Rm - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .MVN = { - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, + {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {}}, + {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 MVN: 010000 1111 Rm Rd - {.MVN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.MVN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MVN imm/reg (op=0011, Rn=15) - {.MVN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MVN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // MOVW / MOVT (ARMv6T2): 16-bit imm split as imm4(19:16) + imm12(11:0) .MOVW = { - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}}, + {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}, {}}, // T32 MOVW: high=11110 i 1 0010 0 imm4 low=0 imm3 Rd imm8 - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MOVT = { - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}}, + {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}, {}}, // T32 MOVT: high=11110 i 1 0110 0 imm4 - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Comparison-only ops: S is implicit-1, Rd is unused (encoded as 0). .TST = { - {.TST, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}}, - {.TST, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}}, + {.TST, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.TST, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 4 TST: 010000 1000 Rm Rn - {.TST, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.TST, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 TST imm/reg (op=0000, S=1, Rd=15) - {.TST, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.TST, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TEQ = { - {.TEQ, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}}, - {.TEQ, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}}, + {.TEQ, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.TEQ, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T32 TEQ imm/reg (op=0100, S=1, Rd=15) - {.TEQ, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.TEQ, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CMP = { - {.CMP, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}}, - {.CMP, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}}, + {.CMP, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.CMP, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 3 CMP imm8: 00101 Rn imm8 - {.CMP, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4 CMP reg: 010000 1010 Rm Rn - {.CMP, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg CMP: 010001 01 H1 H2 Rm Rn - {.CMP, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 CMP imm/reg (op=1101, S=1, Rd=15) - {.CMP, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CMP, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CMN = { - {.CMN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}}, - {.CMN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}}, + {.CMN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.CMN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 4 CMN: 010000 1011 Rm Rn - {.CMN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.CMN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 CMN imm/reg (op=1000, S=1, Rd=15) - {.CMN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CMN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -312,105 +312,105 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // The 1001 nibble at bits 7-4 is the discriminator from data-proc reg. .MUL = { - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}}, - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 MUL: 010000 1101 Rm Rd - {.MUL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.MUL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MUL: high=11111011 0000 Rn low=1111 Rd 0000 Rm - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MLA = { - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}}, - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 MLA: high=11111011 0000 Rn low=Ra Rd 0000 Rm - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MLS = { - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}}, + {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {}}, // T32 MLS: high=11111011 0000 Rn low=Ra Rd 0001 Rm - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UMULL = { - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}}, - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 UMULL: high=11111011 1010 Rn low=RdLo RdHi 0000 Rm - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UMLAL = { - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}}, - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 UMLAL: high=11111011 1110 Rn low=RdLo RdHi 0000 Rm - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SMULL = { - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}}, - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 SMULL: high=11111011 1000 Rn low=RdLo RdHi 0000 Rm - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SMLAL = { - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}}, - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 SMLAL: high=11111011 1100 Rn low=RdLo RdHi 0000 Rm - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // (MLA/MLS/UMULL/UMLAL/SMULL/SMLAL declared earlier in MUL block region.) .UMAAL = { - {.UMAAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}}, + {.UMAAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {}}, }, // ARMv5TE halfword multiply (SMLAxy / SMULxy / SMLAWy / SMULWy / SMLALxy) // Encoding: cond 00010 op0 op1 Rd Rn Rs 1 y x 0 Rm // op0/op1 distinguishes family. x/y selects top/bottom halfword of Rm/Rs. - .SMLABB = { {.SMLABB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLABT = { {.SMLABT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLATB = { {.SMLATB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLATT = { {.SMLATT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLAWB = { {.SMLAWB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLAWT = { {.SMLAWT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMULBB = { {.SMULBB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULBT = { {.SMULBT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULTB = { {.SMULTB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULTT = { {.SMULTT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULWB = { {.SMULWB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULWT = { {.SMULWT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMLALBB = { {.SMLALBB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALBT = { {.SMLALBT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALTB = { {.SMLALTB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALTT = { {.SMLALTT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}} }, + .SMLABB = { {.SMLABB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLABT = { {.SMLABT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLATB = { {.SMLATB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLATT = { {.SMLATT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLAWB = { {.SMLAWB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLAWT = { {.SMLAWT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMULBB = { {.SMULBB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULBT = { {.SMULBT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULTB = { {.SMULTB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULTT = { {.SMULTT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULWB = { {.SMULWB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULWT = { {.SMULWT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMLALBB = { {.SMLALBB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALBT = { {.SMLALBT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALTB = { {.SMLALTB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALTT = { {.SMLALTT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, // ARMv6: dual multiply - .SMUAD = { {.SMUAD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUADX = { {.SMUADX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUSD = { {.SMUSD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUSDX = { {.SMUSDX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMLAD = { {.SMLAD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}} }, - .SMLADX = { {.SMLADX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSD = { {.SMLSD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSDX = { {.SMLSDX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}} }, - .SMLALD = { {.SMLALD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}} }, - .SMLALDX = { {.SMLALDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSLD = { {.SMLSLD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSLDX = { {.SMLSLDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}} }, + .SMUAD = { {.SMUAD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUADX = { {.SMUADX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUSD = { {.SMUSD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUSDX = { {.SMUSDX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMLAD = { {.SMLAD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLADX = { {.SMLADX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSD = { {.SMLSD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSDX = { {.SMLSDX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLALD = { {.SMLALD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLALDX = { {.SMLALDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSLD = { {.SMLSLD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSLDX = { {.SMLSLDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {}} }, // Most-significant-word multiply (ARMv6) - .SMMUL = { {.SMMUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMMULR = { {.SMMULR, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMMLA = { {.SMMLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLAR = { {.SMMLAR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLS = { {.SMMLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLSR = { {.SMMLSR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}} }, + .SMMUL = { {.SMMUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMMULR = { {.SMMULR, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMMLA = { {.SMMLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLAR = { {.SMMLAR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLS = { {.SMMLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLSR = { {.SMMLSR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {}} }, // ARMv7-A optional / ARMv7-R/M: integer division .SDIV = { - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}}, + {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {}}, // T32 SDIV: high=11111011 1001 Rn low=1111 Rd 1111 Rm - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}}, + {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UDIV = { - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}}, + {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {}}, // T32 UDIV: high=11111011 1011 Rn low=1111 Rd 1111 Rm - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}}, + {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -419,24 +419,24 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ARMv5TE saturating arithmetic .QADD = { - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QADD: high=11111010 1000 Rn low=1111 Rd 1000 Rm - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB = { - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QSUB: bits 5:4 = 10 - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QDADD = { - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QDADD: bits 5:4 = 01 - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QDSUB = { - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QDSUB: bits 5:4 = 11 - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 signed parallel arithmetic (8-bit and 16-bit lanes) @@ -445,191 +445,191 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 0001 ADD16 0011 ASX 0101 SAX 0111 SUB16 // 1001 ADD8 1111 SUB8 .SADD16 = { - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}}, + {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SADD16: high=11111010 1001 Rn low=1111 Rd 0000 Rm - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SASX = { - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}}, + {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SASX: 0xFAA0F000 - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSAX = { - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}}, + {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSAX: 0xFAE0F000 - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSUB16 = { - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}}, + {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSUB16: 0xFAD0F000 - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SADD8 = { - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}}, + {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SADD8: 0xFA80F000 - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSUB8 = { - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}}, + {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSUB8: 0xFAC0F000 - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 saturating parallel arithmetic (op family 0110 0010) // Q* (signed saturating): T32 bits 6:4 = 001 .QADD16 = { - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QASX = { - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}}, - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSAX = { - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}}, - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB16 = { - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QADD8 = { - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB8 = { - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 signed halving (T32 bits 6:4 = 010) .SHADD16 = { - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHASX = { - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}}, - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSAX = { - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSUB16 = { - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHADD8 = { - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSUB8 = { - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned parallel arithmetic (op family 0110 0101) .UADD16 = { - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}}, + {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 UADD16: high=11111010 1001 Rn low=1111 Rd 0100 Rm - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UASX = { - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAX = { - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}}, - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USUB16 = { - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UADD8 = { - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USUB8 = { - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned saturating (T32 bits 6:4 = 101) .UQADD16 = { - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQASX = { - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSAX = { - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSUB16 = { - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQADD8 = { - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSUB8 = { - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned halving (T32 bits 6:4 = 110) .UHADD16 = { - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHASX = { - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSAX = { - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSUB16 = { - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHADD8 = { - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSUB8 = { - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 saturate to width .SSAT = { - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}}, + {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {}}, // T32 SSAT: high=11110 0 1 1000 0 Rn low=0 imm3 Rd imm2 0 sat_imm - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT = { - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}}, - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSAT16 = { - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}}, + {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSAT16: high=11110 0 1 1001 0 Rn low=0 000 Rd 0000 sat_imm - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT16 = { - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}}, - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 USAD8 / USADA8 - .USAD8 = { {.USAD8, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .USADA8 = { {.USADA8, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}} }, + .USAD8 = { {.USAD8, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .USADA8 = { {.USADA8, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {}} }, // ========================================================================= // ยง4 -- Extends + bit-field + REV + CLZ + RBIT + SEL + PKHBT/TB @@ -638,130 +638,130 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // PKHBT / PKHTB (pack halfword) // PKHBT: cond 0110 1000 Rn Rd shift_imm 001 Rm // PKHTB: cond 0110 1000 Rn Rd shift_imm 101 Rm - .PKHBT = { {.PKHBT, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}} }, - .PKHTB = { {.PKHTB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}} }, + .PKHBT = { {.PKHBT, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}, {}} }, + .PKHTB = { {.PKHTB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}, {}} }, // Sign-extend / zero-extend (with optional rotation of Rm by 0/8/16/24) // Encoding: cond 0110 1xx0 1111 Rd rotate 0 0 0111 Rm -- variant 1 (no Rn) // cond 0110 1xx0 Rn Rd rotate 0 0 0111 Rm -- variant 2 (with Rn = SXTAB/etc.) .SXTB = { - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 SXTB: 1011 0010 01 Rm Rd - {.SXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.SXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 SXTB (with rotate): high=11111010 0100 1111 low=1111 Rd 1 0 rot Rm - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTB16 = { - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T32 SXTB16 - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTH = { - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 SXTH: 1011 0010 00 Rm Rd - {.SXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.SXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 SXTH: 0xFA0FF080 - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTB = { - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 UXTB: 1011 0010 11 Rm Rd - {.UXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.UXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 UXTB: 0xFA5FF080 - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTB16 = { - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T32 UXTB16 - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTH = { - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 UXTH: 1011 0010 10 Rm Rd - {.UXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.UXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 UXTH: 0xFA1FF080 - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAB = { - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}}, + {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}, {}}, // T32 SXTAB: high=11111010 0100 Rn low=1111 Rd 1 0 rot Rm - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAB16 = { - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}}, - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}, {}}, + {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAH = { - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}}, - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAB = { - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAB16 = { - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAH = { - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Byte-reverse / count leading zeros / select / reverse bits .REV = { - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}}, + {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REV: 1011 1010 00 Rm Rd - {.REV, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REV, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REV: high=11111010 1001 Rm low=1111 Rd 1000 Rm - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .REV16 = { - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, + {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REV16: 1011 1010 01 Rm Rd - {.REV16, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REV16, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REV16: bits 5:4 = 01 - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .REVSH = { - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, + {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REVSH: 1011 1010 11 Rm Rd - {.REVSH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REVSH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REVSH: bits 5:4 = 11 - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RBIT = { - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}}, + {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}, {}}, // T32 RBIT: bits 5:4 = 10 - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CLZ = { - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}}, + {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {}}, // T32 CLZ: high=11111010 1011 Rm low=1111 Rd 1000 Rm - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, - .SEL = { {.SEL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}} }, + .SEL = { {.SEL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}, {}} }, // Bit field operations (ARMv6T2) .BFC = { - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD, .BFI_LSB, .BFI_MSB, .NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}}, + {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD, .BFI_LSB, .BFI_MSB, .NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {}}, // T32 BFC: high=11110 0 1 1011 0 1111 low=0 imm3 Rd imm2 0 msb - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD_T32, .BFI_LSB_T32, .BFI_MSB, .NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD_T32, .BFI_LSB_T32, .BFI_MSB, .NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BFI = { - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}}, + {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 BFI: high=11110 0 1 1011 0 Rn low=0 imm3 Rd imm2 0 msb - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SBFX = { - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 SBFX - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UBFX = { - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 UBFX - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -770,139 +770,139 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // B / BL: cond 101 L imm24 .B = { - {.B, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, + {.B, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {}}, // T16 Format 16 B: 1101 cond imm8 - {.B, {.REL8, .COND, .NONE, .NONE}, {.BRANCH_8_T16, .NONE, .NONE, .NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}}, + {.B, {.REL8, .COND, .NONE, .NONE}, {.BRANCH_8_T16, .NONE, .NONE, .NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}}, // T16 Format 18 B unconditional: 11100 imm11 - {.B, {.REL11, .NONE, .NONE, .NONE}, {.BRANCH_11_T16, .NONE, .NONE, .NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.B, {.REL11, .NONE, .NONE, .NONE}, {.BRANCH_11_T16, .NONE, .NONE, .NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, // T32 B: high=11110 S cond imm6 low=10 J1 0 J2 imm11 - {.B, {.REL20, .COND, .NONE, .NONE}, {.BRANCH_20_T32, .NONE, .NONE, .NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.B, {.REL20, .COND, .NONE, .NONE}, {.BRANCH_20_T32, .NONE, .NONE, .NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, // T32 B unconditional: high=11110 S imm10 low=10 J1 1 J2 imm11 - {.B, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.B, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, }, .BL = { - {.BL, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, + {.BL, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {}}, // Thumb-1 / Thumb-2 BL (4 bytes): high=11110 S imm10 low=11 J1 1 J2 imm11 - {.BL, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.BL, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, }, // BX / BLX (register form) -- ARMv4T+ for BX, ARMv5T+ for BLX_reg .BX = { - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}}, + {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {}}, // T16 Format 5 BX: 010001 11 0 Rm 000 - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, }, .BLX = { // BLX register: cond 0001 0010 1111 1111 1111 0011 Rm - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}}, + {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}, {}}, // BLX immediate (unconditional class): 1111 101 H imm24 -- H=bit24 toggles ARM/Thumb - {.BLX, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BLX, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, // T16 Format 5 BLX reg: 010001 11 1 Rm 000 - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, }, - .BXJ = { {.BXJ, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}} }, + .BXJ = { {.BXJ, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}, {}} }, // SVC (was SWI): cond 1111 imm24 .SVC = { - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.A32_IMM24, .NONE, .NONE, .NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}}, + {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.A32_IMM24, .NONE, .NONE, .NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {}}, // T16 Format 17 SVC: 11011111 imm8 - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, }, // BKPT (unconditional class but uses cond=NV reserved encoding traditionally): // cond 0001 0010 imm12 0111 imm4 (cond=AL only) .BKPT = { - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {cond_in_28=false}}, + {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {cond_in_28=false}, {}}, // T16 BKPT: 1011 1110 imm8 - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {cond_in_28=false}}, + {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {cond_in_28=false}, {}}, }, // HVC: 0001 0100 imm12 0111 imm4 - .HVC = { {.HVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {cond_in_28=false}} }, + .HVC = { {.HVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {cond_in_28=false}, {}} }, // SMC: cond 0001 0110 0000 0000 0000 0111 imm4 - .SMC = { {.SMC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}} }, + .SMC = { {.SMC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {}} }, // UDF: 1111 0111 1111 imm12 1111 imm4 (permanently undefined) .UDF = { - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {cond_in_28=false}, {}}, // T16 UDF: 1101 1110 imm8 - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 UDF: high=11110 0 1111 1111 imm4 low=10 1 0 imm12 - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // HLT (ARMv8 AArch32): 0001 0000 imm12 0111 imm4 - .HLT = { {.HLT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {cond_in_28=false}} }, + .HLT = { {.HLT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {cond_in_28=false}, {}} }, // MSR / MRS (status reg access) .MRS = { - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, // T32 MRS: high=11110011 1110 1111 low=10 0 0 Rd 0000 0000 - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MSR = { // MSR APSR_, #imm12_mod (immediate form) - {.MSR, {.PSR_FIELD, .IMM_MOD, .NONE, .NONE}, {.PSR_FIELD_MASK, .A32_IMM_MOD, .NONE, .NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}}, + {.MSR, {.PSR_FIELD, .IMM_MOD, .NONE, .NONE}, {.PSR_FIELD_MASK, .A32_IMM_MOD, .NONE, .NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}, {}}, // MSR APSR_, Rn (register form) - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RM_A32, .NONE, .NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}}, + {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RM_A32, .NONE, .NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {}}, // T32 MSR: high=11110011 1000 Rn low=10 0 0 mask 0000 0000 - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RN_T32, .NONE, .NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RN_T32, .NONE, .NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CPS (change processor state, ARMv6): 1111 0001 0000 imod M iflags mode_field - .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}} }, + .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}, {}} }, // SETEND (deprecated in ARMv8): 1111 0001 0000 0001 0000 000E 0000 0000 - .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}} }, + .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, // SETPAN (ARMv8.1): A32 = 1111 0001 0001 0000 0000 0000 imm1 0000 0000 โ†’ bit 9 = imm // T16: 1011 0110 0001 0 imm1 000 โ†’ bit 3 = imm .SETPAN = { - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {cond_in_28=false}}, - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {cond_in_28=false}}, + {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {cond_in_28=false}, {}}, + {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {cond_in_28=false}, {}}, }, // ---- Hint instructions (cond 0011 0010 0000 1111 0000 0000 imm8 OR encoded form) .NOP = { - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {}}, // T16 NOP: 1011 1111 0000 0000 - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, // T32 NOP: high=11110011 1010 1111 low=10000000 hint - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .YIELD = { - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .WFE = { - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .WFI = { - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SEV = { - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, - .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}} }, - .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}} }, - .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}} }, + .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {}} }, + .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, + .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {}} }, // Memory barriers (ARMv7): 1111 0101 0111 1111 1111 0000 type imm4 .DMB = { - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, + {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, // T32 DMB: F3BF 8F50 + type - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .DSB = { - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, + {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ISB = { - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, + {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- HINT-family barriers (ARMv8 FEAT_RAS / FEAT_SPE / FEAT_TRF / FEAT_CSV2) ---- @@ -911,58 +911,58 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ESB (Error Synchronization Barrier, FEAT_RAS) -- HINT #16 .ESB = { - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}}, - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // PSB CSYNC (Profiling Synchronization Barrier, FEAT_SPE) -- HINT #17 .PSB_CSYNC = { - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}}, - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // TSB CSYNC (Trace Synchronization Barrier, FEAT_TRF) -- HINT #18 .TSB_CSYNC = { - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}}, - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CSDB (Consumption of Speculative Data Barrier, FEAT_CSV2) -- HINT #20 .CSDB = { - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}}, - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SB (Synchronization Barrier, FEAT_SB, ARMv8.5) -- dedicated barrier encoding // A32: 1111 0101 0111 1111 1111 0000 0111 0000 = 0xF57FF070 // T32: 1111 0011 1011 1111 1000 1111 0111 0000 = 0xF3BF8F70 .SB = { - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}}, - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}, {}}, + {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CLREX (clear exclusive monitor, ARMv6K+) .CLREX = { - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {cond_in_28=false}}, + {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {cond_in_28=false}, {}}, // T32 CLREX - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true, cond_in_28=false}}, + {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Preload data / instruction (PLD/PLDW/PLI) .PLD = { - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {cond_in_28=false}}, + {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {cond_in_28=false}, {}}, // T32 PLD imm12: 0xF890F000 - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PLDW = { - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {cond_in_28=false}}, + {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {cond_in_28=false}, {}}, // T32 PLDW imm12: 0xF830F000 - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PLI = { - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}}, + {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}}, // T32 PLI imm12: 0xF990F000 - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ERET (exception return, ARMv7VE+) - .ERET = { {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}} }, + .ERET = { {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {}} }, // ========================================================================= // ยง6 -- Load / Store (single + multiple) @@ -973,139 +973,139 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // We split into three variants per direction: imm-offset, pre-index, post-index. .LDR = { // LDR imm12 offset: P=1 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 pre-index: P=1 W=1 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 post-index: P=0 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR reg offset: cond 011 P U 0 W 1 Rn Rt shift_imm shift_type 0 Rm - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 6 LDR PC-relative: 01001 Rd imm8 (LDR Rd, [PC, #imm8 << 2]) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 7 LDR reg-offset: 0101 100 Rm Rb Rd - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 LDR imm5: 01101 imm5 Rb Rd (offset = imm5 << 2) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 11 LDR SP-relative: 10011 Rd imm8 (LDR Rd, [SP, #imm8 << 2]) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDR imm12 offset: high=11111000 1101 Rn low=Rt imm12 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDR reg offset: high=11111000 0101 Rn low=Rt 000000 imm2 Rm - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDR literal: high=11111000 X101 1111 low=Rt imm12 (PC-relative) - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STR = { - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STR reg-offset: 0101 000 Rm Rb Rd - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STR imm5: 01100 imm5 Rb Rd (offset = imm5 << 2) - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 11 STR SP-relative: 10010 Rd imm8 (STR Rd, [SP, #imm8 << 2]) - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STR imm12: 0xF8C00000 - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 STR reg: 0xF8400000 base - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRB = { - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 LDRB reg-offset: 0101 110 Rm Rb Rd - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 LDRB imm5: 01111 imm5 Rb Rd - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRB imm12 / reg - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRB = { - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STRB reg-offset: 0101 010 Rm Rb Rd - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STRB imm5: 01110 imm5 Rb Rd - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STRB imm12 / reg - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // LDRH / STRH / LDRSB / LDRSH / LDRD / STRD: cond 000 P U I W L Rn Rt imm4H 1 op2 1 imm4L // where op2 = 01 (halfword), 10 (signed byte), 11 (signed half / doubleword) .LDRH = { // LDRH imm offset (P=1 W=0): cond 000 1 U 1 0 1 Rn Rt imm4H 1011 imm4L - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, // LDRH reg offset: cond 000 1 U 0 0 1 Rn Rt 0000 1011 Rm - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRH reg-offset: 0101 101 Rm Rb Rd - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 LDRH imm5: 10001 imm5 Rb Rd (offset = imm5 << 1) - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRH imm12 / reg - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRH = { - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 STRH reg-offset: 0101 001 Rm Rb Rd - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 STRH imm5: 10000 imm5 Rb Rd - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STRH imm12 / reg - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSB = { - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSB reg-offset: 0101 011 Rm Rb Rd - {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSB imm12 / reg - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSH = { - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSH reg-offset: 0101 111 Rm Rb Rd - {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSH imm12 / reg - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRD = { // LDRD imm offset (ARMv5TE+): cond 000 P U 1 W 0 Rn Rt imm4H 1101 imm4L - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 LDRD imm8: high=11101001 X101 Rn low=Rt Rt2 imm8 - {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRD = { - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 STRD imm8: high=11101001 X100 Rn low=Rt Rt2 imm8 - {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Load/Store multiple (LDM/STM family). cond 100 P U S W L Rn register_list @@ -1116,64 +1116,64 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // base register + register-list into Rn + register_list operand slots. .LDM = { // LDM IA (default) - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMIA writeback (LDM Rn!, {reglist}): W=1 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMIB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMDA - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMDB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 LDMIA: 11001 Rb reg_list8 - {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDMDB: high=11101001 0001 Rn low=PM 0 reg_list14 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STM = { - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 STMIA: 11000 Rb reg_list8 - {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STMIA: 0xE8800000 - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 STMDB: 0xE9000000 - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // PUSH / POP are conventional aliases for STMDB SP! / LDMIA SP! .PUSH = { - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {}}, // T16 Format 14 PUSH: 1011010 R reg_list8 (R bit selects LR included) - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 PUSH (STMDB SP!, reglist): 0xE92D0000 - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .POP = { - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {}}, // T16 Format 14 POP: 1011110 R reg_list8 (R bit selects PC included) - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 POP (LDMIA SP!, reglist): 0xE8BD0000 - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SWP / SWPB (deprecated since ARMv6) - .SWP = { {.SWP, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}} }, - .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}} }, + .SWP = { {.SWP, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, + .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, // RFE / SRS (return-from-exception / store return state) .RFE = { // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 - {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}}, + {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}, {}}, }, .SRS = { // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 - {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}}, + {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}, {}}, }, // ========================================================================= @@ -1182,94 +1182,94 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // LDREX family (ARMv6K+, then ARMv7 added all widths) .LDREX = { - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREX: high=11101000 0101 Rn low=Rt 1111 imm8 - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREX = { - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREX: high=11101000 0100 Rn low=Rt Rd imm8 - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXB = { - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREXB: high=11101000 1101 Rn low=Rt 1111 0100 1111 - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXB = { - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREXB: high=11101000 1100 Rn low=Rt 1111 0100 Rd - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXH = { - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, + {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXH = { - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, + {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXD = { - {.LDREXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREXD: high=11101000 1101 Rn low=Rt Rt2 0111 1111 - {.LDREXD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXD = { - {.STREXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREXD: high=11101000 1100 Rn low=Rt Rt2 0111 Rd - {.STREXD, {.GPR, .GPR, .GPR, .MEM}, {.RD_T32, .RT_T32, .RT2_T32, .RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXD, {.GPR, .GPR, .GPR, .MEM}, {.RD_T32, .RT_T32, .RT2_T32, .RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv8 acquire/release (LDA/STL family, exclusive too) - .LDA = { {.LDA, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}} }, + .LDA = { {.LDA, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, // STL/STLB/STLH: per ARMv8 ARM, Rt is at bits 3:0 (NOT 15:12); bits 15:12 are // 0xF fixed. Use RM_A32 enc for Rt to place it correctly. - .STL = { {.STL, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAB = { {.LDAB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLB = { {.STLB, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAH = { {.LDAH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLH = { {.STLH, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAEX = { {.LDAEX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEX = { {.STLEX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXB = { {.LDAEXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXB = { {.STLEXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXH = { {.LDAEXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXH = { {.STLEXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXD = { {.LDAEXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXD = { {.STLEXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}} }, + .STL = { {.STL, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAB = { {.LDAB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLB = { {.STLB, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAH = { {.LDAH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLH = { {.STLH, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAEX = { {.LDAEX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEX = { {.STLEX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXB = { {.LDAEXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXB = { {.STLEXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXH = { {.LDAEXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXH = { {.STLEXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXD = { {.LDAEXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXD = { {.STLEXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, // ========================================================================= // ยง8 -- Coprocessor + CRC32 + Crypto // ========================================================================= // CDP / CDP2: cond 1110 opc1 CRn CRd cp_num opc2 0 CRm - .CDP = { {.CDP, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}} }, - .CDP2 = { {.CDP2, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {cond_in_28=false}} }, + .CDP = { {.CDP, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {}} }, + .CDP2 = { {.CDP2, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {cond_in_28=false}, {}} }, // MCR / MCR2 / MRC / MRC2: cond 1110 opc1 L CRn Rt cp_num opc2 1 CRm - .MCR = { {.MCR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}} }, - .MCR2 = { {.MCR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {cond_in_28=false}} }, - .MRC = { {.MRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}} }, - .MRC2 = { {.MRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {cond_in_28=false}} }, + .MCR = { {.MCR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {}} }, + .MCR2 = { {.MCR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {cond_in_28=false}, {}} }, + .MRC = { {.MRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {}} }, + .MRC2 = { {.MRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {cond_in_28=false}, {}} }, // MCRR / MCRR2 / MRRC / MRRC2: cond 1100 010 0/1 Rt2 Rt cp_num opc CRm - .MCRR = { {.MCRR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}} }, - .MCRR2 = { {.MCRR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {cond_in_28=false}} }, - .MRRC = { {.MRRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}} }, - .MRRC2 = { {.MRRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {cond_in_28=false}} }, + .MCRR = { {.MCRR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {}} }, + .MCRR2 = { {.MCRR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {cond_in_28=false}, {}} }, + .MRRC = { {.MRRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {}} }, + .MRRC2 = { {.MRRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {cond_in_28=false}, {}} }, // LDC / STC: cond 110 P U N W L Rn CRd cp_num imm8 - .LDC = { {.LDC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}} }, - .LDC2 = { {.LDC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {cond_in_28=false}} }, - .STC = { {.STC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}} }, - .STC2 = { {.STC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {cond_in_28=false}} }, + .LDC = { {.LDC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}, {}} }, + .LDC2 = { {.LDC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {cond_in_28=false}, {}} }, + .STC = { {.STC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}, {}} }, + .STC2 = { {.STC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {cond_in_28=false}, {}} }, // ARMv8 CRC32 family // cond 0001 0 sz 0 Rn Rd 0000 0 0 1 0 0 Rm sz=00 byte / 01 half / 10 word // bit 9 selects CRC32 (0) vs CRC32C (1). - .CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}} }, + .CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, // ========================================================================= @@ -1302,121 +1302,121 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // forms. The matcher dispatches on operand types. .VADD = { // VFP scalar - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar (FEAT_FP16): cp=1001 - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 vector: 1111 0010 0 D 1 0 Vn Vd 1101 N Q M 0 Vm (bit 4 = 0 for VADD) - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (D-reg), size = 00/01/10/11 - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON integer (Q-reg) - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON F32 (D and Q) - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer: Q-only, T32, 1110 1111 0 0 sz Qn Qd 1000 N 1 M 0 Qm - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // MVE FP: 1110 1111 0 0 sz Qn Qd 1101 N 1 M 1 Qm - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // MVE scalar Rm (Qd, Qn, Rt): per LLVM vadd.i8 q1,q2,r3 = 0xEE05_2F43 -> base 0xEE010F40 - {.VADD, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, .VSUB = { // VFP scalar - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 (bit 4 = 0 for VSUB; bit 21 = 1 selects sub) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (D-reg) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON integer (Q-reg) - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON F32 (D and Q) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer / FP / scalar - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // VSUB MVE scalar: per LLVM 0xEE05_3F43 -> base 0xEE011F40 - {.VSUB, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // (VMUL/VMLA/VMLS are declared further below with both VFP scalar and // NEON vector forms in a single block.) .VDIV = { - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VDIV, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VDIV, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, .VNMUL = { - {.VNMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, .VNMLS = { - {.VNMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, .VNMLA = { - {.VNMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VFPv4 fused multiply-add .VFMA = { - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F32: 1111 0010 0 D 0 0 Vn Vd 1100 N Q M 1 Vm - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector + scalar - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VFMS = { - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F32 (bit 21 = 1) - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, + {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VFNMS = { - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFNMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, .VFNMA = { - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFNMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, // ---- 2-operand unary FP (opc1=1011 op2=xxxx) ---- @@ -1424,27 +1424,27 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // opc2 (bits 19:16): 0000 VMOV, 0001 VNEG, 0010 VSQRT, etc. // (VABS / VNEG: VFP scalar + NEON forms declared together further below.) .VSQRT = { - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VSQRT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VSQRT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar (cp=1001) - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}}, + {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, // VMOV reg-reg (opc2=0000, op=0) .VMOV = { - {.VMOV, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VMOV, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VMOV, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMOV, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VMOV imm (opc1=1011 opc2=0000 op=0, imm in (19:16)+(3:0) split) - {.VMOV, {.SPR, .IMM8, .NONE, .NONE}, {.VD_S, .VFP_IMM8, .NONE, .NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}}, - {.VMOV, {.DPR, .IMM8, .NONE, .NONE}, {.VD_D, .VFP_IMM8, .NONE, .NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}}, + {.VMOV, {.SPR, .IMM8, .NONE, .NONE}, {.VD_S, .VFP_IMM8, .NONE, .NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32, .NONE}}, + {.VMOV, {.DPR, .IMM8, .NONE, .NONE}, {.VD_D, .VFP_IMM8, .NONE, .NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64, .NONE}}, // VMOV GPR <-> S reg: cond 1110 000 op L Vn Rt 1010 N 0010000 - {.VMOV, {.SPR, .GPR, .NONE, .NONE}, {.VN_S, .RT_A32, .NONE, .NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}}, - {.VMOV, {.GPR, .SPR, .NONE, .NONE}, {.RT_A32, .VN_S, .NONE, .NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}}, + {.VMOV, {.SPR, .GPR, .NONE, .NONE}, {.VN_S, .RT_A32, .NONE, .NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {}}, + {.VMOV, {.GPR, .SPR, .NONE, .NONE}, {.RT_A32, .VN_S, .NONE, .NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {}}, // VMOV two GPRs <-> D reg (VMOV Rt, Rt2, Dm) - {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}}, + {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // VMOV two GPRs <-> two consecutive S regs - {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}}, + {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // ---- VMOV NEON modified immediate ---- // 1111 0010 1 D 000 imm3 Vd cmode 0 Q op 1 imm4 (op=0 VMOV, op=1 VMVN) // cmode mappings (8 forms when op=0): @@ -1459,79 +1459,79 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1110 .I8 โ†’ 0xF2800E10 // 1111 .F32 (special: high bit = 0) โ†’ 0xF2800F10 (limited to specific imm patterns) // 1110 op=1 + bit 5 set โ†’ .I64 โ†’ 0xF2800E30 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=1100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=1101 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I8 cmode=1110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .F32 cmode=1111 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I64 (op=0+bit5=1) + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) // Q forms (Q=1, bit 6 = 1) - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I16 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I8 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .F32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I64 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q // ---- VMOV scalar to/from GPR (lane access) ---- // VMOV. Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000 // VMOV. Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000 // .8 / .16 / .32 selected by opc1+opc2 split bits in encoding. // 32-bit lane move (.32): - {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}}, - {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}}, + {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] - {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV. Rt, Qd[i] - {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move - {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- VMVN NEON modified immediate (op=1 form) ---- // bit 5 = 1 distinguishes VMVN from VMOV .VMVN = { - {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, // VMVN immediate: 1111 0010 1 D 000 imm3 Vd cmode 0 Q 1 1 imm4 (op=1) - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Q forms - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // MVE VMVN Qd, Qm - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCMP / VCMPE: cond 1110 1011 D 0100 Vd 101 sz E 1 M 0 Vm (E=1 raises invalid op on QNaN) .VCMP = { - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VCMP with zero: cond 1110 1011 D 0101 Vd 101 sz E 1 (0) 0 0000 - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}}, + {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, // MVE VCMP Qn, Qm -- writes VPR.P0. Per LLVM: // vcmp.i8 eq,q2,q3 -> 0xFE05_0F06 base 0xFE01_0F00 // vcmp.f32 eq,q2,q3 -> 0xEE35_0F06 base 0xEE31_0F00 - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VCMPE = { - {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, + {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VCVT family: int<->float and float<->float @@ -1540,164 +1540,164 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F32<->half-prec: VCVTB/VCVTT .VCVT = { // VCVT.F64.F32 Dd, Sm (cond 1110 1011 D 0111 Vd 1010 11 M 0 Vm) sz=0 (output F32)... actually inverse: - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .F32}}, // VCVT.F32.F64 Sd, Dm (sz=1 output F64; opc2=0111) - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .F64}}, // VCVT.S32.F32 Sd, Sm (opc2=1101 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}}, // VCVT.U32.F32 Sd, Sm (opc2=1100 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}}, // VCVT.S32.F64 Sd, Dm - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F64}}, // VCVT.U32.F64 Sd, Dm - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F64}}, // VCVT.F32.S32 Sd, Sm (opc2=1000 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .S32}}, // VCVT.F32.U32 Sd, Sm (opc2=1000 op=0) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .U32}}, // VCVT.F64.S32 Dd, Sm - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .S32}}, // VCVT.F64.U32 Dd, Sm - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .U32}}, // VCVT.BF16.F32 D, Q // vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600 - {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}}, + {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}, {.F16, .F32}}, // VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}}, // VCVT.U32.F32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}}, // VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}}, // VCVT.F32.U32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}}, // VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16, .F32}}, // VCVT.F32.S16 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32, .S16}}, // F64 variants (sz=1): change cp to 1011 (bit 8 = 1) - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}}, // F16 variants (cp=1001, FEAT_FP16) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}}, }, .VCVTB = { // VCVTB.F32.F16 / .F16.F32 - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .F16}}, + {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16, .F32}}, }, .VCVTT = { - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .F16}}, + {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16, .F32}}, }, // ARMv8: VCVTA/N/P/M (rounding-mode FP-to-int) - cond=1111 (unconditional class) .VCVTA = { - {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTN = { - {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTP = { - {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTM = { - {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, // VMRS / VMSR (access FPSCR + friends as GPR) // VMRS: cond 1110 1111 0001 Rt 1010 0001 0000 (Rt=PC means transfer to APSR.NZCV) - .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}} }, - .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}} }, + .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, + .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, // VLDR / VSTR (single / double): cond 1101 U D 0 1 Rn Vd 101 sz imm8 .VLDR = { - {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}}, + {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, .VSTR = { - {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}}, + {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, // VLDM / VSTM (multiple S or D regs): cond 110 P U D W L Rn Vd 101 sz imm8 // IA = P=0 U=1 ; DB = P=1 U=0 ; W=1 writeback; L=1 load / 0 store. .VLDM = { - {.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}}, + {.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {}}, + {.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {}}, }, .VSTM = { - {.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}}, + {.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {}}, + {.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {}}, }, .VPUSH = { - {.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPUSH, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, + {.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, + {.VPUSH, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, }, .VPOP = { - {.VPOP, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPOP, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, + {.VPOP, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, + {.VPOP, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, }, // ARMv8 FP min/max NaN-aware (VMAXNM/VMINNM), VSEL, VRINT* .VMAXNM = { - {.VMAXNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, - {.VMAXNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, + {.VMAXNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMAXNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VMINNM = { - {.VMINNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, - {.VMINNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, + {.VMINNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMINNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VSEL = { // VSEL.F32/F64 Sd, Sn, Sm -- cond field at bits 21-20 + 7 - {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false}}, - {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false}}, + {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VRINTA = { - {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE Q-form (FEAT_MVE_FP): per LLVM `vrinta.f32 q1, q3` -> 0xFFBA_0540 - {.VRINTA, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTA, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTN = { - {.VRINTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTP = { - {.VRINTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTM = { - {.VRINTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTM, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTM, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTR = { - {.VRINTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTR, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTR, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, }, .VRINTZ = { - {.VRINTZ, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTZ, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, // MVE - {.VRINTZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTX = { - {.VRINTX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTX, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTX, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, // MVE - {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // VJCVT (ARMv8.3): F64 -> S32 with JS-style rounding - .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}} }, + .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {}} }, // ---- VFP F16 scalar arithmetic (FEAT_FP16) ---- // Uses coproc 9 (cp_num = 1001) instead of 10/11 used by F32/F64. @@ -1724,526 +1724,526 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---- VMUL (integer + F32) ---- .VMUL = { // VFP scalar - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (.I8/.I16/.I32) D form: 1111 0010 0 size Vn Vd 1001 N 0 M 1 Vm - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON integer Q form - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON polynomial (.P8): U=1 bit 24 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // NEON F32 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer / FP / scalar - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // VMUL MVE scalar: per LLVM 0xEE05_3E63 -> base 0xEE011E60 - {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // Integer D-form .I16/.I32 - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Integer Q-form .I16/.I32 (bit 24 = 1) - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 D-form / Q-form (F=1, size=10) - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON integer (multiply-accumulate) - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE VMLA Qda, Qn, Rm (scalar) - {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 (F=1) - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON integer (op-bit at 24 distinguishes VMLA vs VMLS for U=1) - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 (bit 21 = 1 distinguishes FMLS from FMLA) - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { // VAND D: 1111 0010 0000 Vn Vd 0001 N 0 M 1 Vm (no size; always byte-wise) - {.VAND, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VAND, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBIC = { // VBIC D: 1111 0010 0100 Vn Vd 0001 N 0 M 1 Vm - {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORR = { - {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORN = { - {.VORN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VORN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VEOR = { // U=1 distinguishes VEOR from VAND family - {.VEOR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VEOR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- VBSL / VBIT / VBIF (predicated bitwise select) ---- .VBSL = { - {.VBSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, .VBIT = { - {.VBIT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBIT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, .VBIF = { - {.VBIF, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIF, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBIF, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIF, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, // ---- VMAX / VMIN (integer + F32) ---- .VMAX = { // NEON integer signed (U=0) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON integer unsigned (U=1) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // NEON F32 - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 (sz bit 20 = 1) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // MVE integer (VMAX.F32 doesn't exist in MVE; use VMAXNM.F32 instead) - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMIN = { // bit 4 distinguishes MAX (0) vs MIN (1) within the 0x6_0 op family - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 (bit 21 = 1 selects MIN) - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 (sz=1) - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // MVE integer (VMIN.F32 doesn't exist; use VMINNM.F32) - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VCEQ / VCGT / VCGE (compare) ---- .VCEQ = { // NEON integer (op family 0x8_0) - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // F16 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // F16 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { // signed: F200_0010; unsigned: F300_0010 - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, // unsigned - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQSUB = { - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VHADD / VHSUB / VRHADD ---- .VHADD = { - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VHSUB = { - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VRHADD = { - {.VRHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // MVE - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VPADD (pairwise add, D-form only) ---- .VPADD = { // NEON integer (op 0xB10, bit 4 = 1) - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // F32 - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPADD MVE form doesn't exist; MVE uses VADDV reduction instead) }, // ---- VPMAX / VPMIN (D-form only) ---- .VPMAX = { - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPMAX MVE form doesn't exist; MVE uses VMAXV reduction) }, .VPMIN = { - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPMIN MVE form doesn't exist; MVE uses VMINV reduction) }, // ---- VTST (test bits) ---- .VTST = { - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VABD (absolute difference) ---- .VABD = { // signed - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 (bit 21=1 selects FP) - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VABA (accumulate absolute difference) ---- .VABA = { - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // ---- VSHL register (variable shift) ---- .VSHL = { // signed: F200_0400; unsigned: F300_0400 - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, // unsigned shift by reg - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VSHR immediate (signed/unsigned, .I8/.I16/.I32/.I64) .VSHR = { - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // unsigned - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE imm form (imm6 at bits 21:16) - {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VSRA imm .VSRA = { - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE (imm6 at bits 21:16) - {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VQSHL imm (saturating shift left) .VQSHL = { // register form (signed): F200_0410 - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // unsigned: F300_0410 - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // immediate form: F2800710 - {.VQSHL, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VQSHL, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VRSHL (rounding shift left) .VRSHL = { - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VRSHR (rounding shift right immediate) .VRSHR = { - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE - {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VSLI / VSRI (shift left/right and insert) .VSLI = { - {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSRI = { - {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VABS / VNEG / VMVN / VCNT / VCLZ / VCLS (NEON unary) ---- // (VABS/VNEG VFP scalar already declared; here we add NEON forms.) .VABS = { // VFP scalar (already declared near top of ยง9, here we extend the block) - {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer: 1111 0011 1011 size 01 Vd 0011 0 Q M 0 Vm - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 (size=10, bit 10 = 1) - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vabs.s8 q,q = FFB1_0340; vabs.f32 q,q = FFB9_0740 (bit 19 = 1 for FP). - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VNEG = { - {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer (bit 7 = 1 distinguishes VNEG from VABS) - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vneg.s8 q,q = FFB1_03C0; vneg.f32 q,q = FFB9_07C0. - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // (VMVN declared earlier in VMOV neighbourhood with reg + immediate forms.) .VCNT = { // Byte-only: 1111 0011 1011 0000 size00 Vd 0101 0 Q M 0 Vm - {.VCNT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCNT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VCLZ = { - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VCLS = { - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VREV16 / VREV32 / VREV64 (byte/half/word reverse within block) ---- .VREV64 = { - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VREV32 = { - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, }, .VREV16 = { - {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV16, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV16, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VEXT (vector extract) ---- .VEXT = { // 1111 0010 1011 Vn Vd imm4 N Q M 0 Vm - {.VEXT, {.DPR, .DPR, .DPR, .IMM4}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {cond_in_28=false}}, - {.VEXT, {.QPR, .QPR, .QPR, .IMM4}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {cond_in_28=false}}, + {.VEXT, {.DPR, .DPR, .DPR, .IMM4}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VEXT, {.QPR, .QPR, .QPR, .IMM4}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {cond_in_28=false}, {.SZ64, .NONE}}, }, // ---- VDUP (duplicate scalar/reg to vector) ---- @@ -2253,37 +2253,37 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Variant: vector D[lane] form (1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm) // We list the common scalar/Rt form for V_8B/V_16B/V_4H/V_8H/V_2S/V_4S. // (encoder picks based on operand kinds) - {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}}, - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}}, + {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, + {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, // VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm - {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}}, - {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}}, + {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, // MVE VDUP Qd, Rt - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTRN / VUZP / VZIP (interleave / deinterleave) ---- .VTRN = { - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VUZP = { - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VZIP = { - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTBL / VTBX (table lookup) ---- @@ -2291,46 +2291,46 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // len = 00,01,10,11 selects 1/2/3/4-vec table; op=0 TBL, 1 TBX .VTBL = { // 1-vec table - {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 2-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 3-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 4-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VTBX = { - {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VRECPE / VRSQRTE (reciprocal estimates) ---- .VRECPE = { // Integer: 1111 0011 1011 1011 Vd 0100 0 Q M 0 Vm; FP: bit 8 = 1 - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // FP form - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VRECPE MVE form doesn't exist in current MVE spec) }, .VRSQRTE = { - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VRSQRTE MVE form doesn't exist) }, // VRECPS / VRSQRTS (reciprocal step) .VRECPS = { - {.VRECPS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRECPS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRECPS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VRSQRTS = { - {.VRSQRTS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VLD1 / VST1 (most-used load/store multiple structures) ---- @@ -2339,307 +2339,307 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // have distinct opcode bits; included as separate entries. .VLD1 = { // VLD1 multiple (1-reg list, type=0111, size=00/01/10/11, D form) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (2-reg list, type=1010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (3-reg list, type=0110) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (4-reg list, type=0010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane to all lanes (VLD1R): 1111 0100 1 D 10 Rn Vd 1100 size T a Rm // size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector) - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .8 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .16 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .32 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, .VST1 = { // VST1 multiple (1-reg list) - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .8 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .16 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .32 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, // VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits .VLD2 = { - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST2 = { - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD3 = { - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST3 = { - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD4 = { - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST4 = { - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VMULL / VMLAL / VMLSL (widening multiplies) ---- .VMULL = { // signed: 1111 0010 1U sz Vn Vd 1100 N 0 M 0 Vm - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // polynomial: U=0, op=10 - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // signed .S16/.S32 - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned .U16/.U32 (top byte 0xF3) - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // VMLAL / VMLSL (widening multiply-accumulate) // VMLAL: signed F2800800 / unsigned F3800800; op=1000 (no minus); minus bit at 21 .VMLAL = { - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VMLSL = { // VMLSL: op=1010 (bit 9 = 1) - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // ---- VQDMULH / VQRDMULH (saturating doubling multiply, high half) ---- // 1111 0010 0 D size Vn Vd 1011 N Q M 0 Vm (VQDMULH) // 1111 0011 0 D size Vn Vd 1011 N Q M 0 Vm (VQRDMULH) .VQDMULH = { - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMULH = { - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VQRDMLAH / VQRDMLSH (ARMv8.1 FEAT_RDM, rounding doubling MAC) ---- // VQRDMLAH: 1111 0011 0 D size Vn Vd 1011 N Q M 1 Vm (size = 01 .S16 or 10 .S32) // VQRDMLSH: 1111 0011 0 D size Vn Vd 1100 N Q M 1 Vm .VQRDMLAH = { - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMLSH = { - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMULL: 1111 0010 1 D size Vn Vd 1101 N 0 M 0 Vm .VQDMULL = { - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMLAL / VQDMLSL (saturating doubling multiply-accumulate long) .VQDMLAL = { // signed: 1111 0010 1 D size Vn Vd 1001 N 0 M 0 Vm - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQDMLSL = { // signed: 1111 0010 1 D size Vn Vd 1011 N 0 M 0 Vm - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VMOVL / VMOVN / VQMOVN / VQMOVUN (widening/narrowing moves) ---- .VMOVL = { // VMOVL.S Q, D : 1111 0010 1 D imm3 0 0 0 Vd 1010 0 0 M 1 Vm (imm3 = size) // We list signed/unsigned ร— 3 sizes (.S8/.S16/.S32 and .U variants) - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S8 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S16 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S32 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U8 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U16 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U32 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .S8 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, // .S16 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // .S32 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // .U8 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, // .U16 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // .U32 }, .VMOVN = { // VMOVN.I D, Q : 1111 0011 1 D 11 size 10 Vd 0010 0 0 M 0 Vm - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I16 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I32 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I64 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 }, .VQMOVN = { // VQMOVN. (signed saturating narrowing move) // .S: 1111 0011 1 D 11 size 10 Vd 0010 1 0 M 0 Vm // .U: same with op bit 6 = 1 - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, .VQMOVUN = { // VQMOVUN (signed input, unsigned saturating output): 1111 0011 1 D 11 size 10 Vd 0010 0 1 M 0 Vm (bit 6=1, bit 7=0) - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, }, // ---- VSHLL / VSHRN / VRSHRN / VQSHRN / VQRSHRN ---- .VSHLL = { // VSHLL.S Q, D, #imm: 1111 0010 1 D imm6 Vd 1010 0 0 M 1 Vm // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, // U=1 + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1 // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm - {.VSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VRSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 1 M 1 Vm - {.VRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRN = { // signed: 1111 0010 1 D imm6 Vd 1001 0 0 M 1 Vm; unsigned: U=1 - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRN = { // 1111 0010 1 D imm6 Vd 1001 0 1 M 1 Vm - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRUN = { // signed input, unsigned saturating shift right narrow: // 1111 0011 1 D imm6 Vd 1000 0 0 M 1 Vm - {.VQSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRUN = { - {.VQRSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, // ---- VPADDL / VPADAL (pairwise add long / accumulate) ---- // 1111 0011 1 D 11 size 00 Vd 0010 op Q M 0 Vm (op=0 add long, op=1 accumulate) .VPADDL = { // .S: - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // Q form - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .U variants: bit 7 = 1 - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VPADAL = { // op4=0110 instead of 0010 (bit 8=1) - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // unsigned - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // ---- VSWP (swap) ---- // 1111 0011 1 D 11 size 10 Vd 0000 0 Q M 0 Vm .VSWP = { - {.VSWP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSWP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSWP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VSWP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, }, // ---- VACGE / VACGT (FP absolute compare) ---- .VACGE = { // 1111 0011 0 D 0 sz Vn Vd 1110 N Q M 1 Vm - {.VACGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VACGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VACGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACGT = { // sz bit 21 = 1 - {.VACGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VACGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VACGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // NEON crypto (ARMv8 FEAT_AES / FEAT_SHA1 / FEAT_SHA256) // AESE/AESD/AESMC/AESIMC: 1111 0011 1011 size 00 Vd 0011 op M 0 Vm (op=0 AESE, 1 AESD; bit 7 selects MC) - .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, + .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, // SHA1 family - .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, + .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, // ========================================================================= // ยง11 -- T16 Thumb-1 + T32 Thumb-2 (Thumb-only mnemonics) @@ -2662,74 +2662,74 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 010000 op4 Rs Rd op4=0010 LSL, 0011 LSR, 0100 ASR, 0111 ROR .LSL = { // A32: MOV reg with LSL #imm (cond 00011010 0000 Rd imm5 000 Rm) - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}, {}}, // A32: MOV reg with LSL Rs (RSR form) - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: LSL imm - {.LSL, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LSL, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: LSL reg (Rd = Rd <<= Rs) - {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSL imm (encoded as MOV with shift LSL): high=11101010 0100 1111 low=0 imm3 Rd imm2 00 Rm - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSL reg: high=11111010 0000 Rn low=1111 Rd 0000 Rm - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LSR = { - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}}, - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: LSR imm - {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: LSR reg - {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSR imm (MOV with shift LSR): bits 5:4 = 01 - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSR reg: 0xFA20F000 - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ASR = { - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}}, - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: ASR imm - {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: ASR reg - {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ASR imm: bits 5:4 = 10 - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ASR reg: 0xFA40F000 - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ROR = { - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}}, - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 4: ROR reg - {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ROR imm: bits 5:4 = 11 - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ROR reg: 0xFA60F000 - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RRX = { // RRX is ROR with imm=0 (cond 00011010 0000 Rd 00000110 Rm) - {.RRX, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}}, + {.RRX, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {}}, }, // T16 Format 12: ADR (ADD Rd, PC, #imm8 << 2) .ADR = { // A32 ADR forms (ADD/SUB to PC); handled via ADD encoded with Rn=PC. // T16 Format 12 form (10100 Rd imm8): - {.ADR, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADR, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, }, // T16 NEG Rd, Rm = RSB Rd, Rm, #0 (Format 4, op=1001) .NEG = { - {.NEG, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.NEG, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, }, - .CBZ = { {.CBZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}} }, - .CBNZ = { {.CBNZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}} }, - .IT = { {.IT, {.COND, .IMM4, .NONE, .NONE}, {.NONE, .IT_MASK, .NONE, .NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {cond_in_28=false}} }, - .TBB = { {.TBB, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}} }, - .TBH = { {.TBH, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}} }, + .CBZ = { {.CBZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}} }, + .CBNZ = { {.CBNZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}} }, + .IT = { {.IT, {.COND, .IMM4, .NONE, .NONE}, {.NONE, .IT_MASK, .NONE, .NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {cond_in_28=false}, {}} }, + .TBB = { {.TBB, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}} }, + .TBH = { {.TBH, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}} }, // ========================================================================= // ยง14 -- Extensions: Dot product / FCMA / FHM / BF16 @@ -2738,19 +2738,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // FEAT_DotProd (ARMv8.2-A): VSDOT/VUDOT (8-bit signed/unsigned dot product) .VSDOT = { // VSDOT.S8 D: 0xFC200D00 - {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VUDOT (unsigned): bit 4 = 1 distinguishes from VSDOT (bit 4 = 0). // vudot.u8 d0,d1,d2 = 0xFC21_0D12 -> base 0xFC200D10 .VUDOT = { - {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, // vudot.u8 d0,d1,d2[0] = 0xFE21_0D12 -> base 0xFE200D10 (bit 4 = 1 for U) - {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // FEAT_FCMA (ARMv8.3): VCMLA / VCADD (complex multiply-add + add) @@ -2758,36 +2758,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCADD: rotation in bit 24 only (2 values: 90, 270 deg) .VCMLA = { // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand - {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VCADD = { // Mask 0xFE800F10 leaves bit 24 variable for rotation operand (90 or 270) - {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}}, + {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, // FEAT_FHM (ARMv8.2): FP16 fused multiply-add long .VFMAL = { - {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}}, - {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}}, + {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, }, .VFMSL = { - {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}}, - {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}}, + {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, }, // FEAT_BF16 (ARMv8.6): BFloat16 arithmetic and conversion .VDOT = { // VDOT.BF16 D, D, D - {.VDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}}, - {.VDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, + {.VDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VMMLA = { - {.VMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, // ========================================================================= @@ -2797,13 +2797,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VUMMLA Qd, Qn, Qm: 1111 1100 0 D 1 0 Vn Vd 1100 N 1 M 1 Vm (unsigned) // VUSMMLA Qd, Qn, Qm: 1111 1100 1 D 1 0 Vn Vd 1100 N 1 M 0 Vm (mixed) .VSMMLA = { - {.VSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, .VUMMLA = { - {.VUMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSMMLA = { - {.VUSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VSUDOT Qd, Qn, Qm[idx]: 1111 1110 1 D 00 Vn Vd 1101 N Q M 1 Vm // VUSDOT Qd, Qn, Qm: 1111 1100 0 D 10 Vn Vd 1101 N Q M 0 Vm @@ -2811,14 +2811,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vusdot.s8 d0,d1,d2 = 0xFCA1_0D02 -> base 0xFCA00D00 // vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only) .VSUDOT = { - {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {}}, + {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSDOT = { - {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // ========================================================================= @@ -2848,21 +2848,21 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VQABS Qd, Qm: 1111 1111 1 D 11 size 00 Vd 0111 1 1 M 0 Vm // VQNEG Qd, Qm: 1111 1111 1 D 11 size 00 Vd 0111 1 1 M 1 Vm .VQABS = { - {.VQABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQNEG = { - {.VQNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VMOVX Sd, Sm (extract high F16 lane to bottom of Sd) -- ARMv8.2 FP16 // 1111 1110 1 D 11 0000 Vd 1010 01 M 0 Vm .VMOVX = { - {.VMOVX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, // VINS Sd, Sm (insert F16 from Sm into high half of Sd) // 1111 1110 1 D 11 0000 Vd 1010 11 M 0 Vm .VINS = { - {.VINS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VINS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, // ---- MVE gather/scatter (vector offset addressing) ---------------------- @@ -2902,13 +2902,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vld3.8 {d1[], d2[], d3[]}, [r2] = 0xF4A2_1E0F -> base 0xF4A0_0E0F // vld4.8 {d1[], d2[], d3[], d4[]}, [r2] = 0xF4A2_1F0F -> base 0xF4A0_0F0F .VLD2R = { - {.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD3R = { - {.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD4R = { - {.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ========================================================================= @@ -2918,45 +2918,45 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // N=00 VLDx1, 01 VLDx2, 10 VLDx3, 11 VLDx4 (x = 1..4) // VLD1_LANE Dd[i], [Rn]: size=00 (.8) 0xF4A00000, size=01 (.16) 0xF4A00400, size=10 (.32) 0xF4A00800 .VLD1_LANE = { - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD2_LANE = { - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD3_LANE = { - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD4_LANE = { - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // VST1/2/3/4 single-lane: bit 21 = 0 (store, not load) .VST1_LANE = { - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST2_LANE = { - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST3_LANE = { - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST4_LANE = { - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ========================================================================= @@ -2970,29 +2970,29 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // TTAT : A=1 T=1 -> 0xE840F0C0 // mask 0xFFF0FFC0 keeps Rn and Rd variable, fixes A and T bits per mnemonic. .TT = { - {.TT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTT = { - {.TTT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTA = { - {.TTA, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTA, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTAT = { - {.TTAT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTAT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SG: Secure Gateway -- 32-bit T32 instruction that looks like two NOPs // bits = 0xE97F E97F .SG = { - {.SG, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.SG, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // BXNS Rm: T16 16-bit, 0100 0111 0 Rm[3:0] 100 = 0x4704 base, bit 2 = 1 .BXNS = { - {.BXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}}, + {.BXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}, {}}, }, // BLXNS Rm: T16, 0100 0111 1 Rm[3:0] 100 = 0x4784 base .BLXNS = { - {.BLXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}}, + {.BLXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}, {}}, }, // ========================================================================= @@ -3004,20 +3004,20 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // AUTG Rd, Rn, Rm: more general form using FB50F000 base // BTI: HINT #15 = 0xF3AF80F0 .PAC = { - {.PAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.PAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PACBTI = { - {.PACBTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.PACBTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .AUT = { - {.AUT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.AUT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .AUTG = { // AUTG Rd, Rn, Rm: 1111 1011 0101 Rn 1111 Rd 0000 Rm - {.AUTG, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.AUTG, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BTI = { - {.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -3030,26 +3030,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // LETP / WLSTP / DLSTP: same family with TP variant bit // LCTP: 1111 0000 0000 1111 1110 0 0000 0000 0000 1 .WLS = { - {.WLS, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.WLS, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .WLSTP = { // WLSTP.: bits 22:20 carry size selector (B/H/W/D) - {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, .DLS = { - {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .DLSTP = { - {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .LE = { - {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .LETP = { - {.LETP, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.LETP, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .LCTP = { - {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // BF / BFL / BFLX / BFX (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1. @@ -3057,22 +3057,22 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target // is a register Rm at hw0[3:0]. (BFCSEL has an extra else-target + condition.) .BF = { - {.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .BFL = { - {.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, .BFLX = { - {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .BFX = { - {.BFX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, // BFCSEL: bf-point + true-target (hw1, like BF) + 4-bit condition at hw0[5:2]; // hw0[1] is a static marker. The else-target is the architectural fall-through // (implicit) so it is not a separate operand. .BFCSEL = { - {.BFCSEL, {.REL_BF, .REL_BF, .IMM4, .NONE}, {.BF_BOFF, .BF_BLOC, .BFCSEL_COND, .NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFCSEL, {.REL_BF, .REL_BF, .IMM4, .NONE}, {.BF_BOFF, .BF_BLOC, .BFCSEL_COND, .NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, // ========================================================================= @@ -3093,66 +3093,66 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Base T32 prefix 0xEE/0xEC selects which coproc encoding family. Bit 16 // (A bit) distinguishes accumulator variants (CX1A from CX1, etc.). .CX1 = { - {.CX1, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1A = { - {.CX1A, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1A, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1D = { - {.CX1D, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1D, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1DA = { - {.CX1DA, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1DA, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2 = { - {.CX2, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2A = { - {.CX2A, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2A, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2D = { - {.CX2D, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2D, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2DA = { - {.CX2DA, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2DA, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CX3 has Rn and Rm inputs (Rm placed at bits 3:0 of low half) .CX3 = { - {.CX3, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3A = { - {.CX3A, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3A, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3D = { - {.CX3D, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3D, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3DA = { - {.CX3DA, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3DA, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCX variants -- VFP/FP-register destination using S or D form .VCX1 = { - {.VCX1, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX1, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX1, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX1, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX1A = { - {.VCX1A, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX1A, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX1A, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX1A, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX2 = { - {.VCX2, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX2, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX2, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX2, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX2A = { - {.VCX2A, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX2A, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX2A, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX2A, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX3 = { - {.VCX3, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX3, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX3, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX3, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX3A = { - {.VCX3A, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX3A, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX3A, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX3A, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -3171,296 +3171,296 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // where mask in bits 13-11 encodes then/else pattern + length // VPT (LLVM-verified): vpt.i8 eq, q2, q3 = 0xFE45_0F06 -> base 0xFE010F00 .VPT = { - {.VPT, {.MVE_VPT_MASK, .COND, .QPR, .QPR}, {.MVE_VPT_MASK_FIELD, .NONE, .VN_Q, .VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPT, {.MVE_VPT_MASK, .COND, .QPR, .QPR}, {.MVE_VPT_MASK_FIELD, .NONE, .VN_Q, .VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // VPST = 0xFE71_0F4D .VPST = { - {.VPST, {.MVE_VPT_MASK, .NONE, .NONE, .NONE}, {.MVE_VPT_MASK_FIELD, .NONE, .NONE, .NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPST, {.MVE_VPT_MASK, .NONE, .NONE, .NONE}, {.MVE_VPT_MASK_FIELD, .NONE, .NONE, .NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VPSEL (LLVM): vpsel q1, q2, q3 = 0xFE35_2F07 -> base 0xFE010F01 .VPSEL = { - {.VPSEL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPSEL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, // VPNOT = 0xFE31_0F4D .VPNOT = { - {.VPNOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPNOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCTP (LLVM): vctp.8 r3 = 0xF003_E801 -> base 0xF000E801 with Rn at bits 19:16 .VCTP = { - {.VCTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VCTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- MVE reductions (single Q -> GPR or pair) ----------------------------- // MVE reductions (LLVM-verified bases for size-00 .S8 forms). .VADDV = { // vaddv.s8 r0, q3 = 0xEEF1_0F06 -> base 0xEEF10F00 - {.VADDV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VADDVA = { // vaddva.s8 r0, q3 = 0xEEF1_0F26 -> base 0xEEF10F20 - {.VADDVA, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDVA, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VADDLV = { // vaddlv.s32 r0,r1,q3 = 0xEE89_0F06 -> base 0xEE890F00 (Rd=R0 at 11:8, Rn=R1 implicit pair) - {.VADDLV, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDLV, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VADDLVA = { - {.VADDLVA, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDLVA, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMAXV = { // vmaxv.s8 r0, q3 = 0xEEE2_0F06 -> base 0xEEE20F00 - {.VMAXV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMAXAV = { - {.VMAXAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMINV = { // vminv.s8 r0, q3 = 0xEEE2_0F86 -> base 0xEEE20F80 - {.VMINV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMINAV = { - {.VMINAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMAXNMV = { // vmaxnmv.f32 r0, q3 = 0xEEEE_0F06 -> base 0xEEEE0F00 - {.VMAXNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMAXNMAV = { - {.VMAXNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMINNMV = { // vminnmv.f32 r0, q3 = 0xEEEE_0F86 -> base 0xEEEE0F80 - {.VMINNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMINNMAV = { - {.VMINNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // ---- MVE dual MAC reductions (representative; full B/T/X variants encoded similarly) ---- // MVE MAC reductions (LLVM-verified for .S8 sizes; size bits in 21:20): // vabav.s8 r0, q2, q3 = 0xEE84_0F07 -> base 0xEE800F01 .VABAV = { - {.VABAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VABAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // vmlav.s8 r0,q2,q3 = 0xEEF4_0F06 -> base 0xEEB00F00 // vmladav.s8 = same encoding as vmlav (alias) .VMLAV = { - {.VMLAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLAVA = { - {.VMLAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAV = { - {.VMLADAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVA = { // vmladava.s8 = 0xEEF4_0F26 -> base 0xEEB00F20 - {.VMLADAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVX = { // vmladavx.s8 = 0xEEF4_1F06 -> base 0xEEB01F00 - {.VMLADAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVAX = { - {.VMLADAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAV = { // vmlsdav.s8 r0,q2,q3 = 0xFEF4_0E07 -> base 0xFEB00E01 - {.VMLSDAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVA = { - {.VMLSDAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVX = { - {.VMLSDAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVAX = { - {.VMLSDAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, // Long-version (64-bit pair RdaLo, RdaHi) // vmlaldav.s32 r0,r1,q2,q3 = 0xEE85_0E06 -> base 0xEE800E00 (with Qn at 19:17 expanded view) // Need to verify exact base after Rn at bits 11:8 + Rd at bits 15:12. .VMLALDAV = { - {.VMLALDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVA = { - {.VMLALDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVX = { - {.VMLALDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVAX = { - {.VMLALDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAV = { // vmlsldav.s32 r0,r1,q2,q3 = 0xEE85_0E07 -> base 0xEE800E01 - {.VMLSLDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVA = { - {.VMLSLDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVX = { // vmlsldavx.s32 = 0xEE85_1E07 -> base 0xEE801E01 - {.VMLSLDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVAX = { - {.VMLSLDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, // High-half rounding reductions: // vrmlaldavh.s32 r0,r1,q2,q3 = 0xEE84_0F06 -> base 0xEE800F00 // vrmlsldavh.s32 r0,r1,q2,q3 = 0xFE84_0E07 -> base 0xFE800E01 .VRMLALDAVH = { - {.VRMLALDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHA = { - {.VRMLALDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHX = { - {.VRMLALDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHAX = { - {.VRMLALDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVH = { - {.VRMLSLDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHA = { - {.VRMLSLDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHX = { - {.VRMLSLDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHAX = { - {.VRMLSLDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, // ---- MVE complex arithmetic ------------------------------------------------ .VCMUL = { - {.VCMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VHCADD = { - {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VHCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VHCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- MVE shifts (specialized) --------------------------------------------- .VSHLC = { // VSHLC Qd, Rdm, #imm5 -- vector shift left with carry from GPR - {.VSHLC, {.QPR, .GPR, .IMM5, .NONE}, {.VD_Q, .RM_T32, .A32_IMM_SHIFT, .NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLC, {.QPR, .GPR, .IMM5, .NONE}, {.VD_Q, .RM_T32, .A32_IMM_SHIFT, .NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBRSR = { // VBRSR Qd, Qn, Rm -- bit reverse with shift right - {.VBRSR, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VBRSR, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // ---- MVE counter init duplicates ------------------------------------------ .VDDUP = { - {.VDDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VIDUP = { - {.VIDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VIDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VDWDUP = { - {.VDWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VIWDUP = { - {.VIWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VIWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, // MVE narrow B/T (LLVM-verified for .S16 sizes; T-form bit 12 = 1): .VMOVNB = { // vmovnb.s16 q1, q3 = 0xFE31_2E87 -> base 0xFE310E81 - {.VMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I16, .NONE}}, }, .VMOVNT = { - {.VMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I16, .NONE}}, }, .VQMOVNB = { // vqmovnb.s16 q1, q3 = 0xEE33_2E07 -> base 0xEE330E01 - {.VQMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVNT = { - {.VQMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVUNB = { // vqmovunb.s16 q1, q3 = 0xEE31_2E87 -> base 0xEE310E81 - {.VQMOVUNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVUNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVUNT = { - {.VQMOVUNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVUNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, // MVE widening (long) B/T forms: .VSHLLB = { // vshllb.s8 q1, q3, #4 = 0xEEAC_2F46 -> base 0xEE800F40 (imm6 in 21:16, // includes the size-prefix 101sss for .S8) - {.VSHLLB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLLB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSHLLT = { - {.VSHLLT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLLT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMULLB = { // vmullb.s8 q1, q2, q3 = 0xEE05_2E06 -> base 0xEE000E00 - {.VMULLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMULLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMULLT = { - {.VMULLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMULLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VMLALB/T/VMLSLB/T: LLVM doesn't seem to support direct mnemonics in // its assembler; encodings derived heuristically from VMULL B/T pattern .VMLALB = { - {.VMLALB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLALT = { - {.VMLALT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLSLB = { - {.VMLSLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLSLT = { - {.VMLSLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Narrow shift B/T forms (LLVM-verified): // vshrnb.i16 q,q,#shift = 0xEE8F_2EC7 base 0xEE800EC1 (imm6 = 16-shift) // vshrnt.i16 = bit 12 = 1 .VSHRNB = { - {.VSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSHRNT = { - {.VSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VRSHRNB = { - {.VRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VRSHRNT = { - {.VRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRNB = { // vqshrnb.s16 q,q,#4 = 0xEE8C_2F46 -> base 0xEE800F40 - {.VQSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRNT = { - {.VQSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRNB = { // vqrshrnb.s16 q,q,#4 = 0xEE8C_2F47 -> base 0xEE800F41 - {.VQRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRNT = { - {.VQRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRUNB = { // vqshrunb.s16 q,q,#4 = 0xEE8C_2FC6 -> base 0xEE800FC0 - {.VQSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRUNT = { - {.VQSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRUNB = { // vqrshrunb.s16 q,q,#4 = 0xFE8C_2FC6 -> base 0xFE800FC0 - {.VQRSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRUNT = { - {.VQRSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- MVE Q-lane GPR move --------------------------------------------------- @@ -3471,28 +3471,28 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vqdmlsdh = top byte 0xFE (vs 0xEE) // vqrdmladh = bit 0 = 1 (vs 0) .VQDMLADH = { - {.VQDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLADHX = { - {.VQDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLSDH = { - {.VQDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLSDHX = { - {.VQDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLADH = { - {.VQRDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLADHX = { - {.VQRDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLSDH = { - {.VQRDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLSDHX = { - {.VQRDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- MVE load/store -------------------------------------------------------- @@ -3502,124 +3502,124 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vldrw.u32 q1, [r2] = 0xED92_3F00 -> base 0xED901F00 // vstrb.8 q1, [r2] = 0xED82_3E00 -> base 0xED801E00 .VLDRB = { - {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, + {.VLDRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VLDRH = { - {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U16, .NONE}}, + {.VLDRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U16, .NONE}}, }, .VLDRW = { - {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U32, .NONE}}, + {.VLDRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U32, .NONE}}, }, .VLDRD = { - {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VLDRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U64, .NONE}}, }, .VSTRB = { - {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, + {.VSTRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRH = { - {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ16, .NONE}}, + {.VSTRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRW = { - {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, + {.VSTRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRD = { - {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VSTRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Interleaved load/store -- 2-vector .VLD20 = { - {.VLD20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD21 = { - {.VLD21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD40 = { - {.VLD40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD41 = { - {.VLD41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD42 = { - {.VLD42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD43 = { - {.VLD43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST20 = { - {.VST20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST21 = { - {.VST21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST40 = { - {.VST40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST41 = { - {.VST41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST42 = { - {.VST42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST43 = { - {.VST43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, // Unprivileged (translate) post-indexed loads/stores: the post-index form // with the W bit (21) set. Word/byte use imm12, half/signed use imm8 split. - .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}} }, - .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}} }, - .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}} }, - .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}} }, - .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}} }, - .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}} }, - .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}} }, - .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}} }, + .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, // NEON rounding shift-right-accumulate (imm); FP reciprocal/rsqrt estimate; // FP pairwise add; VFP convert-to-integer using the FPSCR rounding mode. .VRSRA = { - {.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VRECPE_F = { - {.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VRSQRTE_F = { - {.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VPADD_F = { - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, .VCVTR = { - {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}}, + {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}}, + {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F64}}, + {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F64}}, }, // Debug change PE state (T32, fixed encoding, no operands). - .DCPS1 = { {.DCPS1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, - .DCPS2 = { {.DCPS2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, - .DCPS3 = { {.DCPS3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, + .DCPS1 = { {.DCPS1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .DCPS2 = { {.DCPS2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .DCPS3 = { {.DCPS3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, // NEON (saturating) doubling multiply-high by scalar Dm[lane]: // .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5. // VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on // the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size. .VMOV_LANE = { - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, }, // MVE (M-profile vector) multiply-subtract-across-vector reduce, halving @@ -3629,123 +3629,123 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // mask (the MVE convention); the complex ops encode the rotation immediate. // MVE multiply-subtract reduce (Rd at 15:12, Qn at 19:17, Qm at 3:1 -- the // proper 3-bit MVE Q fields, .s16 form). VMLSVA accumulates (bit 5). - .VMLSV = { {.VMLSV, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, - .VMLSVA = { {.VMLSVA, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, + .VMLSV = { {.VMLSV, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .VMLSVA = { {.VMLSVA, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}} }, // SPECGEN:BEGIN .VADDL = { - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VSUBL = { - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VABAL = { - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VABDL = { - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VADDW = { - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VSUBW = { - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VCLE = { - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { - {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VACLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLT = { - {.VACLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VACLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VACLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VQRSHL = { - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, // SPECGEN:END } diff --git a/core/rexcode/isa/arm32/tablegen/gen.odin b/core/rexcode/isa/arm32/tablegen/gen.odin index 8558edcee..617d4a749 100644 --- a/core/rexcode/isa/arm32/tablegen/gen.odin +++ b/core/rexcode/isa/arm32/tablegen/gen.odin @@ -65,6 +65,7 @@ Entry :: struct { feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags, + dt: lib.Data_Types, is_thumb32: bool, key: u16, // primary dispatch key (8 bits A32, 7 bits T32, 6 bits T16) ilen: u8, @@ -101,7 +102,7 @@ emit_encode_tables :: proc() -> (total: int) { if len(forms) == 0 { continue } fmt.sbprintfln(&sb, "\t// .%v", m) for f in forms { - write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags) + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags, f.dt) } } strings.write_string(&sb, "}\n\n") @@ -170,6 +171,7 @@ emit_decode_tables :: proc() -> (total: int) { feature = f.feature, mode = f.mode, flags = f.flags, + dt = f.dt, is_thumb32 = f.flags.thumb32, ilen = ilen, form_idx = u16(fi), @@ -301,7 +303,7 @@ emit_decode_tables :: proc() -> (total: int) { strings.write_string(&sb, "@(rodata)\n") fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) for e in all { - write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags) + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags, e.dt) } strings.write_string(&sb, "}\n\n") @@ -351,10 +353,11 @@ emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, enc: [4]lib.Operand_Encoding, bits, mask: u32, - feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags) { - fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},\n", + feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags, + dt: lib.Data_Types) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}}, {{.%v,.%v}} }},\n", mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], - bits, mask, feature, mode, flags_lit(flags)) + bits, mask, feature, mode, flags_lit(flags), dt[0], dt[1]) } flags_lit :: proc(f: lib.Encoding_Flags) -> string { @@ -412,8 +415,9 @@ Decode_Entry :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 -- see Data_Type in encoding_types.odin } -#assert(size_of(Decode_Entry) == 21) +#assert(size_of(Decode_Entry) == 23) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index c2a2a77e5..73edb4aa0 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -9,1686 +9,1686 @@ import lib "../.." @(rodata) DECODE_ENTRIES := [1680]lib.Decode_Entry{ - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, 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0x00005200, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {}, {.NONE,.NONE} }, + { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, } @(rodata) diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index f41e57c92..7a423c5d2 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -10,2275 +10,2275 @@ import lib "../.." @(rodata) ENCODE_FORMS := [1680]lib.Encoding{ // .AND - { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, + { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .EOR - { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {} }, - { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SUB - { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {} }, - { .SUB, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {} }, - { .SUB, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {} }, - { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {} }, + { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, // .RSB - { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ADD - { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {} }, - { .ADD, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {} }, - { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {} }, + { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, // .ADC - { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {} }, - { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SBC - { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {} }, - { .SBC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RSC - { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, + { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, // .TST - { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {} }, - { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {} }, - { .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {} }, - { .TST, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {} }, - { .TST, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TEQ - { .TEQ, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {} }, - { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {} }, - { .TEQ, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {} }, - { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .TEQ, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CMP - { .CMP, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {} }, - { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {} }, - { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {} }, - { .CMP, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {} }, - { .CMP, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {} }, - { .CMP, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {} }, - { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .CMP, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CMN - { .CMN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {} }, - { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {} }, - { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {} }, - { .CMN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .CMN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ORR - { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {} }, - { .ORR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MOV - { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {} }, - { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {} }, - { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {} }, - { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, + { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .BIC - { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {} }, - { .BIC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MVN - { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {} }, - { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {} }, - { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true} }, + { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSL - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {} }, - { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {} }, - { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSR - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {} }, - { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {} }, - { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ASR - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {} }, - { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {} }, - { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ROR - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {} }, - { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RRX - { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {} }, + { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} }, // .ADR - { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {} }, + { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, // .NEG - { .NEG, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {} }, + { .NEG, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, // .MOVW - { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {} }, - { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true} }, + { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MOVT - { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {} }, - { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true} }, + { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BFC - { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {} }, - { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true} }, + { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BFI - { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {} }, - { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SBFX - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {} }, - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UBFX - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {} }, - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTB - { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {} }, - { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTB16 - { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTH - { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {} }, - { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTB - { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {} }, - { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTB16 - { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTH - { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {} }, - { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAB - { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAB16 - { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAH - { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAB - { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAB16 - { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAH - { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CLZ - { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {} }, - { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {.NONE,.NONE} }, + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RBIT - { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {} }, - { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REV - { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {} }, - { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {} }, - { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REV16 - { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {} }, - { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {} }, - { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REVSH - { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {} }, - { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {} }, - { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEL - { .SEL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {} }, + { .SEL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, // .PKHBT - { .PKHBT, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {} }, + { .PKHBT, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, // .PKHTB - { .PKHTB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {} }, + { .PKHTB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, // .USAD8 - { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .USADA8 - { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {} }, + { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SSAT - { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {} }, - { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true} }, + { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {} }, - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSAT16 - { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT16 - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {} }, - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD - { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB - { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QDADD - { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QDSUB - { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SADD8 - { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {} }, - { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SADD16 - { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {} }, - { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SASX - { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSAX - { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {} }, - { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSUB8 - { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSUB16 - { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {} }, - { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UADD8 - { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UADD16 - { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UASX - { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAX - { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {} }, - { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USUB8 - { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USUB16 - { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {} }, - { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD8 - { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {} }, - { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD16 - { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {} }, - { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QASX - { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {} }, - { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSAX - { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {} }, - { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB8 - { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB16 - { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {} }, - { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQADD8 - { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQADD16 - { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQASX - { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSAX - { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSUB8 - { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSUB16 - { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHADD8 - { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {} }, - { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHADD16 - { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {} }, - { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHASX - { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSAX - { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSUB8 - { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSUB16 - { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHADD8 - { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHADD16 - { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHASX - { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSAX - { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSUB8 - { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSUB16 - { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMUAD - { .SMUAD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUAD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUADX - { .SMUADX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUADX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUSD - { .SMUSD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUSD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUSDX - { .SMUSDX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUSDX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLAD - { .SMLAD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {} }, + { .SMLAD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLADX - { .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {} }, + { .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSD - { .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSDX - { .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLALD - { .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {} }, + { .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLALDX - { .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {} }, + { .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSLD - { .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSLDX - { .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMUL - { .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMULR - { .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLA - { .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLAR - { .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLS - { .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLSR - { .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .MUL - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .MUL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MUL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MLA - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MLS - { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {} }, - { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMULL - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {} }, - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMLAL - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {} }, - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMULL - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {} }, - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMLAL - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {} }, - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMAAL - { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {} }, + { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLABB - { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLABT - { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLATB - { .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLATT - { .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLAWB - { .SMLAWB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLAWB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLAWT - { .SMLAWT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLAWT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULBB - { .SMULBB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULBB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULBT - { .SMULBT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULBT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULTB - { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULTT - { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULWB - { .SMULWB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULWB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULWT - { .SMULWT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULWT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALBB - { .SMLALBB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALBB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALBT - { .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALTB - { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALTT - { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SDIV - { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {} }, - { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true} }, + { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, + { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UDIV - { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {} }, - { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true} }, + { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, + { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, // .B - { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, - { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true} }, - { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true} }, - { .B, {.REL20,.COND,.NONE,.NONE}, {.BRANCH_20_T32,.NONE,.NONE,.NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true} }, - { .B, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL20,.COND,.NONE,.NONE}, {.BRANCH_20_T32,.NONE,.NONE,.NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, + { .B, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .BL - { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, - { .BL, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BL, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .BX - { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true} }, - { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true} }, + { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, // .BLX - { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true} }, - { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true} }, - { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true} }, + { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, // .BXJ - { .BXJ, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true} }, + { .BXJ, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}, {.NONE,.NONE} }, // .CBZ - { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true} }, + { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, // .CBNZ - { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true} }, + { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, // .TBB - { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .TBH - { .TBH, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .TBH, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .MSR - { .MSR, {.PSR_FIELD,.IMM_MOD,.NONE,.NONE}, {.PSR_FIELD_MASK,.A32_IMM_MOD,.NONE,.NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {} }, - { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {} }, - { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true} }, + { .MSR, {.PSR_FIELD,.IMM_MOD,.NONE,.NONE}, {.PSR_FIELD_MASK,.A32_IMM_MOD,.NONE,.NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MRS - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {} }, - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CPS - { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {} }, + { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, // .SETEND - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, // .NOP - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {} }, - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {} }, - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .YIELD - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {} }, - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {} }, - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WFE - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {} }, - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {} }, - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WFI - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {} }, - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {} }, - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEV - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {} }, - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {} }, - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEVL - { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {} }, + { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, // .DBG - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .HINT - { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {} }, + { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, // .DMB - { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {} }, - { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DSB - { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {} }, - { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ISB - { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {} }, - { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CLREX - { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {} }, - { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true} }, + { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLD - { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {} }, - { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true} }, + { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {}, {.NONE,.NONE} }, + { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLDW - { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {} }, - { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true} }, + { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLI - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {} }, - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .HLT - { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {} }, + { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} }, // .DCPS1 - { .DCPS1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DCPS2 - { .DCPS2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DCPS3 - { .DCPS3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ERET - { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true} }, + { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {.NONE,.NONE} }, // .ESB - { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {} }, - { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PSB_CSYNC - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {} }, - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TSB_CSYNC - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {} }, - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CSDB - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {} }, - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SB - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {} }, - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SETPAN - { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {} }, - { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {}, {.NONE,.NONE} }, // .SVC - { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {} }, - { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, // .BKPT - { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {} }, - { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {}, {.NONE,.NONE} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {}, {.NONE,.NONE} }, // .HVC - { .HVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {} }, + { .HVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {}, {.NONE,.NONE} }, // .SMC - { .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {} }, + { .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .UDF - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {} }, - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {} }, - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDR - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STR - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRB - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {} }, - { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {} }, - { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRB - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {} }, - { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {} }, - { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, 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.T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRT - { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {} }, + { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRT - { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {} }, + { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRBT - { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {} }, + { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRBT - { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {} }, + { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRHT - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRHT - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSBT - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSHT - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDA - { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STL - { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAB - { .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLB - { .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAH - { .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLH - { .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDREX - { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true} }, + { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREX - { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, + { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXB - { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true} }, + { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXB - { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true} }, + { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXH - { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true} }, + { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXH - { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true} }, + { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXD - { .LDREXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true} }, + { .LDREXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXD - { .STREXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXD, {.GPR,.GPR,.GPR,.MEM}, {.RD_T32,.RT_T32,.RT2_T32,.RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .STREXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXD, {.GPR,.GPR,.GPR,.MEM}, {.RD_T32,.RT_T32,.RT2_T32,.RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDAEX - { .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEX - { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXB - { .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXB - { .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXH - { .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXH - { .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXD - { .LDAEXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXD - { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDM - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STM - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PUSH - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {} }, - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {} }, - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .POP - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {} }, - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {} }, - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SWP - { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true} }, + { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .SWPB - { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true} }, + { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .RFE - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {} }, + { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, // .SRS - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {} }, + { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, // .CDP - { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {} }, + { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, // .CDP2 - { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {} }, + { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MCR - { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {} }, + { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, // .MCR2 - { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {} }, + { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MRC - { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {} }, + { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, // .MRC2 - { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {} }, + { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MCRR - { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {} }, + { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MCRR2 - { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {} }, + { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MRRC - { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {} }, + { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MRRC2 - { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {} }, + { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .LDC - { .LDC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {} }, + { .LDC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDC2 - { .LDC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {} }, + { .LDC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {}, {.NONE,.NONE} }, // .STC - { .STC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {} }, + { .STC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STC2 - { .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {} }, + { .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {}, {.NONE,.NONE} }, // .CRC32B - { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32H - { .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32W - { .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CB - { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CH - { .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CW - { .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .VADD - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VADD, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {}, {.I64,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {}, {.I64,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VSUB - { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VSUB, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {}, {.I64,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {}, {.I64,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VMUL - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV - { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VMLA - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL - { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VNMLA - { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VNMLS - { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VFMA - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMS - { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {} }, - { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {} }, - { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, // .VFNMA - { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VFNMS - { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VABS - { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true} }, + { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VNEG - { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true} }, + { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VSQRT - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VCMP - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {} }, - { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true} }, - { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VCMPE - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VCVT - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, + { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, // .VCVTB - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, // .VCVTT - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, // .VCVTA - { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTN - { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTP - { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTM - { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTR - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, // .VMOV - { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {} }, - { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {} }, - { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {} }, - { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMRS - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {} }, + { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {} }, + { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDR - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSTR - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDM - { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {} }, - { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSTM - { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {} }, - { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VPUSH - { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, - { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VPOP - { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, - { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSEL - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {} }, + { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, // .VMAXNM - { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {} }, - { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {} }, + { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, // .VMINNM - { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {} }, - { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {} }, + { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, // .VRINTA - { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTN - { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTP - { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTM - { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTM, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTM, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTR - { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {} }, + { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, // .VRINTZ - { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTX - { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTX, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTX, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VADDL - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VADDW - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VSUBL - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VSUBW - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VHADD - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VHSUB - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VRHADD - { .VRHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {} }, - { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {} }, - { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQADD - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSUB - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMULL - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLAL - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLSL - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VQDMULL - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLAL - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLSL - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMULH - { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQRDMULH - { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQRDMLAH - { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VQRDMLSH - { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VABA - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, // .VABAL - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VABD - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VABDL - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VAND - { .VAND, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {} }, - { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {} }, - { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VAND, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBIC - { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {} }, - { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORR - { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {} }, - { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {} }, - { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORN - { .VORN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {} }, - { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {} }, - { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VORN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VEOR - { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {} }, - { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {} }, - { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBSL - { .VBSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VBIT - { .VBIT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBIT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VBIF - { .VBIF, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIF, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBIF, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIF, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VMVN - { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMOVN - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, // .VQMOVN - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, // .VQMOVUN - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, // .VMOVL - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {}, {.U32,.NONE} }, // .VTST - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VCEQ - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE - { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, - { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {} }, + { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGT - { .VACGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {} }, - { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {} }, + { .VACGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VACLE - { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {} }, - { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {} }, + { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, // .VACLT - { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {} }, - { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {} }, + { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, // .VMAX - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMIN - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VPMAX - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPMIN - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPADD - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPADDL - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VPADAL - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VRECPE - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRECPS - { .VRECPS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {} }, - { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {} }, + { .VRECPS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTE - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTS - { .VRSQRTS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {} }, + { .VRSQRTS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VSHL - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VSHR - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VSRA - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSHL - { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {} }, - { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VRSHR - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSRA - { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {} }, - { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {} }, + { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSLI - { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {} }, - { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {} }, + { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSRI - { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {} }, - { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {} }, + { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VQSHL - { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSHRN - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQSHRUN - { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {} }, + { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHL - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {}, {.U64,.NONE} }, // .VQRSHRN - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHRUN - { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {} }, + { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHRN - { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {} }, + { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VRSHRN - { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {} }, + { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCLS - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, // .VCLZ - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCNT - { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VPADD_F - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, + { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, // .VRECPE_F - { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTE_F - { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VREV16 - { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VREV32 - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, // .VREV64 - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VEXT - { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {} }, - { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {} }, + { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, // .VTBL - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTBX - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VUZP - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VZIP - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VDUP - { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true} }, + { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, // .VSWP - { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, // .VMOV_LANE - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VLD1 - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2 - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD3 - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4 - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST1 - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2 - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST3 - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST4 - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .AESE - { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESD - { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESMC - { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESIMC - { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1H - { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1SU0 - { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1SU1 - { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1C - { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1M - { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1P - { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256H - { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256H2 - { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256SU0 - { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256SU1 - { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .VJCVT - { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {} }, + { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, // .VSDOT - { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, + { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, // .VUDOT - { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, + { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, // .VDOT - { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, - { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, + { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {}, {.BF16,.NONE} }, + { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VMMLA - { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, + { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMAL - { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {} }, - { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {} }, + { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, // .VFMSL - { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {} }, - { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {} }, + { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, // .VCMLA - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VCADD - { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, - { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, + { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, // .VSMMLA - { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {} }, + { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VUMMLA - { .VUMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {} }, + { .VUMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSMMLA - { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {} }, + { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VSUDOT - { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, + { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSDOT - { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {} }, - { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, + { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VQABS - { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQNEG - { .VQNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMOVX - { .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, + { .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VINS - { .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, + { .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VLD2R - { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD3R - { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4R - { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD1_LANE - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2_LANE - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD3_LANE - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD4_LANE - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST1_LANE - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2_LANE - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST3_LANE - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST4_LANE - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .IT - { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {} }, + { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, // .TT - { .TT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTT - { .TTT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTA - { .TTA, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTA, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTAT - { .TTAT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTAT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SG - { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true} }, + { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BXNS - { .BXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {branch=true} }, + { .BXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {branch=true}, {.NONE,.NONE} }, // .BLXNS - { .BLXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {branch=true} }, + { .BLXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {branch=true}, {.NONE,.NONE} }, // .PAC - { .PAC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .PAC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PACBTI - { .PACBTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .PACBTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .AUT - { .AUT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .AUT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .AUTG - { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true} }, + { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BTI - { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WLS - { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .WLSTP - { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .DLS - { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} }, + { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DLSTP - { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} }, + { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .LE - { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .LETP - { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .LCTP - { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BF - { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFX - { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFL - { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .BFLX - { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFCSEL - { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .CX1 - { .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1A - { .CX1A, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1A, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1D - { .CX1D, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1D, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1DA - { .CX1DA, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1DA, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2 - { .CX2, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2A - { .CX2A, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2A, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2D - { .CX2D, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2D, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2DA - { .CX2DA, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2DA, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3 - { .CX3, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3A - { .CX3A, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3A, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3D - { .CX3D, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3D, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3DA - { .CX3DA, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3DA, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX1 - { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX1A - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX2 - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX2A - { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX3 - { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX3A - { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VPT - { .VPT, {.MVE_VPT_MASK,.COND,.QPR,.QPR}, {.MVE_VPT_MASK_FIELD,.NONE,.VN_Q,.VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VPT, {.MVE_VPT_MASK,.COND,.QPR,.QPR}, {.MVE_VPT_MASK_FIELD,.NONE,.VN_Q,.VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VPST - { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VPSEL - { .VPSEL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VPSEL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VPNOT - { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCTP - { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VADDV - { .VADDV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VADDVA - { .VADDVA, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDVA, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VADDLV - { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VADDLVA - { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMAXV - { .VMAXV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMAXV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMAXAV - { .VMAXAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMAXAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMINV - { .VMINV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMINV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMINAV - { .VMINAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMINAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMAXNMV - { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMAXNMAV - { .VMAXNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMAXNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMINNMV - { .VMINNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMINNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMINNMAV - { .VMINNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMINNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VABAV - { .VABAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VABAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMLADAV - { .VMLADAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVA - { .VMLADAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVX - { .VMLADAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVAX - { .VMLADAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLALDAV - { .VMLALDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVA - { .VMLALDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVX - { .VMLALDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVAX - { .VMLALDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSDAV - { .VMLSDAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVA - { .VMLSDAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVX - { .VMLSDAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVAX - { .VMLSDAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSLDAV - { .VMLSLDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVA - { .VMLSLDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVX - { .VMLSLDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVAX - { .VMLSLDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VRMLALDAVH - { .VRMLALDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHA - { .VRMLALDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHX - { .VRMLALDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHAX - { .VRMLALDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVH - { .VRMLSLDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHA - { .VRMLSLDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHX - { .VRMLSLDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHAX - { .VRMLSLDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLAV - { .VMLAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLAVA - { .VMLAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSV - { .VMLSV, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSV, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSVA - { .VMLSVA, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSVA, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCMUL - { .VCMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, + { .VCMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VHCADD - { .VHCADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, - { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VHCADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VBRSR - { .VBRSR, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true} }, + { .VBRSR, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VSHLC - { .VSHLC, {.QPR,.GPR,.IMM5,.NONE}, {.VD_Q,.RM_T32,.A32_IMM_SHIFT,.NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLC, {.QPR,.GPR,.IMM5,.NONE}, {.VD_Q,.RM_T32,.A32_IMM_SHIFT,.NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VDDUP - { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, + { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VIDUP - { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, + { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VDWDUP - { .VDWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true} }, + { .VDWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VIWDUP - { .VIWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true} }, + { .VIWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VMOVNB - { .VMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.I16,.NONE} }, // .VMOVNT - { .VMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.I16,.NONE} }, // .VQMOVNB - { .VQMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVNT - { .VQMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVUNB - { .VQMOVUNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVUNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVUNT - { .VQMOVUNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVUNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VSHLLB - { .VSHLLB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLLB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHLLT - { .VSHLLT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLLT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMULLB - { .VMULLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMULLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMULLT - { .VMULLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMULLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMLALB - { .VMLALB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLALT - { .VMLALT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSLB - { .VMLSLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSLT - { .VMLSLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHRNB - { .VSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHRNT - { .VSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VRSHRNB - { .VRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VRSHRNT - { .VRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRNB - { .VQSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRNT - { .VQSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRNB - { .VQRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRNT - { .VQRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRUNB - { .VQSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRUNT - { .VQSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRUNB - { .VQRSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRUNT - { .VQRSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQDMLADH - { .VQDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLADHX - { .VQDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLSDH - { .VQDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLSDHX - { .VQDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLADH - { .VQRDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLADHX - { .VQRDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLSDH - { .VQRDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLSDHX - { .VQRDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VLDRB - { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, + { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VLDRH - { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.U16,.NONE} }, + { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U16,.NONE} }, // .VLDRW - { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, + { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, // .VLDRD - { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, // .VSTRB - { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, + { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRH - { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.SZ16,.NONE} }, + { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRW - { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRD - { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VLD20 - { .VLD20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD21 - { .VLD21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD40 - { .VLD40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD41 - { .VLD41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD42 - { .VLD42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD43 - { .VLD43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST20 - { .VST20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST21 - { .VST21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST40 - { .VST40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST41 - { .VST41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST42 - { .VST42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST43 - { .VST43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, } ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ diff --git a/core/rexcode/isa/arm32/tables.odin b/core/rexcode/isa/arm32/tables.odin index 0798b0603..d9731578d 100644 --- a/core/rexcode/isa/arm32/tables.odin +++ b/core/rexcode/isa/arm32/tables.odin @@ -32,8 +32,9 @@ Decode_Entry :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 -- see Data_Type in encoding_types.odin } -#assert(size_of(Decode_Entry) == 21) +#assert(size_of(Decode_Entry) == 23) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 42514bf8aa7103e1edace4dc7526510dfe45683d..5c773096eb36f4169fd05055c33201d9b43e4f4d 100644 GIT binary patch literal 38640 zcmZ{t37lkAb;i%D>guJcyIu|54T3OJqreQqRtT=3Jj7j*!hMAyDyWIlYK%*aJk&%@ zG*otzxU`zZtTwLfQ)V@*P4-nAvxtgA4TBLCy7QfT-#zDhLp#4;EByK9yJxxYzWbJ{ z&LqorNTYeQ;7>zjBiDbB47de675=Tqcsk%7{=r&0+Xz6(vu$JWYU9)si!d7 zj-y~)h>W-J_u&yDIZ8V7$Kao3BIU;SXR>}B_bR+Q4cVDrQ1v&U-ZFIyCW?C%hPpw? z_dR*VDfvF)u4^-;k7iQBd-#PRW;^eDsd#l%8di(kVP0 z#VMV_(@~t#DLfrE8G1TwGW2xVWa#NMkgk6UqyyY#pfr?^Xxn@vU@H=B$+ZZ;Wt+%50UgHYYn9mQ35j<4g?odIy_ zj(VeM%Ro=SPwEa#(6!LZPt?^_FNJ$KO*L8dnkY^+S@oJIPBmHeny|^5*Mv>hye4e2 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0d614419e01859855adc43781d86fa8d053334a6 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 00:40:20 -0400 Subject: [PATCH 12/89] rexcode: arm32 88 -> 48 bytes, arm64 64 -> 48 x86 keeps Instruction at 64 bytes -- one cache line -- by packing its memory operand into a bit_field u64 rather than a struct. arm32 and arm64 both used a 12-byte Memory struct, and since Memory sits in every Operand that width is multiplied by four in every Instruction. Adopting x86's trick, plus two smaller things, takes both ARM ISAs under the cache line. Instruction ops[4] Operand Memory x86 64 48 12 8 arm32 88 -> 48 72->40 18->10 12->8 arm64 64 -> 48 56->40 14->10 12->8 Memory -> bit_field u64, both ISAs. Field syntax and composite literals are unchanged, so callers see nothing. Registers keep their type: an arm64 Register never exceeds 0x0C1F and an arm32 one never exceeds 0x401F, but the arm64 NONE sentinel is 0xFFFF, so arm64 gives them the full 16 bits and arm32 15. What is left goes to `disp`: 23 bits on arm64 (worst case 65,520, from LDR Q, [Xn, #imm12*16]) and 19 on arm32 (worst case 4,095, an A32 imm12) -- 64x and 32x headroom respectively. arm32 Operand also carried four tail bytes arm64 does not. `cond` was dead: nine builders wrote it and nothing in the package ever read it, and Instruction.cond already exists. shift_type/shift_amt/lane now ride inside the union alongside the register they describe -- they only ever apply to a register operand -- via a `using` bit_field, so op.reg, op.shift_type, op.shift_amt and op.lane still read and write exactly as before. arm32 Instruction packs cond, operand_count, mode, length and the two flag bits into one 16-bit word; they need 13 bits between them and were spending six bytes. `using` again keeps the field names, with the one exception that inst.flags.sets_flags is now inst.sets_flags (five call sites). Verified: every rexcode suite matches baseline; both generators stay idempotent; arm64 is 73/73 byte-exact against llvm-mc on both encode and decode round-trip; arm32's 1680/1680 sweep still passes and a memory/shift encode spot-check is byte-identical to what the same code produced before this commit. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/decoder.odin | 4 +- core/rexcode/isa/arm32/encoder.odin | 6 +-- core/rexcode/isa/arm32/instructions.odin | 37 ++++++++------ core/rexcode/isa/arm32/operands.odin | 64 +++++++++++++++--------- core/rexcode/isa/arm32/printer.odin | 2 +- core/rexcode/isa/arm64/instructions.odin | 2 +- core/rexcode/isa/arm64/operands.odin | 39 +++++++++------ 7 files changed, 92 insertions(+), 62 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 3347c3cf7..847beae09 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -163,7 +163,7 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in inst.cond = 14 // AL / unconditional } if e.flags.sets_flags { - inst.flags.sets_flags = true + inst.sets_flags = true } for _, k in e.enc { @@ -254,7 +254,7 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op st := Shift_Type(u8(st_bits) + u8(Shift_Type.LSL_REG)) rs := u8((word >> 8) & 0xF) return Operand{reg = reg, kind = .REGISTER, size = 4, - shift_type = st, shift_amt = rs, cond = 14} + shift_type = st, shift_amt = rs} case .GPR_SHIFTED: // Imm-shift: amount in bits 11..7, type in 6..5, bit 4 = 0. st := Shift_Type((word >> 5) & 0x3) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 80a699c8a..ec3f358a0 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -163,7 +163,7 @@ encode_one_inline :: #force_inline proc( (inst.dt[0] == .NONE || f.dt == inst.dt) && (want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) && encoding_matches_inline(inst, f) && - inst.flags.sets_flags == f.flags.sets_flags && + inst.sets_flags == f.flags.sets_flags && mem_mode_matches(inst, f) { form = f } @@ -178,8 +178,8 @@ encode_one_inline :: #force_inline proc( if inst.dt[0] != .NONE && f.dt != inst.dt { continue } if want_len > 0 && inst_size_from_bits(f.bits, f.mode) != want_len { continue } if !encoding_matches_inline(inst, &f) { continue } - if inst.flags.sets_flags && !f.flags.sets_flags { continue } - if !inst.flags.sets_flags && f.flags.sets_flags { continue } + if inst.sets_flags && !f.flags.sets_flags { continue } + if !inst.sets_flags && f.flags.sets_flags { continue } if !mem_mode_matches(inst, &f) { continue } form = &f break diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 192513a70..6261f977a 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -21,29 +21,36 @@ Instruction_Flags :: bit_field u8 { } Instruction :: struct #packed { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 18 = 68 + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 10 = 40 mnemonic: Mnemonic, // 2 - cond: u8, // 0..15 (AL=14) - operand_count: u8, // 0..4 - flags: Instruction_Flags, // 1 - mode: Mode, // 1 (A32 or T32) - length: u8, // 2 or 4 bytes + // cond, operand_count, mode, length and the two flag bits share one + // 16-bit word -- together they need 13 bits, and spending six bytes on + // them was what pushed Instruction over 48. `using` keeps inst.cond, + // inst.operand_count, inst.mode, inst.length, inst.sets_flags and + // inst.wide reading and writing exactly as they did as plain fields. + using _: bit_field u16 { + cond: u8 | 4, // 0..15 (AL = 14) + operand_count: u8 | 3, // 0..4 + mode: Mode | 1, // A32 / T32 + length: u8 | 3, // 2 or 4 bytes on the wire + sets_flags: bool | 1, // S bit (writes APSR.NZCV) + wide: bool | 1, // force the T32 wide form when both exist + // 3 bits spare + }, // Form-id hint: when non-zero, this is (1 + the index into // ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder - // uses it as a tie-breaker for shape-ambiguous entries (NEON size variants - // share an operand shape but live in distinct entries with different fixed - // bits). User-constructed instructions leave it at 0; the encoder then - // falls back to first-shape-match. Stored as u16 over the two padding bytes. + // uses it as a tie-breaker for the shape-ambiguous entries the data type + // does not separate on its own -- register lists, LDM/STM addressing + // modes. User-constructed instructions leave it at 0 and take the + // first shape match. form_id: u16, // The `.i32` / `.s32.f32` suffix. Zero (.NONE) means "unspecified": the // encoder then takes the first form of the matching shape, which is what // every instruction did before this field existed. Set it and the encoder - // picks the encoding for that type. Fits in what was already padding, so - // Instruction does not grow. + // picks the encoding for that type. dt: Data_Types, - _: [5]u8, } -#assert(size_of(Instruction) == 88) +#assert(size_of(Instruction) == 48) // ============================================================================= // Builders @@ -141,6 +148,6 @@ inst_set_cond :: #force_inline proc "contextless" (inst: Instruction, cond: u8) @(require_results) inst_set_flags :: #force_inline proc "contextless" (inst: Instruction) -> Instruction { out := inst - out.flags.sets_flags = true + out.sets_flags = true return out } diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 1442183ff..2ce1f2d44 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -57,16 +57,25 @@ Index_Mode :: enum u8 { POST_INDEX = 2, // [Rn], #imm -- writeback, base = Rn pre-update } -Memory :: struct #packed { - base: Register, // GPR base register - index: Register, // GPR or .NONE for imm-only forms - shift_type: Shift_Type, - shift_amt: u8, // 0..31 immediate shift - mode: Index_Mode, - sign: i8, // +1 or -1 (U bit) - disp: i32, // immediate displacement (sign-extended) +// Packed into one word: this sits in every Operand, so its width is +// multiplied by four in every Instruction. Field syntax and composite +// literals are unchanged, so this is invisible to callers. +// +// A Register's raw value never exceeds REG_QPR|31 = 0x401F, so 15 bits hold +// one losslessly (index uses Register(0), not a high sentinel, for "absent"). +// `disp` gets 19 bits (+/-262,143) against a worst case of 4,095 -- the imm12 +// of an A32 load -- so there is ~64x headroom. +Memory :: bit_field u64 { + base: Register | 15, // GPR base register + index: Register | 15, // GPR, or Register(0) for imm-only forms + shift_type: Shift_Type | 4, + shift_amt: u8 | 5, // 0..31 immediate shift + mode: Index_Mode | 2, + sign: i8 | 3, // +1 or -1 (U bit) + disp: i32 | 19, // immediate displacement (sign-extended) + // 1 bit spare } -#assert(size_of(Memory) == 12) +#assert(size_of(Memory) == 8) @(require_results) mem_imm :: #force_inline proc "contextless" (base: Register, disp: i32) -> Memory { @@ -95,57 +104,64 @@ mem_reg_shift :: #force_inline proc "contextless" ( Operand :: struct #packed { using _: struct #raw_union #packed { - reg: Register, + // A register operand's shift and lane ride WITH the register instead + // of in the tail -- that is what keeps Operand at 10 bytes, and they + // only ever apply to a register anyway. `using` means op.reg, + // op.shift_type, op.shift_amt and op.lane still read and write + // exactly as they did when these were separate fields. + using _: bit_field u32 { + reg: Register | 15, + shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain + shift_amt: u8 | 5, // 0..31, or the Rs index for RSR + lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM + // 3 bits spare + }, mem: Memory, immediate: i64, relative: i64, // label id (pre) or signed byte offset (post) }, kind: Operand_Kind, size: u8, - shift_type: Shift_Type, // for GPR_SHIFTED operands (otherwise NONE) - shift_amt: u8, // immediate shift amount 0..31 (or Rs index for RSR) - lane: u8, // SIMD lane index for DPR_ELEM / QPR_ELEM - cond: u8, // condition code 0..15 (default = AL = 14) } -#assert(size_of(Operand) == 18) +#assert(size_of(Operand) == 10) // ---- Operand builders ------------------------------------------------------ @(require_results) op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { - return Operand{reg = r, kind = .REGISTER, size = 4, cond = 14} + return Operand{reg = r, kind = .REGISTER, size = 4} } @(require_results) op_reg_shifted :: #force_inline proc "contextless" ( r: Register, st: Shift_Type, amt: u8, ) -> Operand { - return Operand{reg = r, kind = .REGISTER, size = 4, shift_type = st, shift_amt = amt, cond = 14} + return Operand{reg = r, kind = .REGISTER, size = 4, shift_type = st, shift_amt = amt} } @(require_results) op_imm :: #force_inline proc "contextless" (v: i64, size: u8 = 4) -> Operand { - return Operand{immediate = v, kind = .IMMEDIATE, size = size, cond = 14} + return Operand{immediate = v, kind = .IMMEDIATE, size = size} } @(require_results) op_mem :: #force_inline proc "contextless" (m: Memory) -> Operand { - return Operand{mem = m, kind = .MEMORY, size = 4, cond = 14} + return Operand{mem = m, kind = .MEMORY, size = 4} } @(require_results) op_label :: #force_inline proc "contextless" (label_id: u32, size: u8 = 4) -> Operand { - return Operand{relative = i64(label_id), kind = .RELATIVE, size = size, cond = 14} + return Operand{relative = i64(label_id), kind = .RELATIVE, size = size} } @(require_results) op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand { - return Operand{relative = off, kind = .RELATIVE, size = 4, cond = 14} + return Operand{relative = off, kind = .RELATIVE, size = 4} } @(require_results) op_reg_list :: #force_inline proc "contextless" (mask: u16) -> Operand { - return Operand{immediate = i64(mask), kind = .REG_LIST, size = 2, cond = 14} + return Operand{immediate = i64(mask), kind = .REG_LIST, size = 2} } @(require_results) op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand { - return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx, cond = 14} + return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx} } @(require_results) op_qpr_lane :: #force_inline proc "contextless" (q: Register, idx: u8) -> Operand { - return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx, cond = 14} + return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx} } diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 8428dc513..242fad50c 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -124,7 +124,7 @@ sbprint :: proc( dt_suffix = infer_dt_suffix_from_inst(inst) } - write_mnemonic(sb, inst.mnemonic, inst.cond, inst.flags.sets_flags, opts.uppercase) + write_mnemonic(sb, inst.mnemonic, inst.cond, inst.sets_flags, opts.uppercase) if dt[0] != .NONE { write_data_type(sb, dt, opts.uppercase) } else if dt_suffix != "" { diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index 3583cb8d2..1e5e313a9 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -18,7 +18,7 @@ Instruction :: struct #packed { length: u8, // 1 -- always 4 _: [3]u8, } -#assert(size_of(Instruction) == 64) +#assert(size_of(Instruction) == 48) // ============================================================================= // Builders -- the most common shapes; less-common forms can be built diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 0cb0f3c25..f1fee81db 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -57,21 +57,28 @@ Address_Mode :: enum u8 { LITERAL, // PC-rel target (LDR literal) } -// 16-byte memory operand: base + optional index + signed disp + addressing -// metadata. Index is `NONE` for non-register-offset modes. -Memory :: struct #packed { - base: Register, // 2 - index: Register, // 2 (NONE for OFFSET/PRE/POST/LITERAL) - disp: i32, // 4 (signed; pre/post can be -256..255 unscaled, - // OFFSET supports 0..32760 scaled via imm12*size) - extend: Extend, // 1 (for EXT_REG_OFFSET; UXTX otherwise) - shift: u8, // 1 (0..4 for register-offset / extended; or - // shift amount for shifted-register operands - // when reused there) - mode: Address_Mode, // 1 - _: u8, // 1 +// Memory operand packed into one word: base + optional index + signed disp + +// addressing metadata. Index is `NONE` for non-register-offset modes. +// +// A bit_field rather than a struct because this sits in every Operand, so its +// width is multiplied by four in every Instruction. Field syntax is unchanged +// (`m.base`, `m.disp`) and composite literals still work, so this is invisible +// to callers. +// +// Widths: registers get the full 16 bits because the NONE sentinel is 0xFFFF. +// That leaves 23 bits for `disp` (+/-4.19M) against a worst case of 65,520 -- +// LDR Q, [Xn, #imm12*16] -- the largest displacement any A64 addressing mode +// can encode, so there is ~64x headroom. +Memory :: bit_field u64 { + base: Register | 16, + index: Register | 16, // NONE for OFFSET/PRE/POST/LITERAL + disp: i32 | 23, + extend: Extend | 3, // for EXT_REG_OFFSET; UXTX otherwise + shift: u8 | 3, // 0..4 for register-offset / extended + mode: Address_Mode | 3, + // 1 bit spare } -#assert(size_of(Memory) == 12) +#assert(size_of(Memory) == 8) Shifted_Reg :: struct #packed { reg: Register, // 2 @@ -91,7 +98,7 @@ Extended_Reg :: struct #packed { Operand :: struct #packed { using _: struct #raw_union #packed { reg: Register, // 2 - mem: Memory, // 12 + mem: Memory, // 8 immediate: i64, // 8 relative: i64, // 8 shifted: Shifted_Reg, // 8 @@ -101,7 +108,7 @@ Operand :: struct #packed { kind: Operand_Kind, // 1 size: u8, // 1 -- carried width info; meaning varies } -#assert(size_of(Operand) == 14) +#assert(size_of(Operand) == 10) // ----------------------------------------------------------------------------- // Constructors -- generic From 5a9a7e9f49e0412416607adbbd50bb072cc66a54 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 01:13:06 -0400 Subject: [PATCH 13/89] rexcode: pad arm32/arm64 Instruction back to 64 bytes and align it Shrinking Instruction to 48 was the wrong call, and measuring it said so. The premise was that a sub-cache-line struct touches fewer lines. It does -- but `#packed` aligns the struct to 1, so a 48-byte stride straddles a line boundary 75% of the time, and the heap base is not line-aligned either. The old 64-byte packed layout was worse still: 100% straddling, getting none of the benefit its size implied. Measured on an i7-9750H (L1d 32K/core, L2 256K, L3 12M), best-of-5, median of 3 interleaved rounds, against the 64-byte packed layout this branch started from: scan encode decode 64 packed (was) 1.000x 1.000x 1.000x 48 packed 0.909x 1.040x 1.022x 64 align(64) 1.218x 1.034x 0.806x Decode is ~19% faster aligned, and that holds at every working set including ones that fit entirely in L1 -- so it is split-store cost at the store ports, not cache-line fetches. Decode writes whole Instructions, and the aligned stores are worth more than the 33% extra bytes they move. A fourth variant -- 48 bytes with `#packed` removed -- was measured to rule out the obvious confound, and tracked 48-packed within 0.5% everywhere, so the win is alignment and not the loss of packing. Encode is within a few percent throughout (it is compute-bound; the form scan dominates), and the pure read traversal is slower, but that is a synthetic loop and its regression is codegen, not cache -- it is present even at L1-resident sizes where a standalone struct shows no such penalty. The Operand and Memory work from the previous commit is what makes this possible: a 45/48-byte payload now sits inside one line with room to spare, where the original spent all 64 bytes. The 16-19 spare bytes cost nothing over a straddling 48-byte struct and give new fields somewhere to land. All 11 rexcode suites match baseline; arm64 is 73/73 byte-exact against llvm-mc; arm32's 1680/1680 sweep passes and its encode spot-checks are unchanged. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/instructions.odin | 12 +++++++++-- core/rexcode/isa/arm64/instructions.odin | 26 ++++++++++++++++++++---- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 6261f977a..bbe3959cc 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -20,7 +20,11 @@ Instruction_Flags :: bit_field u8 { _: u8 | 6, } -Instruction :: struct #packed { +// Sized and aligned to a cache line -- see the note in arm64/instructions.odin. +// The payload is 48 bytes; padding out to 64 and aligning is worth ~21% on +// decode, because decode writes whole Instructions and unaligned stores are +// expensive enough to outweigh writing more bytes. +Instruction :: struct #align(64) { ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 10 = 40 mnemonic: Mnemonic, // 2 // cond, operand_count, mode, length and the two flag bits share one @@ -49,8 +53,12 @@ Instruction :: struct #packed { // every instruction did before this field existed. Set it and the encoder // picks the encoding for that type. dt: Data_Types, + // Spare, and free: a 48-byte struct straddles a cache line, so these 16 + // bytes cost nothing. New fields land here without changing the layout. + _: [16]u8, } -#assert(size_of(Instruction) == 48) +#assert(size_of(Instruction) == 64) +#assert(align_of(Instruction) == 64) // ============================================================================= // Builders diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index 1e5e313a9..fc7910658 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -10,15 +10,33 @@ Instruction_Flags :: bit_field u8 { _: u8 | 8, } -Instruction :: struct #packed { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) +// Sized and aligned to a cache line, deliberately. +// +// The payload is 45 bytes -- shrinking Operand to 10 got it there -- but +// leaving the struct at 48 was measurably worse than padding it back out. +// With `#packed` the struct aligns to 1, so a 48-byte stride straddles a line +// boundary 75% of the time and a 64-byte one straddled 100% of the time (the +// heap base is not line-aligned either). Decode writes whole Instructions, and +// unaligned stores cost enough that on an i7-9750H this layout decodes ~21% +// faster than the 48-byte packed one -- while writing MORE bytes. The gap +// holds even when the whole array is L1-resident, so it is split-store cost at +// the store ports, not cache-line fetches. +// +// Encode is within 1% and a pure read traversal is ~9% slower at working sets +// past L2, both of which the decode win dwarfs for real workloads. +// +// The 19 spare bytes are free: they cost nothing over a 48-byte struct that +// straddles, and new fields land in them without changing the layout. +Instruction :: struct #align(64) { + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) = 40 mnemonic: Mnemonic, // 2 operand_count: u8, // 1 flags: Instruction_Flags, // 1 length: u8, // 1 -- always 4 - _: [3]u8, + _: [19]u8, } -#assert(size_of(Instruction) == 48) +#assert(size_of(Instruction) == 64) +#assert(align_of(Instruction) == 64) // ============================================================================= // Builders -- the most common shapes; less-common forms can be built From 038e8a51ddfb33ad785d66047faf8aaa2431591c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 10:41:26 +0100 Subject: [PATCH 14/89] Format INSTRUCTION_TABLE --- .../isa/arm64/tablegen/instruction_table.odin | 4872 ++++++++--------- 1 file changed, 2436 insertions(+), 2436 deletions(-) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index fb287288e..9e720cd35 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -105,4009 +105,4009 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, .ADD = { - {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .ADDS = { - {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SUB = { - {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SUBS = { - {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, }, .AND = { - {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ANDS = { - {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { - {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EOR = { - {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BIC = { - {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BICS = { - {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { - {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EON = { - {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .LSL = { - {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .LSR = { - {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ASR = { - {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ROR = { - {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMP = { - {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMN = { - {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_COND = { - {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, - {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, - {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, }, .FMOV = { - {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, - {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, - {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .TST = { - {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .MUL = { - {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MLA = { - {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .MLS = { - {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .NEG = { - {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, - {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ABS = { - {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .ADDP = { - {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SMULL = { - {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SMULL2 = { - {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMULL = { - {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .UMULL2 = { - {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, }, .FMLA = { - {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMLS = { - {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMAXP = { - {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINP = { - {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXV = { - {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINV = { - {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, }, .FADDP = { - {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, }, .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .SHL = { - {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SQSHL = { - {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, }, .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, }, .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, }, .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, }, .DUP = { - {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, }, .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, }, .MOV = { - {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, - {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, - {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, + {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, }, .EXT = { - {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, }, .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .NOT = { - {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .URECPE = { - {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .URSQRTE = { - {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, }, .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, }, .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .ASRR = { - {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .LSLR = { - {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .LSRR = { - {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .FTSMUL = { - {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUBR = { - {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIVR = { - {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMLA = { - {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .FNMLS = { - {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, }, .SETFFR = { - {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { - {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, }, .CPY = { - {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .COMPACT = { - {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { - {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQRDMLSH = { - {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .ADCLB = { - {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .ADCLT = { - {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SBCLB = { - {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SBCLT = { - {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { - {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .HISTSEG = { - {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .SMSTART = { - {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, }, .SMSTOP = { - {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, }, .ADDHA = { - {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, }, .ADDVA = { - {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, }, .FMOPA = { - {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMOPS = { - {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPA = { - {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPS = { - {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SMOPA = { - {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .SMOPS = { - {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .UMOPA = { - {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .UMOPS = { - {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .USMOPA = { - {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, }, .SUMOPA = { - {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, - {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { - {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { - {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BSL1N = { - {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .BSL2N = { - {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .NBSL = { - {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .PMUL = { - {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, }, .BFCVTNT = { - {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .LDRAA = { - {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, }, .LDRAB = { - {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, }, .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, }, .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, }, .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, }, .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, }, .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, }, .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, }, .BC_COND = { - {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, }, .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, }, .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, }, .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, }, .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, }, .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, }, .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLUR = { - {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURB = { - {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURH = { - {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { - {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLS = { - {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, }, .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, }, .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .BFCLAMP = { - {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, }, .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, }, .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, }, .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, }, .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, }, .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, }, .PRFM = { - {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, - {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, }, .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMP = { - {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMN = { - {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, } From d805730c67f48f4e608d5dfb6aafb22605a74350 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 10:59:54 +0100 Subject: [PATCH 15/89] Correct `cpp-gen.odin` files --- .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 40 +++++-------------- .../x86/tablegen/cpp-compiler/cpp-gen.odin | 5 +++ src/asm_tables_amd64.cpp | 5 +++ src/asm_tables_riscv.cpp | 40 +++++-------------- src/check_asm.cpp | 10 +---- 5 files changed, 29 insertions(+), 71 deletions(-) diff --git a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin index 1eec54f16..2cf467d6e 100644 --- a/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin @@ -79,22 +79,9 @@ main :: proc() { { strings.write_string(&sb, "\n") strings.write_string(&sb, """ - static const u16 REG_CLASS_NONE = 0x000; - static const u16 REG_CLASS_GPR64 = 0x100; - static const u16 REG_CLASS_GPR32 = 0x200; - static const u16 REG_CLASS_GPR16 = 0x300; - static const u16 REG_CLASS_GPR8 = 0x400; - static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs - static const u16 REG_CLASS_XMM = 0x600; - static const u16 REG_CLASS_YMM = 0x700; - static const u16 REG_CLASS_ZMM = 0x800; - static const u16 REG_CLASS_K = 0x900; // opmask - static const u16 REG_CLASS_SEG = 0xA00; // segment - static const u16 REG_CLASS_CR = 0xB00; // control - static const u16 REG_CLASS_DR = 0xC00; // debug - static const u16 REG_CLASS_BND = 0xD00; // bound - static const u16 REG_CLASS_MM = 0xE00; // MMX - static const u16 REG_CLASS_ST = 0xF00; // x87 FPU + static const u16 REG_CLASS_NONE = 0x0000; + static const u16 REG_CLASS_GPR = 0x0100; // x0..x31 + static const u16 REG_CLASS_FPR = 0x0200; // f0..f31 \n """) { @@ -603,25 +590,16 @@ main :: proc() { // size in bits for register u16 reg_size(Register r) const { switch (reg_class(register_codes[r])) { - case REG_CLASS_GPR64: return 64; - case REG_CLASS_GPR32: return 32; - case REG_CLASS_GPR16: return 16; - case REG_CLASS_GPR8: return 8; - case REG_CLASS_GPR8H: return 8; - case REG_CLASS_XMM: return 128; - case REG_CLASS_YMM: return 256; - case REG_CLASS_ZMM: return 512; - case REG_CLASS_K: return 64; - case REG_CLASS_MM: return 64; - case REG_CLASS_ST: return 80; - case REG_CLASS_SEG: return 16; - case REG_CLASS_CR: return 64; - case REG_CLASS_DR: return 64; - case REG_CLASS_BND: return 128; + case REG_CLASS_GPR: return XLEN; + case REG_CLASS_FPR: return FLEN; } return 0; } + bool reg_is_segment(/*Register*/ u16 r) { + return false; + } + bool integer_reg_width_is_exact() const { return false; } diff --git a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin index 0ee411f3d..b7287752b 100644 --- a/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin @@ -592,6 +592,11 @@ main :: proc() { return 0; } + bool reg_is_segment(/*Register*/ u16 r) { + auto c = reg_class(register_codes[r]); + return c == REG_CLASS_SEG; + } + bool integer_reg_width_is_exact() const { return true; } diff --git a/src/asm_tables_amd64.cpp b/src/asm_tables_amd64.cpp index fe7fa0a0f..5ceb62af9 100644 --- a/src/asm_tables_amd64.cpp +++ b/src/asm_tables_amd64.cpp @@ -620,6 +620,11 @@ struct Asm_amd64 { return 0; } + bool reg_is_segment(/*Register*/ u16 r) { + auto c = reg_class(register_codes[r]); + return c == REG_CLASS_SEG; + } + bool integer_reg_width_is_exact() const { return true; } diff --git a/src/asm_tables_riscv.cpp b/src/asm_tables_riscv.cpp index 76f540513..405eddb8e 100644 --- a/src/asm_tables_riscv.cpp +++ b/src/asm_tables_riscv.cpp @@ -41,22 +41,9 @@ struct Asm_riscv { enum PrefixKind : u8 { PrefixKind_None }; - static const u16 REG_CLASS_NONE = 0x000; - static const u16 REG_CLASS_GPR64 = 0x100; - static const u16 REG_CLASS_GPR32 = 0x200; - static const u16 REG_CLASS_GPR16 = 0x300; - static const u16 REG_CLASS_GPR8 = 0x400; - static const u16 REG_CLASS_GPR8H = 0x500; // AH, CH, DH, BH - legacy high byte regs - static const u16 REG_CLASS_XMM = 0x600; - static const u16 REG_CLASS_YMM = 0x700; - static const u16 REG_CLASS_ZMM = 0x800; - static const u16 REG_CLASS_K = 0x900; // opmask - static const u16 REG_CLASS_SEG = 0xA00; // segment - static const u16 REG_CLASS_CR = 0xB00; // control - static const u16 REG_CLASS_DR = 0xC00; // debug - static const u16 REG_CLASS_BND = 0xD00; // bound - static const u16 REG_CLASS_MM = 0xE00; // MMX - static const u16 REG_CLASS_ST = 0xF00; // x87 FPU + static const u16 REG_CLASS_NONE = 0x0000; + static const u16 REG_CLASS_GPR = 0x0100; // x0..x31 + static const u16 REG_CLASS_FPR = 0x0200; // f0..f31 enum Register : u16 { REG_INVALID, REG_ZERO, REG_RA, REG_SP, REG_GP, REG_TP, REG_T0, REG_T1, REG_T2, REG_S0, REG_S1, REG_A0, REG_A1, REG_A2, REG_A3, REG_A4, @@ -576,25 +563,16 @@ struct Asm_riscv { // size in bits for register u16 reg_size(Register r) const { switch (reg_class(register_codes[r])) { - case REG_CLASS_GPR64: return 64; - case REG_CLASS_GPR32: return 32; - case REG_CLASS_GPR16: return 16; - case REG_CLASS_GPR8: return 8; - case REG_CLASS_GPR8H: return 8; - case REG_CLASS_XMM: return 128; - case REG_CLASS_YMM: return 256; - case REG_CLASS_ZMM: return 512; - case REG_CLASS_K: return 64; - case REG_CLASS_MM: return 64; - case REG_CLASS_ST: return 80; - case REG_CLASS_SEG: return 16; - case REG_CLASS_CR: return 64; - case REG_CLASS_DR: return 64; - case REG_CLASS_BND: return 128; + case REG_CLASS_GPR: return XLEN; + case REG_CLASS_FPR: return FLEN; } return 0; } + bool reg_is_segment(/*Register*/ u16 r) { + return false; + } + bool integer_reg_width_is_exact() const { return false; } diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 3a570692d..460047ea7 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -848,13 +848,6 @@ gb_internal bool check_register(AsmCtx *asm_ctx, Operand *operand, AstAsmRegiste if (r) { operand->mode = Addressing_Value; - u16 reg_class = asm_ctx->reg_class(r); - if (reg_class == asm_ctx->REG_CLASS_K) { - // Opmask register: classify as a mask, not a 64-bit integer. - // operand->type = t_asm_mask; // see note if this type does not yet exist - // return true; - } - u16 width_in_bits = asm_ctx->reg_size(r); switch (width_in_bits) { case 0: @@ -2019,8 +2012,7 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * } else if (segment_override.expr->kind == Ast_AsmRegister) { String reg_name = segment_override.expr->AsmRegister.name.string; auto reg = asm_ctx->register_lookup(reg_name); - auto reg_class = asm_ctx->reg_class(asm_ctx->register_codes[reg]); - if (reg_class != asm_ctx->REG_CLASS_SEG) { + if (!asm_ctx->reg_is_segment(cast(u16)reg)) { gbString s = expr_to_string(segment_override.expr); error(segment_override.expr, "A segment override must be a selector register parameter, got %s", s); gb_string_free(s); From 87b9b3974930838a600a3f84931aafc24e5917db Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 11:39:23 +0100 Subject: [PATCH 16/89] Begin integrating arm64 into the Odin compiler --- core/rexcode/isa/arm64/encoding_types.odin | 12 +- .../arm64/tablegen/cpp-compiler/cpp-gen.odin | 1234 +++++ core/rexcode/isa/arm64/tablegen/gen.odin | 13 +- .../tablegen/generated/decode_tables.odin | 4782 ++++++++--------- .../tablegen/generated/encode_tables.odin | 4778 ++++++++-------- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 48720 -> 48720 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 48760 -> 48760 bytes .../riscv/tablegen/cpp-compiler/cpp-gen.odin | 3 + .../x86/tablegen/cpp-compiler/cpp-gen.odin | 3 + src/asm_tables.cpp | 2 + src/asm_tables_amd64.cpp | 3 + src/asm_tables_riscv.cpp | 3 + src/check_asm.cpp | 4 +- 13 files changed, 6048 insertions(+), 4789 deletions(-) create mode 100644 core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 17816ae81..9b7353c7c 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -77,12 +77,12 @@ Endianness :: enum u8 { } Encoding_Flags :: bit_field u8 { - branch: bool | 1, // unconditional change of control flow - cond_branch: bool | 1, // PC-relative conditional - writes_pc: bool | 1, // any PC mutation (RET/BR/BLR/etc.) - sets_flags: bool | 1, // updates NZCV (ADDS/SUBS/ANDS/CMP/CMN/TST/CCMP) - is_64: bool | 1, // 64-bit variant (SF=1 for data-proc) - _: u8 | 3, + branch: bool | 1, // unconditional change of control flow + cond_branch: bool | 1, // PC-relative conditional + writes_pc: bool | 1, // any PC mutation (RET/BR/BLR/etc.) + sets_flags: bool | 1, // updates NZCV (ADDS/SUBS/ANDS/CMP/CMN/TST/CCMP) + is_64: bool | 1, // 64-bit variant (SF=1 for data-proc) + explicit_count: u8 | 3, } // What the user passes in. Most operand types describe a register class diff --git a/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin new file mode 100644 index 000000000..dc38c3dd2 --- /dev/null +++ b/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin @@ -0,0 +1,1234 @@ +package cpp_gen + +import "base:intrinsics" +import "core:fmt" +import "core:os" +import "core:strings" +import "core:reflect" +import "core:rexcode/isa/arm64" + +import gen ".." + +ISA_NAME :: "arm64" + +main :: proc() { + raw_encode_runs := #load("../../tables/arm64.encode_runs.bin", []arm64.Encode_Run) + raw_encode_forms := #load("../../tables/arm64.encode_forms.bin", []u8) + raw_clobber_forms := #load("../../tables/arm64.clobber_forms.bin", []u8) + // NOTE: arm64 has no pseudo-alias table (unlike riscv). Nothing to load here. + + sb := strings.builder_make() + + strings.write_string(&sb, """ + // ============================================================================= + // GENERATED FILE - DO NOT EDIT + // ============================================================================= + // + // Produces a C++ equivalent of the encoding table from core:rexcode written in Odin + // odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file + // odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin + // odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals + // + \n\n + """) + + + fmt.sbprintf(&sb, "struct Asm_%s {{\n", ISA_NAME) + { + strings.write_string(&sb, "\tenum Mnemonic : u16 {\n") + defer strings.write_string(&sb, "\t};\n"); + + iota := 0 + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + assert(int(mnemonic) == iota) + fmt.sbprintf(&sb, "M_%s, ", mnemonic) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + iota += 1 + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n\n"); + strings.write_string(&sb, "\t\tMNEMONIC_COUNT\n"); + } + + strings.write_string(&sb, "\tstatic String const mnemonic_strings[MNEMONIC_COUNT];\n") + + { + // arm64 has no instruction prefixes. Keep dummy symbols so the shared + // C++ front-end still has Prefix / PrefixKind to name. + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + enum Prefix : u8 { + PREFIX_INVALID, + PREFIX_COUNT + }; + enum PrefixKind : u8 { PrefixKind_None }; + \n + """) + } + { + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + static const u16 REG_CLASS_NONE = 0x0000; + static const u16 REG_CLASS_X = 0x0100; // X0..X30, XZR + static const u16 REG_CLASS_W = 0x0200; // W0..W30, WZR + static const u16 REG_CLASS_XSP = 0x0300; // SP (opt-in, distinct from X) + static const u16 REG_CLASS_WSP = 0x0400; // WSP (opt-in, distinct from W) + static const u16 REG_CLASS_V = 0x0500; // V0..V31 (full 128-bit SIMD&FP) + static const u16 REG_CLASS_B = 0x0600; // B0..B31 (byte view) + static const u16 REG_CLASS_H = 0x0700; // H0..H31 (half view) + static const u16 REG_CLASS_S = 0x0800; // S0..S31 (single view) + static const u16 REG_CLASS_D = 0x0900; // D0..D31 (double view) + static const u16 REG_CLASS_Q = 0x0A00; // Q0..Q31 (quad view) + static const u16 REG_CLASS_Z = 0x0B00; // Z0..Z31 SVE scalable vector + static const u16 REG_CLASS_P = 0x0C00; // P0..P15 SVE predicate + \n + """) + { + count := uint(0) + ROW_COUNT :: 16 + strings.write_string(&sb, "\tenum Register : u16 {\n") + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t\t") + } + fmt.sbprintf(&sb, "REG_%s, ", reg) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\t\tREG_COUNT\n") + strings.write_string(&sb, "\t};\n") + } + } + strings.write_string(&sb, "\n") + strings.write_string(&sb, """ + + // Condition flags (PSTATE.NZCV). Named ClobberFlags to match the shared + // C++ front-end's "flags" concept (x86 EFLAGS / riscv fcsr exceptions). + enum ClobberFlags : u8 { + ClobberFlag_N = 1<<0, // negative result + ClobberFlag_Z = 1<<1, // zero result + ClobberFlag_C = 1<<2, // carry-out / no-borrow (unsigned sense) + ClobberFlag_V = 1<<3, // signed overflow + }; + static u16 const CLOBBER_FLAGS_COND = ClobberFlag_N|ClobberFlag_Z|ClobberFlag_C|ClobberFlag_V; + + char const *clobber_flag_bit_name(u16 bit) { + switch (bit) { + case ClobberFlag_N: return \"n\"; + case ClobberFlag_Z: return \"z\"; + case ClobberFlag_C: return \"c\"; + case ClobberFlag_V: return \"v\"; + } + return \"?\"; + } + + // FPSR cumulative FP exception / saturation flags (separate register from NZCV). + enum FPSRFlags : u8 { + FPSRFlag_IOC = 1<<0, // invalid operation + FPSRFlag_DZC = 1<<1, // divide by zero + FPSRFlag_OFC = 1<<2, // overflow + FPSRFlag_UFC = 1<<3, // underflow + FPSRFlag_IXC = 1<<4, // inexact + FPSRFlag_IDC = 1<<5, // input denormal + FPSRFlag_QC = 1<<6, // cumulative saturation (Advanced SIMD) + }; + + char const *fpsr_flag_bit_name(u16 bit) { + switch (bit) { + case FPSRFlag_IOC: return \"ioc\"; + case FPSRFlag_DZC: return \"dzc\"; + case FPSRFlag_OFC: return \"ofc\"; + case FPSRFlag_UFC: return \"ufc\"; + case FPSRFlag_IXC: return \"ixc\"; + case FPSRFlag_IDC: return \"idc\"; + case FPSRFlag_QC: return \"qc\"; + } + return \"?\"; + } + + enum ClobberRegs : u8 { + ClobberReg_LR = 1<<0, // x30, implicit link written by BL/BLR, read by RET + ClobberReg_SP = 1<<1, // sp, implicit base on PACIASP/AUTIASP + stack forms + ClobberReg_X16 = 1<<2, // implicit modifier register for PAC*1716 / AUT*1716 + ClobberReg_X17 = 1<<3, // implicit pointer register for PAC*1716 / AUT*1716 + }; + + static u8 const CLOBBER_REGS_NAMED = + ClobberReg_LR|ClobberReg_SP|ClobberReg_X16|ClobberReg_X17; + + enum SideEffectFlags : u16 { + SideEffectFlag_CONTROL = 1<<0, // writes pc: B/BL/BR/BLR/RET, B.cond, CBZ/CBNZ, TBZ/TBNZ + SideEffectFlag_EXCEPTION = 1<<1, // exception-generating call: SVC / HVC / SMC + SideEffectFlag_TRAP = 1<<2, // deliberately faults: BRK, UDF + SideEffectFlag_FENCE = 1<<3, // memory-ordering barrier: DMB/DSB, acquire/release + SideEffectFlag_ISYNC = 1<<4, // instruction-stream / context sync: ISB + SideEffectFlag_ATOMIC = 1<<5, // indivisible RMW: LDXR/STXR pair, LSE + SideEffectFlag_RESERVATION = 1<<6, // sets/tests/clears the local monitor: LDXR/STXR, CLREX + SideEffectFlag_CACHE = 1<<7, // cache maintenance with coherence effects: DC, IC + SideEffectFlag_HINT = 1<<8, // architecturally-inert hint: NOP/YIELD/PRFM/SEV/ESB/CSDB + SideEffectFlag_BTI = 1<<9, // branch-target-identification landing pad (CFI) + SideEffectFlag_PAC = 1<<10, // pointer authentication: reads an implicit key, may fault + SideEffectFlag_WAIT = 1<<11, // suspends execution until event/interrupt: WFI/WFE + SideEffectFlag_PRIVILEGED = 1<<12, // reads/writes system state: MSR/MRS, ERET, TLBI, AT, DAIF + SideEffectFlag_FFR = 1<<13, // reads/writes the SVE first-fault register + SideEffectFlag_NONDETERMINISTIC = 1<<14, // RNDR/RNDRRS, counter/timer reads (CNTVCT), TSTART + }; + + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + + u16 clobber_bit_for_reg_name(String const &pin) { + static const struct { String name; u16 bit; } table[] = { + {str_lit(\"lr\"), ClobberReg_LR}, + {str_lit(\"x30\"), ClobberReg_LR}, + {str_lit(\"w30\"), ClobberReg_LR}, + {str_lit(\"sp\"), ClobberReg_SP}, + {str_lit(\"wsp\"), ClobberReg_SP}, + {str_lit(\"x16\"), ClobberReg_X16}, + {str_lit(\"w16\"), ClobberReg_X16}, + {str_lit(\"x17\"), ClobberReg_X17}, + {str_lit(\"w17\"), ClobberReg_X17}, + }; + for (auto const &t : table) { + if (pin == t.name) { + return t.bit; + } + } + return 0; + } + + char const *clobber_reg_bit_name(u16 bit) { + switch (bit) { + case ClobberReg_LR: return \"lr\"; + case ClobberReg_SP: return \"sp\"; + case ClobberReg_X16: return \"x16\"; + case ClobberReg_X17: return \"x17\"; + } + return \"\"; + } + + + u16 flag_from_name(String const &name) { + // NZCV condition flags. + static const struct { String name; ClobberFlags flag; } table[] = { + {str_lit(\"n\"), ClobberFlag_N}, + {str_lit(\"z\"), ClobberFlag_Z}, + {str_lit(\"c\"), ClobberFlag_C}, + {str_lit(\"v\"), ClobberFlag_V}, + }; + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + u16 fpsr_flag_from_name(String const &name) { + static const struct { String name; FPSRFlags flag; } table[] = { + {str_lit(\"ioc\"), FPSRFlag_IOC}, // Invalid Operation + {str_lit(\"dzc\"), FPSRFlag_DZC}, // Divide by Zero + {str_lit(\"ofc\"), FPSRFlag_OFC}, // Overflow + {str_lit(\"ufc\"), FPSRFlag_UFC}, // Underflow + {str_lit(\"ixc\"), FPSRFlag_IXC}, // Inexact + {str_lit(\"idc\"), FPSRFlag_IDC}, // Input Denormal + {str_lit(\"qc\"), FPSRFlag_QC}, // Cumulative Saturation + }; + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + + i32 flag_bit_from_name(String const &name, i32 *width_) { + // Real PSTATE.NZCV bit positions (as read/written via MRS/MSR NZCV, bits 31:28). + static const struct { String name; i32 bit; } table[] = { + {str_lit(\"v\"), 28}, // Overflow + {str_lit(\"c\"), 29}, // Carry + {str_lit(\"z\"), 30}, // Zero + {str_lit(\"n\"), 31}, // Negative + }; + for (auto const &t : table) { + if (name == t.name) { + if (width_) { + *width_ = 1; + } + return t.bit; + } + } + return -1; + } + + + struct Clobber { + OperandSet written; // operand slots whose register/SIMD reg is written + OperandSet read; // operand slots whose register / mem-base is read + ClobberRegs implicit_wr; // implicit reg writes (LR on BL/BLR) + ClobberRegs implicit_rd; // implicit reg reads (LR on RET, SP on PAC*SP) + ClobberFlags nzcv_wr; // condition flags written (ADDS/SUBS/ANDS, CMP, FCMP, CCMP...) + ClobberFlags nzcv_undef; // condition flags left UNKNOWN (rare on A64, usually empty) + ClobberFlags nzcv_rd; // condition flags read (B.cond, CSEL, ADC/SBC, CCMP...) + FPSRFlags fpsr_wr; // FP cumulative exception/saturation flags this op may raise + bool reads_fpcr; // consumes the rounding mode / FP control from FPCR + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; + + ClobberFlags flags_rd_call() const { + return nzcv_rd; + } + ClobberFlags flags_wr_call() const { + return nzcv_wr; + } + + bool implies_clobber_flags() const { + return ((cast(u16)nzcv_wr | cast(u16)nzcv_undef) != 0) || + (cast(u16)fpsr_wr != 0); + } + bool implies_clobber_memory() const { + return writes_mem || reads_mem || + (cast(u16)side_effects & (SideEffectFlag_FENCE|SideEffectFlag_ATOMIC|SideEffectFlag_CACHE)) != 0; + } + bool implies_side_effects() const { + u16 const VOLATILE_SE = + SideEffectFlag_CONTROL | + SideEffectFlag_EXCEPTION | + SideEffectFlag_TRAP | + SideEffectFlag_FENCE | + SideEffectFlag_ISYNC | + SideEffectFlag_ATOMIC | + SideEffectFlag_RESERVATION | + SideEffectFlag_CACHE | + SideEffectFlag_BTI | + SideEffectFlag_PAC | + SideEffectFlag_WAIT | + SideEffectFlag_PRIVILEGED | + SideEffectFlag_FFR | + SideEffectFlag_NONDETERMINISTIC; + // NOTE: SideEffectFlag_HINT deliberately excluded โ€” inert, may be DCE'd. + return (cast(u16)side_effects & VOLATILE_SE) != 0; + } + u8 is_call_or_mem() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0 || + (cast(u16)implicit_wr & (ClobberReg_LR|ClobberReg_SP)) != 0; + } + bool has_control() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0; + } + bool has_halt() const { + // WFI/WFE suspend execution (x86 HLT analog); SVC/HVC/SMC gate out. + return (cast(u16)side_effects & (SideEffectFlag_WAIT|SideEffectFlag_EXCEPTION)) != 0; + } + bool is_conditional() const { + return has_control() && (cast(u16)nzcv_rd != 0); + } + bool is_nondeterministic() const { + return (cast(u16)side_effects & SideEffectFlag_NONDETERMINISTIC) != 0; + } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + bool is_atomic = (cast(u16)side_effects & SideEffectFlag_ATOMIC) != 0; + return (implicit & ClobberReg_SP) != 0 || is_atomic; + } + }; + + void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { + u8 regs = cast(u8)implicit_regs & CLOBBER_REGS_NAMED; + + for (u8 bit = 1; bit != 0; bit <<= 1) { + if ((regs & bit) == 0) { + continue; + } + char const *rname = clobber_reg_bit_name(bit); + string_set_update(clobber_registers_set, make_string_c(rname)); + } + } + """) + strings.write_string(&sb, "\n") + + strings.write_string(&sb, "\n") + { + // arm64 has no pseudo-alias expansion table. These are dummy definitions + // (as in the x86 generator) so the shared C++ front-end still links. + strings.write_string(&sb, """ + enum AliasSrc : u8 { + AliasSrc_NONE, // slot unused + AliasSrc_ARG0, // user's 1st operand + AliasSrc_ARG1, // user's 2nd operand + AliasSrc_ARG2, // user's 3rd operand + AliasSrc_ZERO, // hardwired zero + AliasSrc_LINK, // link register + AliasSrc_LIT, // immediate literal + }; + + // NOTE(arm64): dummy โ€” only riscv needs pseudo aliases; arm64 has none. + struct PseudoAlias { + Mnemonic target; // real instruction emitted + AliasSrc src[4]; // how to fill target's four operand slots + i16 lit; // immediate when a src slot is AliasSrc_LIT + u16 csr; // unused on arm64 + u8 nargs; // operands the user supplies (ARG0..>%du)&((1u<<%d)-1));", bit_offset, bit_size) + strings.write_string(&sb, " }\n") + } + } + strings.write_string(&sb, "\n\n") + { + strings.write_string(&sb, "\t// Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS.\n") + strings.write_string(&sb, "\tstruct EncodeRun {\n") + strings.write_string(&sb, "\t\tu32 start; // start index in ENCODE_FORMS\n") + strings.write_string(&sb, "\t\tu32 count; // number of forms for this mnemonic\n") + strings.write_string(&sb, "\t};\n") + } + + strings.write_string(&sb, "\n\n") + fmt.sbprintf(&sb, "\tstatic EncodeRun const raw_encode_runs [%d];\n", len(raw_encode_runs)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_encode_forms [%d];\n", len(raw_encode_forms)) + fmt.sbprintf(&sb, "\tstatic u8 const raw_clobber_forms[%d];\n", len(raw_clobber_forms)) + strings.write_string(&sb, "\n") + strings.write_string(&sb, "\tStringMap mnemonic_map;\n") + strings.write_string(&sb, "\tStringMap register_map;\n") + + strings.write_string(&sb, """ + + bool init(i64 word_size) { + gb_unused(word_size); // A64 is fixed 64-bit; W views are the 32-bit half. + + string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); + for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { + string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); + } + + string_map_init(®ister_map, REG_COUNT*2); + for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_strings[r], cast(Register)r); + } + return true; + } + + + enum MnemonicSuffix : u8 { + MnemonicSuffix_None = 0, + }; + + bool mnemonic_accepts_suffix(u16 m) const { + // A64 acquire/release/atomic variants are distinct mnemonics (LDAR, STLR, + // LDADDA...), not textual suffixes on a base mnemonic. + gb_unused(m); + return false; + } + + Mnemonic mnemonic_lookup_ordered(String const &name, u8 *suffixes_) { + gb_unused(name); + gb_unused(suffixes_); + return M_INVALID; + } + + enum PseudoMacroMnemonic : u8 { + PseudoMacroMnemonic_INVALID, + PseudoMacroMnemonic_COUNT + // NOTE: MOV-wide-immediate expansion (MOV -> MOVZ/MOVN/MOVK sequence) could + // be modelled here if the front-end wants macro lowering for arm64. + }; + + PseudoMacroMnemonic pseudo_macro_mnemonic_lookup(String const &name) { + gb_unused(name); + return PseudoMacroMnemonic_INVALID; + } + + Mnemonic mnemonic_lookup(String const &name) { + Mnemonic *found = string_map_get(&mnemonic_map, name); + return found ? *found : M_INVALID; + } + Prefix prefix_lookup(String const &name) { + gb_unused(name); + return PREFIX_INVALID; + } + static String const prefix_strings[PREFIX_COUNT]; + + Register register_lookup(String const &name) { + Register *found = string_map_get(®ister_map, name); + return found ? *found : REG_INVALID; + } + Slice encoding_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; + return Slice{ENCODE_FORMS+r.start, r.count}; + } + Slice clobber_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms; + return Slice{CLOBBER_FORMS+r.start, r.count}; + } + u16 reg_class(/*Register*/ u16 r) const { + return 0xFF00 & r; + } + // size in bits for register + u16 reg_size(Register r) const { + switch (reg_class(register_codes[r])) { + case REG_CLASS_X: return 64; + case REG_CLASS_W: return 32; + case REG_CLASS_XSP: return 64; + case REG_CLASS_WSP: return 32; + case REG_CLASS_V: return 128; + case REG_CLASS_B: return 8; + case REG_CLASS_H: return 16; + case REG_CLASS_S: return 32; + case REG_CLASS_D: return 64; + case REG_CLASS_Q: return 128; + case REG_CLASS_Z: return 0; // SVE scalable (VL, implementation-defined) + case REG_CLASS_P: return 0; // SVE predicate (scalable) + } + return 0; + } + + bool reg_is_segment(/*Register*/ u16 r) { + gb_unused(r); + return false; // arm64 has no segment registers + } + + bool integer_reg_width_is_exact() const { + return true; // X = 64, W = 32 always + } + bool float_reg_width_is_exact() const { + return true; // B/H/S/D/Q scalar views are exact widths + } + bool supports_memory_index_not_just_disp() const { + return true; // base + (optionally extended/shifted) index register + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmOperandKind kind_from_operand_type(OperandType type) const { + switch (type) { + case OP_NONE: + return AsmOperand_Invalid; + + // ---- Registers ---- + // Integer GPR / GPR-or-SP, including shifted- and extended-register forms. + case OP_W_REG: case OP_X_REG: + case OP_WSP_REG: case OP_XSP_REG: + case OP_W_SHIFTED: case OP_X_SHIFTED: + case OP_W_EXTENDED: case OP_X_EXTENDED: + // SIMD&FP scalar views. + case OP_B_REG: case OP_H_REG: case OP_S_REG: case OP_D_REG: case OP_Q_REG: + // NEON vector: plain, arrangement, FP16, element-indexed. + case OP_V_REG: + case OP_V_8B: case OP_V_16B: case OP_V_4H: case OP_V_8H: + case OP_V_2S: case OP_V_4S: case OP_V_1D: case OP_V_2D: + case OP_V_4H_FP16: case OP_V_8H_FP16: + case OP_V_ELEM_B: case OP_V_ELEM_H: case OP_V_ELEM_S: case OP_V_ELEM_D: + // SVE vector + predicate registers. + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: + // SME2 multi-vector register lists (first register of the list). + case OP_Z_PAIR: case OP_Z_QUAD: + // SME ZA tiles (ZA0.B .. ZAn.Q) โ€” register-like tile operands. + case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S: + case OP_ZA_TILE_D: case OP_ZA_TILE_Q: + return AsmOperand_Register; + + // ---- Immediates (numeric literals and immediate-encoded selectors) ---- + case OP_IMM_2: case OP_IMM_3: case OP_IMM_4: case OP_IMM_5: + case OP_IMM_6: case OP_IMM_8: case OP_IMM_12: case OP_IMM_16: + case OP_NZCV_IMM: + case OP_HW_SHIFT: + case OP_BITMASK_IMM: + case OP_LSE_SIZE: + case OP_LSL_SHIFT_W: case OP_LSL_SHIFT_X: case OP_ROR_SHIFT: + case OP_FCMLA_ROT: case OP_FCADD_ROT: + case OP_SVE_PRFOP: + case OP_VEC_SHIFT: case OP_VEC_INDEX: + // Enum-like tokens that encode into an immediate field: + case OP_COND: // condition code (EQ/NE/...) -> 4-bit field + case OP_SYS_REG: // MRS/MSR system-register name -> 16-bit field (cf. riscv CSR) + case OP_SME_PATTERN: case OP_SVE_PATTERN: // pattern / tile-list selectors + // JUDGMENT CALL: the following are register/tile-slice constructs + // syntactically, but this table models each as a single packed immediate + // descriptor (see Operand_Type comments). If the front-end parses their + // bracketed tile-slice / [Xn,#imm] syntax, reclassify as Register/Memory. + case OP_SME_SLICE_B: case OP_SME_SLICE_H: case OP_SME_SLICE_W: + case OP_SME_SLICE_D: case OP_SME_SLICE_Q: + case OP_LDRAA_IMM10: // signed imm10 displacement of the PAC-load address form + return AsmOperand_Immediate; + + // ---- Branch / PC-relative targets (written as labels) ---- + case OP_REL_26: case OP_REL_19: case OP_REL_14: case OP_REL_PG21: + return AsmOperand_Label; + + // ---- Memory addressing modes ---- + case OP_MEM_OFFSET: case OP_MEM_PRE: case OP_MEM_POST: + case OP_MEM_REG: case OP_MEM_EXT: + case OP_MEM_SVE_SS: case OP_MEM_SVE_SI: + case OP_MEM_SVE_VEC: case OP_MEM_SVE_VB: + return AsmOperand_Memory; + } + return AsmOperand_Invalid; + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmRegClass reg_class_from_operand_type(OperandType type) const { + switch (type) { + // Integer GPRs (incl. GPR-or-SP and shifted/extended register forms). + case OP_W_REG: case OP_X_REG: + case OP_WSP_REG: case OP_XSP_REG: + case OP_W_SHIFTED: case OP_X_SHIFTED: + case OP_W_EXTENDED: case OP_X_EXTENDED: + return AsmRegClass_Integer; + + // SIMD&FP scalar views share the V register file; treated as the float class. + case OP_B_REG: case OP_H_REG: case OP_S_REG: case OP_D_REG: case OP_Q_REG: + return AsmRegClass_Float; + + // NEON vectors (plain / arrangement / FP16 / element-indexed), SVE Z + // vectors, and SME2 Z register-lists โ€” all the vector register file. + case OP_V_REG: + case OP_V_8B: case OP_V_16B: case OP_V_4H: case OP_V_8H: + case OP_V_2S: case OP_V_4S: case OP_V_1D: case OP_V_2D: + case OP_V_4H_FP16: case OP_V_8H_FP16: + case OP_V_ELEM_B: case OP_V_ELEM_H: case OP_V_ELEM_S: case OP_V_ELEM_D: + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: + case OP_Z_PAIR: case OP_Z_QUAD: + return AsmRegClass_Vector; + + // SVE predicate registers. + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: + return AsmRegClass_Mask; + + // Everything else has no GPR/vector/mask class: + // - immediates, selectors, memory, labels, cond, sysreg, patterns. + // - ZA_TILE_* are SME ZA-tile registers, but AsmRegClass has no + // matrix/tile class, so they fall through to Unknown here (still + // Register-kind, the same shape as x86 SREG/CR/DR). + default: + return AsmRegClass_Unknown; + } + } + """) + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + bool operand_type_is_implicit(OperandType t) const { + // A64 operands are written explicitly; fixed regs (LR on RET, SP/X16/X17 + // on PAC*) are tracked via the Clobber implicit_rd/implicit_wr sets, not + // as implicit operand-type slots. + gb_unused(t); + return false; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + AsmRegClass operand_type_reg_class(OperandType t) const { + // Same mapping as reg_class_from_operand_type. + return reg_class_from_operand_type(t); + } + """) + + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + // A64 has no operand slot that only one named hardware register can fill + // (SP-taking slots accept any Xn or SP via the *_SP classes). + u16 operand_type_named_reg_class(OperandType t) const { + gb_unused(t); + return REG_CLASS_NONE; + } + + String named_reg_class_string(u16 reg_class) const { + gb_unused(reg_class); + return str_lit("hardware"); + } + """) + + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + u16 operand_type_bit_width(OperandType t) const { + switch (t) { + case OP_NONE: + return 0; + + // ---- Integer registers (incl. shifted/extended forms) -> data width ---- + case OP_W_REG: case OP_WSP_REG: case OP_W_SHIFTED: case OP_W_EXTENDED: + return 32; + case OP_X_REG: case OP_XSP_REG: case OP_X_SHIFTED: case OP_X_EXTENDED: + return 64; + + // ---- SIMD&FP scalar views ---- + case OP_B_REG: return 8; + case OP_H_REG: return 16; + case OP_S_REG: return 32; + case OP_D_REG: return 64; + case OP_Q_REG: return 128; + + // ---- NEON vectors: total register width of the arrangement ---- + case OP_V_REG: + return 128; // full V (Q view) + case OP_V_8B: case OP_V_4H: case OP_V_2S: case OP_V_1D: + case OP_V_4H_FP16: + return 64; // 64-bit (D-register) arrangements + case OP_V_16B: case OP_V_8H: case OP_V_4S: case OP_V_2D: + case OP_V_8H_FP16: + return 128; // 128-bit (Q-register) arrangements + + // ---- Element-indexed vector: width of the indexed element ---- + case OP_V_ELEM_B: return 8; + case OP_V_ELEM_H: return 16; + case OP_V_ELEM_S: return 32; + case OP_V_ELEM_D: return 64; + + // ---- Immediates -> value / encoded-field width ---- + case OP_IMM_2: return 2; + case OP_IMM_3: return 3; + case OP_IMM_4: return 4; + case OP_IMM_5: return 5; + case OP_IMM_6: return 6; + case OP_IMM_8: return 8; + case OP_IMM_12: return 12; + case OP_IMM_16: return 16; + case OP_NZCV_IMM: return 4; + case OP_HW_SHIFT: return 2; // 2-bit LSL hw (0/16/32/48) + case OP_LSE_SIZE: return 2; + case OP_SYS_REG: return 16; // op0:op1:CRn:CRm:op2 packed + case OP_LSL_SHIFT_W: return 5; // 0..31 + case OP_LSL_SHIFT_X: return 6; // 0..63 + case OP_ROR_SHIFT: return 6; // imms field + case OP_FCMLA_ROT: return 2; + case OP_FCADD_ROT: return 1; + case OP_SVE_PRFOP: return 4; + case OP_LDRAA_IMM10: return 10; + case OP_COND: return 4; + case OP_SVE_PATTERN: return 5; // 5-bit pattern field (PTRUE) + + // ---- PC-relative displacement value widths ---- + case OP_REL_26: return 26; + case OP_REL_19: return 19; + case OP_REL_14: return 14; + case OP_REL_PG21: return 21; // ADR/ADRP imm21 (ADRP scaled << 12) + + // ---- Width is scalable, data-dependent, or set elsewhere -> 0 ---- + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: // SVE VL-scaled + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: // predicate (VL/8) + case OP_Z_PAIR: case OP_Z_QUAD: // SVE reg-lists (scalable) + case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S: + case OP_ZA_TILE_D: case OP_ZA_TILE_Q: // SME tiles (scalable) + case OP_SME_PATTERN: // selector, no data width + case OP_SME_SLICE_B: case OP_SME_SLICE_H: case OP_SME_SLICE_W: + case OP_SME_SLICE_D: case OP_SME_SLICE_Q: // packed slice descriptor + case OP_BITMASK_IMM: // value width = operand width (32/64) + case OP_VEC_SHIFT: // element-size dependent + case OP_VEC_INDEX: // element-size dependent + case OP_MEM_OFFSET: case OP_MEM_PRE: case OP_MEM_POST: + case OP_MEM_REG: case OP_MEM_EXT: + case OP_MEM_SVE_SS: case OP_MEM_SVE_SI: + case OP_MEM_SVE_VEC: case OP_MEM_SVE_VB: // access size from opcode + return 0; + } + return 0; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + int form_explicit_slot(Encoding const &form, int explicit_index) const { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; + } + """) + + strings.write_string(&sb, "\n\n") + + strings.write_string(&sb, """ + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const { + // arm64 does not have instruction prefixes. + gb_unused(prefix); + gb_unused(form); + gb_unused(requires_memory_dest_); + return false; + } + """) + + strings.write_string(&sb, "\n") + + strings.write_string(&sb, """ + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_LSL: case M_LSR: case M_ASR: case M_ROR: + if (op == 2) return {AsmOperandConstraint_ShiftCount, /*reg width*/-1}; + break; + // NOTE: A64 SDIV/UDIV by zero returns 0 (no fault), so no + // NonZeroDivisor constraint is emitted for division. + } + return {AsmOperandConstraint_None, -1}; + } + """) + + strings.write_string(&sb, """ + bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + case M_EOR: // x ^ x == 0 + case M_SUB: // x - x == 0 + case M_BIC: // x & ~x == 0 + return true; + } + return false; + } + """) + + strings.write_string(&sb, "\n};\n") + + strings.write_string(&sb, "\n\n\n") + + fmt.sbprintf(&sb, "gb_global Asm_{0:s} g_asm_{0:s};\n", ISA_NAME) + + strings.write_string(&sb, "\n\n\n") + + fmt.sbprintf(&sb, "String const Asm_{0:s}::prefix_strings[Asm_{0:s}::PREFIX_COUNT]{{}};\n", ISA_NAME) + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::mnemonic_strings[Asm_{0:s}::MNEMONIC_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for mnemonic in gen.Mnemonic { + if count == 0 { + strings.write_string(&sb, "\t") + } + + #partial switch mnemonic { + case .INVALID: + strings.write_string(&sb, "str_lit(\"\"), ") + case: + str := strings.to_lower(reflect.enum_string(mnemonic)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "u16 const Asm_{0:s}::register_codes[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + fmt.sbprintf(&sb, "%d, ", REG_CODES[reg]) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + { + fmt.sbprintf(&sb, "String const Asm_{0:s}::register_strings[Asm_{0:s}::REG_COUNT] {{\n", ISA_NAME) + defer strings.write_string(&sb, "};\n"); + + count := uint(0) + ROW_COUNT :: 16 + for reg in Register { + if count == 0 { + strings.write_string(&sb, "\t") + } + + if reg == .INVALID { + strings.write_string(&sb, "str_lit(\"\"), ") + } else { + str := strings.to_lower(reflect.enum_string(reg)) + fmt.sbprintf(&sb, "str_lit(%q), ", str) + delete(str) + } + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + strings.write_string(&sb, "\n") + } + + // arm64 has no pseudo mnemonics. + fmt.sbprintf(&sb, "String const Asm_{0:s}::pseudo_mnemonic_strings[Asm_{0:s}::PSEUDO_MNEMONIC_COUNT] {{}};\n", ISA_NAME) + + { + fmt.sbprintf(&sb, "Asm_{0:s}::EncodeRun const Asm_{0:s}::raw_encode_runs[{1:d}] = {{\n", ISA_NAME, len(raw_encode_runs)) + defer strings.write_string(&sb, "};\n"); + + ROW_COUNT :: 16 + count := 0 + for run in raw_encode_runs { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "{{% 4d, % 2d}}, ", run.start, run.count) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_encode_forms[%d] = {{\n", ISA_NAME, len(raw_encode_forms)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_encode_forms { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + { + fmt.sbprintf(&sb, "u8 const Asm_{0:s}::raw_clobber_forms[%d] = {{\n", ISA_NAME, len(raw_clobber_forms)) + defer strings.write_string(&sb, "};\n"); + ROW_COUNT :: 64 + count := 0 + for the_byte in raw_clobber_forms { + if count == 0 { + strings.write_string(&sb, "\t") + } + fmt.sbprintf(&sb, "%#02x, ", the_byte) + + if count == ROW_COUNT-1 { + strings.write_string(&sb, "\n") + } + + count = (count + 1) % ROW_COUNT + } + defer strings.write_string(&sb, "\n") + } + + + + path := fmt.tprintf("%s/src/asm_tables_%s.cpp", ODIN_ROOT, ISA_NAME) + + if err := os.write_entire_file(path, strings.to_string(sb)); err != nil { + fmt.eprintfln("rexcode tablegen: failed to write %s: %v", path, err) + os.exit(1) + } +} + +Operand_Encoding :: type_of(gen.Encoding{}.enc[0]) +Feature :: type_of(gen.Encoding{}.feature) + + + +Register :: enum u16 { + INVALID, + X0, + X1, + X2, + X3, + X4, + X5, + X6, + X7, + X8, + X9, + X10, + X11, + X12, + X13, + X14, + X15, + X16, + X17, + X18, + X19, + X20, + X21, + X22, + X23, + X24, + X25, + X26, + X27, + X28, + X29, + X30, + XZR, + SP, + W0, + W1, + W2, + W3, + W4, + W5, + W6, + W7, + W8, + W9, + W10, + W11, + W12, + W13, + W14, + W15, + W16, + W17, + W18, + W19, + W20, + W21, + W22, + W23, + W24, + W25, + W26, + W27, + W28, + W29, + W30, + WZR, + WSP, + V0, + V1, + V2, + V3, + V4, + V5, + V6, + V7, + V8, + V9, + V10, + V11, + V12, + V13, + V14, + V15, + V16, + V17, + V18, + V19, + V20, + V21, + V22, + V23, + V24, + V25, + V26, + V27, + V28, + V29, + V30, + V31, +} + +REG_NONE :: 0x0000 +REG_X :: 0x0100 // X0..X30, XZR (X31 = ZR semantically) +REG_W :: 0x0200 // W0..W30, WZR +REG_XSP :: 0x0300 // SP (only -- distinct class from X to opt-in) +REG_WSP :: 0x0400 // WSP +REG_V :: 0x0500 // V0..V31 (full 128-bit; used in NEON vector form) +REG_B :: 0x0600 // B0..B31 (byte view) +REG_H :: 0x0700 // H0..H31 (half view) +REG_S :: 0x0800 // S0..S31 (single view) +REG_D :: 0x0900 // D0..D31 (double view) +REG_Q :: 0x0A00 // Q0..Q31 (quad view) +REG_Z :: 0x0B00 // Z0..Z31 SVE scalable vector (low 128 aliased with V) +REG_P :: 0x0C00 // P0..P15 SVE predicate + + +@(rodata) +REG_CODES := [Register]arm64.Register{ + .INVALID = 0, + + .X0 = arm64.Register(REG_X | 0), .X1 = arm64.Register(REG_X | 1), .X2 = arm64.Register(REG_X | 2), .X3 = arm64.Register(REG_X | 3), + .X4 = arm64.Register(REG_X | 4), .X5 = arm64.Register(REG_X | 5), .X6 = arm64.Register(REG_X | 6), .X7 = arm64.Register(REG_X | 7), + .X8 = arm64.Register(REG_X | 8), .X9 = arm64.Register(REG_X | 9), .X10 = arm64.Register(REG_X | 10), .X11 = arm64.Register(REG_X | 11), + .X12 = arm64.Register(REG_X | 12), .X13 = arm64.Register(REG_X | 13), .X14 = arm64.Register(REG_X | 14), .X15 = arm64.Register(REG_X | 15), + .X16 = arm64.Register(REG_X | 16), .X17 = arm64.Register(REG_X | 17), .X18 = arm64.Register(REG_X | 18), .X19 = arm64.Register(REG_X | 19), + .X20 = arm64.Register(REG_X | 20), .X21 = arm64.Register(REG_X | 21), .X22 = arm64.Register(REG_X | 22), .X23 = arm64.Register(REG_X | 23), + .X24 = arm64.Register(REG_X | 24), .X25 = arm64.Register(REG_X | 25), .X26 = arm64.Register(REG_X | 26), .X27 = arm64.Register(REG_X | 27), + .X28 = arm64.Register(REG_X | 28), .X29 = arm64.Register(REG_X | 29), .X30 = arm64.Register(REG_X | 30), + .XZR = arm64.Register(REG_X | 31), + + .SP = arm64.Register(REG_XSP | 31), + + // ----------------------------------------------------------------------------- + // 32-bit GPRs (W0..W30, WZR, WSP) + // ----------------------------------------------------------------------------- + + .W0 = arm64.Register(REG_W | 0), .W1 = arm64.Register(REG_W | 1), .W2 = arm64.Register(REG_W | 2), .W3 = arm64.Register(REG_W | 3), + .W4 = arm64.Register(REG_W | 4), .W5 = arm64.Register(REG_W | 5), .W6 = arm64.Register(REG_W | 6), .W7 = arm64.Register(REG_W | 7), + .W8 = arm64.Register(REG_W | 8), .W9 = arm64.Register(REG_W | 9), .W10 = arm64.Register(REG_W | 10), .W11 = arm64.Register(REG_W | 11), + .W12 = arm64.Register(REG_W | 12), .W13 = arm64.Register(REG_W | 13), .W14 = arm64.Register(REG_W | 14), .W15 = arm64.Register(REG_W | 15), + .W16 = arm64.Register(REG_W | 16), .W17 = arm64.Register(REG_W | 17), .W18 = arm64.Register(REG_W | 18), .W19 = arm64.Register(REG_W | 19), + .W20 = arm64.Register(REG_W | 20), .W21 = arm64.Register(REG_W | 21), .W22 = arm64.Register(REG_W | 22), .W23 = arm64.Register(REG_W | 23), + .W24 = arm64.Register(REG_W | 24), .W25 = arm64.Register(REG_W | 25), .W26 = arm64.Register(REG_W | 26), .W27 = arm64.Register(REG_W | 27), + .W28 = arm64.Register(REG_W | 28), .W29 = arm64.Register(REG_W | 29), .W30 = arm64.Register(REG_W | 30), + .WZR = arm64.Register(REG_W | 31), + .WSP = arm64.Register(REG_WSP | 31), + + // ----------------------------------------------------------------------------- + // SIMD/FP register views (full Vn; scalar Bn/Hn/Sn/Dn/Qn are operand-type views) + // ----------------------------------------------------------------------------- + + .V0 = arm64.Register(REG_V | 0), .V1 = arm64.Register(REG_V | 1), .V2 = arm64.Register(REG_V | 2), .V3 = arm64.Register(REG_V | 3), + .V4 = arm64.Register(REG_V | 4), .V5 = arm64.Register(REG_V | 5), .V6 = arm64.Register(REG_V | 6), .V7 = arm64.Register(REG_V | 7), + .V8 = arm64.Register(REG_V | 8), .V9 = arm64.Register(REG_V | 9), .V10 = arm64.Register(REG_V | 10), .V11 = arm64.Register(REG_V | 11), + .V12 = arm64.Register(REG_V | 12), .V13 = arm64.Register(REG_V | 13), .V14 = arm64.Register(REG_V | 14), .V15 = arm64.Register(REG_V | 15), + .V16 = arm64.Register(REG_V | 16), .V17 = arm64.Register(REG_V | 17), .V18 = arm64.Register(REG_V | 18), .V19 = arm64.Register(REG_V | 19), + .V20 = arm64.Register(REG_V | 20), .V21 = arm64.Register(REG_V | 21), .V22 = arm64.Register(REG_V | 22), .V23 = arm64.Register(REG_V | 23), + .V24 = arm64.Register(REG_V | 24), .V25 = arm64.Register(REG_V | 25), .V26 = arm64.Register(REG_V | 26), .V27 = arm64.Register(REG_V | 27), + .V28 = arm64.Register(REG_V | 28), .V29 = arm64.Register(REG_V | 29), .V30 = arm64.Register(REG_V | 30), .V31 = arm64.Register(REG_V | 31), +} diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index b8174b428..47457c785 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -258,10 +258,10 @@ emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", - mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags)) + mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags, ops)) } -flags_lit :: proc(f: lib.Encoding_Flags) -> string { +flags_lit :: proc(f: lib.Encoding_Flags, ops: [4]lib.Operand_Type) -> string { parts: [dynamic]string defer delete(parts) if f.branch { append(&parts, "branch=true") } @@ -269,6 +269,15 @@ flags_lit :: proc(f: lib.Encoding_Flags) -> string { if f.writes_pc { append(&parts, "writes_pc=true") } if f.sets_flags { append(&parts, "sets_flags=true") } if f.is_64 { append(&parts, "is_64=true") } + encoding_operand_count: u8 = 0 + for op_type in ops { + if op_type == .NONE { break } + encoding_operand_count += 1 + } + if encoding_operand_count > 0 { + append(&parts, fmt.tprintf("explicit_count=%d", encoding_operand_count)) + } + return strings.join(parts[:], ", ", context.temp_allocator) } diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 0557a8304..53b0081e1 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -11,1867 +11,1867 @@ import lib "../.." DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true} }, - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {} }, - { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {} }, - { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {} }, - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {} }, - { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {} }, - { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {} }, - { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {} }, - { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, - { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, - { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, - { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, - { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, - { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, - { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, - { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {} }, - { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {} }, - { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {} }, - { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true} }, - { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true} }, - { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {} }, - { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, - { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, - { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, - { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, - { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, - { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true} }, - { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true} }, - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {} }, - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, 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{.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, - { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, - { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, - { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, - { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, - { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, - { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, - { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, - { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, - { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, - { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, - { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, - { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, - { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, - { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, - { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, - { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, - { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, - { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, - { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, - { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, - { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, - { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, - { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, - { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, - { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, - { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {} }, - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {} }, - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {} }, - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {} }, - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {} }, - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true} }, - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {} }, - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, 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.NEON, {} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {} }, - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {} }, - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {} }, - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {} }, - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, 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{.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {} }, - { .SMIN, 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{.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {} }, - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {} }, - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {} }, - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {} }, - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true} }, - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {} }, - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {} }, - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {} }, - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {} }, - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, - { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, - { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, - { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true} }, - { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {} }, - { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, - { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, - { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, - { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, - { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, - { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, - { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, - { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {} }, - { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true} }, - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {} }, - { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, - { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, - { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, + { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, 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{.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, 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{ .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, 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0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, @@ -1910,543 +1910,543 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, - { .BTI, {.IMM_2,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {} }, - { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {} }, - { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {} }, - { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {} }, - { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true} }, - { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE}, 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{.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {} }, - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {} }, - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {} }, - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {} }, - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {} }, - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {} }, - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {} }, - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {} }, - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {} }, - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {} }, - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {} }, - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {} }, - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {} }, - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {} }, + { .BR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, 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0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index c16426c73..4c78d0bac 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -10,406 +10,406 @@ import lib "../.." @(rodata) ENCODE_FORMS := [2436]lib.Encoding{ // .ADD - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, - { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {} }, - { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true} }, - { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, - { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .ADDS - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} }, - { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SUB - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true} }, - { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {} }, - { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true} }, - { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {} }, - { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .SUBS - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true} }, - { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .MOVZ - { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, + { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVN - { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {} }, - { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true} }, + { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVK - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .ADR - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, // .ADRP - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, // .AND - { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {} }, - { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true} }, - { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, - { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true} }, - { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {} }, + { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS - { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true} }, - { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, - { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true} }, - { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR - { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {} }, - { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true} }, - { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, - { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true} }, - { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {} }, + { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR - { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {} }, - { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true} }, - { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, - { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {} }, - { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true} }, - { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {} }, + { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC - { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {} }, - { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true} }, - { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {} }, + { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS - { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true} }, - { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true} }, - { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN - { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {} }, - { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {} }, - { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {} }, + { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON - { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {} }, - { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true} }, + { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, // .LSL - { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, - { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LSR - { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {} }, - { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ASR - { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true} }, + { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ROR - { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {} }, - { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true} }, - { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, - { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, + { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, // .UDIV - { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {} }, - { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .SDIV - { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {} }, - { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .MADD - { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {} }, - { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true} }, + { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .MSUB - { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {} }, - { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true} }, + { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMADDL - { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true} }, + { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMSUBL - { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true} }, + { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMADDL - { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true} }, + { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMSUBL - { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true} }, + { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMULH - { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .UMULH - { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .CLZ - { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {} }, - { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true} }, - { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .CLS - { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {} }, - { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true} }, - { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .RBIT - { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {} }, - { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true} }, - { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, - { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, + { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV - { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {} }, - { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, + { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 - { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {} }, - { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true} }, - { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, - { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, + { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV32 - { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true} }, - { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, - { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, - { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, - { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CSEL - { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {} }, - { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINC - { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {} }, - { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true} }, + { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINV - { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {} }, - { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSNEG - { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {} }, - { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true} }, + { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CCMP - { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CCMN - { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, - { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true} }, - { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, + { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .EXTR - { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true} }, + { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .B - { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true} }, + { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BL - { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true} }, + { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BR - { .BR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true} }, + { .BR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .BLR - { .BLR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true} }, + { .BLR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .RET - { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true} }, + { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .B_COND - { .B_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true} }, + { .B_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, // .CBZ - { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true} }, - { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true} }, + { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .CBNZ - { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true} }, - { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true} }, + { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .TBZ - { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true} }, + { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .TBNZ - { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true} }, + { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .LDR - { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {} }, - { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {} }, - { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {} }, - { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {} }, - { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {} }, - { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} }, - { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, - { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, - { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, - { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR - { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {} }, - { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {} }, - { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true} }, - { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {} }, - { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true} }, - { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {} }, - { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, - { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, - { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, - { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, - { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {} }, + { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB - { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {} }, - { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {} }, - { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {} }, - { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {} }, + { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRB - { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {} }, - { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {} }, - { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {} }, + { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSB - { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {} }, - { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {} }, - { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRH - { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {} }, - { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {} }, - { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {} }, - { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {} }, + { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRH - { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {} }, - { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {} }, - { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {} }, - { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {} }, + { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSH - { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {} }, - { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {} }, - { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRSW - { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDAR - { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLR - { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {} }, - { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .LDARB - { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {} }, + { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRB - { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDARH - { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {} }, + { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRH - { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {} }, + { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDXR - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, // .STXR - { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {} }, - { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .LDAXR - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, // .STLXR - { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {} }, - { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true} }, + { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .NOP { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, // .YIELD @@ -423,696 +423,696 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .SEVL { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, // .HINT - { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {} }, + { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, // .MRS - { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {} }, + { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, // .MSR - { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {} }, - { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {} }, + { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, + { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, // .ISB - { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {} }, + { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DSB - { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {} }, + { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DMB - { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {} }, + { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .SVC - { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true} }, + { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HVC - { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true} }, + { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .SMC - { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true} }, + { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .BRK - { .BRK, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true} }, + { .BRK, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HLT - { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true} }, + { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .ERET { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .FMOV - { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, - { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {} }, - { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {} }, - { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {} }, - { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {} }, + { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, // .FABS - { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {} }, - { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {} }, - { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {} }, - { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .FNEG - { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {} }, - { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {} }, - { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {} }, - { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .FSQRT - { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {} }, - { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {} }, - { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {} }, - { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .FADD - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FSUB - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FMUL - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FDIV - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FNMUL - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMADD - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FMSUB - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMADD - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMSUB - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FCMP - { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true} }, - { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true} }, - { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true} }, + { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCMPE - { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true} }, - { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true} }, - { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true} }, + { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCSEL - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, // .FMAX - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FMIN - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FMAXNM - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FMINNM - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FCVT - { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {} }, - { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {} }, - { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {} }, - { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {} }, - { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {} }, - { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {} }, + { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .SCVTF - { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {} }, - { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true} }, - { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true} }, - { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {} }, - { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {} }, - { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {} }, + { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .UCVTF - { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {} }, - { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true} }, - { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true} }, - { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {} }, - { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {} }, - { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {} }, + { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZS - { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {} }, - { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {} }, - { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {} }, - { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZU - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {} }, - { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {} }, - { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true} }, - { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {} }, - { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAS - { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {} }, - { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {} }, - { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {} }, - { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {} }, - { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {} }, - { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {} }, + { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAU - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {} }, - { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {} }, - { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {} }, - { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {} }, + { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNS - { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {} }, - { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {} }, - { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {} }, - { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNU - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {} }, - { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {} }, - { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {} }, - { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {} }, - { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {} }, - { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {} }, - { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPS - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {} }, - { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {} }, - { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPU - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {} }, - { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {} }, - { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {} }, - { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {} }, - { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMS - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMU - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {} }, - { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {} }, - { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {} }, - { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRINTA - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {} }, - { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {} }, - { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTI - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTM - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {} }, - { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {} }, - { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {} }, - { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTN - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {} }, - { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTP - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {} }, - { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {} }, - { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {} }, - { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTX - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {} }, - { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {} }, - { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {} }, - { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {} }, - { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTZ - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {} }, - { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {} }, - { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {} }, - { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {} }, - { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {} }, - { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .TST - { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true} }, - { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, - { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDUR - { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {} }, - { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {} }, - { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {} }, - { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {} }, + { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .STUR - { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {} }, - { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true} }, - { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {} }, - { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {} }, + { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .LDURB - { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {} }, + { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURB - { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {} }, + { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSB - { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {} }, + { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURH - { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {} }, + { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURH - { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {} }, + { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSH - { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {} }, + { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSW - { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDXP - { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {} }, - { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STXP - { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {} }, - { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true} }, + { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDAXP - { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {} }, - { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STLXP - { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {} }, - { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true} }, + { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDXRB - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, // .STXRB - { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {} }, + { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRB - { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, // .STLXRB - { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDXRH - { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, // .STXRH - { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {} }, + { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRH - { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, // .STLXRH - { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {} }, + { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAPR - { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {} }, - { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, // .LDAPRB - { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDAPRH - { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDADD - { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {} }, - { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDA - { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {} }, - { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDL - { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {} }, - { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDAL - { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLR - { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {} }, - { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRA - { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRL - { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRAL - { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEOR - { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {} }, - { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORA - { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {} }, - { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORL - { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {} }, - { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORAL - { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSET - { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {} }, - { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETA - { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETL - { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {} }, - { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETAL - { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAX - { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXA - { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXL - { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXAL - { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMIN - { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {} }, - { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINA - { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINL - { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINAL - { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAX - { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXA - { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXL - { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXAL - { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {} }, - { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMIN - { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINA - { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINL - { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINAL - { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {} }, - { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWP - { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {} }, - { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPA - { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {} }, - { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPL - { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {} }, - { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPAL - { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {} }, - { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true} }, + { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CAS - { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {} }, - { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASA - { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {} }, - { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASL - { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {} }, - { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASAL - { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {} }, - { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASB - { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {} }, + { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAB - { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLB - { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALB - { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASH - { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {} }, + { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAH - { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {} }, + { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLH - { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALH - { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {} }, + { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASP - { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {} }, - { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPA - { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {} }, - { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPL - { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {} }, - { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPAL - { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {} }, - { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .PACIA - { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true} }, + { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIB - { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true} }, + { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDA - { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true} }, + { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDB - { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true} }, + { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIZA - { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIZB - { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZA - { .PACDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .PACDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZB - { .PACDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .PACDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIA - { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true} }, + { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIB - { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true} }, + { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDA - { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true} }, + { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDB - { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true} }, + { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIZA - { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIZB - { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZA - { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZB - { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIASP { .PACIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, // .PACIBSP @@ -1130,11 +1130,11 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .AUTIB1716 { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, // .PACGA - { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true} }, + { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, // .XPACI - { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACD - { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true} }, + { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACLRI { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, // .RETAA @@ -1142,1878 +1142,1878 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .RETAB { .RETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BRAA - { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true} }, + { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAB - { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true} }, + { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAAZ - { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true} }, + { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BRABZ - { .BRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true} }, + { .BRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRAA - { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true} }, + { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAB - { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true} }, + { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAAZ - { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true} }, + { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRABZ - { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true} }, + { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .ERETAA { .ERETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .ERETAB { .ERETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BTI - { .BTI, {.IMM_2,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {} }, + { .BTI, {.IMM_2,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {explicit_count=1} }, // .IRG - { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true} }, + { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .ADDG - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .SUBG - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .GMI - { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true} }, + { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBP - { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true} }, + { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBPS - { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true} }, + { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true, explicit_count=3} }, // .LDG - { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true} }, + { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STG - { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .ST2G - { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true} }, + { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZG - { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZ2G - { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, // .LDGM - { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true} }, + { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGM - { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true} }, + { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZGM - { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true} }, + { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .CRC32B - { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {} }, + { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32H - { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {} }, + { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32W - { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {} }, + { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32X - { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true} }, + { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .CRC32CB - { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {} }, + { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CH - { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {} }, + { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CW - { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {} }, + { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CX - { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, + { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .AESE - { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, + { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, // .AESD - { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {} }, + { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, // .AESMC - { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {} }, - { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {} }, + { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, // .AESIMC - { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {} }, - { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {} }, + { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, // .SHA1H - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {} }, + { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA1C - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1P - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1M - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU0 - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU1 - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {} }, + { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256H - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256H2 - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256SU0 - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {} }, + { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256SU1 - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H2 - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512SU0 - { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {} }, + { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA512SU1 - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .EOR3 - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .BCAX - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .RAX1 - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .XAR - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, // .SM3PARTW1 - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3PARTW2 - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3SS1 - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, // .SM3TT1A - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, // .SM3TT1B - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, // .SM3TT2A - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, // .SM3TT2B - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, // .SM4E - { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, + { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SM4EKEY - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL2 - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {} }, - { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .BFCVT - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {} }, - { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, + { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMMLA - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALB - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALT - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFCVTN - { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, + { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .BFCVTN2 - { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, + { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .MUL - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .MLA - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MLS - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .NEG - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, // .ABS - { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SHADD - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHADD - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHSUB - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHSUB - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SRHADD - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URHADD - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQADD - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQADD - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SQSUB - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQSUB - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SMAX - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .UMAX - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .SMIN - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .UMIN - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .SABD - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .UABD - { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .SABA - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UABA - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {} }, + { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDP - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {} }, + { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDV - { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {} }, - { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {} }, + { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLP - { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {} }, - { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {} }, - { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {} }, - { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {} }, - { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {} }, - { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {} }, + { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLP - { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {} }, - { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {} }, + { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADALP - { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {} }, - { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {} }, - { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {} }, - { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {} }, - { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {} }, - { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {} }, + { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADALP - { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {} }, - { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {} }, + { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLV - { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {} }, - { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {} }, - { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {} }, - { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {} }, - { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {} }, + { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLV - { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {} }, - { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {} }, + { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXV - { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {} }, - { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {} }, + { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMAXV - { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {} }, - { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {} }, - { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {} }, - { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {} }, - { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {} }, + { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMINV - { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {} }, - { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {} }, - { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {} }, - { .SMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {} }, - { .SMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {} }, + { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMINV - { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {} }, - { .UMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {} }, - { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {} }, - { .UMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {} }, - { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {} }, + { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXP - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {} }, + { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMAXP - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {} }, - { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {} }, - { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMINP - { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {} }, - { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {} }, - { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {} }, + { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMINP - { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {} }, - { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {} }, - { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {} }, - { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {} }, + { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL - { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {} }, - { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {} }, - { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {} }, + { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL2 - { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {} }, - { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {} }, - { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {} }, + { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL - { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {} }, - { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {} }, - { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {} }, + { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL2 - { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {} }, - { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {} }, + { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL - { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {} }, - { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {} }, + { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL2 - { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {} }, - { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {} }, + { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL - { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {} }, - { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {} }, - { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {} }, + { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL2 - { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {} }, - { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {} }, - { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {} }, + { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW - { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {} }, - { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {} }, - { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW2 - { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {} }, - { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {} }, - { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW - { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {} }, - { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW2 - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {} }, - { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {} }, - { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW - { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {} }, - { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {} }, - { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW2 - { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {} }, - { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {} }, - { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW - { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {} }, - { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {} }, - { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW2 - { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {} }, - { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {} }, - { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN - { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {} }, - { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {} }, - { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN2 - { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {} }, - { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {} }, - { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN - { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {} }, - { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {} }, - { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN2 - { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {} }, - { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {} }, - { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN - { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {} }, - { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {} }, - { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN2 - { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {} }, - { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {} }, - { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN - { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {} }, - { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {} }, - { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN2 - { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {} }, - { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {} }, - { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .XTN - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, - { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, - { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .XTN2 - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, - { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, - { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN - { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, - { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, - { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN2 - { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, - { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, - { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN - { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN2 - { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, - { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN - { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {} }, - { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {} }, - { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN2 - { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {} }, - { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {} }, - { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMULL - { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMULL2 - { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL - { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL2 - { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL - { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {} }, + { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL2 - { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {} }, + { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL - { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {} }, - { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {} }, - { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {} }, + { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL2 - { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {} }, - { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {} }, - { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {} }, + { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL - { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {} }, + { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL2 - { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {} }, + { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL - { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {} }, + { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL2 - { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {} }, + { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL - { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {} }, - { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {} }, + { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL2 - { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {} }, - { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {} }, + { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL - { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL2 - { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL - { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL2 - { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULH - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {} }, - { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {} }, - { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {} }, - { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRDMULH - { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {} }, - { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {} }, - { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {} }, - { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {} }, + { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SDOT - { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {} }, + { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .UDOT - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {} }, - { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .USDOT - { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {} }, - { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {} }, + { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .FMLA - { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMLS - { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMULX - { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {} }, + { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXP - { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {} }, + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINP - { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {} }, + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXNMP - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINNMP - { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {} }, + { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXV - { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {} }, - { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {} }, - { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {} }, + { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINV - { .FMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {} }, - { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {} }, - { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {} }, + { .FMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMAXNMV - { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {} }, - { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {} }, - { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {} }, + { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINNMV - { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {} }, - { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {} }, - { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {} }, + { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPE - { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {} }, - { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {} }, - { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {} }, - { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {} }, - { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {} }, + { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRSQRTE - { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {} }, - { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {} }, - { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {} }, - { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {} }, - { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {} }, + { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPS - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRSQRTS - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {} }, - { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRECPX - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {} }, - { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FADDP - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {} }, - { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FCVTL - { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {} }, - { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {} }, + { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTL2 - { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {} }, - { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {} }, + { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN - { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {} }, - { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {} }, + { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN2 - { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {} }, - { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {} }, + { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN - { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {} }, + { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN2 - { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {} }, + { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCMEQ - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGE - { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGT - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMLE - { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {} }, - { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {} }, - { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {} }, - { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {} }, - { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FCMLT - { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {} }, - { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {} }, - { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {} }, - { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {} }, - { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true} }, + { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FACGE - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FACGT - { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {} }, + { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .CMEQ - { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {} }, + { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGE - { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {} }, + { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGT - { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {} }, - { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {} }, + { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHI - { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {} }, + { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHS - { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMLE - { .CMLE, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {} }, - { .CMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {} }, + { .CMLE, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMLT - { .CMLT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {} }, - { .CMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {} }, + { .CMLT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMTST - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MVN - { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, - { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .BIT - { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {} }, + { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BIF - { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} }, + { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BSL - { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .SHL - { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {} }, - { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {} }, - { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {} }, - { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {} }, + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHL - { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {} }, - { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {} }, - { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {} }, + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHLU - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {} }, - { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {} }, - { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHL - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URSHL - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHR - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {} }, - { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USHR - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {} }, - { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {} }, - { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSRA - { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {} }, - { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {} }, + { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USRA - { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {} }, - { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {} }, - { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {} }, - { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {} }, + { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHR - { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {} }, - { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {} }, - { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {} }, + { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSHR - { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {} }, - { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {} }, - { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {} }, + { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSRA - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {} }, - { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {} }, - { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSRA - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {} }, - { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {} }, + { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHL - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHL - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SLI - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRI - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHLL - { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {} }, - { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {} }, + { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHLL2 - { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {} }, - { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {} }, + { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL - { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {} }, - { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {} }, + { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL2 - { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {} }, - { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {} }, + { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SXTL - { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {} }, - { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {} }, - { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {} }, + { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SXTL2 - { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {} }, - { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {} }, - { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {} }, + { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL - { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {} }, + { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL2 - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {} }, - { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SHRN - { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {} }, - { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {} }, + { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHRN2 - { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {} }, - { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {} }, + { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN - { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {} }, - { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {} }, + { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN2 - { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {} }, - { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {} }, + { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN - { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {} }, + { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN2 - { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {} }, + { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN - { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {} }, - { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {} }, + { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN2 - { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {} }, + { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN - { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {} }, + { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN2 - { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {} }, + { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN - { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {} }, + { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN2 - { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {} }, + { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN - { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {} }, + { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN2 - { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {} }, + { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN - { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {} }, + { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN2 - { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {} }, + { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .DUP - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {} }, - { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {} }, - { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {} }, - { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {} }, - { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {} }, - { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .INS - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, // .MOV - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true} }, - { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {} }, - { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {} }, - { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {} }, - { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, // .EXT - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .TBX - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .ZIP1 - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT - { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, - { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {} }, + { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 - { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CNT - { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .URECPE - { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .URSQRTE - { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .MOVI - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .MVNI - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .LD1 - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {} }, - { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {} }, - { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD2 - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {} }, - { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {} }, - { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {} }, - { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD3 - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {} }, - { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {} }, - { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {} }, - { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD4 - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {} }, - { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {} }, - { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {} }, - { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST1 - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {} }, - { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {} }, - { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {} }, - { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST2 - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {} }, - { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {} }, - { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {} }, - { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {} }, - { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST3 - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {} }, - { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {} }, - { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {} }, - { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {} }, - { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST4 - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {} }, - { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {} }, - { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {} }, - { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {} }, - { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD1R - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD2R - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD3R - { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD4R - { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SUBR - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .ASRR - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSLR - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSRR - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FTSMUL - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FSUBR - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIVR - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLA - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLS - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {} }, + { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {} }, + { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {} }, + { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true} }, + { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true} }, + { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE - { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, + { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES - { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, + { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, // .PFALSE - { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {} }, + { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {} }, + { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {} }, + { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {} }, + { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {} }, + { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true} }, + { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {} }, + { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {} }, + { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {} }, + { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR - { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {} }, + { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR - { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {} }, + { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPNE - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGE - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGT - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLE - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLT - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHI - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHS - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLO - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLS - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .FCMNE - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMUO - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .INSR - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .CPY - { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .COMPACT - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true} }, - { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {} }, - { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {} }, - { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {} }, - { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {} }, - { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true} }, - { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true} }, - { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {} }, - { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {} }, - { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {} }, - { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {} }, - { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {} }, - { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {} }, - { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true} }, - { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true} }, - { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LDFF1B - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1H - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1W - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1D - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELE - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELO - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELS - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true} }, + { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .SQRDMLAH - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SQRDMLSH - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLB - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLT - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLB - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLT - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .TBL2 - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .MATCH - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .NMATCH - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .HISTCNT - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, // .HISTSEG - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .SMSTART { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, // .SMSTOP { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, // .ADDHA - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {} }, + { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ADDVA - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {} }, + { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ZERO - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {} }, + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, // .FMOPA - { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {} }, + { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, // .FMOPS - { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, + { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, // .BFMOPA - { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, + { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, // .BFMOPS - { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, + { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, // .SMOPA - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, // .SMOPS - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, // .UMOPA - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, // .UMOPS - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, // .USMOPA - { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, + { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, // .SUMOPA - { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, + { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, // .LD1Q - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {explicit_count=3} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, // .FCADD - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, // .PRFB - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFH - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFW - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFD - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1B - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1H - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1W - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1D - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .STNT1B - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1H - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1W - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1D - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SPLICE - { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, // .BSL1N - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .BSL2N - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .NBSL - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .PMUL - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .BFCVTNT - { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .LDRAA - { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true} }, - { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .LDRAB - { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true} }, - { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true} }, + { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .TSTART - { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TCOMMIT { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, // .TCANCEL - { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {} }, + { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, // .TTEST - { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFET - { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFIT - { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .BC_COND - { .BC_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true} }, + { .BC_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, // .UXTB - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTH - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTW - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .SXTB - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTH - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTW - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true} }, + { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .ADC - { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ADCS - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SBC - { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .SBCS - { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, - { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .NGC - { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .NGCS - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDAPUR - { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {} }, - { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .STLUR - { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {} }, - { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true} }, + { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDAPURB - { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {} }, + { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURB - { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {} }, + { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURH - { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {} }, + { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURH - { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {} }, + { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSB - { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSH - { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true} }, - { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, + { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSW - { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .BFADD - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFSUB - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMUL - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMLA - { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {} }, + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .BFMLS - { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {} }, + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .SB { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, // .CSDB @@ -3031,171 +3031,171 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .BTI_JC { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMAXNM - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {explicit_count=4} }, // .BFMINNM - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {explicit_count=4} }, // .LUTI2 - { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {} }, + { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, // .LUTI4 - { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {} }, + { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, // .ZIP - { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {} }, - { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {} }, + { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, // .UZP - { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {} }, - { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {} }, + { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, // .TLBI_RPALOS - { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_RPAOS - { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1A - { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIPAPA - { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIGDPAPA - { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_PAALL { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDY - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STX - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STY - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZ - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZ - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZI - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZI - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRX - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRY - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA64 - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS64 - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA32 - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS32 - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MAC16 - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA16 - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS16 - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_SET { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, // .AMX_CLR { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, // .AMX_VECINT - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_VECFP - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATINT - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATFP - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_GENLUT - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true} }, + { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .CPYP - { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYM - { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYE - { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFP - { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFM - { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFE - { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true} }, + { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETP - { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true} }, + { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETM - { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true} }, + { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETE - { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true} }, + { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .DC_IVAC - { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ISW - { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CSW - { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CISW - { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ZVA - { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAC - { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAU - { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIVAC - { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .IC_IALLUIS { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, // .IC_IALLU { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, // .IC_IVAU - { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1R - { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1W - { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0R - { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0W - { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2R - { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2W - { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3R - { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3W - { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1R - { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1W - { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0R - { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0W - { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VMALLE1 { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VMALLE1IS { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VAE1 - { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAE1IS - { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1 - { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1IS - { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1 - { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1IS - { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1 - { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1IS - { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1 - { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1IS - { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true} }, + { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ALLE1 { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE1IS @@ -3209,27 +3209,27 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .TLBI_ALLE3IS { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, // .PRFM - { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true} }, - { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true} }, + { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, // .PRFUM - { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .NEGS - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, - { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMP - { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMN - { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true} }, + { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 0d8f5415c43875fc41b054ff11958565ecf7da08..f66570cb49212d2befd9ab327b2e4bceb593bfb5 100644 GIT binary patch literal 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destination @@ -2806,6 +2806,8 @@ gb_internal void check_asm_template_from_entity(CheckerContext *c, Entity *e, De check_asm_template(&g_asm_amd64, c, e, d); } else if (build_context.metrics.arch == TargetArch_riscv64) { check_asm_template(&g_asm_riscv, c, e, d); + } else if (build_context.metrics.arch == TargetArch_arm64) { + check_asm_template(&g_asm_arm64, c, e, d); } else { error(e->token, "asm templates are not currently supported for this target"); } From 3bb6254857a6bd5ab7348d3e9dd29a6bc8b6f011 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 12:01:10 +0100 Subject: [PATCH 17/89] asm: Support `v[idx]` operand _syntax_ --- src/parser.cpp | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/src/parser.cpp b/src/parser.cpp index 43fbea7c9..bfb25cf99 100644 --- a/src/parser.cpp +++ b/src/parser.cpp @@ -2468,6 +2468,7 @@ gb_internal Ast *parse_asm_register(AstFile *f) { return reg; } gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { + Ast *operand = nullptr; switch (f->curr_token.kind) { case Token_Period: { @@ -2479,9 +2480,11 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { return label_decl; } case Token_Ident: - return parse_ident(f); + operand = parse_ident(f); + break; case Token_Mod: - return parse_asm_register(f); + operand = parse_asm_register(f); + break; case Token_Integer: case Token_Float: case Token_Rune: @@ -2572,9 +2575,18 @@ gb_internal Ast *parse_asm_operand(AstFile *f, bool allow_memory_operand) { break; } - syntax_error(f->curr_token, "Invalid asm operand, found '%.*s'", LIT(f->curr_token.string)); - advance_token(f); - return nullptr; + if (operand == nullptr) { + syntax_error(f->curr_token, "Invalid asm operand, found '%.*s'", LIT(f->curr_token.string)); + advance_token(f); + } else if (f->curr_token.kind == Token_OpenBracket) { + f->expr_level++; + Token open = expect_token(f, Token_OpenBracket); + Ast *index = parse_asm_operand(f, false); + Token close = expect_token(f, Token_CloseBracket); + f->expr_level--; + operand = ast_index_expr(f, operand, index, open, close); + } + return operand; } gb_internal Slice parse_asm_operands(AstFile *f) { @@ -2839,10 +2851,11 @@ gb_internal Ast *parse_asm_template(AstFile *f) { } if (build_context.metrics.arch == TargetArch_amd64 || - build_context.metrics.arch == TargetArch_riscv64) { + build_context.metrics.arch == TargetArch_riscv64 || + build_context.metrics.arch == TargetArch_arm64) { // okay } else { - syntax_error(token, "asm templates are currently only supported on -target:*_amd64 or -target:*_riscv64"); + syntax_error(token, "asm templates are currently only supported on -target:*_amd64 or -target:*_riscv64 or -target:*_arm64"); } Ast *asm_template = alloc_ast_node(f, Ast_AsmTemplate); From d8cea6ceb075fc7259e844a1952f33fab516dc43 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 13:02:10 +0100 Subject: [PATCH 18/89] asm: semantic checking for `v[idx]` (arm style) --- .../arm64/tablegen/cpp-compiler/cpp-gen.odin | 6 +- src/asm_tables_arm64.cpp | 2450 +++++++++++++++++ src/check_asm.cpp | 101 +- 3 files changed, 2531 insertions(+), 26 deletions(-) create mode 100644 src/asm_tables_arm64.cpp diff --git a/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin b/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin index dc38c3dd2..5c4d5c97c 100644 --- a/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin +++ b/core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin @@ -439,7 +439,7 @@ main :: proc() { } strings.write_string(&sb, "\n\n") { - strings.write_string(&sb, "\tenum Feature : u16 {\n") + strings.write_string(&sb, "\tenum Feature : u8 {\n") defer strings.write_string(&sb, "\t};\n") for op in Feature { fmt.sbprintf(&sb, "\t\tF_%s,\n", op) @@ -450,7 +450,7 @@ main :: proc() { strings.write_string(&sb, "\ttypedef u8 EncodingFlags; // cannot use a C++ bit field to due lack of portability\n") strings.write_string(&sb, "\n") { - defer strings.write_string(&sb, "\tGB_STATIC_ASSERT(gb_size_of(Encoding) == 21);\n") + defer strings.write_string(&sb, "\tGB_STATIC_ASSERT(gb_size_of(Encoding) == 20);\n") strings.write_string(&sb, "\t#pragma pack(push, 1)\n") defer strings.write_string(&sb, "\t#pragma pack(pop)\n") @@ -636,6 +636,7 @@ main :: proc() { // SME ZA tiles (ZA0.B .. ZAn.Q) โ€” register-like tile operands. case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S: case OP_ZA_TILE_D: case OP_ZA_TILE_Q: + case OP_SYS_REG: // MRS/MSR system-register name -> 16-bit field (cf. riscv CSR) return AsmOperand_Register; // ---- Immediates (numeric literals and immediate-encoded selectors) ---- @@ -651,7 +652,6 @@ main :: proc() { case OP_VEC_SHIFT: case OP_VEC_INDEX: // Enum-like tokens that encode into an immediate field: case OP_COND: // condition code (EQ/NE/...) -> 4-bit field - case OP_SYS_REG: // MRS/MSR system-register name -> 16-bit field (cf. riscv CSR) case OP_SME_PATTERN: case OP_SVE_PATTERN: // pattern / tile-list selectors // JUDGMENT CALL: the following are register/tile-slice constructs // syntactically, but this table models each as a single packed immediate diff --git a/src/asm_tables_arm64.cpp b/src/asm_tables_arm64.cpp new file mode 100644 index 000000000..9ddafd9d2 --- /dev/null +++ b/src/asm_tables_arm64.cpp @@ -0,0 +1,2450 @@ +// ============================================================================= +// GENERATED FILE - DO NOT EDIT +// ============================================================================= +// +// Produces a C++ equivalent of the encoding table from core:rexcode written in Odin +// odin run tablegen # Stage A: ENCODING_TABLE -> generated/ + this file +// odin run tablegen/generated # Stage B: typed Odin literals -> tables/*.bin +// odin run tablegen/cpp-compiler # Stage C: typed Odin literals -> C++ literals +// + + +struct Asm_arm64 { + enum Mnemonic : u16 { + M_INVALID, M_ADD, M_ADDS, M_SUB, M_SUBS, M_MOVZ, M_MOVN, M_MOVK, M_ADR, M_ADRP, M_AND, M_ANDS, M_ORR, M_EOR, M_BIC, M_BICS, + M_ORN, M_EON, M_LSL, M_LSR, M_ASR, M_ROR, M_UDIV, M_SDIV, M_MADD, M_MSUB, M_SMADDL, M_SMSUBL, M_UMADDL, M_UMSUBL, M_SMULH, M_UMULH, + M_CLZ, M_CLS, M_RBIT, M_REV, M_REV16, M_REV32, M_CSEL, M_CSINC, M_CSINV, M_CSNEG, M_CCMP, M_CCMN, M_EXTR, M_B, M_BL, M_BR, + M_BLR, M_RET, M_B_COND, M_CBZ, M_CBNZ, M_TBZ, M_TBNZ, M_LDR, M_STR, M_LDRB, M_STRB, M_LDRSB, M_LDRH, M_STRH, M_LDRSH, M_LDRSW, + M_LDP, M_STP, M_LDPSW, M_LDAR, M_STLR, M_LDARB, M_STLRB, M_LDARH, M_STLRH, M_LDXR, M_STXR, M_LDAXR, M_STLXR, M_NOP, M_YIELD, M_WFE, + M_WFI, M_SEV, M_SEVL, M_HINT, M_MRS, M_MSR, M_ISB, M_DSB, M_DMB, M_SVC, M_HVC, M_SMC, M_BRK, M_HLT, M_ERET, M_FMOV, + M_FABS, M_FNEG, M_FSQRT, M_FADD, M_FSUB, M_FMUL, M_FDIV, M_FNMUL, M_FMADD, M_FMSUB, M_FNMADD, M_FNMSUB, M_FCMP, M_FCMPE, M_FCSEL, M_FMAX, + M_FMIN, M_FMAXNM, M_FMINNM, M_FCVT, M_SCVTF, M_UCVTF, M_FCVTZS, M_FCVTZU, M_FCVTAS, M_FCVTAU, M_FCVTNS, M_FCVTNU, M_FCVTPS, M_FCVTPU, M_FCVTMS, M_FCVTMU, + M_FRINTA, M_FRINTI, M_FRINTM, M_FRINTN, M_FRINTP, M_FRINTX, M_FRINTZ, M_TST, M_LDUR, M_STUR, M_LDURB, M_STURB, M_LDURSB, M_LDURH, M_STURH, M_LDURSH, + M_LDURSW, M_LDNP, M_STNP, M_LDXP, M_STXP, M_LDAXP, M_STLXP, M_LDXRB, M_STXRB, M_LDAXRB, M_STLXRB, M_LDXRH, M_STXRH, M_LDAXRH, M_STLXRH, M_LDAPR, + M_LDAPRB, M_LDAPRH, M_LDADD, M_LDADDA, M_LDADDL, M_LDADDAL, M_LDCLR, M_LDCLRA, M_LDCLRL, M_LDCLRAL, M_LDEOR, M_LDEORA, M_LDEORL, M_LDEORAL, M_LDSET, M_LDSETA, + M_LDSETL, M_LDSETAL, M_LDSMAX, M_LDSMAXA, M_LDSMAXL, M_LDSMAXAL, M_LDSMIN, M_LDSMINA, M_LDSMINL, M_LDSMINAL, M_LDUMAX, M_LDUMAXA, M_LDUMAXL, M_LDUMAXAL, M_LDUMIN, M_LDUMINA, + M_LDUMINL, M_LDUMINAL, M_SWP, M_SWPA, M_SWPL, M_SWPAL, M_CAS, M_CASA, M_CASL, M_CASAL, M_CASB, M_CASAB, M_CASLB, M_CASALB, M_CASH, M_CASAH, + M_CASLH, M_CASALH, M_CASP, M_CASPA, M_CASPL, M_CASPAL, M_PACIA, M_PACIB, M_PACDA, M_PACDB, M_PACIZA, M_PACIZB, M_PACDZA, M_PACDZB, M_AUTIA, M_AUTIB, + M_AUTDA, M_AUTDB, M_AUTIZA, M_AUTIZB, M_AUTDZA, M_AUTDZB, M_PACIASP, M_PACIBSP, M_AUTIASP, M_AUTIBSP, M_PACIA1716, M_PACIB1716, M_AUTIA1716, M_AUTIB1716, M_PACGA, M_XPACI, + M_XPACD, M_XPACLRI, M_RETAA, M_RETAB, M_BRAA, M_BRAB, M_BRAAZ, M_BRABZ, M_BLRAA, M_BLRAB, M_BLRAAZ, M_BLRABZ, M_ERETAA, M_ERETAB, M_BTI, M_IRG, + M_ADDG, M_SUBG, M_GMI, M_SUBP, M_SUBPS, M_LDG, M_STG, M_ST2G, M_STZG, M_STZ2G, M_STGP, M_LDGM, M_STGM, M_STZGM, M_CRC32B, M_CRC32H, + M_CRC32W, M_CRC32X, M_CRC32CB, M_CRC32CH, M_CRC32CW, M_CRC32CX, M_AESE, M_AESD, M_AESMC, M_AESIMC, M_SHA1H, M_SHA1C, M_SHA1P, M_SHA1M, M_SHA1SU0, M_SHA1SU1, + M_SHA256H, M_SHA256H2, M_SHA256SU0, M_SHA256SU1, M_SHA512H, M_SHA512H2, M_SHA512SU0, M_SHA512SU1, M_EOR3, M_BCAX, M_RAX1, M_XAR, M_SM3PARTW1, M_SM3PARTW2, M_SM3SS1, M_SM3TT1A, + M_SM3TT1B, M_SM3TT2A, M_SM3TT2B, M_SM4E, M_SM4EKEY, M_PMULL, M_PMULL2, M_BFCVT, M_BFDOT, M_BFMMLA, M_BFMLALB, M_BFMLALT, M_BFCVTN, M_BFCVTN2, M_MUL, M_MLA, + M_MLS, M_NEG, M_ABS, M_SHADD, M_UHADD, M_SHSUB, M_UHSUB, M_SRHADD, M_URHADD, M_SQADD, M_UQADD, M_SQSUB, M_UQSUB, M_SMAX, M_UMAX, M_SMIN, + M_UMIN, M_SABD, M_UABD, M_SABA, M_UABA, M_ADDP, M_ADDV, M_SADDLP, M_UADDLP, M_SADALP, M_UADALP, M_SADDLV, M_UADDLV, M_SMAXV, M_UMAXV, M_SMINV, + M_UMINV, M_SMAXP, M_UMAXP, M_SMINP, M_UMINP, M_SADDL, M_SADDL2, M_UADDL, M_UADDL2, M_SSUBL, M_SSUBL2, M_USUBL, M_USUBL2, M_SADDW, M_SADDW2, M_UADDW, + M_UADDW2, M_SSUBW, M_SSUBW2, M_USUBW, M_USUBW2, M_RADDHN, M_RADDHN2, M_RSUBHN, M_RSUBHN2, M_ADDHN, M_ADDHN2, M_SUBHN, M_SUBHN2, M_XTN, M_XTN2, M_SQXTN, + M_SQXTN2, M_UQXTN, M_UQXTN2, M_SQXTUN, M_SQXTUN2, M_SMULL, M_SMULL2, M_UMULL, M_UMULL2, M_SMLAL, M_SMLAL2, M_UMLAL, M_UMLAL2, M_SMLSL, M_SMLSL2, M_UMLSL, + M_UMLSL2, M_SQDMULL, M_SQDMULL2, M_SQDMLAL, M_SQDMLAL2, M_SQDMLSL, M_SQDMLSL2, M_SQDMULH, M_SQRDMULH, M_SDOT, M_UDOT, M_USDOT, M_FMLA, M_FMLS, M_FMULX, M_FMAXP, + M_FMINP, M_FMAXNMP, M_FMINNMP, M_FMAXV, M_FMINV, M_FMAXNMV, M_FMINNMV, M_FRECPE, M_FRSQRTE, M_FRECPS, M_FRSQRTS, M_FRECPX, M_FADDP, M_FCVTL, M_FCVTL2, M_FCVTN, + M_FCVTN2, M_FCVTXN, M_FCVTXN2, M_FCMEQ, M_FCMGE, M_FCMGT, M_FCMLE, M_FCMLT, M_FACGE, M_FACGT, M_CMEQ, M_CMGE, M_CMGT, M_CMHI, M_CMHS, M_CMLE, + M_CMLT, M_CMTST, M_MVN, M_BIT, M_BIF, M_BSL, M_SHL, M_SQSHL, M_SQSHLU, M_SRSHL, M_URSHL, M_SSHR, M_USHR, M_SSRA, M_USRA, M_SRSHR, + M_URSHR, M_SRSRA, M_URSRA, M_SSHL, M_USHL, M_SLI, M_SRI, M_SSHLL, M_SSHLL2, M_USHLL, M_USHLL2, M_SXTL, M_SXTL2, M_UXTL, M_UXTL2, M_SHRN, + M_SHRN2, M_RSHRN, M_RSHRN2, M_SQSHRN, M_SQSHRN2, M_UQSHRN, M_UQSHRN2, M_SQRSHRN, M_SQRSHRN2, M_UQRSHRN, M_UQRSHRN2, M_SQSHRUN, M_SQSHRUN2, M_SQRSHRUN, M_SQRSHRUN2, M_DUP, + M_INS, M_MOV, M_EXT, M_TBL, M_TBX, M_ZIP1, M_ZIP2, M_UZP1, M_UZP2, M_TRN1, M_TRN2, M_NOT, M_REV64, M_CNT, M_URECPE, M_URSQRTE, + M_MOVI, M_MVNI, M_LD1, M_LD2, M_LD3, M_LD4, M_ST1, M_ST2, M_ST3, M_ST4, M_LD1R, M_LD2R, M_LD3R, M_LD4R, M_SUBR, M_ASRR, + M_LSLR, M_LSRR, M_FTSMUL, M_FSUBR, M_FDIVR, M_FNMLA, M_FNMLS, M_NAND, M_NOR, M_SEL, M_ORRS, M_EORS, M_NANDS, M_NORS, M_ORNS, M_MOVS, + M_PTRUE, M_PTRUES, M_PFALSE, M_PFIRST, M_PNEXT, M_BRKA, M_BRKB, M_BRKAS, M_BRKBS, M_BRKPA, M_BRKPB, M_BRKN, M_RDFFR, M_WRFFR, M_SETFFR, M_CMPEQ, + M_CMPNE, M_CMPGE, M_CMPGT, M_CMPLE, M_CMPLT, M_CMPHI, M_CMPHS, M_CMPLO, M_CMPLS, M_FCMNE, M_FCMUO, M_INSR, M_CPY, M_COMPACT, M_LD1B, M_LD1H, + M_LD1W, M_LD1D, M_LD1SB, M_LD1SH, M_LD1SW, M_ST1B, M_ST1H, M_ST1W, M_ST1D, M_LDFF1B, M_LDFF1H, M_LDFF1W, M_LDFF1D, M_WHILEGE, M_WHILEGT, M_WHILELE, + M_WHILELT, M_WHILEHI, M_WHILEHS, M_WHILELO, M_WHILELS, M_SQRDMLAH, M_SQRDMLSH, M_ADCLB, M_ADCLT, M_SBCLB, M_SBCLT, M_TBL2, M_MATCH, M_NMATCH, M_HISTCNT, M_HISTSEG, + M_SMSTART, M_SMSTOP, M_RDSVL, M_ADDHA, M_ADDVA, M_ZERO, M_FMOPA, M_FMOPS, M_BFMOPA, M_BFMOPS, M_SMOPA, M_SMOPS, M_UMOPA, M_UMOPS, M_USMOPA, M_SUMOPA, + M_LD1Q, M_ST1Q, M_MOVA, M_FCMLA, M_FCADD, M_PRFB, M_PRFH, M_PRFW, M_PRFD, M_LDNT1B, M_LDNT1H, M_LDNT1W, M_LDNT1D, M_STNT1B, M_STNT1H, M_STNT1W, + M_STNT1D, M_SPLICE, M_INDEX, M_BSL1N, M_BSL2N, M_NBSL, M_PMUL, M_PMULLB, M_PMULLT, M_BFCVTNT, M_LDRAA, M_LDRAB, M_TSTART, M_TCOMMIT, M_TCANCEL, M_TTEST, + M_WFET, M_WFIT, M_BC_COND, M_UXTB, M_UXTH, M_UXTW, M_SXTB, M_SXTH, M_SXTW, M_ADC, M_ADCS, M_SBC, M_SBCS, M_NGC, M_NGCS, M_LDAPUR, + M_STLUR, M_LDAPURB, M_STLURB, M_LDAPURH, M_STLURH, M_LDAPURSB, M_LDAPURSH, M_LDAPURSW, M_BFADD, M_BFSUB, M_BFMUL, M_BFMLA, M_BFMLS, M_SB, M_CSDB, M_DGH, + M_PSB_CSYNC, M_TSB_CSYNC, M_BTI_J, M_BTI_C, M_BTI_JC, M_BFCLAMP, M_BFMAXNM, M_BFMINNM, M_LUTI2, M_LUTI4, M_ZIP, M_UZP, M_TLBI_RPALOS, M_TLBI_RPAOS, M_AT_S1E1A, M_DC_CIPAPA, + M_DC_CIGDPAPA, M_TLBI_PAALL, M_TLBI_PAALLOS, M_AMX_LDX, M_AMX_LDY, M_AMX_STX, M_AMX_STY, M_AMX_LDZ, M_AMX_STZ, M_AMX_LDZI, M_AMX_STZI, M_AMX_EXTRX, M_AMX_EXTRY, M_AMX_FMA64, M_AMX_FMS64, M_AMX_FMA32, + M_AMX_FMS32, M_AMX_MAC16, M_AMX_FMA16, M_AMX_FMS16, M_AMX_SET, M_AMX_CLR, M_AMX_VECINT, M_AMX_VECFP, M_AMX_MATINT, M_AMX_MATFP, M_AMX_GENLUT, M_CPYP, M_CPYM, M_CPYE, M_CPYFP, M_CPYFM, + M_CPYFE, M_SETP, M_SETM, M_SETE, M_DC_IVAC, M_DC_ISW, M_DC_CSW, M_DC_CISW, M_DC_ZVA, M_DC_CVAC, M_DC_CVAU, M_DC_CIVAC, M_IC_IALLUIS, M_IC_IALLU, M_IC_IVAU, M_AT_S1E1R, + M_AT_S1E1W, M_AT_S1E0R, M_AT_S1E0W, M_AT_S1E2R, M_AT_S1E2W, M_AT_S1E3R, M_AT_S1E3W, M_AT_S12E1R, M_AT_S12E1W, M_AT_S12E0R, M_AT_S12E0W, M_TLBI_VMALLE1, M_TLBI_VMALLE1IS, M_TLBI_VAE1, M_TLBI_VAE1IS, M_TLBI_ASIDE1, + M_TLBI_ASIDE1IS, M_TLBI_VAAE1, M_TLBI_VAAE1IS, M_TLBI_VALE1, M_TLBI_VALE1IS, M_TLBI_VAALE1, M_TLBI_VAALE1IS, M_TLBI_ALLE1, M_TLBI_ALLE1IS, M_TLBI_ALLE2, M_TLBI_ALLE2IS, M_TLBI_ALLE3, M_TLBI_ALLE3IS, M_PRFM, M_PRFUM, M_NEGS, + M_CMP, M_CMN, + + MNEMONIC_COUNT + }; + static String const mnemonic_strings[MNEMONIC_COUNT]; + + enum Prefix : u8 { + PREFIX_INVALID, + PREFIX_COUNT + }; + enum PrefixKind : u8 { PrefixKind_None }; + + + static const u16 REG_CLASS_NONE = 0x0000; + static const u16 REG_CLASS_X = 0x0100; // X0..X30, XZR + static const u16 REG_CLASS_W = 0x0200; // W0..W30, WZR + static const u16 REG_CLASS_XSP = 0x0300; // SP (opt-in, distinct from X) + static const u16 REG_CLASS_WSP = 0x0400; // WSP (opt-in, distinct from W) + static const u16 REG_CLASS_V = 0x0500; // V0..V31 (full 128-bit SIMD&FP) + static const u16 REG_CLASS_B = 0x0600; // B0..B31 (byte view) + static const u16 REG_CLASS_H = 0x0700; // H0..H31 (half view) + static const u16 REG_CLASS_S = 0x0800; // S0..S31 (single view) + static const u16 REG_CLASS_D = 0x0900; // D0..D31 (double view) + static const u16 REG_CLASS_Q = 0x0A00; // Q0..Q31 (quad view) + static const u16 REG_CLASS_Z = 0x0B00; // Z0..Z31 SVE scalable vector + static const u16 REG_CLASS_P = 0x0C00; // P0..P15 SVE predicate + + enum Register : u16 { + REG_INVALID, REG_X0, REG_X1, REG_X2, REG_X3, REG_X4, REG_X5, REG_X6, REG_X7, REG_X8, REG_X9, REG_X10, REG_X11, REG_X12, REG_X13, REG_X14, + REG_X15, REG_X16, REG_X17, REG_X18, REG_X19, REG_X20, REG_X21, REG_X22, REG_X23, REG_X24, REG_X25, REG_X26, REG_X27, REG_X28, REG_X29, REG_X30, + REG_XZR, REG_SP, REG_W0, REG_W1, REG_W2, REG_W3, REG_W4, REG_W5, REG_W6, REG_W7, REG_W8, REG_W9, REG_W10, REG_W11, REG_W12, REG_W13, + REG_W14, REG_W15, REG_W16, REG_W17, REG_W18, REG_W19, REG_W20, REG_W21, REG_W22, REG_W23, REG_W24, REG_W25, REG_W26, REG_W27, REG_W28, REG_W29, + REG_W30, REG_WZR, REG_WSP, REG_V0, REG_V1, REG_V2, REG_V3, REG_V4, REG_V5, REG_V6, REG_V7, REG_V8, REG_V9, REG_V10, REG_V11, REG_V12, + REG_V13, REG_V14, REG_V15, REG_V16, REG_V17, REG_V18, REG_V19, REG_V20, REG_V21, REG_V22, REG_V23, REG_V24, REG_V25, REG_V26, REG_V27, REG_V28, + REG_V29, REG_V30, REG_V31, + REG_COUNT + }; + + + // Condition flags (PSTATE.NZCV). Named ClobberFlags to match the shared + // C++ front-end's "flags" concept (x86 EFLAGS / riscv fcsr exceptions). + enum ClobberFlags : u8 { + ClobberFlag_N = 1<<0, // negative result + ClobberFlag_Z = 1<<1, // zero result + ClobberFlag_C = 1<<2, // carry-out / no-borrow (unsigned sense) + ClobberFlag_V = 1<<3, // signed overflow + }; + static u16 const CLOBBER_FLAGS_COND = ClobberFlag_N|ClobberFlag_Z|ClobberFlag_C|ClobberFlag_V; + + char const *clobber_flag_bit_name(u16 bit) { + switch (bit) { + case ClobberFlag_N: return "n"; + case ClobberFlag_Z: return "z"; + case ClobberFlag_C: return "c"; + case ClobberFlag_V: return "v"; + } + return "?"; + } + + // FPSR cumulative FP exception / saturation flags (separate register from NZCV). + enum FPSRFlags : u8 { + FPSRFlag_IOC = 1<<0, // invalid operation + FPSRFlag_DZC = 1<<1, // divide by zero + FPSRFlag_OFC = 1<<2, // overflow + FPSRFlag_UFC = 1<<3, // underflow + FPSRFlag_IXC = 1<<4, // inexact + FPSRFlag_IDC = 1<<5, // input denormal + FPSRFlag_QC = 1<<6, // cumulative saturation (Advanced SIMD) + }; + + char const *fpsr_flag_bit_name(u16 bit) { + switch (bit) { + case FPSRFlag_IOC: return "ioc"; + case FPSRFlag_DZC: return "dzc"; + case FPSRFlag_OFC: return "ofc"; + case FPSRFlag_UFC: return "ufc"; + case FPSRFlag_IXC: return "ixc"; + case FPSRFlag_IDC: return "idc"; + case FPSRFlag_QC: return "qc"; + } + return "?"; + } + + enum ClobberRegs : u8 { + ClobberReg_LR = 1<<0, // x30, implicit link written by BL/BLR, read by RET + ClobberReg_SP = 1<<1, // sp, implicit base on PACIASP/AUTIASP + stack forms + ClobberReg_X16 = 1<<2, // implicit modifier register for PAC*1716 / AUT*1716 + ClobberReg_X17 = 1<<3, // implicit pointer register for PAC*1716 / AUT*1716 + }; + + static u8 const CLOBBER_REGS_NAMED = + ClobberReg_LR|ClobberReg_SP|ClobberReg_X16|ClobberReg_X17; + + enum SideEffectFlags : u16 { + SideEffectFlag_CONTROL = 1<<0, // writes pc: B/BL/BR/BLR/RET, B.cond, CBZ/CBNZ, TBZ/TBNZ + SideEffectFlag_EXCEPTION = 1<<1, // exception-generating call: SVC / HVC / SMC + SideEffectFlag_TRAP = 1<<2, // deliberately faults: BRK, UDF + SideEffectFlag_FENCE = 1<<3, // memory-ordering barrier: DMB/DSB, acquire/release + SideEffectFlag_ISYNC = 1<<4, // instruction-stream / context sync: ISB + SideEffectFlag_ATOMIC = 1<<5, // indivisible RMW: LDXR/STXR pair, LSE + SideEffectFlag_RESERVATION = 1<<6, // sets/tests/clears the local monitor: LDXR/STXR, CLREX + SideEffectFlag_CACHE = 1<<7, // cache maintenance with coherence effects: DC, IC + SideEffectFlag_HINT = 1<<8, // architecturally-inert hint: NOP/YIELD/PRFM/SEV/ESB/CSDB + SideEffectFlag_BTI = 1<<9, // branch-target-identification landing pad (CFI) + SideEffectFlag_PAC = 1<<10, // pointer authentication: reads an implicit key, may fault + SideEffectFlag_WAIT = 1<<11, // suspends execution until event/interrupt: WFI/WFE + SideEffectFlag_PRIVILEGED = 1<<12, // reads/writes system state: MSR/MRS, ERET, TLBI, AT, DAIF + SideEffectFlag_FFR = 1<<13, // reads/writes the SVE first-fault register + SideEffectFlag_NONDETERMINISTIC = 1<<14, // RNDR/RNDRRS, counter/timer reads (CNTVCT), TSTART + }; + + enum OperandSet : u8 { + OperandSet_OP0 = 1<<0, + OperandSet_OP1 = 1<<1, + OperandSet_OP2 = 1<<2, + OperandSet_OP3 = 1<<3, + }; + + u16 clobber_bit_for_reg_name(String const &pin) { + static const struct { String name; u16 bit; } table[] = { + {str_lit("lr"), ClobberReg_LR}, + {str_lit("x30"), ClobberReg_LR}, + {str_lit("w30"), ClobberReg_LR}, + {str_lit("sp"), ClobberReg_SP}, + {str_lit("wsp"), ClobberReg_SP}, + {str_lit("x16"), ClobberReg_X16}, + {str_lit("w16"), ClobberReg_X16}, + {str_lit("x17"), ClobberReg_X17}, + {str_lit("w17"), ClobberReg_X17}, + }; + for (auto const &t : table) { + if (pin == t.name) { + return t.bit; + } + } + return 0; + } + + char const *clobber_reg_bit_name(u16 bit) { + switch (bit) { + case ClobberReg_LR: return "lr"; + case ClobberReg_SP: return "sp"; + case ClobberReg_X16: return "x16"; + case ClobberReg_X17: return "x17"; + } + return ""; + } + + + u16 flag_from_name(String const &name) { + // NZCV condition flags. + static const struct { String name; ClobberFlags flag; } table[] = { + {str_lit("n"), ClobberFlag_N}, + {str_lit("z"), ClobberFlag_Z}, + {str_lit("c"), ClobberFlag_C}, + {str_lit("v"), ClobberFlag_V}, + }; + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + u16 fpsr_flag_from_name(String const &name) { + static const struct { String name; FPSRFlags flag; } table[] = { + {str_lit("ioc"), FPSRFlag_IOC}, // Invalid Operation + {str_lit("dzc"), FPSRFlag_DZC}, // Divide by Zero + {str_lit("ofc"), FPSRFlag_OFC}, // Overflow + {str_lit("ufc"), FPSRFlag_UFC}, // Underflow + {str_lit("ixc"), FPSRFlag_IXC}, // Inexact + {str_lit("idc"), FPSRFlag_IDC}, // Input Denormal + {str_lit("qc"), FPSRFlag_QC}, // Cumulative Saturation + }; + for (auto const &t : table) { + if (name == t.name) { + return cast(u16)t.flag; + } + } + return 0; + } + + + i32 flag_bit_from_name(String const &name, i32 *width_) { + // Real PSTATE.NZCV bit positions (as read/written via MRS/MSR NZCV, bits 31:28). + static const struct { String name; i32 bit; } table[] = { + {str_lit("v"), 28}, // Overflow + {str_lit("c"), 29}, // Carry + {str_lit("z"), 30}, // Zero + {str_lit("n"), 31}, // Negative + }; + for (auto const &t : table) { + if (name == t.name) { + if (width_) { + *width_ = 1; + } + return t.bit; + } + } + return -1; + } + + + struct Clobber { + OperandSet written; // operand slots whose register/SIMD reg is written + OperandSet read; // operand slots whose register / mem-base is read + ClobberRegs implicit_wr; // implicit reg writes (LR on BL/BLR) + ClobberRegs implicit_rd; // implicit reg reads (LR on RET, SP on PAC*SP) + ClobberFlags nzcv_wr; // condition flags written (ADDS/SUBS/ANDS, CMP, FCMP, CCMP...) + ClobberFlags nzcv_undef; // condition flags left UNKNOWN (rare on A64, usually empty) + ClobberFlags nzcv_rd; // condition flags read (B.cond, CSEL, ADC/SBC, CCMP...) + FPSRFlags fpsr_wr; // FP cumulative exception/saturation flags this op may raise + bool reads_fpcr; // consumes the rounding mode / FP control from FPCR + bool writes_mem; + bool reads_mem; + SideEffectFlags side_effects; + + ClobberFlags flags_rd_call() const { + return nzcv_rd; + } + ClobberFlags flags_wr_call() const { + return nzcv_wr; + } + + bool implies_clobber_flags() const { + return ((cast(u16)nzcv_wr | cast(u16)nzcv_undef) != 0) || + (cast(u16)fpsr_wr != 0); + } + bool implies_clobber_memory() const { + return writes_mem || reads_mem || + (cast(u16)side_effects & (SideEffectFlag_FENCE|SideEffectFlag_ATOMIC|SideEffectFlag_CACHE)) != 0; + } + bool implies_side_effects() const { + u16 const VOLATILE_SE = + SideEffectFlag_CONTROL | + SideEffectFlag_EXCEPTION | + SideEffectFlag_TRAP | + SideEffectFlag_FENCE | + SideEffectFlag_ISYNC | + SideEffectFlag_ATOMIC | + SideEffectFlag_RESERVATION | + SideEffectFlag_CACHE | + SideEffectFlag_BTI | + SideEffectFlag_PAC | + SideEffectFlag_WAIT | + SideEffectFlag_PRIVILEGED | + SideEffectFlag_FFR | + SideEffectFlag_NONDETERMINISTIC; + // NOTE: SideEffectFlag_HINT deliberately excluded โ€” inert, may be DCE'd. + return (cast(u16)side_effects & VOLATILE_SE) != 0; + } + u8 is_call_or_mem() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0 || + (cast(u16)implicit_wr & (ClobberReg_LR|ClobberReg_SP)) != 0; + } + bool has_control() const { + return (cast(u16)side_effects & SideEffectFlag_CONTROL) != 0; + } + bool has_halt() const { + // WFI/WFE suspend execution (x86 HLT analog); SVC/HVC/SMC gate out. + return (cast(u16)side_effects & (SideEffectFlag_WAIT|SideEffectFlag_EXCEPTION)) != 0; + } + bool is_conditional() const { + return has_control() && (cast(u16)nzcv_rd != 0); + } + bool is_nondeterministic() const { + return (cast(u16)side_effects & SideEffectFlag_NONDETERMINISTIC) != 0; + } + bool has_implicit_mem() const { + if (!writes_mem && !reads_mem) { + return false; + } + u16 implicit = cast(u16)implicit_rd | cast(u16)implicit_wr; + bool is_atomic = (cast(u16)side_effects & SideEffectFlag_ATOMIC) != 0; + return (implicit & ClobberReg_SP) != 0 || is_atomic; + } + }; + + void clobber_implicit_regs(StringSet *clobber_registers_set, u16 implicit_regs) { + u8 regs = cast(u8)implicit_regs & CLOBBER_REGS_NAMED; + + for (u8 bit = 1; bit != 0; bit <<= 1) { + if ((regs & bit) == 0) { + continue; + } + char const *rname = clobber_reg_bit_name(bit); + string_set_update(clobber_registers_set, make_string_c(rname)); + } + } + + enum AliasSrc : u8 { + AliasSrc_NONE, // slot unused + AliasSrc_ARG0, // user's 1st operand + AliasSrc_ARG1, // user's 2nd operand + AliasSrc_ARG2, // user's 3rd operand + AliasSrc_ZERO, // hardwired zero + AliasSrc_LINK, // link register + AliasSrc_LIT, // immediate literal + }; + + // NOTE(arm64): dummy โ€” only riscv needs pseudo aliases; arm64 has none. + struct PseudoAlias { + Mnemonic target; // real instruction emitted + AliasSrc src[4]; // how to fill target's four operand slots + i16 lit; // immediate when a src slot is AliasSrc_LIT + u16 csr; // unused on arm64 + u8 nargs; // operands the user supplies (ARG0..>5u)&((1u<<3)-1)); } + }; + #pragma pack(pop) + GB_STATIC_ASSERT(gb_size_of(Encoding) == 20); + + + // Companion run index: ENCODE_RUNS[mnemonic] -> contiguous run in ENCODE_FORMS. + struct EncodeRun { + u32 start; // start index in ENCODE_FORMS + u32 count; // number of forms for this mnemonic + }; + + + static EncodeRun const raw_encode_runs [786]; + static u8 const raw_encode_forms [48720]; + static u8 const raw_clobber_forms[34104]; + + StringMap mnemonic_map; + StringMap register_map; + + bool init(i64 word_size) { + gb_unused(word_size); // A64 is fixed 64-bit; W views are the 32-bit half. + + string_map_init(&mnemonic_map, MNEMONIC_COUNT*2); + for (u16 m = M_INVALID+1; m < MNEMONIC_COUNT; m++) { + string_map_set(&mnemonic_map, mnemonic_strings[m], cast(Mnemonic)m); + } + + string_map_init(®ister_map, REG_COUNT*2); + for (u16 r = REG_INVALID+1; r < REG_COUNT; r++) { + string_map_set(®ister_map, register_strings[r], cast(Register)r); + } + return true; + } + + + enum MnemonicSuffix : u8 { + MnemonicSuffix_None = 0, + }; + + bool mnemonic_accepts_suffix(u16 m) const { + // A64 acquire/release/atomic variants are distinct mnemonics (LDAR, STLR, + // LDADDA...), not textual suffixes on a base mnemonic. + gb_unused(m); + return false; + } + + Mnemonic mnemonic_lookup_ordered(String const &name, u8 *suffixes_) { + gb_unused(name); + gb_unused(suffixes_); + return M_INVALID; + } + + enum PseudoMacroMnemonic : u8 { + PseudoMacroMnemonic_INVALID, + PseudoMacroMnemonic_COUNT + // NOTE: MOV-wide-immediate expansion (MOV -> MOVZ/MOVN/MOVK sequence) could + // be modelled here if the front-end wants macro lowering for arm64. + }; + + PseudoMacroMnemonic pseudo_macro_mnemonic_lookup(String const &name) { + gb_unused(name); + return PseudoMacroMnemonic_INVALID; + } + + Mnemonic mnemonic_lookup(String const &name) { + Mnemonic *found = string_map_get(&mnemonic_map, name); + return found ? *found : M_INVALID; + } + Prefix prefix_lookup(String const &name) { + gb_unused(name); + return PREFIX_INVALID; + } + static String const prefix_strings[PREFIX_COUNT]; + + Register register_lookup(String const &name) { + Register *found = string_map_get(®ister_map, name); + return found ? *found : REG_INVALID; + } + Slice encoding_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Encoding *ENCODE_FORMS = cast(Encoding *)raw_encode_forms; + return Slice{ENCODE_FORMS+r.start, r.count}; + } + Slice clobber_forms(/*Mnemonic*/ u16 m) const { + EncodeRun r = raw_encode_runs[m]; + Clobber *CLOBBER_FORMS = cast(Clobber *)raw_clobber_forms; + return Slice{CLOBBER_FORMS+r.start, r.count}; + } + u16 reg_class(/*Register*/ u16 r) const { + return 0xFF00 & r; + } + // size in bits for register + u16 reg_size(Register r) const { + switch (reg_class(register_codes[r])) { + case REG_CLASS_X: return 64; + case REG_CLASS_W: return 32; + case REG_CLASS_XSP: return 64; + case REG_CLASS_WSP: return 32; + case REG_CLASS_V: return 128; + case REG_CLASS_B: return 8; + case REG_CLASS_H: return 16; + case REG_CLASS_S: return 32; + case REG_CLASS_D: return 64; + case REG_CLASS_Q: return 128; + case REG_CLASS_Z: return 0; // SVE scalable (VL, implementation-defined) + case REG_CLASS_P: return 0; // SVE predicate (scalable) + } + return 0; + } + + bool reg_is_segment(/*Register*/ u16 r) { + gb_unused(r); + return false; // arm64 has no segment registers + } + + bool integer_reg_width_is_exact() const { + return true; // X = 64, W = 32 always + } + bool float_reg_width_is_exact() const { + return true; // B/H/S/D/Q scalar views are exact widths + } + bool supports_memory_index_not_just_disp() const { + return true; // base + (optionally extended/shifted) index register + } + + AsmOperandKind kind_from_operand_type(OperandType type) const { + switch (type) { + case OP_NONE: + return AsmOperand_Invalid; + + // ---- Registers ---- + // Integer GPR / GPR-or-SP, including shifted- and extended-register forms. + case OP_W_REG: case OP_X_REG: + case OP_WSP_REG: case OP_XSP_REG: + case OP_W_SHIFTED: case OP_X_SHIFTED: + case OP_W_EXTENDED: case OP_X_EXTENDED: + // SIMD&FP scalar views. + case OP_B_REG: case OP_H_REG: case OP_S_REG: case OP_D_REG: case OP_Q_REG: + // NEON vector: plain, arrangement, FP16, element-indexed. + case OP_V_REG: + case OP_V_8B: case OP_V_16B: case OP_V_4H: case OP_V_8H: + case OP_V_2S: case OP_V_4S: case OP_V_1D: case OP_V_2D: + case OP_V_4H_FP16: case OP_V_8H_FP16: + case OP_V_ELEM_B: case OP_V_ELEM_H: case OP_V_ELEM_S: case OP_V_ELEM_D: + // SVE vector + predicate registers. + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: + // SME2 multi-vector register lists (first register of the list). + case OP_Z_PAIR: case OP_Z_QUAD: + // SME ZA tiles (ZA0.B .. ZAn.Q) โ€” register-like tile operands. + case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S: + case OP_ZA_TILE_D: case OP_ZA_TILE_Q: + case OP_SYS_REG: // MRS/MSR system-register name -> 16-bit field (cf. riscv CSR) + return AsmOperand_Register; + + // ---- Immediates (numeric literals and immediate-encoded selectors) ---- + case OP_IMM_2: case OP_IMM_3: case OP_IMM_4: case OP_IMM_5: + case OP_IMM_6: case OP_IMM_8: case OP_IMM_12: case OP_IMM_16: + case OP_NZCV_IMM: + case OP_HW_SHIFT: + case OP_BITMASK_IMM: + case OP_LSE_SIZE: + case OP_LSL_SHIFT_W: case OP_LSL_SHIFT_X: case OP_ROR_SHIFT: + case OP_FCMLA_ROT: case OP_FCADD_ROT: + case OP_SVE_PRFOP: + case OP_VEC_SHIFT: case OP_VEC_INDEX: + // Enum-like tokens that encode into an immediate field: + case OP_COND: // condition code (EQ/NE/...) -> 4-bit field + case OP_SME_PATTERN: case OP_SVE_PATTERN: // pattern / tile-list selectors + // JUDGMENT CALL: the following are register/tile-slice constructs + // syntactically, but this table models each as a single packed immediate + // descriptor (see Operand_Type comments). If the front-end parses their + // bracketed tile-slice / [Xn,#imm] syntax, reclassify as Register/Memory. + case OP_SME_SLICE_B: case OP_SME_SLICE_H: case OP_SME_SLICE_W: + case OP_SME_SLICE_D: case OP_SME_SLICE_Q: + case OP_LDRAA_IMM10: // signed imm10 displacement of the PAC-load address form + return AsmOperand_Immediate; + + // ---- Branch / PC-relative targets (written as labels) ---- + case OP_REL_26: case OP_REL_19: case OP_REL_14: case OP_REL_PG21: + return AsmOperand_Label; + + // ---- Memory addressing modes ---- + case OP_MEM_OFFSET: case OP_MEM_PRE: case OP_MEM_POST: + case OP_MEM_REG: case OP_MEM_EXT: + case OP_MEM_SVE_SS: case OP_MEM_SVE_SI: + case OP_MEM_SVE_VEC: case OP_MEM_SVE_VB: + return AsmOperand_Memory; + } + return AsmOperand_Invalid; + } + + AsmRegClass reg_class_from_operand_type(OperandType type) const { + switch (type) { + // Integer GPRs (incl. GPR-or-SP and shifted/extended register forms). + case OP_W_REG: case OP_X_REG: + case OP_WSP_REG: case OP_XSP_REG: + case OP_W_SHIFTED: case OP_X_SHIFTED: + case OP_W_EXTENDED: case OP_X_EXTENDED: + return AsmRegClass_Integer; + + // SIMD&FP scalar views share the V register file; treated as the float class. + case OP_B_REG: case OP_H_REG: case OP_S_REG: case OP_D_REG: case OP_Q_REG: + return AsmRegClass_Float; + + // NEON vectors (plain / arrangement / FP16 / element-indexed), SVE Z + // vectors, and SME2 Z register-lists โ€” all the vector register file. + case OP_V_REG: + case OP_V_8B: case OP_V_16B: case OP_V_4H: case OP_V_8H: + case OP_V_2S: case OP_V_4S: case OP_V_1D: case OP_V_2D: + case OP_V_4H_FP16: case OP_V_8H_FP16: + case OP_V_ELEM_B: case OP_V_ELEM_H: case OP_V_ELEM_S: case OP_V_ELEM_D: + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: + case OP_Z_PAIR: case OP_Z_QUAD: + return AsmRegClass_Vector; + + // SVE predicate registers. + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: + return AsmRegClass_Mask; + + // Everything else has no GPR/vector/mask class: + // - immediates, selectors, memory, labels, cond, sysreg, patterns. + // - ZA_TILE_* are SME ZA-tile registers, but AsmRegClass has no + // matrix/tile class, so they fall through to Unknown here (still + // Register-kind, the same shape as x86 SREG/CR/DR). + default: + return AsmRegClass_Unknown; + } + } + + bool operand_type_is_implicit(OperandType t) const { + // A64 operands are written explicitly; fixed regs (LR on RET, SP/X16/X17 + // on PAC*) are tracked via the Clobber implicit_rd/implicit_wr sets, not + // as implicit operand-type slots. + gb_unused(t); + return false; + } + + AsmRegClass operand_type_reg_class(OperandType t) const { + // Same mapping as reg_class_from_operand_type. + return reg_class_from_operand_type(t); + } + + // A64 has no operand slot that only one named hardware register can fill + // (SP-taking slots accept any Xn or SP via the *_SP classes). + u16 operand_type_named_reg_class(OperandType t) const { + gb_unused(t); + return REG_CLASS_NONE; + } + + String named_reg_class_string(u16 reg_class) const { + gb_unused(reg_class); + return str_lit("hardware"); + } + + u16 operand_type_bit_width(OperandType t) const { + switch (t) { + case OP_NONE: + return 0; + + // ---- Integer registers (incl. shifted/extended forms) -> data width ---- + case OP_W_REG: case OP_WSP_REG: case OP_W_SHIFTED: case OP_W_EXTENDED: + return 32; + case OP_X_REG: case OP_XSP_REG: case OP_X_SHIFTED: case OP_X_EXTENDED: + return 64; + + // ---- SIMD&FP scalar views ---- + case OP_B_REG: return 8; + case OP_H_REG: return 16; + case OP_S_REG: return 32; + case OP_D_REG: return 64; + case OP_Q_REG: return 128; + + // ---- NEON vectors: total register width of the arrangement ---- + case OP_V_REG: + return 128; // full V (Q view) + case OP_V_8B: case OP_V_4H: case OP_V_2S: case OP_V_1D: + case OP_V_4H_FP16: + return 64; // 64-bit (D-register) arrangements + case OP_V_16B: case OP_V_8H: case OP_V_4S: case OP_V_2D: + case OP_V_8H_FP16: + return 128; // 128-bit (Q-register) arrangements + + // ---- Element-indexed vector: width of the indexed element ---- + case OP_V_ELEM_B: return 8; + case OP_V_ELEM_H: return 16; + case OP_V_ELEM_S: return 32; + case OP_V_ELEM_D: return 64; + + // ---- Immediates -> value / encoded-field width ---- + case OP_IMM_2: return 2; + case OP_IMM_3: return 3; + case OP_IMM_4: return 4; + case OP_IMM_5: return 5; + case OP_IMM_6: return 6; + case OP_IMM_8: return 8; + case OP_IMM_12: return 12; + case OP_IMM_16: return 16; + case OP_NZCV_IMM: return 4; + case OP_HW_SHIFT: return 2; // 2-bit LSL hw (0/16/32/48) + case OP_LSE_SIZE: return 2; + case OP_SYS_REG: return 16; // op0:op1:CRn:CRm:op2 packed + case OP_LSL_SHIFT_W: return 5; // 0..31 + case OP_LSL_SHIFT_X: return 6; // 0..63 + case OP_ROR_SHIFT: return 6; // imms field + case OP_FCMLA_ROT: return 2; + case OP_FCADD_ROT: return 1; + case OP_SVE_PRFOP: return 4; + case OP_LDRAA_IMM10: return 10; + case OP_COND: return 4; + case OP_SVE_PATTERN: return 5; // 5-bit pattern field (PTRUE) + + // ---- PC-relative displacement value widths ---- + case OP_REL_26: return 26; + case OP_REL_19: return 19; + case OP_REL_14: return 14; + case OP_REL_PG21: return 21; // ADR/ADRP imm21 (ADRP scaled << 12) + + // ---- Width is scalable, data-dependent, or set elsewhere -> 0 ---- + case OP_Z_REG_B: case OP_Z_REG_H: case OP_Z_REG_S: case OP_Z_REG_D: // SVE VL-scaled + case OP_P_REG: case OP_P_REG_MERGE: case OP_P_REG_ZERO: case OP_P_REG_GOV: // predicate (VL/8) + case OP_Z_PAIR: case OP_Z_QUAD: // SVE reg-lists (scalable) + case OP_ZA_TILE_B: case OP_ZA_TILE_H: case OP_ZA_TILE_S: + case OP_ZA_TILE_D: case OP_ZA_TILE_Q: // SME tiles (scalable) + case OP_SME_PATTERN: // selector, no data width + case OP_SME_SLICE_B: case OP_SME_SLICE_H: case OP_SME_SLICE_W: + case OP_SME_SLICE_D: case OP_SME_SLICE_Q: // packed slice descriptor + case OP_BITMASK_IMM: // value width = operand width (32/64) + case OP_VEC_SHIFT: // element-size dependent + case OP_VEC_INDEX: // element-size dependent + case OP_MEM_OFFSET: case OP_MEM_PRE: case OP_MEM_POST: + case OP_MEM_REG: case OP_MEM_EXT: + case OP_MEM_SVE_SS: case OP_MEM_SVE_SI: + case OP_MEM_SVE_VEC: case OP_MEM_SVE_VB: // access size from opcode + return 0; + } + return 0; + } + + int form_explicit_slot(Encoding const &form, int explicit_index) const { + int seen = 0; + for (int j = 0; j < gb_count_of(form.ops); j++) { + auto t = form.ops[j]; + if (!t) { + break; + } + if (operand_type_is_implicit(t)) { + continue; + } + if (seen == explicit_index) { + return j; + } + seen += 1; + } + return -1; + } + + bool prefix_kind_okay(u8 prefix, Encoding const &form, bool *requires_memory_dest_) const { + // arm64 does not have instruction prefixes. + gb_unused(prefix); + gb_unused(form); + gb_unused(requires_memory_dest_); + return false; + } + AsmOperandConstraint operand_value_constraint(u16 m, int op) const { + switch (m) { + case M_LSL: case M_LSR: case M_ASR: case M_ROR: + if (op == 2) return {AsmOperandConstraint_ShiftCount, /*reg width*/-1}; + break; + // NOTE: A64 SDIV/UDIV by zero returns 0 (no fault), so no + // NonZeroDivisor constraint is emitted for division. + } + return {AsmOperandConstraint_None, -1}; + } bool is_self_zeroing_idiom(u16 m) const { + switch (m) { + case M_EOR: // x ^ x == 0 + case M_SUB: // x - x == 0 + case M_BIC: // x & ~x == 0 + return true; + } + return false; + } +}; + + + +gb_global Asm_arm64 g_asm_arm64; + + + +String const Asm_arm64::prefix_strings[Asm_arm64::PREFIX_COUNT]{}; +String const Asm_arm64::mnemonic_strings[Asm_arm64::MNEMONIC_COUNT] { + str_lit(""), str_lit("add"), str_lit("adds"), str_lit("sub"), str_lit("subs"), str_lit("movz"), str_lit("movn"), str_lit("movk"), str_lit("adr"), str_lit("adrp"), str_lit("and"), str_lit("ands"), str_lit("orr"), str_lit("eor"), str_lit("bic"), str_lit("bics"), + str_lit("orn"), str_lit("eon"), str_lit("lsl"), str_lit("lsr"), str_lit("asr"), str_lit("ror"), str_lit("udiv"), str_lit("sdiv"), str_lit("madd"), str_lit("msub"), str_lit("smaddl"), str_lit("smsubl"), str_lit("umaddl"), str_lit("umsubl"), str_lit("smulh"), str_lit("umulh"), + str_lit("clz"), str_lit("cls"), str_lit("rbit"), str_lit("rev"), str_lit("rev16"), str_lit("rev32"), str_lit("csel"), str_lit("csinc"), str_lit("csinv"), str_lit("csneg"), str_lit("ccmp"), str_lit("ccmn"), str_lit("extr"), str_lit("b"), str_lit("bl"), str_lit("br"), + str_lit("blr"), str_lit("ret"), str_lit("b_cond"), str_lit("cbz"), str_lit("cbnz"), str_lit("tbz"), str_lit("tbnz"), str_lit("ldr"), str_lit("str"), str_lit("ldrb"), str_lit("strb"), str_lit("ldrsb"), str_lit("ldrh"), str_lit("strh"), str_lit("ldrsh"), str_lit("ldrsw"), + str_lit("ldp"), str_lit("stp"), str_lit("ldpsw"), str_lit("ldar"), str_lit("stlr"), str_lit("ldarb"), str_lit("stlrb"), str_lit("ldarh"), str_lit("stlrh"), str_lit("ldxr"), str_lit("stxr"), str_lit("ldaxr"), str_lit("stlxr"), str_lit("nop"), str_lit("yield"), str_lit("wfe"), + str_lit("wfi"), str_lit("sev"), str_lit("sevl"), str_lit("hint"), str_lit("mrs"), str_lit("msr"), str_lit("isb"), str_lit("dsb"), str_lit("dmb"), str_lit("svc"), str_lit("hvc"), str_lit("smc"), str_lit("brk"), str_lit("hlt"), str_lit("eret"), str_lit("fmov"), + str_lit("fabs"), str_lit("fneg"), str_lit("fsqrt"), str_lit("fadd"), str_lit("fsub"), str_lit("fmul"), str_lit("fdiv"), str_lit("fnmul"), str_lit("fmadd"), str_lit("fmsub"), str_lit("fnmadd"), str_lit("fnmsub"), str_lit("fcmp"), str_lit("fcmpe"), str_lit("fcsel"), str_lit("fmax"), + str_lit("fmin"), str_lit("fmaxnm"), str_lit("fminnm"), str_lit("fcvt"), str_lit("scvtf"), str_lit("ucvtf"), str_lit("fcvtzs"), str_lit("fcvtzu"), str_lit("fcvtas"), str_lit("fcvtau"), str_lit("fcvtns"), str_lit("fcvtnu"), str_lit("fcvtps"), str_lit("fcvtpu"), str_lit("fcvtms"), str_lit("fcvtmu"), + str_lit("frinta"), str_lit("frinti"), str_lit("frintm"), str_lit("frintn"), str_lit("frintp"), str_lit("frintx"), str_lit("frintz"), str_lit("tst"), str_lit("ldur"), str_lit("stur"), str_lit("ldurb"), str_lit("sturb"), str_lit("ldursb"), str_lit("ldurh"), str_lit("sturh"), str_lit("ldursh"), + str_lit("ldursw"), str_lit("ldnp"), str_lit("stnp"), str_lit("ldxp"), str_lit("stxp"), str_lit("ldaxp"), str_lit("stlxp"), str_lit("ldxrb"), str_lit("stxrb"), str_lit("ldaxrb"), str_lit("stlxrb"), str_lit("ldxrh"), str_lit("stxrh"), str_lit("ldaxrh"), str_lit("stlxrh"), str_lit("ldapr"), + str_lit("ldaprb"), str_lit("ldaprh"), str_lit("ldadd"), str_lit("ldadda"), str_lit("ldaddl"), str_lit("ldaddal"), str_lit("ldclr"), str_lit("ldclra"), str_lit("ldclrl"), str_lit("ldclral"), str_lit("ldeor"), str_lit("ldeora"), str_lit("ldeorl"), str_lit("ldeoral"), str_lit("ldset"), str_lit("ldseta"), + str_lit("ldsetl"), str_lit("ldsetal"), str_lit("ldsmax"), str_lit("ldsmaxa"), str_lit("ldsmaxl"), str_lit("ldsmaxal"), str_lit("ldsmin"), str_lit("ldsmina"), str_lit("ldsminl"), str_lit("ldsminal"), str_lit("ldumax"), str_lit("ldumaxa"), str_lit("ldumaxl"), str_lit("ldumaxal"), str_lit("ldumin"), str_lit("ldumina"), + str_lit("lduminl"), str_lit("lduminal"), str_lit("swp"), str_lit("swpa"), str_lit("swpl"), str_lit("swpal"), str_lit("cas"), str_lit("casa"), str_lit("casl"), str_lit("casal"), str_lit("casb"), str_lit("casab"), str_lit("caslb"), str_lit("casalb"), str_lit("cash"), str_lit("casah"), + str_lit("caslh"), str_lit("casalh"), str_lit("casp"), str_lit("caspa"), str_lit("caspl"), str_lit("caspal"), str_lit("pacia"), str_lit("pacib"), str_lit("pacda"), str_lit("pacdb"), str_lit("paciza"), str_lit("pacizb"), str_lit("pacdza"), str_lit("pacdzb"), str_lit("autia"), str_lit("autib"), + str_lit("autda"), str_lit("autdb"), str_lit("autiza"), str_lit("autizb"), str_lit("autdza"), str_lit("autdzb"), str_lit("paciasp"), str_lit("pacibsp"), str_lit("autiasp"), str_lit("autibsp"), str_lit("pacia1716"), str_lit("pacib1716"), str_lit("autia1716"), str_lit("autib1716"), str_lit("pacga"), str_lit("xpaci"), + str_lit("xpacd"), str_lit("xpaclri"), str_lit("retaa"), str_lit("retab"), str_lit("braa"), str_lit("brab"), str_lit("braaz"), str_lit("brabz"), str_lit("blraa"), str_lit("blrab"), str_lit("blraaz"), str_lit("blrabz"), str_lit("eretaa"), str_lit("eretab"), str_lit("bti"), str_lit("irg"), + str_lit("addg"), str_lit("subg"), str_lit("gmi"), str_lit("subp"), str_lit("subps"), str_lit("ldg"), str_lit("stg"), str_lit("st2g"), str_lit("stzg"), str_lit("stz2g"), str_lit("stgp"), str_lit("ldgm"), str_lit("stgm"), str_lit("stzgm"), str_lit("crc32b"), str_lit("crc32h"), + str_lit("crc32w"), str_lit("crc32x"), str_lit("crc32cb"), str_lit("crc32ch"), str_lit("crc32cw"), str_lit("crc32cx"), str_lit("aese"), str_lit("aesd"), str_lit("aesmc"), str_lit("aesimc"), str_lit("sha1h"), str_lit("sha1c"), str_lit("sha1p"), str_lit("sha1m"), str_lit("sha1su0"), str_lit("sha1su1"), + str_lit("sha256h"), str_lit("sha256h2"), str_lit("sha256su0"), str_lit("sha256su1"), str_lit("sha512h"), str_lit("sha512h2"), str_lit("sha512su0"), str_lit("sha512su1"), str_lit("eor3"), str_lit("bcax"), str_lit("rax1"), str_lit("xar"), str_lit("sm3partw1"), str_lit("sm3partw2"), str_lit("sm3ss1"), str_lit("sm3tt1a"), + str_lit("sm3tt1b"), str_lit("sm3tt2a"), str_lit("sm3tt2b"), str_lit("sm4e"), str_lit("sm4ekey"), str_lit("pmull"), str_lit("pmull2"), str_lit("bfcvt"), str_lit("bfdot"), str_lit("bfmmla"), str_lit("bfmlalb"), str_lit("bfmlalt"), str_lit("bfcvtn"), str_lit("bfcvtn2"), str_lit("mul"), str_lit("mla"), + str_lit("mls"), str_lit("neg"), str_lit("abs"), str_lit("shadd"), str_lit("uhadd"), str_lit("shsub"), str_lit("uhsub"), str_lit("srhadd"), str_lit("urhadd"), str_lit("sqadd"), str_lit("uqadd"), str_lit("sqsub"), str_lit("uqsub"), str_lit("smax"), str_lit("umax"), str_lit("smin"), + str_lit("umin"), str_lit("sabd"), str_lit("uabd"), str_lit("saba"), str_lit("uaba"), str_lit("addp"), str_lit("addv"), str_lit("saddlp"), str_lit("uaddlp"), str_lit("sadalp"), str_lit("uadalp"), str_lit("saddlv"), str_lit("uaddlv"), str_lit("smaxv"), str_lit("umaxv"), str_lit("sminv"), + str_lit("uminv"), str_lit("smaxp"), str_lit("umaxp"), str_lit("sminp"), str_lit("uminp"), str_lit("saddl"), str_lit("saddl2"), str_lit("uaddl"), str_lit("uaddl2"), str_lit("ssubl"), str_lit("ssubl2"), str_lit("usubl"), str_lit("usubl2"), str_lit("saddw"), str_lit("saddw2"), str_lit("uaddw"), + str_lit("uaddw2"), str_lit("ssubw"), str_lit("ssubw2"), str_lit("usubw"), str_lit("usubw2"), str_lit("raddhn"), str_lit("raddhn2"), str_lit("rsubhn"), str_lit("rsubhn2"), str_lit("addhn"), str_lit("addhn2"), str_lit("subhn"), str_lit("subhn2"), str_lit("xtn"), str_lit("xtn2"), str_lit("sqxtn"), + str_lit("sqxtn2"), str_lit("uqxtn"), str_lit("uqxtn2"), str_lit("sqxtun"), str_lit("sqxtun2"), str_lit("smull"), str_lit("smull2"), str_lit("umull"), str_lit("umull2"), str_lit("smlal"), str_lit("smlal2"), str_lit("umlal"), str_lit("umlal2"), str_lit("smlsl"), str_lit("smlsl2"), str_lit("umlsl"), + str_lit("umlsl2"), str_lit("sqdmull"), str_lit("sqdmull2"), str_lit("sqdmlal"), str_lit("sqdmlal2"), str_lit("sqdmlsl"), str_lit("sqdmlsl2"), str_lit("sqdmulh"), str_lit("sqrdmulh"), str_lit("sdot"), str_lit("udot"), str_lit("usdot"), str_lit("fmla"), str_lit("fmls"), str_lit("fmulx"), str_lit("fmaxp"), + str_lit("fminp"), str_lit("fmaxnmp"), str_lit("fminnmp"), str_lit("fmaxv"), str_lit("fminv"), str_lit("fmaxnmv"), str_lit("fminnmv"), str_lit("frecpe"), str_lit("frsqrte"), str_lit("frecps"), str_lit("frsqrts"), str_lit("frecpx"), str_lit("faddp"), str_lit("fcvtl"), str_lit("fcvtl2"), str_lit("fcvtn"), + str_lit("fcvtn2"), str_lit("fcvtxn"), str_lit("fcvtxn2"), str_lit("fcmeq"), str_lit("fcmge"), str_lit("fcmgt"), str_lit("fcmle"), str_lit("fcmlt"), str_lit("facge"), str_lit("facgt"), str_lit("cmeq"), str_lit("cmge"), str_lit("cmgt"), str_lit("cmhi"), str_lit("cmhs"), str_lit("cmle"), + str_lit("cmlt"), str_lit("cmtst"), str_lit("mvn"), str_lit("bit"), str_lit("bif"), str_lit("bsl"), str_lit("shl"), str_lit("sqshl"), str_lit("sqshlu"), str_lit("srshl"), str_lit("urshl"), str_lit("sshr"), str_lit("ushr"), str_lit("ssra"), str_lit("usra"), str_lit("srshr"), + str_lit("urshr"), str_lit("srsra"), str_lit("ursra"), str_lit("sshl"), str_lit("ushl"), str_lit("sli"), str_lit("sri"), str_lit("sshll"), str_lit("sshll2"), str_lit("ushll"), str_lit("ushll2"), str_lit("sxtl"), str_lit("sxtl2"), str_lit("uxtl"), str_lit("uxtl2"), str_lit("shrn"), + str_lit("shrn2"), str_lit("rshrn"), str_lit("rshrn2"), str_lit("sqshrn"), str_lit("sqshrn2"), str_lit("uqshrn"), str_lit("uqshrn2"), str_lit("sqrshrn"), str_lit("sqrshrn2"), str_lit("uqrshrn"), str_lit("uqrshrn2"), str_lit("sqshrun"), str_lit("sqshrun2"), str_lit("sqrshrun"), str_lit("sqrshrun2"), str_lit("dup"), + str_lit("ins"), str_lit("mov"), str_lit("ext"), str_lit("tbl"), str_lit("tbx"), str_lit("zip1"), str_lit("zip2"), str_lit("uzp1"), str_lit("uzp2"), str_lit("trn1"), str_lit("trn2"), str_lit("not"), str_lit("rev64"), str_lit("cnt"), str_lit("urecpe"), str_lit("ursqrte"), + str_lit("movi"), str_lit("mvni"), str_lit("ld1"), str_lit("ld2"), str_lit("ld3"), str_lit("ld4"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("ld1r"), str_lit("ld2r"), str_lit("ld3r"), str_lit("ld4r"), str_lit("subr"), str_lit("asrr"), + str_lit("lslr"), str_lit("lsrr"), str_lit("ftsmul"), str_lit("fsubr"), str_lit("fdivr"), str_lit("fnmla"), str_lit("fnmls"), str_lit("nand"), str_lit("nor"), str_lit("sel"), str_lit("orrs"), str_lit("eors"), str_lit("nands"), str_lit("nors"), str_lit("orns"), str_lit("movs"), + str_lit("ptrue"), str_lit("ptrues"), str_lit("pfalse"), str_lit("pfirst"), str_lit("pnext"), str_lit("brka"), str_lit("brkb"), str_lit("brkas"), str_lit("brkbs"), str_lit("brkpa"), str_lit("brkpb"), str_lit("brkn"), str_lit("rdffr"), str_lit("wrffr"), str_lit("setffr"), str_lit("cmpeq"), + str_lit("cmpne"), str_lit("cmpge"), str_lit("cmpgt"), str_lit("cmple"), str_lit("cmplt"), str_lit("cmphi"), str_lit("cmphs"), str_lit("cmplo"), str_lit("cmpls"), str_lit("fcmne"), str_lit("fcmuo"), str_lit("insr"), str_lit("cpy"), str_lit("compact"), str_lit("ld1b"), str_lit("ld1h"), + str_lit("ld1w"), str_lit("ld1d"), str_lit("ld1sb"), str_lit("ld1sh"), str_lit("ld1sw"), str_lit("st1b"), str_lit("st1h"), str_lit("st1w"), str_lit("st1d"), str_lit("ldff1b"), str_lit("ldff1h"), str_lit("ldff1w"), str_lit("ldff1d"), str_lit("whilege"), str_lit("whilegt"), str_lit("whilele"), + str_lit("whilelt"), str_lit("whilehi"), str_lit("whilehs"), str_lit("whilelo"), str_lit("whilels"), str_lit("sqrdmlah"), str_lit("sqrdmlsh"), str_lit("adclb"), str_lit("adclt"), str_lit("sbclb"), str_lit("sbclt"), str_lit("tbl2"), str_lit("match"), str_lit("nmatch"), str_lit("histcnt"), str_lit("histseg"), + str_lit("smstart"), str_lit("smstop"), str_lit("rdsvl"), str_lit("addha"), str_lit("addva"), str_lit("zero"), str_lit("fmopa"), str_lit("fmops"), str_lit("bfmopa"), str_lit("bfmops"), str_lit("smopa"), str_lit("smops"), str_lit("umopa"), str_lit("umops"), str_lit("usmopa"), str_lit("sumopa"), + str_lit("ld1q"), str_lit("st1q"), str_lit("mova"), str_lit("fcmla"), str_lit("fcadd"), str_lit("prfb"), str_lit("prfh"), str_lit("prfw"), str_lit("prfd"), str_lit("ldnt1b"), str_lit("ldnt1h"), str_lit("ldnt1w"), str_lit("ldnt1d"), str_lit("stnt1b"), str_lit("stnt1h"), str_lit("stnt1w"), + str_lit("stnt1d"), str_lit("splice"), str_lit("index"), str_lit("bsl1n"), str_lit("bsl2n"), str_lit("nbsl"), str_lit("pmul"), str_lit("pmullb"), str_lit("pmullt"), str_lit("bfcvtnt"), str_lit("ldraa"), str_lit("ldrab"), str_lit("tstart"), str_lit("tcommit"), str_lit("tcancel"), str_lit("ttest"), + str_lit("wfet"), str_lit("wfit"), str_lit("bc_cond"), str_lit("uxtb"), str_lit("uxth"), str_lit("uxtw"), str_lit("sxtb"), str_lit("sxth"), str_lit("sxtw"), str_lit("adc"), str_lit("adcs"), str_lit("sbc"), str_lit("sbcs"), str_lit("ngc"), str_lit("ngcs"), str_lit("ldapur"), + str_lit("stlur"), str_lit("ldapurb"), str_lit("stlurb"), str_lit("ldapurh"), str_lit("stlurh"), str_lit("ldapursb"), str_lit("ldapursh"), str_lit("ldapursw"), str_lit("bfadd"), str_lit("bfsub"), str_lit("bfmul"), str_lit("bfmla"), str_lit("bfmls"), str_lit("sb"), str_lit("csdb"), str_lit("dgh"), + str_lit("psb_csync"), str_lit("tsb_csync"), str_lit("bti_j"), str_lit("bti_c"), str_lit("bti_jc"), str_lit("bfclamp"), str_lit("bfmaxnm"), str_lit("bfminnm"), str_lit("luti2"), str_lit("luti4"), str_lit("zip"), str_lit("uzp"), str_lit("tlbi_rpalos"), str_lit("tlbi_rpaos"), str_lit("at_s1e1a"), str_lit("dc_cipapa"), + str_lit("dc_cigdpapa"), str_lit("tlbi_paall"), str_lit("tlbi_paallos"), str_lit("amx_ldx"), str_lit("amx_ldy"), str_lit("amx_stx"), str_lit("amx_sty"), str_lit("amx_ldz"), str_lit("amx_stz"), str_lit("amx_ldzi"), str_lit("amx_stzi"), str_lit("amx_extrx"), str_lit("amx_extry"), str_lit("amx_fma64"), str_lit("amx_fms64"), str_lit("amx_fma32"), + str_lit("amx_fms32"), str_lit("amx_mac16"), str_lit("amx_fma16"), str_lit("amx_fms16"), str_lit("amx_set"), str_lit("amx_clr"), str_lit("amx_vecint"), str_lit("amx_vecfp"), str_lit("amx_matint"), str_lit("amx_matfp"), str_lit("amx_genlut"), str_lit("cpyp"), str_lit("cpym"), str_lit("cpye"), str_lit("cpyfp"), str_lit("cpyfm"), + str_lit("cpyfe"), str_lit("setp"), str_lit("setm"), str_lit("sete"), str_lit("dc_ivac"), str_lit("dc_isw"), str_lit("dc_csw"), str_lit("dc_cisw"), str_lit("dc_zva"), str_lit("dc_cvac"), str_lit("dc_cvau"), str_lit("dc_civac"), str_lit("ic_ialluis"), str_lit("ic_iallu"), str_lit("ic_ivau"), str_lit("at_s1e1r"), + str_lit("at_s1e1w"), str_lit("at_s1e0r"), str_lit("at_s1e0w"), str_lit("at_s1e2r"), str_lit("at_s1e2w"), str_lit("at_s1e3r"), str_lit("at_s1e3w"), str_lit("at_s12e1r"), str_lit("at_s12e1w"), str_lit("at_s12e0r"), str_lit("at_s12e0w"), str_lit("tlbi_vmalle1"), str_lit("tlbi_vmalle1is"), str_lit("tlbi_vae1"), str_lit("tlbi_vae1is"), str_lit("tlbi_aside1"), + str_lit("tlbi_aside1is"), str_lit("tlbi_vaae1"), str_lit("tlbi_vaae1is"), str_lit("tlbi_vale1"), str_lit("tlbi_vale1is"), str_lit("tlbi_vaale1"), str_lit("tlbi_vaale1is"), str_lit("tlbi_alle1"), str_lit("tlbi_alle1is"), str_lit("tlbi_alle2"), str_lit("tlbi_alle2is"), str_lit("tlbi_alle3"), str_lit("tlbi_alle3is"), str_lit("prfm"), str_lit("prfum"), str_lit("negs"), + str_lit("cmp"), str_lit("cmn"), +}; +u16 const Asm_arm64::register_codes[Asm_arm64::REG_COUNT] { + 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, + 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, + 287, 799, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, + 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, + 542, 543, 1055, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, + 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, + 1309, 1310, 1311, +}; +String const Asm_arm64::register_strings[Asm_arm64::REG_COUNT] { + str_lit(""), str_lit("x0"), str_lit("x1"), str_lit("x2"), str_lit("x3"), str_lit("x4"), str_lit("x5"), str_lit("x6"), str_lit("x7"), str_lit("x8"), str_lit("x9"), str_lit("x10"), str_lit("x11"), str_lit("x12"), str_lit("x13"), str_lit("x14"), + str_lit("x15"), str_lit("x16"), str_lit("x17"), str_lit("x18"), str_lit("x19"), str_lit("x20"), str_lit("x21"), str_lit("x22"), str_lit("x23"), str_lit("x24"), str_lit("x25"), str_lit("x26"), str_lit("x27"), str_lit("x28"), str_lit("x29"), str_lit("x30"), + str_lit("xzr"), str_lit("sp"), str_lit("w0"), str_lit("w1"), str_lit("w2"), str_lit("w3"), str_lit("w4"), str_lit("w5"), str_lit("w6"), str_lit("w7"), str_lit("w8"), str_lit("w9"), str_lit("w10"), str_lit("w11"), str_lit("w12"), str_lit("w13"), + str_lit("w14"), str_lit("w15"), str_lit("w16"), str_lit("w17"), str_lit("w18"), str_lit("w19"), str_lit("w20"), str_lit("w21"), str_lit("w22"), str_lit("w23"), str_lit("w24"), str_lit("w25"), str_lit("w26"), str_lit("w27"), str_lit("w28"), str_lit("w29"), + str_lit("w30"), str_lit("wzr"), str_lit("wsp"), str_lit("v0"), str_lit("v1"), str_lit("v2"), str_lit("v3"), str_lit("v4"), str_lit("v5"), str_lit("v6"), str_lit("v7"), str_lit("v8"), str_lit("v9"), str_lit("v10"), str_lit("v11"), str_lit("v12"), + str_lit("v13"), str_lit("v14"), str_lit("v15"), str_lit("v16"), str_lit("v17"), str_lit("v18"), str_lit("v19"), str_lit("v20"), str_lit("v21"), str_lit("v22"), str_lit("v23"), str_lit("v24"), str_lit("v25"), str_lit("v26"), str_lit("v27"), str_lit("v28"), + str_lit("v29"), str_lit("v30"), str_lit("v31"), +}; +String const Asm_arm64::pseudo_mnemonic_strings[Asm_arm64::PSEUDO_MNEMONIC_COUNT] {}; +Asm_arm64::EncodeRun const Asm_arm64::raw_encode_runs[786] = { + { 0, 0}, { 0, 21}, { 21, 6}, { 27, 18}, { 45, 6}, { 51, 2}, { 53, 2}, { 55, 2}, { 57, 1}, { 58, 1}, { 59, 7}, { 66, 5}, { 71, 7}, { 78, 7}, { 85, 5}, { 90, 3}, + { 93, 4}, { 97, 2}, { 99, 8}, { 107, 8}, { 115, 8}, { 123, 4}, { 127, 4}, { 131, 4}, { 135, 2}, { 137, 2}, { 139, 1}, { 140, 1}, { 141, 1}, { 142, 1}, { 143, 5}, { 148, 5}, + { 153, 12}, { 165, 12}, { 177, 4}, { 181, 7}, { 188, 4}, { 192, 5}, { 197, 2}, { 199, 2}, { 201, 2}, { 203, 2}, { 205, 4}, { 209, 4}, { 213, 2}, { 215, 1}, { 216, 1}, { 217, 1}, + { 218, 1}, { 219, 2}, { 221, 1}, { 222, 2}, { 224, 2}, { 226, 1}, { 227, 1}, { 228, 18}, { 246, 16}, { 262, 4}, { 266, 4}, { 270, 4}, { 274, 4}, { 278, 4}, { 282, 4}, { 286, 2}, + { 288, 9}, { 297, 9}, { 306, 3}, { 309, 2}, { 311, 2}, { 313, 1}, { 314, 1}, { 315, 1}, { 316, 1}, { 317, 2}, { 319, 2}, { 321, 2}, { 323, 2}, { 325, 1}, { 326, 1}, { 327, 1}, + { 328, 1}, { 329, 1}, { 330, 1}, { 331, 1}, { 332, 1}, { 333, 2}, { 335, 1}, { 336, 1}, { 337, 1}, { 338, 1}, { 339, 1}, { 340, 1}, { 341, 1}, { 342, 1}, { 343, 1}, { 344, 15}, + { 359, 11}, { 370, 11}, { 381, 11}, { 392, 12}, { 404, 12}, { 416, 12}, { 428, 9}, { 437, 3}, { 440, 3}, { 443, 3}, { 446, 3}, { 449, 3}, { 452, 3}, { 455, 3}, { 458, 3}, { 461, 11}, + { 472, 11}, { 483, 11}, { 494, 11}, { 505, 6}, { 511, 10}, { 521, 10}, { 531, 10}, { 541, 10}, { 551, 11}, { 562, 11}, { 573, 11}, { 584, 11}, { 595, 11}, { 606, 11}, { 617, 11}, { 628, 11}, + { 639, 11}, { 650, 11}, { 661, 11}, { 672, 11}, { 683, 11}, { 694, 11}, { 705, 11}, { 716, 4}, { 720, 5}, { 725, 5}, { 730, 1}, { 731, 1}, { 732, 2}, { 734, 1}, { 735, 1}, { 736, 2}, + { 738, 1}, { 739, 2}, { 741, 2}, { 743, 2}, { 745, 2}, { 747, 2}, { 749, 2}, { 751, 1}, { 752, 1}, { 753, 1}, { 754, 1}, { 755, 1}, { 756, 1}, { 757, 1}, { 758, 1}, { 759, 2}, + { 761, 1}, { 762, 1}, { 763, 2}, { 765, 2}, { 767, 2}, { 769, 2}, { 771, 2}, { 773, 2}, { 775, 2}, { 777, 2}, { 779, 2}, { 781, 2}, { 783, 2}, { 785, 2}, { 787, 2}, { 789, 2}, + { 791, 2}, { 793, 2}, { 795, 2}, { 797, 2}, { 799, 2}, { 801, 2}, { 803, 2}, { 805, 2}, { 807, 2}, { 809, 2}, { 811, 2}, { 813, 2}, { 815, 2}, { 817, 2}, { 819, 2}, { 821, 2}, + { 823, 2}, { 825, 2}, { 827, 2}, { 829, 2}, { 831, 2}, { 833, 2}, { 835, 2}, { 837, 2}, { 839, 2}, { 841, 2}, { 843, 1}, { 844, 1}, { 845, 1}, { 846, 1}, { 847, 1}, { 848, 1}, + { 849, 1}, { 850, 1}, { 851, 2}, { 853, 2}, { 855, 2}, { 857, 2}, { 859, 1}, { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, { 865, 1}, { 866, 1}, { 867, 1}, { 868, 1}, + { 869, 1}, { 870, 1}, { 871, 1}, { 872, 1}, { 873, 1}, { 874, 1}, { 875, 1}, { 876, 1}, { 877, 1}, { 878, 1}, { 879, 1}, { 880, 1}, { 881, 1}, { 882, 1}, { 883, 1}, { 884, 1}, + { 885, 1}, { 886, 1}, { 887, 1}, { 888, 1}, { 889, 1}, { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 1}, { 897, 1}, { 898, 1}, { 899, 1}, { 900, 1}, + { 901, 1}, { 902, 1}, { 903, 1}, { 904, 1}, { 905, 1}, { 906, 1}, { 907, 1}, { 908, 1}, { 909, 1}, { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, + { 917, 1}, { 918, 1}, { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 2}, { 925, 2}, { 927, 2}, { 929, 2}, { 931, 1}, { 932, 1}, { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, + { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, { 942, 1}, { 943, 1}, { 944, 1}, { 945, 2}, { 947, 2}, { 949, 1}, { 950, 5}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, + { 959, 1}, { 960, 1}, { 961, 1}, { 962, 1}, { 963, 1}, { 964, 2}, { 966, 2}, { 968, 2}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, { 975, 1}, { 976, 7}, { 983, 6}, + { 989, 6}, { 995, 13}, {1008, 11}, {1019, 6}, {1025, 6}, {1031, 6}, {1037, 6}, {1043, 6}, {1049, 6}, {1055, 11}, {1066, 11}, {1077, 11}, {1088, 11}, {1099, 10}, {1109, 10}, {1119, 10}, + {1129, 10}, {1139, 10}, {1149, 10}, {1159, 6}, {1165, 6}, {1171, 7}, {1178, 5}, {1183, 6}, {1189, 6}, {1195, 6}, {1201, 6}, {1207, 5}, {1212, 5}, {1217, 5}, {1222, 5}, {1227, 5}, + {1232, 5}, {1237, 6}, {1243, 6}, {1249, 6}, {1255, 6}, {1261, 3}, {1264, 3}, {1267, 3}, {1270, 3}, {1273, 3}, {1276, 3}, {1279, 3}, {1282, 3}, {1285, 3}, {1288, 3}, {1291, 3}, + {1294, 3}, {1297, 3}, {1300, 3}, {1303, 3}, {1306, 3}, {1309, 3}, {1312, 3}, {1315, 3}, {1318, 3}, {1321, 3}, {1324, 3}, {1327, 3}, {1330, 3}, {1333, 3}, {1336, 3}, {1339, 3}, + {1342, 3}, {1345, 3}, {1348, 3}, {1351, 3}, {1354, 3}, {1357, 3}, {1360, 3}, {1363, 3}, {1366, 3}, {1369, 3}, {1372, 3}, {1375, 3}, {1378, 3}, {1381, 3}, {1384, 3}, {1387, 3}, + {1390, 3}, {1393, 2}, {1395, 2}, {1397, 2}, {1399, 2}, {1401, 2}, {1403, 2}, {1405, 4}, {1409, 4}, {1413, 2}, {1415, 2}, {1417, 2}, {1419, 8}, {1427, 8}, {1435, 5}, {1440, 5}, + {1445, 5}, {1450, 5}, {1455, 5}, {1460, 3}, {1463, 3}, {1466, 3}, {1469, 3}, {1472, 5}, {1477, 5}, {1482, 8}, {1490, 8}, {1498, 6}, {1504, 5}, {1509, 2}, {1511, 2}, {1513, 2}, + {1515, 2}, {1517, 1}, {1518, 1}, {1519, 8}, {1527, 8}, {1535, 8}, {1543, 8}, {1551, 8}, {1559, 5}, {1564, 5}, {1569, 4}, {1573, 7}, {1580, 2}, {1582, 2}, {1584, 7}, {1591, 7}, + {1598, 7}, {1605, 7}, {1612, 4}, {1616, 1}, {1617, 1}, {1618, 2}, {1620, 7}, {1627, 7}, {1634, 7}, {1641, 7}, {1648, 7}, {1655, 7}, {1662, 7}, {1669, 7}, {1676, 7}, {1683, 7}, + {1690, 7}, {1697, 7}, {1704, 7}, {1711, 7}, {1718, 7}, {1725, 7}, {1732, 7}, {1739, 3}, {1742, 3}, {1745, 3}, {1748, 3}, {1751, 3}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, + {1766, 3}, {1769, 3}, {1772, 3}, {1775, 3}, {1778, 3}, {1781, 3}, {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 18}, + {1829, 8}, {1837, 12}, {1849, 4}, {1853, 6}, {1859, 3}, {1862, 12}, {1874, 12}, {1886, 12}, {1898, 12}, {1910, 12}, {1922, 12}, {1934, 3}, {1937, 6}, {1943, 6}, {1949, 2}, {1951, 2}, + {1953, 7}, {1960, 4}, {1964, 8}, {1972, 5}, {1977, 5}, {1982, 5}, {1987, 8}, {1995, 5}, {2000, 5}, {2005, 5}, {2010, 1}, {2011, 1}, {2012, 1}, {2013, 1}, {2014, 4}, {2018, 4}, + {2022, 4}, {2026, 4}, {2030, 3}, {2033, 3}, {2036, 3}, {2039, 3}, {2042, 3}, {2045, 1}, {2046, 1}, {2047, 1}, {2048, 1}, {2049, 1}, {2050, 1}, {2051, 1}, {2052, 1}, {2053, 1}, + {2054, 1}, {2055, 1}, {2056, 1}, {2057, 1}, {2058, 1}, {2059, 1}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, {2065, 1}, {2066, 1}, {2067, 1}, {2068, 1}, {2069, 4}, + {2073, 4}, {2077, 4}, {2081, 4}, {2085, 4}, {2089, 4}, {2093, 4}, {2097, 4}, {2101, 4}, {2105, 4}, {2109, 3}, {2112, 3}, {2115, 4}, {2119, 4}, {2123, 2}, {2125, 6}, {2131, 6}, + {2137, 6}, {2143, 5}, {2148, 3}, {2151, 3}, {2154, 2}, {2156, 6}, {2162, 6}, {2168, 6}, {2174, 5}, {2179, 1}, {2180, 1}, {2181, 1}, {2182, 1}, {2183, 1}, {2184, 1}, {2185, 1}, + {2186, 1}, {2187, 1}, {2188, 1}, {2189, 1}, {2190, 1}, {2191, 4}, {2195, 4}, {2199, 2}, {2201, 2}, {2203, 2}, {2205, 2}, {2207, 1}, {2208, 2}, {2210, 2}, {2212, 2}, {2214, 1}, + {2215, 1}, {2216, 1}, {2217, 1}, {2218, 1}, {2219, 1}, {2220, 1}, {2221, 1}, {2222, 1}, {2223, 1}, {2224, 1}, {2225, 2}, {2227, 2}, {2229, 2}, {2231, 2}, {2233, 1}, {2234, 1}, + {2235, 1}, {2236, 1}, {2237, 2}, {2239, 4}, {2243, 4}, {2247, 1}, {2248, 1}, {2249, 1}, {2250, 1}, {2251, 1}, {2252, 1}, {2253, 1}, {2254, 1}, {2255, 1}, {2256, 1}, {2257, 1}, + {2258, 1}, {2259, 1}, {2260, 4}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 1}, {2268, 1}, {2269, 1}, {2270, 1}, {2271, 2}, {2273, 2}, {2275, 1}, {2276, 1}, {2277, 1}, {2278, 1}, + {2279, 1}, {2280, 1}, {2281, 1}, {2282, 1}, {2283, 1}, {2284, 1}, {2285, 1}, {2286, 1}, {2287, 1}, {2288, 2}, {2290, 2}, {2292, 2}, {2294, 2}, {2296, 2}, {2298, 2}, {2300, 2}, + {2302, 2}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 2}, {2310, 2}, {2312, 1}, {2313, 2}, {2315, 2}, {2317, 2}, {2319, 1}, {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, + {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 2}, {2336, 2}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, + {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 1}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, {2356, 1}, {2357, 1}, + {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 1}, {2365, 1}, {2366, 1}, {2367, 1}, {2368, 1}, {2369, 1}, {2370, 1}, {2371, 1}, {2372, 1}, {2373, 1}, + {2374, 1}, {2375, 1}, {2376, 1}, {2377, 1}, {2378, 1}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 1}, {2384, 1}, {2385, 1}, {2386, 1}, {2387, 1}, {2388, 1}, {2389, 1}, + {2390, 1}, {2391, 1}, {2392, 1}, {2393, 1}, {2394, 1}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 1}, {2399, 1}, {2400, 1}, {2401, 1}, {2402, 1}, {2403, 1}, {2404, 1}, {2405, 1}, + {2406, 1}, {2407, 1}, {2408, 1}, {2409, 1}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 1}, {2418, 1}, {2419, 2}, {2421, 1}, {2422, 2}, + {2424, 6}, {2430, 6}, +}; +u8 const Asm_arm64::raw_encode_forms[48720] = { + 0x01, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x80, 0xff, 0x00, 0x70, 0x01, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x60, 0x01, 0x00, 0x02, 0x02, + 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x70, 0x01, 0x00, 0x03, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x0b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x8b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x01, 0x00, 0x10, 0x10, 0x10, 0x00, 0x28, 0x29, + 0x2a, 0x00, 0x00, 0x84, 0x20, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x12, 0x12, 0x12, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x60, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x14, 0x14, 0x14, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xa0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x16, 0x16, 0x16, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, + 0xe0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x0f, 0x0f, 0x0f, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x20, 0x0e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 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0x03, 0x03, 0x07, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x20, 0x6b, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x48, 0x10, 0x03, 0x04, 0x08, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x20, 0xeb, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x58, 0x10, 0x03, 0x03, 0x3a, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x71, 0x1f, 0x00, + 0x80, 0xff, 0x00, 0x48, 0x10, 0x03, 0x04, 0x3a, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x1f, 0x00, 0x00, 0xf1, 0x1f, 0x00, 0x80, 0xff, 0x00, 0x58, 0x11, 0x03, 0x01, 0x05, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x2b, 0x1f, 0x00, 0x20, 0xff, 0x00, 0x48, 0x11, 0x03, 0x02, 0x06, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x00, 0xab, 0x1f, 0x00, 0x20, 0xff, 0x00, 0x58, + 0x11, 0x03, 0x03, 0x07, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x20, 0x2b, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x48, 0x11, 0x03, 0x04, 0x08, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x20, 0xab, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x58, 0x11, 0x03, 0x03, 0x3a, 0x00, 0x00, 0x04, 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0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; diff --git a/src/check_asm.cpp b/src/check_asm.cpp index 901559bed..ca5be1374 100644 --- a/src/check_asm.cpp +++ b/src/check_asm.cpp @@ -81,6 +81,11 @@ gb_internal AsmOperandKind determine_asm_operand_kind(Operand const *operand) { } return AsmOperand_Register; case_end; + + case_ast_node(ie, IndexExpr, expr); + // TODO(bill): Is this correct? + return AsmOperand_Register; + case_end; } return AsmOperand_Invalid; } @@ -151,6 +156,10 @@ gb_internal void check_asm_collect_refs(AsmCtx *asm_ctx, PtrSet *refs, check_asm_collect_refs(asm_ctx, refs, m->disp, touched_regs_); return; } + case Ast_IndexExpr: + check_asm_collect_refs(asm_ctx, refs, expr->IndexExpr.expr, touched_regs_); + check_asm_collect_refs(asm_ctx, refs, expr->IndexExpr.index, touched_regs_); + return; } } enum AsmMismatch : u8 { @@ -1142,6 +1151,7 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm auto form_user_operand_count = [&](typename AsmCtx::Encoding const &form) -> int { int count = is_pseudo ? target_explicit_count : cast(int)form.explicit_count(); + GB_ASSERT_MSG(count <= 4, "%d", count); return gb_max(count, 0); }; @@ -1178,7 +1188,7 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm return asm_ctx->OP_NONE; }; - auto describe_form = [&](typename AsmCtx::Encoding const &form, typename AsmCtx::Clobber const &clobber) -> gbString { + auto describe_form = [&](typename AsmCtx::Encoding const &form, typename AsmCtx::Clobber const &clobber, isize max_count) -> gbString { gbString s = gb_string_make(heap_allocator(), ""); int count = form_user_operand_count(form); for (int i = 0; i < count; i++) { @@ -1224,27 +1234,33 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm s = gb_string_appendc(s, ", "); } - switch (k) { - case AsmOperand_Label: // 5 characters - break; - case AsmOperand_Immediate: // 3+ characters - case AsmOperand_Register_Or_Memory: - if (w == 0) { - s = gb_string_appendc(s, " "); - } else if (w < 10) { - s = gb_string_appendc(s, " "); + if (max_count > 1) { + switch (k) { + case AsmOperand_Label: // 5 characters + break; + case AsmOperand_Immediate: // 3+ characters + case AsmOperand_Register_Or_Memory: + if (w == 0) { + s = gb_string_appendc(s, " "); + } else if (w < 10) { + s = gb_string_appendc(s, " "); + } else if (w < 100) { + s = gb_string_appendc(s, " "); + } + break; + case AsmOperand_Register: // 1+ characters + case AsmOperand_Memory: + if (w == 0) { + s = gb_string_appendc(s, " "); + } else if (w < 10) { + s = gb_string_appendc(s, " "); + } else if (w < 100) { + s = gb_string_appendc(s, " "); + } else { + s = gb_string_appendc(s, " "); + } + break; } - break; - case AsmOperand_Register: // 1+ characters - case AsmOperand_Memory: - if (w == 0) { - s = gb_string_appendc(s, " "); - } else if (w < 10) { - s = gb_string_appendc(s, " "); - } else if (w < 100) { - s = gb_string_appendc(s, " "); - } - break; } } bool all_implicit = true; @@ -1314,7 +1330,7 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm return; } - gbString desc = describe_form(forms[form_index], clobber_forms[form_index]); + gbString desc = describe_form(forms[form_index], clobber_forms[form_index], 1); defer (gb_string_free(desc)); String line = make_string(cast(u8 const *)desc, gb_string_length(desc)); line = string_trim_trailing_whitespace(line); @@ -1336,7 +1352,7 @@ gb_internal bool check_mnemonic(AsmCtx *asm_ctx, CheckerContext *ctx, Entity *tm ); for_array(fi, forms) { - gbString desc = describe_form(forms[fi], clobber_forms[fi]); + gbString desc = describe_form(forms[fi], clobber_forms[fi], forms.count); bool dup = false; for (auto const &l : lines) { if (gb_string_are_equal(l, desc)) { @@ -2305,6 +2321,45 @@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * add_type_and_value(ctx, expr, Addressing_Value, found->type, {}); return; case_end; + + case_ast_node(ie, IndexExpr, expr); + Operand lhs = {}; + Operand rhs = {}; + check_asm_instruction_operand(asm_ctx, ctx, entity, &lhs, ie->expr, false); + check_asm_instruction_operand(asm_ctx, ctx, entity, &rhs, ie->index, false); + + auto lhs_kind = determine_asm_operand_kind(&lhs); + if (lhs_kind != AsmOperand_Register) { + gbString s = expr_to_string(lhs.expr); + error(lhs.expr, "Expected a vector register, got '%s' which is %.*s", + s, LIT(asm_operand_kind_expected_strings[lhs_kind])); + gb_string_free(s); + } else if (!is_type_simd_vector(lhs.type)) { + gbString s = type_to_string(lhs.type); + error(lhs.expr, "Expected a vector register, got %s", s); + gb_string_free(s); + } + + auto rhs_kind = determine_asm_operand_kind(&rhs); + if (rhs_kind != AsmOperand_Immediate) { + gbString s = expr_to_string(rhs.expr); + error(rhs.expr, "Expected an integer immediate as an index, got '%s' which is %.*s", + s, LIT(asm_operand_kind_expected_strings[rhs_kind])); + gb_string_free(s); + } else if (!is_type_integer(rhs.type)) { + gbString s = type_to_string(rhs.type); + error(rhs.expr, "Expected an integer immediate as an index, got %s", s); + gb_string_free(s); + } + + + operand->mode = Addressing_Value; + operand->type = base_array_type(lhs.type); + operand->value = {}; + + add_type_and_value(ctx, expr, Addressing_Value, operand->type, {}); + return; + case_end; } { From 440bd9df3f825ff031db91afd12f2d41ae967582 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 02:37:28 -0400 Subject: [PATCH 19/89] rexcode/arm32: printing a register-shifted operand read past SHIFT_NAMES SHIFT_NAMES holds five entries, LSL..RRX, but Shift_Type has ten: the four register-shifted-register markers (LSL_REG = 6 .. ROR_REG = 9) say the shift count comes from an Rs register rather than an immediate. Both places that indexed the table used the raw enum value, and the guard in front of them only excluded NONE and RRX -- so any operand carrying a register shift indexed a 5-entry array with 6..9 and killed the printer: printer.odin(473:45) Index 6 is out of range 0..<5 Fold the register-shifted variants back onto the table and give each spelling its own case: `, lsl #3` for an immediate amount, `, lsl r3` when the count is in a register (Rs index rides in shift_amt), and a bare `, rrx`, which takes no amount. All nine now print what an assembler accepts -- verified against llvm-mc -- where three of them previously crashed and RRX printed nothing. The memory-operand site indexed the same table the same way and is routed through the same helper. Found by printing every entry in the decode table; that sweep now completes. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/printer.odin | 33 +++++++++++++++++++++++------ 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 242fad50c..9c7c290d3 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -397,6 +397,31 @@ wprintln :: proc( // ============================================================================= // `.i32`, `.s32.f32`, `.8`. Both slots print when the second is set. +// A shift suffix on a register operand. Three spellings, and the enum covers +// all of them: `, lsl #3` for an immediate amount, `, lsl r3` when the count +// comes from a register (Shift_Type.LSL_REG..ROR_REG keep the Rs index in +// shift_amt), and a bare `, rrx`, which takes no amount at all. +// +// SHIFT_NAMES only holds LSL..RRX, so the register-shifted variants have to be +// folded back onto it. Indexing it with the raw enum value ran off the end -- +// LSL_REG is 6 against a 5-entry table -- and crashed the printer outright. +@(private="file") +write_shift :: proc(sb: ^strings.Builder, st: Shift_Type, amt: u8) { + switch st { + case .LSL, .LSR, .ASR, .ROR: + if amt == 0 { + return + } + fmt.sbprintf(sb, ", %s #%d", SHIFT_NAMES[int(st)], amt) + case .RRX: + strings.write_string(sb, ", rrx") + case .NONE: + // no shift to print + case .LSL_REG, .LSR_REG, .ASR_REG, .ROR_REG: + fmt.sbprintf(sb, ", %s %s", SHIFT_NAMES[int(st) - int(Shift_Type.LSL_REG)], GPR_NAMES[amt & 0xF]) + } +} + @(private="file") write_data_type :: proc(sb: ^strings.Builder, dt: Data_Types, uppercase: bool) { for d in dt { @@ -503,9 +528,7 @@ write_operand :: proc( return case .REGISTER: write_register(sb, op.reg) - if op.shift_type != .NONE && op.shift_type != .RRX && op.shift_amt > 0 { - fmt.sbprintf(sb, ", %s #%d", SHIFT_NAMES[int(op.shift_type)], op.shift_amt) - } + write_shift(sb, op.shift_type, op.shift_amt) if op.lane != 0 { fmt.sbprintf(sb, "[%d]", op.lane) } @@ -538,9 +561,7 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory) { strings.write_string(sb, ", ") if m.sign < 0 { strings.write_string(sb, "-") } write_register(sb, m.index) - if m.shift_type != .NONE && m.shift_amt > 0 { - fmt.sbprintf(sb, ", %s #%d", SHIFT_NAMES[int(m.shift_type)], m.shift_amt) - } + write_shift(sb, m.shift_type, m.shift_amt) strings.write_string(sb, "]") case .PRE_INDEX: strings.write_string(sb, ", ") From 02cce151ca431634125404c1dc14fff1a168069f Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 02:45:39 -0400 Subject: [PATCH 20/89] rexcode/arm32: stop presetting operand-driven bits in a form's fixed pattern The encoder builds a word by ORing packed operand fields onto the form's `bits`. It can only ever set a bit that way, never clear one -- so any bit `bits` presets that an operand is supposed to drive is stuck at 1 forever. 72 forms did that, and two families show what it cost: * The U bit (23) on the whole A32 load/store family. U selects add vs subtract for the displacement, and the encoder derives it from the sign of mem.disp -- but every form had it preset, so `ldr r0, [r1, #-4]` silently encoded as `[r1, #4]`. Every negative displacement in the family was wrong. * The Vn high bit (7) on the NEON lane-indexed forms. That bit is the top of the register number, so presetting it meant Vn could only ever name d16..d31; d0..d15 were unreachable. Which bits are operand-driven was decided by llvm-mc rather than by reading the manual: for each of the 230 bits a form preset outside its mask, take the form's canonical word with the bit set and cleared and disassemble both. Same mnemonic, different operands means the bit belongs to an operand (clear it); a different mnemonic, or an undecodable word, means the bit is genuinely fixed for that form. The split was not per-bit -- bit 7 is a register bit for VMUL/VMLA/VFMA but distinguishes VNEG from VABS and VCMPE from VCMP, and bit 23 is the U bit for LDR but the load/store select for VCX3 -- so every form was classified individually. Ten test expectations asserted the old values and were corrected; each had the bug baked in. Verified byte-exact against llvm-mc across the load/store family including every negative-displacement form, and the 1680/1680 decode sweep and all other suites are unchanged. The other half of `bits & ~mask != 0` -- 130 forms where the bit really is fixed and the MASK is merely too loose -- is deliberately not in this commit. Widening those masks alone breaks decode: a bit that distinguishes two mnemonics has to be added to BOTH forms' masks in the same pass, and doing only the ones that set it made LSL swallow MOVS, CX3 swallow VADDLVA and VABAV swallow VRMLSLDAVH. That needs each form's true mask derived empirically (vary the operands, see which bits move) the way specgen does it. Co-Authored-By: Claude Opus 5 (1M context) --- .../isa/arm32/tablegen/encoding_table.odin | 144 ++--- .../tablegen/generated/decode_tables.odin | 504 +++++++++--------- .../tablegen/generated/encode_tables.odin | 144 ++--- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 11106 -> 11106 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38640 -> 38640 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38640 -> 38640 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3360 -> 3360 bytes core/rexcode/isa/arm32/tests/smoke.odin | 20 +- 8 files changed, 406 insertions(+), 406 deletions(-) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index bcaf0a76f..df4e1bbac 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -956,7 +956,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PLI = { - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}}, + {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}}, // T32 PLI imm12: 0xF990F000 {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, @@ -973,13 +973,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // We split into three variants per direction: imm-offset, pre-index, post-index. .LDR = { // LDR imm12 offset: P=1 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 pre-index: P=1 W=1 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 post-index: P=0 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR reg offset: cond 011 P U 0 W 1 Rn Rt shift_imm shift_type 0 Rm - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 6 LDR PC-relative: 01001 Rd imm8 (LDR Rd, [PC, #imm8 << 2]) {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 7 LDR reg-offset: 0101 100 Rm Rb Rd @@ -996,10 +996,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STR = { - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STR reg-offset: 0101 000 Rm Rb Rd {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STR imm5: 01100 imm5 Rb Rd (offset = imm5 << 2) @@ -1012,10 +1012,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRB = { - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 LDRB reg-offset: 0101 110 Rm Rb Rd {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 LDRB imm5: 01111 imm5 Rb Rd @@ -1025,10 +1025,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRB = { - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STRB reg-offset: 0101 010 Rm Rb Rd {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STRB imm5: 01110 imm5 Rb Rd @@ -1042,11 +1042,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // where op2 = 01 (halfword), 10 (signed byte), 11 (signed half / doubleword) .LDRH = { // LDRH imm offset (P=1 W=0): cond 000 1 U 1 0 1 Rn Rt imm4H 1011 imm4L - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, // LDRH reg offset: cond 000 1 U 0 0 1 Rn Rt 0000 1011 Rm - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRH reg-offset: 0101 101 Rm Rb Rd {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 LDRH imm5: 10001 imm5 Rb Rd (offset = imm5 << 1) @@ -1056,10 +1056,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRH = { - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 STRH reg-offset: 0101 001 Rm Rb Rd {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 STRH imm5: 10000 imm5 Rb Rd @@ -1069,10 +1069,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSB = { - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSB reg-offset: 0101 011 Rm Rb Rd {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSB imm12 / reg @@ -1080,10 +1080,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSH = { - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSH reg-offset: 0101 111 Rm Rb Rd {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSH imm12 / reg @@ -1092,18 +1092,18 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .LDRD = { // LDRD imm offset (ARMv5TE+): cond 000 P U 1 W 0 Rn Rt imm4H 1101 imm4L - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 LDRD imm8: high=11101001 X101 Rn low=Rt Rt2 imm8 {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRD = { - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 STRD imm8: high=11101001 X100 Rn low=Rt Rt2 imm8 {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, @@ -1389,8 +1389,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // MVE FP vector + scalar {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, - {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VFMS = { @@ -1403,8 +1403,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, - {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VFNMS = { {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, @@ -1757,8 +1757,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 D-form / Q-form (F=1, size=10) - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { @@ -1783,8 +1783,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 (F=1) - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, @@ -1806,8 +1806,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { @@ -2103,8 +2103,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // unsigned - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE imm form (imm6 at bits 21:16) {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, @@ -2112,8 +2112,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .VSRA = { {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE (imm6 at bits 21:16) {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, @@ -2144,19 +2144,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .VRSHR = { {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VSLI / VSRI (shift left/right and insert) .VSLI = { - {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSRI = { - {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VABS / VNEG / VMVN / VCNT / VCLZ / VCLS (NEON unary) ---- @@ -2549,7 +2549,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VSHLL.S Q, D, #imm: 1111 0010 1 D imm6 Vd 1010 0 0 M 1 Vm // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1 + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1 // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, @@ -2566,12 +2566,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .VQSHRN = { // signed: 1111 0010 1 D imm6 Vd 1001 0 0 M 1 Vm; unsigned: U=1 {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRN = { // 1111 0010 1 D imm6 Vd 1001 0 1 M 1 Vm {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRUN = { // signed input, unsigned saturating shift right narrow: @@ -3573,14 +3573,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Unprivileged (translate) post-indexed loads/stores: the post-index form // with the W bit (21) set. Word/byte use imm12, half/signed use imm8 split. - .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {}} }, - .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {}} }, - .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {}} }, - .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {}} }, - .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, // NEON rounding shift-right-accumulate (imm); FP reciprocal/rsqrt estimate; // FP pairwise add; VFP convert-to-integer using the FPSCR rounding mode. diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 73edb4aa0..bcb3ee5a1 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -22,13 +22,23 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -44,25 +54,15 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, @@ -72,12 +72,18 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, @@ -103,8 +109,14 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {.NONE,.NONE} }, { .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {.NONE,.NONE} }, @@ -113,22 +125,22 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -151,17 +163,11 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, { .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, @@ -169,25 +175,19 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -387,37 +387,50 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -438,10 +451,10 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, @@ -454,24 +467,24 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -506,8 +519,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -585,8 +598,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -599,8 +612,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -641,19 +654,6 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, @@ -686,13 +686,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -713,8 +713,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -723,17 +723,17 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, @@ -741,9 +741,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, @@ -754,16 +754,16 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, @@ -855,6 +855,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -866,6 +868,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, @@ -881,8 +890,6 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -902,28 +909,21 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {}, {.NONE,.NONE} }, { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, @@ -991,27 +991,27 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, { .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, { .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {.NONE,.NONE} }, { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1693,69 +1693,69 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ @(rodata) DECODE_FORM_IDX := [1680]u16{ - 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 5, - 4, 0, 2, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, - 5, 4, 0, 2, 2, 2, 2, 1, 1, 2, 2, 2, 5, 4, 0, 0, - 2, 1, 1, 0, 0, 0, 5, 4, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, - 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 3, 3, - 2, 1, 0, 0, 0, 3, 3, 3, 5, 4, 0, 1, 1, 1, 1, 0, - 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 0, 0, - 0, 2, 1, 0, 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, - 1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 14, 9, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, + 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, + 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, + 5, 4, 0, 2, 1, 1, 5, 4, 0, 0, 0, 0, 0, 0, 0, 3, + 3, 3, 0, 0, 0, 0, 0, 0, 3, 3, 3, 2, 1, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 1, 0, 0, 0, 2, + 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, + 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, + 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 23, 25, 0, 0, - 0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 18, 16, 14, 12, 10, 6, - 0, 0, 0, 7, 5, 6, 8, 9, 4, 2, 3, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 5, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, - 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 0, 2, 0, - 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, - 16, 12, 15, 7, 6, 2, 8, 2, 7, 2, 7, 3, 1, 1, 3, 1, - 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, - 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, - 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, - 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, - 3, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, - 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, - 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, - 13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12, - 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, - 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1, - 2, 2, 2, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, + 0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 16, 14, 18, 12, 10, 6, + 0, 0, 0, 3, 5, 9, 7, 4, 6, 2, 8, 1, 0, 1, 0, 0, + 0, 0, 1, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0, + 2, 0, 2, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, + 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 2, 0, 2, 0, 4, 4, + 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, 16, 12, 15, + 7, 6, 2, 8, 2, 7, 7, 2, 1, 3, 3, 1, 1, 3, 6, 6, + 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, + 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 12, 6, + 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, 6, 6, + 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, 3, 3, + 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, + 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, 1, + 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, + 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, + 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 4, 9, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 23, 15, 17, 16, 14, 8, 7, 5, 10, 5, 9, 9, 5, 7, 7, 0, 10, 3, 2, 1, 0, 3, 0, 1, 2, 0, 1, - 0, 1, 0, 0, 0, 9, 8, 3, 5, 4, 7, 6, 2, 8, 9, 4, - 2, 5, 6, 3, 7, 1, 0, 1, 0, 2, 3, 1, 5, 2, 0, 4, - 2, 1, 0, 13, 11, 10, 12, 13, 12, 15, 14, 15, 14, 13, 12, 15, - 17, 14, 16, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1, + 1, 0, 0, 0, 0, 9, 8, 3, 5, 4, 6, 7, 2, 8, 9, 6, + 4, 5, 2, 7, 3, 1, 0, 1, 0, 2, 3, 1, 2, 0, 5, 4, + 2, 1, 0, 13, 11, 10, 12, 13, 12, 14, 15, 15, 14, 13, 12, 16, + 15, 17, 14, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1, 3, 2, 4, 3, 5, 1, 3, 0, 2, 4, 2, 1, 4, 5, 0, 3, 0, 1, 1, 0, 3, 1, 2, 0, 5, 0, 3, 1, 4, 2, 5, 0, 4, 3, 1, 2, 3, 1, 0, 2, 4, 2, 1, 3, 0, 4, 0, 1, 0, 0, 0, 0, 3, 1, 0, 2, 3, 0, 2, 1, 2, 3, 3, 0, - 3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 0, 3, - 2, 1, 1, 0, 2, 0, 1, 1, 0, 4, 6, 5, 0, 2, 1, 2, - 1, 0, 2, 1, 0, 0, 2, 1, 2, 2, 0, 0, 0, 7, 6, 5, - 4, 2, 1, 0, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 2, - 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, - 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 2, 2, + 0, 3, 2, 1, 1, 0, 2, 0, 1, 1, 0, 0, 0, 2, 0, 2, + 0, 0, 4, 6, 5, 0, 2, 1, 2, 1, 0, 2, 1, 0, 0, 2, + 1, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0, 2, 1, 0, 0, 1, + 2, 0, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 3, 3, 0, 0, 0, 3, 3, 0, 0, 3, 0, 3, + 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, 0, + 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9, 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, @@ -1803,20 +1803,20 @@ DECODE_FORM_IDX := [1680]u16{ @(rodata) DECODE_BUCKET_LIST := [5553]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, - 11, 8, 12, 35, 36, 37, 13, 14, 41, 42, 43, 15, 13, 16, 14, 17, - 47, 18, 19, 51, 52, 53, 20, 21, 18, 19, 22, 23, 24, 25, 22, 26, - 23, 27, 24, 28, 29, 30, 31, 28, 32, 33, 29, 30, 34, 35, 36, 37, - 38, 39, 40, 34, 41, 42, 43, 44, 38, 45, 39, 46, 47, 48, 49, 50, - 46, 51, 52, 53, 54, 48, 55, 49, 56, 57, 58, 59, 60, 61, 62, 109, - 110, 111, 63, 64, 65, 66, 67, 68, 117, 118, 119, 69, 70, 71, 72, 73, - 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 57, 85, 86, 87, 88, - 89, 90, 91, 92, 93, 142, 143, 144, 94, 95, 150, 151, 152, 96, 97, 98, - 74, 99, 100, 101, 102, 103, 160, 161, 162, 104, 105, 168, 169, 170, 106, 107, - 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 112, 113, - 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, - 133, 138, 134, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, - 152, 153, 145, 154, 146, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, - 166, 158, 167, 159, 168, 169, 170, 171, 172, 173, 175, 174, 176, 177, 178, 179, + 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, + 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, + 37, 33, 34, 38, 39, 40, 41, 38, 42, 43, 39, 40, 44, 13, 14, 15, + 45, 46, 47, 44, 18, 19, 20, 48, 49, 45, 46, 50, 24, 51, 52, 53, + 50, 27, 28, 29, 54, 51, 55, 52, 56, 57, 58, 59, 60, 61, 62, 63, + 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 57, 91, 92, 93, 94, + 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, + 80, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, + 126, 63, 64, 65, 127, 128, 129, 130, 131, 72, 73, 74, 132, 127, 133, 128, + 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, + 150, 145, 146, 151, 152, 153, 100, 101, 102, 154, 155, 156, 157, 158, 105, 106, + 107, 159, 160, 154, 155, 161, 162, 163, 164, 165, 116, 117, 118, 166, 167, 168, + 169, 170, 164, 165, 121, 122, 123, 171, 172, 173, 175, 174, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 204, 203, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, @@ -1839,108 +1839,108 @@ DECODE_BUCKET_LIST := [5553]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 363, 365, - 364, 366, 367, 368, 369, 370, 371, 379, 380, 373, 375, 381, 377, 378, 382, 374, - 376, 372, 384, 383, 385, 386, 391, 388, 394, 392, 389, 390, 387, 393, 395, 632, - 396, 633, 397, 398, 399, 634, 635, 400, 401, 636, 637, 402, 403, 638, 639, 404, - 405, 640, 406, 641, 642, 407, 408, 643, 644, 409, 410, 411, 412, 413, 414, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 430, 429, 432, - 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, - 636, 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, - 409, 437, 410, 438, 439, 440, 441, 442, 443, 444, 445, 446, 447, 448, 450, 449, - 451, 452, 453, 454, 456, 455, 458, 457, 459, 460, 462, 461, 464, 463, 465, 466, - 467, 468, 395, 632, 396, 633, 397, 398, 399, 634, 635, 400, 636, 401, 637, 402, - 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 469, 395, - 632, 396, 633, 397, 398, 634, 399, 400, 635, 401, 636, 402, 637, 403, 638, 639, - 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, 409, 470, 471, 472, 469, 358, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 365, 363, + 364, 366, 367, 368, 369, 370, 371, 373, 372, 376, 379, 375, 377, 381, 374, 380, + 382, 378, 383, 384, 385, 386, 389, 387, 390, 393, 391, 388, 394, 392, 395, 396, + 398, 397, 399, 400, 402, 401, 404, 403, 405, 406, 407, 408, 409, 410, 411, 412, + 413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, + 429, 430, 431, 432, 433, 434, 435, 437, 436, 438, 439, 440, 441, 443, 442, 445, + 444, 446, 447, 448, 449, 396, 395, 397, 398, 399, 400, 401, 402, 404, 403, 405, + 406, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421, + 422, 450, 423, 451, 452, 453, 454, 455, 456, 457, 458, 459, 461, 460, 463, 462, + 464, 465, 466, 467, 469, 468, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, + 480, 481, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 405, 406, 407, 408, + 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 482, 396, + 395, 397, 398, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, + 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 483, 484, 485, 482, 358, 359, 360, 365, 364, 363, 362, 361, 366, 367, 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, 375, 383, 384, 385, 386, 394, 393, 392, 391, - 389, 390, 388, 387, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, - 637, 402, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, - 473, 411, 412, 413, 414, 415, 416, 417, 418, 419, 420, 422, 421, 424, 423, 426, - 425, 428, 427, 429, 430, 432, 431, 433, 434, 435, 436, 395, 632, 396, 633, 397, - 398, 634, 399, 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 641, - 406, 407, 642, 408, 643, 644, 409, 474, 473, 438, 439, 440, 441, 442, 443, 444, - 445, 446, 447, 448, 449, 450, 451, 452, 454, 453, 455, 456, 458, 457, 459, 460, - 462, 461, 463, 464, 465, 466, 467, 468, 395, 632, 396, 633, 397, 398, 634, 399, - 400, 635, 636, 401, 637, 402, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, - 408, 643, 644, 409, 475, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 636, - 401, 402, 637, 403, 638, 639, 404, 640, 405, 406, 641, 407, 642, 408, 643, 644, - 409, 470, 471, 476, 475, 478, 477, 479, 480, 481, 482, 484, 483, 485, 486, 487, - 488, 489, 490, 491, 492, 493, 494, 495, 496, 498, 497, 499, 500, 501, 502, 503, - 504, 505, 506, 507, 508, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, - 520, 521, 522, 523, 524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 535, - 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, - 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, - 568, 569, 570, 571, 572, 573, 574, 575, 577, 576, 578, 579, 580, 581, 582, 583, - 584, 585, 586, 587, 588, 589, 591, 590, 592, 593, 594, 595, 596, 597, 598, 599, - 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, - 616, 477, 478, 479, 480, 481, 482, 484, 483, 485, 486, 487, 488, 489, 490, 491, - 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, - 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, - 524, 525, 526, 528, 527, 529, 530, 531, 532, 533, 534, 617, 536, 537, 538, 539, - 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, - 556, 557, 558, 559, 560, 561, 618, 575, 576, 577, 578, 579, 580, 581, 582, 583, - 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, - 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 615, - 619, 620, 621, 622, 365, 364, 363, 361, 362, 623, 624, 625, 626, 370, 371, 382, - 380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 627, 628, 629, 394, 393, 390, - 391, 392, 389, 388, 387, 630, 631, 632, 395, 633, 396, 397, 398, 399, 634, 635, - 400, 636, 401, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, - 643, 644, 409, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, - 658, 659, 661, 660, 662, 663, 664, 665, 630, 631, 632, 395, 633, 396, 397, 398, - 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, 641, - 642, 407, 408, 643, 644, 409, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, - 675, 676, 677, 678, 679, 680, 681, 682, 683, 684, 685, 686, 687, 688, 689, 690, - 691, 630, 631, 395, 632, 633, 396, 397, 398, 634, 399, 400, 635, 636, 401, 402, - 637, 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 692, - 693, 696, 694, 695, 697, 698, 700, 699, 701, 702, 703, 705, 704, 706, 707, 708, - 716, 709, 711, 713, 714, 710, 712, 715, 719, 722, 723, 717, 721, 718, 724, 720, - 726, 725, 729, 727, 728, 733, 731, 735, 730, 734, 732, 738, 736, 737, 739, 741, - 742, 740, 745, 746, 743, 744, 748, 750, 749, 747, 754, 753, 752, 751, 758, 755, - 756, 757, 761, 762, 759, 763, 760, 764, 766, 768, 767, 765, 769, 771, 770, 774, - 776, 777, 775, 772, 773, 783, 779, 782, 778, 781, 780, 785, 784, 787, 786, 790, - 789, 791, 788, 796, 793, 792, 794, 795, 797, 801, 800, 799, 803, 798, 802, 807, - 804, 806, 805, 808, 810, 809, 812, 811, 813, 815, 814, 816, 817, 818, 819, 823, - 821, 822, 820, 827, 825, 824, 826, 829, 828, 630, 631, 395, 632, 396, 633, 397, - 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, - 641, 407, 642, 408, 643, 644, 409, 830, 692, 620, 621, 622, 365, 364, 363, 361, - 362, 623, 624, 625, 626, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373, - 377, 381, 627, 628, 629, 394, 392, 393, 391, 390, 387, 388, 389, 630, 631, 395, - 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, - 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 831, 646, 647, 648, 649, + 389, 390, 388, 387, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 406, 405, + 408, 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, + 486, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 435, 434, 436, 437, 438, + 439, 441, 440, 442, 443, 445, 444, 446, 447, 448, 449, 396, 395, 398, 397, 399, + 400, 402, 401, 403, 404, 405, 406, 408, 407, 409, 410, 411, 412, 413, 414, 416, + 415, 417, 418, 419, 420, 421, 422, 487, 486, 451, 452, 453, 454, 455, 456, 457, + 458, 459, 460, 461, 463, 462, 464, 465, 466, 467, 469, 468, 470, 471, 473, 472, + 475, 474, 477, 476, 478, 479, 480, 481, 396, 395, 398, 397, 399, 400, 402, 401, + 404, 403, 406, 405, 407, 408, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, + 419, 420, 421, 422, 488, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, + 405, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421, + 422, 483, 484, 489, 488, 491, 490, 492, 493, 494, 495, 497, 496, 498, 499, 500, + 501, 502, 503, 504, 505, 506, 508, 507, 509, 510, 511, 512, 513, 514, 515, 516, + 517, 518, 519, 520, 521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532, + 533, 534, 535, 536, 537, 538, 539, 541, 540, 542, 543, 544, 545, 546, 547, 548, + 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, + 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, + 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, + 597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612, + 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, + 629, 490, 491, 492, 493, 494, 495, 497, 496, 498, 499, 500, 501, 502, 503, 504, + 505, 506, 508, 507, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, 520, + 521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, + 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 630, 549, 550, 551, 552, + 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, + 569, 570, 571, 572, 573, 574, 631, 588, 590, 589, 591, 592, 593, 594, 595, 596, + 597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612, + 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, + 632, 633, 634, 635, 365, 364, 363, 361, 362, 636, 637, 638, 639, 370, 371, 382, + 380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 640, 641, 642, 394, 393, 390, + 391, 392, 389, 388, 387, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, + 403, 406, 405, 408, 407, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419, + 420, 421, 422, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, + 659, 658, 660, 661, 663, 662, 664, 665, 643, 644, 395, 396, 398, 397, 399, 400, + 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, 415, + 418, 417, 419, 420, 421, 422, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, + 675, 677, 676, 678, 679, 680, 681, 682, 683, 684, 685, 687, 686, 688, 689, 690, + 691, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, + 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 692, + 693, 696, 694, 695, 697, 698, 701, 700, 699, 703, 702, 705, 704, 706, 707, 708, + 709, 710, 716, 714, 713, 715, 711, 712, 721, 720, 722, 719, 723, 718, 717, 724, + 725, 726, 729, 728, 727, 731, 734, 733, 732, 735, 730, 738, 737, 736, 742, 739, + 740, 741, 745, 746, 743, 744, 748, 749, 750, 747, 752, 754, 751, 753, 756, 758, + 757, 755, 760, 759, 761, 762, 763, 764, 767, 766, 768, 765, 771, 770, 769, 776, + 773, 774, 772, 777, 775, 783, 780, 779, 782, 778, 781, 784, 785, 786, 787, 789, + 790, 791, 788, 796, 793, 794, 795, 792, 797, 801, 798, 802, 800, 803, 799, 805, + 804, 807, 808, 806, 809, 810, 812, 811, 813, 815, 814, 816, 817, 818, 819, 820, + 821, 822, 823, 827, 825, 824, 826, 828, 829, 643, 644, 396, 395, 398, 397, 399, + 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, + 415, 417, 418, 419, 420, 421, 422, 830, 692, 633, 634, 635, 365, 364, 363, 361, + 362, 636, 637, 638, 639, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373, + 377, 381, 640, 641, 642, 394, 392, 393, 391, 390, 387, 388, 389, 643, 644, 396, + 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, + 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 831, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 663, 662, 664, 665, - 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, 637, - 403, 638, 639, 404, 405, 640, 406, 641, 407, 642, 408, 643, 644, 409, 832, 831, + 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, + 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 832, 831, 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 679, 678, 680, 681, 682, - 683, 685, 684, 687, 686, 688, 689, 690, 691, 630, 631, 395, 632, 396, 633, 397, - 398, 399, 634, 400, 635, 401, 636, 402, 637, 403, 638, 639, 404, 405, 640, 406, - 641, 407, 642, 408, 643, 644, 409, 833, 693, 695, 696, 697, 694, 701, 700, 698, + 683, 685, 684, 687, 686, 688, 689, 690, 691, 643, 644, 396, 395, 398, 397, 399, + 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, + 415, 418, 417, 419, 420, 421, 422, 833, 693, 695, 696, 697, 694, 701, 700, 698, 699, 703, 702, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715, 724, 722, 721, 719, 717, 718, 720, 723, 726, 725, 729, 727, 728, 733, 734, 735, 731, 732, 730, 737, 738, 736, 742, 740, 739, 741, 746, 745, 743, 744, 750, 747, 748, 749, 754, 752, 753, 751, 758, 755, 756, 757, 762, 763, 764, 760, 761, 759, 768, 765, 766, 767, 770, 769, 771, 777, 776, 774, 772, 773, 775, 781, 782, 780, 779, 778, 783, 785, 784, 786, 787, 788, 789, 790, 791, 796, 797, 794, 795, 793, - 792, 799, 800, 801, 802, 803, 798, 805, 806, 804, 808, 807, 813, 811, 810, 812, - 809, 814, 815, 816, 817, 818, 819, 822, 821, 820, 823, 825, 824, 826, 827, 828, - 829, 630, 631, 395, 632, 396, 633, 397, 398, 399, 634, 400, 635, 401, 636, 402, - 637, 403, 638, 639, 404, 640, 405, 641, 406, 642, 407, 408, 643, 644, 409, 834, - 833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 872, 873, 846, 847, - 849, 848, 851, 850, 852, 854, 853, 855, 856, 893, 894, 895, 896, 897, 898, 899, - 858, 857, 859, 860, 862, 861, 864, 863, 865, 868, 867, 866, 869, 871, 870, 872, - 873, 874, 875, 876, 878, 880, 879, 877, 883, 882, 881, 886, 884, 885, 887, 888, - 889, 892, 890, 891, 893, 894, 858, 857, 859, 860, 861, 862, 865, 863, 864, 868, - 866, 867, 870, 871, 869, 895, 896, 897, 874, 875, 876, 879, 878, 877, 880, 883, - 882, 881, 886, 884, 885, 888, 889, 887, 890, 891, 892, 898, 899, 905, 906, 907, - 908, 909, 912, 913, 900, 901, 902, 903, 904, 914, 905, 906, 907, 908, 909, 910, - 911, 912, 913, 914, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, + 792, 799, 800, 801, 802, 803, 798, 804, 805, 806, 808, 807, 811, 813, 812, 810, + 809, 814, 815, 816, 817, 818, 819, 823, 821, 820, 822, 827, 825, 824, 826, 829, + 828, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 406, 405, 408, + 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 834, + 833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 851, 848, + 850, 849, 854, 853, 852, 855, 856, 857, 858, 859, 860, 861, 862, 863, 864, 865, + 866, 868, 867, 871, 870, 869, 874, 872, 873, 875, 876, 877, 879, 880, 878, 846, + 847, 881, 882, 883, 884, 885, 886, 887, 890, 889, 888, 891, 892, 893, 896, 894, + 895, 899, 898, 897, 859, 860, 868, 866, 867, 870, 871, 869, 872, 873, 874, 876, + 875, 877, 879, 878, 880, 861, 862, 863, 881, 882, 883, 884, 885, 887, 886, 890, + 888, 889, 891, 892, 893, 896, 894, 895, 898, 897, 899, 864, 865, 900, 901, 902, + 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 900, 901, 902, 903, 904, 913, + 914, 905, 906, 912, 915, 916, 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, 927, 928, 929, 930, 931, 932, 933, 934, 935, 936, 937, 938, 939, 940, 941, 942, 943, 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, 963, 959, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, - 969, 974, 975, 976, 977, 978, 979, 980, 981, 996, 982, 997, 983, 984, 985, 986, - 987, 1001, 988, 989, 990, 991, 992, 993, 1002, 994, 995, 996, 997, 998, 998, 999, - 1000, 1001, 999, 1000, 1002, 1003, 1004, 1003, 1005, 1006, 1007, 1005, 1006, 1007, 1008, 1006, + 969, 974, 975, 976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, + 989, 990, 991, 992, 993, 994, 995, 996, 997, 998, 999, 982, 984, 1000, 1000, 1001, + 1002, 990, 1001, 1002, 997, 1003, 1004, 1003, 1005, 1006, 1007, 1005, 1006, 1007, 1008, 1006, 1008, 1006, 1009, 1011, 1006, 1010, 1013, 1011, 1009, 1006, 1012, 1013, 1010, 1008, 1006, 1008, 1006, 1014, 1006, 1015, 1016, 1014, 1006, 1015, 1008, 1006, 1008, 1006, 1017, 1006, 1018, 1017, 1006, 1018, 1008, 1006, 1008, 1006, 1019, 1020, 1019, 1020, 1019, 1020, 1019, 1020, 1019, 1020, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 7a423c5d2..fa59cdbff 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -600,7 +600,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} }, { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLI - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF450F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .HLT { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} }, @@ -645,10 +645,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDR - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07100000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, @@ -657,95 +657,95 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STR - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07000000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRB - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRB - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07400000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRH - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, 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}, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRSB - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRSH - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRD - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRD - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRT - { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRT - { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRBT - { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRBT - { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRHT - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRHT - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSBT - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSHT - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDA { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STL @@ -933,8 +933,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -956,8 +956,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -974,8 +974,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -993,8 +993,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMS { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, @@ -1003,8 +1003,8 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, // .VFNMA { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, @@ -1644,14 +1644,14 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VSHR { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VSRA { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSHL { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1662,18 +1662,18 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VRSHR { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSRA { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSLI - { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSRI - { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VQSHL { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1684,7 +1684,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSHRN { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQSHRUN { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHL @@ -1706,7 +1706,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {}, {.U64,.NONE} }, // .VQRSHRN { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHRUN { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHRN @@ -1715,7 +1715,7 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin 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rexcode/arm32: LDMIB/LDMDA/LDMDB and STMIB/STMDA/STMDB are their own mnemonics LDM and STM each held five A32 forms with identical operand shapes -- the four increment/decrement orders plus a writeback variant -- distinguished only by their fixed bits. Nothing could tell them apart, so the encoder always took the first and six of the eight A32 encodings were unreachable: `ldmib`, `ldmda`, `ldmdb`, `stmib`, `stmda`, `stmdb` could not be produced at all. They are not variants of one mnemonic in the first place. An assembler spells them `ldmib` / `ldmda` / `ldmdb`, with plain `ldm` meaning IA, so this follows the same rule as the rest of the enum: one member per name an assembler accepts. LDM/STM keep the IA order and the Thumb encodings; the other three orders become their own mnemonics, and the T32 DB encodings join them. All eight now encode, byte-exact against llvm-mc: ldm e8900006 stm e8800006 ldmib e9900006 stmib e9800006 ldmda e8100006 stmda e8000006 ldmdb e9100006 stmdb e9000006 Six test checks referenced these forms by index; they were re-derived by matching (bits, mask) against the rebuilt table rather than by adjusting offsets, and every one was found -- so no form was lost in the move. Writeback (`ldm r0!, {...}`) is still unreachable: it is a property of the base operand, not a separate mnemonic, and there is nowhere to put it yet. That is one form per family rather than four. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/mnemonic_builders.odin | 24 +++++++++ core/rexcode/isa/arm32/mnemonics.odin | 8 ++- .../isa/arm32/tablegen/encoding_table.odin | 33 +++++++----- .../tablegen/generated/decode_tables.odin | 50 +++++++++--------- .../tablegen/generated/encode_tables.odin | 32 +++++++---- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 11106 -> 11106 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38640 -> 38640 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4736 -> 4784 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38640 -> 38640 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3360 -> 3360 bytes core/rexcode/isa/arm32/tests/smoke.odin | 12 ++--- 11 files changed, 104 insertions(+), 55 deletions(-) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index e2932de71..ce36876c5 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -604,6 +604,18 @@ inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, r emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) } inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) } +inst_ldmib_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_ldmib_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmib_r_list(dst, regs)) } +inst_ldmda_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_ldmda_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmda_r_list(dst, regs)) } +inst_ldmdb_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_ldmdb_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldmdb_r_list(dst, regs)) } +inst_stmib_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_stmib_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmib_r_list(dst, regs)) } +inst_stmda_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_stmda_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmda_r_list(dst, regs)) } +inst_stmdb_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STMDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_stmdb_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stmdb_r_list(dst, regs)) } inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) } inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } @@ -1891,6 +1903,18 @@ inst_ldm :: inst_ldm_r_list emit_ldm :: emit_ldm_r_list inst_stm :: inst_stm_r_list emit_stm :: emit_stm_r_list +inst_ldmib :: inst_ldmib_r_list +emit_ldmib :: emit_ldmib_r_list +inst_ldmda :: inst_ldmda_r_list +emit_ldmda :: emit_ldmda_r_list +inst_ldmdb :: inst_ldmdb_r_list +emit_ldmdb :: emit_ldmdb_r_list +inst_stmib :: inst_stmib_r_list +emit_stmib :: emit_stmib_r_list +inst_stmda :: inst_stmda_r_list +emit_stmda :: emit_stmda_r_list +inst_stmdb :: inst_stmdb_r_list +emit_stmdb :: emit_stmdb_r_list inst_push :: inst_push_list emit_push :: emit_push_list inst_pop :: inst_pop_list diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index 13342b0b8..f7982e394 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -190,7 +190,13 @@ Mnemonic :: enum u16 { LDAEXD, STLEXD, // Block move - LDM, STM, // base mnemonic w/ IA/IB/DA/DB suffix flag + LDM, STM, // IA order (the default spelling) + // The other three increment/decrement orders are their own mnemonics -- + // that is how an assembler spells them, and it is the only way to reach + // their encodings: all four share one operand shape, so nothing else + // tells them apart. + LDMIB, LDMDA, LDMDB, + STMIB, STMDA, STMDB, // Stack convenience aliases PUSH, POP, diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index df4e1bbac..928039b5f 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1119,31 +1119,18 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMIA writeback (LDM Rn!, {reglist}): W=1 {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}}, - // LDMIB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}}, - // LDMDA - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}}, - // LDMDB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 LDMIA: 11001 Rb reg_list8 {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14 {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - // T32 LDMDB: high=11101001 0001 Rn low=PM 0 reg_list14 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STM = { {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}}, {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 STMIA: 11000 Rb reg_list8 {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STMIA: 0xE8800000 {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - // T32 STMDB: 0xE9000000 - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // PUSH / POP are conventional aliases for STMDB SP! / LDMIA SP! @@ -3748,5 +3735,25 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, // SPECGEN:END + .LDMIB = { + {.LDMIB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}}, + }, + .LDMDA = { + {.LDMDA, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}}, + }, + .LDMDB = { + {.LDMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.LDMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + }, + .STMIB = { + {.STMIB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}}, + }, + .STMDA = { + {.STMDA, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}}, + }, + .STMDB = { + {.STMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STMDB, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + }, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index bcb3ee5a1..fd06ea7a6 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -373,8 +373,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -400,8 +400,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -1014,20 +1014,20 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, @@ -1236,9 +1236,9 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1704,21 +1704,21 @@ DECODE_FORM_IDX := [1680]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, + 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 23, 25, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 25, 23, 0, 0, 0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 16, 14, 18, 12, 10, 6, - 0, 0, 0, 3, 5, 9, 7, 4, 6, 2, 8, 1, 0, 1, 0, 0, - 0, 0, 1, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0, + 0, 0, 0, 3, 5, 9, 7, 6, 4, 2, 8, 1, 0, 1, 0, 0, + 0, 1, 0, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0, 2, 0, 2, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 2, 0, 2, 0, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, 16, 12, 15, @@ -1755,8 +1755,8 @@ DECODE_FORM_IDX := [1680]u16{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, 0, - 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, - 0, 0, 0, 1, 0, 1, 4, 4, 0, 2, 2, 1, 0, 0, 1, 0, + 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9, 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3, @@ -1769,7 +1769,7 @@ DECODE_FORM_IDX := [1680]u16{ 5, 4, 6, 2, 0, 1, 3, 7, 13, 14, 0, 1, 1, 0, 3, 2, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 4, 1, 0, 1, 0, 16, 15, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 6, 7, 6, 7, 4, 4, + 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1797,7 +1797,7 @@ DECODE_FORM_IDX := [1680]u16{ 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, - 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 5, 5, 1, 1, 1, 2, + 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2, } @(rodata) @@ -2022,8 +2022,8 @@ DECODE_BUCKET_LIST := [5553]u16{ 1648, 1648, 1649, 1649, 1650, 1650, 1651, 1651, 1652, 1652, 1653, 1654, 1655, 1656, 1657, 1658, 1659, 1660, 1661, 1662, 1663, 1664, 1665, 1666, 1667, 1668, 1669, 1670, 1671, 1672, 1673, 1674, 1674, 1675, 1675, 1676, 1676, 1676, 1677, 1678, 1676, 1679, 1679, 1217, 1218, 1219, 1220, 1225, - 1231, 1221, 1230, 1231, 1230, 1228, 1226, 1228, 1224, 1226, 1214, 1215, 1222, 1231, 1210, 1211, - 1212, 1213, 1216, 1230, 1231, 1230, 1229, 1227, 1223, 1229, 1227, 1231, 1230, 1231, 1209, 1230, + 1231, 1221, 1230, 1231, 1230, 1227, 1226, 1227, 1224, 1226, 1214, 1215, 1222, 1231, 1210, 1211, + 1212, 1213, 1216, 1230, 1231, 1230, 1229, 1228, 1223, 1229, 1228, 1231, 1230, 1231, 1209, 1230, 1231, 1230, 1231, 1230, 1244, 1243, 1236, 1244, 1243, 1250, 1250, 1232, 1233, 1234, 1235, 1241, 1240, 1249, 1232, 1233, 1234, 1235, 1240, 1241, 1249, 1242, 1242, 1245, 1237, 1245, 1239, 1247, 1247, 1248, 1248, 1238, 1246, 1246, 1261, 1269, 1268, 1261, 1265, 1266, 1264, 1267, 1261, 1269, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index fa59cdbff..a7d733bdc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -801,21 +801,27 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .LDM { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STM { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + // .LDMIB + { .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + // .LDMDA + { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + // .LDMDB + { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + // .STMIB + { .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + // .STMDA + { .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + // .STMDB + { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PUSH { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, @@ -2506,8 +2512,14 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .STLEXH = { 563, 1}, .LDAEXD = { 564, 1}, .STLEXD = { 565, 1}, - .LDM = { 566, 8}, - .STM = { 574, 8}, + .LDM = { 566, 4}, + .STM = { 570, 4}, + .LDMIB = { 574, 1}, + .LDMDA = { 575, 1}, + .LDMDB = { 576, 2}, + .STMIB = { 578, 1}, + .STMDA = { 579, 1}, + .STMDB = { 580, 2}, .PUSH = { 582, 3}, .POP = { 585, 3}, .SWP = { 588, 1}, diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 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zRZO@$+YL_`pJcdXzhC2+J^69T5Dt71L*y!vw}*IRWN$V+s&FF%zB?q5s%I*Eat7B9 z7=9b$R>-;SD!&3hX)Lh>j5Y&)JYg*ACVVB~TV)0p#qH>!JOMu`*=`GX+r>ab{G|N8 z%kk3)-{JTfgzt9zEW)wLVEa14ce?tygl~6zJ>dh6UqHC>TW=Fr@RPbzHL3Vzge$)l zuM)1BRQv|QRp%9t2v>e9eh1;`$#%tK!d1K#zmM>VGJ{DS=KLCAOz!ODh<};z4o|jE z#YxiAH0v7{#=8tp7@ux<#JDMFF?>erT1u_5B`l18BKW=SsrV0c+4tKx;+~kk-DmJ?%Bp?liQG=z*>AXHe6HaM Date: Thu, 27 Aug 2026 03:04:31 -0400 Subject: [PATCH 22/89] rexcode/arm32: drop 15 duplicate forms the mnemonic merges introduced Collapsing the encoding-shaped mnemonics into their assembler names merged several form lists that already overlapped, leaving byte-identical Encoding rows inside one mnemonic. The matcher takes the first form that matches, so every duplicate was dead weight -- unreachable, and inflating both tables. VMUL, VMLA and VMLS each gained two from the *_LANE merge; VSHR, VSRA and VRSHR two each, VQSHRN, VQRSHRN and VSHLL one each. The branch base had none, so these are mine: the collision check I ran before each merge compared operand signatures, which is the right test for "can the matcher tell these apart", but says nothing about two forms being wholly identical. Comparing the full Encoding would have caught them. 1680 -> 1665 forms. Removing an unreachable exact duplicate cannot change behaviour, and does not: the load/store, LDM/STM and NEON data-type encode checks are byte-for-byte what they were, and the decode sweep still round-trips every form. Co-Authored-By: Claude Opus 5 (1M context) --- .../isa/arm32/tablegen/encoding_table.odin | 19 - .../tablegen/generated/decode_tables.odin | 2271 ++++++++--------- .../tablegen/generated/encode_tables.odin | 693 +++-- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 11106 -> 10794 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38640 -> 38295 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4784 -> 4784 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38640 -> 38295 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3360 -> 3330 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes 12 files changed, 1462 insertions(+), 1521 deletions(-) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 928039b5f..8f6e59141 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1743,9 +1743,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Integer Q-form .I16/.I32 (bit 24 = 1) {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - // FP .F32 D-form / Q-form (F=1, size=10) - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { @@ -1769,9 +1766,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - // FP .F32 (F=1) - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, @@ -1792,9 +1786,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - // FP .F32 - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { @@ -2087,9 +2078,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // VSHR immediate (signed/unsigned, .I8/.I16/.I32/.I64) .VSHR = { - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - // unsigned {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE imm form (imm6 at bits 21:16) @@ -2097,8 +2085,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // VSRA imm .VSRA = { - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE (imm6 at bits 21:16) @@ -2129,8 +2115,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // VRSHR (rounding shift right immediate) .VRSHR = { - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE @@ -2536,7 +2520,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VSHLL.S Q, D, #imm: 1111 0010 1 D imm6 Vd 1010 0 0 M 1 Vm // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1 // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, @@ -2553,12 +2536,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .VQSHRN = { // signed: 1111 0010 1 D imm6 Vd 1001 0 0 M 1 Vm; unsigned: U=1 {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRN = { // 1111 0010 1 D imm6 Vd 1001 0 1 M 1 Vm {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRUN = { // signed input, unsigned saturating shift right narrow: diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index fd06ea7a6..0f6aec39a 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1680]lib.Decode_Entry{ +DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -372,61 +372,52 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -447,10 +438,10 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -468,15 +459,12 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -519,8 +507,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -532,8 +520,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -549,8 +537,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -612,8 +600,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -667,12 +655,12 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -686,157 +674,154 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE_F, 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0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -844,30 +829,30 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -875,40 +860,40 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1049,8 +1034,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1059,8 +1044,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, @@ -1069,12 +1054,12 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1082,13 +1067,13 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, @@ -1127,8 +1112,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, @@ -1144,10 +1129,10 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, @@ -1162,55 +1147,55 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -1273,12 +1258,12 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, - { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1304,8 +1289,8 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1558,10 +1543,10 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1692,7 +1677,7 @@ DECODE_ENTRIES := [1680]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1680]u16{ +DECODE_FORM_IDX := [1665]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1704,104 +1689,104 @@ DECODE_FORM_IDX := [1680]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 22, 25, 23, 0, 0, - 0, 0, 11, 10, 11, 17, 13, 19, 20, 15, 16, 14, 18, 12, 10, 6, - 0, 0, 0, 3, 5, 9, 7, 6, 4, 2, 8, 1, 0, 1, 0, 0, - 0, 1, 0, 1, 3, 1, 3, 3, 1, 1, 1, 1, 5, 2, 0, 0, - 2, 0, 2, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, - 12, 11, 1, 7, 1, 6, 1, 6, 2, 0, 2, 0, 2, 0, 4, 4, - 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 22, 19, 13, 16, 12, 15, - 7, 6, 2, 8, 2, 7, 7, 2, 1, 3, 3, 1, 1, 3, 6, 6, - 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, - 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 12, 6, - 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, 6, 6, - 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, 3, 3, - 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, - 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, 1, - 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, - 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, - 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, - 14, 13, 4, 9, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, - 5, 5, 5, 5, 21, 23, 15, 17, 16, 14, 8, 7, 5, 10, 5, 9, - 9, 5, 7, 7, 0, 10, 3, 2, 1, 0, 3, 0, 1, 2, 0, 1, - 1, 0, 0, 0, 0, 9, 8, 3, 5, 4, 6, 7, 2, 8, 9, 6, - 4, 5, 2, 7, 3, 1, 0, 1, 0, 2, 3, 1, 2, 0, 5, 4, - 2, 1, 0, 13, 11, 10, 12, 13, 12, 14, 15, 15, 14, 13, 12, 16, - 15, 17, 14, 14, 17, 16, 15, 5, 0, 3, 2, 4, 1, 2, 0, 1, - 3, 2, 4, 3, 5, 1, 3, 0, 2, 4, 2, 1, 4, 5, 0, 3, - 0, 1, 1, 0, 3, 1, 2, 0, 5, 0, 3, 1, 4, 2, 5, 0, - 4, 3, 1, 2, 3, 1, 0, 2, 4, 2, 1, 3, 0, 4, 0, 1, - 0, 0, 0, 0, 3, 1, 0, 2, 3, 0, 2, 1, 2, 3, 3, 0, - 3, 0, 3, 3, 1, 0, 2, 1, 2, 0, 0, 1, 0, 1, 2, 2, - 0, 3, 2, 1, 1, 0, 2, 0, 1, 1, 0, 0, 0, 2, 0, 2, - 0, 0, 4, 6, 5, 0, 2, 1, 2, 1, 0, 2, 1, 0, 0, 2, - 1, 0, 0, 0, 7, 6, 5, 4, 2, 1, 0, 2, 1, 0, 0, 1, - 2, 0, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 23, 22, 25, 0, 0, + 0, 0, 10, 11, 18, 17, 15, 19, 14, 10, 13, 11, 12, 16, 20, 6, + 0, 0, 0, 5, 6, 7, 3, 9, 2, 8, 4, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 6, 1, 0, + 2, 2, 0, 2, 0, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, + 2, 19, 13, 12, 7, 6, 8, 2, 2, 7, 7, 2, 1, 3, 3, 1, + 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, + 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, + 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, + 13, 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, + 3, 4, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, + 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, + 1, 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, + 12, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, + 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, + 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, + 4, 4, 4, 20, 14, 13, 9, 4, 8, 4, 4, 8, 6, 6, 3, 5, + 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 8, 7, 10, 5, 5, + 9, 5, 9, 7, 7, 0, 10, 2, 3, 1, 0, 1, 0, 2, 3, 1, + 0, 1, 0, 0, 0, 0, 3, 7, 4, 8, 5, 2, 9, 6, 6, 3, + 7, 2, 8, 9, 5, 4, 0, 1, 0, 2, 1, 1, 5, 3, 4, 2, + 0, 2, 1, 0, 12, 13, 11, 10, 13, 12, 14, 15, 14, 15, 13, 12, + 16, 15, 17, 14, 15, 16, 17, 14, 1, 5, 0, 4, 2, 3, 1, 0, + 2, 3, 3, 2, 1, 5, 3, 0, 4, 1, 2, 2, 4, 1, 0, 5, + 3, 1, 0, 0, 1, 0, 3, 1, 2, 2, 5, 0, 1, 3, 4, 1, + 5, 3, 2, 4, 0, 2, 1, 3, 0, 4, 4, 0, 3, 2, 1, 0, + 1, 0, 0, 0, 0, 1, 3, 0, 2, 2, 3, 1, 0, 2, 3, 3, + 0, 3, 0, 3, 0, 3, 1, 2, 0, 1, 2, 1, 0, 1, 0, 2, + 2, 2, 3, 0, 1, 2, 1, 0, 0, 1, 0, 1, 0, 0, 2, 0, + 2, 0, 0, 6, 4, 5, 0, 1, 2, 1, 0, 2, 0, 2, 1, 1, + 2, 0, 0, 0, 0, 6, 7, 4, 5, 0, 2, 1, 2, 1, 0, 1, + 2, 0, 1, 0, 2, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, 0, - 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, - 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 9, - 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, - 0, 1, 0, 0, 0, 1, 0, 1, 1, 0, 0, 1, 4, 2, 1, 3, - 2, 1, 0, 27, 2, 2, 1, 0, 0, 1, 0, 0, 0, 0, 5, 26, - 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, 2, - 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 0, 1, 2, 2, 1, 0, - 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 2, 3, 5, 3, - 2, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, 1, - 0, 0, 1, 0, 1, 1, 2, 0, 20, 18, 19, 17, 11, 9, 8, 12, - 5, 4, 6, 2, 0, 1, 3, 7, 13, 14, 0, 1, 1, 0, 3, 2, - 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 4, 1, 0, 1, 0, - 16, 15, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, - 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, - 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, - 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, 0, - 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, 29, - 28, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, - 4, 6, 0, 0, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, - 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, - 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, - 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, - 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, - 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, + 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, + 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, + 9, 7, 9, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, 1, 0, 1, + 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1, 4, 2, 1, + 3, 2, 0, 1, 27, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, + 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, + 2, 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 0, 1, 2, 2, 0, + 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 2, 3, 5, + 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, + 1, 0, 1, 0, 0, 1, 1, 0, 2, 17, 18, 14, 19, 11, 12, 8, + 6, 5, 7, 9, 13, 1, 0, 2, 3, 4, 20, 1, 0, 1, 0, 3, + 0, 1, 2, 0, 1, 1, 0, 0, 1, 0, 1, 0, 4, 1, 0, 0, + 1, 15, 16, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, + 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, + 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, + 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, + 28, 29, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, + 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, + 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, + 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, + 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, + 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, + 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, + 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, + 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, 1, - 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, 0, - 1, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, - 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, - 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, - 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, - 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, - 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, - 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, + 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 0, 1, + 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, + 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, + 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, + 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, + 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, + 2, } @(rodata) -DECODE_BUCKET_LIST := [5553]u16{ +DECODE_BUCKET_LIST := [5397]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1839,317 +1824,307 @@ DECODE_BUCKET_LIST := [5553]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 362, 361, 365, 363, - 364, 366, 367, 368, 369, 370, 371, 373, 372, 376, 379, 375, 377, 381, 374, 380, - 382, 378, 383, 384, 385, 386, 389, 387, 390, 393, 391, 388, 394, 392, 395, 396, - 398, 397, 399, 400, 402, 401, 404, 403, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, - 429, 430, 431, 432, 433, 434, 435, 437, 436, 438, 439, 440, 441, 443, 442, 445, - 444, 446, 447, 448, 449, 396, 395, 397, 398, 399, 400, 401, 402, 404, 403, 405, - 406, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421, - 422, 450, 423, 451, 452, 453, 454, 455, 456, 457, 458, 459, 461, 460, 463, 462, - 464, 465, 466, 467, 469, 468, 470, 471, 472, 473, 474, 475, 476, 477, 478, 479, - 480, 481, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 405, 406, 407, 408, - 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419, 420, 421, 422, 482, 396, - 395, 397, 398, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, - 412, 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 483, 484, 485, 482, 358, - 359, 360, 365, 364, 363, 362, 361, 366, 367, 368, 369, 370, 371, 382, 381, 380, - 379, 378, 377, 376, 374, 373, 372, 375, 383, 384, 385, 386, 394, 393, 392, 391, - 389, 390, 388, 387, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 406, 405, - 408, 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, - 486, 424, 425, 426, 427, 428, 429, 430, 431, 432, 433, 435, 434, 436, 437, 438, - 439, 441, 440, 442, 443, 445, 444, 446, 447, 448, 449, 396, 395, 398, 397, 399, - 400, 402, 401, 403, 404, 405, 406, 408, 407, 409, 410, 411, 412, 413, 414, 416, - 415, 417, 418, 419, 420, 421, 422, 487, 486, 451, 452, 453, 454, 455, 456, 457, - 458, 459, 460, 461, 463, 462, 464, 465, 466, 467, 469, 468, 470, 471, 473, 472, - 475, 474, 477, 476, 478, 479, 480, 481, 396, 395, 398, 397, 399, 400, 402, 401, - 404, 403, 406, 405, 407, 408, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, - 419, 420, 421, 422, 488, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, - 405, 407, 408, 409, 410, 411, 412, 414, 413, 415, 416, 417, 418, 419, 420, 421, - 422, 483, 484, 489, 488, 491, 490, 492, 493, 494, 495, 497, 496, 498, 499, 500, - 501, 502, 503, 504, 505, 506, 508, 507, 509, 510, 511, 512, 513, 514, 515, 516, - 517, 518, 519, 520, 521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532, - 533, 534, 535, 536, 537, 538, 539, 541, 540, 542, 543, 544, 545, 546, 547, 548, - 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, - 565, 566, 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, - 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, - 597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612, - 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, - 629, 490, 491, 492, 493, 494, 495, 497, 496, 498, 499, 500, 501, 502, 503, 504, - 505, 506, 508, 507, 509, 511, 510, 512, 513, 514, 515, 516, 517, 518, 519, 520, - 521, 522, 524, 523, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, - 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 630, 549, 550, 551, 552, - 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, - 569, 570, 571, 572, 573, 574, 631, 588, 590, 589, 591, 592, 593, 594, 595, 596, - 597, 598, 599, 600, 601, 602, 604, 603, 605, 606, 607, 608, 609, 610, 611, 612, - 613, 614, 615, 616, 617, 618, 619, 620, 621, 622, 623, 624, 625, 626, 627, 628, - 632, 633, 634, 635, 365, 364, 363, 361, 362, 636, 637, 638, 639, 370, 371, 382, - 380, 379, 381, 378, 375, 376, 377, 374, 373, 372, 640, 641, 642, 394, 393, 390, - 391, 392, 389, 388, 387, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, - 403, 406, 405, 408, 407, 409, 410, 411, 412, 413, 414, 416, 415, 418, 417, 419, - 420, 421, 422, 645, 646, 647, 648, 649, 650, 651, 652, 653, 654, 655, 656, 657, - 659, 658, 660, 661, 663, 662, 664, 665, 643, 644, 395, 396, 398, 397, 399, 400, - 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, 415, - 418, 417, 419, 420, 421, 422, 666, 645, 667, 668, 669, 670, 671, 672, 673, 674, - 675, 677, 676, 678, 679, 680, 681, 682, 683, 684, 685, 687, 686, 688, 689, 690, - 691, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, - 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 692, - 693, 696, 694, 695, 697, 698, 701, 700, 699, 703, 702, 705, 704, 706, 707, 708, - 709, 710, 716, 714, 713, 715, 711, 712, 721, 720, 722, 719, 723, 718, 717, 724, - 725, 726, 729, 728, 727, 731, 734, 733, 732, 735, 730, 738, 737, 736, 742, 739, - 740, 741, 745, 746, 743, 744, 748, 749, 750, 747, 752, 754, 751, 753, 756, 758, - 757, 755, 760, 759, 761, 762, 763, 764, 767, 766, 768, 765, 771, 770, 769, 776, - 773, 774, 772, 777, 775, 783, 780, 779, 782, 778, 781, 784, 785, 786, 787, 789, - 790, 791, 788, 796, 793, 794, 795, 792, 797, 801, 798, 802, 800, 803, 799, 805, - 804, 807, 808, 806, 809, 810, 812, 811, 813, 815, 814, 816, 817, 818, 819, 820, - 821, 822, 823, 827, 825, 824, 826, 828, 829, 643, 644, 396, 395, 398, 397, 399, - 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, - 415, 417, 418, 419, 420, 421, 422, 830, 692, 633, 634, 635, 365, 364, 363, 361, - 362, 636, 637, 638, 639, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373, - 377, 381, 640, 641, 642, 394, 392, 393, 391, 390, 387, 388, 389, 643, 644, 396, - 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, - 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 831, 646, 647, 648, 649, - 650, 651, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 663, 662, 664, 665, - 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 404, 403, 406, 405, 408, 407, - 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 832, 831, - 667, 668, 669, 670, 671, 672, 673, 674, 675, 676, 677, 679, 678, 680, 681, 682, - 683, 685, 684, 687, 686, 688, 689, 690, 691, 643, 644, 396, 395, 398, 397, 399, - 400, 402, 401, 404, 403, 406, 405, 408, 407, 409, 410, 411, 412, 414, 413, 416, - 415, 418, 417, 419, 420, 421, 422, 833, 693, 695, 696, 697, 694, 701, 700, 698, - 699, 703, 702, 704, 705, 706, 707, 708, 716, 713, 714, 712, 711, 709, 710, 715, - 724, 722, 721, 719, 717, 718, 720, 723, 726, 725, 729, 727, 728, 733, 734, 735, - 731, 732, 730, 737, 738, 736, 742, 740, 739, 741, 746, 745, 743, 744, 750, 747, - 748, 749, 754, 752, 753, 751, 758, 755, 756, 757, 762, 763, 764, 760, 761, 759, - 768, 765, 766, 767, 770, 769, 771, 777, 776, 774, 772, 773, 775, 781, 782, 780, - 779, 778, 783, 785, 784, 786, 787, 788, 789, 790, 791, 796, 797, 794, 795, 793, - 792, 799, 800, 801, 802, 803, 798, 804, 805, 806, 808, 807, 811, 813, 812, 810, - 809, 814, 815, 816, 817, 818, 819, 823, 821, 820, 822, 827, 825, 824, 826, 829, - 828, 643, 644, 396, 395, 398, 397, 399, 400, 402, 401, 403, 404, 406, 405, 408, - 407, 409, 410, 411, 412, 414, 413, 416, 415, 418, 417, 419, 420, 421, 422, 834, - 833, 835, 836, 837, 838, 839, 840, 841, 842, 843, 844, 845, 846, 847, 851, 848, - 850, 849, 854, 853, 852, 855, 856, 857, 858, 859, 860, 861, 862, 863, 864, 865, - 866, 868, 867, 871, 870, 869, 874, 872, 873, 875, 876, 877, 879, 880, 878, 846, - 847, 881, 882, 883, 884, 885, 886, 887, 890, 889, 888, 891, 892, 893, 896, 894, - 895, 899, 898, 897, 859, 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1567, 1568, + 1310, 1570, 1313, 1314, 1317, 1318, 1319, 1320, 1321, 1322, 1331, 1332, 1333, 1334, 1583, 1554, + 1277, 1278, 1293, 1294, 1295, 1560, 1306, 1307, 1565, 1566, 1567, 1568, 1310, 1570, 1313, 1314, + 1317, 1318, 1319, 1320, 1321, 1322, 1331, 1332, 1333, 1334, 1579, 1583, 1277, 1278, 1293, 1294, + 1295, 1560, 1307, 1565, 1566, 1567, 1568, 1310, 1570, 1313, 1314, 1317, 1318, 1319, 1320, 1321, + 1322, 1331, 1332, 1333, 1334, 1579, 1583, 1277, 1278, 1293, 1294, 1295, 1560, 1307, 1565, 1566, + 1567, 1568, 1310, 1570, 1313, 1314, 1317, 1318, 1319, 1320, 1321, 1322, 1331, 1332, 1333, 1334, + 1579, 1583, 1538, 1548, 1549, 1277, 1278, 1279, 1293, 1294, 1295, 1296, 1560, 1305, 1307, 1565, + 1566, 1567, 1568, 1310, 1570, 1313, 1314, 1317, 1318, 1319, 1320, 1321, 1322, 1331, 1332, 1333, + 1334, 1579, 1583, 1255, 1256, 1288, 1289, 1290, 1291, 1299, 1300, 1301, 1302, 1561, 1562, 1563, + 1564, 1570, 1315, 1316, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1575, 1576, 1577, 1578, + 1352, 1581, 1584, 1561, 1562, 1563, 1564, 1570, 1315, 1316, 1323, 1324, 1325, 1326, 1327, 1328, + 1329, 1330, 1581, 1584, 1561, 1562, 1563, 1564, 1570, 1315, 1316, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1581, 1584, 1546, 1547, 1286, 1287, 1297, 1298, 1303, 1304, 1561, 1562, 1563, + 1564, 1570, 1315, 1316, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1571, 1572, 1573, 1574, + 1581, 1584, 1288, 1289, 1290, 1291, 1299, 1300, 1301, 1302, 1561, 1562, 1563, 1564, 1570, 1315, + 1316, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1575, 1576, 1577, 1578, 1352, 1580, 1582, + 1584, 1561, 1562, 1563, 1564, 1570, 1315, 1316, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, + 1580, 1582, 1584, 1257, 1258, 1259, 1260, 1269, 1270, 1271, 1272, 1561, 1562, 1563, 1564, 1570, + 1315, 1316, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1580, 1582, 1584, 1546, 1547, 1267, + 1268, 1286, 1287, 1297, 1298, 1303, 1304, 1561, 1562, 1563, 1564, 1570, 1315, 1316, 1323, 1324, + 1325, 1326, 1327, 1328, 1329, 1330, 1571, 1572, 1573, 1574, 1580, 1582, 1584, 1558, 1559, 1560, + 1308, 1569, 1311, 1570, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, + 1559, 1560, 1308, 1569, 1311, 1570, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, + 1345, 1346, 1560, 1569, 1309, 1312, 1570, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + 1344, 1345, 1346, 1560, 1569, 1309, 1312, 1570, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, + 1343, 1344, 1345, 1346, 1558, 1559, 1560, 1308, 1569, 1311, 1570, 1335, 1336, 1337, 1338, 1339, + 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1559, 1560, 1308, 1569, 1311, 1570, 1335, 1336, 1337, + 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1560, 1309, 1569, 1312, 1570, 1335, 1336, + 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1560, 1569, 1309, 1312, 1570, 1335, + 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1570, 1349, 1350, 1351, 1570, + 1349, 1350, 1351, 1570, 1349, 1350, 1351, 1540, 1541, 1542, 1543, 1544, 1545, 1550, 1551, 1552, + 1553, 1555, 1556, 1557, 1570, 1349, 1350, 1351, 1570, 1349, 1350, 1351, 1570, 1349, 1350, 1351, + 1570, 1349, 1350, 1351, 1540, 1541, 1542, 1543, 1544, 1545, 1550, 1551, 1552, 1553, 1555, 1556, + 1557, 1570, 1349, 1350, 1351, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2193,608 +2168,608 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x25 = { 477, 51}, 0x26 = { 528, 54}, 0x27 = { 582, 19}, - 0x28 = { 601, 66}, - 0x29 = { 667, 56}, - 0x2A = { 723, 60}, - 0x2B = { 783, 32}, - 0x2C = { 815, 66}, - 0x2D = { 881, 56}, - 0x2E = { 937, 60}, - 0x2F = { 997, 32}, - 0x30 = { 1029, 59}, - 0x31 = { 1088, 27}, - 0x32 = { 1115, 45}, - 0x33 = { 1160, 9}, - 0x34 = { 1169, 59}, - 0x35 = { 1228, 27}, - 0x36 = { 1255, 33}, - 0x37 = { 1288, 9}, - 0x38 = { 1297, 67}, - 0x39 = { 1364, 52}, - 0x3A = { 1416, 56}, - 0x3B = { 1472, 169}, - 0x3C = { 1641, 67}, - 0x3D = { 1708, 52}, - 0x3E = { 1760, 56}, - 0x3F = { 1816, 169}, - 0x40 = { 1985, 12}, - 0x41 = { 1997, 1}, - 0x42 = { 1998, 12}, - 0x43 = { 2010, 1}, - 0x44 = { 2011, 1}, - 0x45 = { 2012, 2}, - 0x46 = { 2014, 1}, - 0x47 = { 2015, 1}, - 0x48 = { 2016, 16}, - 0x49 = { 2032, 1}, - 0x4A = { 2033, 20}, - 0x4B = { 2053, 1}, - 0x4C = { 2054, 16}, - 0x4D = { 2070, 2}, - 0x4E = { 2072, 20}, - 0x4F = { 2092, 1}, - 0x50 = { 2093, 1}, - 0x51 = { 2094, 1}, - 0x52 = { 2095, 1}, - 0x53 = { 2096, 1}, - 0x54 = { 2097, 1}, - 0x55 = { 2098, 1}, - 0x56 = { 2099, 1}, - 0x57 = { 2100, 6}, - 0x58 = { 2106, 1}, - 0x59 = { 2107, 1}, - 0x5A = { 2108, 1}, - 0x5B = { 2109, 1}, - 0x5C = { 2110, 1}, - 0x5D = { 2111, 3}, - 0x5E = { 2114, 1}, - 0x5F = { 2115, 1}, - 0x61 = { 2116, 6}, - 0x62 = { 2122, 6}, - 0x63 = { 2128, 6}, - 0x65 = { 2134, 6}, - 0x66 = { 2140, 6}, - 0x67 = { 2146, 6}, - 0x68 = { 2152, 5}, - 0x6A = { 2157, 4}, - 0x6B = { 2161, 5}, - 0x6C = { 2166, 2}, - 0x6E = { 2168, 4}, - 0x6F = { 2172, 5}, - 0x70 = { 2177, 9}, - 0x71 = { 2186, 2}, - 0x73 = { 2188, 1}, - 0x74 = { 2189, 5}, - 0x75 = { 2194, 7}, - 0x78 = { 2201, 3}, - 0x79 = { 2204, 1}, - 0x7A = { 2205, 1}, - 0x7B = { 2206, 1}, - 0x7C = { 2207, 3}, - 0x7D = { 2210, 3}, - 0x7E = { 2213, 1}, - 0x7F = { 2214, 2}, - 0x80 = { 2216, 1}, - 0x81 = { 2217, 2}, - 0x82 = { 2219, 1}, - 0x83 = { 2220, 2}, - 0x84 = { 2222, 1}, - 0x85 = { 2223, 1}, - 0x86 = { 2224, 1}, - 0x87 = { 2225, 1}, - 0x88 = { 2226, 2}, - 0x89 = { 2228, 3}, - 0x8A = { 2231, 2}, - 0x8B = { 2233, 4}, - 0x8C = { 2237, 1}, - 0x8D = { 2238, 1}, - 0x8E = { 2239, 1}, - 0x8F = { 2240, 1}, - 0x90 = { 2241, 1}, - 0x91 = { 2242, 2}, - 0x92 = { 2244, 2}, - 0x93 = { 2246, 2}, - 0x94 = { 2248, 1}, - 0x95 = { 2249, 1}, - 0x96 = { 2250, 1}, - 0x97 = { 2251, 1}, - 0x98 = { 2252, 1}, - 0x99 = { 2253, 2}, - 0x9A = { 2255, 1}, - 0x9B = { 2256, 2}, - 0x9C = { 2258, 1}, - 0x9D = { 2259, 1}, - 0x9E = { 2260, 1}, - 0x9F = { 2261, 1}, - 0xA0 = { 2262, 2}, - 0xA1 = { 2264, 2}, - 0xA2 = { 2266, 2}, - 0xA3 = { 2268, 2}, - 0xA4 = { 2270, 2}, - 0xA5 = { 2272, 2}, - 0xA6 = { 2274, 2}, - 0xA7 = { 2276, 2}, - 0xA8 = { 2278, 2}, - 0xA9 = { 2280, 2}, - 0xAA = { 2282, 2}, - 0xAB = { 2284, 2}, - 0xAC = { 2286, 2}, - 0xAD = { 2288, 2}, - 0xAE = { 2290, 2}, - 0xAF = { 2292, 2}, - 0xB0 = { 2294, 2}, - 0xB1 = { 2296, 2}, - 0xB2 = { 2298, 2}, - 0xB3 = { 2300, 2}, - 0xB4 = { 2302, 2}, - 0xB5 = { 2304, 2}, - 0xB6 = { 2306, 2}, - 0xB7 = { 2308, 2}, - 0xB8 = { 2310, 2}, - 0xB9 = { 2312, 2}, - 0xBA = { 2314, 2}, - 0xBB = { 2316, 2}, - 0xBC = { 2318, 2}, - 0xBD = { 2320, 2}, - 0xBE = { 2322, 2}, - 0xBF = { 2324, 2}, - 0xC0 = { 2326, 7}, - 0xC1 = { 2333, 4}, - 0xC2 = { 2337, 12}, - 0xC3 = { 2349, 5}, - 0xC4 = { 2354, 11}, - 0xC5 = { 2365, 8}, - 0xC6 = { 2373, 12}, - 0xC7 = { 2385, 5}, - 0xC8 = { 2390, 6}, - 0xC9 = { 2396, 6}, - 0xCA = { 2402, 12}, - 0xCB = { 2414, 8}, - 0xCC = { 2422, 6}, - 0xCD = { 2428, 6}, - 0xCE = { 2434, 12}, - 0xCF = { 2446, 6}, - 0xD0 = { 2452, 4}, - 0xD1 = { 2456, 4}, - 0xD2 = { 2460, 4}, - 0xD3 = { 2464, 2}, - 0xD4 = { 2466, 4}, - 0xD5 = { 2470, 4}, - 0xD6 = { 2474, 2}, - 0xD7 = { 2476, 2}, - 0xD8 = { 2478, 4}, - 0xD9 = { 2482, 4}, - 0xDA = { 2486, 2}, - 0xDB = { 2488, 2}, - 0xDC = { 2490, 4}, - 0xDD = { 2494, 4}, - 0xDE = { 2498, 2}, - 0xDF = { 2500, 2}, - 0xE0 = { 2502, 20}, - 0xE1 = { 2522, 14}, - 0xE2 = { 2536, 20}, - 0xE3 = { 2556, 15}, - 0xE4 = { 2571, 18}, - 0xE5 = { 2589, 13}, - 0xE6 = { 2602, 19}, - 0xE7 = { 2621, 15}, - 0xE8 = { 2636, 15}, - 0xE9 = { 2651, 11}, - 0xEA = { 2662, 11}, - 0xEB = { 2673, 77}, - 0xEC = { 2750, 16}, - 0xED = { 2766, 11}, - 0xEE = { 2777, 13}, - 0xEF = { 2790, 78}, - 0xF0 = { 2868, 3}, - 0xF1 = { 2871, 3}, - 0xF2 = { 2874, 3}, - 0xF3 = { 2877, 3}, - 0xF4 = { 2880, 3}, - 0xF5 = { 2883, 3}, - 0xF6 = { 2886, 3}, - 0xF7 = { 2889, 3}, - 0xF8 = { 2892, 1}, - 0xF9 = { 2893, 1}, - 0xFA = { 2894, 1}, - 0xFB = { 2895, 1}, - 0xFC = { 2896, 1}, - 0xFD = { 2897, 1}, - 0xFE = { 2898, 1}, - 0xFF = { 2899, 1}, + 0x28 = { 601, 57}, + 0x29 = { 658, 47}, + 0x2A = { 705, 48}, + 0x2B = { 753, 23}, + 0x2C = { 776, 57}, + 0x2D = { 833, 47}, + 0x2E = { 880, 48}, + 0x2F = { 928, 23}, + 0x30 = { 951, 59}, + 0x31 = { 1010, 27}, + 0x32 = { 1037, 45}, + 0x33 = { 1082, 9}, + 0x34 = { 1091, 59}, + 0x35 = { 1150, 27}, + 0x36 = { 1177, 33}, + 0x37 = { 1210, 9}, + 0x38 = { 1219, 58}, + 0x39 = { 1277, 43}, + 0x3A = { 1320, 44}, + 0x3B = { 1364, 160}, + 0x3C = { 1524, 58}, + 0x3D = { 1582, 43}, + 0x3E = { 1625, 44}, + 0x3F = { 1669, 160}, + 0x40 = { 1829, 12}, + 0x41 = { 1841, 1}, + 0x42 = { 1842, 12}, + 0x43 = { 1854, 1}, + 0x44 = { 1855, 1}, + 0x45 = { 1856, 2}, + 0x46 = { 1858, 1}, + 0x47 = { 1859, 1}, + 0x48 = { 1860, 16}, + 0x49 = { 1876, 1}, + 0x4A = { 1877, 20}, + 0x4B = { 1897, 1}, + 0x4C = { 1898, 16}, + 0x4D = { 1914, 2}, + 0x4E = { 1916, 20}, + 0x4F = { 1936, 1}, + 0x50 = { 1937, 1}, + 0x51 = { 1938, 1}, + 0x52 = { 1939, 1}, + 0x53 = { 1940, 1}, + 0x54 = { 1941, 1}, + 0x55 = { 1942, 1}, + 0x56 = { 1943, 1}, + 0x57 = { 1944, 6}, + 0x58 = { 1950, 1}, + 0x59 = { 1951, 1}, + 0x5A = { 1952, 1}, + 0x5B = { 1953, 1}, + 0x5C = { 1954, 1}, + 0x5D = { 1955, 3}, + 0x5E = { 1958, 1}, + 0x5F = { 1959, 1}, + 0x61 = { 1960, 6}, + 0x62 = { 1966, 6}, + 0x63 = { 1972, 6}, + 0x65 = { 1978, 6}, + 0x66 = { 1984, 6}, + 0x67 = { 1990, 6}, + 0x68 = { 1996, 5}, + 0x6A = { 2001, 4}, + 0x6B = { 2005, 5}, + 0x6C = { 2010, 2}, + 0x6E = { 2012, 4}, + 0x6F = { 2016, 5}, + 0x70 = { 2021, 9}, + 0x71 = { 2030, 2}, + 0x73 = { 2032, 1}, + 0x74 = { 2033, 5}, + 0x75 = { 2038, 7}, + 0x78 = { 2045, 3}, + 0x79 = { 2048, 1}, + 0x7A = { 2049, 1}, + 0x7B = { 2050, 1}, + 0x7C = { 2051, 3}, + 0x7D = { 2054, 3}, + 0x7E = { 2057, 1}, + 0x7F = { 2058, 2}, + 0x80 = { 2060, 1}, + 0x81 = { 2061, 2}, + 0x82 = { 2063, 1}, + 0x83 = { 2064, 2}, + 0x84 = { 2066, 1}, + 0x85 = { 2067, 1}, + 0x86 = { 2068, 1}, + 0x87 = { 2069, 1}, + 0x88 = { 2070, 2}, + 0x89 = { 2072, 3}, + 0x8A = { 2075, 2}, + 0x8B = { 2077, 4}, + 0x8C = { 2081, 1}, + 0x8D = { 2082, 1}, + 0x8E = { 2083, 1}, + 0x8F = { 2084, 1}, + 0x90 = { 2085, 1}, + 0x91 = { 2086, 2}, + 0x92 = { 2088, 2}, + 0x93 = { 2090, 2}, + 0x94 = { 2092, 1}, + 0x95 = { 2093, 1}, + 0x96 = { 2094, 1}, + 0x97 = { 2095, 1}, + 0x98 = { 2096, 1}, + 0x99 = { 2097, 2}, + 0x9A = { 2099, 1}, + 0x9B = { 2100, 2}, + 0x9C = { 2102, 1}, + 0x9D = { 2103, 1}, + 0x9E = { 2104, 1}, + 0x9F = { 2105, 1}, + 0xA0 = { 2106, 2}, + 0xA1 = { 2108, 2}, + 0xA2 = { 2110, 2}, + 0xA3 = { 2112, 2}, + 0xA4 = { 2114, 2}, + 0xA5 = { 2116, 2}, + 0xA6 = { 2118, 2}, + 0xA7 = { 2120, 2}, + 0xA8 = { 2122, 2}, + 0xA9 = { 2124, 2}, + 0xAA = { 2126, 2}, + 0xAB = { 2128, 2}, + 0xAC = { 2130, 2}, + 0xAD = { 2132, 2}, + 0xAE = { 2134, 2}, + 0xAF = { 2136, 2}, + 0xB0 = { 2138, 2}, + 0xB1 = { 2140, 2}, + 0xB2 = { 2142, 2}, + 0xB3 = { 2144, 2}, + 0xB4 = { 2146, 2}, + 0xB5 = { 2148, 2}, + 0xB6 = { 2150, 2}, + 0xB7 = { 2152, 2}, + 0xB8 = { 2154, 2}, + 0xB9 = { 2156, 2}, + 0xBA = { 2158, 2}, + 0xBB = { 2160, 2}, + 0xBC = { 2162, 2}, + 0xBD = { 2164, 2}, + 0xBE = { 2166, 2}, + 0xBF = { 2168, 2}, + 0xC0 = { 2170, 7}, + 0xC1 = { 2177, 4}, + 0xC2 = { 2181, 12}, + 0xC3 = { 2193, 5}, + 0xC4 = { 2198, 11}, + 0xC5 = { 2209, 8}, + 0xC6 = { 2217, 12}, + 0xC7 = { 2229, 5}, + 0xC8 = { 2234, 6}, + 0xC9 = { 2240, 6}, + 0xCA = { 2246, 12}, + 0xCB = { 2258, 8}, + 0xCC = { 2266, 6}, + 0xCD = { 2272, 6}, + 0xCE = { 2278, 12}, + 0xCF = { 2290, 6}, + 0xD0 = { 2296, 4}, + 0xD1 = { 2300, 4}, + 0xD2 = { 2304, 4}, + 0xD3 = { 2308, 2}, + 0xD4 = { 2310, 4}, + 0xD5 = { 2314, 4}, + 0xD6 = { 2318, 2}, + 0xD7 = { 2320, 2}, + 0xD8 = { 2322, 4}, + 0xD9 = { 2326, 4}, + 0xDA = { 2330, 2}, + 0xDB = { 2332, 2}, + 0xDC = { 2334, 4}, + 0xDD = { 2338, 4}, + 0xDE = { 2342, 2}, + 0xDF = { 2344, 2}, + 0xE0 = { 2346, 20}, + 0xE1 = { 2366, 14}, + 0xE2 = { 2380, 20}, + 0xE3 = { 2400, 15}, + 0xE4 = { 2415, 18}, + 0xE5 = { 2433, 13}, + 0xE6 = { 2446, 19}, + 0xE7 = { 2465, 15}, + 0xE8 = { 2480, 15}, + 0xE9 = { 2495, 11}, + 0xEA = { 2506, 11}, + 0xEB = { 2517, 77}, + 0xEC = { 2594, 16}, + 0xED = { 2610, 11}, + 0xEE = { 2621, 13}, + 0xEF = { 2634, 78}, + 0xF0 = { 2712, 3}, + 0xF1 = { 2715, 3}, + 0xF2 = { 2718, 3}, + 0xF3 = { 2721, 3}, + 0xF4 = { 2724, 3}, + 0xF5 = { 2727, 3}, + 0xF6 = { 2730, 3}, + 0xF7 = { 2733, 3}, + 0xF8 = { 2736, 1}, + 0xF9 = { 2737, 1}, + 0xFA = { 2738, 1}, + 0xFB = { 2739, 1}, + 0xFC = { 2740, 1}, + 0xFD = { 2741, 1}, + 0xFE = { 2742, 1}, + 0xFF = { 2743, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2900, 23}, - 0x75 = { 2923, 19}, - 0x76 = { 2942, 19}, - 0x77 = { 2961, 104}, - 0x78 = { 3065, 31}, - 0x79 = { 3096, 38}, - 0x7A = { 3134, 23}, - 0x7B = { 3157, 14}, - 0x7C = { 3171, 20}, - 0x7D = { 3191, 71}, - 0x7E = { 3262, 23}, - 0x7F = { 3285, 126}, + 0x74 = { 2744, 23}, + 0x75 = { 2767, 19}, + 0x76 = { 2786, 19}, + 0x77 = { 2805, 104}, + 0x78 = { 2909, 31}, + 0x79 = { 2940, 38}, + 0x7A = { 2978, 23}, + 0x7B = { 3001, 14}, + 0x7C = { 3015, 20}, + 0x7D = { 3035, 71}, + 0x7E = { 3106, 23}, + 0x7F = { 3129, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3411, 1}, - 0x01 = { 3412, 1}, - 0x02 = { 3413, 1}, - 0x03 = { 3414, 1}, - 0x04 = { 3415, 1}, - 0x05 = { 3416, 1}, - 0x06 = { 3417, 2}, - 0x07 = { 3419, 2}, - 0x08 = { 3421, 1}, - 0x09 = { 3422, 1}, - 0x0A = { 3423, 1}, - 0x0B = { 3424, 1}, - 0x0C = { 3425, 1}, - 0x0D = { 3426, 1}, - 0x0E = { 3427, 1}, - 0x0F = { 3428, 1}, - 0x10 = { 3429, 16}, - 0x11 = { 3445, 7}, - 0x12 = { 3452, 1}, - 0x13 = { 3453, 1}, - 0x14 = { 3454, 2}, - 0x15 = { 3456, 2}, - 0x16 = { 3458, 2}, - 0x17 = { 3460, 2}, - 0x18 = { 3462, 1}, - 0x19 = { 3463, 1}, - 0x1A = { 3464, 1}, - 0x1B = { 3465, 1}, - 0x1C = { 3466, 1}, - 0x1D = { 3467, 1}, - 0x1E = { 3468, 1}, - 0x1F = { 3469, 1}, - 0x20 = { 3470, 1}, - 0x21 = { 3471, 1}, - 0x22 = { 3472, 1}, - 0x23 = { 3473, 1}, - 0x24 = { 3474, 1}, - 0x25 = { 3475, 1}, - 0x26 = { 3476, 1}, - 0x27 = { 3477, 1}, - 0x28 = { 3478, 1}, - 0x29 = { 3479, 1}, - 0x2A = { 3480, 1}, - 0x2B = { 3481, 1}, - 0x2C = { 3482, 7}, - 0x2D = { 3489, 2}, - 0x2E = { 3491, 4}, - 0x2F = { 3495, 8}, - 0x30 = { 3503, 1}, - 0x31 = { 3504, 1}, - 0x32 = { 3505, 1}, - 0x33 = { 3506, 1}, - 0x34 = { 3507, 1}, - 0x35 = { 3508, 1}, - 0x36 = { 3509, 1}, - 0x37 = { 3510, 3}, - 0x38 = { 3513, 1}, - 0x39 = { 3514, 1}, + 0x00 = { 3255, 1}, + 0x01 = { 3256, 1}, + 0x02 = { 3257, 1}, + 0x03 = { 3258, 1}, + 0x04 = { 3259, 1}, + 0x05 = { 3260, 1}, + 0x06 = { 3261, 2}, + 0x07 = { 3263, 2}, + 0x08 = { 3265, 1}, + 0x09 = { 3266, 1}, + 0x0A = { 3267, 1}, + 0x0B = { 3268, 1}, + 0x0C = { 3269, 1}, + 0x0D = { 3270, 1}, + 0x0E = { 3271, 1}, + 0x0F = { 3272, 1}, + 0x10 = { 3273, 16}, + 0x11 = { 3289, 7}, + 0x12 = { 3296, 1}, + 0x13 = { 3297, 1}, + 0x14 = { 3298, 2}, + 0x15 = { 3300, 2}, + 0x16 = { 3302, 2}, + 0x17 = { 3304, 2}, + 0x18 = { 3306, 1}, + 0x19 = { 3307, 1}, + 0x1A = { 3308, 1}, + 0x1B = { 3309, 1}, + 0x1C = { 3310, 1}, + 0x1D = { 3311, 1}, + 0x1E = { 3312, 1}, + 0x1F = { 3313, 1}, + 0x20 = { 3314, 1}, + 0x21 = { 3315, 1}, + 0x22 = { 3316, 1}, + 0x23 = { 3317, 1}, + 0x24 = { 3318, 1}, + 0x25 = { 3319, 1}, + 0x26 = { 3320, 1}, + 0x27 = { 3321, 1}, + 0x28 = { 3322, 1}, + 0x29 = { 3323, 1}, + 0x2A = { 3324, 1}, + 0x2B = { 3325, 1}, + 0x2C = { 3326, 7}, + 0x2D = { 3333, 2}, + 0x2E = { 3335, 4}, + 0x2F = { 3339, 8}, + 0x30 = { 3347, 1}, + 0x31 = { 3348, 1}, + 0x32 = { 3349, 1}, + 0x33 = { 3350, 1}, + 0x34 = { 3351, 1}, + 0x35 = { 3352, 1}, + 0x36 = { 3353, 1}, + 0x37 = { 3354, 3}, + 0x38 = { 3357, 1}, + 0x39 = { 3358, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3515, 6}, - 0xE85 = { 3521, 2}, - 0xE86 = { 3523, 1}, - 0xE87 = { 3524, 1}, - 0xE88 = { 3525, 1}, - 0xE89 = { 3526, 1}, - 0xE8A = { 3527, 1}, - 0xE8B = { 3528, 2}, - 0xE8C = { 3530, 4}, - 0xE8D = { 3534, 6}, - 0xE8E = { 3540, 1}, - 0xE8F = { 3541, 1}, - 0xE90 = { 3542, 1}, - 0xE91 = { 3543, 1}, - 0xE92 = { 3544, 2}, - 0xE93 = { 3546, 1}, - 0xE94 = { 3547, 1}, - 0xE95 = { 3548, 1}, - 0xE96 = { 3549, 1}, - 0xE97 = { 3550, 2}, - 0xE9C = { 3552, 1}, - 0xE9D = { 3553, 1}, - 0xE9E = { 3554, 1}, - 0xE9F = { 3555, 1}, - 0xEA0 = { 3556, 2}, - 0xEA1 = { 3558, 3}, - 0xEA2 = { 3561, 1}, - 0xEA3 = { 3562, 1}, - 0xEA4 = { 3563, 7}, - 0xEA5 = { 3570, 7}, - 0xEA6 = { 3577, 1}, - 0xEA7 = { 3578, 1}, - 0xEA8 = { 3579, 1}, - 0xEA9 = { 3580, 2}, - 0xEB1 = { 3582, 1}, - 0xEB4 = { 3583, 1}, - 0xEB5 = { 3584, 1}, - 0xEB6 = { 3585, 1}, - 0xEB7 = { 3586, 1}, - 0xEBB = { 3587, 1}, - 0xEBC = { 3588, 1}, - 0xEBD = { 3589, 1}, - 0xEC0 = { 3590, 2}, - 0xEC1 = { 3592, 1}, - 0xEC2 = { 3593, 3}, - 0xEC3 = { 3596, 2}, - 0xEC4 = { 3598, 2}, - 0xEC5 = { 3600, 1}, - 0xEC6 = { 3601, 7}, - 0xEC7 = { 3608, 2}, - 0xEC8 = { 3610, 1}, - 0xEC9 = { 3611, 1}, - 0xECA = { 3612, 2}, - 0xECB = { 3614, 2}, - 0xECC = { 3616, 1}, - 0xECD = { 3617, 1}, - 0xECE = { 3618, 2}, - 0xECF = { 3620, 2}, - 0xED6 = { 3622, 4}, - 0xED8 = { 3626, 4}, - 0xED9 = { 3630, 4}, - 0xEDC = { 3634, 4}, - 0xEDD = { 3638, 4}, - 0xEE0 = { 3642, 24}, - 0xEE1 = { 3666, 23}, - 0xEE2 = { 3689, 22}, - 0xEE3 = { 3711, 29}, - 0xEE4 = { 3740, 23}, - 0xEE5 = { 3763, 22}, - 0xEE6 = { 3785, 22}, - 0xEE7 = { 3807, 29}, - 0xEE8 = { 3836, 28}, - 0xEE9 = { 3864, 12}, - 0xEEA = { 3876, 13}, - 0xEEB = { 3889, 18}, - 0xEEC = { 3907, 27}, - 0xEED = { 3934, 13}, - 0xEEE = { 3947, 22}, - 0xEEF = { 3969, 23}, - 0xEF0 = { 3992, 15}, - 0xEF1 = { 4007, 15}, - 0xEF2 = { 4022, 15}, - 0xEF3 = { 4037, 15}, - 0xEF4 = { 4052, 15}, - 0xEF5 = { 4067, 15}, - 0xEF6 = { 4082, 15}, - 0xEF7 = { 4097, 15}, - 0xEF8 = { 4112, 3}, - 0xEF9 = { 4115, 3}, - 0xEFA = { 4118, 3}, - 0xEFB = { 4121, 3}, - 0xEFC = { 4124, 3}, - 0xEFD = { 4127, 3}, - 0xEFE = { 4130, 3}, - 0xEFF = { 4133, 3}, - 0xF00 = { 4136, 12}, - 0xF01 = { 4148, 11}, - 0xF02 = { 4159, 8}, - 0xF03 = { 4167, 8}, - 0xF04 = { 4175, 9}, - 0xF05 = { 4184, 6}, - 0xF06 = { 4190, 5}, - 0xF07 = { 4195, 5}, - 0xF08 = { 4200, 6}, - 0xF09 = { 4206, 6}, - 0xF0A = { 4212, 4}, - 0xF0B = { 4216, 4}, - 0xF0C = { 4220, 4}, - 0xF0D = { 4224, 3}, - 0xF0E = { 4227, 4}, - 0xF0F = { 4231, 4}, - 0xF10 = { 4235, 7}, - 0xF11 = { 4242, 7}, - 0xF12 = { 4249, 6}, - 0xF13 = { 4255, 6}, - 0xF14 = { 4261, 5}, - 0xF15 = { 4266, 4}, - 0xF16 = { 4270, 5}, - 0xF17 = { 4275, 5}, - 0xF18 = { 4280, 5}, - 0xF19 = { 4285, 4}, - 0xF1A = { 4289, 4}, - 0xF1B = { 4293, 5}, - 0xF1C = { 4298, 5}, - 0xF1D = { 4303, 4}, - 0xF1E = { 4307, 4}, - 0xF1F = { 4311, 4}, - 0xF20 = { 4315, 5}, - 0xF21 = { 4320, 4}, - 0xF22 = { 4324, 4}, - 0xF23 = { 4328, 4}, - 0xF24 = { 4332, 5}, - 0xF25 = { 4337, 3}, - 0xF26 = { 4340, 4}, - 0xF27 = { 4344, 4}, - 0xF28 = { 4348, 5}, - 0xF29 = { 4353, 4}, - 0xF2A = { 4357, 4}, - 0xF2B = { 4361, 4}, - 0xF2C = { 4365, 5}, - 0xF2D = { 4370, 3}, - 0xF2E = { 4373, 4}, - 0xF2F = { 4377, 4}, - 0xF30 = { 4381, 6}, - 0xF31 = { 4387, 4}, - 0xF32 = { 4391, 6}, - 0xF33 = { 4397, 4}, - 0xF34 = { 4401, 5}, - 0xF35 = { 4406, 3}, - 0xF36 = { 4409, 6}, - 0xF37 = { 4415, 4}, - 0xF38 = { 4419, 7}, - 0xF39 = { 4426, 4}, - 0xF3A = { 4430, 19}, - 0xF3B = { 4449, 9}, - 0xF3C = { 4458, 5}, - 0xF3D = { 4463, 3}, - 0xF3E = { 4466, 5}, - 0xF3F = { 4471, 4}, - 0xF40 = { 4475, 7}, - 0xF41 = { 4482, 7}, - 0xF42 = { 4489, 5}, - 0xF43 = { 4494, 5}, - 0xF44 = { 4499, 7}, - 0xF45 = { 4506, 6}, - 0xF46 = { 4512, 5}, - 0xF47 = { 4517, 5}, - 0xF48 = { 4522, 6}, - 0xF49 = { 4528, 6}, - 0xF4A = { 4534, 4}, - 0xF4B = { 4538, 4}, - 0xF4C = { 4542, 4}, - 0xF4D = { 4546, 3}, - 0xF4E = { 4549, 4}, - 0xF4F = { 4553, 4}, - 0xF50 = { 4557, 5}, - 0xF51 = { 4562, 5}, - 0xF52 = { 4567, 4}, - 0xF53 = { 4571, 4}, - 0xF54 = { 4575, 5}, - 0xF55 = { 4580, 4}, - 0xF56 = { 4584, 5}, - 0xF57 = { 4589, 5}, - 0xF58 = { 4594, 5}, - 0xF59 = { 4599, 4}, - 0xF5A = { 4603, 4}, - 0xF5B = { 4607, 5}, - 0xF5C = { 4612, 5}, - 0xF5D = { 4617, 4}, - 0xF5E = { 4621, 4}, - 0xF5F = { 4625, 4}, - 0xF60 = { 4629, 5}, - 0xF61 = { 4634, 4}, - 0xF62 = { 4638, 4}, - 0xF63 = { 4642, 4}, - 0xF64 = { 4646, 5}, - 0xF65 = { 4651, 3}, - 0xF66 = { 4654, 4}, - 0xF67 = { 4658, 4}, - 0xF68 = { 4662, 5}, - 0xF69 = { 4667, 4}, - 0xF6A = { 4671, 4}, - 0xF6B = { 4675, 4}, - 0xF6C = { 4679, 5}, - 0xF6D = { 4684, 3}, - 0xF6E = { 4687, 4}, - 0xF6F = { 4691, 4}, - 0xF70 = { 4695, 5}, - 0xF71 = { 4700, 4}, - 0xF72 = { 4704, 4}, - 0xF73 = { 4708, 4}, - 0xF74 = { 4712, 4}, - 0xF75 = { 4716, 3}, - 0xF76 = { 4719, 4}, - 0xF77 = { 4723, 4}, - 0xF78 = { 4727, 8}, - 0xF79 = { 4735, 4}, - 0xF7A = { 4739, 4}, - 0xF7B = { 4743, 4}, - 0xF7C = { 4747, 4}, - 0xF7D = { 4751, 3}, - 0xF7E = { 4754, 4}, - 0xF7F = { 4758, 5}, - 0xF80 = { 4763, 1}, - 0xF81 = { 4764, 1}, - 0xF82 = { 4765, 1}, - 0xF83 = { 4766, 2}, - 0xF84 = { 4768, 1}, - 0xF85 = { 4769, 2}, - 0xF88 = { 4771, 1}, - 0xF89 = { 4772, 2}, - 0xF8A = { 4774, 1}, - 0xF8B = { 4775, 1}, - 0xF8C = { 4776, 1}, - 0xF8D = { 4777, 2}, - 0xF91 = { 4779, 1}, - 0xF93 = { 4780, 1}, - 0xF99 = { 4781, 2}, - 0xF9B = { 4783, 1}, - 0xFA0 = { 4784, 3}, - 0xFA1 = { 4787, 3}, - 0xFA2 = { 4790, 3}, - 0xFA3 = { 4793, 3}, - 0xFA4 = { 4796, 3}, - 0xFA5 = { 4799, 3}, - 0xFA6 = { 4802, 1}, - 0xFA7 = { 4803, 1}, - 0xFA8 = { 4804, 10}, - 0xFA9 = { 4814, 10}, - 0xFAA = { 4824, 6}, - 0xFAB = { 4830, 1}, - 0xFAC = { 4831, 6}, - 0xFAD = { 4837, 6}, - 0xFAE = { 4843, 6}, - 0xFB0 = { 4849, 3}, - 0xFB5 = { 4852, 1}, - 0xFB8 = { 4853, 1}, - 0xFB9 = { 4854, 1}, - 0xFBA = { 4855, 1}, - 0xFBB = { 4856, 1}, - 0xFBC = { 4857, 1}, - 0xFBE = { 4858, 1}, - 0xFC0 = { 4859, 1}, - 0xFC1 = { 4860, 1}, - 0xFC2 = { 4861, 3}, - 0xFC3 = { 4864, 3}, - 0xFC4 = { 4867, 1}, - 0xFC5 = { 4868, 1}, - 0xFC6 = { 4869, 2}, - 0xFC7 = { 4871, 2}, - 0xFC8 = { 4873, 7}, - 0xFC9 = { 4880, 11}, - 0xFCA = { 4891, 3}, - 0xFCB = { 4894, 3}, - 0xFCC = { 4897, 7}, - 0xFCD = { 4904, 7}, - 0xFCE = { 4911, 2}, - 0xFCF = { 4913, 2}, - 0xFD2 = { 4915, 1}, - 0xFD3 = { 4916, 1}, - 0xFD9 = { 4917, 4}, - 0xFDA = { 4921, 1}, - 0xFDB = { 4922, 1}, - 0xFE0 = { 4923, 28}, - 0xFE1 = { 4951, 26}, - 0xFE2 = { 4977, 26}, - 0xFE3 = { 5003, 32}, - 0xFE4 = { 5035, 29}, - 0xFE5 = { 5064, 27}, - 0xFE6 = { 5091, 27}, - 0xFE7 = { 5118, 33}, - 0xFE8 = { 5151, 32}, - 0xFE9 = { 5183, 17}, - 0xFEA = { 5200, 17}, - 0xFEB = { 5217, 29}, - 0xFEC = { 5246, 31}, - 0xFED = { 5277, 18}, - 0xFEE = { 5295, 26}, - 0xFEF = { 5321, 32}, - 0xFF0 = { 5353, 19}, - 0xFF1 = { 5372, 18}, - 0xFF2 = { 5390, 17}, - 0xFF3 = { 5407, 17}, - 0xFF4 = { 5424, 19}, - 0xFF5 = { 5443, 18}, - 0xFF6 = { 5461, 17}, - 0xFF7 = { 5478, 17}, - 0xFF8 = { 5495, 4}, - 0xFF9 = { 5499, 4}, - 0xFFA = { 5503, 4}, - 0xFFB = { 5507, 17}, - 0xFFC = { 5524, 4}, - 0xFFD = { 5528, 4}, - 0xFFE = { 5532, 4}, - 0xFFF = { 5536, 17}, + 0xE84 = { 3359, 6}, + 0xE85 = { 3365, 2}, + 0xE86 = { 3367, 1}, + 0xE87 = { 3368, 1}, + 0xE88 = { 3369, 1}, + 0xE89 = { 3370, 1}, + 0xE8A = { 3371, 1}, + 0xE8B = { 3372, 2}, + 0xE8C = { 3374, 4}, + 0xE8D = { 3378, 6}, + 0xE8E = { 3384, 1}, + 0xE8F = { 3385, 1}, + 0xE90 = { 3386, 1}, + 0xE91 = { 3387, 1}, + 0xE92 = { 3388, 2}, + 0xE93 = { 3390, 1}, + 0xE94 = { 3391, 1}, + 0xE95 = { 3392, 1}, + 0xE96 = { 3393, 1}, + 0xE97 = { 3394, 2}, + 0xE9C = { 3396, 1}, + 0xE9D = { 3397, 1}, + 0xE9E = { 3398, 1}, + 0xE9F = { 3399, 1}, + 0xEA0 = { 3400, 2}, + 0xEA1 = { 3402, 3}, + 0xEA2 = { 3405, 1}, + 0xEA3 = { 3406, 1}, + 0xEA4 = { 3407, 7}, + 0xEA5 = { 3414, 7}, + 0xEA6 = { 3421, 1}, + 0xEA7 = { 3422, 1}, + 0xEA8 = { 3423, 1}, + 0xEA9 = { 3424, 2}, + 0xEB1 = { 3426, 1}, + 0xEB4 = { 3427, 1}, + 0xEB5 = { 3428, 1}, + 0xEB6 = { 3429, 1}, + 0xEB7 = { 3430, 1}, + 0xEBB = { 3431, 1}, + 0xEBC = { 3432, 1}, + 0xEBD = { 3433, 1}, + 0xEC0 = { 3434, 2}, + 0xEC1 = { 3436, 1}, + 0xEC2 = { 3437, 3}, + 0xEC3 = { 3440, 2}, + 0xEC4 = { 3442, 2}, + 0xEC5 = { 3444, 1}, + 0xEC6 = { 3445, 7}, + 0xEC7 = { 3452, 2}, + 0xEC8 = { 3454, 1}, + 0xEC9 = { 3455, 1}, + 0xECA = { 3456, 2}, + 0xECB = { 3458, 2}, + 0xECC = { 3460, 1}, + 0xECD = { 3461, 1}, + 0xECE = { 3462, 2}, + 0xECF = { 3464, 2}, + 0xED6 = { 3466, 4}, + 0xED8 = { 3470, 4}, + 0xED9 = { 3474, 4}, + 0xEDC = { 3478, 4}, + 0xEDD = { 3482, 4}, + 0xEE0 = { 3486, 24}, + 0xEE1 = { 3510, 23}, + 0xEE2 = { 3533, 22}, + 0xEE3 = { 3555, 29}, + 0xEE4 = { 3584, 23}, + 0xEE5 = { 3607, 22}, + 0xEE6 = { 3629, 22}, + 0xEE7 = { 3651, 29}, + 0xEE8 = { 3680, 28}, + 0xEE9 = { 3708, 12}, + 0xEEA = { 3720, 13}, + 0xEEB = { 3733, 18}, + 0xEEC = { 3751, 27}, + 0xEED = { 3778, 13}, + 0xEEE = { 3791, 22}, + 0xEEF = { 3813, 23}, + 0xEF0 = { 3836, 15}, + 0xEF1 = { 3851, 15}, + 0xEF2 = { 3866, 15}, + 0xEF3 = { 3881, 15}, + 0xEF4 = { 3896, 15}, + 0xEF5 = { 3911, 15}, + 0xEF6 = { 3926, 15}, + 0xEF7 = { 3941, 15}, + 0xEF8 = { 3956, 3}, + 0xEF9 = { 3959, 3}, + 0xEFA = { 3962, 3}, + 0xEFB = { 3965, 3}, + 0xEFC = { 3968, 3}, + 0xEFD = { 3971, 3}, + 0xEFE = { 3974, 3}, + 0xEFF = { 3977, 3}, + 0xF00 = { 3980, 12}, + 0xF01 = { 3992, 11}, + 0xF02 = { 4003, 8}, + 0xF03 = { 4011, 8}, + 0xF04 = { 4019, 9}, + 0xF05 = { 4028, 6}, + 0xF06 = { 4034, 5}, + 0xF07 = { 4039, 5}, + 0xF08 = { 4044, 6}, + 0xF09 = { 4050, 6}, + 0xF0A = { 4056, 4}, + 0xF0B = { 4060, 4}, + 0xF0C = { 4064, 4}, + 0xF0D = { 4068, 3}, + 0xF0E = { 4071, 4}, + 0xF0F = { 4075, 4}, + 0xF10 = { 4079, 7}, + 0xF11 = { 4086, 7}, + 0xF12 = { 4093, 6}, + 0xF13 = { 4099, 6}, + 0xF14 = { 4105, 5}, + 0xF15 = { 4110, 4}, + 0xF16 = { 4114, 5}, + 0xF17 = { 4119, 5}, + 0xF18 = { 4124, 5}, + 0xF19 = { 4129, 4}, + 0xF1A = { 4133, 4}, + 0xF1B = { 4137, 5}, + 0xF1C = { 4142, 5}, + 0xF1D = { 4147, 4}, + 0xF1E = { 4151, 4}, + 0xF1F = { 4155, 4}, + 0xF20 = { 4159, 5}, + 0xF21 = { 4164, 4}, + 0xF22 = { 4168, 4}, + 0xF23 = { 4172, 4}, + 0xF24 = { 4176, 5}, + 0xF25 = { 4181, 3}, + 0xF26 = { 4184, 4}, + 0xF27 = { 4188, 4}, + 0xF28 = { 4192, 5}, + 0xF29 = { 4197, 4}, + 0xF2A = { 4201, 4}, + 0xF2B = { 4205, 4}, + 0xF2C = { 4209, 5}, + 0xF2D = { 4214, 3}, + 0xF2E = { 4217, 4}, + 0xF2F = { 4221, 4}, + 0xF30 = { 4225, 6}, + 0xF31 = { 4231, 4}, + 0xF32 = { 4235, 6}, + 0xF33 = { 4241, 4}, + 0xF34 = { 4245, 5}, + 0xF35 = { 4250, 3}, + 0xF36 = { 4253, 6}, + 0xF37 = { 4259, 4}, + 0xF38 = { 4263, 7}, + 0xF39 = { 4270, 4}, + 0xF3A = { 4274, 19}, + 0xF3B = { 4293, 9}, + 0xF3C = { 4302, 5}, + 0xF3D = { 4307, 3}, + 0xF3E = { 4310, 5}, + 0xF3F = { 4315, 4}, + 0xF40 = { 4319, 7}, + 0xF41 = { 4326, 7}, + 0xF42 = { 4333, 5}, + 0xF43 = { 4338, 5}, + 0xF44 = { 4343, 7}, + 0xF45 = { 4350, 6}, + 0xF46 = { 4356, 5}, + 0xF47 = { 4361, 5}, + 0xF48 = { 4366, 6}, + 0xF49 = { 4372, 6}, + 0xF4A = { 4378, 4}, + 0xF4B = { 4382, 4}, + 0xF4C = { 4386, 4}, + 0xF4D = { 4390, 3}, + 0xF4E = { 4393, 4}, + 0xF4F = { 4397, 4}, + 0xF50 = { 4401, 5}, + 0xF51 = { 4406, 5}, + 0xF52 = { 4411, 4}, + 0xF53 = { 4415, 4}, + 0xF54 = { 4419, 5}, + 0xF55 = { 4424, 4}, + 0xF56 = { 4428, 5}, + 0xF57 = { 4433, 5}, + 0xF58 = { 4438, 5}, + 0xF59 = { 4443, 4}, + 0xF5A = { 4447, 4}, + 0xF5B = { 4451, 5}, + 0xF5C = { 4456, 5}, + 0xF5D = { 4461, 4}, + 0xF5E = { 4465, 4}, + 0xF5F = { 4469, 4}, + 0xF60 = { 4473, 5}, + 0xF61 = { 4478, 4}, + 0xF62 = { 4482, 4}, + 0xF63 = { 4486, 4}, + 0xF64 = { 4490, 5}, + 0xF65 = { 4495, 3}, + 0xF66 = { 4498, 4}, + 0xF67 = { 4502, 4}, + 0xF68 = { 4506, 5}, + 0xF69 = { 4511, 4}, + 0xF6A = { 4515, 4}, + 0xF6B = { 4519, 4}, + 0xF6C = { 4523, 5}, + 0xF6D = { 4528, 3}, + 0xF6E = { 4531, 4}, + 0xF6F = { 4535, 4}, + 0xF70 = { 4539, 5}, + 0xF71 = { 4544, 4}, + 0xF72 = { 4548, 4}, + 0xF73 = { 4552, 4}, + 0xF74 = { 4556, 4}, + 0xF75 = { 4560, 3}, + 0xF76 = { 4563, 4}, + 0xF77 = { 4567, 4}, + 0xF78 = { 4571, 8}, + 0xF79 = { 4579, 4}, + 0xF7A = { 4583, 4}, + 0xF7B = { 4587, 4}, + 0xF7C = { 4591, 4}, + 0xF7D = { 4595, 3}, + 0xF7E = { 4598, 4}, + 0xF7F = { 4602, 5}, + 0xF80 = { 4607, 1}, + 0xF81 = { 4608, 1}, + 0xF82 = { 4609, 1}, + 0xF83 = { 4610, 2}, + 0xF84 = { 4612, 1}, + 0xF85 = { 4613, 2}, + 0xF88 = { 4615, 1}, + 0xF89 = { 4616, 2}, + 0xF8A = { 4618, 1}, + 0xF8B = { 4619, 1}, + 0xF8C = { 4620, 1}, + 0xF8D = { 4621, 2}, + 0xF91 = { 4623, 1}, + 0xF93 = { 4624, 1}, + 0xF99 = { 4625, 2}, + 0xF9B = { 4627, 1}, + 0xFA0 = { 4628, 3}, + 0xFA1 = { 4631, 3}, + 0xFA2 = { 4634, 3}, + 0xFA3 = { 4637, 3}, + 0xFA4 = { 4640, 3}, + 0xFA5 = { 4643, 3}, + 0xFA6 = { 4646, 1}, + 0xFA7 = { 4647, 1}, + 0xFA8 = { 4648, 10}, + 0xFA9 = { 4658, 10}, + 0xFAA = { 4668, 6}, + 0xFAB = { 4674, 1}, + 0xFAC = { 4675, 6}, + 0xFAD = { 4681, 6}, + 0xFAE = { 4687, 6}, + 0xFB0 = { 4693, 3}, + 0xFB5 = { 4696, 1}, + 0xFB8 = { 4697, 1}, + 0xFB9 = { 4698, 1}, + 0xFBA = { 4699, 1}, + 0xFBB = { 4700, 1}, + 0xFBC = { 4701, 1}, + 0xFBE = { 4702, 1}, + 0xFC0 = { 4703, 1}, + 0xFC1 = { 4704, 1}, + 0xFC2 = { 4705, 3}, + 0xFC3 = { 4708, 3}, + 0xFC4 = { 4711, 1}, + 0xFC5 = { 4712, 1}, + 0xFC6 = { 4713, 2}, + 0xFC7 = { 4715, 2}, + 0xFC8 = { 4717, 7}, + 0xFC9 = { 4724, 11}, + 0xFCA = { 4735, 3}, + 0xFCB = { 4738, 3}, + 0xFCC = { 4741, 7}, + 0xFCD = { 4748, 7}, + 0xFCE = { 4755, 2}, + 0xFCF = { 4757, 2}, + 0xFD2 = { 4759, 1}, + 0xFD3 = { 4760, 1}, + 0xFD9 = { 4761, 4}, + 0xFDA = { 4765, 1}, + 0xFDB = { 4766, 1}, + 0xFE0 = { 4767, 28}, + 0xFE1 = { 4795, 26}, + 0xFE2 = { 4821, 26}, + 0xFE3 = { 4847, 32}, + 0xFE4 = { 4879, 29}, + 0xFE5 = { 4908, 27}, + 0xFE6 = { 4935, 27}, + 0xFE7 = { 4962, 33}, + 0xFE8 = { 4995, 32}, + 0xFE9 = { 5027, 17}, + 0xFEA = { 5044, 17}, + 0xFEB = { 5061, 29}, + 0xFEC = { 5090, 31}, + 0xFED = { 5121, 18}, + 0xFEE = { 5139, 26}, + 0xFEF = { 5165, 32}, + 0xFF0 = { 5197, 19}, + 0xFF1 = { 5216, 18}, + 0xFF2 = { 5234, 17}, + 0xFF3 = { 5251, 17}, + 0xFF4 = { 5268, 19}, + 0xFF5 = { 5287, 18}, + 0xFF6 = { 5305, 17}, + 0xFF7 = { 5322, 17}, + 0xFF8 = { 5339, 4}, + 0xFF9 = { 5343, 4}, + 0xFFA = { 5347, 4}, + 0xFFB = { 5351, 17}, + 0xFFC = { 5368, 4}, + 0xFFD = { 5372, 4}, + 0xFFE = { 5376, 4}, + 0xFFF = { 5380, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index a7d733bdc..17a9506a2 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1680]lib.Encoding{ +ENCODE_FORMS := [1665]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -939,8 +939,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -962,8 +960,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -980,8 +976,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1650,14 +1644,10 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VSHR { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VSRA { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSHL { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1668,8 +1658,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ // .VRSHR { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSRA { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -1690,7 +1678,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSHRN { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQSHRUN { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHL @@ -1712,7 +1699,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {}, {.U64,.NONE} }, // .VQRSHRN { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHRUN { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHRN @@ -1721,7 +1707,6 @@ ENCODE_FORMS := [1680]lib.Encoding{ { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, @@ -2548,342 +2533,342 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .CRC32CW = { 611, 1}, .VADD = { 612, 18}, .VSUB = { 630, 18}, - .VMUL = { 648, 24}, - .VDIV = { 672, 3}, - .VMLA = { 675, 18}, - .VMLS = { 693, 17}, - .VNMUL = { 710, 2}, - .VNMLA = { 712, 2}, - .VNMLS = { 714, 2}, - .VFMA = { 716, 10}, - .VFMS = { 726, 8}, - .VFNMA = { 734, 3}, - .VFNMS = { 737, 3}, - .VABS = { 740, 12}, - .VNEG = { 752, 12}, - .VSQRT = { 764, 3}, - .VCMP = { 767, 8}, - .VCMPE = { 775, 4}, - .VCVT = { 779, 21}, - .VCVTB = { 800, 2}, - .VCVTT = { 802, 2}, - .VCVTA = { 804, 2}, - .VCVTN = { 806, 2}, - .VCVTP = { 808, 2}, - .VCVTM = { 810, 2}, - .VCVTR = { 812, 4}, - .VMOV = { 816, 31}, - .VMRS = { 847, 1}, - .VMSR = { 848, 1}, - .VLDR = { 849, 2}, - .VSTR = { 851, 2}, - .VLDM = { 853, 2}, - .VSTM = { 855, 2}, - .VPUSH = { 857, 2}, - .VPOP = { 859, 2}, - .VSEL = { 861, 2}, - .VMAXNM = { 863, 2}, - .VMINNM = { 865, 2}, - .VRINTA = { 867, 3}, - .VRINTN = { 870, 3}, - .VRINTP = { 873, 3}, - .VRINTM = { 876, 3}, - .VRINTR = { 879, 2}, - .VRINTZ = { 881, 3}, - .VRINTX = { 884, 3}, - .VADDL = { 887, 6}, - .VADDW = { 893, 6}, - .VSUBL = { 899, 6}, - .VSUBW = { 905, 6}, - .VHADD = { 911, 9}, - .VHSUB = { 920, 9}, - .VRHADD = { 929, 3}, - .VQADD = { 932, 11}, - .VQSUB = { 943, 11}, - .VMULL = { 954, 11}, - .VMLAL = { 965, 10}, - .VMLSL = { 975, 10}, - .VQDMULL = { 985, 4}, - .VQDMLAL = { 989, 4}, - .VQDMLSL = { 993, 4}, - .VQDMULH = { 997, 8}, - .VQRDMULH = { 1005, 8}, - .VQRDMLAH = { 1013, 8}, - .VQRDMLSH = { 1021, 8}, - .VABA = { 1029, 8}, - .VABAL = { 1037, 6}, - .VABD = { 1043, 10}, - .VABDL = { 1053, 6}, - .VAND = { 1059, 3}, - .VBIC = { 1062, 3}, - .VORR = { 1065, 3}, - .VORN = { 1068, 3}, - .VEOR = { 1071, 3}, - .VBSL = { 1074, 2}, - .VBIT = { 1076, 2}, - .VBIF = { 1078, 2}, - .VMVN = { 1080, 13}, - .VMOVN = { 1093, 3}, - .VQMOVN = { 1096, 6}, - .VQMOVUN = { 1102, 3}, - .VMOVL = { 1105, 6}, - .VTST = { 1111, 6}, - .VCEQ = { 1117, 14}, - .VCGE = { 1131, 16}, - .VCGT = { 1147, 16}, - .VCLE = { 1163, 18}, - .VCLT = { 1181, 18}, - .VACGE = { 1199, 2}, - .VACGT = { 1201, 2}, - .VACLE = { 1203, 2}, - .VACLT = { 1205, 2}, - .VMAX = { 1207, 13}, - .VMIN = { 1220, 13}, - .VPMAX = { 1233, 5}, - .VPMIN = { 1238, 5}, - .VPADD = { 1243, 4}, - .VPADDL = { 1247, 6}, - .VPADAL = { 1253, 4}, - .VRECPE = { 1257, 4}, - .VRECPS = { 1261, 2}, - .VRSQRTE = { 1263, 4}, - .VRSQRTS = { 1267, 2}, - .VSHL = { 1269, 9}, - .VSHR = { 1278, 5}, - .VSRA = { 1283, 5}, - .VRSHL = { 1288, 5}, - .VRSHR = { 1293, 5}, - .VRSRA = { 1298, 2}, - .VSLI = { 1300, 2}, - .VSRI = { 1302, 2}, - .VQSHL = { 1304, 7}, - .VQSHRN = { 1311, 2}, - .VQSHRUN = { 1313, 1}, - .VQRSHL = { 1314, 16}, - .VQRSHRN = { 1330, 2}, - .VQRSHRUN = { 1332, 1}, - .VSHRN = { 1333, 1}, - .VRSHRN = { 1334, 1}, - .VSHLL = { 1335, 5}, - .VCLS = { 1340, 6}, - .VCLZ = { 1346, 6}, - .VCNT = { 1352, 2}, - .VPADD_F = { 1354, 2}, - .VRECPE_F = { 1356, 2}, - .VRSQRTE_F = { 1358, 2}, - .VREV16 = { 1360, 2}, - .VREV32 = { 1362, 4}, - .VREV64 = { 1366, 6}, - .VEXT = { 1372, 2}, - .VTBL = { 1374, 4}, - .VTBX = { 1378, 4}, - .VTRN = { 1382, 6}, - .VUZP = { 1388, 5}, - .VZIP = { 1393, 5}, - .VDUP = { 1398, 5}, - .VSWP = { 1403, 2}, - .VMOV_LANE = { 1405, 3}, - .VLD1 = { 1408, 8}, - .VLD2 = { 1416, 3}, - .VLD3 = { 1419, 2}, - .VLD4 = { 1421, 2}, - .VST1 = { 1423, 7}, - .VST2 = { 1430, 3}, - .VST3 = { 1433, 2}, - .VST4 = { 1435, 2}, - .AESE = { 1437, 1}, - .AESD = { 1438, 1}, - .AESMC = { 1439, 1}, - .AESIMC = { 1440, 1}, - .SHA1H = { 1441, 1}, - .SHA1SU0 = { 1442, 1}, - .SHA1SU1 = { 1443, 1}, - .SHA1C = { 1444, 1}, - .SHA1M = { 1445, 1}, - .SHA1P = { 1446, 1}, - .SHA256H = { 1447, 1}, - .SHA256H2 = { 1448, 1}, - .SHA256SU0 = { 1449, 1}, - .SHA256SU1 = { 1450, 1}, - .VJCVT = { 1451, 1}, - .VSDOT = { 1452, 4}, - .VUDOT = { 1456, 4}, - .VDOT = { 1460, 2}, - .VMMLA = { 1462, 1}, - .VFMAL = { 1463, 2}, - .VFMSL = { 1465, 2}, - .VCMLA = { 1467, 5}, - .VCADD = { 1472, 2}, - .VSMMLA = { 1474, 1}, - .VUMMLA = { 1475, 1}, - .VUSMMLA = { 1476, 1}, - .VSUDOT = { 1477, 2}, - .VUSDOT = { 1479, 4}, - .VQABS = { 1483, 1}, - .VQNEG = { 1484, 1}, - .VMOVX = { 1485, 1}, - .VINS = { 1486, 1}, - .VLD2R = { 1487, 1}, - .VLD3R = { 1488, 1}, - .VLD4R = { 1489, 1}, - .VLD1_LANE = { 1490, 3}, - .VLD2_LANE = { 1493, 3}, - .VLD3_LANE = { 1496, 3}, - .VLD4_LANE = { 1499, 3}, - .VST1_LANE = { 1502, 3}, - .VST2_LANE = { 1505, 3}, - .VST3_LANE = { 1508, 3}, - .VST4_LANE = { 1511, 3}, - .IT = { 1514, 1}, - .TT = { 1515, 1}, - .TTT = { 1516, 1}, - .TTA = { 1517, 1}, - .TTAT = { 1518, 1}, - .SG = { 1519, 1}, - .BXNS = { 1520, 1}, - .BLXNS = { 1521, 1}, - .PAC = { 1522, 1}, - .PACBTI = { 1523, 1}, - .AUT = { 1524, 1}, - .AUTG = { 1525, 1}, - .BTI = { 1526, 1}, - .WLS = { 1527, 1}, - .WLSTP = { 1528, 1}, - .DLS = { 1529, 1}, - .DLSTP = { 1530, 1}, - .LE = { 1531, 1}, - .LETP = { 1532, 1}, - .LCTP = { 1533, 1}, - .BF = { 1534, 1}, - .BFX = { 1535, 1}, - .BFL = { 1536, 1}, - .BFLX = { 1537, 1}, - .BFCSEL = { 1538, 1}, - .CX1 = { 1539, 1}, - .CX1A = { 1540, 1}, - .CX1D = { 1541, 1}, - .CX1DA = { 1542, 1}, - .CX2 = { 1543, 1}, - .CX2A = { 1544, 1}, - .CX2D = { 1545, 1}, - .CX2DA = { 1546, 1}, - .CX3 = { 1547, 1}, - .CX3A = { 1548, 1}, - .CX3D = { 1549, 1}, - .CX3DA = { 1550, 1}, - .VCX1 = { 1551, 2}, - .VCX1A = { 1553, 2}, - .VCX2 = { 1555, 2}, - .VCX2A = { 1557, 2}, - .VCX3 = { 1559, 2}, - .VCX3A = { 1561, 2}, - .VPT = { 1563, 1}, - .VPST = { 1564, 1}, - .VPSEL = { 1565, 1}, - .VPNOT = { 1566, 1}, - .VCTP = { 1567, 1}, - .VADDV = { 1568, 1}, - .VADDVA = { 1569, 1}, - .VADDLV = { 1570, 1}, - .VADDLVA = { 1571, 1}, - .VMAXV = { 1572, 1}, - .VMAXAV = { 1573, 1}, - .VMINV = { 1574, 1}, - .VMINAV = { 1575, 1}, - .VMAXNMV = { 1576, 1}, - .VMAXNMAV = { 1577, 1}, - .VMINNMV = { 1578, 1}, - .VMINNMAV = { 1579, 1}, - .VABAV = { 1580, 1}, - .VMLADAV = { 1581, 1}, - .VMLADAVA = { 1582, 1}, - .VMLADAVX = { 1583, 1}, - .VMLADAVAX = { 1584, 1}, - .VMLALDAV = { 1585, 1}, - .VMLALDAVA = { 1586, 1}, - .VMLALDAVX = { 1587, 1}, - .VMLALDAVAX = { 1588, 1}, - .VMLSDAV = { 1589, 1}, - .VMLSDAVA = { 1590, 1}, - .VMLSDAVX = { 1591, 1}, - .VMLSDAVAX = { 1592, 1}, - .VMLSLDAV = { 1593, 1}, - .VMLSLDAVA = { 1594, 1}, - .VMLSLDAVX = { 1595, 1}, - .VMLSLDAVAX = { 1596, 1}, - .VRMLALDAVH = { 1597, 1}, - .VRMLALDAVHA = { 1598, 1}, - .VRMLALDAVHX = { 1599, 1}, - .VRMLALDAVHAX = { 1600, 1}, - .VRMLSLDAVH = { 1601, 1}, - .VRMLSLDAVHA = { 1602, 1}, - .VRMLSLDAVHX = { 1603, 1}, - .VRMLSLDAVHAX = { 1604, 1}, - .VMLAV = { 1605, 1}, - .VMLAVA = { 1606, 1}, - .VMLSV = { 1607, 1}, - .VMLSVA = { 1608, 1}, - .VCMUL = { 1609, 1}, - .VHCADD = { 1610, 2}, - .VBRSR = { 1612, 1}, - .VSHLC = { 1613, 1}, - .VDDUP = { 1614, 1}, - .VIDUP = { 1615, 1}, - .VDWDUP = { 1616, 1}, - .VIWDUP = { 1617, 1}, - .VMOVNB = { 1618, 1}, - .VMOVNT = { 1619, 1}, - .VQMOVNB = { 1620, 1}, - .VQMOVNT = { 1621, 1}, - .VQMOVUNB = { 1622, 1}, - .VQMOVUNT = { 1623, 1}, - .VSHLLB = { 1624, 1}, - .VSHLLT = { 1625, 1}, - .VMULLB = { 1626, 1}, - .VMULLT = { 1627, 1}, - .VMLALB = { 1628, 1}, - .VMLALT = { 1629, 1}, - .VMLSLB = { 1630, 1}, - .VMLSLT = { 1631, 1}, - .VSHRNB = { 1632, 1}, - .VSHRNT = { 1633, 1}, - .VRSHRNB = { 1634, 1}, - .VRSHRNT = { 1635, 1}, - .VQSHRNB = { 1636, 1}, - .VQSHRNT = { 1637, 1}, - .VQRSHRNB = { 1638, 1}, - .VQRSHRNT = { 1639, 1}, - .VQSHRUNB = { 1640, 1}, - .VQSHRUNT = { 1641, 1}, - .VQRSHRUNB = { 1642, 1}, - .VQRSHRUNT = { 1643, 1}, - .VQDMLADH = { 1644, 1}, - .VQDMLADHX = { 1645, 1}, - .VQDMLSDH = { 1646, 1}, - .VQDMLSDHX = { 1647, 1}, - .VQRDMLADH = { 1648, 1}, - .VQRDMLADHX = { 1649, 1}, - .VQRDMLSDH = { 1650, 1}, - .VQRDMLSDHX = { 1651, 1}, - .VLDRB = { 1652, 2}, - .VLDRH = { 1654, 2}, - .VLDRW = { 1656, 2}, - .VLDRD = { 1658, 2}, - .VSTRB = { 1660, 2}, - .VSTRH = { 1662, 2}, - .VSTRW = { 1664, 2}, - .VSTRD = { 1666, 2}, - .VLD20 = { 1668, 1}, - .VLD21 = { 1669, 1}, - .VLD40 = { 1670, 1}, - .VLD41 = { 1671, 1}, - .VLD42 = { 1672, 1}, - .VLD43 = { 1673, 1}, - .VST20 = { 1674, 1}, - .VST21 = { 1675, 1}, - .VST40 = { 1676, 1}, - .VST41 = { 1677, 1}, - .VST42 = { 1678, 1}, - .VST43 = { 1679, 1}, - ._COUNT = { 1680, 0}, + .VMUL = { 648, 22}, + .VDIV = { 670, 3}, + .VMLA = { 673, 16}, + .VMLS = { 689, 15}, + .VNMUL = { 704, 2}, + .VNMLA = { 706, 2}, + .VNMLS = { 708, 2}, + .VFMA = { 710, 10}, + .VFMS = { 720, 8}, + .VFNMA = { 728, 3}, + .VFNMS = { 731, 3}, + .VABS = { 734, 12}, + .VNEG = { 746, 12}, + .VSQRT = { 758, 3}, + .VCMP = { 761, 8}, + .VCMPE = { 769, 4}, + .VCVT = { 773, 21}, + .VCVTB = { 794, 2}, + .VCVTT = { 796, 2}, + .VCVTA = { 798, 2}, + .VCVTN = { 800, 2}, + .VCVTP = { 802, 2}, + .VCVTM = { 804, 2}, + .VCVTR = { 806, 4}, + .VMOV = { 810, 31}, + .VMRS = { 841, 1}, + .VMSR = { 842, 1}, + .VLDR = { 843, 2}, + .VSTR = { 845, 2}, + .VLDM = { 847, 2}, + .VSTM = { 849, 2}, + .VPUSH = { 851, 2}, + .VPOP = { 853, 2}, + .VSEL = { 855, 2}, + .VMAXNM = { 857, 2}, + .VMINNM = { 859, 2}, + .VRINTA = { 861, 3}, + .VRINTN = { 864, 3}, + .VRINTP = { 867, 3}, + .VRINTM = { 870, 3}, + .VRINTR = { 873, 2}, + .VRINTZ = { 875, 3}, + .VRINTX = { 878, 3}, + .VADDL = { 881, 6}, + .VADDW = { 887, 6}, + .VSUBL = { 893, 6}, + .VSUBW = { 899, 6}, + .VHADD = { 905, 9}, + .VHSUB = { 914, 9}, + .VRHADD = { 923, 3}, + .VQADD = { 926, 11}, + .VQSUB = { 937, 11}, + .VMULL = { 948, 11}, + .VMLAL = { 959, 10}, + .VMLSL = { 969, 10}, + .VQDMULL = { 979, 4}, + .VQDMLAL = { 983, 4}, + .VQDMLSL = { 987, 4}, + .VQDMULH = { 991, 8}, + .VQRDMULH = { 999, 8}, + .VQRDMLAH = { 1007, 8}, + .VQRDMLSH = { 1015, 8}, + .VABA = { 1023, 8}, + .VABAL = { 1031, 6}, + .VABD = { 1037, 10}, + .VABDL = { 1047, 6}, + .VAND = { 1053, 3}, + .VBIC = { 1056, 3}, + .VORR = { 1059, 3}, + .VORN = { 1062, 3}, + .VEOR = { 1065, 3}, + .VBSL = { 1068, 2}, + .VBIT = { 1070, 2}, + .VBIF = { 1072, 2}, + .VMVN = { 1074, 13}, + .VMOVN = { 1087, 3}, + .VQMOVN = { 1090, 6}, + .VQMOVUN = { 1096, 3}, + .VMOVL = { 1099, 6}, + .VTST = { 1105, 6}, + .VCEQ = { 1111, 14}, + .VCGE = { 1125, 16}, + .VCGT = { 1141, 16}, + .VCLE = { 1157, 18}, + .VCLT = { 1175, 18}, + .VACGE = { 1193, 2}, + .VACGT = { 1195, 2}, + .VACLE = { 1197, 2}, + .VACLT = { 1199, 2}, + .VMAX = { 1201, 13}, + .VMIN = { 1214, 13}, + .VPMAX = { 1227, 5}, + .VPMIN = { 1232, 5}, + .VPADD = { 1237, 4}, + .VPADDL = { 1241, 6}, + .VPADAL = { 1247, 4}, + .VRECPE = { 1251, 4}, + .VRECPS = { 1255, 2}, + .VRSQRTE = { 1257, 4}, + .VRSQRTS = { 1261, 2}, + .VSHL = { 1263, 9}, + .VSHR = { 1272, 3}, + .VSRA = { 1275, 3}, + .VRSHL = { 1278, 5}, + .VRSHR = { 1283, 3}, + .VRSRA = { 1286, 2}, + .VSLI = { 1288, 2}, + .VSRI = { 1290, 2}, + .VQSHL = { 1292, 7}, + .VQSHRN = { 1299, 1}, + .VQSHRUN = { 1300, 1}, + .VQRSHL = { 1301, 16}, + .VQRSHRN = { 1317, 1}, + .VQRSHRUN = { 1318, 1}, + .VSHRN = { 1319, 1}, + .VRSHRN = { 1320, 1}, + .VSHLL = { 1321, 4}, + .VCLS = { 1325, 6}, + .VCLZ = { 1331, 6}, + .VCNT = { 1337, 2}, + .VPADD_F = { 1339, 2}, + .VRECPE_F = { 1341, 2}, + .VRSQRTE_F = { 1343, 2}, + .VREV16 = { 1345, 2}, + .VREV32 = { 1347, 4}, + .VREV64 = { 1351, 6}, + .VEXT = { 1357, 2}, + .VTBL = { 1359, 4}, + .VTBX = { 1363, 4}, + .VTRN = { 1367, 6}, + .VUZP = { 1373, 5}, + .VZIP = { 1378, 5}, + .VDUP = { 1383, 5}, + .VSWP = { 1388, 2}, + .VMOV_LANE = { 1390, 3}, + .VLD1 = { 1393, 8}, + .VLD2 = { 1401, 3}, + .VLD3 = { 1404, 2}, + .VLD4 = { 1406, 2}, + .VST1 = { 1408, 7}, + .VST2 = { 1415, 3}, + .VST3 = { 1418, 2}, + .VST4 = { 1420, 2}, + .AESE = { 1422, 1}, + .AESD = { 1423, 1}, + .AESMC = { 1424, 1}, + .AESIMC = { 1425, 1}, + .SHA1H = { 1426, 1}, + .SHA1SU0 = { 1427, 1}, + .SHA1SU1 = { 1428, 1}, + .SHA1C = { 1429, 1}, + .SHA1M = { 1430, 1}, + .SHA1P = { 1431, 1}, + .SHA256H = { 1432, 1}, + .SHA256H2 = { 1433, 1}, + .SHA256SU0 = { 1434, 1}, + .SHA256SU1 = { 1435, 1}, + .VJCVT = { 1436, 1}, + .VSDOT = { 1437, 4}, + .VUDOT = { 1441, 4}, + .VDOT = { 1445, 2}, + .VMMLA = { 1447, 1}, + .VFMAL = { 1448, 2}, + .VFMSL = { 1450, 2}, + .VCMLA = { 1452, 5}, + .VCADD = { 1457, 2}, + .VSMMLA = { 1459, 1}, + .VUMMLA = { 1460, 1}, + .VUSMMLA = { 1461, 1}, + .VSUDOT = { 1462, 2}, + .VUSDOT = { 1464, 4}, + .VQABS = { 1468, 1}, + .VQNEG = { 1469, 1}, + .VMOVX = { 1470, 1}, + .VINS = { 1471, 1}, + .VLD2R = { 1472, 1}, + .VLD3R = { 1473, 1}, + .VLD4R = { 1474, 1}, + .VLD1_LANE = { 1475, 3}, + .VLD2_LANE = { 1478, 3}, + .VLD3_LANE = { 1481, 3}, + .VLD4_LANE = { 1484, 3}, + .VST1_LANE = { 1487, 3}, + .VST2_LANE = { 1490, 3}, + .VST3_LANE = { 1493, 3}, + .VST4_LANE = { 1496, 3}, + .IT = { 1499, 1}, + .TT = { 1500, 1}, + .TTT = { 1501, 1}, + .TTA = { 1502, 1}, + .TTAT = { 1503, 1}, + .SG = { 1504, 1}, + .BXNS = { 1505, 1}, + .BLXNS = { 1506, 1}, + .PAC = { 1507, 1}, + .PACBTI = { 1508, 1}, + .AUT = { 1509, 1}, + .AUTG = { 1510, 1}, + .BTI = { 1511, 1}, + .WLS = { 1512, 1}, + .WLSTP = { 1513, 1}, + .DLS = { 1514, 1}, + .DLSTP = { 1515, 1}, + .LE = { 1516, 1}, + .LETP = { 1517, 1}, + .LCTP = { 1518, 1}, + .BF = { 1519, 1}, + .BFX = { 1520, 1}, + .BFL = { 1521, 1}, + .BFLX = { 1522, 1}, + .BFCSEL = { 1523, 1}, + .CX1 = { 1524, 1}, + .CX1A = { 1525, 1}, + .CX1D = { 1526, 1}, + .CX1DA = { 1527, 1}, + .CX2 = { 1528, 1}, + .CX2A = { 1529, 1}, + .CX2D = { 1530, 1}, + .CX2DA = { 1531, 1}, + .CX3 = { 1532, 1}, + .CX3A = { 1533, 1}, + .CX3D = { 1534, 1}, + .CX3DA = { 1535, 1}, + .VCX1 = { 1536, 2}, + .VCX1A = { 1538, 2}, + .VCX2 = { 1540, 2}, + .VCX2A = { 1542, 2}, + .VCX3 = { 1544, 2}, + .VCX3A = { 1546, 2}, + .VPT = { 1548, 1}, + .VPST = { 1549, 1}, + .VPSEL = { 1550, 1}, + .VPNOT = { 1551, 1}, + .VCTP = { 1552, 1}, + .VADDV = { 1553, 1}, + .VADDVA = { 1554, 1}, + .VADDLV = { 1555, 1}, + .VADDLVA = { 1556, 1}, + .VMAXV = { 1557, 1}, + .VMAXAV = { 1558, 1}, + .VMINV = { 1559, 1}, + .VMINAV = { 1560, 1}, + .VMAXNMV = { 1561, 1}, + .VMAXNMAV = { 1562, 1}, + .VMINNMV = { 1563, 1}, + .VMINNMAV = { 1564, 1}, + .VABAV = { 1565, 1}, + .VMLADAV = { 1566, 1}, + .VMLADAVA = { 1567, 1}, + .VMLADAVX = { 1568, 1}, + .VMLADAVAX = { 1569, 1}, + .VMLALDAV = { 1570, 1}, + .VMLALDAVA = { 1571, 1}, + .VMLALDAVX = { 1572, 1}, + .VMLALDAVAX = { 1573, 1}, + .VMLSDAV = { 1574, 1}, + .VMLSDAVA = { 1575, 1}, + .VMLSDAVX = { 1576, 1}, + .VMLSDAVAX = { 1577, 1}, + .VMLSLDAV = { 1578, 1}, + .VMLSLDAVA = { 1579, 1}, + .VMLSLDAVX = { 1580, 1}, + .VMLSLDAVAX = { 1581, 1}, + .VRMLALDAVH = { 1582, 1}, + .VRMLALDAVHA = { 1583, 1}, + .VRMLALDAVHX = { 1584, 1}, + .VRMLALDAVHAX = { 1585, 1}, + .VRMLSLDAVH = { 1586, 1}, + .VRMLSLDAVHA = { 1587, 1}, + .VRMLSLDAVHX = { 1588, 1}, + .VRMLSLDAVHAX = { 1589, 1}, + .VMLAV = { 1590, 1}, + .VMLAVA = { 1591, 1}, + .VMLSV = { 1592, 1}, + .VMLSVA = { 1593, 1}, + .VCMUL = { 1594, 1}, + .VHCADD = { 1595, 2}, + .VBRSR = { 1597, 1}, + .VSHLC = { 1598, 1}, + .VDDUP = { 1599, 1}, + .VIDUP = { 1600, 1}, + .VDWDUP = { 1601, 1}, + .VIWDUP = { 1602, 1}, + .VMOVNB = { 1603, 1}, + .VMOVNT = { 1604, 1}, + .VQMOVNB = { 1605, 1}, + .VQMOVNT = { 1606, 1}, + .VQMOVUNB = { 1607, 1}, + .VQMOVUNT = { 1608, 1}, + .VSHLLB = { 1609, 1}, + .VSHLLT = { 1610, 1}, + .VMULLB = { 1611, 1}, + .VMULLT = { 1612, 1}, + .VMLALB = { 1613, 1}, + .VMLALT = { 1614, 1}, + .VMLSLB = { 1615, 1}, + .VMLSLT = { 1616, 1}, + .VSHRNB = { 1617, 1}, + .VSHRNT = { 1618, 1}, + .VRSHRNB = { 1619, 1}, + .VRSHRNT = { 1620, 1}, + .VQSHRNB = { 1621, 1}, + .VQSHRNT = { 1622, 1}, + .VQRSHRNB = { 1623, 1}, + .VQRSHRNT = { 1624, 1}, + .VQSHRUNB = { 1625, 1}, + .VQSHRUNT = { 1626, 1}, + .VQRSHRUNB = { 1627, 1}, + .VQRSHRUNT = { 1628, 1}, + .VQDMLADH = { 1629, 1}, + .VQDMLADHX = { 1630, 1}, + .VQDMLSDH = { 1631, 1}, + .VQDMLSDHX = { 1632, 1}, + .VQRDMLADH = { 1633, 1}, + .VQRDMLADHX = { 1634, 1}, + .VQRDMLSDH = { 1635, 1}, + .VQRDMLSDHX = { 1636, 1}, + .VLDRB = { 1637, 2}, + .VLDRH = { 1639, 2}, + .VLDRW = { 1641, 2}, + .VLDRD = { 1643, 2}, + .VSTRB = { 1645, 2}, + .VSTRH = { 1647, 2}, + .VSTRW = { 1649, 2}, + .VSTRD = { 1651, 2}, + .VLD20 = { 1653, 1}, + .VLD21 = { 1654, 1}, + .VLD40 = { 1655, 1}, + .VLD41 = { 1656, 1}, + .VLD42 = { 1657, 1}, + .VLD43 = { 1658, 1}, + .VST20 = { 1659, 1}, + .VST21 = { 1660, 1}, + .VST40 = { 1661, 1}, + .VST41 = { 1662, 1}, + .VST42 = { 1663, 1}, + .VST43 = { 1664, 1}, + ._COUNT = { 1665, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 6ecfc17830fe1ff4f0a674179dd3bfcdb15ee34c..45e43b9dbfbd334414f4f6a95c2c2915b813462c 100644 GIT binary patch literal 10794 zcmc(D1-MmJ^Y`SUrMp8wI+PHU?(R!>w=~ivA_{^9A|R=#AS&HThlGNNqynO-h@c26 z{AZtiHurLc%LU)>`JVOcy=rFG%$(nzHFE$E2p9mwMrvaRaUd?lvp&9!64*E)B!WjE zF(iSckPMPT3P=g5LbKG62GT-0NDmnxBV>Zip;;El3fUk#WPu#;XlR@hazSo*401vq z$Qv5x3(L$81)w103(GA8g~3}XVseYZOp;I01crLG=?S+0ZpNq$!HEOpe3||*3bsp zLOW;=9iSt0g3izdx5jm18ZR&tcMM-5jMeQ*aDxzXRsBv!FJdIJ7E{>hP|){_QB_{9}d7lI0Rq7 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zec-0`r8`bTZk6PvmG;J|77bpNvRW zq7lt#MW-Lr8+a4juoKUGJVDV3j3?n zL7sol{wMs*{0n}g|BKH$L5a%X1#zX22^>wpWK0cWs-f26A?`eaI{JDv&^J*RQ=daK zRx-C>9eo=*=r>|BwlHs}cA*D*ncw662k8%^kNG6E9|JhWe1`ow`VVn|`4j4=_#Bt< z4f`w9YZwelHAEf8ZH(Yo_IId%@Y%lu{_liEDnfBsEQeY`y>}AKrOacf<*0yLu+QD| zd6qlLeEoMQ_z~pqN2BahVN7XcP=#tdh^gG2hUwuL&B44dt_92u)Tgl&xwD+R_n#F7 zzvp@S7qAkmuo}6uCSO~qS-i-5)?)*G8`}BKub?ALs530r4t8DG#k?Pf*!AZBuH5^M z@R_3+?Hmgo9cOo9l>N!DQWwIEzQagZEkCN#tZ2L%u{N5d?xq;3ny5tp literal 16384 zcmeIyU1-&H9LMp`dEUvL|KmAx?s>~hlC+r()Qes0LWsyHL@z>;B+Mewgat*jb|En+ zun5zsi!w_qg~2F$5Fe&a(4ee|E2nOSW?eWeA9m8-M>aUfy6@uqgV(;_@BjPzpKTw; zBs-RXC143y0+xU!UjZaBGXIF5(2rB>PE!Z)Gk(Dtp51xQ^86gmV+h0C z`7IOEMf%@yDU;F&uG8PZDDo40PVwj7^xm&8KZbpr6pcc1MOX;6;%k-K%SsPtfJJ5q(oWu}D5b<1jUQ8j% zFa=epMFZ}^bgxu%yh&>IO0)nAy|k8iNiFpfdKxR}U%*-~u9xr%*706Dbv-(~ls4c! z?rg($-r33X&#B$`0^cz2M=$*`d`JHS`Z2(KmO6|J_=EW}pMQn^8uH8$KduDQ$oL5b zeoQ&~DX8|7x|@10^?qt2`zH2tnVXqg{FEN1KI(^B=BKri{VMirsI5GInf>c{gZWLo zO}~kEyXd!LC;cAuaCa}h#R1;$rS{=CcfLnI{Qw5(hp88+e_{kznMZMpJ{}~L4){Ib zBgb4ptw95(G0zBMnn^z!P0aJD&1k^_=115sq<;d7nV+OSh2>a*=h?5KzKGVKL~Yb| ztVajlV!wghl0Cw0;htc&M*&Bf5jyf&Smc2d9DY1lw7Q04_p9gto4kkJeg>lVg zH*bRd{IE)k!wRiNM_8v_VYQBil^Vj$uwJ#ue{&?5S0(3<0K9BpW4euugdo# Date: Thu, 27 Aug 2026 08:28:39 -0400 Subject: [PATCH 23/89] rexcode/arm64: B.cond is sixteen mnemonics, not one with a condition operand B_COND was a straight contradiction of the rule the rest of the enum follows. No assembler has a mnemonic called `b.cond`; it has `b.eq`, `b.le`, `b.ne` and thirteen more, and x86 in this same library already models exactly this shape the right way -- JE, JNE, JG, JLE are sixteen separate mnemonics with the condition in the opcode. Two things were wrong with folding it into an operand. The condition is not an operand. It is four bits of the opcode, no different from x86 putting Jcc's condition in the low nibble of 0x7_. Modelling it as one has to be papered over everywhere: the printer special-cased B_COND to rebuild `b.eq` out of operand 0, sbprint had to skip that operand so it did not print twice, and the public mnemonic_to_string -- which has no instruction to read the operand from -- returned "b_cond", a string no assembler takes. All three of those are now gone; the name prints itself. More importantly it destroyed the flag data. x86 records per condition which status bits it consults: JE reads {ZF}, JLE reads {ZF, SF, OF}. One B_COND entry could not say that, so it claimed nzcv_rd = {N, Z, C, V} -- all four flags, for every condition. Every entry was wrong. Split apart they carry what they actually read: b.eq/b.ne Z b.hi/b.ls Z, C b.cs/b.cc C b.ge/b.lt N, V b.mi/b.pl N b.gt/b.le N, Z, V b.vs/b.vc V b.al/b.nv none which is the data the compiler's asm checker reads for flag liveness, now that arm64 feeds it. The mask also covers the condition field for the first time (0xFF000010 -> 0xFF00001F): with the condition in an operand, four opcode bits sat outside the mask. BC.cond gets the same treatment. Builders come out per condition, so `b.le` is `inst_b_le(label)` rather than `inst_b_cond(.LE, label)`. Cond stays exactly as it is -- CSEL, CSINC, CSINV, CSNEG, CCMP, CCMN and FCSEL take a real condition operand, and the compiler's OP_COND handling is untouched. All sixteen verified by disassembling our own output with llvm-mc: b.eq, b.ne, b.hs, b.lo, b.mi, b.pl, b.vs, b.vc, b.hi, b.ls, b.ge, b.lt, b.gt, b.le, b.al, b.nv. Rows follow the table's current column formatting. All rexcode suites pass and the generators stay idempotent. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm64/mnemonic_builders.odin | 136 +- core/rexcode/isa/arm64/mnemonics.odin | 27 +- core/rexcode/isa/arm64/printer.odin | 54 +- .../tablegen/generated/decode_tables.odin | 1196 ++++++------ .../tablegen/generated/encode_tables.odin | 1642 +++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 98 +- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 34104 -> 34524 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 48720 -> 49320 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6288 -> 6528 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 48760 -> 49360 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes .../isa/arm64/tests/pipeline_smoke.odin | 4 +- core/rexcode/isa/arm64/tests/smoke.odin | 6 +- 13 files changed, 1775 insertions(+), 1388 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index ee731a3be..eea626f79 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -223,8 +223,38 @@ inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } -inst_b_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } -emit_b_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_b_cond_c_l(cond, label)) } +inst_b_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_EQ, label) } +emit_b_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_eq_l(label)) } +inst_b_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NE, label) } +emit_b_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ne_l(label)) } +inst_b_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CS, label) } +emit_b_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cs_l(label)) } +inst_b_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CC, label) } +emit_b_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cc_l(label)) } +inst_b_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_MI, label) } +emit_b_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_mi_l(label)) } +inst_b_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_PL, label) } +emit_b_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_pl_l(label)) } +inst_b_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VS, label) } +emit_b_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vs_l(label)) } +inst_b_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VC, label) } +emit_b_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vc_l(label)) } +inst_b_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_HI, label) } +emit_b_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_hi_l(label)) } +inst_b_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LS, label) } +emit_b_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ls_l(label)) } +inst_b_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GE, label) } +emit_b_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ge_l(label)) } +inst_b_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LT, label) } +emit_b_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_lt_l(label)) } +inst_b_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GT, label) } +emit_b_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_gt_l(label)) } +inst_b_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LE, label) } +emit_b_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_le_l(label)) } +inst_b_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_AL, label) } +emit_b_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_al_l(label)) } +inst_b_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NV, label) } +emit_b_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_nv_l(label)) } inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } @@ -1659,8 +1689,38 @@ inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } -inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } -emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) } +inst_bc_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_EQ, label) } +emit_bc_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_eq_l(label)) } +inst_bc_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NE, label) } +emit_bc_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ne_l(label)) } +inst_bc_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CS, label) } +emit_bc_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cs_l(label)) } +inst_bc_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CC, label) } +emit_bc_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cc_l(label)) } +inst_bc_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_MI, label) } +emit_bc_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_mi_l(label)) } +inst_bc_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_PL, label) } +emit_bc_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_pl_l(label)) } +inst_bc_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VS, label) } +emit_bc_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vs_l(label)) } +inst_bc_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VC, label) } +emit_bc_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vc_l(label)) } +inst_bc_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_HI, label) } +emit_bc_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_hi_l(label)) } +inst_bc_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LS, label) } +emit_bc_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ls_l(label)) } +inst_bc_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GE, label) } +emit_bc_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ge_l(label)) } +inst_bc_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LT, label) } +emit_bc_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_lt_l(label)) } +inst_bc_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GT, label) } +emit_bc_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_gt_l(label)) } +inst_bc_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LE, label) } +emit_bc_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_le_l(label)) } +inst_bc_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_AL, label) } +emit_bc_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_al_l(label)) } +inst_bc_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NV, label) } +emit_bc_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_nv_l(label)) } inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } @@ -2038,8 +2098,38 @@ inst_blr :: inst_blr_r emit_blr :: emit_blr_r inst_ret :: proc{ inst_ret_r, inst_ret_none } emit_ret :: proc{ emit_ret_r, emit_ret_none } -inst_b_cond :: inst_b_cond_c_l -emit_b_cond :: emit_b_cond_c_l +inst_b_eq :: inst_b_eq_l +emit_b_eq :: emit_b_eq_l +inst_b_ne :: inst_b_ne_l +emit_b_ne :: emit_b_ne_l +inst_b_cs :: inst_b_cs_l +emit_b_cs :: emit_b_cs_l +inst_b_cc :: inst_b_cc_l +emit_b_cc :: emit_b_cc_l +inst_b_mi :: inst_b_mi_l +emit_b_mi :: emit_b_mi_l +inst_b_pl :: inst_b_pl_l +emit_b_pl :: emit_b_pl_l +inst_b_vs :: inst_b_vs_l +emit_b_vs :: emit_b_vs_l +inst_b_vc :: inst_b_vc_l +emit_b_vc :: emit_b_vc_l +inst_b_hi :: inst_b_hi_l +emit_b_hi :: emit_b_hi_l +inst_b_ls :: inst_b_ls_l +emit_b_ls :: emit_b_ls_l +inst_b_ge :: inst_b_ge_l +emit_b_ge :: emit_b_ge_l +inst_b_lt :: inst_b_lt_l +emit_b_lt :: emit_b_lt_l +inst_b_gt :: inst_b_gt_l +emit_b_gt :: emit_b_gt_l +inst_b_le :: inst_b_le_l +emit_b_le :: emit_b_le_l +inst_b_al :: inst_b_al_l +emit_b_al :: emit_b_al_l +inst_b_nv :: inst_b_nv_l +emit_b_nv :: emit_b_nv_l inst_cbz :: inst_cbz_r_l emit_cbz :: emit_cbz_r_l inst_cbnz :: inst_cbnz_r_l @@ -3254,8 +3344,38 @@ inst_wfet :: inst_wfet_r emit_wfet :: emit_wfet_r inst_wfit :: inst_wfit_r emit_wfit :: emit_wfit_r -inst_bc_cond :: inst_bc_cond_c_l -emit_bc_cond :: emit_bc_cond_c_l +inst_bc_eq :: inst_bc_eq_l +emit_bc_eq :: emit_bc_eq_l +inst_bc_ne :: inst_bc_ne_l +emit_bc_ne :: emit_bc_ne_l +inst_bc_cs :: inst_bc_cs_l +emit_bc_cs :: emit_bc_cs_l +inst_bc_cc :: inst_bc_cc_l +emit_bc_cc :: emit_bc_cc_l +inst_bc_mi :: inst_bc_mi_l +emit_bc_mi :: emit_bc_mi_l +inst_bc_pl :: inst_bc_pl_l +emit_bc_pl :: emit_bc_pl_l +inst_bc_vs :: inst_bc_vs_l +emit_bc_vs :: emit_bc_vs_l +inst_bc_vc :: inst_bc_vc_l +emit_bc_vc :: emit_bc_vc_l +inst_bc_hi :: inst_bc_hi_l +emit_bc_hi :: emit_bc_hi_l +inst_bc_ls :: inst_bc_ls_l +emit_bc_ls :: emit_bc_ls_l +inst_bc_ge :: inst_bc_ge_l +emit_bc_ge :: emit_bc_ge_l +inst_bc_lt :: inst_bc_lt_l +emit_bc_lt :: emit_bc_lt_l +inst_bc_gt :: inst_bc_gt_l +emit_bc_gt :: emit_bc_gt_l +inst_bc_le :: inst_bc_le_l +emit_bc_le :: emit_bc_le_l +inst_bc_al :: inst_bc_al_l +emit_bc_al :: emit_bc_al_l +inst_bc_nv :: inst_bc_nv_l +emit_bc_nv :: emit_bc_nv_l inst_uxtb :: inst_uxtb_r_r emit_uxtb :: emit_uxtb_r_r inst_uxth :: inst_uxth_r_r diff --git a/core/rexcode/isa/arm64/mnemonics.odin b/core/rexcode/isa/arm64/mnemonics.odin index fa648c572..7825c8564 100644 --- a/core/rexcode/isa/arm64/mnemonics.odin +++ b/core/rexcode/isa/arm64/mnemonics.odin @@ -13,11 +13,12 @@ package rexcode_arm64 // between them by matching the operands against that mnemonic's run of // forms in INSTRUCTION_TABLE (see tablegen/instruction_table.odin). // -// The only names holding an underscore are the system instructions an -// assembler writes as two tokens -- `dc zva`, `tlbi vae1`, `at s1e1r`, -// `bti j`, `psb csync` -- plus B_COND / BC_COND, whose condition lives in -// an operand and prints as `b.eq` / `bc.eq`, and the AMX_* pseudo-ops for -// Apple's undocumented coprocessor, which has no assembler spelling. +// Names holding an underscore are the ones an assembler writes with a +// separator: the two-token system instructions -- `dc zva`, `tlbi vae1`, +// `at s1e1r`, `bti j`, `psb csync` -- and the conditional branches, where +// the underscore is a dot: B_LE prints `b.le`, BC_NE prints `bc.ne`. The +// AMX_* pseudo-ops keep theirs literally; Apple's undocumented coprocessor +// has no assembler spelling at all. // // Architectural aliases that share an encoding (MOV/MVN of ORR/ORN, NEG of // SUB, CMP of SUBS, TST of ANDS, ...) are listed as the mnemonics they are: @@ -81,7 +82,15 @@ Mnemonic :: enum u16 { B, BL, // 26-bit PC-rel BR, BLR, RET, // register indirect - B_COND, // B.cond -- 19-bit PC-rel + // One member per condition, the way an assembler spells them and the way + // x86 does its Jcc. The condition is not an operand: it is four bits of + // the opcode, and splitting it lets each entry record the flags it + // actually reads -- b.eq consults Z alone, b.le consults N, Z and V -- + // where a single B_COND had to claim all four for every condition. + B_EQ, B_NE, B_CS, B_CC, // B.cond -- 19-bit PC-rel + B_MI, B_PL, B_VS, B_VC, + B_HI, B_LS, B_GE, B_LT, + B_GT, B_LE, B_AL, B_NV, CBZ, CBNZ, // 19-bit PC-rel + Rt TBZ, TBNZ, // 14-bit PC-rel + bit position @@ -433,7 +442,11 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // Branch consistency hint (v8.8-A BC.cond) // ------------------------------------------------------------------------- - BC_COND, + // BC.cond: the consistent-branch form, same 16 conditions. + BC_EQ, BC_NE, BC_CS, BC_CC, + BC_MI, BC_PL, BC_VS, BC_VC, + BC_HI, BC_LS, BC_GE, BC_LT, + BC_GT, BC_LE, BC_AL, BC_NV, // ------------------------------------------------------------------------- // Sign/zero extend aliases (canonical names for SBFM/UBFM specific cases) diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index ce2015007..e0ddea32a 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -115,13 +115,6 @@ sbprint :: proc( write_full_mnemonic(sb, inst, opts.uppercase) - // B.cond / BC.cond fold the condition into the mnemonic (b.eq), so the - // operand carrying it must not be printed a second time. - start_slot := 0 - if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && - inst.operand_count >= 1 && inst.ops[0].kind == .COND { - start_slot = 1 - } // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), // which assemblers write as `lsl #16` and omit entirely when it is zero. @@ -131,10 +124,10 @@ sbprint :: proc( end_slot = 2 } - if end_slot > start_slot { + if end_slot > 0 { strings.write_byte(sb, ' ') - for slot in start_slot.. start_slot { + for slot in 0.. 0 { strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } @@ -287,32 +280,11 @@ wprintln :: proc( // Internal writers // ============================================================================= -// write_full_mnemonic handles the two mnemonics whose printed spelling is not -// just the enum name: B_COND / BC_COND carry the condition in the mnemonic -// itself (`b.eq`, `bc.ne`) rather than as a printed operand. - +// Every mnemonic now prints straight from its name -- the conditional +// branches carry their condition in the name (B_LE -> `b.le`), so there is +// no operand to fold in. @(private="file") write_full_mnemonic :: proc(sb: ^strings.Builder, inst: ^Instruction, uppercase: bool) { - // B_COND / BC_COND -> `b.` / `bc.` from the first operand. - if (inst.mnemonic == .B_COND || inst.mnemonic == .BC_COND) && inst.operand_count >= 1 && inst.ops[0].kind == .COND { - if inst.mnemonic == .BC_COND { - strings.write_string(sb, uppercase ? "BC." : "bc.") - } else { - strings.write_string(sb, uppercase ? "B." : "b.") - } - c := inst.ops[0].cond & 0xF - cn := COND_NAMES[c] - if uppercase { - for i in 0..= 'a' && ch <= 'z' { strings.write_byte(sb, ch - 32) } else { strings.write_byte(sb, ch) } - } - } else { - strings.write_string(sb, cn) - } - return - } - write_mnemonic(sb, inst.mnemonic, uppercase) } @@ -329,18 +301,28 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { // underscore is kept: AMX_LDX is an undocumented Apple coprocessor op // with no assembler spelling at all, and printing it `amx ldx` would // imply a two-token syntax that does not exist. - split := -1 + split, sep := -1, byte(' ') for prefix in ([]string{"DC_", "IC_", "AT_", "TLBI_", "BTI_", "PSB_", "TSB_"}) { if len(name) > len(prefix) && name[:len(prefix)] == prefix { split = len(prefix) - 1 break } } + // Conditional branches spell the separator as a dot: B_LE -> `b.le`. + // BC_ is checked first, since it also starts with B. + if split < 0 { + for prefix in ([]string{"BC_", "B_"}) { + if len(name) > len(prefix) && name[:len(prefix)] == prefix { + split, sep = len(prefix) - 1, '.' + break + } + } + } for i in 0..= 'A' && c <= 'Z' { strings.write_byte(sb, c + 32) } else { diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 53b0081e1..1ceeea50f 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2438]lib.Decode_Entry{ +DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -42,34 +42,34 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, - { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, @@ -97,27 +97,27 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, @@ -127,61 +127,61 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -192,97 +192,97 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -318,19 +318,19 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, @@ -345,47 +345,47 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {explicit_count=4} }, @@ -431,102 +431,102 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, @@ -565,27 +565,27 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {explicit_count=4} }, { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -594,14 +594,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, - { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, @@ -612,8 +612,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, @@ -626,16 +626,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, @@ -647,14 +647,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, @@ -662,18 +662,18 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, @@ -720,25 +720,25 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, @@ -758,12 +758,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -784,79 +784,79 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, @@ -869,25 +869,25 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -903,199 +903,199 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, 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{.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, @@ -1105,28 +1105,28 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, @@ -1150,43 +1150,43 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1207,10 +1207,10 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1233,12 +1233,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1246,19 +1246,19 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -1266,47 +1266,47 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1314,31 +1314,31 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1346,43 +1346,43 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1392,40 +1392,40 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1438,21 +1438,21 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1462,39 +1462,39 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1504,14 +1504,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1522,23 +1522,23 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1552,89 +1552,89 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1648,77 +1648,77 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1741,54 +1741,54 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, @@ -1807,14 +1807,14 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, @@ -1822,10 +1822,10 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -1962,14 +1962,44 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .BRK, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, + { .B_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, - { .B_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, - { .BC_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, - { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, @@ -1993,36 +2023,36 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, - { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, @@ -2035,16 +2065,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, @@ -2063,8 +2093,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, @@ -2077,37 +2107,37 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, @@ -2127,16 +2157,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, @@ -2149,16 +2179,16 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, @@ -2189,8 +2219,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, - { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, @@ -2220,12 +2250,12 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, @@ -2258,56 +2288,56 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, @@ -2315,22 +2345,22 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, @@ -2340,51 +2370,51 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, @@ -2392,8 +2422,8 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, @@ -2401,29 +2431,29 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -2432,21 +2462,21 @@ DECODE_ENTRIES := [2438]lib.Decode_Entry{ { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, } @(rodata) @@ -2459,11 +2489,11 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x07 = { 755, 1058}, 0x08 = {1813, 16}, 0x09 = {1829, 34}, - 0x0A = {1863, 100}, - 0x0B = {1963, 21}, - 0x0C = {1984, 167}, - 0x0D = {2151, 92}, - 0x0E = {2243, 19}, - 0x0F = {2262, 176}, + 0x0A = {1863, 130}, + 0x0B = {1993, 21}, + 0x0C = {2014, 167}, + 0x0D = {2181, 92}, + 0x0E = {2273, 19}, + 0x0F = {2292, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 4c78d0bac..045c5d064 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2436]lib.Encoding{ +ENCODE_FORMS := [2466]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -279,8 +279,38 @@ ENCODE_FORMS := [2436]lib.Encoding{ // .RET { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, - // .B_COND - { .B_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, + // .B_EQ + { .B_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_NE + { .B_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_CS + { .B_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_CC + { .B_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_MI + { .B_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_PL + { .B_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_VS + { .B_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_VC + { .B_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_HI + { .B_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_LS + { .B_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_GE + { .B_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_LT + { .B_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_GT + { .B_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_LE + { .B_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_AL + { .B_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .B_NV + { .B_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .CBZ { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, @@ -2947,8 +2977,38 @@ ENCODE_FORMS := [2436]lib.Encoding{ { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFIT { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, - // .BC_COND - { .BC_COND, {.COND,.REL_19,.NONE,.NONE}, {.COND_LO,.BRANCH_19,.NONE,.NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true, explicit_count=2} }, + // .BC_EQ + { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_NE + { .BC_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_CS + { .BC_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_CC + { .BC_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_MI + { .BC_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_PL + { .BC_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_VS + { .BC_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_VC + { .BC_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_HI + { .BC_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_LS + { .BC_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_GE + { .BC_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_LT + { .BC_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_GT + { .BC_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_LE + { .BC_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_AL + { .BC_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + // .BC_NV + { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .UXTB { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTH @@ -3233,7 +3293,7 @@ ENCODE_FORMS := [2436]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2436]lib.Clobber{ +CLOBBER_FORMS := [2466]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -3504,8 +3564,38 @@ CLOBBER_FORMS := [2436]lib.Clobber{ // .RET {read={0}, side_effects={.CONTROL}}, {implicit_rd={.LR}, side_effects={.CONTROL}}, - // .B_COND - {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}, + // .B_EQ + {nzcv_rd={.Z}, side_effects={.CONTROL}}, + // .B_NE + {nzcv_rd={.Z}, side_effects={.CONTROL}}, + // .B_CS + {nzcv_rd={.C}, side_effects={.CONTROL}}, + // .B_CC + {nzcv_rd={.C}, side_effects={.CONTROL}}, + // .B_MI + {nzcv_rd={.N}, side_effects={.CONTROL}}, + // .B_PL + {nzcv_rd={.N}, side_effects={.CONTROL}}, + // .B_VS + {nzcv_rd={.V}, side_effects={.CONTROL}}, + // .B_VC + {nzcv_rd={.V}, side_effects={.CONTROL}}, + // .B_HI + {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}, + // .B_LS + {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}, + // .B_GE + {nzcv_rd={.N, .V}, side_effects={.CONTROL}}, + // .B_LT + {nzcv_rd={.N, .V}, side_effects={.CONTROL}}, + // .B_GT + {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}, + // .B_LE + {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}, + // .B_AL + {side_effects={.CONTROL}}, + // .B_NV + {side_effects={.CONTROL}}, // .CBZ {read={0}, side_effects={.CONTROL}}, {read={0}, side_effects={.CONTROL}}, @@ -6172,8 +6262,38 @@ CLOBBER_FORMS := [2436]lib.Clobber{ {read={0}, side_effects={.WAIT}}, // .WFIT {read={0}, side_effects={.WAIT}}, - // .BC_COND - {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}, + // .BC_EQ + {nzcv_rd={.Z}, side_effects={.CONTROL}}, + // .BC_NE + {nzcv_rd={.Z}, side_effects={.CONTROL}}, + // .BC_CS + {nzcv_rd={.C}, side_effects={.CONTROL}}, + // .BC_CC + {nzcv_rd={.C}, side_effects={.CONTROL}}, + // .BC_MI + {nzcv_rd={.N}, side_effects={.CONTROL}}, + // .BC_PL + {nzcv_rd={.N}, side_effects={.CONTROL}}, + // .BC_VS + {nzcv_rd={.V}, side_effects={.CONTROL}}, + // .BC_VC + {nzcv_rd={.V}, side_effects={.CONTROL}}, + // .BC_HI + {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}, + // .BC_LS + {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}, + // .BC_GE + {nzcv_rd={.N, .V}, side_effects={.CONTROL}}, + // .BC_LT + {nzcv_rd={.N, .V}, side_effects={.CONTROL}}, + // .BC_GT + {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}, + // .BC_LE + {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}, + // .BC_AL + {side_effects={.CONTROL}}, + // .BC_NV + {side_effects={.CONTROL}}, // .UXTB {written={0}, read={1}}, // .UXTH @@ -6509,740 +6629,770 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .BR = { 217, 1}, .BLR = { 218, 1}, .RET = { 219, 2}, - .B_COND = { 221, 1}, - .CBZ = { 222, 2}, - .CBNZ = { 224, 2}, - .TBZ = { 226, 1}, - .TBNZ = { 227, 1}, - .LDR = { 228, 18}, - .STR = { 246, 16}, - .LDRB = { 262, 4}, - .STRB = { 266, 4}, - .LDRSB = { 270, 4}, - .LDRH = { 274, 4}, - .STRH = { 278, 4}, - .LDRSH = { 282, 4}, - .LDRSW = { 286, 2}, - .LDP = { 288, 9}, - .STP = { 297, 9}, - .LDPSW = { 306, 3}, - .LDAR = { 309, 2}, - .STLR = { 311, 2}, - .LDARB = { 313, 1}, - .STLRB = { 314, 1}, - .LDARH = { 315, 1}, - .STLRH = { 316, 1}, - .LDXR = { 317, 2}, - .STXR = { 319, 2}, - .LDAXR = { 321, 2}, - .STLXR = { 323, 2}, - .NOP = { 325, 1}, - .YIELD = { 326, 1}, - .WFE = { 327, 1}, - .WFI = { 328, 1}, - .SEV = { 329, 1}, - .SEVL = { 330, 1}, - .HINT = { 331, 1}, - .MRS = { 332, 1}, - .MSR = { 333, 2}, - .ISB = { 335, 1}, - .DSB = { 336, 1}, - .DMB = { 337, 1}, - .SVC = { 338, 1}, - .HVC = { 339, 1}, - .SMC = { 340, 1}, - .BRK = { 341, 1}, - .HLT = { 342, 1}, - .ERET = { 343, 1}, - .FMOV = { 344, 15}, - .FABS = { 359, 11}, - .FNEG = { 370, 11}, - .FSQRT = { 381, 11}, - .FADD = { 392, 12}, - .FSUB = { 404, 12}, - .FMUL = { 416, 12}, - .FDIV = { 428, 9}, - .FNMUL = { 437, 3}, - .FMADD = { 440, 3}, - .FMSUB = { 443, 3}, - .FNMADD = { 446, 3}, - .FNMSUB = { 449, 3}, - .FCMP = { 452, 3}, - .FCMPE = { 455, 3}, - .FCSEL = { 458, 3}, - .FMAX = { 461, 11}, - .FMIN = { 472, 11}, - .FMAXNM = { 483, 11}, - .FMINNM = { 494, 11}, - .FCVT = { 505, 6}, - .SCVTF = { 511, 10}, - .UCVTF = { 521, 10}, - .FCVTZS = { 531, 10}, - .FCVTZU = { 541, 10}, - .FCVTAS = { 551, 11}, - .FCVTAU = { 562, 11}, - .FCVTNS = { 573, 11}, - .FCVTNU = { 584, 11}, - .FCVTPS = { 595, 11}, - .FCVTPU = { 606, 11}, - .FCVTMS = { 617, 11}, - .FCVTMU = { 628, 11}, - .FRINTA = { 639, 11}, - .FRINTI = { 650, 11}, - .FRINTM = { 661, 11}, - .FRINTN = { 672, 11}, - .FRINTP = { 683, 11}, - .FRINTX = { 694, 11}, - .FRINTZ = { 705, 11}, - .TST = { 716, 4}, - .LDUR = { 720, 5}, - .STUR = { 725, 5}, - .LDURB = { 730, 1}, - .STURB = { 731, 1}, - .LDURSB = { 732, 2}, - .LDURH = { 734, 1}, - .STURH = { 735, 1}, - .LDURSH = { 736, 2}, - .LDURSW = { 738, 1}, - .LDNP = { 739, 2}, - .STNP = { 741, 2}, - .LDXP = { 743, 2}, - .STXP = { 745, 2}, - .LDAXP = { 747, 2}, - .STLXP = { 749, 2}, - .LDXRB = { 751, 1}, - .STXRB = { 752, 1}, - .LDAXRB = { 753, 1}, - .STLXRB = { 754, 1}, - .LDXRH = { 755, 1}, - .STXRH = { 756, 1}, - .LDAXRH = { 757, 1}, - .STLXRH = { 758, 1}, - .LDAPR = { 759, 2}, - .LDAPRB = { 761, 1}, - .LDAPRH = { 762, 1}, - .LDADD = { 763, 2}, - .LDADDA = { 765, 2}, - .LDADDL = { 767, 2}, - .LDADDAL = { 769, 2}, - .LDCLR = { 771, 2}, - .LDCLRA = { 773, 2}, - .LDCLRL = { 775, 2}, - .LDCLRAL = { 777, 2}, - .LDEOR = { 779, 2}, - .LDEORA = { 781, 2}, - .LDEORL = { 783, 2}, - .LDEORAL = { 785, 2}, - .LDSET = { 787, 2}, - .LDSETA = { 789, 2}, - .LDSETL = { 791, 2}, - .LDSETAL = { 793, 2}, - .LDSMAX = { 795, 2}, - .LDSMAXA = { 797, 2}, - .LDSMAXL = { 799, 2}, - .LDSMAXAL = { 801, 2}, - .LDSMIN = { 803, 2}, - .LDSMINA = { 805, 2}, - .LDSMINL = { 807, 2}, - .LDSMINAL = { 809, 2}, - .LDUMAX = { 811, 2}, - .LDUMAXA = { 813, 2}, - .LDUMAXL = { 815, 2}, - .LDUMAXAL = { 817, 2}, - .LDUMIN = { 819, 2}, - .LDUMINA = { 821, 2}, - .LDUMINL = { 823, 2}, - .LDUMINAL = { 825, 2}, - .SWP = { 827, 2}, - .SWPA = { 829, 2}, - .SWPL = { 831, 2}, - .SWPAL = { 833, 2}, - .CAS = { 835, 2}, - .CASA = { 837, 2}, - .CASL = { 839, 2}, - .CASAL = { 841, 2}, - .CASB = { 843, 1}, - .CASAB = { 844, 1}, - .CASLB = { 845, 1}, - .CASALB = { 846, 1}, - .CASH = { 847, 1}, - .CASAH = { 848, 1}, - .CASLH = { 849, 1}, - .CASALH = { 850, 1}, - .CASP = { 851, 2}, - .CASPA = { 853, 2}, - .CASPL = { 855, 2}, - .CASPAL = { 857, 2}, - .PACIA = { 859, 1}, - .PACIB = { 860, 1}, - .PACDA = { 861, 1}, - .PACDB = { 862, 1}, - .PACIZA = { 863, 1}, - .PACIZB = { 864, 1}, - .PACDZA = { 865, 1}, - .PACDZB = { 866, 1}, - .AUTIA = { 867, 1}, - .AUTIB = { 868, 1}, - .AUTDA = { 869, 1}, - .AUTDB = { 870, 1}, - .AUTIZA = { 871, 1}, - .AUTIZB = { 872, 1}, - .AUTDZA = { 873, 1}, - .AUTDZB = { 874, 1}, - .PACIASP = { 875, 1}, - .PACIBSP = { 876, 1}, - .AUTIASP = { 877, 1}, - .AUTIBSP = { 878, 1}, - .PACIA1716 = { 879, 1}, - .PACIB1716 = { 880, 1}, - .AUTIA1716 = { 881, 1}, - .AUTIB1716 = { 882, 1}, - .PACGA = { 883, 1}, - .XPACI = { 884, 1}, - .XPACD = { 885, 1}, - .XPACLRI = { 886, 1}, - .RETAA = { 887, 1}, - .RETAB = { 888, 1}, - .BRAA = { 889, 1}, - .BRAB = { 890, 1}, - .BRAAZ = { 891, 1}, - .BRABZ = { 892, 1}, - .BLRAA = { 893, 1}, - .BLRAB = { 894, 1}, - .BLRAAZ = { 895, 1}, - .BLRABZ = { 896, 1}, - .ERETAA = { 897, 1}, - .ERETAB = { 898, 1}, - .BTI = { 899, 1}, - .IRG = { 900, 1}, - .ADDG = { 901, 1}, - .SUBG = { 902, 1}, - .GMI = { 903, 1}, - .SUBP = { 904, 1}, - .SUBPS = { 905, 1}, - .LDG = { 906, 1}, - .STG = { 907, 1}, - .ST2G = { 908, 1}, - .STZG = { 909, 1}, - .STZ2G = { 910, 1}, - .STGP = { 911, 1}, - .LDGM = { 912, 1}, - .STGM = { 913, 1}, - .STZGM = { 914, 1}, - .CRC32B = { 915, 1}, - .CRC32H = { 916, 1}, - .CRC32W = { 917, 1}, - .CRC32X = { 918, 1}, - .CRC32CB = { 919, 1}, - .CRC32CH = { 920, 1}, - .CRC32CW = { 921, 1}, - .CRC32CX = { 922, 1}, - .AESE = { 923, 2}, - .AESD = { 925, 2}, - .AESMC = { 927, 2}, - .AESIMC = { 929, 2}, - .SHA1H = { 931, 1}, - .SHA1C = { 932, 1}, - .SHA1P = { 933, 1}, - .SHA1M = { 934, 1}, - .SHA1SU0 = { 935, 1}, - .SHA1SU1 = { 936, 1}, - .SHA256H = { 937, 1}, - .SHA256H2 = { 938, 1}, - .SHA256SU0 = { 939, 1}, - .SHA256SU1 = { 940, 1}, - .SHA512H = { 941, 1}, - .SHA512H2 = { 942, 1}, - .SHA512SU0 = { 943, 1}, - .SHA512SU1 = { 944, 1}, - .EOR3 = { 945, 2}, - .BCAX = { 947, 2}, - .RAX1 = { 949, 1}, - .XAR = { 950, 5}, - .SM3PARTW1 = { 955, 1}, - .SM3PARTW2 = { 956, 1}, - .SM3SS1 = { 957, 1}, - .SM3TT1A = { 958, 1}, - .SM3TT1B = { 959, 1}, - .SM3TT2A = { 960, 1}, - .SM3TT2B = { 961, 1}, - .SM4E = { 962, 1}, - .SM4EKEY = { 963, 1}, - .PMULL = { 964, 2}, - .PMULL2 = { 966, 2}, - .BFCVT = { 968, 2}, - .BFDOT = { 970, 1}, - .BFMMLA = { 971, 1}, - .BFMLALB = { 972, 1}, - .BFMLALT = { 973, 1}, - .BFCVTN = { 974, 1}, - .BFCVTN2 = { 975, 1}, - .MUL = { 976, 7}, - .MLA = { 983, 6}, - .MLS = { 989, 6}, - .NEG = { 995, 13}, - .ABS = { 1008, 11}, - .SHADD = { 1019, 6}, - .UHADD = { 1025, 6}, - .SHSUB = { 1031, 6}, - .UHSUB = { 1037, 6}, - .SRHADD = { 1043, 6}, - .URHADD = { 1049, 6}, - .SQADD = { 1055, 11}, - .UQADD = { 1066, 11}, - .SQSUB = { 1077, 11}, - .UQSUB = { 1088, 11}, - .SMAX = { 1099, 10}, - .UMAX = { 1109, 10}, - .SMIN = { 1119, 10}, - .UMIN = { 1129, 10}, - .SABD = { 1139, 10}, - .UABD = { 1149, 10}, - .SABA = { 1159, 6}, - .UABA = { 1165, 6}, - .ADDP = { 1171, 7}, - .ADDV = { 1178, 5}, - .SADDLP = { 1183, 6}, - .UADDLP = { 1189, 6}, - .SADALP = { 1195, 6}, - .UADALP = { 1201, 6}, - .SADDLV = { 1207, 5}, - .UADDLV = { 1212, 5}, - .SMAXV = { 1217, 5}, - .UMAXV = { 1222, 5}, - .SMINV = { 1227, 5}, - .UMINV = { 1232, 5}, - .SMAXP = { 1237, 6}, - .UMAXP = { 1243, 6}, - .SMINP = { 1249, 6}, - .UMINP = { 1255, 6}, - .SADDL = { 1261, 3}, - .SADDL2 = { 1264, 3}, - .UADDL = { 1267, 3}, - .UADDL2 = { 1270, 3}, - .SSUBL = { 1273, 3}, - .SSUBL2 = { 1276, 3}, - .USUBL = { 1279, 3}, - .USUBL2 = { 1282, 3}, - .SADDW = { 1285, 3}, - .SADDW2 = { 1288, 3}, - .UADDW = { 1291, 3}, - .UADDW2 = { 1294, 3}, - .SSUBW = { 1297, 3}, - .SSUBW2 = { 1300, 3}, - .USUBW = { 1303, 3}, - .USUBW2 = { 1306, 3}, - .RADDHN = { 1309, 3}, - .RADDHN2 = { 1312, 3}, - .RSUBHN = { 1315, 3}, - .RSUBHN2 = { 1318, 3}, - .ADDHN = { 1321, 3}, - .ADDHN2 = { 1324, 3}, - .SUBHN = { 1327, 3}, - .SUBHN2 = { 1330, 3}, - .XTN = { 1333, 3}, - .XTN2 = { 1336, 3}, - .SQXTN = { 1339, 3}, - .SQXTN2 = { 1342, 3}, - .UQXTN = { 1345, 3}, - .UQXTN2 = { 1348, 3}, - .SQXTUN = { 1351, 3}, - .SQXTUN2 = { 1354, 3}, - .SMULL = { 1357, 3}, - .SMULL2 = { 1360, 3}, - .UMULL = { 1363, 3}, - .UMULL2 = { 1366, 3}, - .SMLAL = { 1369, 3}, - .SMLAL2 = { 1372, 3}, - .UMLAL = { 1375, 3}, - .UMLAL2 = { 1378, 3}, - .SMLSL = { 1381, 3}, - .SMLSL2 = { 1384, 3}, - .UMLSL = { 1387, 3}, - .UMLSL2 = { 1390, 3}, - .SQDMULL = { 1393, 2}, - .SQDMULL2 = { 1395, 2}, - .SQDMLAL = { 1397, 2}, - .SQDMLAL2 = { 1399, 2}, - .SQDMLSL = { 1401, 2}, - .SQDMLSL2 = { 1403, 2}, - .SQDMULH = { 1405, 4}, - .SQRDMULH = { 1409, 4}, - .SDOT = { 1413, 2}, - .UDOT = { 1415, 2}, - .USDOT = { 1417, 2}, - .FMLA = { 1419, 8}, - .FMLS = { 1427, 8}, - .FMULX = { 1435, 5}, - .FMAXP = { 1440, 5}, - .FMINP = { 1445, 5}, - .FMAXNMP = { 1450, 5}, - .FMINNMP = { 1455, 5}, - .FMAXV = { 1460, 3}, - .FMINV = { 1463, 3}, - .FMAXNMV = { 1466, 3}, - .FMINNMV = { 1469, 3}, - .FRECPE = { 1472, 5}, - .FRSQRTE = { 1477, 5}, - .FRECPS = { 1482, 8}, - .FRSQRTS = { 1490, 8}, - .FRECPX = { 1498, 6}, - .FADDP = { 1504, 5}, - .FCVTL = { 1509, 2}, - .FCVTL2 = { 1511, 2}, - .FCVTN = { 1513, 2}, - .FCVTN2 = { 1515, 2}, - .FCVTXN = { 1517, 1}, - .FCVTXN2 = { 1518, 1}, - .FCMEQ = { 1519, 8}, - .FCMGE = { 1527, 8}, - .FCMGT = { 1535, 8}, - .FCMLE = { 1543, 8}, - .FCMLT = { 1551, 8}, - .FACGE = { 1559, 5}, - .FACGT = { 1564, 5}, - .CMEQ = { 1569, 4}, - .CMGE = { 1573, 7}, - .CMGT = { 1580, 2}, - .CMHI = { 1582, 2}, - .CMHS = { 1584, 7}, - .CMLE = { 1591, 7}, - .CMLT = { 1598, 7}, - .CMTST = { 1605, 7}, - .MVN = { 1612, 4}, - .BIT = { 1616, 1}, - .BIF = { 1617, 1}, - .BSL = { 1618, 2}, - .SHL = { 1620, 7}, - .SQSHL = { 1627, 7}, - .SQSHLU = { 1634, 7}, - .SRSHL = { 1641, 7}, - .URSHL = { 1648, 7}, - .SSHR = { 1655, 7}, - .USHR = { 1662, 7}, - .SSRA = { 1669, 7}, - .USRA = { 1676, 7}, - .SRSHR = { 1683, 7}, - .URSHR = { 1690, 7}, - .SRSRA = { 1697, 7}, - .URSRA = { 1704, 7}, - .SSHL = { 1711, 7}, - .USHL = { 1718, 7}, - .SLI = { 1725, 7}, - .SRI = { 1732, 7}, - .SSHLL = { 1739, 3}, - .SSHLL2 = { 1742, 3}, - .USHLL = { 1745, 3}, - .USHLL2 = { 1748, 3}, - .SXTL = { 1751, 3}, - .SXTL2 = { 1754, 3}, - .UXTL = { 1757, 3}, - .UXTL2 = { 1760, 3}, - .SHRN = { 1763, 3}, - .SHRN2 = { 1766, 3}, - .RSHRN = { 1769, 3}, - .RSHRN2 = { 1772, 3}, - .SQSHRN = { 1775, 3}, - .SQSHRN2 = { 1778, 3}, - .UQSHRN = { 1781, 3}, - .UQSHRN2 = { 1784, 3}, - .SQRSHRN = { 1787, 3}, - .SQRSHRN2 = { 1790, 3}, - .UQRSHRN = { 1793, 3}, - .UQRSHRN2 = { 1796, 3}, - .SQSHRUN = { 1799, 3}, - .SQSHRUN2 = { 1802, 3}, - .SQRSHRUN = { 1805, 3}, - .SQRSHRUN2 = { 1808, 3}, - .DUP = { 1811, 18}, - .INS = { 1829, 8}, - .MOV = { 1837, 12}, - .EXT = { 1849, 4}, - .TBL = { 1853, 6}, - .TBX = { 1859, 3}, - .ZIP1 = { 1862, 12}, - .ZIP2 = { 1874, 12}, - .UZP1 = { 1886, 12}, - .UZP2 = { 1898, 12}, - .TRN1 = { 1910, 12}, - .TRN2 = { 1922, 12}, - .NOT = { 1934, 3}, - .REV64 = { 1937, 6}, - .CNT = { 1943, 6}, - .URECPE = { 1949, 2}, - .URSQRTE = { 1951, 2}, - .MOVI = { 1953, 7}, - .MVNI = { 1960, 4}, - .LD1 = { 1964, 8}, - .LD2 = { 1972, 5}, - .LD3 = { 1977, 5}, - .LD4 = { 1982, 5}, - .ST1 = { 1987, 8}, - .ST2 = { 1995, 5}, - .ST3 = { 2000, 5}, - .ST4 = { 2005, 5}, - .LD1R = { 2010, 1}, - .LD2R = { 2011, 1}, - .LD3R = { 2012, 1}, - .LD4R = { 2013, 1}, - .SUBR = { 2014, 4}, - .ASRR = { 2018, 4}, - .LSLR = { 2022, 4}, - .LSRR = { 2026, 4}, - .FTSMUL = { 2030, 3}, - .FSUBR = { 2033, 3}, - .FDIVR = { 2036, 3}, - .FNMLA = { 2039, 3}, - .FNMLS = { 2042, 3}, - .NAND = { 2045, 1}, - .NOR = { 2046, 1}, - .SEL = { 2047, 1}, - .ORRS = { 2048, 1}, - .EORS = { 2049, 1}, - .NANDS = { 2050, 1}, - .NORS = { 2051, 1}, - .ORNS = { 2052, 1}, - .MOVS = { 2053, 1}, - .PTRUE = { 2054, 1}, - .PTRUES = { 2055, 1}, - .PFALSE = { 2056, 1}, - .PFIRST = { 2057, 1}, - .PNEXT = { 2058, 1}, - .BRKA = { 2059, 1}, - .BRKB = { 2060, 1}, - .BRKAS = { 2061, 1}, - .BRKBS = { 2062, 1}, - .BRKPA = { 2063, 1}, - .BRKPB = { 2064, 1}, - .BRKN = { 2065, 1}, - .RDFFR = { 2066, 1}, - .WRFFR = { 2067, 1}, - .SETFFR = { 2068, 1}, - .CMPEQ = { 2069, 4}, - .CMPNE = { 2073, 4}, - .CMPGE = { 2077, 4}, - .CMPGT = { 2081, 4}, - .CMPLE = { 2085, 4}, - .CMPLT = { 2089, 4}, - .CMPHI = { 2093, 4}, - .CMPHS = { 2097, 4}, - .CMPLO = { 2101, 4}, - .CMPLS = { 2105, 4}, - .FCMNE = { 2109, 3}, - .FCMUO = { 2112, 3}, - .INSR = { 2115, 4}, - .CPY = { 2119, 4}, - .COMPACT = { 2123, 2}, - .LD1B = { 2125, 6}, - .LD1H = { 2131, 6}, - .LD1W = { 2137, 6}, - .LD1D = { 2143, 5}, - .LD1SB = { 2148, 3}, - .LD1SH = { 2151, 3}, - .LD1SW = { 2154, 2}, - .ST1B = { 2156, 6}, - .ST1H = { 2162, 6}, - .ST1W = { 2168, 6}, - .ST1D = { 2174, 5}, - .LDFF1B = { 2179, 1}, - .LDFF1H = { 2180, 1}, - .LDFF1W = { 2181, 1}, - .LDFF1D = { 2182, 1}, - .WHILEGE = { 2183, 1}, - .WHILEGT = { 2184, 1}, - .WHILELE = { 2185, 1}, - .WHILELT = { 2186, 1}, - .WHILEHI = { 2187, 1}, - .WHILEHS = { 2188, 1}, - .WHILELO = { 2189, 1}, - .WHILELS = { 2190, 1}, - .SQRDMLAH = { 2191, 4}, - .SQRDMLSH = { 2195, 4}, - .ADCLB = { 2199, 2}, - .ADCLT = { 2201, 2}, - .SBCLB = { 2203, 2}, - .SBCLT = { 2205, 2}, - .TBL2 = { 2207, 1}, - .MATCH = { 2208, 2}, - .NMATCH = { 2210, 2}, - .HISTCNT = { 2212, 2}, - .HISTSEG = { 2214, 1}, - .SMSTART = { 2215, 1}, - .SMSTOP = { 2216, 1}, - .RDSVL = { 2217, 1}, - .ADDHA = { 2218, 1}, - .ADDVA = { 2219, 1}, - .ZERO = { 2220, 1}, - .FMOPA = { 2221, 1}, - .FMOPS = { 2222, 1}, - .BFMOPA = { 2223, 1}, - .BFMOPS = { 2224, 1}, - .SMOPA = { 2225, 2}, - .SMOPS = { 2227, 2}, - .UMOPA = { 2229, 2}, - .UMOPS = { 2231, 2}, - .USMOPA = { 2233, 1}, - .SUMOPA = { 2234, 1}, - .LD1Q = { 2235, 1}, - .ST1Q = { 2236, 1}, - .MOVA = { 2237, 2}, - .FCMLA = { 2239, 4}, - .FCADD = { 2243, 4}, - .PRFB = { 2247, 1}, - .PRFH = { 2248, 1}, - .PRFW = { 2249, 1}, - .PRFD = { 2250, 1}, - .LDNT1B = { 2251, 1}, - .LDNT1H = { 2252, 1}, - .LDNT1W = { 2253, 1}, - .LDNT1D = { 2254, 1}, - .STNT1B = { 2255, 1}, - .STNT1H = { 2256, 1}, - .STNT1W = { 2257, 1}, - .STNT1D = { 2258, 1}, - .SPLICE = { 2259, 1}, - .INDEX = { 2260, 4}, - .BSL1N = { 2264, 1}, - .BSL2N = { 2265, 1}, - .NBSL = { 2266, 1}, - .PMUL = { 2267, 1}, - .PMULLB = { 2268, 1}, - .PMULLT = { 2269, 1}, - .BFCVTNT = { 2270, 1}, - .LDRAA = { 2271, 2}, - .LDRAB = { 2273, 2}, - .TSTART = { 2275, 1}, - .TCOMMIT = { 2276, 1}, - .TCANCEL = { 2277, 1}, - .TTEST = { 2278, 1}, - .WFET = { 2279, 1}, - .WFIT = { 2280, 1}, - .BC_COND = { 2281, 1}, - .UXTB = { 2282, 1}, - .UXTH = { 2283, 1}, - .UXTW = { 2284, 1}, - .SXTB = { 2285, 1}, - .SXTH = { 2286, 1}, - .SXTW = { 2287, 1}, - .ADC = { 2288, 2}, - .ADCS = { 2290, 2}, - .SBC = { 2292, 2}, - .SBCS = { 2294, 2}, - .NGC = { 2296, 2}, - .NGCS = { 2298, 2}, - .LDAPUR = { 2300, 2}, - .STLUR = { 2302, 2}, - .LDAPURB = { 2304, 1}, - .STLURB = { 2305, 1}, - .LDAPURH = { 2306, 1}, - .STLURH = { 2307, 1}, - .LDAPURSB = { 2308, 2}, - .LDAPURSH = { 2310, 2}, - .LDAPURSW = { 2312, 1}, - .BFADD = { 2313, 2}, - .BFSUB = { 2315, 2}, - .BFMUL = { 2317, 2}, - .BFMLA = { 2319, 1}, - .BFMLS = { 2320, 1}, - .SB = { 2321, 1}, - .CSDB = { 2322, 1}, - .DGH = { 2323, 1}, - .PSB_CSYNC = { 2324, 1}, - .TSB_CSYNC = { 2325, 1}, - .BTI_J = { 2326, 1}, - .BTI_C = { 2327, 1}, - .BTI_JC = { 2328, 1}, - .BFCLAMP = { 2329, 1}, - .BFMAXNM = { 2330, 1}, - .BFMINNM = { 2331, 1}, - .LUTI2 = { 2332, 1}, - .LUTI4 = { 2333, 1}, - .ZIP = { 2334, 2}, - .UZP = { 2336, 2}, - .TLBI_RPALOS = { 2338, 1}, - .TLBI_RPAOS = { 2339, 1}, - .AT_S1E1A = { 2340, 1}, - .DC_CIPAPA = { 2341, 1}, - .DC_CIGDPAPA = { 2342, 1}, - .TLBI_PAALL = { 2343, 1}, - .TLBI_PAALLOS = { 2344, 1}, - .AMX_LDX = { 2345, 1}, - .AMX_LDY = { 2346, 1}, - .AMX_STX = { 2347, 1}, - .AMX_STY = { 2348, 1}, - .AMX_LDZ = { 2349, 1}, - .AMX_STZ = { 2350, 1}, - .AMX_LDZI = { 2351, 1}, - .AMX_STZI = { 2352, 1}, - .AMX_EXTRX = { 2353, 1}, - .AMX_EXTRY = { 2354, 1}, - .AMX_FMA64 = { 2355, 1}, - .AMX_FMS64 = { 2356, 1}, - .AMX_FMA32 = { 2357, 1}, - .AMX_FMS32 = { 2358, 1}, - .AMX_MAC16 = { 2359, 1}, - .AMX_FMA16 = { 2360, 1}, - .AMX_FMS16 = { 2361, 1}, - .AMX_SET = { 2362, 1}, - .AMX_CLR = { 2363, 1}, - .AMX_VECINT = { 2364, 1}, - .AMX_VECFP = { 2365, 1}, - .AMX_MATINT = { 2366, 1}, - .AMX_MATFP = { 2367, 1}, - .AMX_GENLUT = { 2368, 1}, - .CPYP = { 2369, 1}, - .CPYM = { 2370, 1}, - .CPYE = { 2371, 1}, - .CPYFP = { 2372, 1}, - .CPYFM = { 2373, 1}, - .CPYFE = { 2374, 1}, - .SETP = { 2375, 1}, - .SETM = { 2376, 1}, - .SETE = { 2377, 1}, - .DC_IVAC = { 2378, 1}, - .DC_ISW = { 2379, 1}, - .DC_CSW = { 2380, 1}, - .DC_CISW = { 2381, 1}, - .DC_ZVA = { 2382, 1}, - .DC_CVAC = { 2383, 1}, - .DC_CVAU = { 2384, 1}, - .DC_CIVAC = { 2385, 1}, - .IC_IALLUIS = { 2386, 1}, - .IC_IALLU = { 2387, 1}, - .IC_IVAU = { 2388, 1}, - .AT_S1E1R = { 2389, 1}, - .AT_S1E1W = { 2390, 1}, - .AT_S1E0R = { 2391, 1}, - .AT_S1E0W = { 2392, 1}, - .AT_S1E2R = { 2393, 1}, - .AT_S1E2W = { 2394, 1}, - .AT_S1E3R = { 2395, 1}, - .AT_S1E3W = { 2396, 1}, - .AT_S12E1R = { 2397, 1}, - .AT_S12E1W = { 2398, 1}, - .AT_S12E0R = { 2399, 1}, - .AT_S12E0W = { 2400, 1}, - .TLBI_VMALLE1 = { 2401, 1}, - .TLBI_VMALLE1IS = { 2402, 1}, - .TLBI_VAE1 = { 2403, 1}, - .TLBI_VAE1IS = { 2404, 1}, - .TLBI_ASIDE1 = { 2405, 1}, - .TLBI_ASIDE1IS = { 2406, 1}, - .TLBI_VAAE1 = { 2407, 1}, - .TLBI_VAAE1IS = { 2408, 1}, - .TLBI_VALE1 = { 2409, 1}, - .TLBI_VALE1IS = { 2410, 1}, - .TLBI_VAALE1 = { 2411, 1}, - .TLBI_VAALE1IS = { 2412, 1}, - .TLBI_ALLE1 = { 2413, 1}, - .TLBI_ALLE1IS = { 2414, 1}, - .TLBI_ALLE2 = { 2415, 1}, - .TLBI_ALLE2IS = { 2416, 1}, - .TLBI_ALLE3 = { 2417, 1}, - .TLBI_ALLE3IS = { 2418, 1}, - .PRFM = { 2419, 2}, - .PRFUM = { 2421, 1}, - .NEGS = { 2422, 2}, - .CMP = { 2424, 6}, - .CMN = { 2430, 6}, + .B_EQ = { 221, 1}, + .B_NE = { 222, 1}, + .B_CS = { 223, 1}, + .B_CC = { 224, 1}, + .B_MI = { 225, 1}, + .B_PL = { 226, 1}, + .B_VS = { 227, 1}, + .B_VC = { 228, 1}, + .B_HI = { 229, 1}, + .B_LS = { 230, 1}, + .B_GE = { 231, 1}, + .B_LT = { 232, 1}, + .B_GT = { 233, 1}, + .B_LE = { 234, 1}, + .B_AL = { 235, 1}, + .B_NV = { 236, 1}, + .CBZ = { 237, 2}, + .CBNZ = { 239, 2}, + .TBZ = { 241, 1}, + .TBNZ = { 242, 1}, + .LDR = { 243, 18}, + .STR = { 261, 16}, + .LDRB = { 277, 4}, + .STRB = { 281, 4}, + .LDRSB = { 285, 4}, + .LDRH = { 289, 4}, + .STRH = { 293, 4}, + .LDRSH = { 297, 4}, + .LDRSW = { 301, 2}, + .LDP = { 303, 9}, + .STP = { 312, 9}, + .LDPSW = { 321, 3}, + .LDAR = { 324, 2}, + .STLR = { 326, 2}, + .LDARB = { 328, 1}, + .STLRB = { 329, 1}, + .LDARH = { 330, 1}, + .STLRH = { 331, 1}, + .LDXR = { 332, 2}, + .STXR = { 334, 2}, + .LDAXR = { 336, 2}, + .STLXR = { 338, 2}, + .NOP = { 340, 1}, + .YIELD = { 341, 1}, + .WFE = { 342, 1}, + .WFI = { 343, 1}, + .SEV = { 344, 1}, + .SEVL = { 345, 1}, + .HINT = { 346, 1}, + .MRS = { 347, 1}, + .MSR = { 348, 2}, + .ISB = { 350, 1}, + .DSB = { 351, 1}, + .DMB = { 352, 1}, + .SVC = { 353, 1}, + .HVC = { 354, 1}, + .SMC = { 355, 1}, + .BRK = { 356, 1}, + .HLT = { 357, 1}, + .ERET = { 358, 1}, + .FMOV = { 359, 15}, + .FABS = { 374, 11}, + .FNEG = { 385, 11}, + .FSQRT = { 396, 11}, + .FADD = { 407, 12}, + .FSUB = { 419, 12}, + .FMUL = { 431, 12}, + .FDIV = { 443, 9}, + .FNMUL = { 452, 3}, + .FMADD = { 455, 3}, + .FMSUB = { 458, 3}, + .FNMADD = { 461, 3}, + .FNMSUB = { 464, 3}, + .FCMP = { 467, 3}, + .FCMPE = { 470, 3}, + .FCSEL = { 473, 3}, + .FMAX = { 476, 11}, + .FMIN = { 487, 11}, + .FMAXNM = { 498, 11}, + .FMINNM = { 509, 11}, + .FCVT = { 520, 6}, + .SCVTF = { 526, 10}, + .UCVTF = { 536, 10}, + .FCVTZS = { 546, 10}, + .FCVTZU = { 556, 10}, + .FCVTAS = { 566, 11}, + .FCVTAU = { 577, 11}, + .FCVTNS = { 588, 11}, + .FCVTNU = { 599, 11}, + .FCVTPS = { 610, 11}, + .FCVTPU = { 621, 11}, + .FCVTMS = { 632, 11}, + .FCVTMU = { 643, 11}, + .FRINTA = { 654, 11}, + .FRINTI = { 665, 11}, + .FRINTM = { 676, 11}, + .FRINTN = { 687, 11}, + .FRINTP = { 698, 11}, + .FRINTX = { 709, 11}, + .FRINTZ = { 720, 11}, + .TST = { 731, 4}, + .LDUR = { 735, 5}, + .STUR = { 740, 5}, + .LDURB = { 745, 1}, + .STURB = { 746, 1}, + .LDURSB = { 747, 2}, + .LDURH = { 749, 1}, + .STURH = { 750, 1}, + .LDURSH = { 751, 2}, + .LDURSW = { 753, 1}, + .LDNP = { 754, 2}, + .STNP = { 756, 2}, + .LDXP = { 758, 2}, + .STXP = { 760, 2}, + .LDAXP = { 762, 2}, + .STLXP = { 764, 2}, + .LDXRB = { 766, 1}, + .STXRB = { 767, 1}, + .LDAXRB = { 768, 1}, + .STLXRB = { 769, 1}, + .LDXRH = { 770, 1}, + .STXRH = { 771, 1}, + .LDAXRH = { 772, 1}, + .STLXRH = { 773, 1}, + .LDAPR = { 774, 2}, + .LDAPRB = { 776, 1}, + .LDAPRH = { 777, 1}, + .LDADD = { 778, 2}, + .LDADDA = { 780, 2}, + .LDADDL = { 782, 2}, + .LDADDAL = { 784, 2}, + .LDCLR = { 786, 2}, + .LDCLRA = { 788, 2}, + .LDCLRL = { 790, 2}, + .LDCLRAL = { 792, 2}, + .LDEOR = { 794, 2}, + .LDEORA = { 796, 2}, + .LDEORL = { 798, 2}, + .LDEORAL = { 800, 2}, + .LDSET = { 802, 2}, + .LDSETA = { 804, 2}, + .LDSETL = { 806, 2}, + .LDSETAL = { 808, 2}, + .LDSMAX = { 810, 2}, + .LDSMAXA = { 812, 2}, + .LDSMAXL = { 814, 2}, + .LDSMAXAL = { 816, 2}, + .LDSMIN = { 818, 2}, + .LDSMINA = { 820, 2}, + .LDSMINL = { 822, 2}, + .LDSMINAL = { 824, 2}, + .LDUMAX = { 826, 2}, + .LDUMAXA = { 828, 2}, + .LDUMAXL = { 830, 2}, + .LDUMAXAL = { 832, 2}, + .LDUMIN = { 834, 2}, + .LDUMINA = { 836, 2}, + .LDUMINL = { 838, 2}, + .LDUMINAL = { 840, 2}, + .SWP = { 842, 2}, + .SWPA = { 844, 2}, + .SWPL = { 846, 2}, + .SWPAL = { 848, 2}, + .CAS = { 850, 2}, + .CASA = { 852, 2}, + .CASL = { 854, 2}, + .CASAL = { 856, 2}, + .CASB = { 858, 1}, + .CASAB = { 859, 1}, + .CASLB = { 860, 1}, + .CASALB = { 861, 1}, + .CASH = { 862, 1}, + .CASAH = { 863, 1}, + .CASLH = { 864, 1}, + .CASALH = { 865, 1}, + .CASP = { 866, 2}, + .CASPA = { 868, 2}, + .CASPL = { 870, 2}, + .CASPAL = { 872, 2}, + .PACIA = { 874, 1}, + .PACIB = { 875, 1}, + .PACDA = { 876, 1}, + .PACDB = { 877, 1}, + .PACIZA = { 878, 1}, + .PACIZB = { 879, 1}, + .PACDZA = { 880, 1}, + .PACDZB = { 881, 1}, + .AUTIA = { 882, 1}, + .AUTIB = { 883, 1}, + .AUTDA = { 884, 1}, + .AUTDB = { 885, 1}, + .AUTIZA = { 886, 1}, + .AUTIZB = { 887, 1}, + .AUTDZA = { 888, 1}, + .AUTDZB = { 889, 1}, + .PACIASP = { 890, 1}, + .PACIBSP = { 891, 1}, + .AUTIASP = { 892, 1}, + .AUTIBSP = { 893, 1}, + .PACIA1716 = { 894, 1}, + .PACIB1716 = { 895, 1}, + .AUTIA1716 = { 896, 1}, + .AUTIB1716 = { 897, 1}, + .PACGA = { 898, 1}, + .XPACI = { 899, 1}, + .XPACD = { 900, 1}, + .XPACLRI = { 901, 1}, + .RETAA = { 902, 1}, + .RETAB = { 903, 1}, + .BRAA = { 904, 1}, + .BRAB = { 905, 1}, + .BRAAZ = { 906, 1}, + .BRABZ = { 907, 1}, + .BLRAA = { 908, 1}, + .BLRAB = { 909, 1}, + .BLRAAZ = { 910, 1}, + .BLRABZ = { 911, 1}, + .ERETAA = { 912, 1}, + .ERETAB = { 913, 1}, + .BTI = { 914, 1}, + .IRG = { 915, 1}, + .ADDG = { 916, 1}, + .SUBG = { 917, 1}, + .GMI = { 918, 1}, + .SUBP = { 919, 1}, + .SUBPS = { 920, 1}, + .LDG = { 921, 1}, + .STG = { 922, 1}, + .ST2G = { 923, 1}, + .STZG = { 924, 1}, + .STZ2G = { 925, 1}, + .STGP = { 926, 1}, + .LDGM = { 927, 1}, + .STGM = { 928, 1}, + .STZGM = { 929, 1}, + .CRC32B = { 930, 1}, + .CRC32H = { 931, 1}, + .CRC32W = { 932, 1}, + .CRC32X = { 933, 1}, + .CRC32CB = { 934, 1}, + .CRC32CH = { 935, 1}, + .CRC32CW = { 936, 1}, + .CRC32CX = { 937, 1}, + .AESE = { 938, 2}, + .AESD = { 940, 2}, + .AESMC = { 942, 2}, + .AESIMC = { 944, 2}, + .SHA1H = { 946, 1}, + .SHA1C = { 947, 1}, + .SHA1P = { 948, 1}, + .SHA1M = { 949, 1}, + .SHA1SU0 = { 950, 1}, + .SHA1SU1 = { 951, 1}, + .SHA256H = { 952, 1}, + .SHA256H2 = { 953, 1}, + .SHA256SU0 = { 954, 1}, + .SHA256SU1 = { 955, 1}, + .SHA512H = { 956, 1}, + .SHA512H2 = { 957, 1}, + .SHA512SU0 = { 958, 1}, + .SHA512SU1 = { 959, 1}, + .EOR3 = { 960, 2}, + .BCAX = { 962, 2}, + .RAX1 = { 964, 1}, + .XAR = { 965, 5}, + .SM3PARTW1 = { 970, 1}, + .SM3PARTW2 = { 971, 1}, + .SM3SS1 = { 972, 1}, + .SM3TT1A = { 973, 1}, + .SM3TT1B = { 974, 1}, + .SM3TT2A = { 975, 1}, + .SM3TT2B = { 976, 1}, + .SM4E = { 977, 1}, + .SM4EKEY = { 978, 1}, + .PMULL = { 979, 2}, + .PMULL2 = { 981, 2}, + .BFCVT = { 983, 2}, + .BFDOT = { 985, 1}, + .BFMMLA = { 986, 1}, + .BFMLALB = { 987, 1}, + .BFMLALT = { 988, 1}, + .BFCVTN = { 989, 1}, + .BFCVTN2 = { 990, 1}, + .MUL = { 991, 7}, + .MLA = { 998, 6}, + .MLS = { 1004, 6}, + .NEG = { 1010, 13}, + .ABS = { 1023, 11}, + .SHADD = { 1034, 6}, + .UHADD = { 1040, 6}, + .SHSUB = { 1046, 6}, + .UHSUB = { 1052, 6}, + .SRHADD = { 1058, 6}, + .URHADD = { 1064, 6}, + .SQADD = { 1070, 11}, + .UQADD = { 1081, 11}, + .SQSUB = { 1092, 11}, + .UQSUB = { 1103, 11}, + .SMAX = { 1114, 10}, + .UMAX = { 1124, 10}, + .SMIN = { 1134, 10}, + .UMIN = { 1144, 10}, + .SABD = { 1154, 10}, + .UABD = { 1164, 10}, + .SABA = { 1174, 6}, + .UABA = { 1180, 6}, + .ADDP = { 1186, 7}, + .ADDV = { 1193, 5}, + .SADDLP = { 1198, 6}, + .UADDLP = { 1204, 6}, + .SADALP = { 1210, 6}, + .UADALP = { 1216, 6}, + .SADDLV = { 1222, 5}, + .UADDLV = { 1227, 5}, + .SMAXV = { 1232, 5}, + .UMAXV = { 1237, 5}, + .SMINV = { 1242, 5}, + .UMINV = { 1247, 5}, + .SMAXP = { 1252, 6}, + .UMAXP = { 1258, 6}, + .SMINP = { 1264, 6}, + .UMINP = { 1270, 6}, + .SADDL = { 1276, 3}, + .SADDL2 = { 1279, 3}, + .UADDL = { 1282, 3}, + .UADDL2 = { 1285, 3}, + .SSUBL = { 1288, 3}, + .SSUBL2 = { 1291, 3}, + .USUBL = { 1294, 3}, + .USUBL2 = { 1297, 3}, + .SADDW = { 1300, 3}, + .SADDW2 = { 1303, 3}, + .UADDW = { 1306, 3}, + .UADDW2 = { 1309, 3}, + .SSUBW = { 1312, 3}, + .SSUBW2 = { 1315, 3}, + .USUBW = { 1318, 3}, + .USUBW2 = { 1321, 3}, + .RADDHN = { 1324, 3}, + .RADDHN2 = { 1327, 3}, + .RSUBHN = { 1330, 3}, + .RSUBHN2 = { 1333, 3}, + .ADDHN = { 1336, 3}, + .ADDHN2 = { 1339, 3}, + .SUBHN = { 1342, 3}, + .SUBHN2 = { 1345, 3}, + .XTN = { 1348, 3}, + .XTN2 = { 1351, 3}, + .SQXTN = { 1354, 3}, + .SQXTN2 = { 1357, 3}, + .UQXTN = { 1360, 3}, + .UQXTN2 = { 1363, 3}, + .SQXTUN = { 1366, 3}, + .SQXTUN2 = { 1369, 3}, + .SMULL = { 1372, 3}, + .SMULL2 = { 1375, 3}, + .UMULL = { 1378, 3}, + .UMULL2 = { 1381, 3}, + .SMLAL = { 1384, 3}, + .SMLAL2 = { 1387, 3}, + .UMLAL = { 1390, 3}, + .UMLAL2 = { 1393, 3}, + .SMLSL = { 1396, 3}, + .SMLSL2 = { 1399, 3}, + .UMLSL = { 1402, 3}, + .UMLSL2 = { 1405, 3}, + .SQDMULL = { 1408, 2}, + .SQDMULL2 = { 1410, 2}, + .SQDMLAL = { 1412, 2}, + .SQDMLAL2 = { 1414, 2}, + .SQDMLSL = { 1416, 2}, + .SQDMLSL2 = { 1418, 2}, + .SQDMULH = { 1420, 4}, + .SQRDMULH = { 1424, 4}, + .SDOT = { 1428, 2}, + .UDOT = { 1430, 2}, + .USDOT = { 1432, 2}, + .FMLA = { 1434, 8}, + .FMLS = { 1442, 8}, + .FMULX = { 1450, 5}, + .FMAXP = { 1455, 5}, + .FMINP = { 1460, 5}, + .FMAXNMP = { 1465, 5}, + .FMINNMP = { 1470, 5}, + .FMAXV = { 1475, 3}, + .FMINV = { 1478, 3}, + .FMAXNMV = { 1481, 3}, + .FMINNMV = { 1484, 3}, + .FRECPE = { 1487, 5}, + .FRSQRTE = { 1492, 5}, + .FRECPS = { 1497, 8}, + .FRSQRTS = { 1505, 8}, + .FRECPX = { 1513, 6}, + .FADDP = { 1519, 5}, + .FCVTL = { 1524, 2}, + .FCVTL2 = { 1526, 2}, + .FCVTN = { 1528, 2}, + .FCVTN2 = { 1530, 2}, + .FCVTXN = { 1532, 1}, + .FCVTXN2 = { 1533, 1}, + .FCMEQ = { 1534, 8}, + .FCMGE = { 1542, 8}, + .FCMGT = { 1550, 8}, + .FCMLE = { 1558, 8}, + .FCMLT = { 1566, 8}, + .FACGE = { 1574, 5}, + .FACGT = { 1579, 5}, + .CMEQ = { 1584, 4}, + .CMGE = { 1588, 7}, + .CMGT = { 1595, 2}, + .CMHI = { 1597, 2}, + .CMHS = { 1599, 7}, + .CMLE = { 1606, 7}, + .CMLT = { 1613, 7}, + .CMTST = { 1620, 7}, + .MVN = { 1627, 4}, + .BIT = { 1631, 1}, + .BIF = { 1632, 1}, + .BSL = { 1633, 2}, + .SHL = { 1635, 7}, + .SQSHL = { 1642, 7}, + .SQSHLU = { 1649, 7}, + .SRSHL = { 1656, 7}, + .URSHL = { 1663, 7}, + .SSHR = { 1670, 7}, + .USHR = { 1677, 7}, + .SSRA = { 1684, 7}, + .USRA = { 1691, 7}, + .SRSHR = { 1698, 7}, + .URSHR = { 1705, 7}, + .SRSRA = { 1712, 7}, + .URSRA = { 1719, 7}, + .SSHL = { 1726, 7}, + .USHL = { 1733, 7}, + .SLI = { 1740, 7}, + .SRI = { 1747, 7}, + .SSHLL = { 1754, 3}, + .SSHLL2 = { 1757, 3}, + .USHLL = { 1760, 3}, + .USHLL2 = { 1763, 3}, + .SXTL = { 1766, 3}, + .SXTL2 = { 1769, 3}, + .UXTL = { 1772, 3}, + .UXTL2 = { 1775, 3}, + .SHRN = { 1778, 3}, + .SHRN2 = { 1781, 3}, + .RSHRN = { 1784, 3}, + .RSHRN2 = { 1787, 3}, + .SQSHRN = { 1790, 3}, + .SQSHRN2 = { 1793, 3}, + .UQSHRN = { 1796, 3}, + .UQSHRN2 = { 1799, 3}, + .SQRSHRN = { 1802, 3}, + .SQRSHRN2 = { 1805, 3}, + .UQRSHRN = { 1808, 3}, + .UQRSHRN2 = { 1811, 3}, + .SQSHRUN = { 1814, 3}, + .SQSHRUN2 = { 1817, 3}, + .SQRSHRUN = { 1820, 3}, + .SQRSHRUN2 = { 1823, 3}, + .DUP = { 1826, 18}, + .INS = { 1844, 8}, + .MOV = { 1852, 12}, + .EXT = { 1864, 4}, + .TBL = { 1868, 6}, + .TBX = { 1874, 3}, + .ZIP1 = { 1877, 12}, + .ZIP2 = { 1889, 12}, + .UZP1 = { 1901, 12}, + .UZP2 = { 1913, 12}, + .TRN1 = { 1925, 12}, + .TRN2 = { 1937, 12}, + .NOT = { 1949, 3}, + .REV64 = { 1952, 6}, + .CNT = { 1958, 6}, + .URECPE = { 1964, 2}, + .URSQRTE = { 1966, 2}, + .MOVI = { 1968, 7}, + .MVNI = { 1975, 4}, + .LD1 = { 1979, 8}, + .LD2 = { 1987, 5}, + .LD3 = { 1992, 5}, + .LD4 = { 1997, 5}, + .ST1 = { 2002, 8}, + .ST2 = { 2010, 5}, + .ST3 = { 2015, 5}, + .ST4 = { 2020, 5}, + .LD1R = { 2025, 1}, + .LD2R = { 2026, 1}, + .LD3R = { 2027, 1}, + .LD4R = { 2028, 1}, + .SUBR = { 2029, 4}, + .ASRR = { 2033, 4}, + .LSLR = { 2037, 4}, + .LSRR = { 2041, 4}, + .FTSMUL = { 2045, 3}, + .FSUBR = { 2048, 3}, + .FDIVR = { 2051, 3}, + .FNMLA = { 2054, 3}, + .FNMLS = { 2057, 3}, + .NAND = { 2060, 1}, + .NOR = { 2061, 1}, + .SEL = { 2062, 1}, + .ORRS = { 2063, 1}, + .EORS = { 2064, 1}, + .NANDS = { 2065, 1}, + .NORS = { 2066, 1}, + .ORNS = { 2067, 1}, + .MOVS = { 2068, 1}, + .PTRUE = { 2069, 1}, + .PTRUES = { 2070, 1}, + .PFALSE = { 2071, 1}, + .PFIRST = { 2072, 1}, + .PNEXT = { 2073, 1}, + .BRKA = { 2074, 1}, + .BRKB = { 2075, 1}, + .BRKAS = { 2076, 1}, + .BRKBS = { 2077, 1}, + .BRKPA = { 2078, 1}, + .BRKPB = { 2079, 1}, + .BRKN = { 2080, 1}, + .RDFFR = { 2081, 1}, + .WRFFR = { 2082, 1}, + .SETFFR = { 2083, 1}, + .CMPEQ = { 2084, 4}, + .CMPNE = { 2088, 4}, + .CMPGE = { 2092, 4}, + .CMPGT = { 2096, 4}, + .CMPLE = { 2100, 4}, + .CMPLT = { 2104, 4}, + .CMPHI = { 2108, 4}, + .CMPHS = { 2112, 4}, + .CMPLO = { 2116, 4}, + .CMPLS = { 2120, 4}, + .FCMNE = { 2124, 3}, + .FCMUO = { 2127, 3}, + .INSR = { 2130, 4}, + .CPY = { 2134, 4}, + .COMPACT = { 2138, 2}, + .LD1B = { 2140, 6}, + .LD1H = { 2146, 6}, + .LD1W = { 2152, 6}, + .LD1D = { 2158, 5}, + .LD1SB = { 2163, 3}, + .LD1SH = { 2166, 3}, + .LD1SW = { 2169, 2}, + .ST1B = { 2171, 6}, + .ST1H = { 2177, 6}, + .ST1W = { 2183, 6}, + .ST1D = { 2189, 5}, + .LDFF1B = { 2194, 1}, + .LDFF1H = { 2195, 1}, + .LDFF1W = { 2196, 1}, + .LDFF1D = { 2197, 1}, + .WHILEGE = { 2198, 1}, + .WHILEGT = { 2199, 1}, + .WHILELE = { 2200, 1}, + .WHILELT = { 2201, 1}, + .WHILEHI = { 2202, 1}, + .WHILEHS = { 2203, 1}, + .WHILELO = { 2204, 1}, + .WHILELS = { 2205, 1}, + .SQRDMLAH = { 2206, 4}, + .SQRDMLSH = { 2210, 4}, + .ADCLB = { 2214, 2}, + .ADCLT = { 2216, 2}, + .SBCLB = { 2218, 2}, + .SBCLT = { 2220, 2}, + .TBL2 = { 2222, 1}, + .MATCH = { 2223, 2}, + .NMATCH = { 2225, 2}, + .HISTCNT = { 2227, 2}, + .HISTSEG = { 2229, 1}, + .SMSTART = { 2230, 1}, + .SMSTOP = { 2231, 1}, + .RDSVL = { 2232, 1}, + .ADDHA = { 2233, 1}, + .ADDVA = { 2234, 1}, + .ZERO = { 2235, 1}, + .FMOPA = { 2236, 1}, + .FMOPS = { 2237, 1}, + .BFMOPA = { 2238, 1}, + .BFMOPS = { 2239, 1}, + .SMOPA = { 2240, 2}, + .SMOPS = { 2242, 2}, + .UMOPA = { 2244, 2}, + .UMOPS = { 2246, 2}, + .USMOPA = { 2248, 1}, + .SUMOPA = { 2249, 1}, + .LD1Q = { 2250, 1}, + .ST1Q = { 2251, 1}, + .MOVA = { 2252, 2}, + .FCMLA = { 2254, 4}, + .FCADD = { 2258, 4}, + .PRFB = { 2262, 1}, + .PRFH = { 2263, 1}, + .PRFW = { 2264, 1}, + .PRFD = { 2265, 1}, + .LDNT1B = { 2266, 1}, + .LDNT1H = { 2267, 1}, + .LDNT1W = { 2268, 1}, + .LDNT1D = { 2269, 1}, + .STNT1B = { 2270, 1}, + .STNT1H = { 2271, 1}, + .STNT1W = { 2272, 1}, + .STNT1D = { 2273, 1}, + .SPLICE = { 2274, 1}, + .INDEX = { 2275, 4}, + .BSL1N = { 2279, 1}, + .BSL2N = { 2280, 1}, + .NBSL = { 2281, 1}, + .PMUL = { 2282, 1}, + .PMULLB = { 2283, 1}, + .PMULLT = { 2284, 1}, + .BFCVTNT = { 2285, 1}, + .LDRAA = { 2286, 2}, + .LDRAB = { 2288, 2}, + .TSTART = { 2290, 1}, + .TCOMMIT = { 2291, 1}, + .TCANCEL = { 2292, 1}, + .TTEST = { 2293, 1}, + .WFET = { 2294, 1}, + .WFIT = { 2295, 1}, + .BC_EQ = { 2296, 1}, + .BC_NE = { 2297, 1}, + .BC_CS = { 2298, 1}, + .BC_CC = { 2299, 1}, + .BC_MI = { 2300, 1}, + .BC_PL = { 2301, 1}, + .BC_VS = { 2302, 1}, + .BC_VC = { 2303, 1}, + .BC_HI = { 2304, 1}, + .BC_LS = { 2305, 1}, + .BC_GE = { 2306, 1}, + .BC_LT = { 2307, 1}, + .BC_GT = { 2308, 1}, + .BC_LE = { 2309, 1}, + .BC_AL = { 2310, 1}, + .BC_NV = { 2311, 1}, + .UXTB = { 2312, 1}, + .UXTH = { 2313, 1}, + .UXTW = { 2314, 1}, + .SXTB = { 2315, 1}, + .SXTH = { 2316, 1}, + .SXTW = { 2317, 1}, + .ADC = { 2318, 2}, + .ADCS = { 2320, 2}, + .SBC = { 2322, 2}, + .SBCS = { 2324, 2}, + .NGC = { 2326, 2}, + .NGCS = { 2328, 2}, + .LDAPUR = { 2330, 2}, + .STLUR = { 2332, 2}, + .LDAPURB = { 2334, 1}, + .STLURB = { 2335, 1}, + .LDAPURH = { 2336, 1}, + .STLURH = { 2337, 1}, + .LDAPURSB = { 2338, 2}, + .LDAPURSH = { 2340, 2}, + .LDAPURSW = { 2342, 1}, + .BFADD = { 2343, 2}, + .BFSUB = { 2345, 2}, + .BFMUL = { 2347, 2}, + .BFMLA = { 2349, 1}, + .BFMLS = { 2350, 1}, + .SB = { 2351, 1}, + .CSDB = { 2352, 1}, + .DGH = { 2353, 1}, + .PSB_CSYNC = { 2354, 1}, + .TSB_CSYNC = { 2355, 1}, + .BTI_J = { 2356, 1}, + .BTI_C = { 2357, 1}, + .BTI_JC = { 2358, 1}, + .BFCLAMP = { 2359, 1}, + .BFMAXNM = { 2360, 1}, + .BFMINNM = { 2361, 1}, + .LUTI2 = { 2362, 1}, + .LUTI4 = { 2363, 1}, + .ZIP = { 2364, 2}, + .UZP = { 2366, 2}, + .TLBI_RPALOS = { 2368, 1}, + .TLBI_RPAOS = { 2369, 1}, + .AT_S1E1A = { 2370, 1}, + .DC_CIPAPA = { 2371, 1}, + .DC_CIGDPAPA = { 2372, 1}, + .TLBI_PAALL = { 2373, 1}, + .TLBI_PAALLOS = { 2374, 1}, + .AMX_LDX = { 2375, 1}, + .AMX_LDY = { 2376, 1}, + .AMX_STX = { 2377, 1}, + .AMX_STY = { 2378, 1}, + .AMX_LDZ = { 2379, 1}, + .AMX_STZ = { 2380, 1}, + .AMX_LDZI = { 2381, 1}, + .AMX_STZI = { 2382, 1}, + .AMX_EXTRX = { 2383, 1}, + .AMX_EXTRY = { 2384, 1}, + .AMX_FMA64 = { 2385, 1}, + .AMX_FMS64 = { 2386, 1}, + .AMX_FMA32 = { 2387, 1}, + .AMX_FMS32 = { 2388, 1}, + .AMX_MAC16 = { 2389, 1}, + .AMX_FMA16 = { 2390, 1}, + .AMX_FMS16 = { 2391, 1}, + .AMX_SET = { 2392, 1}, + .AMX_CLR = { 2393, 1}, + .AMX_VECINT = { 2394, 1}, + .AMX_VECFP = { 2395, 1}, + .AMX_MATINT = { 2396, 1}, + .AMX_MATFP = { 2397, 1}, + .AMX_GENLUT = { 2398, 1}, + .CPYP = { 2399, 1}, + .CPYM = { 2400, 1}, + .CPYE = { 2401, 1}, + .CPYFP = { 2402, 1}, + .CPYFM = { 2403, 1}, + .CPYFE = { 2404, 1}, + .SETP = { 2405, 1}, + .SETM = { 2406, 1}, + .SETE = { 2407, 1}, + .DC_IVAC = { 2408, 1}, + .DC_ISW = { 2409, 1}, + .DC_CSW = { 2410, 1}, + .DC_CISW = { 2411, 1}, + .DC_ZVA = { 2412, 1}, + .DC_CVAC = { 2413, 1}, + .DC_CVAU = { 2414, 1}, + .DC_CIVAC = { 2415, 1}, + .IC_IALLUIS = { 2416, 1}, + .IC_IALLU = { 2417, 1}, + .IC_IVAU = { 2418, 1}, + .AT_S1E1R = { 2419, 1}, + .AT_S1E1W = { 2420, 1}, + .AT_S1E0R = { 2421, 1}, + .AT_S1E0W = { 2422, 1}, + .AT_S1E2R = { 2423, 1}, + .AT_S1E2W = { 2424, 1}, + .AT_S1E3R = { 2425, 1}, + .AT_S1E3W = { 2426, 1}, + .AT_S12E1R = { 2427, 1}, + .AT_S12E1W = { 2428, 1}, + .AT_S12E0R = { 2429, 1}, + .AT_S12E0W = { 2430, 1}, + .TLBI_VMALLE1 = { 2431, 1}, + .TLBI_VMALLE1IS = { 2432, 1}, + .TLBI_VAE1 = { 2433, 1}, + .TLBI_VAE1IS = { 2434, 1}, + .TLBI_ASIDE1 = { 2435, 1}, + .TLBI_ASIDE1IS = { 2436, 1}, + .TLBI_VAAE1 = { 2437, 1}, + .TLBI_VAAE1IS = { 2438, 1}, + .TLBI_VALE1 = { 2439, 1}, + .TLBI_VALE1IS = { 2440, 1}, + .TLBI_VAALE1 = { 2441, 1}, + .TLBI_VAALE1IS = { 2442, 1}, + .TLBI_ALLE1 = { 2443, 1}, + .TLBI_ALLE1IS = { 2444, 1}, + .TLBI_ALLE2 = { 2445, 1}, + .TLBI_ALLE2IS = { 2446, 1}, + .TLBI_ALLE3 = { 2447, 1}, + .TLBI_ALLE3IS = { 2448, 1}, + .PRFM = { 2449, 2}, + .PRFUM = { 2451, 1}, + .NEGS = { 2452, 2}, + .CMP = { 2454, 6}, + .CMN = { 2460, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 9e720cd35..e7ad938b7 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -423,8 +423,53 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, }, - .B_COND = { - {{.B_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000000, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + .B_EQ = { + {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + }, + .B_NE = { + {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + }, + .B_CS = { + {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + }, + .B_CC = { + {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + }, + .B_MI = { + {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + }, + .B_PL = { + {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + }, + .B_VS = { + {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + }, + .B_VC = { + {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + }, + .B_HI = { + {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + }, + .B_LS = { + {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + }, + .B_GE = { + {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + }, + .B_LT = { + {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + }, + .B_GT = { + {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + }, + .B_LE = { + {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + }, + .B_AL = { + {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + }, + .B_NV = { + {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, }, .CBZ = { {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, @@ -3699,8 +3744,53 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .WFIT = { {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, }, - .BC_COND = { - {{.BC_COND, {.COND, .REL_19, .NONE, .NONE}, {.COND_LO, .BRANCH_19, .NONE, .NONE}, 0x54000010, 0xFF000010, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .C, .V}, side_effects={.CONTROL}}}, + .BC_EQ = { + {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + }, + .BC_NE = { + {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + }, + .BC_CS = { + {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + }, + .BC_CC = { + {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + }, + .BC_MI = { + {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + }, + .BC_PL = { + {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + }, + .BC_VS = { + {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + }, + .BC_VC = { + {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + }, + .BC_HI = { + {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + }, + .BC_LS = { + {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + }, + .BC_GE = { + {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + }, + .BC_LT = { + {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + }, + .BC_GT = { + {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + }, + .BC_LE = { + {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + }, + .BC_AL = { + {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + }, + .BC_NV = { + {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, }, .UXTB = { {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, diff --git 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z>Vx{-ARZz0d%eWwsE_LH_#e<)$ey%~Jy#IJ+nOHGV(Tb&ndpj0w@h?JqT~9C@>t(RqAMreMUt&3Wv1rNp*U>`JM*m10*)Y%9gC5?u%B zR!P1N%C|~lJ1F)TZz%jQ9(-ONHkP@-u6aQ;Mp&BISYZLNarX1~F1D6f0N<&NEF@Mb ztclnJiH(T0**@HB=Mv}xUYB|BrwFh&kU`DB3W32sMFzbkx>n0d-0Rv9KC*3NTW!7} z_*$148n4l%r#Bh>bl;Ixxa)wrp7>0)&!VF(HHZTAHY{duF delta 27 jcmZ>8n4l$=!myfMl;HsTa)xw{7>2_f!VK3qHZTAHV<`tA diff --git a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin index dae368cf2..2953b8bf1 100644 --- a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin @@ -382,7 +382,7 @@ run_pipeline_tests :: proc() { src := []a.Instruction{ a.inst_r_r_i(.SUBS, a.X0, a.X1, 0), - a.inst_b_cond(.EQ, 0), + a.inst_b_eq(0), a.inst_none(.RET), } byte_count, success := a.encode(src, ld[:], code[:], &relocs, &errors) @@ -646,7 +646,7 @@ run_pipeline_tests :: proc() { append(&insts, a.inst_r_r_i(.ADD, a.X0, a.X0, 1)) // [0] byte 0: ADD X0,X0,#1 append(&insts, a.inst_r_r_i(.SUBS, a.XZR, a.X0, 5)) // [1] byte 4: SUBS XZR,X0,#5 fwd := isa.label_forward(&labels) // reserve .L1 - append(&insts, a.inst_b_cond(.LT, fwd)) // [2] byte 8: B.LT .L1 + append(&insts, a.inst_b_lt(fwd)) // [2] byte 8: B.LT .L1 append(&insts, a.inst_branch(.B, back)) // [3] byte 12: B .L0 isa.label_set_at(&labels, fwd, &insts) // .L1: at instruction 4 append(&insts, a.inst_none(.RET)) // [4] byte 16: RET diff --git a/core/rexcode/isa/arm64/tests/smoke.odin b/core/rexcode/isa/arm64/tests/smoke.odin index 22bece4d5..5a489203c 100644 --- a/core/rexcode/isa/arm64/tests/smoke.odin +++ b/core/rexcode/isa/arm64/tests/smoke.odin @@ -97,7 +97,8 @@ main :: proc() { // ---- Branches ----------------------------------------------------------- check("B", .B, 0, 0x14000000, 0xFC000000) check("BL", .BL, 0, 0x94000000, 0xFC000000) - check("B.cond", .B_COND, 0, 0x54000000, 0xFF000010) + check("B.eq", .B_EQ, 0, 0x54000000, 0xFF00001F) + check("B.le", .B_LE, 0, 0x5400000D, 0xFF00001F) check("CBZ 64", .CBZ, 1, 0xB4000000, 0xFF000000) check("CBNZ 64", .CBNZ, 1, 0xB5000000, 0xFF000000) check("TBZ", .TBZ, 0, 0x36000000, 0x7F000000) @@ -387,7 +388,8 @@ main :: proc() { check("WFIT", .WFIT, 0, 0xD5031020, 0xFFFFFFE0) // ---- BC.cond (v8.8-A) ------------------------------------------------ - check("BC.cond", .BC_COND, 0, 0x54000010, 0xFF000010) + check("BC.eq", .BC_EQ, 0, 0x54000010, 0xFF00001F) + check("BC.le", .BC_LE, 0, 0x5400001D, 0xFF00001F) // ---- Sign/zero-extend aliases --------------------------------------- check("UXTB", .UXTB, 0, 0x53001C00, 0xFFFFFC00) From a2cd94f406bf68bd13dc13e7d7d2bf4b1f158d3a Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 08:33:23 -0400 Subject: [PATCH 24/89] rexcode/arm64: catch the tooling up to per-condition branch mnemonics Splitting B_COND left three places still describing the old model. The generated builders were already right -- inst_b_le(label), inst_bc_ne(label), one per condition, all 32 verified to encode and round-trip -- but the hand-written scaffolding around them was not. verify_against_llvm normalised our mnemonic by truncating at the first underscore, which turned B_COND into "b". LLVM prints b.eq/b.ne/..., so the tool carried 32 alias rows pairing "b" with each of them to stop the mismatch being reported. That truncation now collapses all sixteen B_* onto "b" and makes every condition compare equal to every other -- the check would pass whatever the table said. Keep the condition instead (B_LE -> "b.le") and the 32 alias rows are unnecessary; they are gone. specgen's canonicalizer kept B_COND and BC_COND off its rename path by name. Those names no longer exist, so replace the entry with a rule that matches the shape (BC?_%u%u), which is what the intent was. And the note in instructions.odin still pointed at inst_b_cond. It now says what is actually true: a conditional branch is one builder per condition because the condition is part of the mnemonic, while the select/compare family -- CSEL, CSINC, CSINV, CSNEG, CCMP, CCMN, FCSEL -- really does take a condition operand and keeps one. specgen still re-derives its 1130 forms from llvm-mc and finds every one already present, all suites pass, and all 13 packages build. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm64/instructions.odin | 12 +++++++----- core/rexcode/isa/arm64/tablegen/specgen.lua | 7 +++++-- .../isa/arm64/tools/verify_against_llvm.odin | 16 +++++++--------- 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index fc7910658..e52db3d27 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -118,8 +118,10 @@ inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> ops = {op_label(label_id, 4), {}, {}, {}}} } -// NOTE: inst_b_cond / inst_cbz (+cbnz) / inst_tbz (+tbnz) / -// inst_csel (+csinc/csinv/csneg) are now generated per-mnemonic in -// mnemonic_builders.odin (e.g. inst_cbz(rt, label), inst_cbnz(rt, label), -// inst_csinc(rd, rn, rm, cond)). They are no longer hand-written here so the -// generator can own those names for full mnemonic coverage. +// NOTE: the conditional branches, inst_cbz (+cbnz), inst_tbz (+tbnz) and +// inst_csel (+csinc/csinv/csneg) are generated per-mnemonic in +// mnemonic_builders.odin, so the generator owns those names. A conditional +// branch is one builder per condition -- inst_b_le(label), inst_bc_ne(label) +// -- because the condition is part of the mnemonic, not an operand; the +// condition-operand builders are the select/compare family, which really do +// take one (inst_csinc(rd, rn, rm, cond)). diff --git a/core/rexcode/isa/arm64/tablegen/specgen.lua b/core/rexcode/isa/arm64/tablegen/specgen.lua index 13197ba8a..8d90b11e8 100644 --- a/core/rexcode/isa/arm64/tablegen/specgen.lua +++ b/core/rexcode/isa/arm64/tablegen/specgen.lua @@ -71,10 +71,13 @@ local CANON_SUF = { "_II","_IR","_RI","_RR","_X2","_X4","_SR","_ER","_ZA", "_Z","_P","_V","_H","_S","_D","_B","_3","_4", } -local CANON_KEEP = { B_COND=true, BC_COND=true } +-- A conditional branch is one mnemonic per condition (B_LE -> `b.le`), so +-- nothing about those names should be canonicalized away. +local function is_cond_branch(name) return name:match("^BC?_%u%u$") ~= nil end +local CANON_KEEP = {} local CANON_RENAME = { LSLV="LSL", LSRV="LSR", ASRV="ASR", RORV="ROR" } local function canon(name) - if CANON_KEEP[name] then return name end + if CANON_KEEP[name] or is_cond_branch(name) then return name end for _, k in ipairs({"DC_","IC_","AT_","TLBI_","BTI_","PSB_","TSB_"}) do if name:sub(1, #k) == k then return name end end diff --git a/core/rexcode/isa/arm64/tools/verify_against_llvm.odin b/core/rexcode/isa/arm64/tools/verify_against_llvm.odin index 051166b3f..08a0088b3 100644 --- a/core/rexcode/isa/arm64/tools/verify_against_llvm.odin +++ b/core/rexcode/isa/arm64/tools/verify_against_llvm.odin @@ -37,6 +37,13 @@ normalize_our :: proc(name: string) -> string { break } } + // A conditional branch keeps its condition: B_LE is `b.le`, not `b`. + // Truncating at the underscore would collapse all sixteen onto one name + // and make every one of them compare equal to every other. + if strings.has_prefix(s, "b_") || strings.has_prefix(s, "bc_") { + return strings.concatenate({s[:strings.index_byte(s, '_')], ".", + s[strings.index_byte(s, '_')+1:]}, context.temp_allocator) + } if i := strings.index_byte(s, '_'); i >= 0 { s = s[:i] } @@ -146,15 +153,6 @@ is_known_alias :: proc(ours, llvm: string) -> bool { {"and", "mov"}, {"facge", "facge"}, {"facgt", "facgt"}, - // Conditional branches: our table has B_COND but LLVM prints b.eq/b.ne/... - {"b", "b.eq"}, {"b", "b.ne"}, {"b", "b.cs"}, {"b", "b.cc"}, - {"b", "b.mi"}, {"b", "b.pl"}, {"b", "b.vs"}, {"b", "b.vc"}, - {"b", "b.hi"}, {"b", "b.ls"}, {"b", "b.ge"}, {"b", "b.lt"}, - {"b", "b.gt"}, {"b", "b.le"}, {"b", "b.al"}, {"b", "b.nv"}, - {"bc", "bc.eq"}, {"bc", "bc.ne"}, {"bc", "bc.cs"}, {"bc", "bc.cc"}, - {"bc", "bc.mi"}, {"bc", "bc.pl"}, {"bc", "bc.vs"}, {"bc", "bc.vc"}, - {"bc", "bc.hi"}, {"bc", "bc.ls"}, {"bc", "bc.ge"}, {"bc", "bc.lt"}, - {"bc", "bc.gt"}, {"bc", "bc.le"}, {"bc", "bc.al"}, {"bc", "bc.nv"}, // FCSEL is canonical for FCSET/FCINC variants if any {"fmov", "fmov"}, // Atomics: many of these LLVM might print without the size suffix From d951ee9963d206fde69f4a48ed4473e97a4c448f Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 08:42:04 -0400 Subject: [PATCH 25/89] rexcode/arm32: VFMA/VFMS carried VMLA/VMLS encodings; drop three duplicate mnemonics Asking for a VFMA with a lane operand emitted a VMLA. NEON's fused multiply-add has no by-element form at all -- llvm-mc rejects `vfma.f32 d0, d1, d2[0]` -- and the four rows sitting under VFMA/VFMS held VMLA/VMLS's lane encodings, which VMLA and VMLS already own. Their data type gave it away too: `.I32` on a fused multiply-add, which is float-only. Deleted. They were also the reason `bits & ~mask` looked wrong on those rows: as authored they were F2A000C0, and clearing the Vn high bit -- correct, since bit 7 is the top of the register number -- landed them exactly on VMLA's F2A00040. Found by asking which (bits, mask, mode) triples more than one mnemonic claims. That check found 18; this commit takes it to 9. Three of the eighteen were whole mnemonics duplicating a base: VRECPE_F, VRSQRTE_F every form already present under VRECPE / VRSQRTE, which carry both the U32 and F32 variants. VPADD_F its F32 form duplicated VPADD's; its F16 form was the only thing it owned, so that moves to VPADD, where the data type now selects it. All three were on the list of names no assembler spells, so that count goes from 14 to 11 -- and nine of the remaining eleven are the *_LANE group, still waiting on register-list and lane-index modelling. The other two are `psb csync` and `tsb csync`, which are correct as they are. Two smoke checks asserted the VFMA/VFMS by-element forms and are gone with them; a third moved index. Verified against llvm-mc: vpadd.i8/.f32/.f16, vrecpe.u32/.f32 and vrsqrte.f32 all byte-exact, 1656/1656 decode sweep, every suite at baseline. Co-Authored-By: Claude Opus 5 (1M context) --- core/rexcode/isa/arm32/mnemonic_builders.odin | 24 +- core/rexcode/isa/arm32/mnemonics.odin | 2 +- .../isa/arm32/tablegen/encoding_table.odin | 17 +- .../tablegen/generated/decode_tables.odin | 2257 ++++++++--------- .../tablegen/generated/encode_tables.odin | 675 +++-- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10794 -> 10758 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38295 -> 38088 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4784 -> 4760 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38295 -> 38088 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3330 -> 3312 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 4 +- 15 files changed, 1460 insertions(+), 1519 deletions(-) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index ce36876c5..ff246fdd8 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -693,13 +693,9 @@ emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruc inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vfma_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } -emit_vfma_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_d_d_dlane(dst, src, src2, lane)) } inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vfms_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } -emit_vfms_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_d_d_dlane(dst, src, src2, lane)) } inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -976,12 +972,6 @@ inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) } inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) } -inst_vpadd_f_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD_F, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpadd_f_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_f_d_d_d(dst, src, src2)) } -inst_vrecpe_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrecpe_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_f_d_d(dst, src)) } -inst_vrsqrte_f_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE_F, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrsqrte_f_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_f_d_d(dst, src)) } inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) } inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -1985,10 +1975,10 @@ inst_vnmla :: inst_vnmla_s_s_s emit_vnmla :: emit_vnmla_s_s_s inst_vnmls :: inst_vnmls_s_s_s emit_vnmls :: emit_vnmls_s_s_s -inst_vfma :: proc{ inst_vfma_s_s_s, inst_vfma_d_d_dlane } -emit_vfma :: proc{ emit_vfma_s_s_s, emit_vfma_d_d_dlane } -inst_vfms :: proc{ inst_vfms_s_s_s, inst_vfms_d_d_dlane } -emit_vfms :: proc{ emit_vfms_s_s_s, emit_vfms_d_d_dlane } +inst_vfma :: inst_vfma_s_s_s +emit_vfma :: emit_vfma_s_s_s +inst_vfms :: inst_vfms_s_s_s +emit_vfms :: emit_vfms_s_s_s inst_vfnma :: inst_vfnma_s_s_s emit_vfnma :: emit_vfnma_s_s_s inst_vfnms :: inst_vfnms_s_s_s @@ -2211,12 +2201,6 @@ inst_vclz :: inst_vclz_d_d emit_vclz :: emit_vclz_d_d inst_vcnt :: inst_vcnt_d_d emit_vcnt :: emit_vcnt_d_d -inst_vpadd_f :: inst_vpadd_f_d_d_d -emit_vpadd_f :: emit_vpadd_f_d_d_d -inst_vrecpe_f :: inst_vrecpe_f_d_d -emit_vrecpe_f :: emit_vrecpe_f_d_d -inst_vrsqrte_f :: inst_vrsqrte_f_d_d -emit_vrsqrte_f :: emit_vrsqrte_f_d_d inst_vrev16 :: inst_vrev16_d_d emit_vrev16 :: emit_vrev16_d_d inst_vrev32 :: inst_vrev32_d_d diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index f7982e394..f922eeaa4 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -290,7 +290,7 @@ Mnemonic :: enum u16 { VSHLL, // shift-left long VCLS, VCLZ, VCNT, - VPADD_F, VRECPE_F, VRSQRTE_F, // (placeholders; canonical via operand types) + // (placeholders; canonical via operand types) VREV16, VREV32, VREV64, VEXT, // vector extract diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 8f6e59141..8f7a78e3a 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1376,8 +1376,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // MVE FP vector + scalar {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, - {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VFMS = { @@ -1390,8 +1388,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, - {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VFNMS = { {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, @@ -2005,6 +2001,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F32 {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPADD MVE form doesn't exist; MVE uses VADDV reduction instead) + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, // ---- VPMAX / VPMIN (D-form only) ---- .VPMAX = { @@ -3556,18 +3553,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, {.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, - .VRECPE_F = { - {.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - }, - .VRSQRTE_F = { - {.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - }, - .VPADD_F = { - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - }, .VCVTR = { {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}}, {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 0f6aec39a..959620224 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1665]lib.Decode_Entry{ +DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -370,40 +370,40 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -434,18 +434,18 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, @@ -461,18 +461,16 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -537,14 +535,13 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, @@ -571,7 +568,7 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VBSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, @@ -657,8 +654,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, @@ -676,152 +673,146 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VABS, 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{.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, 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0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, 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{.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, 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.BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -860,21 +851,21 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -882,18 +873,18 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1034,20 +1025,20 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, - { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, @@ -1056,12 +1047,12 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, @@ -1106,8 +1097,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, + { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, @@ -1126,78 +1117,78 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, - { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, - { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -1258,8 +1249,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, - { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1289,8 +1280,8 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1541,12 +1532,12 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1677,7 +1668,7 @@ DECODE_ENTRIES := [1665]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1665]u16{ +DECODE_FORM_IDX := [1656]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1690,103 +1681,102 @@ DECODE_FORM_IDX := [1665]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, + 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 21, 24, 23, 22, 25, 0, 0, - 0, 0, 10, 11, 18, 17, 15, 19, 14, 10, 13, 11, 12, 16, 20, 6, - 0, 0, 0, 5, 6, 7, 3, 9, 2, 8, 4, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 25, 24, 22, 21, 23, 0, 0, + 0, 0, 10, 11, 15, 20, 18, 17, 14, 12, 10, 11, 19, 13, 16, 0, + 6, 0, 0, 2, 6, 5, 8, 7, 9, 4, 3, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 6, 1, 0, - 2, 2, 0, 2, 0, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 7, 6, 8, 2, 2, 7, 7, 2, 1, 3, 3, 1, - 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, - 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, - 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, - 13, 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, - 3, 4, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, - 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, - 1, 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, - 12, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, - 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, - 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, - 4, 4, 4, 20, 14, 13, 9, 4, 8, 4, 4, 8, 6, 6, 3, 5, - 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 8, 7, 10, 5, 5, - 9, 5, 9, 7, 7, 0, 10, 2, 3, 1, 0, 1, 0, 2, 3, 1, - 0, 1, 0, 0, 0, 0, 3, 7, 4, 8, 5, 2, 9, 6, 6, 3, - 7, 2, 8, 9, 5, 4, 0, 1, 0, 2, 1, 1, 5, 3, 4, 2, - 0, 2, 1, 0, 12, 13, 11, 10, 13, 12, 14, 15, 14, 15, 13, 12, - 16, 15, 17, 14, 15, 16, 17, 14, 1, 5, 0, 4, 2, 3, 1, 0, - 2, 3, 3, 2, 1, 5, 3, 0, 4, 1, 2, 2, 4, 1, 0, 5, - 3, 1, 0, 0, 1, 0, 3, 1, 2, 2, 5, 0, 1, 3, 4, 1, - 5, 3, 2, 4, 0, 2, 1, 3, 0, 4, 4, 0, 3, 2, 1, 0, - 1, 0, 0, 0, 0, 1, 3, 0, 2, 2, 3, 1, 0, 2, 3, 3, - 0, 3, 0, 3, 0, 3, 1, 2, 0, 1, 2, 1, 0, 1, 0, 2, - 2, 2, 3, 0, 1, 2, 1, 0, 0, 1, 0, 1, 0, 0, 2, 0, - 2, 0, 0, 6, 4, 5, 0, 1, 2, 1, 0, 2, 0, 2, 1, 1, - 2, 0, 0, 0, 0, 6, 7, 4, 5, 0, 2, 1, 2, 1, 0, 1, - 2, 0, 1, 0, 2, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 6, 1, 2, + 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 3, 1, 1, 3, 1, 3, + 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, + 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, + 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, + 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, + 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, + 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, + 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12, 1, 0, + 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, + 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, + 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, + 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, + 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, + 0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 4, 7, + 5, 8, 2, 6, 3, 3, 7, 6, 5, 4, 2, 8, 9, 0, 1, 2, + 0, 1, 5, 3, 0, 2, 1, 4, 0, 1, 2, 13, 11, 12, 10, 14, + 13, 15, 12, 14, 15, 13, 12, 17, 15, 16, 14, 15, 16, 17, 14, 4, + 3, 1, 2, 5, 0, 3, 2, 1, 0, 2, 3, 1, 5, 2, 3, 4, + 0, 1, 1, 0, 4, 5, 2, 3, 0, 1, 1, 0, 3, 0, 2, 1, + 2, 1, 3, 4, 5, 0, 0, 3, 1, 5, 4, 2, 3, 2, 4, 1, + 0, 2, 4, 1, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 3, 2, + 3, 2, 0, 1, 2, 3, 3, 0, 3, 0, 3, 3, 2, 0, 1, 0, + 2, 1, 1, 0, 0, 1, 2, 2, 3, 0, 2, 1, 0, 1, 2, 0, + 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 5, 4, 6, 0, 2, 1, + 0, 1, 2, 2, 1, 0, 1, 0, 2, 0, 0, 0, 6, 7, 4, 5, + 1, 0, 2, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 1, 1, + 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, 3, - 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, - 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, - 9, 7, 9, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, 1, 0, 1, - 0, 0, 1, 0, 0, 1, 0, 1, 0, 0, 1, 0, 1, 4, 2, 1, - 3, 2, 0, 1, 27, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, - 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, - 2, 2, 0, 1, 1, 0, 0, 1, 3, 0, 1, 0, 1, 2, 2, 0, - 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 2, 3, 5, - 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 1, 0, - 1, 0, 1, 0, 0, 1, 1, 0, 2, 17, 18, 14, 19, 11, 12, 8, - 6, 5, 7, 9, 13, 1, 0, 2, 3, 4, 20, 1, 0, 1, 0, 3, - 0, 1, 2, 0, 1, 1, 0, 0, 1, 0, 1, 0, 4, 1, 0, 0, - 1, 15, 16, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, - 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, - 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, - 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 30, 0, - 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, - 28, 29, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, - 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, - 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, - 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, - 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, - 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, - 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, - 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, - 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, + 3, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, + 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, + 0, 0, 0, 0, 0, 1, 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, + 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, + 1, 0, 1, 0, 4, 2, 1, 3, 2, 0, 1, 27, 2, 2, 0, 1, + 0, 1, 0, 0, 0, 0, 5, 26, 0, 1, 1, 0, 0, 0, 3, 3, + 2, 2, 2, 0, 1, 0, 1, 2, 2, 0, 1, 1, 0, 0, 1, 3, + 1, 0, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, + 0, 1, 1, 0, 5, 2, 3, 3, 2, 1, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 2, 0, 1, + 19, 18, 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, + 7, 8, 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 0, 1, 1, 0, + 0, 1, 0, 1, 0, 4, 0, 1, 15, 16, 3, 2, 0, 0, 1, 0, + 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, + 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, + 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 4, 0, 0, 0, 0, 7, 29, 28, 2, 2, 2, 2, 0, 0, 0, + 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, + 8, 8, 2, 10, 10, 12, 12, 8, 4, 6, 0, 0, 2, 2, 2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 4, 3, 6, 4, 8, 9, 7, 0, 0, 7, 8, 7, 6, 7, 7, + 7, 7, 4, 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, + 1, 1, 10, 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, + 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, - 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 0, 1, - 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, - 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, - 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, - 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, - 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, - 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, - 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, + 1, 0, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, + 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, + 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 2, 2, 2, 2, 2, + 2, 0, 0, 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, + 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, + 3, 8, 8, 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, 3, 3, 3, + 2, 0, 2, 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, + 4, 4, 4, 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, + 1, 9, 11, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, + 0, 1, 2, 2, 1, 1, 1, 2, } @(rodata) -DECODE_BUCKET_LIST := [5397]u16{ +DECODE_BUCKET_LIST := [5379]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1824,307 +1814,306 @@ DECODE_BUCKET_LIST := [5397]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 363, 361, 362, 365, - 364, 366, 367, 368, 369, 370, 371, 376, 378, 379, 381, 374, 382, 377, 373, 380, - 372, 375, 383, 384, 385, 386, 392, 387, 388, 389, 394, 390, 393, 391, 395, 396, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 365, 361, 362, 363, + 364, 366, 367, 368, 369, 370, 371, 374, 380, 372, 379, 381, 378, 377, 373, 375, + 376, 382, 383, 384, 385, 386, 387, 389, 388, 394, 391, 393, 392, 390, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, - 429, 430, 432, 431, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, + 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 427, 428, + 430, 429, 431, 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 441, 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, - 457, 459, 458, 460, 461, 462, 463, 465, 464, 466, 467, 468, 469, 395, 396, 397, - 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, - 470, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, - 410, 411, 412, 413, 471, 472, 473, 470, 358, 359, 360, 365, 364, 363, 362, 361, - 366, 367, 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, - 375, 383, 384, 385, 386, 394, 393, 392, 391, 389, 390, 388, 387, 395, 396, 397, - 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, - 474, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, 429, - 430, 431, 432, 433, 434, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 475, 474, - 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 455, 454, 456, 457, - 459, 458, 460, 461, 462, 463, 465, 464, 466, 467, 468, 469, 395, 396, 397, 398, - 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 476, - 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, - 411, 412, 413, 471, 472, 477, 476, 478, 479, 480, 481, 482, 483, 485, 484, 486, - 487, 488, 489, 490, 491, 492, 493, 494, 495, 496, 497, 499, 498, 500, 501, 502, - 503, 504, 505, 506, 507, 508, 509, 510, 512, 511, 513, 514, 515, 516, 517, 518, - 519, 520, 521, 523, 522, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, - 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, - 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, - 567, 568, 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, - 583, 584, 585, 586, 587, 588, 589, 590, 592, 591, 593, 594, 595, 596, 597, 598, - 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, - 615, 616, 617, 478, 479, 480, 481, 482, 483, 484, 485, 486, 487, 488, 489, 490, - 491, 492, 493, 494, 495, 496, 497, 499, 498, 500, 501, 502, 503, 504, 505, 506, - 507, 508, 509, 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, - 523, 524, 525, 526, 527, 529, 528, 530, 531, 532, 533, 534, 535, 618, 537, 538, - 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 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1331, 1332, 1333, + 1334, 1335, 1336, 1337, 1275, 1300, 1303, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, + 1335, 1336, 1337, 1276, 1300, 1303, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, + 1336, 1337, 1340, 1341, 1342, 1340, 1341, 1342, 1340, 1341, 1342, 1340, 1341, 1342, 1340, 1341, + 1342, 1340, 1341, 1342, 1340, 1341, 1342, 1340, 1341, 1342, 1350, 1352, 1353, 1356, 1360, 1368, + 1369, 1370, 1371, 1379, 1378, 1380, 1352, 1353, 1357, 1361, 1368, 1369, 1370, 1371, 1378, 1379, + 1380, 1352, 1353, 1368, 1369, 1377, 1379, 1378, 1380, 1352, 1353, 1368, 1369, 1377, 1378, 1379, + 1380, 1351, 1358, 1359, 1366, 1365, 1376, 1379, 1378, 1380, 1365, 1366, 1376, 1379, 1378, 1380, + 1354, 1367, 1378, 1379, 1380, 1355, 1367, 1378, 1379, 1380, 1360, 1369, 1372, 1379, 1378, 1380, + 1362, 1369, 1372, 1379, 1378, 1380, 1369, 1379, 1378, 1380, 1369, 1379, 1378, 1380, 1359, 1378, + 1379, 1380, 1379, 1378, 1380, 1354, 1378, 1379, 1380, 1355, 1379, 1378, 1380, 1353, 1360, 1368, + 1369, 1379, 1378, 1380, 1353, 1364, 1368, 1369, 1378, 1379, 1380, 1353, 1368, 1369, 1379, 1378, + 1380, 1353, 1368, 1369, 1378, 1379, 1380, 1359, 1374, 1379, 1378, 1380, 1374, 1379, 1378, 1380, + 1354, 1375, 1378, 1379, 1380, 1355, 1375, 1378, 1379, 1380, 1360, 1369, 1378, 1379, 1380, 1369, + 1379, 1378, 1380, 1369, 1378, 1379, 1380, 1363, 1369, 1378, 1379, 1380, 1359, 1373, 1379, 1378, + 1380, 1373, 1378, 1379, 1380, 1354, 1378, 1379, 1380, 1355, 1378, 1379, 1380, 1360, 1369, 1378, + 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1379, 1378, 1380, 1359, 1409, + 1378, 1379, 1380, 1378, 1379, 1380, 1354, 1379, 1378, 1380, 1355, 1379, 1378, 1380, 1360, 1369, + 1379, 1378, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1359, + 1410, 1378, 1379, 1380, 1378, 1379, 1380, 1354, 1378, 1379, 1380, 1355, 1378, 1379, 1380, 1360, + 1407, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1401, 1407, 1369, 1378, 1379, 1380, 1369, + 1378, 1379, 1380, 1359, 1405, 1379, 1378, 1380, 1379, 1378, 1380, 1354, 1403, 1404, 1378, 1379, + 1380, 1355, 1378, 1379, 1380, 1400, 1360, 1408, 1369, 1379, 1378, 1380, 1369, 1378, 1379, 1380, + 1381, 1382, 1383, 1384, 1385, 1387, 1388, 1389, 1390, 1392, 1393, 1394, 1395, 1402, 1408, 1369, + 1379, 1378, 1380, 1386, 1391, 1397, 1398, 1399, 1369, 1379, 1378, 1380, 1359, 1406, 1378, 1379, + 1380, 1379, 1378, 1380, 1396, 1354, 1379, 1378, 1380, 1355, 1378, 1379, 1380, 1360, 1369, 1370, + 1371, 1379, 1378, 1380, 1361, 1369, 1370, 1371, 1378, 1379, 1380, 1369, 1377, 1378, 1379, 1380, + 1369, 1377, 1379, 1378, 1380, 1359, 1366, 1365, 1376, 1379, 1378, 1380, 1365, 1366, 1376, 1379, + 1378, 1380, 1354, 1367, 1378, 1379, 1380, 1355, 1367, 1378, 1379, 1380, 1360, 1369, 1372, 1379, + 1378, 1380, 1362, 1369, 1372, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, + 1359, 1378, 1379, 1380, 1378, 1379, 1380, 1354, 1378, 1379, 1380, 1355, 1379, 1378, 1380, 1360, + 1369, 1379, 1378, 1380, 1364, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, + 1380, 1359, 1374, 1378, 1379, 1380, 1374, 1379, 1378, 1380, 1354, 1375, 1379, 1378, 1380, 1355, + 1375, 1379, 1378, 1380, 1360, 1369, 1379, 1378, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, + 1380, 1363, 1369, 1378, 1379, 1380, 1359, 1373, 1379, 1378, 1380, 1373, 1379, 1378, 1380, 1354, + 1379, 1378, 1380, 1355, 1378, 1379, 1380, 1360, 1369, 1378, 1379, 1380, 1369, 1379, 1378, 1380, + 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1359, 1409, 1379, 1378, 1380, 1378, 1379, 1380, + 1354, 1379, 1378, 1380, 1355, 1378, 1379, 1380, 1360, 1369, 1378, 1379, 1380, 1369, 1378, 1379, + 1380, 1369, 1379, 1378, 1380, 1369, 1378, 1379, 1380, 1359, 1410, 1379, 1378, 1380, 1378, 1379, + 1380, 1354, 1379, 1378, 1380, 1355, 1379, 1378, 1380, 1360, 1369, 1379, 1378, 1380, 1369, 1378, + 1379, 1380, 1369, 1378, 1379, 1380, 1369, 1378, 1379, 1380, 1359, 1379, 1378, 1380, 1379, 1378, + 1380, 1354, 1378, 1379, 1380, 1355, 1378, 1379, 1380, 1411, 1412, 1413, 1360, 1369, 1379, 1378, + 1380, 1369, 1379, 1378, 1380, 1369, 1379, 1378, 1380, 1369, 1379, 1378, 1380, 1359, 1378, 1379, + 1380, 1379, 1378, 1380, 1354, 1378, 1379, 1380, 1355, 1414, 1379, 1378, 1380, 1418, 1417, 1420, + 1419, 1424, 1416, 1415, 1426, 1430, 1423, 1429, 1432, 1431, 1428, 1426, 1427, 1421, 1422, 1425, + 1433, 1434, 1437, 1490, 1496, 1440, 1490, 1499, 1436, 1491, 1495, 1439, 1491, 1498, 1435, 1492, + 1494, 1438, 1492, 1497, 1493, 1493, 1446, 1447, 1448, 1449, 1450, 1456, 1462, 1468, 1474, 1480, + 1442, 1443, 1444, 1445, 1451, 1457, 1463, 1469, 1475, 1481, 1452, 1458, 1464, 1470, 1476, 1482, + 1441, 1454, 1460, 1466, 1472, 1478, 1484, 1455, 1461, 1467, 1473, 1479, 1485, 1453, 1459, 1465, + 1471, 1477, 1483, 1486, 1500, 1501, 1489, 1504, 1487, 1502, 1488, 1505, 1503, 1527, 1528, 1518, + 1523, 1525, 1518, 1524, 1526, 1527, 1528, 1523, 1525, 1524, 1526, 1512, 1513, 1514, 1515, 1516, + 1517, 1527, 1506, 1507, 1508, 1509, 1510, 1511, 1519, 1520, 1521, 1522, 1528, 1518, 1523, 1525, + 1518, 1524, 1526, 1512, 1513, 1514, 1515, 1516, 1517, 1527, 1506, 1507, 1508, 1509, 1510, 1511, + 1528, 1523, 1525, 1524, 1526, 1518, 1518, 1519, 1520, 1521, 1522, 1518, 1518, 1545, 1268, 1269, + 1284, 1285, 1286, 1551, 1297, 1298, 1556, 1557, 1558, 1559, 1301, 1561, 1304, 1305, 1308, 1309, + 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1574, 1268, 1269, 1284, 1285, 1286, 1551, 1298, + 1556, 1557, 1558, 1559, 1301, 1561, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, + 1324, 1325, 1574, 1268, 1269, 1284, 1285, 1286, 1551, 1298, 1556, 1557, 1558, 1559, 1301, 1561, + 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1574, 1530, 1539, 1540, + 1268, 1269, 1270, 1284, 1285, 1286, 1287, 1551, 1296, 1298, 1556, 1557, 1558, 1559, 1301, 1561, + 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1574, 1545, 1268, 1269, + 1284, 1285, 1286, 1551, 1297, 1298, 1556, 1557, 1558, 1559, 1301, 1561, 1304, 1305, 1308, 1309, + 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1570, 1574, 1268, 1269, 1284, 1285, 1286, 1551, + 1298, 1556, 1557, 1558, 1559, 1301, 1561, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, + 1323, 1324, 1325, 1570, 1574, 1268, 1269, 1284, 1285, 1286, 1551, 1298, 1556, 1557, 1558, 1559, + 1301, 1561, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1570, 1574, + 1529, 1539, 1540, 1268, 1269, 1270, 1284, 1285, 1286, 1287, 1551, 1296, 1298, 1556, 1557, 1558, + 1559, 1301, 1561, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1570, + 1574, 1246, 1247, 1279, 1280, 1281, 1282, 1290, 1291, 1292, 1293, 1552, 1553, 1554, 1555, 1561, + 1306, 1307, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1566, 1567, 1568, 1569, 1343, 1572, + 1575, 1552, 1553, 1554, 1555, 1561, 1306, 1307, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, + 1572, 1575, 1552, 1553, 1554, 1555, 1561, 1306, 1307, 1314, 1315, 1316, 1317, 1318, 1319, 1320, + 1321, 1572, 1575, 1537, 1538, 1277, 1278, 1288, 1289, 1294, 1295, 1552, 1553, 1554, 1555, 1561, + 1306, 1307, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1562, 1563, 1564, 1565, 1572, 1575, + 1279, 1280, 1281, 1282, 1290, 1291, 1292, 1293, 1552, 1553, 1554, 1555, 1561, 1306, 1307, 1314, + 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1566, 1567, 1568, 1569, 1343, 1571, 1573, 1575, 1552, + 1553, 1554, 1555, 1561, 1306, 1307, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1571, 1573, + 1575, 1248, 1249, 1250, 1251, 1260, 1261, 1262, 1263, 1552, 1553, 1554, 1555, 1561, 1306, 1307, + 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1571, 1573, 1575, 1537, 1538, 1258, 1259, 1277, + 1278, 1288, 1289, 1294, 1295, 1552, 1553, 1554, 1555, 1561, 1306, 1307, 1314, 1315, 1316, 1317, + 1318, 1319, 1320, 1321, 1562, 1563, 1564, 1565, 1571, 1573, 1575, 1549, 1550, 1551, 1299, 1560, + 1302, 1561, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1550, 1551, + 1299, 1560, 1302, 1561, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, + 1551, 1560, 1300, 1303, 1561, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, + 1337, 1551, 1560, 1300, 1303, 1561, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, + 1336, 1337, 1549, 1550, 1551, 1299, 1560, 1302, 1561, 1326, 1327, 1328, 1329, 1330, 1331, 1332, + 1333, 1334, 1335, 1336, 1337, 1550, 1551, 1299, 1560, 1302, 1561, 1326, 1327, 1328, 1329, 1330, + 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1551, 1300, 1560, 1303, 1561, 1326, 1327, 1328, 1329, + 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1551, 1560, 1300, 1303, 1561, 1326, 1327, 1328, + 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1561, 1340, 1341, 1342, 1561, 1340, 1341, + 1342, 1561, 1340, 1341, 1342, 1531, 1532, 1533, 1534, 1535, 1536, 1541, 1542, 1543, 1544, 1546, + 1547, 1548, 1561, 1340, 1341, 1342, 1561, 1340, 1341, 1342, 1561, 1340, 1341, 1342, 1561, 1340, + 1341, 1342, 1531, 1532, 1533, 1534, 1535, 1536, 1541, 1542, 1543, 1544, 1546, 1547, 1548, 1561, + 1340, 1341, 1342, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2170,606 +2159,606 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x27 = { 582, 19}, 0x28 = { 601, 57}, 0x29 = { 658, 47}, - 0x2A = { 705, 48}, - 0x2B = { 753, 23}, - 0x2C = { 776, 57}, - 0x2D = { 833, 47}, - 0x2E = { 880, 48}, - 0x2F = { 928, 23}, - 0x30 = { 951, 59}, - 0x31 = { 1010, 27}, - 0x32 = { 1037, 45}, - 0x33 = { 1082, 9}, - 0x34 = { 1091, 59}, - 0x35 = { 1150, 27}, - 0x36 = { 1177, 33}, - 0x37 = { 1210, 9}, - 0x38 = { 1219, 58}, - 0x39 = { 1277, 43}, - 0x3A = { 1320, 44}, - 0x3B = { 1364, 160}, - 0x3C = { 1524, 58}, - 0x3D = { 1582, 43}, - 0x3E = { 1625, 44}, - 0x3F = { 1669, 160}, - 0x40 = { 1829, 12}, - 0x41 = { 1841, 1}, - 0x42 = { 1842, 12}, - 0x43 = { 1854, 1}, - 0x44 = { 1855, 1}, - 0x45 = { 1856, 2}, - 0x46 = { 1858, 1}, - 0x47 = { 1859, 1}, - 0x48 = { 1860, 16}, - 0x49 = { 1876, 1}, - 0x4A = { 1877, 20}, - 0x4B = { 1897, 1}, - 0x4C = { 1898, 16}, - 0x4D = { 1914, 2}, - 0x4E = { 1916, 20}, - 0x4F = { 1936, 1}, - 0x50 = { 1937, 1}, - 0x51 = { 1938, 1}, - 0x52 = { 1939, 1}, - 0x53 = { 1940, 1}, - 0x54 = { 1941, 1}, - 0x55 = { 1942, 1}, - 0x56 = { 1943, 1}, - 0x57 = { 1944, 6}, - 0x58 = { 1950, 1}, - 0x59 = { 1951, 1}, - 0x5A = { 1952, 1}, - 0x5B = { 1953, 1}, - 0x5C = { 1954, 1}, - 0x5D = { 1955, 3}, - 0x5E = { 1958, 1}, - 0x5F = { 1959, 1}, - 0x61 = { 1960, 6}, - 0x62 = { 1966, 6}, - 0x63 = { 1972, 6}, - 0x65 = { 1978, 6}, - 0x66 = { 1984, 6}, - 0x67 = { 1990, 6}, - 0x68 = { 1996, 5}, - 0x6A = { 2001, 4}, - 0x6B = { 2005, 5}, - 0x6C = { 2010, 2}, - 0x6E = { 2012, 4}, - 0x6F = { 2016, 5}, - 0x70 = { 2021, 9}, - 0x71 = { 2030, 2}, - 0x73 = { 2032, 1}, - 0x74 = { 2033, 5}, - 0x75 = { 2038, 7}, - 0x78 = { 2045, 3}, - 0x79 = { 2048, 1}, - 0x7A = { 2049, 1}, - 0x7B = { 2050, 1}, - 0x7C = { 2051, 3}, - 0x7D = { 2054, 3}, - 0x7E = { 2057, 1}, - 0x7F = { 2058, 2}, - 0x80 = { 2060, 1}, - 0x81 = { 2061, 2}, - 0x82 = { 2063, 1}, - 0x83 = { 2064, 2}, - 0x84 = { 2066, 1}, - 0x85 = { 2067, 1}, - 0x86 = { 2068, 1}, - 0x87 = { 2069, 1}, - 0x88 = { 2070, 2}, - 0x89 = { 2072, 3}, - 0x8A = { 2075, 2}, - 0x8B = { 2077, 4}, - 0x8C = { 2081, 1}, - 0x8D = { 2082, 1}, - 0x8E = { 2083, 1}, - 0x8F = { 2084, 1}, - 0x90 = { 2085, 1}, - 0x91 = { 2086, 2}, - 0x92 = { 2088, 2}, - 0x93 = { 2090, 2}, - 0x94 = { 2092, 1}, - 0x95 = { 2093, 1}, - 0x96 = { 2094, 1}, - 0x97 = { 2095, 1}, - 0x98 = { 2096, 1}, - 0x99 = { 2097, 2}, - 0x9A = { 2099, 1}, - 0x9B = { 2100, 2}, - 0x9C = { 2102, 1}, - 0x9D = { 2103, 1}, - 0x9E = { 2104, 1}, - 0x9F = { 2105, 1}, - 0xA0 = { 2106, 2}, - 0xA1 = { 2108, 2}, - 0xA2 = { 2110, 2}, - 0xA3 = { 2112, 2}, - 0xA4 = { 2114, 2}, - 0xA5 = { 2116, 2}, - 0xA6 = { 2118, 2}, - 0xA7 = { 2120, 2}, - 0xA8 = { 2122, 2}, - 0xA9 = { 2124, 2}, - 0xAA = { 2126, 2}, - 0xAB = { 2128, 2}, - 0xAC = { 2130, 2}, - 0xAD = { 2132, 2}, - 0xAE = { 2134, 2}, - 0xAF = { 2136, 2}, - 0xB0 = { 2138, 2}, - 0xB1 = { 2140, 2}, - 0xB2 = { 2142, 2}, - 0xB3 = { 2144, 2}, - 0xB4 = { 2146, 2}, - 0xB5 = { 2148, 2}, - 0xB6 = { 2150, 2}, - 0xB7 = { 2152, 2}, - 0xB8 = { 2154, 2}, - 0xB9 = { 2156, 2}, - 0xBA = { 2158, 2}, - 0xBB = { 2160, 2}, - 0xBC = { 2162, 2}, - 0xBD = { 2164, 2}, - 0xBE = { 2166, 2}, - 0xBF = { 2168, 2}, - 0xC0 = { 2170, 7}, - 0xC1 = { 2177, 4}, - 0xC2 = { 2181, 12}, - 0xC3 = { 2193, 5}, - 0xC4 = { 2198, 11}, - 0xC5 = { 2209, 8}, - 0xC6 = { 2217, 12}, - 0xC7 = { 2229, 5}, - 0xC8 = { 2234, 6}, - 0xC9 = { 2240, 6}, - 0xCA = { 2246, 12}, - 0xCB = { 2258, 8}, - 0xCC = { 2266, 6}, - 0xCD = { 2272, 6}, - 0xCE = { 2278, 12}, - 0xCF = { 2290, 6}, - 0xD0 = { 2296, 4}, - 0xD1 = { 2300, 4}, - 0xD2 = { 2304, 4}, - 0xD3 = { 2308, 2}, - 0xD4 = { 2310, 4}, - 0xD5 = { 2314, 4}, - 0xD6 = { 2318, 2}, - 0xD7 = { 2320, 2}, - 0xD8 = { 2322, 4}, - 0xD9 = { 2326, 4}, - 0xDA = { 2330, 2}, - 0xDB = { 2332, 2}, - 0xDC = { 2334, 4}, - 0xDD = { 2338, 4}, - 0xDE = { 2342, 2}, - 0xDF = { 2344, 2}, - 0xE0 = { 2346, 20}, - 0xE1 = { 2366, 14}, - 0xE2 = { 2380, 20}, - 0xE3 = { 2400, 15}, - 0xE4 = { 2415, 18}, - 0xE5 = { 2433, 13}, - 0xE6 = { 2446, 19}, - 0xE7 = { 2465, 15}, - 0xE8 = { 2480, 15}, - 0xE9 = { 2495, 11}, - 0xEA = { 2506, 11}, - 0xEB = { 2517, 77}, - 0xEC = { 2594, 16}, - 0xED = { 2610, 11}, - 0xEE = { 2621, 13}, - 0xEF = { 2634, 78}, - 0xF0 = { 2712, 3}, - 0xF1 = { 2715, 3}, - 0xF2 = { 2718, 3}, - 0xF3 = { 2721, 3}, - 0xF4 = { 2724, 3}, - 0xF5 = { 2727, 3}, - 0xF6 = { 2730, 3}, - 0xF7 = { 2733, 3}, - 0xF8 = { 2736, 1}, - 0xF9 = { 2737, 1}, - 0xFA = { 2738, 1}, - 0xFB = { 2739, 1}, - 0xFC = { 2740, 1}, - 0xFD = { 2741, 1}, - 0xFE = { 2742, 1}, - 0xFF = { 2743, 1}, + 0x2A = { 705, 46}, + 0x2B = { 751, 23}, + 0x2C = { 774, 57}, + 0x2D = { 831, 47}, + 0x2E = { 878, 46}, + 0x2F = { 924, 23}, + 0x30 = { 947, 58}, + 0x31 = { 1005, 27}, + 0x32 = { 1032, 45}, + 0x33 = { 1077, 9}, + 0x34 = { 1086, 58}, + 0x35 = { 1144, 27}, + 0x36 = { 1171, 33}, + 0x37 = { 1204, 9}, + 0x38 = { 1213, 58}, + 0x39 = { 1271, 43}, + 0x3A = { 1314, 42}, + 0x3B = { 1356, 156}, + 0x3C = { 1512, 58}, + 0x3D = { 1570, 43}, + 0x3E = { 1613, 42}, + 0x3F = { 1655, 156}, + 0x40 = { 1811, 12}, + 0x41 = { 1823, 1}, + 0x42 = { 1824, 12}, + 0x43 = { 1836, 1}, + 0x44 = { 1837, 1}, + 0x45 = { 1838, 2}, + 0x46 = { 1840, 1}, + 0x47 = { 1841, 1}, + 0x48 = { 1842, 16}, + 0x49 = { 1858, 1}, + 0x4A = { 1859, 20}, + 0x4B = { 1879, 1}, + 0x4C = { 1880, 16}, + 0x4D = { 1896, 2}, + 0x4E = { 1898, 20}, + 0x4F = { 1918, 1}, + 0x50 = { 1919, 1}, + 0x51 = { 1920, 1}, + 0x52 = { 1921, 1}, + 0x53 = { 1922, 1}, + 0x54 = { 1923, 1}, + 0x55 = { 1924, 1}, + 0x56 = { 1925, 1}, + 0x57 = { 1926, 6}, + 0x58 = { 1932, 1}, + 0x59 = { 1933, 1}, + 0x5A = { 1934, 1}, + 0x5B = { 1935, 1}, + 0x5C = { 1936, 1}, + 0x5D = { 1937, 3}, + 0x5E = { 1940, 1}, + 0x5F = { 1941, 1}, + 0x61 = { 1942, 6}, + 0x62 = { 1948, 6}, + 0x63 = { 1954, 6}, + 0x65 = { 1960, 6}, + 0x66 = { 1966, 6}, + 0x67 = { 1972, 6}, + 0x68 = { 1978, 5}, + 0x6A = { 1983, 4}, + 0x6B = { 1987, 5}, + 0x6C = { 1992, 2}, + 0x6E = { 1994, 4}, + 0x6F = { 1998, 5}, + 0x70 = { 2003, 9}, + 0x71 = { 2012, 2}, + 0x73 = { 2014, 1}, + 0x74 = { 2015, 5}, + 0x75 = { 2020, 7}, + 0x78 = { 2027, 3}, + 0x79 = { 2030, 1}, + 0x7A = { 2031, 1}, + 0x7B = { 2032, 1}, + 0x7C = { 2033, 3}, + 0x7D = { 2036, 3}, + 0x7E = { 2039, 1}, + 0x7F = { 2040, 2}, + 0x80 = { 2042, 1}, + 0x81 = { 2043, 2}, + 0x82 = { 2045, 1}, + 0x83 = { 2046, 2}, + 0x84 = { 2048, 1}, + 0x85 = { 2049, 1}, + 0x86 = { 2050, 1}, + 0x87 = { 2051, 1}, + 0x88 = { 2052, 2}, + 0x89 = { 2054, 3}, + 0x8A = { 2057, 2}, + 0x8B = { 2059, 4}, + 0x8C = { 2063, 1}, + 0x8D = { 2064, 1}, + 0x8E = { 2065, 1}, + 0x8F = { 2066, 1}, + 0x90 = { 2067, 1}, + 0x91 = { 2068, 2}, + 0x92 = { 2070, 2}, + 0x93 = { 2072, 2}, + 0x94 = { 2074, 1}, + 0x95 = { 2075, 1}, + 0x96 = { 2076, 1}, + 0x97 = { 2077, 1}, + 0x98 = { 2078, 1}, + 0x99 = { 2079, 2}, + 0x9A = { 2081, 1}, + 0x9B = { 2082, 2}, + 0x9C = { 2084, 1}, + 0x9D = { 2085, 1}, + 0x9E = { 2086, 1}, + 0x9F = { 2087, 1}, + 0xA0 = { 2088, 2}, + 0xA1 = { 2090, 2}, + 0xA2 = { 2092, 2}, + 0xA3 = { 2094, 2}, + 0xA4 = { 2096, 2}, + 0xA5 = { 2098, 2}, + 0xA6 = { 2100, 2}, + 0xA7 = { 2102, 2}, + 0xA8 = { 2104, 2}, + 0xA9 = { 2106, 2}, + 0xAA = { 2108, 2}, + 0xAB = { 2110, 2}, + 0xAC = { 2112, 2}, + 0xAD = { 2114, 2}, + 0xAE = { 2116, 2}, + 0xAF = { 2118, 2}, + 0xB0 = { 2120, 2}, + 0xB1 = { 2122, 2}, + 0xB2 = { 2124, 2}, + 0xB3 = { 2126, 2}, + 0xB4 = { 2128, 2}, + 0xB5 = { 2130, 2}, + 0xB6 = { 2132, 2}, + 0xB7 = { 2134, 2}, + 0xB8 = { 2136, 2}, + 0xB9 = { 2138, 2}, + 0xBA = { 2140, 2}, + 0xBB = { 2142, 2}, + 0xBC = { 2144, 2}, + 0xBD = { 2146, 2}, + 0xBE = { 2148, 2}, + 0xBF = { 2150, 2}, + 0xC0 = { 2152, 7}, + 0xC1 = { 2159, 4}, + 0xC2 = { 2163, 12}, + 0xC3 = { 2175, 5}, + 0xC4 = { 2180, 11}, + 0xC5 = { 2191, 8}, + 0xC6 = { 2199, 12}, + 0xC7 = { 2211, 5}, + 0xC8 = { 2216, 6}, + 0xC9 = { 2222, 6}, + 0xCA = { 2228, 12}, + 0xCB = { 2240, 8}, + 0xCC = { 2248, 6}, + 0xCD = { 2254, 6}, + 0xCE = { 2260, 12}, + 0xCF = { 2272, 6}, + 0xD0 = { 2278, 4}, + 0xD1 = { 2282, 4}, + 0xD2 = { 2286, 4}, + 0xD3 = { 2290, 2}, + 0xD4 = { 2292, 4}, + 0xD5 = { 2296, 4}, + 0xD6 = { 2300, 2}, + 0xD7 = { 2302, 2}, + 0xD8 = { 2304, 4}, + 0xD9 = { 2308, 4}, + 0xDA = { 2312, 2}, + 0xDB = { 2314, 2}, + 0xDC = { 2316, 4}, + 0xDD = { 2320, 4}, + 0xDE = { 2324, 2}, + 0xDF = { 2326, 2}, + 0xE0 = { 2328, 20}, + 0xE1 = { 2348, 14}, + 0xE2 = { 2362, 20}, + 0xE3 = { 2382, 15}, + 0xE4 = { 2397, 18}, + 0xE5 = { 2415, 13}, + 0xE6 = { 2428, 19}, + 0xE7 = { 2447, 15}, + 0xE8 = { 2462, 15}, + 0xE9 = { 2477, 11}, + 0xEA = { 2488, 11}, + 0xEB = { 2499, 77}, + 0xEC = { 2576, 16}, + 0xED = { 2592, 11}, + 0xEE = { 2603, 13}, + 0xEF = { 2616, 78}, + 0xF0 = { 2694, 3}, + 0xF1 = { 2697, 3}, + 0xF2 = { 2700, 3}, + 0xF3 = { 2703, 3}, + 0xF4 = { 2706, 3}, + 0xF5 = { 2709, 3}, + 0xF6 = { 2712, 3}, + 0xF7 = { 2715, 3}, + 0xF8 = { 2718, 1}, + 0xF9 = { 2719, 1}, + 0xFA = { 2720, 1}, + 0xFB = { 2721, 1}, + 0xFC = { 2722, 1}, + 0xFD = { 2723, 1}, + 0xFE = { 2724, 1}, + 0xFF = { 2725, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2744, 23}, - 0x75 = { 2767, 19}, - 0x76 = { 2786, 19}, - 0x77 = { 2805, 104}, - 0x78 = { 2909, 31}, - 0x79 = { 2940, 38}, - 0x7A = { 2978, 23}, - 0x7B = { 3001, 14}, - 0x7C = { 3015, 20}, - 0x7D = { 3035, 71}, - 0x7E = { 3106, 23}, - 0x7F = { 3129, 126}, + 0x74 = { 2726, 23}, + 0x75 = { 2749, 19}, + 0x76 = { 2768, 19}, + 0x77 = { 2787, 104}, + 0x78 = { 2891, 31}, + 0x79 = { 2922, 38}, + 0x7A = { 2960, 23}, + 0x7B = { 2983, 14}, + 0x7C = { 2997, 20}, + 0x7D = { 3017, 71}, + 0x7E = { 3088, 23}, + 0x7F = { 3111, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3255, 1}, - 0x01 = { 3256, 1}, - 0x02 = { 3257, 1}, - 0x03 = { 3258, 1}, - 0x04 = { 3259, 1}, - 0x05 = { 3260, 1}, - 0x06 = { 3261, 2}, - 0x07 = { 3263, 2}, - 0x08 = { 3265, 1}, - 0x09 = { 3266, 1}, - 0x0A = { 3267, 1}, - 0x0B = { 3268, 1}, - 0x0C = { 3269, 1}, - 0x0D = { 3270, 1}, - 0x0E = { 3271, 1}, - 0x0F = { 3272, 1}, - 0x10 = { 3273, 16}, - 0x11 = { 3289, 7}, - 0x12 = { 3296, 1}, - 0x13 = { 3297, 1}, - 0x14 = { 3298, 2}, - 0x15 = { 3300, 2}, - 0x16 = { 3302, 2}, - 0x17 = { 3304, 2}, - 0x18 = { 3306, 1}, - 0x19 = { 3307, 1}, - 0x1A = { 3308, 1}, - 0x1B = { 3309, 1}, - 0x1C = { 3310, 1}, - 0x1D = { 3311, 1}, - 0x1E = { 3312, 1}, - 0x1F = { 3313, 1}, - 0x20 = { 3314, 1}, - 0x21 = { 3315, 1}, - 0x22 = { 3316, 1}, - 0x23 = { 3317, 1}, - 0x24 = { 3318, 1}, - 0x25 = { 3319, 1}, - 0x26 = { 3320, 1}, - 0x27 = { 3321, 1}, - 0x28 = { 3322, 1}, - 0x29 = { 3323, 1}, - 0x2A = { 3324, 1}, - 0x2B = { 3325, 1}, - 0x2C = { 3326, 7}, - 0x2D = { 3333, 2}, - 0x2E = { 3335, 4}, - 0x2F = { 3339, 8}, - 0x30 = { 3347, 1}, - 0x31 = { 3348, 1}, - 0x32 = { 3349, 1}, - 0x33 = { 3350, 1}, - 0x34 = { 3351, 1}, - 0x35 = { 3352, 1}, - 0x36 = { 3353, 1}, - 0x37 = { 3354, 3}, - 0x38 = { 3357, 1}, - 0x39 = { 3358, 1}, + 0x00 = { 3237, 1}, + 0x01 = { 3238, 1}, + 0x02 = { 3239, 1}, + 0x03 = { 3240, 1}, + 0x04 = { 3241, 1}, + 0x05 = { 3242, 1}, + 0x06 = { 3243, 2}, + 0x07 = { 3245, 2}, + 0x08 = { 3247, 1}, + 0x09 = { 3248, 1}, + 0x0A = { 3249, 1}, + 0x0B = { 3250, 1}, + 0x0C = { 3251, 1}, + 0x0D = { 3252, 1}, + 0x0E = { 3253, 1}, + 0x0F = { 3254, 1}, + 0x10 = { 3255, 16}, + 0x11 = { 3271, 7}, + 0x12 = { 3278, 1}, + 0x13 = { 3279, 1}, + 0x14 = { 3280, 2}, + 0x15 = { 3282, 2}, + 0x16 = { 3284, 2}, + 0x17 = { 3286, 2}, + 0x18 = { 3288, 1}, + 0x19 = { 3289, 1}, + 0x1A = { 3290, 1}, + 0x1B = { 3291, 1}, + 0x1C = { 3292, 1}, + 0x1D = { 3293, 1}, + 0x1E = { 3294, 1}, + 0x1F = { 3295, 1}, + 0x20 = { 3296, 1}, + 0x21 = { 3297, 1}, + 0x22 = { 3298, 1}, + 0x23 = { 3299, 1}, + 0x24 = { 3300, 1}, + 0x25 = { 3301, 1}, + 0x26 = { 3302, 1}, + 0x27 = { 3303, 1}, + 0x28 = { 3304, 1}, + 0x29 = { 3305, 1}, + 0x2A = { 3306, 1}, + 0x2B = { 3307, 1}, + 0x2C = { 3308, 7}, + 0x2D = { 3315, 2}, + 0x2E = { 3317, 4}, + 0x2F = { 3321, 8}, + 0x30 = { 3329, 1}, + 0x31 = { 3330, 1}, + 0x32 = { 3331, 1}, + 0x33 = { 3332, 1}, + 0x34 = { 3333, 1}, + 0x35 = { 3334, 1}, + 0x36 = { 3335, 1}, + 0x37 = { 3336, 3}, + 0x38 = { 3339, 1}, + 0x39 = { 3340, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3359, 6}, - 0xE85 = { 3365, 2}, - 0xE86 = { 3367, 1}, - 0xE87 = { 3368, 1}, - 0xE88 = { 3369, 1}, - 0xE89 = { 3370, 1}, - 0xE8A = { 3371, 1}, - 0xE8B = { 3372, 2}, - 0xE8C = { 3374, 4}, - 0xE8D = { 3378, 6}, - 0xE8E = { 3384, 1}, - 0xE8F = { 3385, 1}, - 0xE90 = { 3386, 1}, - 0xE91 = { 3387, 1}, - 0xE92 = { 3388, 2}, - 0xE93 = { 3390, 1}, - 0xE94 = { 3391, 1}, - 0xE95 = { 3392, 1}, - 0xE96 = { 3393, 1}, - 0xE97 = { 3394, 2}, - 0xE9C = { 3396, 1}, - 0xE9D = { 3397, 1}, - 0xE9E = { 3398, 1}, - 0xE9F = { 3399, 1}, - 0xEA0 = { 3400, 2}, - 0xEA1 = { 3402, 3}, - 0xEA2 = { 3405, 1}, - 0xEA3 = { 3406, 1}, - 0xEA4 = { 3407, 7}, - 0xEA5 = { 3414, 7}, - 0xEA6 = { 3421, 1}, - 0xEA7 = { 3422, 1}, - 0xEA8 = { 3423, 1}, - 0xEA9 = { 3424, 2}, - 0xEB1 = { 3426, 1}, - 0xEB4 = { 3427, 1}, - 0xEB5 = { 3428, 1}, - 0xEB6 = { 3429, 1}, - 0xEB7 = { 3430, 1}, - 0xEBB = { 3431, 1}, - 0xEBC = { 3432, 1}, - 0xEBD = { 3433, 1}, - 0xEC0 = { 3434, 2}, - 0xEC1 = { 3436, 1}, - 0xEC2 = { 3437, 3}, - 0xEC3 = { 3440, 2}, - 0xEC4 = { 3442, 2}, - 0xEC5 = { 3444, 1}, - 0xEC6 = { 3445, 7}, - 0xEC7 = { 3452, 2}, - 0xEC8 = { 3454, 1}, - 0xEC9 = { 3455, 1}, - 0xECA = { 3456, 2}, - 0xECB = { 3458, 2}, - 0xECC = { 3460, 1}, - 0xECD = { 3461, 1}, - 0xECE = { 3462, 2}, - 0xECF = { 3464, 2}, - 0xED6 = { 3466, 4}, - 0xED8 = { 3470, 4}, - 0xED9 = { 3474, 4}, - 0xEDC = { 3478, 4}, - 0xEDD = { 3482, 4}, - 0xEE0 = { 3486, 24}, - 0xEE1 = { 3510, 23}, - 0xEE2 = { 3533, 22}, - 0xEE3 = { 3555, 29}, - 0xEE4 = { 3584, 23}, - 0xEE5 = { 3607, 22}, - 0xEE6 = { 3629, 22}, - 0xEE7 = { 3651, 29}, - 0xEE8 = { 3680, 28}, - 0xEE9 = { 3708, 12}, - 0xEEA = { 3720, 13}, - 0xEEB = { 3733, 18}, - 0xEEC = { 3751, 27}, - 0xEED = { 3778, 13}, - 0xEEE = { 3791, 22}, - 0xEEF = { 3813, 23}, - 0xEF0 = { 3836, 15}, - 0xEF1 = { 3851, 15}, - 0xEF2 = { 3866, 15}, - 0xEF3 = { 3881, 15}, - 0xEF4 = { 3896, 15}, - 0xEF5 = { 3911, 15}, - 0xEF6 = { 3926, 15}, - 0xEF7 = { 3941, 15}, - 0xEF8 = { 3956, 3}, - 0xEF9 = { 3959, 3}, - 0xEFA = { 3962, 3}, - 0xEFB = { 3965, 3}, - 0xEFC = { 3968, 3}, - 0xEFD = { 3971, 3}, - 0xEFE = { 3974, 3}, - 0xEFF = { 3977, 3}, - 0xF00 = { 3980, 12}, - 0xF01 = { 3992, 11}, - 0xF02 = { 4003, 8}, - 0xF03 = { 4011, 8}, - 0xF04 = { 4019, 9}, - 0xF05 = { 4028, 6}, - 0xF06 = { 4034, 5}, - 0xF07 = { 4039, 5}, - 0xF08 = { 4044, 6}, - 0xF09 = { 4050, 6}, - 0xF0A = { 4056, 4}, - 0xF0B = { 4060, 4}, - 0xF0C = { 4064, 4}, - 0xF0D = { 4068, 3}, - 0xF0E = { 4071, 4}, - 0xF0F = { 4075, 4}, - 0xF10 = { 4079, 7}, - 0xF11 = { 4086, 7}, - 0xF12 = { 4093, 6}, - 0xF13 = { 4099, 6}, - 0xF14 = { 4105, 5}, - 0xF15 = { 4110, 4}, - 0xF16 = { 4114, 5}, - 0xF17 = { 4119, 5}, - 0xF18 = { 4124, 5}, - 0xF19 = { 4129, 4}, - 0xF1A = { 4133, 4}, - 0xF1B = { 4137, 5}, - 0xF1C = { 4142, 5}, - 0xF1D = { 4147, 4}, - 0xF1E = { 4151, 4}, - 0xF1F = { 4155, 4}, - 0xF20 = { 4159, 5}, - 0xF21 = { 4164, 4}, - 0xF22 = { 4168, 4}, - 0xF23 = { 4172, 4}, - 0xF24 = { 4176, 5}, - 0xF25 = { 4181, 3}, - 0xF26 = { 4184, 4}, - 0xF27 = { 4188, 4}, - 0xF28 = { 4192, 5}, - 0xF29 = { 4197, 4}, - 0xF2A = { 4201, 4}, - 0xF2B = { 4205, 4}, - 0xF2C = { 4209, 5}, - 0xF2D = { 4214, 3}, - 0xF2E = { 4217, 4}, - 0xF2F = { 4221, 4}, - 0xF30 = { 4225, 6}, - 0xF31 = { 4231, 4}, - 0xF32 = { 4235, 6}, - 0xF33 = { 4241, 4}, - 0xF34 = { 4245, 5}, - 0xF35 = { 4250, 3}, - 0xF36 = { 4253, 6}, - 0xF37 = { 4259, 4}, - 0xF38 = { 4263, 7}, - 0xF39 = { 4270, 4}, - 0xF3A = { 4274, 19}, - 0xF3B = { 4293, 9}, - 0xF3C = { 4302, 5}, - 0xF3D = { 4307, 3}, - 0xF3E = { 4310, 5}, - 0xF3F = { 4315, 4}, - 0xF40 = { 4319, 7}, - 0xF41 = { 4326, 7}, - 0xF42 = { 4333, 5}, - 0xF43 = { 4338, 5}, - 0xF44 = { 4343, 7}, - 0xF45 = { 4350, 6}, - 0xF46 = { 4356, 5}, - 0xF47 = { 4361, 5}, - 0xF48 = { 4366, 6}, - 0xF49 = { 4372, 6}, - 0xF4A = { 4378, 4}, - 0xF4B = { 4382, 4}, - 0xF4C = { 4386, 4}, - 0xF4D = { 4390, 3}, - 0xF4E = { 4393, 4}, - 0xF4F = { 4397, 4}, - 0xF50 = { 4401, 5}, - 0xF51 = { 4406, 5}, - 0xF52 = { 4411, 4}, - 0xF53 = { 4415, 4}, - 0xF54 = { 4419, 5}, - 0xF55 = { 4424, 4}, - 0xF56 = { 4428, 5}, - 0xF57 = { 4433, 5}, - 0xF58 = { 4438, 5}, - 0xF59 = { 4443, 4}, - 0xF5A = { 4447, 4}, - 0xF5B = { 4451, 5}, - 0xF5C = { 4456, 5}, - 0xF5D = { 4461, 4}, - 0xF5E = { 4465, 4}, - 0xF5F = { 4469, 4}, - 0xF60 = { 4473, 5}, - 0xF61 = { 4478, 4}, - 0xF62 = { 4482, 4}, - 0xF63 = { 4486, 4}, - 0xF64 = { 4490, 5}, - 0xF65 = { 4495, 3}, - 0xF66 = { 4498, 4}, - 0xF67 = { 4502, 4}, - 0xF68 = { 4506, 5}, - 0xF69 = { 4511, 4}, - 0xF6A = { 4515, 4}, - 0xF6B = { 4519, 4}, - 0xF6C = { 4523, 5}, - 0xF6D = { 4528, 3}, - 0xF6E = { 4531, 4}, - 0xF6F = { 4535, 4}, - 0xF70 = { 4539, 5}, - 0xF71 = { 4544, 4}, - 0xF72 = { 4548, 4}, - 0xF73 = { 4552, 4}, - 0xF74 = { 4556, 4}, - 0xF75 = { 4560, 3}, - 0xF76 = { 4563, 4}, - 0xF77 = { 4567, 4}, - 0xF78 = { 4571, 8}, - 0xF79 = { 4579, 4}, - 0xF7A = { 4583, 4}, - 0xF7B = { 4587, 4}, - 0xF7C = { 4591, 4}, - 0xF7D = { 4595, 3}, - 0xF7E = { 4598, 4}, - 0xF7F = { 4602, 5}, - 0xF80 = { 4607, 1}, - 0xF81 = { 4608, 1}, - 0xF82 = { 4609, 1}, - 0xF83 = { 4610, 2}, - 0xF84 = { 4612, 1}, - 0xF85 = { 4613, 2}, - 0xF88 = { 4615, 1}, - 0xF89 = { 4616, 2}, - 0xF8A = { 4618, 1}, - 0xF8B = { 4619, 1}, - 0xF8C = { 4620, 1}, - 0xF8D = { 4621, 2}, - 0xF91 = { 4623, 1}, - 0xF93 = { 4624, 1}, - 0xF99 = { 4625, 2}, - 0xF9B = { 4627, 1}, - 0xFA0 = { 4628, 3}, - 0xFA1 = { 4631, 3}, - 0xFA2 = { 4634, 3}, - 0xFA3 = { 4637, 3}, - 0xFA4 = { 4640, 3}, - 0xFA5 = { 4643, 3}, - 0xFA6 = { 4646, 1}, - 0xFA7 = { 4647, 1}, - 0xFA8 = { 4648, 10}, - 0xFA9 = { 4658, 10}, - 0xFAA = { 4668, 6}, - 0xFAB = { 4674, 1}, - 0xFAC = { 4675, 6}, - 0xFAD = { 4681, 6}, - 0xFAE = { 4687, 6}, - 0xFB0 = { 4693, 3}, - 0xFB5 = { 4696, 1}, - 0xFB8 = { 4697, 1}, - 0xFB9 = { 4698, 1}, - 0xFBA = { 4699, 1}, - 0xFBB = { 4700, 1}, - 0xFBC = { 4701, 1}, - 0xFBE = { 4702, 1}, - 0xFC0 = { 4703, 1}, - 0xFC1 = { 4704, 1}, - 0xFC2 = { 4705, 3}, - 0xFC3 = { 4708, 3}, - 0xFC4 = { 4711, 1}, - 0xFC5 = { 4712, 1}, - 0xFC6 = { 4713, 2}, - 0xFC7 = { 4715, 2}, - 0xFC8 = { 4717, 7}, - 0xFC9 = { 4724, 11}, - 0xFCA = { 4735, 3}, - 0xFCB = { 4738, 3}, - 0xFCC = { 4741, 7}, - 0xFCD = { 4748, 7}, - 0xFCE = { 4755, 2}, - 0xFCF = { 4757, 2}, - 0xFD2 = { 4759, 1}, - 0xFD3 = { 4760, 1}, - 0xFD9 = { 4761, 4}, - 0xFDA = { 4765, 1}, - 0xFDB = { 4766, 1}, - 0xFE0 = { 4767, 28}, - 0xFE1 = { 4795, 26}, - 0xFE2 = { 4821, 26}, - 0xFE3 = { 4847, 32}, - 0xFE4 = { 4879, 29}, - 0xFE5 = { 4908, 27}, - 0xFE6 = { 4935, 27}, - 0xFE7 = { 4962, 33}, - 0xFE8 = { 4995, 32}, - 0xFE9 = { 5027, 17}, - 0xFEA = { 5044, 17}, - 0xFEB = { 5061, 29}, - 0xFEC = { 5090, 31}, - 0xFED = { 5121, 18}, - 0xFEE = { 5139, 26}, - 0xFEF = { 5165, 32}, - 0xFF0 = { 5197, 19}, - 0xFF1 = { 5216, 18}, - 0xFF2 = { 5234, 17}, - 0xFF3 = { 5251, 17}, - 0xFF4 = { 5268, 19}, - 0xFF5 = { 5287, 18}, - 0xFF6 = { 5305, 17}, - 0xFF7 = { 5322, 17}, - 0xFF8 = { 5339, 4}, - 0xFF9 = { 5343, 4}, - 0xFFA = { 5347, 4}, - 0xFFB = { 5351, 17}, - 0xFFC = { 5368, 4}, - 0xFFD = { 5372, 4}, - 0xFFE = { 5376, 4}, - 0xFFF = { 5380, 17}, + 0xE84 = { 3341, 6}, + 0xE85 = { 3347, 2}, + 0xE86 = { 3349, 1}, + 0xE87 = { 3350, 1}, + 0xE88 = { 3351, 1}, + 0xE89 = { 3352, 1}, + 0xE8A = { 3353, 1}, + 0xE8B = { 3354, 2}, + 0xE8C = { 3356, 4}, + 0xE8D = { 3360, 6}, + 0xE8E = { 3366, 1}, + 0xE8F = { 3367, 1}, + 0xE90 = { 3368, 1}, + 0xE91 = { 3369, 1}, + 0xE92 = { 3370, 2}, + 0xE93 = { 3372, 1}, + 0xE94 = { 3373, 1}, + 0xE95 = { 3374, 1}, + 0xE96 = { 3375, 1}, + 0xE97 = { 3376, 2}, + 0xE9C = { 3378, 1}, + 0xE9D = { 3379, 1}, + 0xE9E = { 3380, 1}, + 0xE9F = { 3381, 1}, + 0xEA0 = { 3382, 2}, + 0xEA1 = { 3384, 3}, + 0xEA2 = { 3387, 1}, + 0xEA3 = { 3388, 1}, + 0xEA4 = { 3389, 7}, + 0xEA5 = { 3396, 7}, + 0xEA6 = { 3403, 1}, + 0xEA7 = { 3404, 1}, + 0xEA8 = { 3405, 1}, + 0xEA9 = { 3406, 2}, + 0xEB1 = { 3408, 1}, + 0xEB4 = { 3409, 1}, + 0xEB5 = { 3410, 1}, + 0xEB6 = { 3411, 1}, + 0xEB7 = { 3412, 1}, + 0xEBB = { 3413, 1}, + 0xEBC = { 3414, 1}, + 0xEBD = { 3415, 1}, + 0xEC0 = { 3416, 2}, + 0xEC1 = { 3418, 1}, + 0xEC2 = { 3419, 3}, + 0xEC3 = { 3422, 2}, + 0xEC4 = { 3424, 2}, + 0xEC5 = { 3426, 1}, + 0xEC6 = { 3427, 7}, + 0xEC7 = { 3434, 2}, + 0xEC8 = { 3436, 1}, + 0xEC9 = { 3437, 1}, + 0xECA = { 3438, 2}, + 0xECB = { 3440, 2}, + 0xECC = { 3442, 1}, + 0xECD = { 3443, 1}, + 0xECE = { 3444, 2}, + 0xECF = { 3446, 2}, + 0xED6 = { 3448, 4}, + 0xED8 = { 3452, 4}, + 0xED9 = { 3456, 4}, + 0xEDC = { 3460, 4}, + 0xEDD = { 3464, 4}, + 0xEE0 = { 3468, 24}, + 0xEE1 = { 3492, 23}, + 0xEE2 = { 3515, 22}, + 0xEE3 = { 3537, 29}, + 0xEE4 = { 3566, 23}, + 0xEE5 = { 3589, 22}, + 0xEE6 = { 3611, 22}, + 0xEE7 = { 3633, 29}, + 0xEE8 = { 3662, 28}, + 0xEE9 = { 3690, 12}, + 0xEEA = { 3702, 13}, + 0xEEB = { 3715, 18}, + 0xEEC = { 3733, 27}, + 0xEED = { 3760, 13}, + 0xEEE = { 3773, 22}, + 0xEEF = { 3795, 23}, + 0xEF0 = { 3818, 15}, + 0xEF1 = { 3833, 15}, + 0xEF2 = { 3848, 15}, + 0xEF3 = { 3863, 15}, + 0xEF4 = { 3878, 15}, + 0xEF5 = { 3893, 15}, + 0xEF6 = { 3908, 15}, + 0xEF7 = { 3923, 15}, + 0xEF8 = { 3938, 3}, + 0xEF9 = { 3941, 3}, + 0xEFA = { 3944, 3}, + 0xEFB = { 3947, 3}, + 0xEFC = { 3950, 3}, + 0xEFD = { 3953, 3}, + 0xEFE = { 3956, 3}, + 0xEFF = { 3959, 3}, + 0xF00 = { 3962, 12}, + 0xF01 = { 3974, 11}, + 0xF02 = { 3985, 8}, + 0xF03 = { 3993, 8}, + 0xF04 = { 4001, 9}, + 0xF05 = { 4010, 6}, + 0xF06 = { 4016, 5}, + 0xF07 = { 4021, 5}, + 0xF08 = { 4026, 6}, + 0xF09 = { 4032, 6}, + 0xF0A = { 4038, 4}, + 0xF0B = { 4042, 4}, + 0xF0C = { 4046, 4}, + 0xF0D = { 4050, 3}, + 0xF0E = { 4053, 4}, + 0xF0F = { 4057, 4}, + 0xF10 = { 4061, 7}, + 0xF11 = { 4068, 7}, + 0xF12 = { 4075, 6}, + 0xF13 = { 4081, 6}, + 0xF14 = { 4087, 5}, + 0xF15 = { 4092, 4}, + 0xF16 = { 4096, 5}, + 0xF17 = { 4101, 5}, + 0xF18 = { 4106, 5}, + 0xF19 = { 4111, 4}, + 0xF1A = { 4115, 4}, + 0xF1B = { 4119, 5}, + 0xF1C = { 4124, 5}, + 0xF1D = { 4129, 4}, + 0xF1E = { 4133, 4}, + 0xF1F = { 4137, 4}, + 0xF20 = { 4141, 5}, + 0xF21 = { 4146, 4}, + 0xF22 = { 4150, 4}, + 0xF23 = { 4154, 4}, + 0xF24 = { 4158, 5}, + 0xF25 = { 4163, 3}, + 0xF26 = { 4166, 4}, + 0xF27 = { 4170, 4}, + 0xF28 = { 4174, 5}, + 0xF29 = { 4179, 4}, + 0xF2A = { 4183, 4}, + 0xF2B = { 4187, 4}, + 0xF2C = { 4191, 5}, + 0xF2D = { 4196, 3}, + 0xF2E = { 4199, 4}, + 0xF2F = { 4203, 4}, + 0xF30 = { 4207, 6}, + 0xF31 = { 4213, 4}, + 0xF32 = { 4217, 6}, + 0xF33 = { 4223, 4}, + 0xF34 = { 4227, 5}, + 0xF35 = { 4232, 3}, + 0xF36 = { 4235, 6}, + 0xF37 = { 4241, 4}, + 0xF38 = { 4245, 7}, + 0xF39 = { 4252, 4}, + 0xF3A = { 4256, 19}, + 0xF3B = { 4275, 9}, + 0xF3C = { 4284, 5}, + 0xF3D = { 4289, 3}, + 0xF3E = { 4292, 5}, + 0xF3F = { 4297, 4}, + 0xF40 = { 4301, 7}, + 0xF41 = { 4308, 7}, + 0xF42 = { 4315, 5}, + 0xF43 = { 4320, 5}, + 0xF44 = { 4325, 7}, + 0xF45 = { 4332, 6}, + 0xF46 = { 4338, 5}, + 0xF47 = { 4343, 5}, + 0xF48 = { 4348, 6}, + 0xF49 = { 4354, 6}, + 0xF4A = { 4360, 4}, + 0xF4B = { 4364, 4}, + 0xF4C = { 4368, 4}, + 0xF4D = { 4372, 3}, + 0xF4E = { 4375, 4}, + 0xF4F = { 4379, 4}, + 0xF50 = { 4383, 5}, + 0xF51 = { 4388, 5}, + 0xF52 = { 4393, 4}, + 0xF53 = { 4397, 4}, + 0xF54 = { 4401, 5}, + 0xF55 = { 4406, 4}, + 0xF56 = { 4410, 5}, + 0xF57 = { 4415, 5}, + 0xF58 = { 4420, 5}, + 0xF59 = { 4425, 4}, + 0xF5A = { 4429, 4}, + 0xF5B = { 4433, 5}, + 0xF5C = { 4438, 5}, + 0xF5D = { 4443, 4}, + 0xF5E = { 4447, 4}, + 0xF5F = { 4451, 4}, + 0xF60 = { 4455, 5}, + 0xF61 = { 4460, 4}, + 0xF62 = { 4464, 4}, + 0xF63 = { 4468, 4}, + 0xF64 = { 4472, 5}, + 0xF65 = { 4477, 3}, + 0xF66 = { 4480, 4}, + 0xF67 = { 4484, 4}, + 0xF68 = { 4488, 5}, + 0xF69 = { 4493, 4}, + 0xF6A = { 4497, 4}, + 0xF6B = { 4501, 4}, + 0xF6C = { 4505, 5}, + 0xF6D = { 4510, 3}, + 0xF6E = { 4513, 4}, + 0xF6F = { 4517, 4}, + 0xF70 = { 4521, 5}, + 0xF71 = { 4526, 4}, + 0xF72 = { 4530, 4}, + 0xF73 = { 4534, 4}, + 0xF74 = { 4538, 4}, + 0xF75 = { 4542, 3}, + 0xF76 = { 4545, 4}, + 0xF77 = { 4549, 4}, + 0xF78 = { 4553, 8}, + 0xF79 = { 4561, 4}, + 0xF7A = { 4565, 4}, + 0xF7B = { 4569, 4}, + 0xF7C = { 4573, 4}, + 0xF7D = { 4577, 3}, + 0xF7E = { 4580, 4}, + 0xF7F = { 4584, 5}, + 0xF80 = { 4589, 1}, + 0xF81 = { 4590, 1}, + 0xF82 = { 4591, 1}, + 0xF83 = { 4592, 2}, + 0xF84 = { 4594, 1}, + 0xF85 = { 4595, 2}, + 0xF88 = { 4597, 1}, + 0xF89 = { 4598, 2}, + 0xF8A = { 4600, 1}, + 0xF8B = { 4601, 1}, + 0xF8C = { 4602, 1}, + 0xF8D = { 4603, 2}, + 0xF91 = { 4605, 1}, + 0xF93 = { 4606, 1}, + 0xF99 = { 4607, 2}, + 0xF9B = { 4609, 1}, + 0xFA0 = { 4610, 3}, + 0xFA1 = { 4613, 3}, + 0xFA2 = { 4616, 3}, + 0xFA3 = { 4619, 3}, + 0xFA4 = { 4622, 3}, + 0xFA5 = { 4625, 3}, + 0xFA6 = { 4628, 1}, + 0xFA7 = { 4629, 1}, + 0xFA8 = { 4630, 10}, + 0xFA9 = { 4640, 10}, + 0xFAA = { 4650, 6}, + 0xFAB = { 4656, 1}, + 0xFAC = { 4657, 6}, + 0xFAD = { 4663, 6}, + 0xFAE = { 4669, 6}, + 0xFB0 = { 4675, 3}, + 0xFB5 = { 4678, 1}, + 0xFB8 = { 4679, 1}, + 0xFB9 = { 4680, 1}, + 0xFBA = { 4681, 1}, + 0xFBB = { 4682, 1}, + 0xFBC = { 4683, 1}, + 0xFBE = { 4684, 1}, + 0xFC0 = { 4685, 1}, + 0xFC1 = { 4686, 1}, + 0xFC2 = { 4687, 3}, + 0xFC3 = { 4690, 3}, + 0xFC4 = { 4693, 1}, + 0xFC5 = { 4694, 1}, + 0xFC6 = { 4695, 2}, + 0xFC7 = { 4697, 2}, + 0xFC8 = { 4699, 7}, + 0xFC9 = { 4706, 11}, + 0xFCA = { 4717, 3}, + 0xFCB = { 4720, 3}, + 0xFCC = { 4723, 7}, + 0xFCD = { 4730, 7}, + 0xFCE = { 4737, 2}, + 0xFCF = { 4739, 2}, + 0xFD2 = { 4741, 1}, + 0xFD3 = { 4742, 1}, + 0xFD9 = { 4743, 4}, + 0xFDA = { 4747, 1}, + 0xFDB = { 4748, 1}, + 0xFE0 = { 4749, 28}, + 0xFE1 = { 4777, 26}, + 0xFE2 = { 4803, 26}, + 0xFE3 = { 4829, 32}, + 0xFE4 = { 4861, 29}, + 0xFE5 = { 4890, 27}, + 0xFE6 = { 4917, 27}, + 0xFE7 = { 4944, 33}, + 0xFE8 = { 4977, 32}, + 0xFE9 = { 5009, 17}, + 0xFEA = { 5026, 17}, + 0xFEB = { 5043, 29}, + 0xFEC = { 5072, 31}, + 0xFED = { 5103, 18}, + 0xFEE = { 5121, 26}, + 0xFEF = { 5147, 32}, + 0xFF0 = { 5179, 19}, + 0xFF1 = { 5198, 18}, + 0xFF2 = { 5216, 17}, + 0xFF3 = { 5233, 17}, + 0xFF4 = { 5250, 19}, + 0xFF5 = { 5269, 18}, + 0xFF6 = { 5287, 17}, + 0xFF7 = { 5304, 17}, + 0xFF8 = { 5321, 4}, + 0xFF9 = { 5325, 4}, + 0xFFA = { 5329, 4}, + 0xFFB = { 5333, 17}, + 0xFFC = { 5350, 4}, + 0xFFD = { 5354, 4}, + 0xFFE = { 5358, 4}, + 0xFFF = { 5362, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 17a9506a2..ac5d48cde 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1665]lib.Encoding{ +ENCODE_FORMS := [1656]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -993,8 +993,6 @@ ENCODE_FORMS := [1665]lib.Encoding{ { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMS { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, @@ -1003,8 +1001,6 @@ ENCODE_FORMS := [1665]lib.Encoding{ { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, // .VFNMA { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, @@ -1603,6 +1599,7 @@ ENCODE_FORMS := [1665]lib.Encoding{ { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, // .VPADDL { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1727,15 +1724,6 @@ ENCODE_FORMS := [1665]lib.Encoding{ // .VCNT { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - // .VPADD_F - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - // .VRECPE_F - { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - // .VRSQRTE_F - { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VREV16 { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -2540,335 +2528,332 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .VNMUL = { 704, 2}, .VNMLA = { 706, 2}, .VNMLS = { 708, 2}, - .VFMA = { 710, 10}, - .VFMS = { 720, 8}, - .VFNMA = { 728, 3}, - .VFNMS = { 731, 3}, - .VABS = { 734, 12}, - .VNEG = { 746, 12}, - .VSQRT = { 758, 3}, - .VCMP = { 761, 8}, - .VCMPE = { 769, 4}, - .VCVT = { 773, 21}, - .VCVTB = { 794, 2}, - .VCVTT = { 796, 2}, - .VCVTA = { 798, 2}, - .VCVTN = { 800, 2}, - .VCVTP = { 802, 2}, - .VCVTM = { 804, 2}, - .VCVTR = { 806, 4}, - .VMOV = { 810, 31}, - .VMRS = { 841, 1}, - .VMSR = { 842, 1}, - .VLDR = { 843, 2}, - .VSTR = { 845, 2}, - .VLDM = { 847, 2}, - .VSTM = { 849, 2}, - .VPUSH = { 851, 2}, - .VPOP = { 853, 2}, - .VSEL = { 855, 2}, - .VMAXNM = { 857, 2}, - .VMINNM = { 859, 2}, - .VRINTA = { 861, 3}, - .VRINTN = { 864, 3}, - .VRINTP = { 867, 3}, - .VRINTM = { 870, 3}, - .VRINTR = { 873, 2}, - .VRINTZ = { 875, 3}, - .VRINTX = { 878, 3}, - .VADDL = { 881, 6}, - .VADDW = { 887, 6}, - .VSUBL = { 893, 6}, - .VSUBW = { 899, 6}, - .VHADD = { 905, 9}, - .VHSUB = { 914, 9}, - .VRHADD = { 923, 3}, - .VQADD = { 926, 11}, - .VQSUB = { 937, 11}, - .VMULL = { 948, 11}, - .VMLAL = { 959, 10}, - .VMLSL = { 969, 10}, - .VQDMULL = { 979, 4}, - .VQDMLAL = { 983, 4}, - .VQDMLSL = { 987, 4}, - .VQDMULH = { 991, 8}, - .VQRDMULH = { 999, 8}, - .VQRDMLAH = { 1007, 8}, - .VQRDMLSH = { 1015, 8}, - .VABA = { 1023, 8}, - .VABAL = { 1031, 6}, - .VABD = { 1037, 10}, - .VABDL = { 1047, 6}, - .VAND = { 1053, 3}, - .VBIC = { 1056, 3}, - .VORR = { 1059, 3}, - .VORN = { 1062, 3}, - .VEOR = { 1065, 3}, - .VBSL = { 1068, 2}, - .VBIT = { 1070, 2}, - .VBIF = { 1072, 2}, - .VMVN = { 1074, 13}, - .VMOVN = { 1087, 3}, - .VQMOVN = { 1090, 6}, - .VQMOVUN = { 1096, 3}, - .VMOVL = { 1099, 6}, - .VTST = { 1105, 6}, - .VCEQ = { 1111, 14}, - .VCGE = { 1125, 16}, - .VCGT = { 1141, 16}, - .VCLE = { 1157, 18}, - .VCLT = { 1175, 18}, - .VACGE = { 1193, 2}, - .VACGT = { 1195, 2}, - .VACLE = { 1197, 2}, - .VACLT = { 1199, 2}, - .VMAX = { 1201, 13}, - .VMIN = { 1214, 13}, - .VPMAX = { 1227, 5}, - .VPMIN = { 1232, 5}, - .VPADD = { 1237, 4}, - .VPADDL = { 1241, 6}, - .VPADAL = { 1247, 4}, - .VRECPE = { 1251, 4}, - .VRECPS = { 1255, 2}, - .VRSQRTE = { 1257, 4}, - .VRSQRTS = { 1261, 2}, - .VSHL = { 1263, 9}, - .VSHR = { 1272, 3}, - .VSRA = { 1275, 3}, - .VRSHL = { 1278, 5}, - .VRSHR = { 1283, 3}, - .VRSRA = { 1286, 2}, - .VSLI = { 1288, 2}, - .VSRI = { 1290, 2}, - .VQSHL = { 1292, 7}, - .VQSHRN = { 1299, 1}, - .VQSHRUN = { 1300, 1}, - .VQRSHL = { 1301, 16}, - .VQRSHRN = { 1317, 1}, - .VQRSHRUN = { 1318, 1}, - .VSHRN = { 1319, 1}, - .VRSHRN = { 1320, 1}, - .VSHLL = { 1321, 4}, - .VCLS = { 1325, 6}, - .VCLZ = { 1331, 6}, - .VCNT = { 1337, 2}, - .VPADD_F = { 1339, 2}, - .VRECPE_F = { 1341, 2}, - .VRSQRTE_F = { 1343, 2}, - .VREV16 = { 1345, 2}, - .VREV32 = { 1347, 4}, - .VREV64 = { 1351, 6}, - .VEXT = { 1357, 2}, - .VTBL = { 1359, 4}, - .VTBX = { 1363, 4}, - .VTRN = { 1367, 6}, - .VUZP = { 1373, 5}, - .VZIP = { 1378, 5}, - .VDUP = { 1383, 5}, - .VSWP = { 1388, 2}, - .VMOV_LANE = { 1390, 3}, - .VLD1 = { 1393, 8}, - .VLD2 = { 1401, 3}, - .VLD3 = { 1404, 2}, - .VLD4 = { 1406, 2}, - .VST1 = { 1408, 7}, - .VST2 = { 1415, 3}, - .VST3 = { 1418, 2}, - .VST4 = { 1420, 2}, - .AESE = { 1422, 1}, - .AESD = { 1423, 1}, - .AESMC = { 1424, 1}, - .AESIMC = { 1425, 1}, - .SHA1H = { 1426, 1}, - .SHA1SU0 = { 1427, 1}, - .SHA1SU1 = { 1428, 1}, - .SHA1C = { 1429, 1}, - .SHA1M = { 1430, 1}, - .SHA1P = { 1431, 1}, - .SHA256H = { 1432, 1}, - .SHA256H2 = { 1433, 1}, - .SHA256SU0 = { 1434, 1}, - .SHA256SU1 = { 1435, 1}, - .VJCVT = { 1436, 1}, - .VSDOT = { 1437, 4}, - .VUDOT = { 1441, 4}, - .VDOT = { 1445, 2}, - .VMMLA = { 1447, 1}, - .VFMAL = { 1448, 2}, - .VFMSL = { 1450, 2}, - .VCMLA = { 1452, 5}, - .VCADD = { 1457, 2}, - .VSMMLA = { 1459, 1}, - .VUMMLA = { 1460, 1}, - .VUSMMLA = { 1461, 1}, - .VSUDOT = { 1462, 2}, - .VUSDOT = { 1464, 4}, - .VQABS = { 1468, 1}, - .VQNEG = { 1469, 1}, - .VMOVX = { 1470, 1}, - .VINS = { 1471, 1}, - .VLD2R = { 1472, 1}, - .VLD3R = { 1473, 1}, - .VLD4R = { 1474, 1}, - .VLD1_LANE = { 1475, 3}, - .VLD2_LANE = { 1478, 3}, - .VLD3_LANE = { 1481, 3}, - .VLD4_LANE = { 1484, 3}, - .VST1_LANE = { 1487, 3}, - .VST2_LANE = { 1490, 3}, - .VST3_LANE = { 1493, 3}, - .VST4_LANE = { 1496, 3}, - .IT = { 1499, 1}, - .TT = { 1500, 1}, - .TTT = { 1501, 1}, - .TTA = { 1502, 1}, - .TTAT = { 1503, 1}, - .SG = { 1504, 1}, - .BXNS = { 1505, 1}, - .BLXNS = { 1506, 1}, - .PAC = { 1507, 1}, - .PACBTI = { 1508, 1}, - .AUT = { 1509, 1}, - .AUTG = { 1510, 1}, - .BTI = { 1511, 1}, - .WLS = { 1512, 1}, - .WLSTP = { 1513, 1}, - .DLS = { 1514, 1}, - .DLSTP = { 1515, 1}, - .LE = { 1516, 1}, - .LETP = { 1517, 1}, - .LCTP = { 1518, 1}, - .BF = { 1519, 1}, - .BFX = { 1520, 1}, - .BFL = { 1521, 1}, - .BFLX = { 1522, 1}, - .BFCSEL = { 1523, 1}, - .CX1 = { 1524, 1}, - .CX1A = { 1525, 1}, - .CX1D = { 1526, 1}, - .CX1DA = { 1527, 1}, - .CX2 = { 1528, 1}, - .CX2A = { 1529, 1}, - .CX2D = { 1530, 1}, - .CX2DA = { 1531, 1}, - .CX3 = { 1532, 1}, - .CX3A = { 1533, 1}, - .CX3D = { 1534, 1}, - .CX3DA = { 1535, 1}, - .VCX1 = { 1536, 2}, - .VCX1A = { 1538, 2}, - .VCX2 = { 1540, 2}, - .VCX2A = { 1542, 2}, - .VCX3 = { 1544, 2}, - .VCX3A = { 1546, 2}, - .VPT = { 1548, 1}, - .VPST = { 1549, 1}, - .VPSEL = { 1550, 1}, - .VPNOT = { 1551, 1}, - .VCTP = { 1552, 1}, - .VADDV = { 1553, 1}, - .VADDVA = { 1554, 1}, - .VADDLV = { 1555, 1}, - .VADDLVA = { 1556, 1}, - .VMAXV = { 1557, 1}, - .VMAXAV = { 1558, 1}, - .VMINV = { 1559, 1}, - .VMINAV = { 1560, 1}, - .VMAXNMV = { 1561, 1}, - .VMAXNMAV = { 1562, 1}, - .VMINNMV = { 1563, 1}, - .VMINNMAV = { 1564, 1}, - .VABAV = { 1565, 1}, - .VMLADAV = { 1566, 1}, - .VMLADAVA = { 1567, 1}, - .VMLADAVX = { 1568, 1}, - .VMLADAVAX = { 1569, 1}, - .VMLALDAV = { 1570, 1}, - .VMLALDAVA = { 1571, 1}, - .VMLALDAVX = { 1572, 1}, - .VMLALDAVAX = { 1573, 1}, - .VMLSDAV = { 1574, 1}, - .VMLSDAVA = { 1575, 1}, - .VMLSDAVX = { 1576, 1}, - .VMLSDAVAX = { 1577, 1}, - .VMLSLDAV = { 1578, 1}, - .VMLSLDAVA = { 1579, 1}, - .VMLSLDAVX = { 1580, 1}, - .VMLSLDAVAX = { 1581, 1}, - .VRMLALDAVH = { 1582, 1}, - .VRMLALDAVHA = { 1583, 1}, - .VRMLALDAVHX = { 1584, 1}, - .VRMLALDAVHAX = { 1585, 1}, - .VRMLSLDAVH = { 1586, 1}, - .VRMLSLDAVHA = { 1587, 1}, - .VRMLSLDAVHX = { 1588, 1}, - .VRMLSLDAVHAX = { 1589, 1}, - .VMLAV = { 1590, 1}, - .VMLAVA = { 1591, 1}, - .VMLSV = { 1592, 1}, - .VMLSVA = { 1593, 1}, - .VCMUL = { 1594, 1}, - .VHCADD = { 1595, 2}, - .VBRSR = { 1597, 1}, - .VSHLC = { 1598, 1}, - .VDDUP = { 1599, 1}, - .VIDUP = { 1600, 1}, - .VDWDUP = { 1601, 1}, - .VIWDUP = { 1602, 1}, - .VMOVNB = { 1603, 1}, - .VMOVNT = { 1604, 1}, - .VQMOVNB = { 1605, 1}, - .VQMOVNT = { 1606, 1}, - .VQMOVUNB = { 1607, 1}, - .VQMOVUNT = { 1608, 1}, - .VSHLLB = { 1609, 1}, - .VSHLLT = { 1610, 1}, - .VMULLB = { 1611, 1}, - .VMULLT = { 1612, 1}, - .VMLALB = { 1613, 1}, - .VMLALT = { 1614, 1}, - .VMLSLB = { 1615, 1}, - .VMLSLT = { 1616, 1}, - .VSHRNB = { 1617, 1}, - .VSHRNT = { 1618, 1}, - .VRSHRNB = { 1619, 1}, - .VRSHRNT = { 1620, 1}, - .VQSHRNB = { 1621, 1}, - .VQSHRNT = { 1622, 1}, - .VQRSHRNB = { 1623, 1}, - .VQRSHRNT = { 1624, 1}, - .VQSHRUNB = { 1625, 1}, - .VQSHRUNT = { 1626, 1}, - .VQRSHRUNB = { 1627, 1}, - .VQRSHRUNT = { 1628, 1}, - .VQDMLADH = { 1629, 1}, - .VQDMLADHX = { 1630, 1}, - .VQDMLSDH = { 1631, 1}, - .VQDMLSDHX = { 1632, 1}, - .VQRDMLADH = { 1633, 1}, - .VQRDMLADHX = { 1634, 1}, - .VQRDMLSDH = { 1635, 1}, - .VQRDMLSDHX = { 1636, 1}, - .VLDRB = { 1637, 2}, - .VLDRH = { 1639, 2}, - .VLDRW = { 1641, 2}, - .VLDRD = { 1643, 2}, - .VSTRB = { 1645, 2}, - .VSTRH = { 1647, 2}, - .VSTRW = { 1649, 2}, - .VSTRD = { 1651, 2}, - .VLD20 = { 1653, 1}, - .VLD21 = { 1654, 1}, - .VLD40 = { 1655, 1}, - .VLD41 = { 1656, 1}, - .VLD42 = { 1657, 1}, - .VLD43 = { 1658, 1}, - .VST20 = { 1659, 1}, - .VST21 = { 1660, 1}, - .VST40 = { 1661, 1}, - .VST41 = { 1662, 1}, - .VST42 = { 1663, 1}, - .VST43 = { 1664, 1}, - ._COUNT = { 1665, 0}, + .VFMA = { 710, 8}, + .VFMS = { 718, 6}, + .VFNMA = { 724, 3}, + .VFNMS = { 727, 3}, + .VABS = { 730, 12}, + .VNEG = { 742, 12}, + .VSQRT = { 754, 3}, + .VCMP = { 757, 8}, + .VCMPE = { 765, 4}, + .VCVT = { 769, 21}, + .VCVTB = { 790, 2}, + .VCVTT = { 792, 2}, + .VCVTA = { 794, 2}, + .VCVTN = { 796, 2}, + .VCVTP = { 798, 2}, + .VCVTM = { 800, 2}, + .VCVTR = { 802, 4}, + .VMOV = { 806, 31}, + .VMRS = { 837, 1}, + .VMSR = { 838, 1}, + .VLDR = { 839, 2}, + .VSTR = { 841, 2}, + .VLDM = { 843, 2}, + .VSTM = { 845, 2}, + .VPUSH = { 847, 2}, + .VPOP = { 849, 2}, + .VSEL = { 851, 2}, + .VMAXNM = { 853, 2}, + .VMINNM = { 855, 2}, + .VRINTA = { 857, 3}, + .VRINTN = { 860, 3}, + .VRINTP = { 863, 3}, + .VRINTM = { 866, 3}, + .VRINTR = { 869, 2}, + .VRINTZ = { 871, 3}, + .VRINTX = { 874, 3}, + .VADDL = { 877, 6}, + .VADDW = { 883, 6}, + .VSUBL = { 889, 6}, + .VSUBW = { 895, 6}, + .VHADD = { 901, 9}, + .VHSUB = { 910, 9}, + .VRHADD = { 919, 3}, + .VQADD = { 922, 11}, + .VQSUB = { 933, 11}, + .VMULL = { 944, 11}, + .VMLAL = { 955, 10}, + .VMLSL = { 965, 10}, + .VQDMULL = { 975, 4}, + .VQDMLAL = { 979, 4}, + .VQDMLSL = { 983, 4}, + .VQDMULH = { 987, 8}, + .VQRDMULH = { 995, 8}, + .VQRDMLAH = { 1003, 8}, + .VQRDMLSH = { 1011, 8}, + .VABA = { 1019, 8}, + .VABAL = { 1027, 6}, + .VABD = { 1033, 10}, + .VABDL = { 1043, 6}, + .VAND = { 1049, 3}, + .VBIC = { 1052, 3}, + .VORR = { 1055, 3}, + .VORN = { 1058, 3}, + .VEOR = { 1061, 3}, + .VBSL = { 1064, 2}, + .VBIT = { 1066, 2}, + .VBIF = { 1068, 2}, + .VMVN = { 1070, 13}, + .VMOVN = { 1083, 3}, + .VQMOVN = { 1086, 6}, + .VQMOVUN = { 1092, 3}, + .VMOVL = { 1095, 6}, + .VTST = { 1101, 6}, + .VCEQ = { 1107, 14}, + .VCGE = { 1121, 16}, + .VCGT = { 1137, 16}, + .VCLE = { 1153, 18}, + .VCLT = { 1171, 18}, + .VACGE = { 1189, 2}, + .VACGT = { 1191, 2}, + .VACLE = { 1193, 2}, + .VACLT = { 1195, 2}, + .VMAX = { 1197, 13}, + .VMIN = { 1210, 13}, + .VPMAX = { 1223, 5}, + .VPMIN = { 1228, 5}, + .VPADD = { 1233, 5}, + .VPADDL = { 1238, 6}, + .VPADAL = { 1244, 4}, + .VRECPE = { 1248, 4}, + .VRECPS = { 1252, 2}, + .VRSQRTE = { 1254, 4}, + .VRSQRTS = { 1258, 2}, + .VSHL = { 1260, 9}, + .VSHR = { 1269, 3}, + .VSRA = { 1272, 3}, + .VRSHL = { 1275, 5}, + .VRSHR = { 1280, 3}, + .VRSRA = { 1283, 2}, + .VSLI = { 1285, 2}, + .VSRI = { 1287, 2}, + .VQSHL = { 1289, 7}, + .VQSHRN = { 1296, 1}, + .VQSHRUN = { 1297, 1}, + .VQRSHL = { 1298, 16}, + .VQRSHRN = { 1314, 1}, + .VQRSHRUN = { 1315, 1}, + .VSHRN = { 1316, 1}, + .VRSHRN = { 1317, 1}, + .VSHLL = { 1318, 4}, + .VCLS = { 1322, 6}, + .VCLZ = { 1328, 6}, + .VCNT = { 1334, 2}, + .VREV16 = { 1336, 2}, + .VREV32 = { 1338, 4}, + .VREV64 = { 1342, 6}, + .VEXT = { 1348, 2}, + .VTBL = { 1350, 4}, + .VTBX = { 1354, 4}, + .VTRN = { 1358, 6}, + .VUZP = { 1364, 5}, + .VZIP = { 1369, 5}, + .VDUP = { 1374, 5}, + .VSWP = { 1379, 2}, + .VMOV_LANE = { 1381, 3}, + .VLD1 = { 1384, 8}, + .VLD2 = { 1392, 3}, + .VLD3 = { 1395, 2}, + .VLD4 = { 1397, 2}, + .VST1 = { 1399, 7}, + .VST2 = { 1406, 3}, + .VST3 = { 1409, 2}, + .VST4 = { 1411, 2}, + .AESE = { 1413, 1}, + .AESD = { 1414, 1}, + .AESMC = { 1415, 1}, + .AESIMC = { 1416, 1}, + .SHA1H = { 1417, 1}, + .SHA1SU0 = { 1418, 1}, + .SHA1SU1 = { 1419, 1}, + .SHA1C = { 1420, 1}, + .SHA1M = { 1421, 1}, + .SHA1P = { 1422, 1}, + .SHA256H = { 1423, 1}, + .SHA256H2 = { 1424, 1}, + .SHA256SU0 = { 1425, 1}, + .SHA256SU1 = { 1426, 1}, + .VJCVT = { 1427, 1}, + .VSDOT = { 1428, 4}, + .VUDOT = { 1432, 4}, + .VDOT = { 1436, 2}, + .VMMLA = { 1438, 1}, + .VFMAL = { 1439, 2}, + .VFMSL = { 1441, 2}, + .VCMLA = { 1443, 5}, + .VCADD = { 1448, 2}, + .VSMMLA = { 1450, 1}, + .VUMMLA = { 1451, 1}, + .VUSMMLA = { 1452, 1}, + .VSUDOT = { 1453, 2}, + .VUSDOT = { 1455, 4}, + .VQABS = { 1459, 1}, + .VQNEG = { 1460, 1}, + .VMOVX = { 1461, 1}, + .VINS = { 1462, 1}, + .VLD2R = { 1463, 1}, + .VLD3R = { 1464, 1}, + .VLD4R = { 1465, 1}, + .VLD1_LANE = { 1466, 3}, + .VLD2_LANE = { 1469, 3}, + .VLD3_LANE = { 1472, 3}, + .VLD4_LANE = { 1475, 3}, + .VST1_LANE = { 1478, 3}, + .VST2_LANE = { 1481, 3}, + .VST3_LANE = { 1484, 3}, + .VST4_LANE = { 1487, 3}, + .IT = { 1490, 1}, + .TT = { 1491, 1}, + .TTT = { 1492, 1}, + .TTA = { 1493, 1}, + .TTAT = { 1494, 1}, + .SG = { 1495, 1}, + .BXNS = { 1496, 1}, + .BLXNS = { 1497, 1}, + .PAC = { 1498, 1}, + .PACBTI = { 1499, 1}, + .AUT = { 1500, 1}, + .AUTG = { 1501, 1}, + .BTI = { 1502, 1}, + .WLS = { 1503, 1}, + .WLSTP = { 1504, 1}, + .DLS = { 1505, 1}, + .DLSTP = { 1506, 1}, + .LE = { 1507, 1}, + .LETP = { 1508, 1}, + .LCTP = { 1509, 1}, + .BF = { 1510, 1}, + .BFX = { 1511, 1}, + .BFL = { 1512, 1}, + .BFLX = { 1513, 1}, + .BFCSEL = { 1514, 1}, + .CX1 = { 1515, 1}, + .CX1A = { 1516, 1}, + .CX1D = { 1517, 1}, + .CX1DA = { 1518, 1}, + .CX2 = { 1519, 1}, + .CX2A = { 1520, 1}, + .CX2D = { 1521, 1}, + .CX2DA = { 1522, 1}, + .CX3 = { 1523, 1}, + .CX3A = { 1524, 1}, + .CX3D = { 1525, 1}, + .CX3DA = { 1526, 1}, + .VCX1 = { 1527, 2}, + .VCX1A = { 1529, 2}, + .VCX2 = { 1531, 2}, + .VCX2A = { 1533, 2}, + .VCX3 = { 1535, 2}, + .VCX3A = { 1537, 2}, + .VPT = { 1539, 1}, + .VPST = { 1540, 1}, + .VPSEL = { 1541, 1}, + .VPNOT = { 1542, 1}, + .VCTP = { 1543, 1}, + .VADDV = { 1544, 1}, + .VADDVA = { 1545, 1}, + .VADDLV = { 1546, 1}, + .VADDLVA = { 1547, 1}, + .VMAXV = { 1548, 1}, + .VMAXAV = { 1549, 1}, + .VMINV = { 1550, 1}, + .VMINAV = { 1551, 1}, + .VMAXNMV = { 1552, 1}, + .VMAXNMAV = { 1553, 1}, + .VMINNMV = { 1554, 1}, + .VMINNMAV = { 1555, 1}, + .VABAV = { 1556, 1}, + .VMLADAV = { 1557, 1}, + .VMLADAVA = { 1558, 1}, + .VMLADAVX = { 1559, 1}, + .VMLADAVAX = { 1560, 1}, + .VMLALDAV = { 1561, 1}, + .VMLALDAVA = { 1562, 1}, + .VMLALDAVX = { 1563, 1}, + .VMLALDAVAX = { 1564, 1}, + .VMLSDAV = { 1565, 1}, + .VMLSDAVA = { 1566, 1}, + .VMLSDAVX = { 1567, 1}, + .VMLSDAVAX = { 1568, 1}, + .VMLSLDAV = { 1569, 1}, + .VMLSLDAVA = { 1570, 1}, + .VMLSLDAVX = { 1571, 1}, + .VMLSLDAVAX = { 1572, 1}, + .VRMLALDAVH = { 1573, 1}, + .VRMLALDAVHA = { 1574, 1}, + .VRMLALDAVHX = { 1575, 1}, + .VRMLALDAVHAX = { 1576, 1}, + .VRMLSLDAVH = { 1577, 1}, + .VRMLSLDAVHA = { 1578, 1}, + .VRMLSLDAVHX = { 1579, 1}, + .VRMLSLDAVHAX = { 1580, 1}, + .VMLAV = { 1581, 1}, + .VMLAVA = { 1582, 1}, + .VMLSV = { 1583, 1}, + .VMLSVA = { 1584, 1}, + .VCMUL = { 1585, 1}, + .VHCADD = { 1586, 2}, + .VBRSR = { 1588, 1}, + .VSHLC = { 1589, 1}, + .VDDUP = { 1590, 1}, + .VIDUP = { 1591, 1}, + .VDWDUP = { 1592, 1}, + .VIWDUP = { 1593, 1}, + .VMOVNB = { 1594, 1}, + .VMOVNT = { 1595, 1}, + .VQMOVNB = { 1596, 1}, + .VQMOVNT = { 1597, 1}, + .VQMOVUNB = { 1598, 1}, + .VQMOVUNT = { 1599, 1}, + .VSHLLB = { 1600, 1}, + .VSHLLT = { 1601, 1}, + .VMULLB = { 1602, 1}, + .VMULLT = { 1603, 1}, + .VMLALB = { 1604, 1}, + .VMLALT = { 1605, 1}, + .VMLSLB = { 1606, 1}, + .VMLSLT = { 1607, 1}, + .VSHRNB = { 1608, 1}, + .VSHRNT = { 1609, 1}, + .VRSHRNB = { 1610, 1}, + .VRSHRNT = { 1611, 1}, + .VQSHRNB = { 1612, 1}, + .VQSHRNT = { 1613, 1}, + .VQRSHRNB = { 1614, 1}, + .VQRSHRNT = { 1615, 1}, + .VQSHRUNB = { 1616, 1}, + .VQSHRUNT = { 1617, 1}, + .VQRSHRUNB = { 1618, 1}, + .VQRSHRUNT = { 1619, 1}, + .VQDMLADH = { 1620, 1}, + .VQDMLADHX = { 1621, 1}, + .VQDMLSDH = { 1622, 1}, + .VQDMLSDHX = { 1623, 1}, + .VQRDMLADH = { 1624, 1}, + .VQRDMLADHX = { 1625, 1}, + .VQRDMLSDH = { 1626, 1}, + .VQRDMLSDHX = { 1627, 1}, + .VLDRB = { 1628, 2}, + .VLDRH = { 1630, 2}, + .VLDRW = { 1632, 2}, + .VLDRD = { 1634, 2}, + .VSTRB = { 1636, 2}, + .VSTRH = { 1638, 2}, + .VSTRW = { 1640, 2}, + .VSTRD = { 1642, 2}, + .VLD20 = { 1644, 1}, + .VLD21 = { 1645, 1}, + .VLD40 = { 1646, 1}, + .VLD41 = { 1647, 1}, + .VLD42 = { 1648, 1}, + .VLD43 = { 1649, 1}, + .VST20 = { 1650, 1}, + .VST21 = { 1651, 1}, + .VST40 = { 1652, 1}, + .VST41 = { 1653, 1}, + .VST42 = { 1654, 1}, + .VST43 = { 1655, 1}, + ._COUNT = { 1656, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 45e43b9dbfbd334414f4f6a95c2c2915b813462c..b9c14de52346f6219d1b0e22336c394554d4eafe 100644 GIT binary patch literal 10758 zcmc&&1-MmJ)1KUPH;8nHgh;1!UAnuwyA=r$1w=pu6buCE25F?bQ$Q3%Ku|y$vteH9QnKkbLKp7SaX!=^+DTgiMegGDDU? zKWk8DHpmWdK-Qq%9FP;-nOvqfH@pdXtmo-|%f@+aCLiR70#FbNL18EYMWGlJhZ68M zl!Q`H8p=RfCkae;5D*VNlS9!7v2g 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zzvp@S7qAkmuo}6uCSO~qS-i-5)?)*G8`}BKub?ALs530r4t8DG#k?Pf*!AZBuH5^M z@R_3+?Hmgo9cOo9l>N!DQWwIEzQagZEkCN#tZ2L%u{N5d?xq;3ny5tp diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index c626b48cf..b7b38dd1c 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -389,7 +389,7 @@ run_smoke :: proc() { check("VFMSL Q", .VFMSL, 1, 0xFCA00850, 0xFFB00F50) check("VCVT BF16", .VCVT, 10, 0xF3B60600, 0xFFBF0FD0) check("VDOT BF16 D", .VDOT, 0, 0xFC000D00, 0xFFB00F10) - check("VFMA BF16 Q", .VFMA, 9, 0xFC300850, 0xFFB00F50) + check("VFMA BF16 Q", .VFMA, 7, 0xFC300850, 0xFFB00F50) check("VMMLA BF16 Q", .VMMLA, 0, 0xFC000C40, 0xFFB00F50) // ---- Barriers / hints: ESB, PSB CSYNC, TSB CSYNC, CSDB, SB ---- @@ -513,8 +513,6 @@ run_smoke :: proc() { check("VQDMULL lane .S16",.VQDMULL, 2, 0xF2900B40, 0xFFB00F50) check("VQDMLAL lane .S32",.VQDMLAL, 3, 0xF2A00340, 0xFFB00F50) check("VQDMLSL lane", .VQDMLSL, 2, 0xF2900740, 0xFFB00F50) - check("VFMA lane D", .VFMA, 7, 0xF2A00040, 0xFFB00F50) - check("VFMS lane Q", .VFMS, 7, 0xF3A00440, 0xFFB00F50) check("VQRDMLAH lane", .VQRDMLAH, 4, 0xF2900E40, 0xFFB00F50) check("VQRDMLSH lane", .VQRDMLSH, 4, 0xF2900F40, 0xFFB00F50) check("VCMLA lane D", .VCMLA, 2, 0xFE000800, 0xFFB00F10) From 01bdf7522c6548ab0f59633b6ee206d722653923 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 08:59:47 -0400 Subject: [PATCH 26/89] rexcode/arm64: MRS/MSR printed the system register as a number `mrs x0, cntvct_el0` came back out of the disassembler as `mrs x0, #24322`. The 230 sysreg constants were already there and the encoding was byte-exact against llvm-mc -- the printer simply had no SYS_REG handling, so the packed 15-bit field printed as an immediate. Nothing an assembler would take back. Adds a value -> name table (sorted, binary searched) and prints that operand by name for MRS, and for the MSR form that takes one. MSR's other form holds a PSTATE field selector in the same slot, which is a different namespace; the two are told apart by whether the second operand is a register or an immediate. Six encodings carry two names, so a round-trip can come back spelled as the sibling; the first by source order wins. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/printer.odin | 36 ++++ core/rexcode/isa/arm64/sysregs.odin | 262 ++++++++++++++++++++++++++++ 2 files changed, 298 insertions(+) diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index e0ddea32a..85d8c21c9 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -118,6 +118,20 @@ sbprint :: proc( // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), // which assemblers write as `lsl #16` and omit entirely when it is zero. + // MRS/MSR carry the system register as a packed field, so it has to be + // printed by name -- a bare number is not something an assembler takes. + // MSR's other form takes a PSTATE field selector in the same slot, + // which is a different namespace; it is the one whose second operand + // is an immediate rather than a register. + sysreg_slot, sysreg_ok := -1, false + #partial switch inst.mnemonic { + case .MRS: + sysreg_slot, sysreg_ok = 1, inst.operand_count >= 2 + case .MSR: + sysreg_slot = 0 + sysreg_ok = inst.operand_count >= 2 && inst.ops[1].kind == .REGISTER + } + mov_wide := inst.mnemonic == .MOVZ || inst.mnemonic == .MOVN || inst.mnemonic == .MOVK end_slot := int(inst.operand_count) if mov_wide && end_slot == 3 && inst.ops[2].kind == .IMMEDIATE && inst.ops[2].immediate == 0 { @@ -134,6 +148,8 @@ sbprint :: proc( if mov_wide && slot == 2 { strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) + } else if slot == sysreg_slot && sysreg_ok { + write_sysreg(sb, inst.ops[slot].immediate, opts.uppercase) } else { write_operand(sb, &inst.ops[slot], &display, opts) } @@ -340,6 +356,26 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { // NOTE: an element-indexed operand still prints as `v0.s` -- the lane index // rides in a separate immediate operand, so `v0.s[2]` needs the printer to // fold that operand into this one, which it does not yet do. +// A system register by name (`cntvct_el0`), falling back to the raw field +// when it is not one we know. +@(private="file") +write_sysreg :: proc(sb: ^strings.Builder, value: i64, uppercase: bool) { + name, ok := sysreg_name(value) + if !ok { + strings.write_byte(sb, '#') + write_signed_decimal(sb, value) + return + } + for i in 0 ..< len(name) { + c := name[i] + if uppercase && c >= 'a' && c <= 'z' { + strings.write_byte(sb, c - 'a' + 'A') + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { shape := "" diff --git a/core/rexcode/isa/arm64/sysregs.odin b/core/rexcode/isa/arm64/sysregs.odin index 32522a820..0e142edf4 100644 --- a/core/rexcode/isa/arm64/sysregs.odin +++ b/core/rexcode/isa/arm64/sysregs.odin @@ -405,3 +405,265 @@ MFAR_EL3 :: i64(0x7305) // 3 6 6 0 5 (Multiple FAR) // ---- Performance Monitor extras ---- PMCCFILTR_EL0 :: i64(0x5F7F) // 3 3 14 15 7 PMUSERENR_EL0_REPEAT :: PMUSERENR_EL0 // re-export alias placeholder + +// ----------------------------------------------------------------------------- +// Value -> name, for printing +// ----------------------------------------------------------------------------- +// +// MRS/MSR carry the system register as a packed 15-bit field, so a disassembly +// has a number where an assembler wants a name. Sorted by value; binary search. +// +// Six encodings have two names (a read view and a write view, or an alias +// added by a later extension); the first by source order wins, so a round-trip +// can come back spelled as the sibling. + +Sysreg_Name :: struct { + value: u16, + name: string, +} + +@(rodata) +SYSREG_NAMES := [?]Sysreg_Name{ + {0x0010, "mdccint_el1"}, + {0x0012, "mdscr_el1"}, + {0x0084, "oslar_el1"}, + {0x008C, "oslsr_el1"}, + {0x1080, "mdrar_el1"}, + {0x1A20, "dbgdtr_el0"}, + {0x1A28, "dbgdtrrx_el0"}, + {0x1BC6, "dbgclaimset_el1"}, + {0x1BCE, "dbgclaimclr_el1"}, + {0x1BF6, "dbgauthstatus_el1"}, + {0x4000, "midr_el1"}, + {0x4005, "mpidr_el1"}, + {0x4008, "id_pfr0_el1"}, + {0x4009, "id_pfr1_el1"}, + {0x400A, "id_dfr0_el1"}, + {0x400B, "id_afr0_el1"}, + {0x400C, "id_mmfr0_el1"}, + {0x400D, "id_mmfr1_el1"}, + {0x400E, "id_mmfr2_el1"}, + {0x400F, "id_mmfr3_el1"}, + {0x4010, "id_isar0_el1"}, + {0x4011, "id_isar1_el1"}, + {0x4012, "id_isar2_el1"}, + {0x4013, "id_isar3_el1"}, + {0x4014, "id_isar4_el1"}, + {0x4015, "id_isar5_el1"}, + {0x4017, "id_isar6_el1"}, + {0x4018, "mvfr0_el1"}, + {0x4019, "mvfr1_el1"}, + {0x401A, "mvfr2_el1"}, + {0x4020, "id_aa64pfr0_el1"}, + {0x4021, "id_aa64pfr1_el1"}, + {0x4024, "id_aa64zfr0_el1"}, + {0x4025, "id_aa64smfr0_el1"}, + {0x4028, "id_aa64dfr0_el1"}, + {0x4029, "id_aa64dfr1_el1"}, + {0x402A, "id_aa64dfr2_el1"}, + {0x402C, "id_aa64afr0_el1"}, + {0x402D, "id_aa64afr1_el1"}, + {0x402E, "id_mmfr5_el1"}, + {0x4030, "id_aa64isar0_el1"}, + {0x4031, "id_aa64isar1_el1"}, + {0x4032, "id_aa64isar2_el1"}, + {0x4033, "id_aa64isar3_el1"}, + {0x4036, "id_mmfr4_el1"}, + {0x4038, "id_aa64mmfr0_el1"}, + {0x4039, "id_aa64mmfr1_el1"}, + {0x403A, "id_aa64mmfr2_el1"}, + {0x4080, "sctlr_el1"}, + {0x4081, "actlr_el1"}, + {0x4082, "cpacr_el1"}, + {0x4100, "ttbr0_el1"}, + {0x4101, "ttbr1_el1"}, + {0x4200, "spsr_el1"}, + {0x4201, "elr_el1"}, + {0x4208, "sp_el0"}, + {0x4212, "current_el"}, + {0x4282, "tcr_el1"}, + {0x4288, "afsr0_el1"}, + {0x4289, "afsr1_el1"}, + {0x4290, "zcr_el1"}, + {0x4296, "smcr_el1"}, + {0x4298, "erridr_el1"}, + {0x4299, "errselr_el1"}, + {0x42A0, "erxfr_el1"}, + {0x42A1, "erxctlr_el1"}, + {0x42A2, "erxstatus_el1"}, + {0x42A3, "erxaddr_el1"}, + {0x42A8, "erxmisc0_el1"}, + {0x42A9, "erxmisc1_el1"}, + {0x42AA, "erxmisc2_el1"}, + {0x42AB, "erxmisc3_el1"}, + {0x4300, "tfsr_el1"}, + {0x4301, "tfsre0_el1"}, + {0x4318, "apiakeylo_el1"}, + {0x4319, "apiakeyhi_el1"}, + {0x431A, "apibkeylo_el1"}, + {0x431B, "apibkeyhi_el1"}, + {0x4320, "apdakeylo_el1"}, + {0x4321, "apdakeyhi_el1"}, + {0x4322, "apdbkeylo_el1"}, + {0x4323, "apdbkeyhi_el1"}, + {0x4328, "apgakeylo_el1"}, + {0x4329, "apgakeyhi_el1"}, + {0x4380, "par_el1"}, + {0x4510, "mair_el1"}, + {0x4518, "amair_el1"}, + {0x4520, "lorsa_el1"}, + {0x4521, "lorea_el1"}, + {0x4522, "lorn_el1"}, + {0x4523, "lorc_el1"}, + {0x4527, "lorid_el1"}, + {0x4600, "vbar_el1"}, + {0x4608, "isr_el1"}, + {0x4609, "disr_el1"}, + {0x4630, "icc_pmr_el1"}, + {0x4681, "contextidr_el1"}, + {0x4684, "tpidr_el1"}, + {0x4708, "cntkctl_el1"}, + {0x4800, "ccsidr_el1"}, + {0x4801, "clidr_el1"}, + {0x4804, "gmid_el1"}, + {0x4948, "pmscr_el1"}, + {0x494A, "pmsicr_el1"}, + {0x494B, "pmsirr_el1"}, + {0x494C, "pmsfcr_el1"}, + {0x494D, "pmsevfr_el1"}, + {0x494E, "pmslatfr_el1"}, + {0x494F, "pmsidr_el1"}, + {0x4950, "pmblimitr_el1"}, + {0x4951, "pmbptr_el1"}, + {0x4953, "pmbsr_el1"}, + {0x4957, "pmbidr_el1"}, + {0x4B90, "trblimitr_el1"}, + {0x4B91, "trbptr_el1"}, + {0x4B92, "trbbaser_el1"}, + {0x4B93, "trbsr_el1"}, + {0x4B94, "trbmar_el1"}, + {0x4B96, "trbtrg_el1"}, + {0x4B97, "trbidr_el1"}, + {0x4C40, "icc_iar0_el1"}, + {0x4C41, "icc_eoir0_el1"}, + {0x4C42, "icc_hppir0_el1"}, + {0x4C43, "icc_bpr0_el1"}, + {0x4C59, "icc_dir_el1"}, + {0x4C5B, "icc_rpr_el1"}, + {0x4C60, "icc_iar1_el1"}, + {0x4C61, "icc_eoir1_el1"}, + {0x4C62, "icc_hppir1_el1"}, + {0x4C63, "icc_bpr1_el1"}, + {0x4C64, "icc_ctlr_el1"}, + {0x4C65, "icc_sre_el1"}, + {0x4C66, "icc_igrpen0_el1"}, + {0x4C67, "icc_igrpen1_el1"}, + {0x4CE1, "pmintenset_el1"}, + {0x4CE2, "pmintenclr_el1"}, + {0x5000, "csselr_el1"}, + {0x5290, "esr_el1"}, + {0x5300, "far_el1"}, + {0x5801, "ctr_el0"}, + {0x5807, "dczid_el0"}, + {0x5920, "rndr"}, + {0x5921, "rndrrs"}, + {0x5A10, "nzcv"}, + {0x5A11, "daif"}, + {0x5A20, "fpcr"}, + {0x5A21, "fpsr"}, + {0x5A22, "svcr"}, + {0x5A28, "dspsr_el0"}, + {0x5A29, "dlr_el0"}, + {0x5CDD, "icc_sgi1r_el1"}, + {0x5CDE, "icc_asgi1r_el1"}, + {0x5CDF, "icc_sgi0r_el1"}, + {0x5CE0, "pmcr_el0"}, + {0x5CE1, "pmcntenset_el0"}, + {0x5CE2, "pmcntenclr_el0"}, + {0x5CE3, "pmovsclr_el0"}, + {0x5CE4, "pmswinc_el0"}, + {0x5CE5, "pmselr_el0"}, + {0x5CE6, "pmceid0_el0"}, + {0x5CE7, "pmceid1_el0"}, + {0x5CE8, "pmccntr_el0"}, + {0x5CF0, "pmuserenr_el0"}, + {0x5E82, "tpidr_el0"}, + {0x5E83, "tpidrro_el0"}, + {0x5E85, "tpidr2_el0"}, + {0x5F00, "cntfrq_el0"}, + {0x5F01, "cntpct_el0"}, + {0x5F02, "cntvct_el0"}, + {0x5F10, "cntp_tval_el0"}, + {0x5F11, "cntp_ctl_el0"}, + {0x5F12, "cntp_cval_el0"}, + {0x5F18, "cntv_tval_el0"}, + {0x5F19, "cntv_ctl_el0"}, + {0x5F1A, "cntv_cval_el0"}, + {0x5F7F, "pmccfiltr_el0"}, + {0x6080, "sctlr_el2"}, + {0x6088, "hcr_el2"}, + {0x6089, "mdcr_el2"}, + {0x608B, "hstr_el2"}, + {0x6108, "vttbr_el2"}, + {0x610A, "vtcr_el2"}, + {0x6180, "dacr32_el2"}, + {0x6200, "spsr_el2"}, + {0x6201, "elr_el2"}, + {0x6208, "sp_el1"}, + {0x628B, "vsesr_el2"}, + {0x6290, "esr_el2"}, + {0x6296, "smcr_el2"}, + {0x6298, "fpexc32_el2"}, + {0x6300, "far_el2"}, + {0x6600, "vbar_el2"}, + {0x6609, "vdisr_el2"}, + {0x6708, "cnthctl_el2"}, + {0x6710, "cnthp_tval_el2"}, + {0x6711, "cnthp_ctl_el2"}, + {0x6712, "cnthp_cval_el2"}, + {0x6718, "cnthv_tval_el2"}, + {0x6719, "cnthv_ctl_el2"}, + {0x671A, "cnthv_cval_el2"}, + {0x671B, "cntvoff_el2"}, + {0x6C65, "icc_sre_el2"}, + {0x6CD8, "ich_hcr_el2"}, + {0x6CD9, "ich_vtr_el2"}, + {0x6CDA, "ich_misr_el2"}, + {0x6CDB, "ich_eisr_el2"}, + {0x6CDD, "ich_elrsr_el2"}, + {0x6CDF, "ich_vmcr_el2"}, + {0x6E82, "tpidr_el2"}, + {0x7080, "sctlr_el3"}, + {0x70B4, "gptbr_el3"}, + {0x70B6, "gpccr_el3"}, + {0x7200, "spsr_el3"}, + {0x7201, "elr_el3"}, + {0x7290, "zcr_el3"}, + {0x7305, "mfar_el3"}, + {0x7600, "vbar_el3"}, + {0x7682, "tpidr_el3"}, + {0x7C64, "icc_ctlr_el3"}, + {0x7C65, "icc_sre_el3"}, + {0x7C67, "icc_igrpen1_el3"}, + {0x7F10, "cntps_tval_el1"}, + {0x7F11, "cntps_ctl_el1"}, + {0x7F12, "cntps_cval_el1"}, +} + +// Name for a packed system-register field, or ok=false when it is not one we +// know -- callers should fall back to printing the raw immediate. +@(require_results) +sysreg_name :: proc "contextless" (value: i64) -> (name: string, ok: bool) { + v := u16(value & 0x7FFF) + lo, hi := 0, len(SYSREG_NAMES) - 1 + for lo <= hi { + mid := (lo + hi) / 2 + e := SYSREG_NAMES[mid] + switch { + case e.value == v: return e.name, true + case e.value < v: lo = mid + 1 + case: hi = mid - 1 + } + } + return "", false +} From 5627cc94d6fe9cef57f5c4ca533dcd4e9a44b5d5 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 08:59:59 -0400 Subject: [PATCH 27/89] rexcode/arm64: add the cset/csetm/cinc/cinv/cneg aliases These are what an assembler writes -- and what one prints back -- for CSINC/CSINV/CSNEG with the condition inverted, and none of the five existed. A disassembly of `cset w0, eq` came out as `csinc w0, wzr, wzr, ne`. Two constraints the table could not state before: - The condition is stored inverted, so COND_HI_INV packs `cond ~ 1` and reads it back the same way. The printer needs nothing; the decoder hands it a plain condition operand. - cinc/cinv/cneg are only the alias when Rn == Rm, which is a cross-field equality no mask expresses. One operand fills both slots on the way in (RN_RM), and decode checks the two fields agree before accepting the entry -- reached only on a mask match, so it costs nothing in the scan. The aliases also require cond != 111x. That one *is* expressible: the 14 legal values are covered exactly by three masked patterns (0xxx, 10xx, 110x), so AL and NV fall through to the underlying instruction the way llvm-mc does. COND_NOT_AL rejects them on the encode side. Verified against llvm-mc across all five mnemonics, both widths and all 14 conditions: 140/140 of our printed strings assemble to exactly our bytes. Disassembly agrees except for cs/hs and cc/lo, which is the package's existing spelling of those two conditions and shows up on CSEL and B.cond alike. AL/NV and Rn != Rm both fall through correctly. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 12 +- core/rexcode/isa/arm64/encoder.odin | 8 + core/rexcode/isa/arm64/encoding_types.odin | 8 + core/rexcode/isa/arm64/mnemonic_builders.odin | 20 + core/rexcode/isa/arm64/mnemonics.odin | 4 + .../tablegen/generated/decode_tables.odin | 1384 +++++++------- .../tablegen/generated/encode_tables.odin | 1623 +++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 40 + .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 34524 -> 34944 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49320 -> 49920 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6528 -> 6568 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49360 -> 49960 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes .../arm64/tools/gen_mnemonic_builders.odin | 2 +- 14 files changed, 1648 insertions(+), 1453 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 10c0eb37e..057065941 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -96,6 +96,14 @@ decode_one_inline :: #force_inline proc "contextless" ( for i in 0..> 16) & 0x1F) != ((word >> 5) & 0x1F) { + continue + } matched_idx = base + i break } @@ -142,7 +150,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- Register slots ---------------------------------------------------- case .RD, .RT: return reg_from_field(word, 0, ot) - case .RN: + case .RN, .RN_RM: return reg_from_field(word, 5, ot) case .RT2, .RA: return reg_from_field(word, 10, ot) @@ -188,6 +196,8 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .EXT_IMM3: return Operand{immediate = i64((word >> 10) & 0x7), kind = .IMMEDIATE, size = 1} case .COND_HI: return Operand{cond = u8((word >> 12) & 0xF), kind = .COND, size = 1} + case .COND_HI_INV: + return Operand{cond = u8(((word >> 12) & 0xF) ~ 1), kind = .COND, size = 1} case .COND_LO: return Operand{cond = u8(word & 0xF), kind = .COND, size = 1} case .NZCV_FIELD: diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 304311f25..5c567489d 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -311,6 +311,8 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .MEMORY && op.mem.mode == .OFFSET && reg_class(op.mem.base) == REG_Z case .COND: return op.kind == .COND + case .COND_NOT_AL: + return op.kind == .COND && (op.cond & 0xE) != 0xE } return false } @@ -367,6 +369,9 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0x1F) << 0 case .RN: return (u32(reg_hw(op.reg)) & 0x1F) << 5 + case .RN_RM: + r := u32(reg_hw(op.reg)) & 0x1F + return (r << 5) | (r << 16) case .RT2, .RA: return (u32(reg_hw(op.reg)) & 0x1F) << 10 case .RM: @@ -403,6 +408,9 @@ pack_operand_inline :: #force_inline proc( // Condition payload may arrive as IMMEDIATE (raw) or COND kind. c := u32(op.cond) if op.kind == .COND else u32(op.immediate) return (c & 0xF) << 12 + case .COND_HI_INV: + c := u32(op.cond) if op.kind == .COND else u32(op.immediate) + return ((c ~ 1) & 0xF) << 12 case .COND_LO: c := u32(op.cond) if op.kind == .COND else u32(op.immediate) return (c & 0xF) << 0 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 9b7353c7c..a4fe99f41 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -186,6 +186,10 @@ Operand_Type :: enum u8 { // ---- Condition code ---- COND, + // Condition with AL/NV excluded. The cset/cinc alias family is only the + // preferred spelling when cond != 111x -- with AL or NV the underlying + // CSINC/CSINV/CSNEG is what an assembler writes. + COND_NOT_AL, // ---- NEON shift-by-immediate amount (encoded into immh:immb together // with the element size: left = esize+shift, right = 2*esize-shift) ---- @@ -208,6 +212,8 @@ Operand_Encoding :: enum u8 { RT2, // bits 10-14 RA, // bits 10-14 (alias of RT2 used in MADD/MSUB) RM, // bits 16-20 + RN_RM, // bits 5-9 AND 16-20 -- one register into both source + // slots (cinc/cinv/cneg, whose alias condition is Rn==Rm) // ---- Immediates ---- IMM12, // bits 10-21 @@ -227,6 +233,8 @@ Operand_Encoding :: enum u8 { EXT_OPT, // bits 13-15 (extend type for extended-register) EXT_IMM3, // bits 10-12 (extend amount) COND_HI, // bits 12-15 (CSEL/CSINC/CSINV/CSNEG, FCSEL, CCMP) + COND_HI_INV, // bits 12-15, stored inverted -- the cset/cinc aliases + // read as `cset Wd, eq` but encode CSINC's cond as NE COND_LO, // bits 0-3 (B.cond) NZCV_FIELD, // bits 0-3 (CCMP/CCMN immediate NZCV) SYS_FIELD, // bits 5-19 (MRS/MSR: op0/op1/CRn/CRm/op2) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index eea626f79..113adcf76 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -209,6 +209,16 @@ inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } +inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +emit_cset_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_cset_r_c(dst, cond)) } +inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +emit_csetm_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_csetm_r_c(dst, cond)) } +inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cinc_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinc_r_r_c(dst, src, cond)) } +inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cinv_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinv_r_r_c(dst, src, cond)) } +inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cneg_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cneg_r_r_c(dst, src, cond)) } inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } @@ -2086,6 +2096,16 @@ inst_ccmp :: proc{ inst_ccmp_r_r_i_c, inst_ccmp_r_i_i_c } emit_ccmp :: proc{ emit_ccmp_r_r_i_c, emit_ccmp_r_i_i_c } inst_ccmn :: proc{ inst_ccmn_r_r_i_c, inst_ccmn_r_i_i_c } emit_ccmn :: proc{ emit_ccmn_r_r_i_c, emit_ccmn_r_i_i_c } +inst_cset :: inst_cset_r_c +emit_cset :: emit_cset_r_c +inst_csetm :: inst_csetm_r_c +emit_csetm :: emit_csetm_r_c +inst_cinc :: inst_cinc_r_r_c +emit_cinc :: emit_cinc_r_r_c +inst_cinv :: inst_cinv_r_r_c +emit_cinv :: emit_cinv_r_r_c +inst_cneg :: inst_cneg_r_r_c +emit_cneg :: emit_cneg_r_r_c inst_extr :: inst_extr_r_r_r_i emit_extr :: emit_extr_r_r_r_i inst_b :: inst_b_l diff --git a/core/rexcode/isa/arm64/mnemonics.odin b/core/rexcode/isa/arm64/mnemonics.odin index 7825c8564..6aae469af 100644 --- a/core/rexcode/isa/arm64/mnemonics.odin +++ b/core/rexcode/isa/arm64/mnemonics.odin @@ -69,6 +69,10 @@ Mnemonic :: enum u16 { CSEL, CSINC, CSINV, CSNEG, CCMP, CCMN, + // Aliases of the above with the condition inverted; every assembler both + // accepts and prefers these spellings. + CSET, CSETM, // CSINC/CSINV with Rn = Rm = ZR + CINC, CINV, CNEG, // CSINC/CSINV/CSNEG with Rn = Rm // ------------------------------------------------------------------------- // Extract diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 1ceeea50f..e01c4b843 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2468]lib.Decode_Entry{ +DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -44,12 +44,12 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, @@ -62,14 +62,14 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, @@ -97,27 +97,27 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, @@ -130,27 +130,27 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, @@ -158,30 +158,30 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -192,97 +192,97 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -318,19 +318,19 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, @@ -340,48 +340,48 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, @@ -429,104 +429,104 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, @@ -563,8 +563,8 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {explicit_count=4} }, { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, @@ -575,15 +575,15 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -592,16 +592,16 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, - { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, @@ -610,14 +610,14 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, @@ -626,35 +626,35 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, @@ -666,10 +666,10 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, @@ -720,25 +720,25 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, @@ -759,11 +759,11 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -785,69 +785,69 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -855,45 +855,45 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, @@ -903,230 +903,230 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, 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{.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, @@ -1147,22 +1147,22 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1173,18 +1173,18 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1209,8 +1209,8 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1227,38 +1227,38 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -1266,190 +1266,190 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1457,265 +1457,265 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, 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.SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1745,49 +1745,49 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, @@ -1807,14 +1807,14 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, @@ -1996,10 +1996,10 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, - { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, - { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, @@ -2027,38 +2027,38 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, @@ -2069,79 +2069,79 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, 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explicit_count=3} }, + { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, 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{.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 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0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, @@ -2163,20 +2163,20 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2187,8 +2187,8 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, @@ -2200,6 +2200,18 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -2221,8 +2233,8 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, @@ -2250,14 +2262,26 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, - { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, @@ -2266,6 +2290,12 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, @@ -2285,170 +2315,170 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, - { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, 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{.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -2463,20 +2493,20 @@ DECODE_ENTRIES := [2468]lib.Decode_Entry{ { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, } @(rodata) @@ -2492,8 +2522,8 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x0A = {1863, 130}, 0x0B = {1993, 21}, 0x0C = {2014, 167}, - 0x0D = {2181, 92}, - 0x0E = {2273, 19}, - 0x0F = {2292, 176}, + 0x0D = {2181, 122}, + 0x0E = {2303, 19}, + 0x0F = {2322, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 045c5d064..f0feb9801 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2466]lib.Encoding{ +ENCODE_FORMS := [2496]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -265,6 +265,41 @@ ENCODE_FORMS := [2466]lib.Encoding{ { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + // .CSET + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + // .CSETM + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + // .CINC + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + // .CINV + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + // .CNEG + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .EXTR { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, @@ -3293,7 +3328,7 @@ ENCODE_FORMS := [2466]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2466]lib.Clobber{ +CLOBBER_FORMS := [2496]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -3550,6 +3585,41 @@ CLOBBER_FORMS := [2466]lib.Clobber{ {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}, + // .CSET + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + // .CSETM + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, nzcv_rd={.N, .Z, .C, .V}}, + // .CINC + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + // .CINV + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + // .CNEG + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, + {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}, // .EXTR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -6623,776 +6693,781 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .CSNEG = { 203, 2}, .CCMP = { 205, 4}, .CCMN = { 209, 4}, - .EXTR = { 213, 2}, - .B = { 215, 1}, - .BL = { 216, 1}, - .BR = { 217, 1}, - .BLR = { 218, 1}, - .RET = { 219, 2}, - .B_EQ = { 221, 1}, - .B_NE = { 222, 1}, - .B_CS = { 223, 1}, - .B_CC = { 224, 1}, - .B_MI = { 225, 1}, - .B_PL = { 226, 1}, - .B_VS = { 227, 1}, - .B_VC = { 228, 1}, - .B_HI = { 229, 1}, - .B_LS = { 230, 1}, - .B_GE = { 231, 1}, - .B_LT = { 232, 1}, - .B_GT = { 233, 1}, - .B_LE = { 234, 1}, - .B_AL = { 235, 1}, - .B_NV = { 236, 1}, - .CBZ = { 237, 2}, - .CBNZ = { 239, 2}, - .TBZ = { 241, 1}, - .TBNZ = { 242, 1}, - .LDR = { 243, 18}, - .STR = { 261, 16}, - .LDRB = { 277, 4}, - .STRB = { 281, 4}, - .LDRSB = { 285, 4}, - .LDRH = { 289, 4}, - .STRH = { 293, 4}, - .LDRSH = { 297, 4}, - .LDRSW = { 301, 2}, - .LDP = { 303, 9}, - .STP = { 312, 9}, - .LDPSW = { 321, 3}, - .LDAR = { 324, 2}, - .STLR = { 326, 2}, - .LDARB = { 328, 1}, - .STLRB = { 329, 1}, - .LDARH = { 330, 1}, - .STLRH = { 331, 1}, - .LDXR = { 332, 2}, - .STXR = { 334, 2}, - .LDAXR = { 336, 2}, - .STLXR = { 338, 2}, - .NOP = { 340, 1}, - .YIELD = { 341, 1}, - .WFE = { 342, 1}, - .WFI = { 343, 1}, - .SEV = { 344, 1}, - .SEVL = { 345, 1}, - .HINT = { 346, 1}, - .MRS = { 347, 1}, - .MSR = { 348, 2}, - .ISB = { 350, 1}, - .DSB = { 351, 1}, - .DMB = { 352, 1}, - .SVC = { 353, 1}, - .HVC = { 354, 1}, - .SMC = { 355, 1}, - .BRK = { 356, 1}, - .HLT = { 357, 1}, - .ERET = { 358, 1}, - .FMOV = { 359, 15}, - .FABS = { 374, 11}, - .FNEG = { 385, 11}, - .FSQRT = { 396, 11}, - .FADD = { 407, 12}, - .FSUB = { 419, 12}, - .FMUL = { 431, 12}, - .FDIV = { 443, 9}, - .FNMUL = { 452, 3}, - .FMADD = { 455, 3}, - .FMSUB = { 458, 3}, - .FNMADD = { 461, 3}, - .FNMSUB = { 464, 3}, - .FCMP = { 467, 3}, - .FCMPE = { 470, 3}, - .FCSEL = { 473, 3}, - .FMAX = { 476, 11}, - .FMIN = { 487, 11}, - .FMAXNM = { 498, 11}, - .FMINNM = { 509, 11}, - .FCVT = { 520, 6}, - .SCVTF = { 526, 10}, - .UCVTF = { 536, 10}, - .FCVTZS = { 546, 10}, - .FCVTZU = { 556, 10}, - .FCVTAS = { 566, 11}, - .FCVTAU = { 577, 11}, - .FCVTNS = { 588, 11}, - .FCVTNU = { 599, 11}, - .FCVTPS = { 610, 11}, - .FCVTPU = { 621, 11}, - .FCVTMS = { 632, 11}, - .FCVTMU = { 643, 11}, - .FRINTA = { 654, 11}, - .FRINTI = { 665, 11}, - .FRINTM = { 676, 11}, - .FRINTN = { 687, 11}, - .FRINTP = { 698, 11}, - .FRINTX = { 709, 11}, - .FRINTZ = { 720, 11}, - .TST = { 731, 4}, - .LDUR = { 735, 5}, - .STUR = { 740, 5}, - .LDURB = { 745, 1}, - .STURB = { 746, 1}, - .LDURSB = { 747, 2}, - .LDURH = { 749, 1}, - .STURH = { 750, 1}, - .LDURSH = { 751, 2}, - .LDURSW = { 753, 1}, - .LDNP = { 754, 2}, - .STNP = { 756, 2}, - .LDXP = { 758, 2}, - .STXP = { 760, 2}, - .LDAXP = { 762, 2}, - .STLXP = { 764, 2}, - .LDXRB = { 766, 1}, - .STXRB = { 767, 1}, - .LDAXRB = { 768, 1}, - .STLXRB = { 769, 1}, - .LDXRH = { 770, 1}, - .STXRH = { 771, 1}, - .LDAXRH = { 772, 1}, - .STLXRH = { 773, 1}, - .LDAPR = { 774, 2}, - .LDAPRB = { 776, 1}, - .LDAPRH = { 777, 1}, - .LDADD = { 778, 2}, - .LDADDA = { 780, 2}, - .LDADDL = { 782, 2}, - .LDADDAL = { 784, 2}, - .LDCLR = { 786, 2}, - .LDCLRA = { 788, 2}, - .LDCLRL = { 790, 2}, - .LDCLRAL = { 792, 2}, - .LDEOR = { 794, 2}, - .LDEORA = { 796, 2}, - .LDEORL = { 798, 2}, - .LDEORAL = { 800, 2}, - .LDSET = { 802, 2}, - .LDSETA = { 804, 2}, - .LDSETL = { 806, 2}, - .LDSETAL = { 808, 2}, - .LDSMAX = { 810, 2}, - .LDSMAXA = { 812, 2}, - .LDSMAXL = { 814, 2}, - .LDSMAXAL = { 816, 2}, - .LDSMIN = { 818, 2}, - .LDSMINA = { 820, 2}, - .LDSMINL = { 822, 2}, - .LDSMINAL = { 824, 2}, - .LDUMAX = { 826, 2}, - .LDUMAXA = { 828, 2}, - .LDUMAXL = { 830, 2}, - .LDUMAXAL = { 832, 2}, - .LDUMIN = { 834, 2}, - .LDUMINA = { 836, 2}, - .LDUMINL = { 838, 2}, - .LDUMINAL = { 840, 2}, - .SWP = { 842, 2}, - .SWPA = { 844, 2}, - .SWPL = { 846, 2}, - .SWPAL = { 848, 2}, - .CAS = { 850, 2}, - .CASA = { 852, 2}, - .CASL = { 854, 2}, - .CASAL = { 856, 2}, - .CASB = { 858, 1}, - .CASAB = { 859, 1}, - .CASLB = { 860, 1}, - .CASALB = { 861, 1}, - .CASH = { 862, 1}, - .CASAH = { 863, 1}, - .CASLH = { 864, 1}, - .CASALH = { 865, 1}, - .CASP = { 866, 2}, - .CASPA = { 868, 2}, - .CASPL = { 870, 2}, - .CASPAL = { 872, 2}, - .PACIA = { 874, 1}, - .PACIB = { 875, 1}, - .PACDA = { 876, 1}, - .PACDB = { 877, 1}, - .PACIZA = { 878, 1}, - .PACIZB = { 879, 1}, - .PACDZA = { 880, 1}, - .PACDZB = { 881, 1}, - .AUTIA = { 882, 1}, - .AUTIB = { 883, 1}, - .AUTDA = { 884, 1}, - .AUTDB = { 885, 1}, - .AUTIZA = { 886, 1}, - .AUTIZB = { 887, 1}, - .AUTDZA = { 888, 1}, - .AUTDZB = { 889, 1}, - .PACIASP = { 890, 1}, - .PACIBSP = { 891, 1}, - .AUTIASP = { 892, 1}, - .AUTIBSP = { 893, 1}, - .PACIA1716 = { 894, 1}, - .PACIB1716 = { 895, 1}, - .AUTIA1716 = { 896, 1}, - .AUTIB1716 = { 897, 1}, - .PACGA = { 898, 1}, - .XPACI = { 899, 1}, - .XPACD = { 900, 1}, - .XPACLRI = { 901, 1}, - .RETAA = { 902, 1}, - .RETAB = { 903, 1}, - .BRAA = { 904, 1}, - .BRAB = { 905, 1}, - .BRAAZ = { 906, 1}, - .BRABZ = { 907, 1}, - .BLRAA = { 908, 1}, - .BLRAB = { 909, 1}, - .BLRAAZ = { 910, 1}, - .BLRABZ = { 911, 1}, - .ERETAA = { 912, 1}, - .ERETAB = { 913, 1}, - .BTI = { 914, 1}, - .IRG = { 915, 1}, - .ADDG = { 916, 1}, - .SUBG = { 917, 1}, - .GMI = { 918, 1}, - .SUBP = { 919, 1}, - .SUBPS = { 920, 1}, - .LDG = { 921, 1}, - .STG = { 922, 1}, - .ST2G = { 923, 1}, - .STZG = { 924, 1}, - .STZ2G = { 925, 1}, - .STGP = { 926, 1}, - .LDGM = { 927, 1}, - .STGM = { 928, 1}, - .STZGM = { 929, 1}, - .CRC32B = { 930, 1}, - .CRC32H = { 931, 1}, - .CRC32W = { 932, 1}, - .CRC32X = { 933, 1}, - .CRC32CB = { 934, 1}, - .CRC32CH = { 935, 1}, - .CRC32CW = { 936, 1}, - .CRC32CX = { 937, 1}, - .AESE = { 938, 2}, - .AESD = { 940, 2}, - .AESMC = { 942, 2}, - .AESIMC = { 944, 2}, - .SHA1H = { 946, 1}, - .SHA1C = { 947, 1}, - .SHA1P = { 948, 1}, - .SHA1M = { 949, 1}, - .SHA1SU0 = { 950, 1}, - .SHA1SU1 = { 951, 1}, - .SHA256H = { 952, 1}, - .SHA256H2 = { 953, 1}, - .SHA256SU0 = { 954, 1}, - .SHA256SU1 = { 955, 1}, - .SHA512H = { 956, 1}, - .SHA512H2 = { 957, 1}, - .SHA512SU0 = { 958, 1}, - .SHA512SU1 = { 959, 1}, - .EOR3 = { 960, 2}, - .BCAX = { 962, 2}, - .RAX1 = { 964, 1}, - .XAR = { 965, 5}, - .SM3PARTW1 = { 970, 1}, - .SM3PARTW2 = { 971, 1}, - .SM3SS1 = { 972, 1}, - .SM3TT1A = { 973, 1}, - .SM3TT1B = { 974, 1}, - .SM3TT2A = { 975, 1}, - .SM3TT2B = { 976, 1}, - .SM4E = { 977, 1}, - .SM4EKEY = { 978, 1}, - .PMULL = { 979, 2}, - .PMULL2 = { 981, 2}, - .BFCVT = { 983, 2}, - .BFDOT = { 985, 1}, - .BFMMLA = { 986, 1}, - .BFMLALB = { 987, 1}, - .BFMLALT = { 988, 1}, - .BFCVTN = { 989, 1}, - .BFCVTN2 = { 990, 1}, - .MUL = { 991, 7}, - .MLA = { 998, 6}, - .MLS = { 1004, 6}, - .NEG = { 1010, 13}, - .ABS = { 1023, 11}, - .SHADD = { 1034, 6}, - .UHADD = { 1040, 6}, - .SHSUB = { 1046, 6}, - .UHSUB = { 1052, 6}, - .SRHADD = { 1058, 6}, - .URHADD = { 1064, 6}, - .SQADD = { 1070, 11}, - .UQADD = { 1081, 11}, - .SQSUB = { 1092, 11}, - .UQSUB = { 1103, 11}, - .SMAX = { 1114, 10}, - .UMAX = { 1124, 10}, - .SMIN = { 1134, 10}, - .UMIN = { 1144, 10}, - .SABD = { 1154, 10}, - .UABD = { 1164, 10}, - .SABA = { 1174, 6}, - .UABA = { 1180, 6}, - .ADDP = { 1186, 7}, - .ADDV = { 1193, 5}, - .SADDLP = { 1198, 6}, - .UADDLP = { 1204, 6}, - .SADALP = { 1210, 6}, - .UADALP = { 1216, 6}, - .SADDLV = { 1222, 5}, - .UADDLV = { 1227, 5}, - .SMAXV = { 1232, 5}, - .UMAXV = { 1237, 5}, - .SMINV = { 1242, 5}, - .UMINV = { 1247, 5}, - .SMAXP = { 1252, 6}, - .UMAXP = { 1258, 6}, - .SMINP = { 1264, 6}, - .UMINP = { 1270, 6}, - .SADDL = { 1276, 3}, - .SADDL2 = { 1279, 3}, - .UADDL = { 1282, 3}, - .UADDL2 = { 1285, 3}, - .SSUBL = { 1288, 3}, - .SSUBL2 = { 1291, 3}, - .USUBL = { 1294, 3}, - .USUBL2 = { 1297, 3}, - .SADDW = { 1300, 3}, - .SADDW2 = { 1303, 3}, - .UADDW = { 1306, 3}, - .UADDW2 = { 1309, 3}, - .SSUBW = { 1312, 3}, - .SSUBW2 = { 1315, 3}, - .USUBW = { 1318, 3}, - .USUBW2 = { 1321, 3}, - .RADDHN = { 1324, 3}, - .RADDHN2 = { 1327, 3}, - .RSUBHN = { 1330, 3}, - .RSUBHN2 = { 1333, 3}, - .ADDHN = { 1336, 3}, - .ADDHN2 = { 1339, 3}, - .SUBHN = { 1342, 3}, - .SUBHN2 = { 1345, 3}, - .XTN = { 1348, 3}, - .XTN2 = { 1351, 3}, - .SQXTN = { 1354, 3}, - .SQXTN2 = { 1357, 3}, - .UQXTN = { 1360, 3}, - .UQXTN2 = { 1363, 3}, - .SQXTUN = { 1366, 3}, - .SQXTUN2 = { 1369, 3}, - .SMULL = { 1372, 3}, - .SMULL2 = { 1375, 3}, - .UMULL = { 1378, 3}, - .UMULL2 = { 1381, 3}, - .SMLAL = { 1384, 3}, - .SMLAL2 = { 1387, 3}, - .UMLAL = { 1390, 3}, - .UMLAL2 = { 1393, 3}, - .SMLSL = { 1396, 3}, - .SMLSL2 = { 1399, 3}, - .UMLSL = { 1402, 3}, - .UMLSL2 = { 1405, 3}, - .SQDMULL = { 1408, 2}, - .SQDMULL2 = { 1410, 2}, - .SQDMLAL = { 1412, 2}, - .SQDMLAL2 = { 1414, 2}, - .SQDMLSL = { 1416, 2}, - .SQDMLSL2 = { 1418, 2}, - .SQDMULH = { 1420, 4}, - .SQRDMULH = { 1424, 4}, - .SDOT = { 1428, 2}, - .UDOT = { 1430, 2}, - .USDOT = { 1432, 2}, - .FMLA = { 1434, 8}, - .FMLS = { 1442, 8}, - .FMULX = { 1450, 5}, - .FMAXP = { 1455, 5}, - .FMINP = { 1460, 5}, - .FMAXNMP = { 1465, 5}, - .FMINNMP = { 1470, 5}, - .FMAXV = { 1475, 3}, - .FMINV = { 1478, 3}, - .FMAXNMV = { 1481, 3}, - .FMINNMV = { 1484, 3}, - .FRECPE = { 1487, 5}, - .FRSQRTE = { 1492, 5}, - .FRECPS = { 1497, 8}, - .FRSQRTS = { 1505, 8}, - .FRECPX = { 1513, 6}, - .FADDP = { 1519, 5}, - .FCVTL = { 1524, 2}, - .FCVTL2 = { 1526, 2}, - .FCVTN = { 1528, 2}, - .FCVTN2 = { 1530, 2}, - .FCVTXN = { 1532, 1}, - .FCVTXN2 = { 1533, 1}, - .FCMEQ = { 1534, 8}, - .FCMGE = { 1542, 8}, - .FCMGT = { 1550, 8}, - .FCMLE = { 1558, 8}, - .FCMLT = { 1566, 8}, - .FACGE = { 1574, 5}, - .FACGT = { 1579, 5}, - .CMEQ = { 1584, 4}, - .CMGE = { 1588, 7}, - .CMGT = { 1595, 2}, - .CMHI = { 1597, 2}, - .CMHS = { 1599, 7}, - .CMLE = { 1606, 7}, - .CMLT = { 1613, 7}, - .CMTST = { 1620, 7}, - .MVN = { 1627, 4}, - .BIT = { 1631, 1}, - .BIF = { 1632, 1}, - .BSL = { 1633, 2}, - .SHL = { 1635, 7}, - .SQSHL = { 1642, 7}, - .SQSHLU = { 1649, 7}, - .SRSHL = { 1656, 7}, - .URSHL = { 1663, 7}, - .SSHR = { 1670, 7}, - .USHR = { 1677, 7}, - .SSRA = { 1684, 7}, - .USRA = { 1691, 7}, - .SRSHR = { 1698, 7}, - .URSHR = { 1705, 7}, - .SRSRA = { 1712, 7}, - .URSRA = { 1719, 7}, - .SSHL = { 1726, 7}, - .USHL = { 1733, 7}, - .SLI = { 1740, 7}, - .SRI = { 1747, 7}, - .SSHLL = { 1754, 3}, - .SSHLL2 = { 1757, 3}, - .USHLL = { 1760, 3}, - .USHLL2 = { 1763, 3}, - .SXTL = { 1766, 3}, - .SXTL2 = { 1769, 3}, - .UXTL = { 1772, 3}, - .UXTL2 = { 1775, 3}, - .SHRN = { 1778, 3}, - .SHRN2 = { 1781, 3}, - .RSHRN = { 1784, 3}, - .RSHRN2 = { 1787, 3}, - .SQSHRN = { 1790, 3}, - .SQSHRN2 = { 1793, 3}, - .UQSHRN = { 1796, 3}, - .UQSHRN2 = { 1799, 3}, - .SQRSHRN = { 1802, 3}, - .SQRSHRN2 = { 1805, 3}, - .UQRSHRN = { 1808, 3}, - .UQRSHRN2 = { 1811, 3}, - .SQSHRUN = { 1814, 3}, - .SQSHRUN2 = { 1817, 3}, - .SQRSHRUN = { 1820, 3}, - .SQRSHRUN2 = { 1823, 3}, - .DUP = { 1826, 18}, - .INS = { 1844, 8}, - .MOV = { 1852, 12}, - .EXT = { 1864, 4}, - .TBL = { 1868, 6}, - .TBX = { 1874, 3}, - .ZIP1 = { 1877, 12}, - .ZIP2 = { 1889, 12}, - .UZP1 = { 1901, 12}, - .UZP2 = { 1913, 12}, - .TRN1 = { 1925, 12}, - .TRN2 = { 1937, 12}, - .NOT = { 1949, 3}, - .REV64 = { 1952, 6}, - .CNT = { 1958, 6}, - .URECPE = { 1964, 2}, - .URSQRTE = { 1966, 2}, - .MOVI = { 1968, 7}, - .MVNI = { 1975, 4}, - .LD1 = { 1979, 8}, - .LD2 = { 1987, 5}, - .LD3 = { 1992, 5}, - .LD4 = { 1997, 5}, - .ST1 = { 2002, 8}, - .ST2 = { 2010, 5}, - .ST3 = { 2015, 5}, - .ST4 = { 2020, 5}, - .LD1R = { 2025, 1}, - .LD2R = { 2026, 1}, - .LD3R = { 2027, 1}, - .LD4R = { 2028, 1}, - .SUBR = { 2029, 4}, - .ASRR = { 2033, 4}, - .LSLR = { 2037, 4}, - .LSRR = { 2041, 4}, - .FTSMUL = { 2045, 3}, - .FSUBR = { 2048, 3}, - .FDIVR = { 2051, 3}, - .FNMLA = { 2054, 3}, - .FNMLS = { 2057, 3}, - .NAND = { 2060, 1}, - .NOR = { 2061, 1}, - .SEL = { 2062, 1}, - .ORRS = { 2063, 1}, - .EORS = { 2064, 1}, - .NANDS = { 2065, 1}, - .NORS = { 2066, 1}, - .ORNS = { 2067, 1}, - .MOVS = { 2068, 1}, - .PTRUE = { 2069, 1}, - .PTRUES = { 2070, 1}, - .PFALSE = { 2071, 1}, - .PFIRST = { 2072, 1}, - .PNEXT = { 2073, 1}, - .BRKA = { 2074, 1}, - .BRKB = { 2075, 1}, - .BRKAS = { 2076, 1}, - .BRKBS = { 2077, 1}, - .BRKPA = { 2078, 1}, - .BRKPB = { 2079, 1}, - .BRKN = { 2080, 1}, - .RDFFR = { 2081, 1}, - .WRFFR = { 2082, 1}, - .SETFFR = { 2083, 1}, - .CMPEQ = { 2084, 4}, - .CMPNE = { 2088, 4}, - .CMPGE = { 2092, 4}, - .CMPGT = { 2096, 4}, - .CMPLE = { 2100, 4}, - .CMPLT = { 2104, 4}, - .CMPHI = { 2108, 4}, - .CMPHS = { 2112, 4}, - .CMPLO = { 2116, 4}, - .CMPLS = { 2120, 4}, - .FCMNE = { 2124, 3}, - .FCMUO = { 2127, 3}, - .INSR = { 2130, 4}, - .CPY = { 2134, 4}, - .COMPACT = { 2138, 2}, - .LD1B = { 2140, 6}, - .LD1H = { 2146, 6}, - .LD1W = { 2152, 6}, - .LD1D = { 2158, 5}, - .LD1SB = { 2163, 3}, - .LD1SH = { 2166, 3}, - .LD1SW = { 2169, 2}, - .ST1B = { 2171, 6}, - .ST1H = { 2177, 6}, - .ST1W = { 2183, 6}, - .ST1D = { 2189, 5}, - .LDFF1B = { 2194, 1}, - .LDFF1H = { 2195, 1}, - .LDFF1W = { 2196, 1}, - .LDFF1D = { 2197, 1}, - .WHILEGE = { 2198, 1}, - .WHILEGT = { 2199, 1}, - .WHILELE = { 2200, 1}, - .WHILELT = { 2201, 1}, - .WHILEHI = { 2202, 1}, - .WHILEHS = { 2203, 1}, - .WHILELO = { 2204, 1}, - .WHILELS = { 2205, 1}, - .SQRDMLAH = { 2206, 4}, - .SQRDMLSH = { 2210, 4}, - .ADCLB = { 2214, 2}, - .ADCLT = { 2216, 2}, - .SBCLB = { 2218, 2}, - .SBCLT = { 2220, 2}, - .TBL2 = { 2222, 1}, - .MATCH = { 2223, 2}, - .NMATCH = { 2225, 2}, - .HISTCNT = { 2227, 2}, - .HISTSEG = { 2229, 1}, - .SMSTART = { 2230, 1}, - .SMSTOP = { 2231, 1}, - .RDSVL = { 2232, 1}, - .ADDHA = { 2233, 1}, - .ADDVA = { 2234, 1}, - .ZERO = { 2235, 1}, - .FMOPA = { 2236, 1}, - .FMOPS = { 2237, 1}, - .BFMOPA = { 2238, 1}, - .BFMOPS = { 2239, 1}, - .SMOPA = { 2240, 2}, - .SMOPS = { 2242, 2}, - .UMOPA = { 2244, 2}, - .UMOPS = { 2246, 2}, - .USMOPA = { 2248, 1}, - .SUMOPA = { 2249, 1}, - .LD1Q = { 2250, 1}, - .ST1Q = { 2251, 1}, - .MOVA = { 2252, 2}, - .FCMLA = { 2254, 4}, - .FCADD = { 2258, 4}, - .PRFB = { 2262, 1}, - .PRFH = { 2263, 1}, - .PRFW = { 2264, 1}, - .PRFD = { 2265, 1}, - .LDNT1B = { 2266, 1}, - .LDNT1H = { 2267, 1}, - .LDNT1W = { 2268, 1}, - .LDNT1D = { 2269, 1}, - .STNT1B = { 2270, 1}, - .STNT1H = { 2271, 1}, - .STNT1W = { 2272, 1}, - .STNT1D = { 2273, 1}, - .SPLICE = { 2274, 1}, - .INDEX = { 2275, 4}, - .BSL1N = { 2279, 1}, - .BSL2N = { 2280, 1}, - .NBSL = { 2281, 1}, - .PMUL = { 2282, 1}, - .PMULLB = { 2283, 1}, - .PMULLT = { 2284, 1}, - .BFCVTNT = { 2285, 1}, - .LDRAA = { 2286, 2}, - .LDRAB = { 2288, 2}, - .TSTART = { 2290, 1}, - .TCOMMIT = { 2291, 1}, - .TCANCEL = { 2292, 1}, - .TTEST = { 2293, 1}, - .WFET = { 2294, 1}, - .WFIT = { 2295, 1}, - .BC_EQ = { 2296, 1}, - .BC_NE = { 2297, 1}, - .BC_CS = { 2298, 1}, - .BC_CC = { 2299, 1}, - .BC_MI = { 2300, 1}, - .BC_PL = { 2301, 1}, - .BC_VS = { 2302, 1}, - .BC_VC = { 2303, 1}, - .BC_HI = { 2304, 1}, - .BC_LS = { 2305, 1}, - .BC_GE = { 2306, 1}, - .BC_LT = { 2307, 1}, - .BC_GT = { 2308, 1}, - .BC_LE = { 2309, 1}, - .BC_AL = { 2310, 1}, - .BC_NV = { 2311, 1}, - .UXTB = { 2312, 1}, - .UXTH = { 2313, 1}, - .UXTW = { 2314, 1}, - .SXTB = { 2315, 1}, - .SXTH = { 2316, 1}, - .SXTW = { 2317, 1}, - .ADC = { 2318, 2}, - .ADCS = { 2320, 2}, - .SBC = { 2322, 2}, - .SBCS = { 2324, 2}, - .NGC = { 2326, 2}, - .NGCS = { 2328, 2}, - .LDAPUR = { 2330, 2}, - .STLUR = { 2332, 2}, - .LDAPURB = { 2334, 1}, - .STLURB = { 2335, 1}, - .LDAPURH = { 2336, 1}, - .STLURH = { 2337, 1}, - .LDAPURSB = { 2338, 2}, - .LDAPURSH = { 2340, 2}, - .LDAPURSW = { 2342, 1}, - .BFADD = { 2343, 2}, - .BFSUB = { 2345, 2}, - .BFMUL = { 2347, 2}, - .BFMLA = { 2349, 1}, - .BFMLS = { 2350, 1}, - .SB = { 2351, 1}, - .CSDB = { 2352, 1}, - .DGH = { 2353, 1}, - .PSB_CSYNC = { 2354, 1}, - .TSB_CSYNC = { 2355, 1}, - .BTI_J = { 2356, 1}, - .BTI_C = { 2357, 1}, - .BTI_JC = { 2358, 1}, - .BFCLAMP = { 2359, 1}, - .BFMAXNM = { 2360, 1}, - .BFMINNM = { 2361, 1}, - .LUTI2 = { 2362, 1}, - .LUTI4 = { 2363, 1}, - .ZIP = { 2364, 2}, - .UZP = { 2366, 2}, - .TLBI_RPALOS = { 2368, 1}, - .TLBI_RPAOS = { 2369, 1}, - .AT_S1E1A = { 2370, 1}, - .DC_CIPAPA = { 2371, 1}, - .DC_CIGDPAPA = { 2372, 1}, - .TLBI_PAALL = { 2373, 1}, - .TLBI_PAALLOS = { 2374, 1}, - .AMX_LDX = { 2375, 1}, - .AMX_LDY = { 2376, 1}, - .AMX_STX = { 2377, 1}, - .AMX_STY = { 2378, 1}, - .AMX_LDZ = { 2379, 1}, - .AMX_STZ = { 2380, 1}, - .AMX_LDZI = { 2381, 1}, - .AMX_STZI = { 2382, 1}, - .AMX_EXTRX = { 2383, 1}, - .AMX_EXTRY = { 2384, 1}, - .AMX_FMA64 = { 2385, 1}, - .AMX_FMS64 = { 2386, 1}, - .AMX_FMA32 = { 2387, 1}, - .AMX_FMS32 = { 2388, 1}, - .AMX_MAC16 = { 2389, 1}, - .AMX_FMA16 = { 2390, 1}, - .AMX_FMS16 = { 2391, 1}, - .AMX_SET = { 2392, 1}, - .AMX_CLR = { 2393, 1}, - .AMX_VECINT = { 2394, 1}, - .AMX_VECFP = { 2395, 1}, - .AMX_MATINT = { 2396, 1}, - .AMX_MATFP = { 2397, 1}, - .AMX_GENLUT = { 2398, 1}, - .CPYP = { 2399, 1}, - .CPYM = { 2400, 1}, - .CPYE = { 2401, 1}, - .CPYFP = { 2402, 1}, - .CPYFM = { 2403, 1}, - .CPYFE = { 2404, 1}, - .SETP = { 2405, 1}, - .SETM = { 2406, 1}, - .SETE = { 2407, 1}, - .DC_IVAC = { 2408, 1}, - .DC_ISW = { 2409, 1}, - .DC_CSW = { 2410, 1}, - .DC_CISW = { 2411, 1}, - .DC_ZVA = { 2412, 1}, - .DC_CVAC = { 2413, 1}, - .DC_CVAU = { 2414, 1}, - .DC_CIVAC = { 2415, 1}, - .IC_IALLUIS = { 2416, 1}, - .IC_IALLU = { 2417, 1}, - .IC_IVAU = { 2418, 1}, - .AT_S1E1R = { 2419, 1}, - .AT_S1E1W = { 2420, 1}, - .AT_S1E0R = { 2421, 1}, - .AT_S1E0W = { 2422, 1}, - .AT_S1E2R = { 2423, 1}, - .AT_S1E2W = { 2424, 1}, - .AT_S1E3R = { 2425, 1}, - .AT_S1E3W = { 2426, 1}, - .AT_S12E1R = { 2427, 1}, - .AT_S12E1W = { 2428, 1}, - .AT_S12E0R = { 2429, 1}, - .AT_S12E0W = { 2430, 1}, - .TLBI_VMALLE1 = { 2431, 1}, - .TLBI_VMALLE1IS = { 2432, 1}, - .TLBI_VAE1 = { 2433, 1}, - .TLBI_VAE1IS = { 2434, 1}, - .TLBI_ASIDE1 = { 2435, 1}, - .TLBI_ASIDE1IS = { 2436, 1}, - .TLBI_VAAE1 = { 2437, 1}, - .TLBI_VAAE1IS = { 2438, 1}, - .TLBI_VALE1 = { 2439, 1}, - .TLBI_VALE1IS = { 2440, 1}, - .TLBI_VAALE1 = { 2441, 1}, - .TLBI_VAALE1IS = { 2442, 1}, - .TLBI_ALLE1 = { 2443, 1}, - .TLBI_ALLE1IS = { 2444, 1}, - .TLBI_ALLE2 = { 2445, 1}, - .TLBI_ALLE2IS = { 2446, 1}, - .TLBI_ALLE3 = { 2447, 1}, - .TLBI_ALLE3IS = { 2448, 1}, - .PRFM = { 2449, 2}, - .PRFUM = { 2451, 1}, - .NEGS = { 2452, 2}, - .CMP = { 2454, 6}, - .CMN = { 2460, 6}, + .CSET = { 213, 6}, + .CSETM = { 219, 6}, + .CINC = { 225, 6}, + .CINV = { 231, 6}, + .CNEG = { 237, 6}, + .EXTR = { 243, 2}, + .B = { 245, 1}, + .BL = { 246, 1}, + .BR = { 247, 1}, + .BLR = { 248, 1}, + .RET = { 249, 2}, + .B_EQ = { 251, 1}, + .B_NE = { 252, 1}, + .B_CS = { 253, 1}, + .B_CC = { 254, 1}, + .B_MI = { 255, 1}, + .B_PL = { 256, 1}, + .B_VS = { 257, 1}, + .B_VC = { 258, 1}, + .B_HI = { 259, 1}, + .B_LS = { 260, 1}, + .B_GE = { 261, 1}, + .B_LT = { 262, 1}, + .B_GT = { 263, 1}, + .B_LE = { 264, 1}, + .B_AL = { 265, 1}, + .B_NV = { 266, 1}, + .CBZ = { 267, 2}, + .CBNZ = { 269, 2}, + .TBZ = { 271, 1}, + .TBNZ = { 272, 1}, + .LDR = { 273, 18}, + .STR = { 291, 16}, + .LDRB = { 307, 4}, + .STRB = { 311, 4}, + .LDRSB = { 315, 4}, + .LDRH = { 319, 4}, + .STRH = { 323, 4}, + .LDRSH = { 327, 4}, + .LDRSW = { 331, 2}, + .LDP = { 333, 9}, + .STP = { 342, 9}, + .LDPSW = { 351, 3}, + .LDAR = { 354, 2}, + .STLR = { 356, 2}, + .LDARB = { 358, 1}, + .STLRB = { 359, 1}, + .LDARH = { 360, 1}, + .STLRH = { 361, 1}, + .LDXR = { 362, 2}, + .STXR = { 364, 2}, + .LDAXR = { 366, 2}, + .STLXR = { 368, 2}, + .NOP = { 370, 1}, + .YIELD = { 371, 1}, + .WFE = { 372, 1}, + .WFI = { 373, 1}, + .SEV = { 374, 1}, + .SEVL = { 375, 1}, + .HINT = { 376, 1}, + .MRS = { 377, 1}, + .MSR = { 378, 2}, + .ISB = { 380, 1}, + .DSB = { 381, 1}, + .DMB = { 382, 1}, + .SVC = { 383, 1}, + .HVC = { 384, 1}, + .SMC = { 385, 1}, + .BRK = { 386, 1}, + .HLT = { 387, 1}, + .ERET = { 388, 1}, + .FMOV = { 389, 15}, + .FABS = { 404, 11}, + .FNEG = { 415, 11}, + .FSQRT = { 426, 11}, + .FADD = { 437, 12}, + .FSUB = { 449, 12}, + .FMUL = { 461, 12}, + .FDIV = { 473, 9}, + .FNMUL = { 482, 3}, + .FMADD = { 485, 3}, + .FMSUB = { 488, 3}, + .FNMADD = { 491, 3}, + .FNMSUB = { 494, 3}, + .FCMP = { 497, 3}, + .FCMPE = { 500, 3}, + .FCSEL = { 503, 3}, + .FMAX = { 506, 11}, + .FMIN = { 517, 11}, + .FMAXNM = { 528, 11}, + .FMINNM = { 539, 11}, + .FCVT = { 550, 6}, + .SCVTF = { 556, 10}, + .UCVTF = { 566, 10}, + .FCVTZS = { 576, 10}, + .FCVTZU = { 586, 10}, + .FCVTAS = { 596, 11}, + .FCVTAU = { 607, 11}, + .FCVTNS = { 618, 11}, + .FCVTNU = { 629, 11}, + .FCVTPS = { 640, 11}, + .FCVTPU = { 651, 11}, + .FCVTMS = { 662, 11}, + .FCVTMU = { 673, 11}, + .FRINTA = { 684, 11}, + .FRINTI = { 695, 11}, + .FRINTM = { 706, 11}, + .FRINTN = { 717, 11}, + .FRINTP = { 728, 11}, + .FRINTX = { 739, 11}, + .FRINTZ = { 750, 11}, + .TST = { 761, 4}, + .LDUR = { 765, 5}, + .STUR = { 770, 5}, + .LDURB = { 775, 1}, + .STURB = { 776, 1}, + .LDURSB = { 777, 2}, + .LDURH = { 779, 1}, + .STURH = { 780, 1}, + .LDURSH = { 781, 2}, + .LDURSW = { 783, 1}, + .LDNP = { 784, 2}, + .STNP = { 786, 2}, + .LDXP = { 788, 2}, + .STXP = { 790, 2}, + .LDAXP = { 792, 2}, + .STLXP = { 794, 2}, + .LDXRB = { 796, 1}, + .STXRB = { 797, 1}, + .LDAXRB = { 798, 1}, + .STLXRB = { 799, 1}, + .LDXRH = { 800, 1}, + .STXRH = { 801, 1}, + .LDAXRH = { 802, 1}, + .STLXRH = { 803, 1}, + .LDAPR = { 804, 2}, + .LDAPRB = { 806, 1}, + .LDAPRH = { 807, 1}, + .LDADD = { 808, 2}, + .LDADDA = { 810, 2}, + .LDADDL = { 812, 2}, + .LDADDAL = { 814, 2}, + .LDCLR = { 816, 2}, + .LDCLRA = { 818, 2}, + .LDCLRL = { 820, 2}, + .LDCLRAL = { 822, 2}, + .LDEOR = { 824, 2}, + .LDEORA = { 826, 2}, + .LDEORL = { 828, 2}, + .LDEORAL = { 830, 2}, + .LDSET = { 832, 2}, + .LDSETA = { 834, 2}, + .LDSETL = { 836, 2}, + .LDSETAL = { 838, 2}, + .LDSMAX = { 840, 2}, + .LDSMAXA = { 842, 2}, + .LDSMAXL = { 844, 2}, + .LDSMAXAL = { 846, 2}, + .LDSMIN = { 848, 2}, + .LDSMINA = { 850, 2}, + .LDSMINL = { 852, 2}, + .LDSMINAL = { 854, 2}, + .LDUMAX = { 856, 2}, + .LDUMAXA = { 858, 2}, + .LDUMAXL = { 860, 2}, + .LDUMAXAL = { 862, 2}, + .LDUMIN = { 864, 2}, + .LDUMINA = { 866, 2}, + .LDUMINL = { 868, 2}, + .LDUMINAL = { 870, 2}, + .SWP = { 872, 2}, + .SWPA = { 874, 2}, + .SWPL = { 876, 2}, + .SWPAL = { 878, 2}, + .CAS = { 880, 2}, + .CASA = { 882, 2}, + .CASL = { 884, 2}, + .CASAL = { 886, 2}, + .CASB = { 888, 1}, + .CASAB = { 889, 1}, + .CASLB = { 890, 1}, + .CASALB = { 891, 1}, + .CASH = { 892, 1}, + .CASAH = { 893, 1}, + .CASLH = { 894, 1}, + .CASALH = { 895, 1}, + .CASP = { 896, 2}, + .CASPA = { 898, 2}, + .CASPL = { 900, 2}, + .CASPAL = { 902, 2}, + .PACIA = { 904, 1}, + .PACIB = { 905, 1}, + .PACDA = { 906, 1}, + .PACDB = { 907, 1}, + .PACIZA = { 908, 1}, + .PACIZB = { 909, 1}, + .PACDZA = { 910, 1}, + .PACDZB = { 911, 1}, + .AUTIA = { 912, 1}, + .AUTIB = { 913, 1}, + .AUTDA = { 914, 1}, + .AUTDB = { 915, 1}, + .AUTIZA = { 916, 1}, + .AUTIZB = { 917, 1}, + .AUTDZA = { 918, 1}, + .AUTDZB = { 919, 1}, + .PACIASP = { 920, 1}, + .PACIBSP = { 921, 1}, + .AUTIASP = { 922, 1}, + .AUTIBSP = { 923, 1}, + .PACIA1716 = { 924, 1}, + .PACIB1716 = { 925, 1}, + .AUTIA1716 = { 926, 1}, + .AUTIB1716 = { 927, 1}, + .PACGA = { 928, 1}, + .XPACI = { 929, 1}, + .XPACD = { 930, 1}, + .XPACLRI = { 931, 1}, + .RETAA = { 932, 1}, + .RETAB = { 933, 1}, + .BRAA = { 934, 1}, + .BRAB = { 935, 1}, + .BRAAZ = { 936, 1}, + .BRABZ = { 937, 1}, + .BLRAA = { 938, 1}, + .BLRAB = { 939, 1}, + .BLRAAZ = { 940, 1}, + .BLRABZ = { 941, 1}, + .ERETAA = { 942, 1}, + .ERETAB = { 943, 1}, + .BTI = { 944, 1}, + .IRG = { 945, 1}, + .ADDG = { 946, 1}, + .SUBG = { 947, 1}, + .GMI = { 948, 1}, + .SUBP = { 949, 1}, + .SUBPS = { 950, 1}, + .LDG = { 951, 1}, + .STG = { 952, 1}, + .ST2G = { 953, 1}, + .STZG = { 954, 1}, + .STZ2G = { 955, 1}, + .STGP = { 956, 1}, + .LDGM = { 957, 1}, + .STGM = { 958, 1}, + .STZGM = { 959, 1}, + .CRC32B = { 960, 1}, + .CRC32H = { 961, 1}, + .CRC32W = { 962, 1}, + .CRC32X = { 963, 1}, + .CRC32CB = { 964, 1}, + .CRC32CH = { 965, 1}, + .CRC32CW = { 966, 1}, + .CRC32CX = { 967, 1}, + .AESE = { 968, 2}, + .AESD = { 970, 2}, + .AESMC = { 972, 2}, + .AESIMC = { 974, 2}, + .SHA1H = { 976, 1}, + .SHA1C = { 977, 1}, + .SHA1P = { 978, 1}, + .SHA1M = { 979, 1}, + .SHA1SU0 = { 980, 1}, + .SHA1SU1 = { 981, 1}, + .SHA256H = { 982, 1}, + .SHA256H2 = { 983, 1}, + .SHA256SU0 = { 984, 1}, + .SHA256SU1 = { 985, 1}, + .SHA512H = { 986, 1}, + .SHA512H2 = { 987, 1}, + .SHA512SU0 = { 988, 1}, + .SHA512SU1 = { 989, 1}, + .EOR3 = { 990, 2}, + .BCAX = { 992, 2}, + .RAX1 = { 994, 1}, + .XAR = { 995, 5}, + .SM3PARTW1 = { 1000, 1}, + .SM3PARTW2 = { 1001, 1}, + .SM3SS1 = { 1002, 1}, + .SM3TT1A = { 1003, 1}, + .SM3TT1B = { 1004, 1}, + .SM3TT2A = { 1005, 1}, + .SM3TT2B = { 1006, 1}, + .SM4E = { 1007, 1}, + .SM4EKEY = { 1008, 1}, + .PMULL = { 1009, 2}, + .PMULL2 = { 1011, 2}, + .BFCVT = { 1013, 2}, + .BFDOT = { 1015, 1}, + .BFMMLA = { 1016, 1}, + .BFMLALB = { 1017, 1}, + .BFMLALT = { 1018, 1}, + .BFCVTN = { 1019, 1}, + .BFCVTN2 = { 1020, 1}, + .MUL = { 1021, 7}, + .MLA = { 1028, 6}, + .MLS = { 1034, 6}, + .NEG = { 1040, 13}, + .ABS = { 1053, 11}, + .SHADD = { 1064, 6}, + .UHADD = { 1070, 6}, + .SHSUB = { 1076, 6}, + .UHSUB = { 1082, 6}, + .SRHADD = { 1088, 6}, + .URHADD = { 1094, 6}, + .SQADD = { 1100, 11}, + .UQADD = { 1111, 11}, + .SQSUB = { 1122, 11}, + .UQSUB = { 1133, 11}, + .SMAX = { 1144, 10}, + .UMAX = { 1154, 10}, + .SMIN = { 1164, 10}, + .UMIN = { 1174, 10}, + .SABD = { 1184, 10}, + .UABD = { 1194, 10}, + .SABA = { 1204, 6}, + .UABA = { 1210, 6}, + .ADDP = { 1216, 7}, + .ADDV = { 1223, 5}, + .SADDLP = { 1228, 6}, + .UADDLP = { 1234, 6}, + .SADALP = { 1240, 6}, + .UADALP = { 1246, 6}, + .SADDLV = { 1252, 5}, + .UADDLV = { 1257, 5}, + .SMAXV = { 1262, 5}, + .UMAXV = { 1267, 5}, + .SMINV = { 1272, 5}, + .UMINV = { 1277, 5}, + .SMAXP = { 1282, 6}, + .UMAXP = { 1288, 6}, + .SMINP = { 1294, 6}, + .UMINP = { 1300, 6}, + .SADDL = { 1306, 3}, + .SADDL2 = { 1309, 3}, + .UADDL = { 1312, 3}, + .UADDL2 = { 1315, 3}, + .SSUBL = { 1318, 3}, + .SSUBL2 = { 1321, 3}, + .USUBL = { 1324, 3}, + .USUBL2 = { 1327, 3}, + .SADDW = { 1330, 3}, + .SADDW2 = { 1333, 3}, + .UADDW = { 1336, 3}, + .UADDW2 = { 1339, 3}, + .SSUBW = { 1342, 3}, + .SSUBW2 = { 1345, 3}, + .USUBW = { 1348, 3}, + .USUBW2 = { 1351, 3}, + .RADDHN = { 1354, 3}, + .RADDHN2 = { 1357, 3}, + .RSUBHN = { 1360, 3}, + .RSUBHN2 = { 1363, 3}, + .ADDHN = { 1366, 3}, + .ADDHN2 = { 1369, 3}, + .SUBHN = { 1372, 3}, + .SUBHN2 = { 1375, 3}, + .XTN = { 1378, 3}, + .XTN2 = { 1381, 3}, + .SQXTN = { 1384, 3}, + .SQXTN2 = { 1387, 3}, + .UQXTN = { 1390, 3}, + .UQXTN2 = { 1393, 3}, + .SQXTUN = { 1396, 3}, + .SQXTUN2 = { 1399, 3}, + .SMULL = { 1402, 3}, + .SMULL2 = { 1405, 3}, + .UMULL = { 1408, 3}, + .UMULL2 = { 1411, 3}, + .SMLAL = { 1414, 3}, + .SMLAL2 = { 1417, 3}, + .UMLAL = { 1420, 3}, + .UMLAL2 = { 1423, 3}, + .SMLSL = { 1426, 3}, + .SMLSL2 = { 1429, 3}, + .UMLSL = { 1432, 3}, + .UMLSL2 = { 1435, 3}, + .SQDMULL = { 1438, 2}, + .SQDMULL2 = { 1440, 2}, + .SQDMLAL = { 1442, 2}, + .SQDMLAL2 = { 1444, 2}, + .SQDMLSL = { 1446, 2}, + .SQDMLSL2 = { 1448, 2}, + .SQDMULH = { 1450, 4}, + .SQRDMULH = { 1454, 4}, + .SDOT = { 1458, 2}, + .UDOT = { 1460, 2}, + .USDOT = { 1462, 2}, + .FMLA = { 1464, 8}, + .FMLS = { 1472, 8}, + .FMULX = { 1480, 5}, + .FMAXP = { 1485, 5}, + .FMINP = { 1490, 5}, + .FMAXNMP = { 1495, 5}, + .FMINNMP = { 1500, 5}, + .FMAXV = { 1505, 3}, + .FMINV = { 1508, 3}, + .FMAXNMV = { 1511, 3}, + .FMINNMV = { 1514, 3}, + .FRECPE = { 1517, 5}, + .FRSQRTE = { 1522, 5}, + .FRECPS = { 1527, 8}, + .FRSQRTS = { 1535, 8}, + .FRECPX = { 1543, 6}, + .FADDP = { 1549, 5}, + .FCVTL = { 1554, 2}, + .FCVTL2 = { 1556, 2}, + .FCVTN = { 1558, 2}, + .FCVTN2 = { 1560, 2}, + .FCVTXN = { 1562, 1}, + .FCVTXN2 = { 1563, 1}, + .FCMEQ = { 1564, 8}, + .FCMGE = { 1572, 8}, + .FCMGT = { 1580, 8}, + .FCMLE = { 1588, 8}, + .FCMLT = { 1596, 8}, + .FACGE = { 1604, 5}, + .FACGT = { 1609, 5}, + .CMEQ = { 1614, 4}, + .CMGE = { 1618, 7}, + .CMGT = { 1625, 2}, + .CMHI = { 1627, 2}, + .CMHS = { 1629, 7}, + .CMLE = { 1636, 7}, + .CMLT = { 1643, 7}, + .CMTST = { 1650, 7}, + .MVN = { 1657, 4}, + .BIT = { 1661, 1}, + .BIF = { 1662, 1}, + .BSL = { 1663, 2}, + .SHL = { 1665, 7}, + .SQSHL = { 1672, 7}, + .SQSHLU = { 1679, 7}, + .SRSHL = { 1686, 7}, + .URSHL = { 1693, 7}, + .SSHR = { 1700, 7}, + .USHR = { 1707, 7}, + .SSRA = { 1714, 7}, + .USRA = { 1721, 7}, + .SRSHR = { 1728, 7}, + .URSHR = { 1735, 7}, + .SRSRA = { 1742, 7}, + .URSRA = { 1749, 7}, + .SSHL = { 1756, 7}, + .USHL = { 1763, 7}, + .SLI = { 1770, 7}, + .SRI = { 1777, 7}, + .SSHLL = { 1784, 3}, + .SSHLL2 = { 1787, 3}, + .USHLL = { 1790, 3}, + .USHLL2 = { 1793, 3}, + .SXTL = { 1796, 3}, + .SXTL2 = { 1799, 3}, + .UXTL = { 1802, 3}, + .UXTL2 = { 1805, 3}, + .SHRN = { 1808, 3}, + .SHRN2 = { 1811, 3}, + .RSHRN = { 1814, 3}, + .RSHRN2 = { 1817, 3}, + .SQSHRN = { 1820, 3}, + .SQSHRN2 = { 1823, 3}, + .UQSHRN = { 1826, 3}, + .UQSHRN2 = { 1829, 3}, + .SQRSHRN = { 1832, 3}, + .SQRSHRN2 = { 1835, 3}, + .UQRSHRN = { 1838, 3}, + .UQRSHRN2 = { 1841, 3}, + .SQSHRUN = { 1844, 3}, + .SQSHRUN2 = { 1847, 3}, + .SQRSHRUN = { 1850, 3}, + .SQRSHRUN2 = { 1853, 3}, + .DUP = { 1856, 18}, + .INS = { 1874, 8}, + .MOV = { 1882, 12}, + .EXT = { 1894, 4}, + .TBL = { 1898, 6}, + .TBX = { 1904, 3}, + .ZIP1 = { 1907, 12}, + .ZIP2 = { 1919, 12}, + .UZP1 = { 1931, 12}, + .UZP2 = { 1943, 12}, + .TRN1 = { 1955, 12}, + .TRN2 = { 1967, 12}, + .NOT = { 1979, 3}, + .REV64 = { 1982, 6}, + .CNT = { 1988, 6}, + .URECPE = { 1994, 2}, + .URSQRTE = { 1996, 2}, + .MOVI = { 1998, 7}, + .MVNI = { 2005, 4}, + .LD1 = { 2009, 8}, + .LD2 = { 2017, 5}, + .LD3 = { 2022, 5}, + .LD4 = { 2027, 5}, + .ST1 = { 2032, 8}, + .ST2 = { 2040, 5}, + .ST3 = { 2045, 5}, + .ST4 = { 2050, 5}, + .LD1R = { 2055, 1}, + .LD2R = { 2056, 1}, + .LD3R = { 2057, 1}, + .LD4R = { 2058, 1}, + .SUBR = { 2059, 4}, + .ASRR = { 2063, 4}, + .LSLR = { 2067, 4}, + .LSRR = { 2071, 4}, + .FTSMUL = { 2075, 3}, + .FSUBR = { 2078, 3}, + .FDIVR = { 2081, 3}, + .FNMLA = { 2084, 3}, + .FNMLS = { 2087, 3}, + .NAND = { 2090, 1}, + .NOR = { 2091, 1}, + .SEL = { 2092, 1}, + .ORRS = { 2093, 1}, + .EORS = { 2094, 1}, + .NANDS = { 2095, 1}, + .NORS = { 2096, 1}, + .ORNS = { 2097, 1}, + .MOVS = { 2098, 1}, + .PTRUE = { 2099, 1}, + .PTRUES = { 2100, 1}, + .PFALSE = { 2101, 1}, + .PFIRST = { 2102, 1}, + .PNEXT = { 2103, 1}, + .BRKA = { 2104, 1}, + .BRKB = { 2105, 1}, + .BRKAS = { 2106, 1}, + .BRKBS = { 2107, 1}, + .BRKPA = { 2108, 1}, + .BRKPB = { 2109, 1}, + .BRKN = { 2110, 1}, + .RDFFR = { 2111, 1}, + .WRFFR = { 2112, 1}, + .SETFFR = { 2113, 1}, + .CMPEQ = { 2114, 4}, + .CMPNE = { 2118, 4}, + .CMPGE = { 2122, 4}, + .CMPGT = { 2126, 4}, + .CMPLE = { 2130, 4}, + .CMPLT = { 2134, 4}, + .CMPHI = { 2138, 4}, + .CMPHS = { 2142, 4}, + .CMPLO = { 2146, 4}, + .CMPLS = { 2150, 4}, + .FCMNE = { 2154, 3}, + .FCMUO = { 2157, 3}, + .INSR = { 2160, 4}, + .CPY = { 2164, 4}, + .COMPACT = { 2168, 2}, + .LD1B = { 2170, 6}, + .LD1H = { 2176, 6}, + .LD1W = { 2182, 6}, + .LD1D = { 2188, 5}, + .LD1SB = { 2193, 3}, + .LD1SH = { 2196, 3}, + .LD1SW = { 2199, 2}, + .ST1B = { 2201, 6}, + .ST1H = { 2207, 6}, + .ST1W = { 2213, 6}, + .ST1D = { 2219, 5}, + .LDFF1B = { 2224, 1}, + .LDFF1H = { 2225, 1}, + .LDFF1W = { 2226, 1}, + .LDFF1D = { 2227, 1}, + .WHILEGE = { 2228, 1}, + .WHILEGT = { 2229, 1}, + .WHILELE = { 2230, 1}, + .WHILELT = { 2231, 1}, + .WHILEHI = { 2232, 1}, + .WHILEHS = { 2233, 1}, + .WHILELO = { 2234, 1}, + .WHILELS = { 2235, 1}, + .SQRDMLAH = { 2236, 4}, + .SQRDMLSH = { 2240, 4}, + .ADCLB = { 2244, 2}, + .ADCLT = { 2246, 2}, + .SBCLB = { 2248, 2}, + .SBCLT = { 2250, 2}, + .TBL2 = { 2252, 1}, + .MATCH = { 2253, 2}, + .NMATCH = { 2255, 2}, + .HISTCNT = { 2257, 2}, + .HISTSEG = { 2259, 1}, + .SMSTART = { 2260, 1}, + .SMSTOP = { 2261, 1}, + .RDSVL = { 2262, 1}, + .ADDHA = { 2263, 1}, + .ADDVA = { 2264, 1}, + .ZERO = { 2265, 1}, + .FMOPA = { 2266, 1}, + .FMOPS = { 2267, 1}, + .BFMOPA = { 2268, 1}, + .BFMOPS = { 2269, 1}, + .SMOPA = { 2270, 2}, + .SMOPS = { 2272, 2}, + .UMOPA = { 2274, 2}, + .UMOPS = { 2276, 2}, + .USMOPA = { 2278, 1}, + .SUMOPA = { 2279, 1}, + .LD1Q = { 2280, 1}, + .ST1Q = { 2281, 1}, + .MOVA = { 2282, 2}, + .FCMLA = { 2284, 4}, + .FCADD = { 2288, 4}, + .PRFB = { 2292, 1}, + .PRFH = { 2293, 1}, + .PRFW = { 2294, 1}, + .PRFD = { 2295, 1}, + .LDNT1B = { 2296, 1}, + .LDNT1H = { 2297, 1}, + .LDNT1W = { 2298, 1}, + .LDNT1D = { 2299, 1}, + .STNT1B = { 2300, 1}, + .STNT1H = { 2301, 1}, + .STNT1W = { 2302, 1}, + .STNT1D = { 2303, 1}, + .SPLICE = { 2304, 1}, + .INDEX = { 2305, 4}, + .BSL1N = { 2309, 1}, + .BSL2N = { 2310, 1}, + .NBSL = { 2311, 1}, + .PMUL = { 2312, 1}, + .PMULLB = { 2313, 1}, + .PMULLT = { 2314, 1}, + .BFCVTNT = { 2315, 1}, + .LDRAA = { 2316, 2}, + .LDRAB = { 2318, 2}, + .TSTART = { 2320, 1}, + .TCOMMIT = { 2321, 1}, + .TCANCEL = { 2322, 1}, + .TTEST = { 2323, 1}, + .WFET = { 2324, 1}, + .WFIT = { 2325, 1}, + .BC_EQ = { 2326, 1}, + .BC_NE = { 2327, 1}, + .BC_CS = { 2328, 1}, + .BC_CC = { 2329, 1}, + .BC_MI = { 2330, 1}, + .BC_PL = { 2331, 1}, + .BC_VS = { 2332, 1}, + .BC_VC = { 2333, 1}, + .BC_HI = { 2334, 1}, + .BC_LS = { 2335, 1}, + .BC_GE = { 2336, 1}, + .BC_LT = { 2337, 1}, + .BC_GT = { 2338, 1}, + .BC_LE = { 2339, 1}, + .BC_AL = { 2340, 1}, + .BC_NV = { 2341, 1}, + .UXTB = { 2342, 1}, + .UXTH = { 2343, 1}, + .UXTW = { 2344, 1}, + .SXTB = { 2345, 1}, + .SXTH = { 2346, 1}, + .SXTW = { 2347, 1}, + .ADC = { 2348, 2}, + .ADCS = { 2350, 2}, + .SBC = { 2352, 2}, + .SBCS = { 2354, 2}, + .NGC = { 2356, 2}, + .NGCS = { 2358, 2}, + .LDAPUR = { 2360, 2}, + .STLUR = { 2362, 2}, + .LDAPURB = { 2364, 1}, + .STLURB = { 2365, 1}, + .LDAPURH = { 2366, 1}, + .STLURH = { 2367, 1}, + .LDAPURSB = { 2368, 2}, + .LDAPURSH = { 2370, 2}, + .LDAPURSW = { 2372, 1}, + .BFADD = { 2373, 2}, + .BFSUB = { 2375, 2}, + .BFMUL = { 2377, 2}, + .BFMLA = { 2379, 1}, + .BFMLS = { 2380, 1}, + .SB = { 2381, 1}, + .CSDB = { 2382, 1}, + .DGH = { 2383, 1}, + .PSB_CSYNC = { 2384, 1}, + .TSB_CSYNC = { 2385, 1}, + .BTI_J = { 2386, 1}, + .BTI_C = { 2387, 1}, + .BTI_JC = { 2388, 1}, + .BFCLAMP = { 2389, 1}, + .BFMAXNM = { 2390, 1}, + .BFMINNM = { 2391, 1}, + .LUTI2 = { 2392, 1}, + .LUTI4 = { 2393, 1}, + .ZIP = { 2394, 2}, + .UZP = { 2396, 2}, + .TLBI_RPALOS = { 2398, 1}, + .TLBI_RPAOS = { 2399, 1}, + .AT_S1E1A = { 2400, 1}, + .DC_CIPAPA = { 2401, 1}, + .DC_CIGDPAPA = { 2402, 1}, + .TLBI_PAALL = { 2403, 1}, + .TLBI_PAALLOS = { 2404, 1}, + .AMX_LDX = { 2405, 1}, + .AMX_LDY = { 2406, 1}, + .AMX_STX = { 2407, 1}, + .AMX_STY = { 2408, 1}, + .AMX_LDZ = { 2409, 1}, + .AMX_STZ = { 2410, 1}, + .AMX_LDZI = { 2411, 1}, + .AMX_STZI = { 2412, 1}, + .AMX_EXTRX = { 2413, 1}, + .AMX_EXTRY = { 2414, 1}, + .AMX_FMA64 = { 2415, 1}, + .AMX_FMS64 = { 2416, 1}, + .AMX_FMA32 = { 2417, 1}, + .AMX_FMS32 = { 2418, 1}, + .AMX_MAC16 = { 2419, 1}, + .AMX_FMA16 = { 2420, 1}, + .AMX_FMS16 = { 2421, 1}, + .AMX_SET = { 2422, 1}, + .AMX_CLR = { 2423, 1}, + .AMX_VECINT = { 2424, 1}, + .AMX_VECFP = { 2425, 1}, + .AMX_MATINT = { 2426, 1}, + .AMX_MATFP = { 2427, 1}, + .AMX_GENLUT = { 2428, 1}, + .CPYP = { 2429, 1}, + .CPYM = { 2430, 1}, + .CPYE = { 2431, 1}, + .CPYFP = { 2432, 1}, + .CPYFM = { 2433, 1}, + .CPYFE = { 2434, 1}, + .SETP = { 2435, 1}, + .SETM = { 2436, 1}, + .SETE = { 2437, 1}, + .DC_IVAC = { 2438, 1}, + .DC_ISW = { 2439, 1}, + .DC_CSW = { 2440, 1}, + .DC_CISW = { 2441, 1}, + .DC_ZVA = { 2442, 1}, + .DC_CVAC = { 2443, 1}, + .DC_CVAU = { 2444, 1}, + .DC_CIVAC = { 2445, 1}, + .IC_IALLUIS = { 2446, 1}, + .IC_IALLU = { 2447, 1}, + .IC_IVAU = { 2448, 1}, + .AT_S1E1R = { 2449, 1}, + .AT_S1E1W = { 2450, 1}, + .AT_S1E0R = { 2451, 1}, + .AT_S1E0W = { 2452, 1}, + .AT_S1E2R = { 2453, 1}, + .AT_S1E2W = { 2454, 1}, + .AT_S1E3R = { 2455, 1}, + .AT_S1E3W = { 2456, 1}, + .AT_S12E1R = { 2457, 1}, + .AT_S12E1W = { 2458, 1}, + .AT_S12E0R = { 2459, 1}, + .AT_S12E0W = { 2460, 1}, + .TLBI_VMALLE1 = { 2461, 1}, + .TLBI_VMALLE1IS = { 2462, 1}, + .TLBI_VAE1 = { 2463, 1}, + .TLBI_VAE1IS = { 2464, 1}, + .TLBI_ASIDE1 = { 2465, 1}, + .TLBI_ASIDE1IS = { 2466, 1}, + .TLBI_VAAE1 = { 2467, 1}, + .TLBI_VAAE1IS = { 2468, 1}, + .TLBI_VALE1 = { 2469, 1}, + .TLBI_VALE1IS = { 2470, 1}, + .TLBI_VAALE1 = { 2471, 1}, + .TLBI_VAALE1IS = { 2472, 1}, + .TLBI_ALLE1 = { 2473, 1}, + .TLBI_ALLE1IS = { 2474, 1}, + .TLBI_ALLE2 = { 2475, 1}, + .TLBI_ALLE2IS = { 2476, 1}, + .TLBI_ALLE3 = { 2477, 1}, + .TLBI_ALLE3IS = { 2478, 1}, + .PRFM = { 2479, 2}, + .PRFUM = { 2481, 1}, + .NEGS = { 2482, 2}, + .CMP = { 2484, 6}, + .CMN = { 2490, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index e7ad938b7..13fb3296c 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -379,6 +379,46 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, + .CSET = { + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSETM = { + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CINC = { + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CINV = { + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CNEG = { + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + }, .CSINC = { {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 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zB`imM+$FI&>h~_Gkz0g)9OK!U)*J)Z_@bKm_V_IbYvHr($SR1PAgqSiSsq`1Lw7wY z3Lo)!eGlzR@_E2`-41PL#`8P$al(>&Gx#u*Uk_f=(S&?u9_~BaO$oDrSuwMG!V1G> zFoRmR&2XUKq#LQ|z@;qdt!{I;2Js z={h7|5#{TU*dmI(PFRI7_E$l%*GY|v06l+2YIKqAE28TX9nYmJkDhOox(&j(-v)}k zQED_qSa+qwwovR!(Y1(<^R-aESYq2KHWtrqqT?B~QNC4Dqf;2y=%mSzr%oyW#-#8FNls4mL@huSU~J}`*$5KwvO0T_^x(jA+b7PO~gJUu@SKwtUveK zxfJ}t>#f5020H^}&<8LN7|Z}!gzT%9mAcoaA^a(T)qT~*mf&k$W>BNpv0TCm<4)1V z@TVt9Y^UUlDPO1c=VD`uT`tVzG2e2@X9CQ(T=JO++4T||Q|$E;8&mA{5*t(O{{e`8 BSt9@d diff --git a/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin b/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin index ea4c00bdb26da568c9b7fefc194b54518197fe35..0cc877c3a7618282f937affa829bdc71d6d69339 100644 GIT binary patch delta 15 WcmZ>8m|(_L#qgg)m_dkh0|Njcz5}oT delta 15 WcmZ>8m|(^g!|;$pnBfb@1_l5kCj?ah diff --git a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin index 86b9baa4a..8b68749a0 100644 --- a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin @@ -131,7 +131,7 @@ operand_category :: proc(t: a.Operand_Type) -> Operand_Category { // All addressing modes take one `Memory` parameter, so they share a // builder signature: the encoder picks the form from mem.mode. return .MEM - case .COND: + case .COND, .COND_NOT_AL: return .COND case .W_SHIFTED, .X_SHIFTED: return .SHIFTED From ba5d1dab009d26724d3002500db4aa8f2f99f111 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 09:43:17 -0400 Subject: [PATCH 28/89] rexcode/arm64: 89 system registers had the wrong encoding Printing MRS/MSR operands by name made these visible: sweeping all 230 constants through encode -> decode -> print -> llvm-mc, 89 of them assembled to bytes we did not produce. TCR_EL1 encoded as 0x4282 where the architecture says 0x4102, FAR_EL1 as 0x5300 for 0x4300, the whole pointer-auth key block was off by a CRn, and so on. Anything reading one of them got a different register than it asked for. The field comments were right and only the packed values were wrong, so most of the file could be rebuilt from its own comments and checked against llvm-mc. Thirteen needed more: nine had bad comments too (RGSR/GCR/TFSR/TFSRE0, ID_MMFR4/5, and the three ICC SGI registers -- ICC_SGI*_EL1 are op1=0, not 3), and four carried a "historic collision" note instead of fields. Those were derived from the ARM ARM and agree with llvm-mc. Five of the six encodings that looked like duplicates were simply wrong values landing on each other; one real pair is left, DBGDTRRX_EL0 and DBGDTRTX_EL0, which genuinely share an encoding as the read and write views of one register. The name table prefers the read name, since MRS is the direction that has to print. All 230 now verified byte-exact against llvm-mc: 222 through MRS, and the 8 write-only ones through MSR. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/sysregs.odin | 357 ++++++++++++++-------------- 1 file changed, 182 insertions(+), 175 deletions(-) diff --git a/core/rexcode/isa/arm64/sysregs.odin b/core/rexcode/isa/arm64/sysregs.odin index 0e142edf4..33dff77cb 100644 --- a/core/rexcode/isa/arm64/sysregs.odin +++ b/core/rexcode/isa/arm64/sysregs.odin @@ -60,9 +60,9 @@ ELR_EL1 :: i64(0x4201) // 3 0 4 0 1 ELR_EL2 :: i64(0x6201) // 3 4 4 0 1 SPSR_EL1 :: i64(0x4200) // 3 0 4 0 0 SPSR_EL2 :: i64(0x6200) // 3 4 4 0 0 -ESR_EL1 :: i64(0x5290) // 3 0 5 2 0 +ESR_EL1 :: i64(0x4290) // 3 0 5 2 0 ESR_EL2 :: i64(0x6290) // 3 4 5 2 0 -FAR_EL1 :: i64(0x5300) // 3 0 6 0 0 +FAR_EL1 :: i64(0x4300) // 3 0 6 0 0 FAR_EL2 :: i64(0x6300) // 3 4 6 0 0 TPIDR_EL0 :: i64(0x5E82) // 3 3 13 0 2 TPIDRRO_EL0 :: i64(0x5E83) // 3 3 13 0 3 @@ -76,7 +76,7 @@ MIDR_EL1 :: i64(0x4000) // 3 0 0 0 0 MPIDR_EL1 :: i64(0x4005) // 3 0 0 0 5 DCZID_EL0 :: i64(0x5807) // 3 3 0 0 7 (used by __sve_max_vl-style probes too) CTR_EL0 :: i64(0x5801) // 3 3 0 0 1 -TCR_EL1 :: i64(0x4282) // 3 0 2 0 2 +TCR_EL1 :: i64(0x4102) // 3 0 2 0 2 SCTLR_EL1 :: i64(0x4080) // 3 0 1 0 0 VBAR_EL1 :: i64(0x4600) // 3 0 12 0 0 HCR_EL2 :: i64(0x6088) // 3 4 1 1 0 @@ -153,7 +153,7 @@ SCTLR_EL2 :: i64(0x6080) // 3 4 1 0 0 SCTLR_EL3 :: i64(0x7080) // 3 6 1 0 0 SPSR_EL3 :: i64(0x7200) // 3 6 4 0 0 ELR_EL3 :: i64(0x7201) // 3 6 4 0 1 -TPIDR_EL2 :: i64(0x6E82) // 3 4 13 0 2 +TPIDR_EL2 :: i64(0x6682) // 3 4 13 0 2 TPIDR_EL3 :: i64(0x7682) // 3 6 13 0 2 -- err, EL3 needs op1=6 HSTR_EL2 :: i64(0x608B) // 3 4 1 1 3 MDCR_EL2 :: i64(0x6089) // 3 4 1 1 1 @@ -176,36 +176,36 @@ OSLSR_EL1 :: i64(0x008C) // 2 0 1 1 4 // ----------------------------------------------------------------------------- // Cache / Memory feature extras // ----------------------------------------------------------------------------- -RGSR_EL1 :: i64(0x4288) // 3 0 5 1 0 (FEAT_MTE) -GCR_EL1 :: i64(0x4289) // 3 0 5 1 2 (FEAT_MTE) -TFSR_EL1 :: i64(0x4300) // 3 0 6 0 0 (FEAT_MTE) -TFSRE0_EL1 :: i64(0x4301) // 3 0 6 0 1 (FEAT_MTE) +RGSR_EL1 :: i64(0x4085) // 3 0 1 0 5 (FEAT_MTE) +GCR_EL1 :: i64(0x4086) // 3 0 1 0 6 (FEAT_MTE) +TFSR_EL1 :: i64(0x42B0) // 3 0 5 6 0 (FEAT_MTE) +TFSRE0_EL1 :: i64(0x42B1) // 3 0 5 6 1 (FEAT_MTE) GMID_EL1 :: i64(0x4804) // 3 1 0 0 4 (FEAT_MTE) // ----------------------------------------------------------------------------- // SME / SVE configuration // ----------------------------------------------------------------------------- -SVCR :: i64(0x5A22) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) -SMCR_EL1 :: i64(0x4296) // 3 0 1 2 6 (FEAT_SME) -SMCR_EL2 :: i64(0x6296) // 3 4 1 2 6 -ZCR_EL1 :: i64(0x4290) // 3 0 1 2 0 (FEAT_SVE) -ZCR_EL2 :: i64(0x6290) // 3 4 1 2 0 -ZCR_EL3 :: i64(0x7290) // 3 6 1 2 0 +SVCR :: i64(0x5A12) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) +SMCR_EL1 :: i64(0x4096) // 3 0 1 2 6 (FEAT_SME) +SMCR_EL2 :: i64(0x6096) // 3 4 1 2 6 +ZCR_EL1 :: i64(0x4090) // 3 0 1 2 0 (FEAT_SVE) +ZCR_EL2 :: i64(0x6090) // 3 4 1 2 0 +ZCR_EL3 :: i64(0x7090) // 3 6 1 2 0 // ----------------------------------------------------------------------------- // Cache / data prefetch hint controls // ----------------------------------------------------------------------------- -PRSELR_EL1 :: i64(0x4288) // ... (collision with RGSR_EL1; keep historic) -APIAKEYLO_EL1 :: i64(0x4318) // 3 0 2 1 0 (FEAT_PAuth) -APIAKEYHI_EL1 :: i64(0x4319) // 3 0 2 1 1 -APIBKEYLO_EL1 :: i64(0x431A) // 3 0 2 1 2 -APIBKEYHI_EL1 :: i64(0x431B) // 3 0 2 1 3 -APDAKEYLO_EL1 :: i64(0x4320) // 3 0 2 2 0 -APDAKEYHI_EL1 :: i64(0x4321) // 3 0 2 2 1 -APDBKEYLO_EL1 :: i64(0x4322) // 3 0 2 2 2 -APDBKEYHI_EL1 :: i64(0x4323) // 3 0 2 2 3 -APGAKEYLO_EL1 :: i64(0x4328) // 3 0 2 3 0 -APGAKEYHI_EL1 :: i64(0x4329) // 3 0 2 3 1 +PRSELR_EL1 :: i64(0x4311) // 3 0 6 2 1 +APIAKEYLO_EL1 :: i64(0x4108) // 3 0 2 1 0 (FEAT_PAuth) +APIAKEYHI_EL1 :: i64(0x4109) // 3 0 2 1 1 +APIBKEYLO_EL1 :: i64(0x410A) // 3 0 2 1 2 +APIBKEYHI_EL1 :: i64(0x410B) // 3 0 2 1 3 +APDAKEYLO_EL1 :: i64(0x4110) // 3 0 2 2 0 +APDAKEYHI_EL1 :: i64(0x4111) // 3 0 2 2 1 +APDBKEYLO_EL1 :: i64(0x4112) // 3 0 2 2 2 +APDBKEYHI_EL1 :: i64(0x4113) // 3 0 2 2 3 +APGAKEYLO_EL1 :: i64(0x4118) // 3 0 2 3 0 +APGAKEYHI_EL1 :: i64(0x4119) // 3 0 2 3 1 // ============================================================================= // Batch 5: comprehensive sysreg sweep @@ -222,8 +222,8 @@ ID_MMFR0_EL1 :: i64(0x400C) // 3 0 0 1 4 ID_MMFR1_EL1 :: i64(0x400D) // 3 0 0 1 5 ID_MMFR2_EL1 :: i64(0x400E) // 3 0 0 1 6 ID_MMFR3_EL1 :: i64(0x400F) // 3 0 0 1 7 -ID_MMFR4_EL1 :: i64(0x4036) // 3 0 0 6 6 -ID_MMFR5_EL1 :: i64(0x402E) // 3 0 0 5 6 +ID_MMFR4_EL1 :: i64(0x4016) // 3 0 0 2 6 +ID_MMFR5_EL1 :: i64(0x401E) // 3 0 0 3 6 ID_ISAR0_EL1 :: i64(0x4010) // 3 0 0 2 0 ID_ISAR1_EL1 :: i64(0x4011) // 3 0 0 2 1 ID_ISAR2_EL1 :: i64(0x4012) // 3 0 0 2 2 @@ -231,7 +231,7 @@ ID_ISAR3_EL1 :: i64(0x4013) // 3 0 0 2 3 ID_ISAR4_EL1 :: i64(0x4014) // 3 0 0 2 4 ID_ISAR5_EL1 :: i64(0x4015) // 3 0 0 2 5 ID_ISAR6_EL1 :: i64(0x4017) // 3 0 0 2 7 -ID_PFR2_EL1 :: i64(0x402C) // (overlap historic; check if collision) +ID_PFR2_EL1 :: i64(0x401C) // 3 0 0 3 4 MVFR0_EL1 :: i64(0x4018) // 3 0 0 3 0 MVFR1_EL1 :: i64(0x4019) // 3 0 0 3 1 MVFR2_EL1 :: i64(0x401A) // 3 0 0 3 2 @@ -253,7 +253,7 @@ CNTHV_CVAL_EL2 :: i64(0x671A) // 3 4 14 3 2 CNTPS_TVAL_EL1 :: i64(0x7F10) // 3 7 14 2 0 CNTPS_CTL_EL1 :: i64(0x7F11) // 3 7 14 2 1 CNTPS_CVAL_EL1 :: i64(0x7F12) // 3 7 14 2 2 -CNTVOFF_EL2 :: i64(0x671B) // 3 4 14 0 3 +CNTVOFF_EL2 :: i64(0x6703) // 3 4 14 0 3 // ---- Debug breakpoints (DBGB*) and watchpoints (DBGW*), numbered ---- // @@ -278,15 +278,15 @@ sysreg_debug_watchpoint_control :: #force_inline proc "contextless" (n: u32) -> } // Other debug registers -DBGDTR_EL0 :: i64(0x1A20) // 2 3 0 4 0 -DBGDTRRX_EL0 :: i64(0x1A28) // 2 3 0 5 0 -DBGDTRTX_EL0 :: i64(0x1A28) -DBGPRCR_EL1 :: i64(0x0084) // (collision flag; treat as canonical from doc) -DBGCLAIMSET_EL1 :: i64(0x1BC6) // 2 0 7 8 6 -DBGCLAIMCLR_EL1 :: i64(0x1BCE) // 2 0 7 9 6 -DBGAUTHSTATUS_EL1:: i64(0x1BF6) // 2 0 7 14 6 +DBGDTR_EL0 :: i64(0x1820) // 2 3 0 4 0 +DBGDTRRX_EL0 :: i64(0x1828) // 2 3 0 5 0 +DBGDTRTX_EL0 :: i64(0x1828) // 2 3 0 5 0 (write view of DBGDTRRX_EL0) +DBGPRCR_EL1 :: i64(0x00A4) // 2 0 1 4 4 +DBGCLAIMSET_EL1 :: i64(0x03C6) // 2 0 7 8 6 +DBGCLAIMCLR_EL1 :: i64(0x03CE) // 2 0 7 9 6 +DBGAUTHSTATUS_EL1:: i64(0x03F6) // 2 0 7 14 6 MDCCINT_EL1 :: i64(0x0010) // 2 0 0 2 0 -MDRAR_EL1 :: i64(0x1080) // 2 0 1 0 0 +MDRAR_EL1 :: i64(0x0080) // 2 0 1 0 0 // PMU event counters (PMEVCNTRn_EL0 / PMEVTYPERn_EL0). Up to n=30. // PMEVCNTRn_EL0 = sysreg(3, 3, 14, 8+(n>>3), n & 7) @@ -299,40 +299,40 @@ sysreg_pmu_event_typer :: #force_inline proc "contextless" (n: u32) -> i64 { return sysreg_field(3, 3, 14, 12 + ((n >> 3) & 0x3), n & 0x7) } -PMINTENSET_EL1 :: i64(0x4CE1) // 3 0 9 14 1 -PMINTENCLR_EL1 :: i64(0x4CE2) // 3 0 9 14 2 +PMINTENSET_EL1 :: i64(0x44F1) // 3 0 9 14 1 +PMINTENCLR_EL1 :: i64(0x44F2) // 3 0 9 14 2 // ---- GICv3 (ICC_*) -- CPU interface ---- -ICC_IAR0_EL1 :: i64(0x4C40) // 3 0 12 8 0 -ICC_IAR1_EL1 :: i64(0x4C60) // 3 0 12 12 0 -ICC_EOIR0_EL1 :: i64(0x4C41) // 3 0 12 8 1 -ICC_EOIR1_EL1 :: i64(0x4C61) // 3 0 12 12 1 -ICC_HPPIR0_EL1 :: i64(0x4C42) // 3 0 12 8 2 -ICC_HPPIR1_EL1 :: i64(0x4C62) // 3 0 12 12 2 -ICC_BPR0_EL1 :: i64(0x4C43) // 3 0 12 8 3 -ICC_BPR1_EL1 :: i64(0x4C63) // 3 0 12 12 3 -ICC_DIR_EL1 :: i64(0x4C59) // 3 0 12 11 1 -ICC_PMR_EL1 :: i64(0x4630) // 3 0 4 6 0 -ICC_RPR_EL1 :: i64(0x4C5B) // 3 0 12 11 3 -ICC_SGI0R_EL1 :: i64(0x5CDF) // 3 3 12 11 7 -ICC_SGI1R_EL1 :: i64(0x5CDD) // 3 3 12 11 5 -ICC_ASGI1R_EL1 :: i64(0x5CDE) // 3 3 12 11 6 -ICC_SRE_EL1 :: i64(0x4C65) // 3 0 12 12 5 -ICC_SRE_EL2 :: i64(0x6C65) // 3 4 12 9 5 -ICC_SRE_EL3 :: i64(0x7C65) // 3 6 12 12 5 -ICC_CTLR_EL1 :: i64(0x4C64) // 3 0 12 12 4 -ICC_CTLR_EL3 :: i64(0x7C64) // 3 6 12 12 4 -ICC_IGRPEN0_EL1 :: i64(0x4C66) // 3 0 12 12 6 -ICC_IGRPEN1_EL1 :: i64(0x4C67) // 3 0 12 12 7 -ICC_IGRPEN1_EL3 :: i64(0x7C67) // 3 6 12 12 7 +ICC_IAR0_EL1 :: i64(0x4640) // 3 0 12 8 0 +ICC_IAR1_EL1 :: i64(0x4660) // 3 0 12 12 0 +ICC_EOIR0_EL1 :: i64(0x4641) // 3 0 12 8 1 +ICC_EOIR1_EL1 :: i64(0x4661) // 3 0 12 12 1 +ICC_HPPIR0_EL1 :: i64(0x4642) // 3 0 12 8 2 +ICC_HPPIR1_EL1 :: i64(0x4662) // 3 0 12 12 2 +ICC_BPR0_EL1 :: i64(0x4643) // 3 0 12 8 3 +ICC_BPR1_EL1 :: i64(0x4663) // 3 0 12 12 3 +ICC_DIR_EL1 :: i64(0x4659) // 3 0 12 11 1 +ICC_PMR_EL1 :: i64(0x4230) // 3 0 4 6 0 +ICC_RPR_EL1 :: i64(0x465B) // 3 0 12 11 3 +ICC_SGI0R_EL1 :: i64(0x465F) // 3 0 12 11 7 +ICC_SGI1R_EL1 :: i64(0x465D) // 3 0 12 11 5 +ICC_ASGI1R_EL1 :: i64(0x465E) // 3 0 12 11 6 +ICC_SRE_EL1 :: i64(0x4665) // 3 0 12 12 5 +ICC_SRE_EL2 :: i64(0x664D) // 3 4 12 9 5 +ICC_SRE_EL3 :: i64(0x7665) // 3 6 12 12 5 +ICC_CTLR_EL1 :: i64(0x4664) // 3 0 12 12 4 +ICC_CTLR_EL3 :: i64(0x7664) // 3 6 12 12 4 +ICC_IGRPEN0_EL1 :: i64(0x4666) // 3 0 12 12 6 +ICC_IGRPEN1_EL1 :: i64(0x4667) // 3 0 12 12 7 +ICC_IGRPEN1_EL3 :: i64(0x7667) // 3 6 12 12 7 // ---- GICv3 hypervisor (ICH_*) ---- -ICH_HCR_EL2 :: i64(0x6CD8) // 3 4 12 11 0 -ICH_VTR_EL2 :: i64(0x6CD9) // 3 4 12 11 1 -ICH_MISR_EL2 :: i64(0x6CDA) // 3 4 12 11 2 -ICH_EISR_EL2 :: i64(0x6CDB) // 3 4 12 11 3 -ICH_ELRSR_EL2 :: i64(0x6CDD) // 3 4 12 11 5 -ICH_VMCR_EL2 :: i64(0x6CDF) // 3 4 12 11 7 +ICH_HCR_EL2 :: i64(0x6658) // 3 4 12 11 0 +ICH_VTR_EL2 :: i64(0x6659) // 3 4 12 11 1 +ICH_MISR_EL2 :: i64(0x665A) // 3 4 12 11 2 +ICH_EISR_EL2 :: i64(0x665B) // 3 4 12 11 3 +ICH_ELRSR_EL2 :: i64(0x665D) // 3 4 12 11 5 +ICH_VMCR_EL2 :: i64(0x665F) // 3 4 12 11 7 // ICH_LR0_EL2 .. ICH_LR15_EL2 = sysreg(3, 4, 12, 12+(n>>3), n & 7) sysreg_ich_lr :: #force_inline proc "contextless" (n: u32) -> i64 { @@ -348,26 +348,26 @@ sysreg_ich_ap1r :: #force_inline proc "contextless" (n: u32) -> i64 { } // ---- TRBE (Trace Buffer Extension, FEAT_TRBE) ---- -TRBLIMITR_EL1 :: i64(0x4B90) // 3 0 9 11 0 -TRBPTR_EL1 :: i64(0x4B91) // 3 0 9 11 1 -TRBBASER_EL1 :: i64(0x4B92) // 3 0 9 11 2 -TRBSR_EL1 :: i64(0x4B93) // 3 0 9 11 3 -TRBMAR_EL1 :: i64(0x4B94) // 3 0 9 11 4 -TRBTRG_EL1 :: i64(0x4B96) // 3 0 9 11 6 -TRBIDR_EL1 :: i64(0x4B97) // 3 0 9 11 7 +TRBLIMITR_EL1 :: i64(0x44D8) // 3 0 9 11 0 +TRBPTR_EL1 :: i64(0x44D9) // 3 0 9 11 1 +TRBBASER_EL1 :: i64(0x44DA) // 3 0 9 11 2 +TRBSR_EL1 :: i64(0x44DB) // 3 0 9 11 3 +TRBMAR_EL1 :: i64(0x44DC) // 3 0 9 11 4 +TRBTRG_EL1 :: i64(0x44DE) // 3 0 9 11 6 +TRBIDR_EL1 :: i64(0x44DF) // 3 0 9 11 7 // ---- SPE (Statistical Profiling Extension, FEAT_SPE) ---- -PMSCR_EL1 :: i64(0x4948) // 3 0 9 9 0 -PMSICR_EL1 :: i64(0x494A) // 3 0 9 9 2 -PMSIRR_EL1 :: i64(0x494B) // 3 0 9 9 3 -PMSFCR_EL1 :: i64(0x494C) // 3 0 9 9 4 -PMSEVFR_EL1 :: i64(0x494D) // 3 0 9 9 5 -PMSLATFR_EL1 :: i64(0x494E) // 3 0 9 9 6 -PMSIDR_EL1 :: i64(0x494F) // 3 0 9 9 7 -PMBLIMITR_EL1 :: i64(0x4950) // 3 0 9 10 0 -PMBPTR_EL1 :: i64(0x4951) // 3 0 9 10 1 -PMBSR_EL1 :: i64(0x4953) // 3 0 9 10 3 -PMBIDR_EL1 :: i64(0x4957) // 3 0 9 10 7 +PMSCR_EL1 :: i64(0x44C8) // 3 0 9 9 0 +PMSICR_EL1 :: i64(0x44CA) // 3 0 9 9 2 +PMSIRR_EL1 :: i64(0x44CB) // 3 0 9 9 3 +PMSFCR_EL1 :: i64(0x44CC) // 3 0 9 9 4 +PMSEVFR_EL1 :: i64(0x44CD) // 3 0 9 9 5 +PMSLATFR_EL1 :: i64(0x44CE) // 3 0 9 9 6 +PMSIDR_EL1 :: i64(0x44CF) // 3 0 9 9 7 +PMBLIMITR_EL1 :: i64(0x44D0) // 3 0 9 10 0 +PMBPTR_EL1 :: i64(0x44D1) // 3 0 9 10 1 +PMBSR_EL1 :: i64(0x44D3) // 3 0 9 10 3 +PMBIDR_EL1 :: i64(0x44D7) // 3 0 9 10 7 // ---- RAS (Reliability, Availability, Serviceability) ---- ERRSELR_EL1 :: i64(0x4299) // 3 0 5 3 1 @@ -382,7 +382,7 @@ ERXMISC2_EL1 :: i64(0x42AA) // 3 0 5 5 2 ERXMISC3_EL1 :: i64(0x42AB) // 3 0 5 5 3 DISR_EL1 :: i64(0x4609) // 3 0 12 1 1 VDISR_EL2 :: i64(0x6609) // 3 4 12 1 1 -VSESR_EL2 :: i64(0x628B) // 3 4 5 2 3 +VSESR_EL2 :: i64(0x6293) // 3 4 5 2 3 // ---- LOR (Limited Ordering Region) ---- LORC_EL1 :: i64(0x4523) // 3 0 10 4 3 @@ -392,11 +392,11 @@ LORN_EL1 :: i64(0x4522) // 3 0 10 4 2 LORSA_EL1 :: i64(0x4520) // 3 0 10 4 0 // ---- Translation result (returned by AT) ---- -PAR_EL1 :: i64(0x4380) // 3 0 7 4 0 +PAR_EL1 :: i64(0x43A0) // 3 0 7 4 0 // ---- RME (Realm Management Extension) sysregs ---- -GPCCR_EL3 :: i64(0x70B6) // 3 6 2 1 6 (Granule Protection Control) -GPTBR_EL3 :: i64(0x70B4) // 3 6 2 1 4 (Granule Protection Table Base) +GPCCR_EL3 :: i64(0x710E) // 3 6 2 1 6 (Granule Protection Control) +GPTBR_EL3 :: i64(0x710C) // 3 6 2 1 4 (Granule Protection Table Base) MFAR_EL3 :: i64(0x7305) // 3 6 6 0 5 (Multiple FAR) // ---- TPIDRRO_EL0 alias / extra thread pointers ---- @@ -413,9 +413,10 @@ PMUSERENR_EL0_REPEAT :: PMUSERENR_EL0 // re-export alias placeholder // MRS/MSR carry the system register as a packed 15-bit field, so a disassembly // has a number where an assembler wants a name. Sorted by value; binary search. // -// Six encodings have two names (a read view and a write view, or an alias -// added by a later extension); the first by source order wins, so a round-trip -// can come back spelled as the sibling. +// 1 encodings carry two names. Where the pair is a read view and a write +// view of one register (DBGDTRRX/DBGDTRTX) the read name wins, since MRS is +// the direction that has to print; the rest are genuine aliases and either +// name assembles, so a round-trip can come back spelled as the sibling. Sysreg_Name :: struct { value: u16, @@ -426,14 +427,15 @@ Sysreg_Name :: struct { SYSREG_NAMES := [?]Sysreg_Name{ {0x0010, "mdccint_el1"}, {0x0012, "mdscr_el1"}, + {0x0080, "mdrar_el1"}, {0x0084, "oslar_el1"}, {0x008C, "oslsr_el1"}, - {0x1080, "mdrar_el1"}, - {0x1A20, "dbgdtr_el0"}, - {0x1A28, "dbgdtrrx_el0"}, - {0x1BC6, "dbgclaimset_el1"}, - {0x1BCE, "dbgclaimclr_el1"}, - {0x1BF6, "dbgauthstatus_el1"}, + {0x00A4, "dbgprcr_el1"}, + {0x03C6, "dbgclaimset_el1"}, + {0x03CE, "dbgclaimclr_el1"}, + {0x03F6, "dbgauthstatus_el1"}, + {0x1820, "dbgdtr_el0"}, + {0x1828, "dbgdtrrx_el0"}, {0x4000, "midr_el1"}, {0x4005, "mpidr_el1"}, {0x4008, "id_pfr0_el1"}, @@ -450,10 +452,13 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x4013, "id_isar3_el1"}, {0x4014, "id_isar4_el1"}, {0x4015, "id_isar5_el1"}, + {0x4016, "id_mmfr4_el1"}, {0x4017, "id_isar6_el1"}, {0x4018, "mvfr0_el1"}, {0x4019, "mvfr1_el1"}, {0x401A, "mvfr2_el1"}, + {0x401C, "id_pfr2_el1"}, + {0x401E, "id_mmfr5_el1"}, {0x4020, "id_aa64pfr0_el1"}, {0x4021, "id_aa64pfr1_el1"}, {0x4024, "id_aa64zfr0_el1"}, @@ -463,29 +468,41 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x402A, "id_aa64dfr2_el1"}, {0x402C, "id_aa64afr0_el1"}, {0x402D, "id_aa64afr1_el1"}, - {0x402E, "id_mmfr5_el1"}, {0x4030, "id_aa64isar0_el1"}, {0x4031, "id_aa64isar1_el1"}, {0x4032, "id_aa64isar2_el1"}, {0x4033, "id_aa64isar3_el1"}, - {0x4036, "id_mmfr4_el1"}, {0x4038, "id_aa64mmfr0_el1"}, {0x4039, "id_aa64mmfr1_el1"}, {0x403A, "id_aa64mmfr2_el1"}, {0x4080, "sctlr_el1"}, {0x4081, "actlr_el1"}, {0x4082, "cpacr_el1"}, + {0x4085, "rgsr_el1"}, + {0x4086, "gcr_el1"}, + {0x4090, "zcr_el1"}, + {0x4096, "smcr_el1"}, {0x4100, "ttbr0_el1"}, {0x4101, "ttbr1_el1"}, + {0x4102, "tcr_el1"}, + {0x4108, "apiakeylo_el1"}, + {0x4109, "apiakeyhi_el1"}, + {0x410A, "apibkeylo_el1"}, + {0x410B, "apibkeyhi_el1"}, + {0x4110, "apdakeylo_el1"}, + {0x4111, "apdakeyhi_el1"}, + {0x4112, "apdbkeylo_el1"}, + {0x4113, "apdbkeyhi_el1"}, + {0x4118, "apgakeylo_el1"}, + {0x4119, "apgakeyhi_el1"}, {0x4200, "spsr_el1"}, {0x4201, "elr_el1"}, {0x4208, "sp_el0"}, - {0x4212, "current_el"}, - {0x4282, "tcr_el1"}, + {0x4212, "currentel"}, + {0x4230, "icc_pmr_el1"}, {0x4288, "afsr0_el1"}, {0x4289, "afsr1_el1"}, - {0x4290, "zcr_el1"}, - {0x4296, "smcr_el1"}, + {0x4290, "esr_el1"}, {0x4298, "erridr_el1"}, {0x4299, "errselr_el1"}, {0x42A0, "erxfr_el1"}, @@ -496,19 +513,31 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x42A9, "erxmisc1_el1"}, {0x42AA, "erxmisc2_el1"}, {0x42AB, "erxmisc3_el1"}, - {0x4300, "tfsr_el1"}, - {0x4301, "tfsre0_el1"}, - {0x4318, "apiakeylo_el1"}, - {0x4319, "apiakeyhi_el1"}, - {0x431A, "apibkeylo_el1"}, - {0x431B, "apibkeyhi_el1"}, - {0x4320, "apdakeylo_el1"}, - {0x4321, "apdakeyhi_el1"}, - {0x4322, "apdbkeylo_el1"}, - {0x4323, "apdbkeyhi_el1"}, - {0x4328, "apgakeylo_el1"}, - {0x4329, "apgakeyhi_el1"}, - {0x4380, "par_el1"}, + {0x42B0, "tfsr_el1"}, + {0x42B1, "tfsre0_el1"}, + {0x4300, "far_el1"}, + {0x4311, "prselr_el1"}, + {0x43A0, "par_el1"}, + {0x44C8, "pmscr_el1"}, + {0x44CA, "pmsicr_el1"}, + {0x44CB, "pmsirr_el1"}, + {0x44CC, "pmsfcr_el1"}, + {0x44CD, "pmsevfr_el1"}, + {0x44CE, "pmslatfr_el1"}, + {0x44CF, "pmsidr_el1"}, + {0x44D0, "pmblimitr_el1"}, + {0x44D1, "pmbptr_el1"}, + {0x44D3, "pmbsr_el1"}, + {0x44D7, "pmbidr_el1"}, + {0x44D8, "trblimitr_el1"}, + {0x44D9, "trbptr_el1"}, + {0x44DA, "trbbaser_el1"}, + {0x44DB, "trbsr_el1"}, + {0x44DC, "trbmar_el1"}, + {0x44DE, "trbtrg_el1"}, + {0x44DF, "trbidr_el1"}, + {0x44F1, "pmintenset_el1"}, + {0x44F2, "pmintenclr_el1"}, {0x4510, "mair_el1"}, {0x4518, "amair_el1"}, {0x4520, "lorsa_el1"}, @@ -519,64 +548,41 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x4600, "vbar_el1"}, {0x4608, "isr_el1"}, {0x4609, "disr_el1"}, - {0x4630, "icc_pmr_el1"}, + {0x4640, "icc_iar0_el1"}, + {0x4641, "icc_eoir0_el1"}, + {0x4642, "icc_hppir0_el1"}, + {0x4643, "icc_bpr0_el1"}, + {0x4659, "icc_dir_el1"}, + {0x465B, "icc_rpr_el1"}, + {0x465D, "icc_sgi1r_el1"}, + {0x465E, "icc_asgi1r_el1"}, + {0x465F, "icc_sgi0r_el1"}, + {0x4660, "icc_iar1_el1"}, + {0x4661, "icc_eoir1_el1"}, + {0x4662, "icc_hppir1_el1"}, + {0x4663, "icc_bpr1_el1"}, + {0x4664, "icc_ctlr_el1"}, + {0x4665, "icc_sre_el1"}, + {0x4666, "icc_igrpen0_el1"}, + {0x4667, "icc_igrpen1_el1"}, {0x4681, "contextidr_el1"}, {0x4684, "tpidr_el1"}, {0x4708, "cntkctl_el1"}, {0x4800, "ccsidr_el1"}, {0x4801, "clidr_el1"}, {0x4804, "gmid_el1"}, - {0x4948, "pmscr_el1"}, - {0x494A, "pmsicr_el1"}, - {0x494B, "pmsirr_el1"}, - {0x494C, "pmsfcr_el1"}, - {0x494D, "pmsevfr_el1"}, - {0x494E, "pmslatfr_el1"}, - {0x494F, "pmsidr_el1"}, - {0x4950, "pmblimitr_el1"}, - {0x4951, "pmbptr_el1"}, - {0x4953, "pmbsr_el1"}, - {0x4957, "pmbidr_el1"}, - {0x4B90, "trblimitr_el1"}, - {0x4B91, "trbptr_el1"}, - {0x4B92, "trbbaser_el1"}, - {0x4B93, "trbsr_el1"}, - {0x4B94, "trbmar_el1"}, - {0x4B96, "trbtrg_el1"}, - {0x4B97, "trbidr_el1"}, - {0x4C40, "icc_iar0_el1"}, - {0x4C41, "icc_eoir0_el1"}, - {0x4C42, "icc_hppir0_el1"}, - {0x4C43, "icc_bpr0_el1"}, - {0x4C59, "icc_dir_el1"}, - {0x4C5B, "icc_rpr_el1"}, - {0x4C60, "icc_iar1_el1"}, - {0x4C61, "icc_eoir1_el1"}, - {0x4C62, "icc_hppir1_el1"}, - {0x4C63, "icc_bpr1_el1"}, - {0x4C64, "icc_ctlr_el1"}, - {0x4C65, "icc_sre_el1"}, - {0x4C66, "icc_igrpen0_el1"}, - {0x4C67, "icc_igrpen1_el1"}, - {0x4CE1, "pmintenset_el1"}, - {0x4CE2, "pmintenclr_el1"}, {0x5000, "csselr_el1"}, - {0x5290, "esr_el1"}, - {0x5300, "far_el1"}, {0x5801, "ctr_el0"}, {0x5807, "dczid_el0"}, {0x5920, "rndr"}, {0x5921, "rndrrs"}, {0x5A10, "nzcv"}, {0x5A11, "daif"}, + {0x5A12, "svcr"}, {0x5A20, "fpcr"}, {0x5A21, "fpsr"}, - {0x5A22, "svcr"}, {0x5A28, "dspsr_el0"}, {0x5A29, "dlr_el0"}, - {0x5CDD, "icc_sgi1r_el1"}, - {0x5CDE, "icc_asgi1r_el1"}, - {0x5CDF, "icc_sgi0r_el1"}, {0x5CE0, "pmcr_el0"}, {0x5CE1, "pmcntenset_el0"}, {0x5CE2, "pmcntenclr_el0"}, @@ -604,19 +610,29 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x6088, "hcr_el2"}, {0x6089, "mdcr_el2"}, {0x608B, "hstr_el2"}, + {0x6090, "zcr_el2"}, + {0x6096, "smcr_el2"}, {0x6108, "vttbr_el2"}, {0x610A, "vtcr_el2"}, {0x6180, "dacr32_el2"}, {0x6200, "spsr_el2"}, {0x6201, "elr_el2"}, {0x6208, "sp_el1"}, - {0x628B, "vsesr_el2"}, {0x6290, "esr_el2"}, - {0x6296, "smcr_el2"}, + {0x6293, "vsesr_el2"}, {0x6298, "fpexc32_el2"}, {0x6300, "far_el2"}, {0x6600, "vbar_el2"}, {0x6609, "vdisr_el2"}, + {0x664D, "icc_sre_el2"}, + {0x6658, "ich_hcr_el2"}, + {0x6659, "ich_vtr_el2"}, + {0x665A, "ich_misr_el2"}, + {0x665B, "ich_eisr_el2"}, + {0x665D, "ich_elrsr_el2"}, + {0x665F, "ich_vmcr_el2"}, + {0x6682, "tpidr_el2"}, + {0x6703, "cntvoff_el2"}, {0x6708, "cnthctl_el2"}, {0x6710, "cnthp_tval_el2"}, {0x6711, "cnthp_ctl_el2"}, @@ -624,27 +640,18 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x6718, "cnthv_tval_el2"}, {0x6719, "cnthv_ctl_el2"}, {0x671A, "cnthv_cval_el2"}, - {0x671B, "cntvoff_el2"}, - {0x6C65, "icc_sre_el2"}, - {0x6CD8, "ich_hcr_el2"}, - {0x6CD9, "ich_vtr_el2"}, - {0x6CDA, "ich_misr_el2"}, - {0x6CDB, "ich_eisr_el2"}, - {0x6CDD, "ich_elrsr_el2"}, - {0x6CDF, "ich_vmcr_el2"}, - {0x6E82, "tpidr_el2"}, {0x7080, "sctlr_el3"}, - {0x70B4, "gptbr_el3"}, - {0x70B6, "gpccr_el3"}, + {0x7090, "zcr_el3"}, + {0x710C, "gptbr_el3"}, + {0x710E, "gpccr_el3"}, {0x7200, "spsr_el3"}, {0x7201, "elr_el3"}, - {0x7290, "zcr_el3"}, {0x7305, "mfar_el3"}, {0x7600, "vbar_el3"}, + {0x7664, "icc_ctlr_el3"}, + {0x7665, "icc_sre_el3"}, + {0x7667, "icc_igrpen1_el3"}, {0x7682, "tpidr_el3"}, - {0x7C64, "icc_ctlr_el3"}, - {0x7C65, "icc_sre_el3"}, - {0x7C67, "icc_igrpen1_el3"}, {0x7F10, "cntps_tval_el1"}, {0x7F11, "cntps_ctl_el1"}, {0x7F12, "cntps_cval_el1"}, From 3b3bba54a80917316dd9c434a6324b54155a8997 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 15:06:12 +0100 Subject: [PATCH 29/89] Update for new mnemonics --- src/asm_tables_arm64.cpp | 2526 +++++++++++++++++++------------------- src/check_asm.cpp | 4 + 2 files changed, 1278 insertions(+), 1252 deletions(-) diff --git a/src/asm_tables_arm64.cpp b/src/asm_tables_arm64.cpp index 9ddafd9d2..804b24fb2 100644 --- a/src/asm_tables_arm64.cpp +++ b/src/asm_tables_arm64.cpp @@ -14,53 +14,55 @@ struct Asm_arm64 { M_INVALID, M_ADD, M_ADDS, M_SUB, M_SUBS, M_MOVZ, M_MOVN, M_MOVK, M_ADR, M_ADRP, M_AND, M_ANDS, M_ORR, M_EOR, M_BIC, M_BICS, M_ORN, M_EON, M_LSL, M_LSR, M_ASR, M_ROR, M_UDIV, M_SDIV, M_MADD, M_MSUB, M_SMADDL, M_SMSUBL, M_UMADDL, M_UMSUBL, M_SMULH, M_UMULH, M_CLZ, M_CLS, M_RBIT, M_REV, M_REV16, M_REV32, M_CSEL, M_CSINC, M_CSINV, M_CSNEG, M_CCMP, M_CCMN, M_EXTR, M_B, M_BL, M_BR, - M_BLR, M_RET, M_B_COND, M_CBZ, M_CBNZ, M_TBZ, M_TBNZ, M_LDR, M_STR, M_LDRB, M_STRB, M_LDRSB, M_LDRH, M_STRH, M_LDRSH, M_LDRSW, - M_LDP, M_STP, M_LDPSW, M_LDAR, M_STLR, M_LDARB, M_STLRB, M_LDARH, M_STLRH, M_LDXR, M_STXR, M_LDAXR, M_STLXR, M_NOP, M_YIELD, M_WFE, - M_WFI, M_SEV, M_SEVL, M_HINT, M_MRS, M_MSR, M_ISB, M_DSB, M_DMB, M_SVC, M_HVC, M_SMC, M_BRK, M_HLT, M_ERET, M_FMOV, - M_FABS, M_FNEG, M_FSQRT, M_FADD, M_FSUB, M_FMUL, M_FDIV, M_FNMUL, M_FMADD, M_FMSUB, M_FNMADD, M_FNMSUB, M_FCMP, M_FCMPE, M_FCSEL, M_FMAX, - M_FMIN, M_FMAXNM, M_FMINNM, M_FCVT, M_SCVTF, M_UCVTF, M_FCVTZS, M_FCVTZU, M_FCVTAS, M_FCVTAU, M_FCVTNS, M_FCVTNU, M_FCVTPS, M_FCVTPU, M_FCVTMS, M_FCVTMU, - M_FRINTA, M_FRINTI, M_FRINTM, M_FRINTN, M_FRINTP, M_FRINTX, M_FRINTZ, M_TST, M_LDUR, M_STUR, M_LDURB, M_STURB, M_LDURSB, M_LDURH, M_STURH, M_LDURSH, - M_LDURSW, M_LDNP, M_STNP, M_LDXP, M_STXP, M_LDAXP, M_STLXP, M_LDXRB, M_STXRB, M_LDAXRB, M_STLXRB, M_LDXRH, M_STXRH, M_LDAXRH, M_STLXRH, M_LDAPR, - M_LDAPRB, M_LDAPRH, M_LDADD, M_LDADDA, M_LDADDL, M_LDADDAL, M_LDCLR, M_LDCLRA, M_LDCLRL, M_LDCLRAL, M_LDEOR, M_LDEORA, M_LDEORL, M_LDEORAL, M_LDSET, M_LDSETA, - M_LDSETL, M_LDSETAL, M_LDSMAX, M_LDSMAXA, M_LDSMAXL, M_LDSMAXAL, M_LDSMIN, M_LDSMINA, M_LDSMINL, M_LDSMINAL, M_LDUMAX, M_LDUMAXA, M_LDUMAXL, M_LDUMAXAL, M_LDUMIN, M_LDUMINA, - M_LDUMINL, M_LDUMINAL, M_SWP, M_SWPA, M_SWPL, M_SWPAL, M_CAS, M_CASA, M_CASL, M_CASAL, M_CASB, M_CASAB, M_CASLB, M_CASALB, M_CASH, M_CASAH, - M_CASLH, M_CASALH, M_CASP, M_CASPA, M_CASPL, M_CASPAL, M_PACIA, M_PACIB, M_PACDA, M_PACDB, M_PACIZA, M_PACIZB, M_PACDZA, M_PACDZB, M_AUTIA, M_AUTIB, - M_AUTDA, M_AUTDB, M_AUTIZA, M_AUTIZB, M_AUTDZA, M_AUTDZB, M_PACIASP, M_PACIBSP, M_AUTIASP, M_AUTIBSP, M_PACIA1716, M_PACIB1716, M_AUTIA1716, M_AUTIB1716, M_PACGA, M_XPACI, - M_XPACD, M_XPACLRI, M_RETAA, M_RETAB, M_BRAA, M_BRAB, M_BRAAZ, M_BRABZ, M_BLRAA, M_BLRAB, M_BLRAAZ, M_BLRABZ, M_ERETAA, M_ERETAB, M_BTI, M_IRG, - M_ADDG, M_SUBG, M_GMI, M_SUBP, M_SUBPS, M_LDG, M_STG, M_ST2G, M_STZG, M_STZ2G, M_STGP, M_LDGM, M_STGM, M_STZGM, M_CRC32B, M_CRC32H, - M_CRC32W, M_CRC32X, M_CRC32CB, M_CRC32CH, M_CRC32CW, M_CRC32CX, M_AESE, M_AESD, M_AESMC, M_AESIMC, M_SHA1H, M_SHA1C, M_SHA1P, M_SHA1M, M_SHA1SU0, M_SHA1SU1, - M_SHA256H, M_SHA256H2, M_SHA256SU0, M_SHA256SU1, M_SHA512H, M_SHA512H2, M_SHA512SU0, M_SHA512SU1, M_EOR3, M_BCAX, M_RAX1, M_XAR, M_SM3PARTW1, M_SM3PARTW2, M_SM3SS1, M_SM3TT1A, - M_SM3TT1B, M_SM3TT2A, M_SM3TT2B, M_SM4E, M_SM4EKEY, M_PMULL, M_PMULL2, M_BFCVT, M_BFDOT, M_BFMMLA, M_BFMLALB, M_BFMLALT, M_BFCVTN, M_BFCVTN2, M_MUL, M_MLA, - M_MLS, M_NEG, M_ABS, M_SHADD, M_UHADD, M_SHSUB, M_UHSUB, M_SRHADD, M_URHADD, M_SQADD, M_UQADD, M_SQSUB, M_UQSUB, M_SMAX, M_UMAX, M_SMIN, - M_UMIN, M_SABD, M_UABD, M_SABA, M_UABA, M_ADDP, M_ADDV, M_SADDLP, M_UADDLP, M_SADALP, M_UADALP, M_SADDLV, M_UADDLV, M_SMAXV, M_UMAXV, M_SMINV, - M_UMINV, M_SMAXP, M_UMAXP, M_SMINP, M_UMINP, M_SADDL, M_SADDL2, M_UADDL, M_UADDL2, M_SSUBL, M_SSUBL2, M_USUBL, M_USUBL2, M_SADDW, M_SADDW2, M_UADDW, - M_UADDW2, M_SSUBW, M_SSUBW2, M_USUBW, M_USUBW2, M_RADDHN, M_RADDHN2, M_RSUBHN, M_RSUBHN2, M_ADDHN, M_ADDHN2, M_SUBHN, M_SUBHN2, M_XTN, M_XTN2, M_SQXTN, - M_SQXTN2, M_UQXTN, M_UQXTN2, M_SQXTUN, M_SQXTUN2, M_SMULL, M_SMULL2, M_UMULL, M_UMULL2, M_SMLAL, M_SMLAL2, M_UMLAL, M_UMLAL2, M_SMLSL, M_SMLSL2, M_UMLSL, - M_UMLSL2, M_SQDMULL, M_SQDMULL2, M_SQDMLAL, M_SQDMLAL2, M_SQDMLSL, M_SQDMLSL2, M_SQDMULH, M_SQRDMULH, M_SDOT, M_UDOT, M_USDOT, M_FMLA, M_FMLS, M_FMULX, M_FMAXP, - M_FMINP, M_FMAXNMP, M_FMINNMP, M_FMAXV, M_FMINV, M_FMAXNMV, M_FMINNMV, M_FRECPE, M_FRSQRTE, M_FRECPS, M_FRSQRTS, M_FRECPX, M_FADDP, M_FCVTL, M_FCVTL2, M_FCVTN, - M_FCVTN2, M_FCVTXN, M_FCVTXN2, M_FCMEQ, M_FCMGE, M_FCMGT, M_FCMLE, M_FCMLT, M_FACGE, M_FACGT, M_CMEQ, M_CMGE, M_CMGT, M_CMHI, M_CMHS, M_CMLE, - M_CMLT, M_CMTST, M_MVN, M_BIT, M_BIF, M_BSL, M_SHL, M_SQSHL, M_SQSHLU, M_SRSHL, M_URSHL, M_SSHR, M_USHR, M_SSRA, M_USRA, M_SRSHR, - M_URSHR, M_SRSRA, M_URSRA, M_SSHL, M_USHL, M_SLI, M_SRI, M_SSHLL, M_SSHLL2, M_USHLL, M_USHLL2, M_SXTL, M_SXTL2, M_UXTL, M_UXTL2, M_SHRN, - M_SHRN2, M_RSHRN, M_RSHRN2, M_SQSHRN, M_SQSHRN2, M_UQSHRN, M_UQSHRN2, M_SQRSHRN, M_SQRSHRN2, M_UQRSHRN, M_UQRSHRN2, M_SQSHRUN, M_SQSHRUN2, M_SQRSHRUN, M_SQRSHRUN2, M_DUP, - M_INS, M_MOV, M_EXT, M_TBL, M_TBX, M_ZIP1, M_ZIP2, M_UZP1, M_UZP2, M_TRN1, M_TRN2, M_NOT, M_REV64, M_CNT, M_URECPE, M_URSQRTE, - M_MOVI, M_MVNI, M_LD1, M_LD2, M_LD3, M_LD4, M_ST1, M_ST2, M_ST3, M_ST4, M_LD1R, M_LD2R, M_LD3R, M_LD4R, M_SUBR, M_ASRR, - M_LSLR, M_LSRR, M_FTSMUL, M_FSUBR, M_FDIVR, M_FNMLA, M_FNMLS, M_NAND, M_NOR, M_SEL, M_ORRS, M_EORS, M_NANDS, M_NORS, M_ORNS, M_MOVS, - M_PTRUE, M_PTRUES, M_PFALSE, M_PFIRST, M_PNEXT, M_BRKA, M_BRKB, M_BRKAS, M_BRKBS, M_BRKPA, M_BRKPB, M_BRKN, M_RDFFR, M_WRFFR, M_SETFFR, M_CMPEQ, - M_CMPNE, M_CMPGE, M_CMPGT, M_CMPLE, M_CMPLT, M_CMPHI, M_CMPHS, M_CMPLO, M_CMPLS, M_FCMNE, M_FCMUO, M_INSR, M_CPY, M_COMPACT, M_LD1B, M_LD1H, - M_LD1W, M_LD1D, M_LD1SB, M_LD1SH, M_LD1SW, M_ST1B, M_ST1H, M_ST1W, M_ST1D, M_LDFF1B, M_LDFF1H, M_LDFF1W, M_LDFF1D, M_WHILEGE, M_WHILEGT, M_WHILELE, - M_WHILELT, M_WHILEHI, M_WHILEHS, M_WHILELO, M_WHILELS, M_SQRDMLAH, M_SQRDMLSH, M_ADCLB, M_ADCLT, M_SBCLB, M_SBCLT, M_TBL2, M_MATCH, M_NMATCH, M_HISTCNT, M_HISTSEG, - M_SMSTART, M_SMSTOP, M_RDSVL, M_ADDHA, M_ADDVA, M_ZERO, M_FMOPA, M_FMOPS, M_BFMOPA, M_BFMOPS, M_SMOPA, M_SMOPS, M_UMOPA, M_UMOPS, M_USMOPA, M_SUMOPA, - M_LD1Q, M_ST1Q, M_MOVA, M_FCMLA, M_FCADD, M_PRFB, M_PRFH, M_PRFW, M_PRFD, M_LDNT1B, M_LDNT1H, M_LDNT1W, M_LDNT1D, M_STNT1B, M_STNT1H, M_STNT1W, - M_STNT1D, M_SPLICE, M_INDEX, M_BSL1N, M_BSL2N, M_NBSL, M_PMUL, M_PMULLB, M_PMULLT, M_BFCVTNT, M_LDRAA, M_LDRAB, M_TSTART, M_TCOMMIT, M_TCANCEL, M_TTEST, - M_WFET, M_WFIT, M_BC_COND, M_UXTB, M_UXTH, M_UXTW, M_SXTB, M_SXTH, M_SXTW, M_ADC, M_ADCS, M_SBC, M_SBCS, M_NGC, M_NGCS, M_LDAPUR, - M_STLUR, M_LDAPURB, M_STLURB, M_LDAPURH, M_STLURH, M_LDAPURSB, M_LDAPURSH, M_LDAPURSW, M_BFADD, M_BFSUB, M_BFMUL, M_BFMLA, M_BFMLS, M_SB, M_CSDB, M_DGH, - M_PSB_CSYNC, M_TSB_CSYNC, M_BTI_J, M_BTI_C, M_BTI_JC, M_BFCLAMP, M_BFMAXNM, M_BFMINNM, M_LUTI2, M_LUTI4, M_ZIP, M_UZP, M_TLBI_RPALOS, M_TLBI_RPAOS, M_AT_S1E1A, M_DC_CIPAPA, - M_DC_CIGDPAPA, M_TLBI_PAALL, M_TLBI_PAALLOS, M_AMX_LDX, M_AMX_LDY, M_AMX_STX, M_AMX_STY, M_AMX_LDZ, M_AMX_STZ, M_AMX_LDZI, M_AMX_STZI, M_AMX_EXTRX, M_AMX_EXTRY, M_AMX_FMA64, M_AMX_FMS64, M_AMX_FMA32, - M_AMX_FMS32, M_AMX_MAC16, M_AMX_FMA16, M_AMX_FMS16, M_AMX_SET, M_AMX_CLR, M_AMX_VECINT, M_AMX_VECFP, M_AMX_MATINT, M_AMX_MATFP, M_AMX_GENLUT, M_CPYP, M_CPYM, M_CPYE, M_CPYFP, M_CPYFM, - M_CPYFE, M_SETP, M_SETM, M_SETE, M_DC_IVAC, M_DC_ISW, M_DC_CSW, M_DC_CISW, M_DC_ZVA, M_DC_CVAC, M_DC_CVAU, M_DC_CIVAC, M_IC_IALLUIS, M_IC_IALLU, M_IC_IVAU, M_AT_S1E1R, - M_AT_S1E1W, M_AT_S1E0R, M_AT_S1E0W, M_AT_S1E2R, M_AT_S1E2W, M_AT_S1E3R, M_AT_S1E3W, M_AT_S12E1R, M_AT_S12E1W, M_AT_S12E0R, M_AT_S12E0W, M_TLBI_VMALLE1, M_TLBI_VMALLE1IS, M_TLBI_VAE1, M_TLBI_VAE1IS, M_TLBI_ASIDE1, - M_TLBI_ASIDE1IS, M_TLBI_VAAE1, M_TLBI_VAAE1IS, M_TLBI_VALE1, M_TLBI_VALE1IS, M_TLBI_VAALE1, M_TLBI_VAALE1IS, M_TLBI_ALLE1, M_TLBI_ALLE1IS, M_TLBI_ALLE2, M_TLBI_ALLE2IS, M_TLBI_ALLE3, M_TLBI_ALLE3IS, M_PRFM, M_PRFUM, M_NEGS, - M_CMP, M_CMN, + M_BLR, M_RET, M_B_EQ, M_B_NE, M_B_CS, M_B_CC, M_B_MI, M_B_PL, M_B_VS, M_B_VC, M_B_HI, M_B_LS, M_B_GE, M_B_LT, M_B_GT, M_B_LE, + M_B_AL, M_B_NV, M_CBZ, M_CBNZ, M_TBZ, M_TBNZ, M_LDR, M_STR, M_LDRB, M_STRB, M_LDRSB, M_LDRH, M_STRH, M_LDRSH, M_LDRSW, M_LDP, + M_STP, M_LDPSW, M_LDAR, M_STLR, M_LDARB, M_STLRB, M_LDARH, M_STLRH, M_LDXR, M_STXR, M_LDAXR, M_STLXR, M_NOP, M_YIELD, M_WFE, M_WFI, + M_SEV, M_SEVL, M_HINT, M_MRS, M_MSR, M_ISB, M_DSB, M_DMB, M_SVC, M_HVC, M_SMC, M_BRK, M_HLT, M_ERET, M_FMOV, M_FABS, + M_FNEG, M_FSQRT, M_FADD, M_FSUB, M_FMUL, M_FDIV, M_FNMUL, M_FMADD, M_FMSUB, M_FNMADD, M_FNMSUB, M_FCMP, M_FCMPE, M_FCSEL, M_FMAX, M_FMIN, + M_FMAXNM, M_FMINNM, M_FCVT, M_SCVTF, M_UCVTF, M_FCVTZS, M_FCVTZU, M_FCVTAS, M_FCVTAU, M_FCVTNS, M_FCVTNU, M_FCVTPS, M_FCVTPU, M_FCVTMS, M_FCVTMU, M_FRINTA, + M_FRINTI, M_FRINTM, M_FRINTN, M_FRINTP, M_FRINTX, M_FRINTZ, M_TST, M_LDUR, M_STUR, M_LDURB, M_STURB, M_LDURSB, M_LDURH, M_STURH, M_LDURSH, M_LDURSW, + M_LDNP, M_STNP, M_LDXP, M_STXP, M_LDAXP, M_STLXP, M_LDXRB, M_STXRB, M_LDAXRB, M_STLXRB, M_LDXRH, M_STXRH, M_LDAXRH, M_STLXRH, M_LDAPR, M_LDAPRB, + M_LDAPRH, M_LDADD, M_LDADDA, M_LDADDL, M_LDADDAL, M_LDCLR, M_LDCLRA, M_LDCLRL, M_LDCLRAL, M_LDEOR, M_LDEORA, M_LDEORL, M_LDEORAL, M_LDSET, M_LDSETA, M_LDSETL, + M_LDSETAL, M_LDSMAX, M_LDSMAXA, M_LDSMAXL, M_LDSMAXAL, M_LDSMIN, M_LDSMINA, M_LDSMINL, M_LDSMINAL, M_LDUMAX, M_LDUMAXA, M_LDUMAXL, M_LDUMAXAL, M_LDUMIN, M_LDUMINA, M_LDUMINL, + M_LDUMINAL, M_SWP, M_SWPA, M_SWPL, M_SWPAL, M_CAS, M_CASA, M_CASL, M_CASAL, M_CASB, M_CASAB, M_CASLB, M_CASALB, M_CASH, M_CASAH, M_CASLH, + M_CASALH, M_CASP, M_CASPA, M_CASPL, M_CASPAL, M_PACIA, M_PACIB, M_PACDA, M_PACDB, M_PACIZA, M_PACIZB, M_PACDZA, M_PACDZB, M_AUTIA, M_AUTIB, M_AUTDA, + M_AUTDB, M_AUTIZA, M_AUTIZB, M_AUTDZA, M_AUTDZB, M_PACIASP, M_PACIBSP, M_AUTIASP, M_AUTIBSP, M_PACIA1716, M_PACIB1716, M_AUTIA1716, M_AUTIB1716, M_PACGA, M_XPACI, M_XPACD, + M_XPACLRI, M_RETAA, M_RETAB, M_BRAA, M_BRAB, M_BRAAZ, M_BRABZ, M_BLRAA, M_BLRAB, M_BLRAAZ, M_BLRABZ, M_ERETAA, M_ERETAB, M_BTI, M_IRG, M_ADDG, + M_SUBG, M_GMI, M_SUBP, M_SUBPS, M_LDG, M_STG, M_ST2G, M_STZG, M_STZ2G, M_STGP, M_LDGM, M_STGM, M_STZGM, M_CRC32B, M_CRC32H, M_CRC32W, + M_CRC32X, M_CRC32CB, M_CRC32CH, M_CRC32CW, M_CRC32CX, M_AESE, M_AESD, M_AESMC, M_AESIMC, M_SHA1H, M_SHA1C, M_SHA1P, M_SHA1M, M_SHA1SU0, M_SHA1SU1, M_SHA256H, + M_SHA256H2, M_SHA256SU0, M_SHA256SU1, M_SHA512H, M_SHA512H2, M_SHA512SU0, M_SHA512SU1, M_EOR3, M_BCAX, M_RAX1, M_XAR, M_SM3PARTW1, M_SM3PARTW2, M_SM3SS1, M_SM3TT1A, M_SM3TT1B, + M_SM3TT2A, M_SM3TT2B, M_SM4E, M_SM4EKEY, M_PMULL, M_PMULL2, M_BFCVT, M_BFDOT, M_BFMMLA, M_BFMLALB, M_BFMLALT, M_BFCVTN, M_BFCVTN2, M_MUL, M_MLA, M_MLS, + M_NEG, M_ABS, M_SHADD, M_UHADD, M_SHSUB, M_UHSUB, M_SRHADD, M_URHADD, M_SQADD, M_UQADD, M_SQSUB, M_UQSUB, M_SMAX, M_UMAX, M_SMIN, M_UMIN, + M_SABD, M_UABD, M_SABA, M_UABA, M_ADDP, M_ADDV, M_SADDLP, M_UADDLP, M_SADALP, M_UADALP, M_SADDLV, M_UADDLV, M_SMAXV, M_UMAXV, M_SMINV, M_UMINV, + M_SMAXP, M_UMAXP, M_SMINP, M_UMINP, M_SADDL, M_SADDL2, M_UADDL, M_UADDL2, M_SSUBL, M_SSUBL2, M_USUBL, M_USUBL2, M_SADDW, M_SADDW2, M_UADDW, M_UADDW2, + M_SSUBW, M_SSUBW2, M_USUBW, M_USUBW2, M_RADDHN, M_RADDHN2, M_RSUBHN, M_RSUBHN2, M_ADDHN, M_ADDHN2, M_SUBHN, M_SUBHN2, M_XTN, M_XTN2, M_SQXTN, M_SQXTN2, + M_UQXTN, M_UQXTN2, M_SQXTUN, M_SQXTUN2, M_SMULL, M_SMULL2, M_UMULL, M_UMULL2, M_SMLAL, M_SMLAL2, M_UMLAL, M_UMLAL2, M_SMLSL, M_SMLSL2, M_UMLSL, M_UMLSL2, + M_SQDMULL, M_SQDMULL2, M_SQDMLAL, M_SQDMLAL2, M_SQDMLSL, M_SQDMLSL2, M_SQDMULH, M_SQRDMULH, M_SDOT, M_UDOT, M_USDOT, M_FMLA, M_FMLS, M_FMULX, M_FMAXP, M_FMINP, + M_FMAXNMP, M_FMINNMP, M_FMAXV, M_FMINV, M_FMAXNMV, M_FMINNMV, M_FRECPE, M_FRSQRTE, M_FRECPS, M_FRSQRTS, M_FRECPX, M_FADDP, M_FCVTL, M_FCVTL2, M_FCVTN, M_FCVTN2, + M_FCVTXN, M_FCVTXN2, M_FCMEQ, M_FCMGE, M_FCMGT, M_FCMLE, M_FCMLT, M_FACGE, M_FACGT, M_CMEQ, M_CMGE, M_CMGT, M_CMHI, M_CMHS, M_CMLE, M_CMLT, + M_CMTST, M_MVN, M_BIT, M_BIF, M_BSL, M_SHL, M_SQSHL, M_SQSHLU, M_SRSHL, M_URSHL, M_SSHR, M_USHR, M_SSRA, M_USRA, M_SRSHR, M_URSHR, + M_SRSRA, M_URSRA, M_SSHL, M_USHL, M_SLI, M_SRI, M_SSHLL, M_SSHLL2, M_USHLL, M_USHLL2, M_SXTL, M_SXTL2, M_UXTL, M_UXTL2, M_SHRN, M_SHRN2, + M_RSHRN, M_RSHRN2, M_SQSHRN, M_SQSHRN2, M_UQSHRN, M_UQSHRN2, M_SQRSHRN, M_SQRSHRN2, M_UQRSHRN, M_UQRSHRN2, M_SQSHRUN, M_SQSHRUN2, M_SQRSHRUN, M_SQRSHRUN2, M_DUP, M_INS, + M_MOV, M_EXT, M_TBL, M_TBX, M_ZIP1, M_ZIP2, M_UZP1, M_UZP2, M_TRN1, M_TRN2, M_NOT, M_REV64, M_CNT, M_URECPE, M_URSQRTE, M_MOVI, + M_MVNI, M_LD1, M_LD2, M_LD3, M_LD4, M_ST1, M_ST2, M_ST3, M_ST4, M_LD1R, M_LD2R, M_LD3R, M_LD4R, M_SUBR, M_ASRR, M_LSLR, + M_LSRR, M_FTSMUL, M_FSUBR, M_FDIVR, M_FNMLA, M_FNMLS, M_NAND, M_NOR, M_SEL, M_ORRS, M_EORS, M_NANDS, M_NORS, M_ORNS, M_MOVS, M_PTRUE, + M_PTRUES, M_PFALSE, M_PFIRST, M_PNEXT, M_BRKA, M_BRKB, M_BRKAS, M_BRKBS, M_BRKPA, M_BRKPB, M_BRKN, M_RDFFR, M_WRFFR, M_SETFFR, M_CMPEQ, M_CMPNE, + M_CMPGE, M_CMPGT, M_CMPLE, M_CMPLT, M_CMPHI, M_CMPHS, M_CMPLO, M_CMPLS, M_FCMNE, M_FCMUO, M_INSR, M_CPY, M_COMPACT, M_LD1B, M_LD1H, M_LD1W, + M_LD1D, M_LD1SB, M_LD1SH, M_LD1SW, M_ST1B, M_ST1H, M_ST1W, M_ST1D, M_LDFF1B, M_LDFF1H, M_LDFF1W, M_LDFF1D, M_WHILEGE, M_WHILEGT, M_WHILELE, M_WHILELT, + M_WHILEHI, M_WHILEHS, M_WHILELO, M_WHILELS, M_SQRDMLAH, M_SQRDMLSH, M_ADCLB, M_ADCLT, M_SBCLB, M_SBCLT, M_TBL2, M_MATCH, M_NMATCH, M_HISTCNT, M_HISTSEG, M_SMSTART, + M_SMSTOP, M_RDSVL, M_ADDHA, M_ADDVA, M_ZERO, M_FMOPA, M_FMOPS, M_BFMOPA, M_BFMOPS, M_SMOPA, M_SMOPS, M_UMOPA, M_UMOPS, M_USMOPA, M_SUMOPA, M_LD1Q, + M_ST1Q, M_MOVA, M_FCMLA, M_FCADD, M_PRFB, M_PRFH, M_PRFW, M_PRFD, M_LDNT1B, M_LDNT1H, M_LDNT1W, M_LDNT1D, M_STNT1B, M_STNT1H, M_STNT1W, M_STNT1D, + M_SPLICE, M_INDEX, M_BSL1N, M_BSL2N, M_NBSL, M_PMUL, M_PMULLB, M_PMULLT, M_BFCVTNT, M_LDRAA, M_LDRAB, M_TSTART, M_TCOMMIT, M_TCANCEL, M_TTEST, M_WFET, + M_WFIT, M_BC_EQ, M_BC_NE, M_BC_CS, M_BC_CC, M_BC_MI, M_BC_PL, M_BC_VS, M_BC_VC, M_BC_HI, M_BC_LS, M_BC_GE, M_BC_LT, M_BC_GT, M_BC_LE, M_BC_AL, + M_BC_NV, M_UXTB, M_UXTH, M_UXTW, M_SXTB, M_SXTH, M_SXTW, M_ADC, M_ADCS, M_SBC, M_SBCS, M_NGC, M_NGCS, M_LDAPUR, M_STLUR, M_LDAPURB, + M_STLURB, M_LDAPURH, M_STLURH, M_LDAPURSB, M_LDAPURSH, M_LDAPURSW, M_BFADD, M_BFSUB, M_BFMUL, M_BFMLA, M_BFMLS, M_SB, M_CSDB, M_DGH, M_PSB_CSYNC, M_TSB_CSYNC, + M_BTI_J, M_BTI_C, M_BTI_JC, M_BFCLAMP, M_BFMAXNM, M_BFMINNM, M_LUTI2, M_LUTI4, M_ZIP, M_UZP, M_TLBI_RPALOS, M_TLBI_RPAOS, M_AT_S1E1A, M_DC_CIPAPA, M_DC_CIGDPAPA, M_TLBI_PAALL, + M_TLBI_PAALLOS, M_AMX_LDX, M_AMX_LDY, M_AMX_STX, M_AMX_STY, M_AMX_LDZ, M_AMX_STZ, M_AMX_LDZI, M_AMX_STZI, M_AMX_EXTRX, M_AMX_EXTRY, M_AMX_FMA64, M_AMX_FMS64, M_AMX_FMA32, M_AMX_FMS32, M_AMX_MAC16, + M_AMX_FMA16, M_AMX_FMS16, M_AMX_SET, M_AMX_CLR, M_AMX_VECINT, M_AMX_VECFP, M_AMX_MATINT, M_AMX_MATFP, M_AMX_GENLUT, M_CPYP, M_CPYM, M_CPYE, M_CPYFP, M_CPYFM, M_CPYFE, M_SETP, + M_SETM, M_SETE, M_DC_IVAC, M_DC_ISW, M_DC_CSW, M_DC_CISW, M_DC_ZVA, M_DC_CVAC, M_DC_CVAU, M_DC_CIVAC, M_IC_IALLUIS, M_IC_IALLU, M_IC_IVAU, M_AT_S1E1R, M_AT_S1E1W, M_AT_S1E0R, + M_AT_S1E0W, M_AT_S1E2R, M_AT_S1E2W, M_AT_S1E3R, M_AT_S1E3W, M_AT_S12E1R, M_AT_S12E1W, M_AT_S12E0R, M_AT_S12E0W, M_TLBI_VMALLE1, M_TLBI_VMALLE1IS, M_TLBI_VAE1, M_TLBI_VAE1IS, M_TLBI_ASIDE1, M_TLBI_ASIDE1IS, M_TLBI_VAAE1, + M_TLBI_VAAE1IS, M_TLBI_VALE1, M_TLBI_VALE1IS, M_TLBI_VAALE1, M_TLBI_VAALE1IS, M_TLBI_ALLE1, M_TLBI_ALLE1IS, M_TLBI_ALLE2, M_TLBI_ALLE2IS, M_TLBI_ALLE3, M_TLBI_ALLE3IS, M_PRFM, M_PRFUM, M_NEGS, M_CMP, M_CMN, + MNEMONIC_COUNT }; @@ -647,9 +649,9 @@ struct Asm_arm64 { }; - static EncodeRun const raw_encode_runs [786]; - static u8 const raw_encode_forms [48720]; - static u8 const raw_clobber_forms[34104]; + static EncodeRun const raw_encode_runs [816]; + static u8 const raw_encode_forms [49320]; + static u8 const raw_clobber_forms[34524]; StringMap mnemonic_map; StringMap register_map; @@ -1030,53 +1032,55 @@ String const Asm_arm64::mnemonic_strings[Asm_arm64::MNEMONIC_COUNT] { str_lit(""), str_lit("add"), str_lit("adds"), str_lit("sub"), str_lit("subs"), str_lit("movz"), str_lit("movn"), str_lit("movk"), str_lit("adr"), str_lit("adrp"), str_lit("and"), str_lit("ands"), str_lit("orr"), str_lit("eor"), str_lit("bic"), str_lit("bics"), str_lit("orn"), str_lit("eon"), str_lit("lsl"), str_lit("lsr"), str_lit("asr"), str_lit("ror"), str_lit("udiv"), str_lit("sdiv"), str_lit("madd"), str_lit("msub"), str_lit("smaddl"), str_lit("smsubl"), str_lit("umaddl"), str_lit("umsubl"), str_lit("smulh"), str_lit("umulh"), str_lit("clz"), str_lit("cls"), str_lit("rbit"), str_lit("rev"), str_lit("rev16"), str_lit("rev32"), str_lit("csel"), str_lit("csinc"), str_lit("csinv"), str_lit("csneg"), str_lit("ccmp"), str_lit("ccmn"), str_lit("extr"), str_lit("b"), str_lit("bl"), str_lit("br"), - str_lit("blr"), str_lit("ret"), str_lit("b_cond"), str_lit("cbz"), str_lit("cbnz"), str_lit("tbz"), str_lit("tbnz"), str_lit("ldr"), str_lit("str"), str_lit("ldrb"), str_lit("strb"), str_lit("ldrsb"), str_lit("ldrh"), str_lit("strh"), str_lit("ldrsh"), str_lit("ldrsw"), - str_lit("ldp"), str_lit("stp"), str_lit("ldpsw"), str_lit("ldar"), str_lit("stlr"), str_lit("ldarb"), str_lit("stlrb"), str_lit("ldarh"), str_lit("stlrh"), str_lit("ldxr"), str_lit("stxr"), str_lit("ldaxr"), str_lit("stlxr"), str_lit("nop"), str_lit("yield"), str_lit("wfe"), - str_lit("wfi"), str_lit("sev"), str_lit("sevl"), str_lit("hint"), str_lit("mrs"), str_lit("msr"), str_lit("isb"), str_lit("dsb"), str_lit("dmb"), str_lit("svc"), str_lit("hvc"), str_lit("smc"), str_lit("brk"), str_lit("hlt"), str_lit("eret"), str_lit("fmov"), - str_lit("fabs"), str_lit("fneg"), str_lit("fsqrt"), str_lit("fadd"), str_lit("fsub"), str_lit("fmul"), str_lit("fdiv"), str_lit("fnmul"), str_lit("fmadd"), str_lit("fmsub"), str_lit("fnmadd"), str_lit("fnmsub"), str_lit("fcmp"), str_lit("fcmpe"), str_lit("fcsel"), str_lit("fmax"), - str_lit("fmin"), str_lit("fmaxnm"), str_lit("fminnm"), str_lit("fcvt"), str_lit("scvtf"), str_lit("ucvtf"), str_lit("fcvtzs"), str_lit("fcvtzu"), str_lit("fcvtas"), str_lit("fcvtau"), str_lit("fcvtns"), str_lit("fcvtnu"), str_lit("fcvtps"), str_lit("fcvtpu"), str_lit("fcvtms"), str_lit("fcvtmu"), - str_lit("frinta"), str_lit("frinti"), str_lit("frintm"), str_lit("frintn"), str_lit("frintp"), str_lit("frintx"), str_lit("frintz"), str_lit("tst"), str_lit("ldur"), str_lit("stur"), str_lit("ldurb"), str_lit("sturb"), str_lit("ldursb"), str_lit("ldurh"), str_lit("sturh"), str_lit("ldursh"), - str_lit("ldursw"), str_lit("ldnp"), str_lit("stnp"), str_lit("ldxp"), str_lit("stxp"), str_lit("ldaxp"), str_lit("stlxp"), str_lit("ldxrb"), str_lit("stxrb"), str_lit("ldaxrb"), str_lit("stlxrb"), str_lit("ldxrh"), str_lit("stxrh"), str_lit("ldaxrh"), str_lit("stlxrh"), str_lit("ldapr"), - str_lit("ldaprb"), str_lit("ldaprh"), str_lit("ldadd"), str_lit("ldadda"), str_lit("ldaddl"), str_lit("ldaddal"), str_lit("ldclr"), str_lit("ldclra"), str_lit("ldclrl"), str_lit("ldclral"), str_lit("ldeor"), str_lit("ldeora"), str_lit("ldeorl"), str_lit("ldeoral"), str_lit("ldset"), str_lit("ldseta"), - str_lit("ldsetl"), str_lit("ldsetal"), str_lit("ldsmax"), str_lit("ldsmaxa"), str_lit("ldsmaxl"), str_lit("ldsmaxal"), str_lit("ldsmin"), str_lit("ldsmina"), str_lit("ldsminl"), str_lit("ldsminal"), str_lit("ldumax"), str_lit("ldumaxa"), str_lit("ldumaxl"), str_lit("ldumaxal"), str_lit("ldumin"), str_lit("ldumina"), - str_lit("lduminl"), str_lit("lduminal"), str_lit("swp"), str_lit("swpa"), str_lit("swpl"), str_lit("swpal"), str_lit("cas"), str_lit("casa"), str_lit("casl"), str_lit("casal"), str_lit("casb"), str_lit("casab"), str_lit("caslb"), str_lit("casalb"), str_lit("cash"), str_lit("casah"), - str_lit("caslh"), str_lit("casalh"), str_lit("casp"), str_lit("caspa"), str_lit("caspl"), str_lit("caspal"), str_lit("pacia"), str_lit("pacib"), str_lit("pacda"), str_lit("pacdb"), str_lit("paciza"), str_lit("pacizb"), str_lit("pacdza"), str_lit("pacdzb"), str_lit("autia"), str_lit("autib"), - str_lit("autda"), str_lit("autdb"), str_lit("autiza"), str_lit("autizb"), str_lit("autdza"), str_lit("autdzb"), str_lit("paciasp"), str_lit("pacibsp"), str_lit("autiasp"), str_lit("autibsp"), str_lit("pacia1716"), str_lit("pacib1716"), str_lit("autia1716"), str_lit("autib1716"), str_lit("pacga"), str_lit("xpaci"), - str_lit("xpacd"), str_lit("xpaclri"), str_lit("retaa"), str_lit("retab"), str_lit("braa"), str_lit("brab"), str_lit("braaz"), str_lit("brabz"), str_lit("blraa"), str_lit("blrab"), str_lit("blraaz"), str_lit("blrabz"), str_lit("eretaa"), str_lit("eretab"), str_lit("bti"), str_lit("irg"), - str_lit("addg"), str_lit("subg"), str_lit("gmi"), str_lit("subp"), str_lit("subps"), str_lit("ldg"), str_lit("stg"), str_lit("st2g"), str_lit("stzg"), str_lit("stz2g"), str_lit("stgp"), str_lit("ldgm"), str_lit("stgm"), str_lit("stzgm"), str_lit("crc32b"), str_lit("crc32h"), - str_lit("crc32w"), str_lit("crc32x"), str_lit("crc32cb"), str_lit("crc32ch"), str_lit("crc32cw"), str_lit("crc32cx"), str_lit("aese"), str_lit("aesd"), str_lit("aesmc"), str_lit("aesimc"), str_lit("sha1h"), str_lit("sha1c"), str_lit("sha1p"), str_lit("sha1m"), str_lit("sha1su0"), str_lit("sha1su1"), - str_lit("sha256h"), str_lit("sha256h2"), str_lit("sha256su0"), str_lit("sha256su1"), str_lit("sha512h"), str_lit("sha512h2"), str_lit("sha512su0"), str_lit("sha512su1"), str_lit("eor3"), str_lit("bcax"), str_lit("rax1"), str_lit("xar"), str_lit("sm3partw1"), str_lit("sm3partw2"), str_lit("sm3ss1"), str_lit("sm3tt1a"), - str_lit("sm3tt1b"), str_lit("sm3tt2a"), str_lit("sm3tt2b"), str_lit("sm4e"), str_lit("sm4ekey"), str_lit("pmull"), str_lit("pmull2"), str_lit("bfcvt"), str_lit("bfdot"), str_lit("bfmmla"), str_lit("bfmlalb"), str_lit("bfmlalt"), str_lit("bfcvtn"), str_lit("bfcvtn2"), str_lit("mul"), str_lit("mla"), - str_lit("mls"), str_lit("neg"), str_lit("abs"), str_lit("shadd"), str_lit("uhadd"), str_lit("shsub"), str_lit("uhsub"), str_lit("srhadd"), str_lit("urhadd"), str_lit("sqadd"), str_lit("uqadd"), str_lit("sqsub"), str_lit("uqsub"), str_lit("smax"), str_lit("umax"), str_lit("smin"), - str_lit("umin"), str_lit("sabd"), str_lit("uabd"), str_lit("saba"), str_lit("uaba"), str_lit("addp"), str_lit("addv"), str_lit("saddlp"), str_lit("uaddlp"), str_lit("sadalp"), str_lit("uadalp"), str_lit("saddlv"), str_lit("uaddlv"), str_lit("smaxv"), str_lit("umaxv"), str_lit("sminv"), - str_lit("uminv"), str_lit("smaxp"), str_lit("umaxp"), str_lit("sminp"), str_lit("uminp"), str_lit("saddl"), str_lit("saddl2"), str_lit("uaddl"), str_lit("uaddl2"), str_lit("ssubl"), str_lit("ssubl2"), str_lit("usubl"), str_lit("usubl2"), str_lit("saddw"), str_lit("saddw2"), str_lit("uaddw"), - str_lit("uaddw2"), str_lit("ssubw"), str_lit("ssubw2"), str_lit("usubw"), str_lit("usubw2"), str_lit("raddhn"), str_lit("raddhn2"), str_lit("rsubhn"), str_lit("rsubhn2"), str_lit("addhn"), str_lit("addhn2"), str_lit("subhn"), str_lit("subhn2"), str_lit("xtn"), str_lit("xtn2"), str_lit("sqxtn"), - str_lit("sqxtn2"), str_lit("uqxtn"), str_lit("uqxtn2"), str_lit("sqxtun"), str_lit("sqxtun2"), str_lit("smull"), str_lit("smull2"), str_lit("umull"), str_lit("umull2"), str_lit("smlal"), str_lit("smlal2"), str_lit("umlal"), str_lit("umlal2"), str_lit("smlsl"), str_lit("smlsl2"), str_lit("umlsl"), - str_lit("umlsl2"), str_lit("sqdmull"), str_lit("sqdmull2"), str_lit("sqdmlal"), str_lit("sqdmlal2"), str_lit("sqdmlsl"), str_lit("sqdmlsl2"), str_lit("sqdmulh"), str_lit("sqrdmulh"), str_lit("sdot"), str_lit("udot"), str_lit("usdot"), str_lit("fmla"), str_lit("fmls"), str_lit("fmulx"), str_lit("fmaxp"), - str_lit("fminp"), str_lit("fmaxnmp"), str_lit("fminnmp"), str_lit("fmaxv"), str_lit("fminv"), str_lit("fmaxnmv"), str_lit("fminnmv"), str_lit("frecpe"), str_lit("frsqrte"), str_lit("frecps"), str_lit("frsqrts"), str_lit("frecpx"), str_lit("faddp"), str_lit("fcvtl"), str_lit("fcvtl2"), str_lit("fcvtn"), - str_lit("fcvtn2"), str_lit("fcvtxn"), str_lit("fcvtxn2"), str_lit("fcmeq"), str_lit("fcmge"), str_lit("fcmgt"), str_lit("fcmle"), str_lit("fcmlt"), str_lit("facge"), str_lit("facgt"), str_lit("cmeq"), str_lit("cmge"), str_lit("cmgt"), str_lit("cmhi"), str_lit("cmhs"), str_lit("cmle"), - str_lit("cmlt"), str_lit("cmtst"), str_lit("mvn"), str_lit("bit"), str_lit("bif"), str_lit("bsl"), str_lit("shl"), str_lit("sqshl"), str_lit("sqshlu"), str_lit("srshl"), str_lit("urshl"), str_lit("sshr"), str_lit("ushr"), str_lit("ssra"), str_lit("usra"), str_lit("srshr"), - str_lit("urshr"), str_lit("srsra"), str_lit("ursra"), str_lit("sshl"), str_lit("ushl"), str_lit("sli"), str_lit("sri"), str_lit("sshll"), str_lit("sshll2"), str_lit("ushll"), str_lit("ushll2"), str_lit("sxtl"), str_lit("sxtl2"), str_lit("uxtl"), str_lit("uxtl2"), str_lit("shrn"), - str_lit("shrn2"), str_lit("rshrn"), str_lit("rshrn2"), str_lit("sqshrn"), str_lit("sqshrn2"), str_lit("uqshrn"), str_lit("uqshrn2"), str_lit("sqrshrn"), str_lit("sqrshrn2"), str_lit("uqrshrn"), str_lit("uqrshrn2"), str_lit("sqshrun"), str_lit("sqshrun2"), str_lit("sqrshrun"), str_lit("sqrshrun2"), str_lit("dup"), - str_lit("ins"), str_lit("mov"), str_lit("ext"), str_lit("tbl"), str_lit("tbx"), str_lit("zip1"), str_lit("zip2"), str_lit("uzp1"), str_lit("uzp2"), str_lit("trn1"), str_lit("trn2"), str_lit("not"), str_lit("rev64"), str_lit("cnt"), str_lit("urecpe"), str_lit("ursqrte"), - str_lit("movi"), str_lit("mvni"), str_lit("ld1"), str_lit("ld2"), str_lit("ld3"), str_lit("ld4"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("ld1r"), str_lit("ld2r"), str_lit("ld3r"), str_lit("ld4r"), str_lit("subr"), str_lit("asrr"), - str_lit("lslr"), str_lit("lsrr"), str_lit("ftsmul"), str_lit("fsubr"), str_lit("fdivr"), str_lit("fnmla"), str_lit("fnmls"), str_lit("nand"), str_lit("nor"), str_lit("sel"), str_lit("orrs"), str_lit("eors"), str_lit("nands"), str_lit("nors"), str_lit("orns"), str_lit("movs"), - str_lit("ptrue"), str_lit("ptrues"), str_lit("pfalse"), str_lit("pfirst"), str_lit("pnext"), str_lit("brka"), str_lit("brkb"), str_lit("brkas"), str_lit("brkbs"), str_lit("brkpa"), str_lit("brkpb"), str_lit("brkn"), str_lit("rdffr"), str_lit("wrffr"), str_lit("setffr"), str_lit("cmpeq"), - str_lit("cmpne"), str_lit("cmpge"), str_lit("cmpgt"), str_lit("cmple"), str_lit("cmplt"), str_lit("cmphi"), str_lit("cmphs"), str_lit("cmplo"), str_lit("cmpls"), str_lit("fcmne"), str_lit("fcmuo"), str_lit("insr"), str_lit("cpy"), str_lit("compact"), str_lit("ld1b"), str_lit("ld1h"), - str_lit("ld1w"), str_lit("ld1d"), str_lit("ld1sb"), str_lit("ld1sh"), str_lit("ld1sw"), str_lit("st1b"), str_lit("st1h"), str_lit("st1w"), str_lit("st1d"), str_lit("ldff1b"), str_lit("ldff1h"), str_lit("ldff1w"), str_lit("ldff1d"), str_lit("whilege"), str_lit("whilegt"), str_lit("whilele"), - str_lit("whilelt"), str_lit("whilehi"), str_lit("whilehs"), str_lit("whilelo"), str_lit("whilels"), str_lit("sqrdmlah"), str_lit("sqrdmlsh"), str_lit("adclb"), str_lit("adclt"), str_lit("sbclb"), str_lit("sbclt"), str_lit("tbl2"), str_lit("match"), str_lit("nmatch"), str_lit("histcnt"), str_lit("histseg"), - str_lit("smstart"), str_lit("smstop"), str_lit("rdsvl"), str_lit("addha"), str_lit("addva"), str_lit("zero"), str_lit("fmopa"), str_lit("fmops"), str_lit("bfmopa"), str_lit("bfmops"), str_lit("smopa"), str_lit("smops"), str_lit("umopa"), str_lit("umops"), str_lit("usmopa"), str_lit("sumopa"), - str_lit("ld1q"), str_lit("st1q"), str_lit("mova"), str_lit("fcmla"), str_lit("fcadd"), str_lit("prfb"), str_lit("prfh"), str_lit("prfw"), str_lit("prfd"), str_lit("ldnt1b"), str_lit("ldnt1h"), str_lit("ldnt1w"), str_lit("ldnt1d"), str_lit("stnt1b"), str_lit("stnt1h"), str_lit("stnt1w"), - str_lit("stnt1d"), str_lit("splice"), str_lit("index"), str_lit("bsl1n"), str_lit("bsl2n"), str_lit("nbsl"), str_lit("pmul"), str_lit("pmullb"), str_lit("pmullt"), str_lit("bfcvtnt"), str_lit("ldraa"), str_lit("ldrab"), str_lit("tstart"), str_lit("tcommit"), str_lit("tcancel"), str_lit("ttest"), - str_lit("wfet"), str_lit("wfit"), str_lit("bc_cond"), str_lit("uxtb"), str_lit("uxth"), str_lit("uxtw"), str_lit("sxtb"), str_lit("sxth"), str_lit("sxtw"), str_lit("adc"), str_lit("adcs"), str_lit("sbc"), str_lit("sbcs"), str_lit("ngc"), str_lit("ngcs"), str_lit("ldapur"), - str_lit("stlur"), str_lit("ldapurb"), str_lit("stlurb"), str_lit("ldapurh"), str_lit("stlurh"), str_lit("ldapursb"), str_lit("ldapursh"), str_lit("ldapursw"), str_lit("bfadd"), str_lit("bfsub"), str_lit("bfmul"), str_lit("bfmla"), str_lit("bfmls"), str_lit("sb"), str_lit("csdb"), str_lit("dgh"), - str_lit("psb_csync"), str_lit("tsb_csync"), str_lit("bti_j"), str_lit("bti_c"), str_lit("bti_jc"), str_lit("bfclamp"), str_lit("bfmaxnm"), str_lit("bfminnm"), str_lit("luti2"), str_lit("luti4"), str_lit("zip"), str_lit("uzp"), str_lit("tlbi_rpalos"), str_lit("tlbi_rpaos"), str_lit("at_s1e1a"), str_lit("dc_cipapa"), - str_lit("dc_cigdpapa"), str_lit("tlbi_paall"), str_lit("tlbi_paallos"), str_lit("amx_ldx"), str_lit("amx_ldy"), str_lit("amx_stx"), str_lit("amx_sty"), str_lit("amx_ldz"), str_lit("amx_stz"), str_lit("amx_ldzi"), str_lit("amx_stzi"), str_lit("amx_extrx"), str_lit("amx_extry"), str_lit("amx_fma64"), str_lit("amx_fms64"), str_lit("amx_fma32"), - str_lit("amx_fms32"), str_lit("amx_mac16"), str_lit("amx_fma16"), str_lit("amx_fms16"), str_lit("amx_set"), str_lit("amx_clr"), str_lit("amx_vecint"), str_lit("amx_vecfp"), str_lit("amx_matint"), str_lit("amx_matfp"), str_lit("amx_genlut"), str_lit("cpyp"), str_lit("cpym"), str_lit("cpye"), str_lit("cpyfp"), str_lit("cpyfm"), - str_lit("cpyfe"), str_lit("setp"), str_lit("setm"), str_lit("sete"), str_lit("dc_ivac"), str_lit("dc_isw"), str_lit("dc_csw"), str_lit("dc_cisw"), str_lit("dc_zva"), str_lit("dc_cvac"), str_lit("dc_cvau"), str_lit("dc_civac"), str_lit("ic_ialluis"), str_lit("ic_iallu"), str_lit("ic_ivau"), str_lit("at_s1e1r"), - str_lit("at_s1e1w"), str_lit("at_s1e0r"), str_lit("at_s1e0w"), str_lit("at_s1e2r"), str_lit("at_s1e2w"), str_lit("at_s1e3r"), str_lit("at_s1e3w"), str_lit("at_s12e1r"), str_lit("at_s12e1w"), str_lit("at_s12e0r"), str_lit("at_s12e0w"), str_lit("tlbi_vmalle1"), str_lit("tlbi_vmalle1is"), str_lit("tlbi_vae1"), str_lit("tlbi_vae1is"), str_lit("tlbi_aside1"), - str_lit("tlbi_aside1is"), str_lit("tlbi_vaae1"), str_lit("tlbi_vaae1is"), str_lit("tlbi_vale1"), str_lit("tlbi_vale1is"), str_lit("tlbi_vaale1"), str_lit("tlbi_vaale1is"), str_lit("tlbi_alle1"), str_lit("tlbi_alle1is"), str_lit("tlbi_alle2"), str_lit("tlbi_alle2is"), str_lit("tlbi_alle3"), str_lit("tlbi_alle3is"), str_lit("prfm"), str_lit("prfum"), str_lit("negs"), - str_lit("cmp"), str_lit("cmn"), + str_lit("blr"), str_lit("ret"), str_lit("b_eq"), str_lit("b_ne"), str_lit("b_cs"), str_lit("b_cc"), str_lit("b_mi"), str_lit("b_pl"), str_lit("b_vs"), str_lit("b_vc"), str_lit("b_hi"), str_lit("b_ls"), str_lit("b_ge"), str_lit("b_lt"), str_lit("b_gt"), str_lit("b_le"), + str_lit("b_al"), str_lit("b_nv"), str_lit("cbz"), str_lit("cbnz"), str_lit("tbz"), str_lit("tbnz"), str_lit("ldr"), str_lit("str"), str_lit("ldrb"), str_lit("strb"), str_lit("ldrsb"), str_lit("ldrh"), str_lit("strh"), str_lit("ldrsh"), str_lit("ldrsw"), str_lit("ldp"), + str_lit("stp"), str_lit("ldpsw"), str_lit("ldar"), str_lit("stlr"), str_lit("ldarb"), str_lit("stlrb"), str_lit("ldarh"), str_lit("stlrh"), str_lit("ldxr"), str_lit("stxr"), str_lit("ldaxr"), str_lit("stlxr"), str_lit("nop"), str_lit("yield"), str_lit("wfe"), str_lit("wfi"), + str_lit("sev"), str_lit("sevl"), str_lit("hint"), str_lit("mrs"), str_lit("msr"), str_lit("isb"), str_lit("dsb"), str_lit("dmb"), str_lit("svc"), str_lit("hvc"), str_lit("smc"), str_lit("brk"), str_lit("hlt"), str_lit("eret"), str_lit("fmov"), str_lit("fabs"), + str_lit("fneg"), str_lit("fsqrt"), str_lit("fadd"), str_lit("fsub"), str_lit("fmul"), str_lit("fdiv"), str_lit("fnmul"), str_lit("fmadd"), str_lit("fmsub"), str_lit("fnmadd"), str_lit("fnmsub"), str_lit("fcmp"), str_lit("fcmpe"), str_lit("fcsel"), str_lit("fmax"), str_lit("fmin"), + str_lit("fmaxnm"), str_lit("fminnm"), str_lit("fcvt"), str_lit("scvtf"), str_lit("ucvtf"), str_lit("fcvtzs"), str_lit("fcvtzu"), str_lit("fcvtas"), str_lit("fcvtau"), str_lit("fcvtns"), str_lit("fcvtnu"), str_lit("fcvtps"), str_lit("fcvtpu"), str_lit("fcvtms"), str_lit("fcvtmu"), str_lit("frinta"), + str_lit("frinti"), str_lit("frintm"), str_lit("frintn"), str_lit("frintp"), str_lit("frintx"), str_lit("frintz"), str_lit("tst"), str_lit("ldur"), str_lit("stur"), str_lit("ldurb"), str_lit("sturb"), str_lit("ldursb"), str_lit("ldurh"), str_lit("sturh"), str_lit("ldursh"), str_lit("ldursw"), + str_lit("ldnp"), str_lit("stnp"), str_lit("ldxp"), str_lit("stxp"), str_lit("ldaxp"), str_lit("stlxp"), str_lit("ldxrb"), str_lit("stxrb"), str_lit("ldaxrb"), str_lit("stlxrb"), str_lit("ldxrh"), str_lit("stxrh"), str_lit("ldaxrh"), str_lit("stlxrh"), str_lit("ldapr"), str_lit("ldaprb"), + str_lit("ldaprh"), str_lit("ldadd"), str_lit("ldadda"), str_lit("ldaddl"), str_lit("ldaddal"), str_lit("ldclr"), str_lit("ldclra"), str_lit("ldclrl"), str_lit("ldclral"), str_lit("ldeor"), str_lit("ldeora"), str_lit("ldeorl"), str_lit("ldeoral"), str_lit("ldset"), str_lit("ldseta"), str_lit("ldsetl"), + str_lit("ldsetal"), str_lit("ldsmax"), str_lit("ldsmaxa"), str_lit("ldsmaxl"), str_lit("ldsmaxal"), str_lit("ldsmin"), str_lit("ldsmina"), str_lit("ldsminl"), str_lit("ldsminal"), str_lit("ldumax"), str_lit("ldumaxa"), str_lit("ldumaxl"), str_lit("ldumaxal"), str_lit("ldumin"), str_lit("ldumina"), str_lit("lduminl"), + str_lit("lduminal"), str_lit("swp"), str_lit("swpa"), str_lit("swpl"), str_lit("swpal"), str_lit("cas"), str_lit("casa"), str_lit("casl"), str_lit("casal"), str_lit("casb"), str_lit("casab"), str_lit("caslb"), str_lit("casalb"), str_lit("cash"), str_lit("casah"), str_lit("caslh"), + str_lit("casalh"), str_lit("casp"), str_lit("caspa"), str_lit("caspl"), str_lit("caspal"), str_lit("pacia"), str_lit("pacib"), str_lit("pacda"), str_lit("pacdb"), str_lit("paciza"), str_lit("pacizb"), str_lit("pacdza"), str_lit("pacdzb"), str_lit("autia"), str_lit("autib"), str_lit("autda"), + str_lit("autdb"), str_lit("autiza"), str_lit("autizb"), str_lit("autdza"), str_lit("autdzb"), str_lit("paciasp"), str_lit("pacibsp"), str_lit("autiasp"), str_lit("autibsp"), str_lit("pacia1716"), str_lit("pacib1716"), str_lit("autia1716"), str_lit("autib1716"), str_lit("pacga"), str_lit("xpaci"), str_lit("xpacd"), + str_lit("xpaclri"), str_lit("retaa"), str_lit("retab"), str_lit("braa"), str_lit("brab"), str_lit("braaz"), str_lit("brabz"), str_lit("blraa"), str_lit("blrab"), str_lit("blraaz"), str_lit("blrabz"), str_lit("eretaa"), str_lit("eretab"), str_lit("bti"), str_lit("irg"), str_lit("addg"), + str_lit("subg"), str_lit("gmi"), str_lit("subp"), str_lit("subps"), str_lit("ldg"), str_lit("stg"), str_lit("st2g"), str_lit("stzg"), str_lit("stz2g"), str_lit("stgp"), str_lit("ldgm"), str_lit("stgm"), str_lit("stzgm"), str_lit("crc32b"), str_lit("crc32h"), str_lit("crc32w"), + str_lit("crc32x"), str_lit("crc32cb"), str_lit("crc32ch"), str_lit("crc32cw"), str_lit("crc32cx"), str_lit("aese"), str_lit("aesd"), str_lit("aesmc"), str_lit("aesimc"), str_lit("sha1h"), str_lit("sha1c"), str_lit("sha1p"), str_lit("sha1m"), str_lit("sha1su0"), str_lit("sha1su1"), str_lit("sha256h"), + str_lit("sha256h2"), str_lit("sha256su0"), str_lit("sha256su1"), str_lit("sha512h"), str_lit("sha512h2"), str_lit("sha512su0"), str_lit("sha512su1"), str_lit("eor3"), str_lit("bcax"), str_lit("rax1"), str_lit("xar"), str_lit("sm3partw1"), str_lit("sm3partw2"), str_lit("sm3ss1"), str_lit("sm3tt1a"), str_lit("sm3tt1b"), + str_lit("sm3tt2a"), str_lit("sm3tt2b"), str_lit("sm4e"), str_lit("sm4ekey"), str_lit("pmull"), str_lit("pmull2"), str_lit("bfcvt"), str_lit("bfdot"), str_lit("bfmmla"), str_lit("bfmlalb"), str_lit("bfmlalt"), str_lit("bfcvtn"), str_lit("bfcvtn2"), str_lit("mul"), str_lit("mla"), str_lit("mls"), + str_lit("neg"), str_lit("abs"), str_lit("shadd"), str_lit("uhadd"), str_lit("shsub"), str_lit("uhsub"), str_lit("srhadd"), str_lit("urhadd"), str_lit("sqadd"), str_lit("uqadd"), str_lit("sqsub"), str_lit("uqsub"), str_lit("smax"), str_lit("umax"), str_lit("smin"), str_lit("umin"), + str_lit("sabd"), str_lit("uabd"), str_lit("saba"), str_lit("uaba"), str_lit("addp"), str_lit("addv"), str_lit("saddlp"), str_lit("uaddlp"), str_lit("sadalp"), str_lit("uadalp"), str_lit("saddlv"), str_lit("uaddlv"), str_lit("smaxv"), str_lit("umaxv"), str_lit("sminv"), str_lit("uminv"), + str_lit("smaxp"), str_lit("umaxp"), str_lit("sminp"), str_lit("uminp"), str_lit("saddl"), str_lit("saddl2"), str_lit("uaddl"), str_lit("uaddl2"), str_lit("ssubl"), str_lit("ssubl2"), str_lit("usubl"), str_lit("usubl2"), str_lit("saddw"), str_lit("saddw2"), str_lit("uaddw"), str_lit("uaddw2"), + str_lit("ssubw"), str_lit("ssubw2"), str_lit("usubw"), str_lit("usubw2"), str_lit("raddhn"), str_lit("raddhn2"), str_lit("rsubhn"), str_lit("rsubhn2"), str_lit("addhn"), str_lit("addhn2"), str_lit("subhn"), str_lit("subhn2"), str_lit("xtn"), str_lit("xtn2"), str_lit("sqxtn"), str_lit("sqxtn2"), + str_lit("uqxtn"), str_lit("uqxtn2"), str_lit("sqxtun"), str_lit("sqxtun2"), str_lit("smull"), str_lit("smull2"), str_lit("umull"), str_lit("umull2"), str_lit("smlal"), str_lit("smlal2"), str_lit("umlal"), str_lit("umlal2"), str_lit("smlsl"), str_lit("smlsl2"), str_lit("umlsl"), str_lit("umlsl2"), + str_lit("sqdmull"), str_lit("sqdmull2"), str_lit("sqdmlal"), str_lit("sqdmlal2"), str_lit("sqdmlsl"), str_lit("sqdmlsl2"), str_lit("sqdmulh"), str_lit("sqrdmulh"), str_lit("sdot"), str_lit("udot"), str_lit("usdot"), str_lit("fmla"), str_lit("fmls"), str_lit("fmulx"), str_lit("fmaxp"), str_lit("fminp"), + str_lit("fmaxnmp"), str_lit("fminnmp"), str_lit("fmaxv"), str_lit("fminv"), str_lit("fmaxnmv"), str_lit("fminnmv"), str_lit("frecpe"), str_lit("frsqrte"), str_lit("frecps"), str_lit("frsqrts"), str_lit("frecpx"), str_lit("faddp"), str_lit("fcvtl"), str_lit("fcvtl2"), str_lit("fcvtn"), str_lit("fcvtn2"), + str_lit("fcvtxn"), str_lit("fcvtxn2"), str_lit("fcmeq"), str_lit("fcmge"), str_lit("fcmgt"), str_lit("fcmle"), str_lit("fcmlt"), str_lit("facge"), str_lit("facgt"), str_lit("cmeq"), str_lit("cmge"), str_lit("cmgt"), str_lit("cmhi"), str_lit("cmhs"), str_lit("cmle"), str_lit("cmlt"), + str_lit("cmtst"), str_lit("mvn"), str_lit("bit"), str_lit("bif"), str_lit("bsl"), str_lit("shl"), str_lit("sqshl"), str_lit("sqshlu"), str_lit("srshl"), str_lit("urshl"), str_lit("sshr"), str_lit("ushr"), str_lit("ssra"), str_lit("usra"), str_lit("srshr"), str_lit("urshr"), + str_lit("srsra"), str_lit("ursra"), str_lit("sshl"), str_lit("ushl"), str_lit("sli"), str_lit("sri"), str_lit("sshll"), str_lit("sshll2"), str_lit("ushll"), str_lit("ushll2"), str_lit("sxtl"), str_lit("sxtl2"), str_lit("uxtl"), str_lit("uxtl2"), str_lit("shrn"), str_lit("shrn2"), + str_lit("rshrn"), str_lit("rshrn2"), str_lit("sqshrn"), str_lit("sqshrn2"), str_lit("uqshrn"), str_lit("uqshrn2"), str_lit("sqrshrn"), str_lit("sqrshrn2"), str_lit("uqrshrn"), str_lit("uqrshrn2"), str_lit("sqshrun"), str_lit("sqshrun2"), str_lit("sqrshrun"), str_lit("sqrshrun2"), str_lit("dup"), str_lit("ins"), + str_lit("mov"), str_lit("ext"), str_lit("tbl"), str_lit("tbx"), str_lit("zip1"), str_lit("zip2"), str_lit("uzp1"), str_lit("uzp2"), str_lit("trn1"), str_lit("trn2"), str_lit("not"), str_lit("rev64"), str_lit("cnt"), str_lit("urecpe"), str_lit("ursqrte"), str_lit("movi"), + str_lit("mvni"), str_lit("ld1"), str_lit("ld2"), str_lit("ld3"), str_lit("ld4"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("ld1r"), str_lit("ld2r"), str_lit("ld3r"), str_lit("ld4r"), str_lit("subr"), str_lit("asrr"), str_lit("lslr"), + str_lit("lsrr"), str_lit("ftsmul"), str_lit("fsubr"), str_lit("fdivr"), str_lit("fnmla"), str_lit("fnmls"), str_lit("nand"), str_lit("nor"), str_lit("sel"), str_lit("orrs"), str_lit("eors"), str_lit("nands"), str_lit("nors"), str_lit("orns"), str_lit("movs"), str_lit("ptrue"), + str_lit("ptrues"), str_lit("pfalse"), str_lit("pfirst"), str_lit("pnext"), str_lit("brka"), str_lit("brkb"), str_lit("brkas"), str_lit("brkbs"), str_lit("brkpa"), str_lit("brkpb"), str_lit("brkn"), str_lit("rdffr"), str_lit("wrffr"), str_lit("setffr"), str_lit("cmpeq"), str_lit("cmpne"), + str_lit("cmpge"), str_lit("cmpgt"), str_lit("cmple"), str_lit("cmplt"), str_lit("cmphi"), str_lit("cmphs"), str_lit("cmplo"), str_lit("cmpls"), str_lit("fcmne"), str_lit("fcmuo"), str_lit("insr"), str_lit("cpy"), str_lit("compact"), str_lit("ld1b"), str_lit("ld1h"), str_lit("ld1w"), + str_lit("ld1d"), str_lit("ld1sb"), str_lit("ld1sh"), str_lit("ld1sw"), str_lit("st1b"), str_lit("st1h"), str_lit("st1w"), str_lit("st1d"), str_lit("ldff1b"), str_lit("ldff1h"), str_lit("ldff1w"), str_lit("ldff1d"), str_lit("whilege"), str_lit("whilegt"), str_lit("whilele"), str_lit("whilelt"), + str_lit("whilehi"), str_lit("whilehs"), str_lit("whilelo"), str_lit("whilels"), str_lit("sqrdmlah"), str_lit("sqrdmlsh"), str_lit("adclb"), str_lit("adclt"), str_lit("sbclb"), str_lit("sbclt"), str_lit("tbl2"), str_lit("match"), str_lit("nmatch"), str_lit("histcnt"), str_lit("histseg"), str_lit("smstart"), + str_lit("smstop"), str_lit("rdsvl"), str_lit("addha"), str_lit("addva"), str_lit("zero"), str_lit("fmopa"), str_lit("fmops"), str_lit("bfmopa"), str_lit("bfmops"), str_lit("smopa"), str_lit("smops"), str_lit("umopa"), str_lit("umops"), str_lit("usmopa"), str_lit("sumopa"), str_lit("ld1q"), + str_lit("st1q"), str_lit("mova"), str_lit("fcmla"), str_lit("fcadd"), str_lit("prfb"), str_lit("prfh"), str_lit("prfw"), str_lit("prfd"), str_lit("ldnt1b"), str_lit("ldnt1h"), str_lit("ldnt1w"), str_lit("ldnt1d"), str_lit("stnt1b"), str_lit("stnt1h"), str_lit("stnt1w"), str_lit("stnt1d"), + str_lit("splice"), str_lit("index"), str_lit("bsl1n"), str_lit("bsl2n"), str_lit("nbsl"), str_lit("pmul"), str_lit("pmullb"), str_lit("pmullt"), str_lit("bfcvtnt"), str_lit("ldraa"), str_lit("ldrab"), str_lit("tstart"), str_lit("tcommit"), str_lit("tcancel"), str_lit("ttest"), str_lit("wfet"), + str_lit("wfit"), str_lit("bc_eq"), str_lit("bc_ne"), str_lit("bc_cs"), str_lit("bc_cc"), str_lit("bc_mi"), str_lit("bc_pl"), str_lit("bc_vs"), str_lit("bc_vc"), str_lit("bc_hi"), str_lit("bc_ls"), str_lit("bc_ge"), str_lit("bc_lt"), str_lit("bc_gt"), str_lit("bc_le"), str_lit("bc_al"), + str_lit("bc_nv"), str_lit("uxtb"), str_lit("uxth"), str_lit("uxtw"), str_lit("sxtb"), str_lit("sxth"), str_lit("sxtw"), str_lit("adc"), str_lit("adcs"), str_lit("sbc"), str_lit("sbcs"), str_lit("ngc"), str_lit("ngcs"), str_lit("ldapur"), str_lit("stlur"), str_lit("ldapurb"), + str_lit("stlurb"), str_lit("ldapurh"), str_lit("stlurh"), str_lit("ldapursb"), str_lit("ldapursh"), str_lit("ldapursw"), str_lit("bfadd"), str_lit("bfsub"), str_lit("bfmul"), str_lit("bfmla"), str_lit("bfmls"), str_lit("sb"), str_lit("csdb"), str_lit("dgh"), str_lit("psb_csync"), str_lit("tsb_csync"), + str_lit("bti_j"), str_lit("bti_c"), str_lit("bti_jc"), str_lit("bfclamp"), str_lit("bfmaxnm"), str_lit("bfminnm"), str_lit("luti2"), str_lit("luti4"), str_lit("zip"), str_lit("uzp"), str_lit("tlbi_rpalos"), str_lit("tlbi_rpaos"), str_lit("at_s1e1a"), str_lit("dc_cipapa"), str_lit("dc_cigdpapa"), str_lit("tlbi_paall"), + str_lit("tlbi_paallos"), str_lit("amx_ldx"), str_lit("amx_ldy"), str_lit("amx_stx"), str_lit("amx_sty"), str_lit("amx_ldz"), str_lit("amx_stz"), str_lit("amx_ldzi"), str_lit("amx_stzi"), str_lit("amx_extrx"), str_lit("amx_extry"), str_lit("amx_fma64"), str_lit("amx_fms64"), str_lit("amx_fma32"), str_lit("amx_fms32"), str_lit("amx_mac16"), + str_lit("amx_fma16"), str_lit("amx_fms16"), str_lit("amx_set"), str_lit("amx_clr"), str_lit("amx_vecint"), str_lit("amx_vecfp"), str_lit("amx_matint"), str_lit("amx_matfp"), str_lit("amx_genlut"), str_lit("cpyp"), str_lit("cpym"), str_lit("cpye"), str_lit("cpyfp"), str_lit("cpyfm"), str_lit("cpyfe"), str_lit("setp"), + str_lit("setm"), str_lit("sete"), str_lit("dc_ivac"), str_lit("dc_isw"), str_lit("dc_csw"), str_lit("dc_cisw"), str_lit("dc_zva"), str_lit("dc_cvac"), str_lit("dc_cvau"), str_lit("dc_civac"), str_lit("ic_ialluis"), str_lit("ic_iallu"), str_lit("ic_ivau"), str_lit("at_s1e1r"), str_lit("at_s1e1w"), str_lit("at_s1e0r"), + str_lit("at_s1e0w"), str_lit("at_s1e2r"), str_lit("at_s1e2w"), str_lit("at_s1e3r"), str_lit("at_s1e3w"), str_lit("at_s12e1r"), str_lit("at_s12e1w"), str_lit("at_s12e0r"), str_lit("at_s12e0w"), str_lit("tlbi_vmalle1"), str_lit("tlbi_vmalle1is"), str_lit("tlbi_vae1"), str_lit("tlbi_vae1is"), str_lit("tlbi_aside1"), str_lit("tlbi_aside1is"), str_lit("tlbi_vaae1"), + str_lit("tlbi_vaae1is"), str_lit("tlbi_vale1"), str_lit("tlbi_vale1is"), str_lit("tlbi_vaale1"), str_lit("tlbi_vaale1is"), str_lit("tlbi_alle1"), str_lit("tlbi_alle1is"), str_lit("tlbi_alle2"), str_lit("tlbi_alle2is"), str_lit("tlbi_alle3"), str_lit("tlbi_alle3is"), str_lit("prfm"), str_lit("prfum"), str_lit("negs"), str_lit("cmp"), str_lit("cmn"), + }; u16 const Asm_arm64::register_codes[Asm_arm64::REG_COUNT] { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, @@ -1097,59 +1101,61 @@ String const Asm_arm64::register_strings[Asm_arm64::REG_COUNT] { str_lit("v29"), str_lit("v30"), str_lit("v31"), }; String const Asm_arm64::pseudo_mnemonic_strings[Asm_arm64::PSEUDO_MNEMONIC_COUNT] {}; -Asm_arm64::EncodeRun const Asm_arm64::raw_encode_runs[786] = { +Asm_arm64::EncodeRun const Asm_arm64::raw_encode_runs[816] = { { 0, 0}, { 0, 21}, { 21, 6}, { 27, 18}, { 45, 6}, { 51, 2}, { 53, 2}, { 55, 2}, { 57, 1}, { 58, 1}, { 59, 7}, { 66, 5}, { 71, 7}, { 78, 7}, { 85, 5}, { 90, 3}, { 93, 4}, { 97, 2}, { 99, 8}, { 107, 8}, { 115, 8}, { 123, 4}, { 127, 4}, { 131, 4}, { 135, 2}, { 137, 2}, { 139, 1}, { 140, 1}, { 141, 1}, { 142, 1}, { 143, 5}, { 148, 5}, { 153, 12}, { 165, 12}, { 177, 4}, { 181, 7}, { 188, 4}, { 192, 5}, { 197, 2}, { 199, 2}, { 201, 2}, { 203, 2}, { 205, 4}, { 209, 4}, { 213, 2}, { 215, 1}, { 216, 1}, { 217, 1}, - { 218, 1}, { 219, 2}, { 221, 1}, { 222, 2}, { 224, 2}, { 226, 1}, { 227, 1}, { 228, 18}, { 246, 16}, { 262, 4}, { 266, 4}, { 270, 4}, { 274, 4}, { 278, 4}, { 282, 4}, { 286, 2}, - { 288, 9}, { 297, 9}, { 306, 3}, { 309, 2}, { 311, 2}, { 313, 1}, { 314, 1}, { 315, 1}, { 316, 1}, { 317, 2}, { 319, 2}, { 321, 2}, { 323, 2}, { 325, 1}, { 326, 1}, { 327, 1}, - { 328, 1}, { 329, 1}, { 330, 1}, { 331, 1}, { 332, 1}, { 333, 2}, { 335, 1}, { 336, 1}, { 337, 1}, { 338, 1}, { 339, 1}, { 340, 1}, { 341, 1}, { 342, 1}, { 343, 1}, { 344, 15}, - { 359, 11}, { 370, 11}, { 381, 11}, { 392, 12}, { 404, 12}, { 416, 12}, { 428, 9}, { 437, 3}, { 440, 3}, { 443, 3}, { 446, 3}, { 449, 3}, { 452, 3}, { 455, 3}, { 458, 3}, { 461, 11}, - { 472, 11}, { 483, 11}, { 494, 11}, { 505, 6}, { 511, 10}, { 521, 10}, { 531, 10}, { 541, 10}, { 551, 11}, { 562, 11}, { 573, 11}, { 584, 11}, { 595, 11}, { 606, 11}, { 617, 11}, { 628, 11}, - { 639, 11}, { 650, 11}, { 661, 11}, { 672, 11}, { 683, 11}, { 694, 11}, { 705, 11}, { 716, 4}, { 720, 5}, { 725, 5}, { 730, 1}, { 731, 1}, { 732, 2}, { 734, 1}, { 735, 1}, { 736, 2}, - { 738, 1}, { 739, 2}, { 741, 2}, { 743, 2}, { 745, 2}, { 747, 2}, { 749, 2}, { 751, 1}, { 752, 1}, { 753, 1}, { 754, 1}, { 755, 1}, { 756, 1}, { 757, 1}, { 758, 1}, { 759, 2}, - { 761, 1}, { 762, 1}, { 763, 2}, { 765, 2}, { 767, 2}, { 769, 2}, { 771, 2}, { 773, 2}, { 775, 2}, { 777, 2}, { 779, 2}, { 781, 2}, { 783, 2}, { 785, 2}, { 787, 2}, { 789, 2}, - { 791, 2}, { 793, 2}, { 795, 2}, { 797, 2}, { 799, 2}, { 801, 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{2310, 1}, + {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 2}, {2320, 2}, {2322, 2}, {2324, 2}, {2326, 2}, {2328, 2}, {2330, 2}, {2332, 2}, {2334, 1}, + {2335, 1}, {2336, 1}, {2337, 1}, {2338, 2}, {2340, 2}, {2342, 1}, {2343, 2}, {2345, 2}, {2347, 2}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, + {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 2}, {2366, 2}, {2368, 1}, {2369, 1}, {2370, 1}, {2371, 1}, {2372, 1}, {2373, 1}, {2374, 1}, {2375, 1}, {2376, 1}, {2377, 1}, {2378, 1}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 1}, {2384, 1}, {2385, 1}, {2386, 1}, {2387, 1}, {2388, 1}, {2389, 1}, {2390, 1}, {2391, 1}, {2392, 1}, {2393, 1}, {2394, 1}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 1}, {2399, 1}, {2400, 1}, {2401, 1}, {2402, 1}, {2403, 1}, {2404, 1}, {2405, 1}, - {2406, 1}, {2407, 1}, {2408, 1}, {2409, 1}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 1}, {2418, 1}, {2419, 2}, {2421, 1}, {2422, 2}, - {2424, 6}, {2430, 6}, + {2406, 1}, {2407, 1}, {2408, 1}, {2409, 1}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 1}, {2418, 1}, {2419, 1}, {2420, 1}, {2421, 1}, + {2422, 1}, {2423, 1}, {2424, 1}, {2425, 1}, {2426, 1}, {2427, 1}, {2428, 1}, {2429, 1}, {2430, 1}, {2431, 1}, {2432, 1}, {2433, 1}, {2434, 1}, {2435, 1}, {2436, 1}, {2437, 1}, + {2438, 1}, {2439, 1}, {2440, 1}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 1}, {2445, 1}, {2446, 1}, {2447, 1}, {2448, 1}, {2449, 2}, {2451, 1}, {2452, 2}, {2454, 6}, {2460, 6}, + }; -u8 const Asm_arm64::raw_encode_forms[48720] = { +u8 const Asm_arm64::raw_encode_forms[49320] = { 0x01, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x80, 0xff, 0x00, 0x70, 0x01, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x60, 0x01, 0x00, 0x02, 0x02, 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x70, 0x01, 0x00, 0x03, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x0b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x8b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x01, 0x00, 0x10, 0x10, 0x10, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x20, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x12, 0x12, 0x12, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x60, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x14, 0x14, 0x14, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xa0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x16, 0x16, 0x16, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, @@ -1219,701 +1225,710 @@ u8 const Asm_arm64::raw_encode_forms[48720] = { 0x42, 0x54, 0x04, 0x36, 0x15, 0x13, 0x00, 0x08, 0x40, 0x3a, 0x10, 0x0c, 0xe0, 0xff, 0x00, 0x88, 0x2b, 0x00, 0x02, 0x3e, 0x42, 0x54, 0x04, 0x36, 0x15, 0x13, 0x00, 0x08, 0x40, 0xba, 0x10, 0x0c, 0xe0, 0xff, 0x00, 0x98, 0x2c, 0x00, 0x01, 0x01, 0x01, 0x3d, 0x02, 0x04, 0x07, 0x0a, 0x00, 0x00, 0x80, 0x13, 0x00, 0x80, 0xe0, 0xff, 0x00, 0x80, 0x2c, 0x00, 0x02, 0x02, 0x02, 0x3d, 0x02, 0x04, 0x07, 0x0a, 0x00, 0x00, 0xc0, 0x93, 0x00, 0x80, 0xe0, 0xff, 0x00, 0x90, 0x2d, 0x00, 0x47, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x21, 0x2e, 0x00, 0x47, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x00, 0x00, 0x00, 0xfc, 0x00, 0x21, 0x2f, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0xd6, 0x1f, 0xfc, 0xff, 0xff, 0x00, 0x25, 0x30, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f, 0xd6, 0x1f, 0xfc, 0xff, 0xff, 0x00, 0x25, 0x31, 0x00, 0x02, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5f, 0xd6, 0x1f, 0xfc, 0xff, 0xff, 0x00, 0x25, 0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x03, 0x5f, 0xd6, 0xff, 0xff, - 0xff, 0xff, 0x00, 0x05, 0x32, 0x00, 0x54, 0x48, 0x00, 0x00, 0x14, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x10, 0x00, 0x00, 0xff, 0x00, 0x42, 0x33, 0x00, 0x01, 0x48, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0xff, 0x00, 0x42, 0x33, 0x00, 0x02, 0x48, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x00, 0x00, 0x00, 0xff, 0x00, 0x52, - 0x34, 0x00, 0x01, 0x48, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x35, 0x00, 0x00, 0x00, 0xff, 0x00, 0x42, 0x34, 0x00, 0x02, 0x48, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb5, 0x00, 0x00, 0x00, 0xff, 0x00, 0x52, 0x35, 0x00, 0x02, 0x3e, 0x49, 0x00, 0x03, 0x27, 0x25, 0x00, 0x00, 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x62, 0x36, 0x00, 0x02, 0x3e, - 0x49, 0x00, 0x03, 0x27, 0x25, 0x00, 0x00, 0x00, 0x00, 0x37, 0x00, 0x00, 0x00, 0x7f, 0x00, 0x62, 0x37, 0x00, 0x01, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0xb9, 0x00, 0x00, 0xc0, 0xff, 0x00, 0x40, 0x37, 0x00, 0x02, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0xf9, 0x00, 0x00, 0xc0, 0xff, 0x00, 0x50, 0x37, 0x00, 0x01, 0x48, 0x00, 0x00, 0x03, 0x24, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0xff, 0x00, 0x40, 0x37, 0x00, 0x02, 0x48, 0x00, 0x00, 0x03, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x58, 0x00, 0x00, 0x00, 0xff, 0x00, 0x50, 0x37, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x03, 0x1b, 0x00, 0x00, 0x00, 0x0c, 0x40, 0xb8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x40, 0x37, 0x00, 0x02, 0x4c, 0x00, 0x00, 0x03, 0x1b, 0x00, 0x00, 0x00, 0x0c, - 0x40, 0xf8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x50, 0x37, 0x00, 0x01, 0x4d, 0x00, 0x00, 0x03, 0x1c, 0x00, 0x00, 0x00, 0x04, 0x40, 0xb8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x40, 0x37, 0x00, 0x02, 0x4d, 0x00, 0x00, 0x03, 0x1c, 0x00, 0x00, 0x00, 0x04, 0x40, 0xf8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x50, 0x37, 0x00, 0x01, 0x4e, 0x00, 0x00, 0x03, 0x21, 0x00, 0x00, 0x00, 0x08, 0x60, 0xb8, 0x00, 0x0c, - 0xe0, 0xff, 0x00, 0x40, 0x37, 0x00, 0x02, 0x4e, 0x00, 0x00, 0x03, 0x21, 0x00, 0x00, 0x00, 0x08, 0x60, 0xf8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x50, 0x37, 0x00, 0x09, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0x3d, 0x00, 0x00, 0xc0, 0xff, 0x01, 0x40, 0x37, 0x00, 0x0a, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0x7d, 0x00, 0x00, 0xc0, 0xff, 0x01, 0x40, - 0x37, 0x00, 0x0b, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0xbd, 0x00, 0x00, 0xc0, 0xff, 0x01, 0x40, 0x37, 0x00, 0x0c, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x40, 0xfd, 0x00, 0x00, 0xc0, 0xff, 0x01, 0x40, 0x37, 0x00, 0x0d, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3d, 0x00, 0x00, 0xc0, 0xff, 0x01, 0x40, 0x37, 0x00, 0x1d, 0x51, - 0x00, 0x00, 0x28, 0x53, 0x00, 0x00, 0x00, 0x40, 0x80, 0x85, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x40, 0x37, 0x00, 0x21, 0x51, 0x00, 0x00, 0x48, 0x53, 0x00, 0x00, 0x00, 0x00, 0x80, 0x85, 0x10, 0xe0, 0xe0, 0xff, 0x0d, 0x40, 0x37, 0x00, 0x3e, 0x51, 0x00, 0x00, 0x4f, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe1, 0x00, 0x80, 0xe0, 0xff, 0x0f, 0x40, 0x38, 0x00, 0x01, 0x4b, 0x00, 0x00, 0x03, 0x19, - 0x00, 0x00, 0x00, 0x00, 0x00, 0xb9, 0x00, 0x00, 0xc0, 0xff, 0x00, 0x40, 0x38, 0x00, 0x02, 0x4b, 0x00, 0x00, 0x03, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x00, 0xc0, 0xff, 0x00, 0x50, 0x38, 0x00, 0x01, 0x4c, 0x00, 0x00, 0x03, 0x1b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0xb8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x40, 0x38, 0x00, 0x02, 0x4c, 0x00, 0x00, 0x03, 0x1b, 0x00, 0x00, 0x00, 0x0c, - 0x00, 0xf8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x50, 0x38, 0x00, 0x01, 0x4d, 0x00, 0x00, 0x03, 0x1c, 0x00, 0x00, 0x00, 0x04, 0x00, 0xb8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x40, 0x38, 0x00, 0x02, 0x4d, 0x00, 0x00, 0x03, 0x1c, 0x00, 0x00, 0x00, 0x04, 0x00, 0xf8, 0x00, 0x0c, 0xe0, 0xff, 0x00, 0x50, 0x38, 0x00, 0x01, 0x4e, 0x00, 0x00, 0x03, 0x21, 0x00, 0x00, 0x00, 0x08, 0x20, 0xb8, 0x00, 0x0c, - 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0x1f, 0x00, 0x20, 0x2b, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x48, 0x2f, 0x03, 0x04, 0x08, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 0x1f, 0x00, 0x20, 0xab, 0x1f, 0x00, 0xe0, 0xff, 0x00, 0x58, + 0x2f, 0x03, 0x03, 0x3a, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x31, 0x1f, 0x00, 0x80, 0xff, 0x00, 0x48, 0x2f, 0x03, 0x04, 0x3a, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x1f, 0x00, 0x00, 0xb1, 0x1f, 0x00, 0x80, 0xff, 0x00, 0x58, }; -u8 const Asm_arm64::raw_clobber_forms[34104] = { +u8 const Asm_arm64::raw_clobber_forms[34524] = { 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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@@ gb_internal void check_asm_instruction_operand(AsmCtx *asm_ctx, CheckerContext * gb_string_free(s); } + if (build_context.metrics.arch != TargetArch_arm64) { + error(expr, "The target platform does not support vector element extraction syntax"); + } + operand->mode = Addressing_Value; operand->type = base_array_type(lhs.type); From b12463c4e5531443a322944a071497cbafaf86d5 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Thu, 27 Aug 2026 15:06:35 +0100 Subject: [PATCH 30/89] Update tables --- src/asm_tables_arm64.cpp | 2596 +++++++++++++++++++------------------- 1 file changed, 1308 insertions(+), 1288 deletions(-) diff --git a/src/asm_tables_arm64.cpp b/src/asm_tables_arm64.cpp index 804b24fb2..9bba3ba29 100644 --- a/src/asm_tables_arm64.cpp +++ b/src/asm_tables_arm64.cpp @@ -13,56 +13,56 @@ struct Asm_arm64 { enum Mnemonic : u16 { M_INVALID, M_ADD, M_ADDS, M_SUB, M_SUBS, M_MOVZ, M_MOVN, M_MOVK, M_ADR, M_ADRP, M_AND, M_ANDS, M_ORR, M_EOR, M_BIC, M_BICS, M_ORN, M_EON, M_LSL, M_LSR, M_ASR, M_ROR, M_UDIV, M_SDIV, M_MADD, M_MSUB, M_SMADDL, M_SMSUBL, M_UMADDL, M_UMSUBL, M_SMULH, M_UMULH, - M_CLZ, M_CLS, M_RBIT, M_REV, M_REV16, M_REV32, M_CSEL, M_CSINC, M_CSINV, M_CSNEG, M_CCMP, M_CCMN, M_EXTR, M_B, M_BL, M_BR, - M_BLR, M_RET, M_B_EQ, M_B_NE, M_B_CS, M_B_CC, M_B_MI, M_B_PL, M_B_VS, M_B_VC, M_B_HI, M_B_LS, M_B_GE, M_B_LT, M_B_GT, M_B_LE, - M_B_AL, M_B_NV, M_CBZ, M_CBNZ, M_TBZ, M_TBNZ, M_LDR, M_STR, M_LDRB, M_STRB, M_LDRSB, M_LDRH, M_STRH, M_LDRSH, M_LDRSW, M_LDP, - M_STP, M_LDPSW, M_LDAR, M_STLR, M_LDARB, M_STLRB, M_LDARH, M_STLRH, M_LDXR, M_STXR, M_LDAXR, M_STLXR, M_NOP, M_YIELD, M_WFE, M_WFI, - M_SEV, M_SEVL, M_HINT, M_MRS, M_MSR, M_ISB, M_DSB, M_DMB, M_SVC, M_HVC, M_SMC, M_BRK, M_HLT, M_ERET, M_FMOV, M_FABS, - M_FNEG, M_FSQRT, M_FADD, M_FSUB, M_FMUL, M_FDIV, M_FNMUL, M_FMADD, M_FMSUB, M_FNMADD, M_FNMSUB, M_FCMP, M_FCMPE, M_FCSEL, M_FMAX, M_FMIN, - M_FMAXNM, M_FMINNM, M_FCVT, M_SCVTF, M_UCVTF, M_FCVTZS, M_FCVTZU, M_FCVTAS, M_FCVTAU, M_FCVTNS, M_FCVTNU, M_FCVTPS, M_FCVTPU, M_FCVTMS, M_FCVTMU, M_FRINTA, - M_FRINTI, M_FRINTM, M_FRINTN, M_FRINTP, M_FRINTX, M_FRINTZ, M_TST, M_LDUR, M_STUR, M_LDURB, M_STURB, M_LDURSB, M_LDURH, M_STURH, M_LDURSH, M_LDURSW, - M_LDNP, M_STNP, M_LDXP, M_STXP, M_LDAXP, M_STLXP, M_LDXRB, M_STXRB, M_LDAXRB, M_STLXRB, M_LDXRH, M_STXRH, M_LDAXRH, M_STLXRH, M_LDAPR, M_LDAPRB, - M_LDAPRH, M_LDADD, M_LDADDA, M_LDADDL, M_LDADDAL, M_LDCLR, M_LDCLRA, M_LDCLRL, M_LDCLRAL, M_LDEOR, M_LDEORA, M_LDEORL, M_LDEORAL, M_LDSET, M_LDSETA, M_LDSETL, - M_LDSETAL, M_LDSMAX, M_LDSMAXA, M_LDSMAXL, M_LDSMAXAL, M_LDSMIN, M_LDSMINA, M_LDSMINL, M_LDSMINAL, M_LDUMAX, M_LDUMAXA, M_LDUMAXL, M_LDUMAXAL, M_LDUMIN, M_LDUMINA, M_LDUMINL, - M_LDUMINAL, M_SWP, M_SWPA, M_SWPL, M_SWPAL, M_CAS, M_CASA, M_CASL, M_CASAL, M_CASB, M_CASAB, M_CASLB, M_CASALB, M_CASH, M_CASAH, M_CASLH, - M_CASALH, M_CASP, M_CASPA, M_CASPL, M_CASPAL, M_PACIA, M_PACIB, M_PACDA, M_PACDB, M_PACIZA, M_PACIZB, M_PACDZA, M_PACDZB, M_AUTIA, M_AUTIB, M_AUTDA, - M_AUTDB, M_AUTIZA, M_AUTIZB, M_AUTDZA, M_AUTDZB, M_PACIASP, M_PACIBSP, M_AUTIASP, M_AUTIBSP, M_PACIA1716, M_PACIB1716, M_AUTIA1716, M_AUTIB1716, M_PACGA, M_XPACI, M_XPACD, - M_XPACLRI, M_RETAA, M_RETAB, M_BRAA, M_BRAB, M_BRAAZ, M_BRABZ, M_BLRAA, M_BLRAB, M_BLRAAZ, M_BLRABZ, M_ERETAA, M_ERETAB, M_BTI, M_IRG, M_ADDG, - M_SUBG, M_GMI, M_SUBP, M_SUBPS, M_LDG, M_STG, M_ST2G, M_STZG, M_STZ2G, M_STGP, M_LDGM, M_STGM, M_STZGM, M_CRC32B, M_CRC32H, M_CRC32W, - M_CRC32X, M_CRC32CB, M_CRC32CH, M_CRC32CW, M_CRC32CX, M_AESE, M_AESD, M_AESMC, M_AESIMC, M_SHA1H, M_SHA1C, M_SHA1P, M_SHA1M, M_SHA1SU0, M_SHA1SU1, M_SHA256H, - M_SHA256H2, M_SHA256SU0, M_SHA256SU1, M_SHA512H, M_SHA512H2, M_SHA512SU0, M_SHA512SU1, M_EOR3, M_BCAX, M_RAX1, M_XAR, M_SM3PARTW1, M_SM3PARTW2, M_SM3SS1, M_SM3TT1A, M_SM3TT1B, - M_SM3TT2A, M_SM3TT2B, M_SM4E, M_SM4EKEY, M_PMULL, M_PMULL2, M_BFCVT, M_BFDOT, M_BFMMLA, M_BFMLALB, M_BFMLALT, M_BFCVTN, M_BFCVTN2, M_MUL, M_MLA, M_MLS, - M_NEG, M_ABS, M_SHADD, M_UHADD, M_SHSUB, M_UHSUB, M_SRHADD, M_URHADD, M_SQADD, M_UQADD, M_SQSUB, M_UQSUB, M_SMAX, M_UMAX, M_SMIN, M_UMIN, - M_SABD, M_UABD, M_SABA, M_UABA, M_ADDP, M_ADDV, M_SADDLP, M_UADDLP, M_SADALP, M_UADALP, M_SADDLV, M_UADDLV, M_SMAXV, M_UMAXV, M_SMINV, M_UMINV, - M_SMAXP, M_UMAXP, M_SMINP, M_UMINP, M_SADDL, M_SADDL2, M_UADDL, M_UADDL2, M_SSUBL, M_SSUBL2, M_USUBL, M_USUBL2, M_SADDW, M_SADDW2, M_UADDW, M_UADDW2, - M_SSUBW, M_SSUBW2, M_USUBW, M_USUBW2, M_RADDHN, M_RADDHN2, M_RSUBHN, M_RSUBHN2, M_ADDHN, M_ADDHN2, M_SUBHN, M_SUBHN2, M_XTN, M_XTN2, M_SQXTN, M_SQXTN2, - M_UQXTN, M_UQXTN2, M_SQXTUN, M_SQXTUN2, M_SMULL, M_SMULL2, M_UMULL, M_UMULL2, M_SMLAL, M_SMLAL2, M_UMLAL, M_UMLAL2, M_SMLSL, M_SMLSL2, M_UMLSL, M_UMLSL2, - M_SQDMULL, M_SQDMULL2, M_SQDMLAL, M_SQDMLAL2, M_SQDMLSL, M_SQDMLSL2, M_SQDMULH, M_SQRDMULH, M_SDOT, M_UDOT, M_USDOT, M_FMLA, M_FMLS, M_FMULX, M_FMAXP, M_FMINP, - M_FMAXNMP, M_FMINNMP, M_FMAXV, M_FMINV, M_FMAXNMV, M_FMINNMV, M_FRECPE, M_FRSQRTE, M_FRECPS, M_FRSQRTS, M_FRECPX, M_FADDP, M_FCVTL, M_FCVTL2, M_FCVTN, M_FCVTN2, - M_FCVTXN, M_FCVTXN2, M_FCMEQ, M_FCMGE, M_FCMGT, M_FCMLE, M_FCMLT, M_FACGE, M_FACGT, M_CMEQ, M_CMGE, M_CMGT, M_CMHI, M_CMHS, M_CMLE, M_CMLT, - M_CMTST, M_MVN, M_BIT, M_BIF, M_BSL, M_SHL, M_SQSHL, M_SQSHLU, M_SRSHL, M_URSHL, M_SSHR, M_USHR, M_SSRA, M_USRA, M_SRSHR, M_URSHR, - M_SRSRA, M_URSRA, M_SSHL, M_USHL, M_SLI, M_SRI, M_SSHLL, M_SSHLL2, M_USHLL, M_USHLL2, M_SXTL, M_SXTL2, M_UXTL, M_UXTL2, M_SHRN, M_SHRN2, - M_RSHRN, M_RSHRN2, M_SQSHRN, M_SQSHRN2, M_UQSHRN, M_UQSHRN2, M_SQRSHRN, M_SQRSHRN2, M_UQRSHRN, M_UQRSHRN2, M_SQSHRUN, M_SQSHRUN2, M_SQRSHRUN, M_SQRSHRUN2, M_DUP, M_INS, - M_MOV, M_EXT, M_TBL, M_TBX, M_ZIP1, M_ZIP2, M_UZP1, M_UZP2, M_TRN1, M_TRN2, M_NOT, M_REV64, M_CNT, M_URECPE, M_URSQRTE, M_MOVI, - M_MVNI, M_LD1, M_LD2, M_LD3, M_LD4, M_ST1, M_ST2, M_ST3, M_ST4, M_LD1R, M_LD2R, M_LD3R, M_LD4R, M_SUBR, M_ASRR, M_LSLR, - M_LSRR, M_FTSMUL, M_FSUBR, M_FDIVR, M_FNMLA, M_FNMLS, M_NAND, M_NOR, M_SEL, M_ORRS, M_EORS, M_NANDS, M_NORS, M_ORNS, M_MOVS, M_PTRUE, - M_PTRUES, M_PFALSE, M_PFIRST, M_PNEXT, M_BRKA, M_BRKB, M_BRKAS, M_BRKBS, M_BRKPA, M_BRKPB, M_BRKN, M_RDFFR, M_WRFFR, M_SETFFR, M_CMPEQ, M_CMPNE, - M_CMPGE, M_CMPGT, M_CMPLE, M_CMPLT, M_CMPHI, M_CMPHS, M_CMPLO, M_CMPLS, M_FCMNE, M_FCMUO, M_INSR, M_CPY, M_COMPACT, M_LD1B, M_LD1H, M_LD1W, - M_LD1D, M_LD1SB, M_LD1SH, M_LD1SW, M_ST1B, M_ST1H, M_ST1W, M_ST1D, M_LDFF1B, M_LDFF1H, M_LDFF1W, M_LDFF1D, M_WHILEGE, M_WHILEGT, M_WHILELE, M_WHILELT, - M_WHILEHI, M_WHILEHS, M_WHILELO, M_WHILELS, M_SQRDMLAH, M_SQRDMLSH, M_ADCLB, M_ADCLT, M_SBCLB, M_SBCLT, M_TBL2, M_MATCH, M_NMATCH, M_HISTCNT, M_HISTSEG, M_SMSTART, - M_SMSTOP, M_RDSVL, M_ADDHA, M_ADDVA, M_ZERO, M_FMOPA, M_FMOPS, M_BFMOPA, M_BFMOPS, M_SMOPA, M_SMOPS, M_UMOPA, M_UMOPS, M_USMOPA, M_SUMOPA, M_LD1Q, - M_ST1Q, M_MOVA, M_FCMLA, M_FCADD, M_PRFB, M_PRFH, M_PRFW, M_PRFD, M_LDNT1B, M_LDNT1H, M_LDNT1W, M_LDNT1D, M_STNT1B, M_STNT1H, M_STNT1W, M_STNT1D, - M_SPLICE, M_INDEX, M_BSL1N, M_BSL2N, M_NBSL, M_PMUL, M_PMULLB, M_PMULLT, M_BFCVTNT, M_LDRAA, M_LDRAB, M_TSTART, M_TCOMMIT, M_TCANCEL, M_TTEST, M_WFET, - M_WFIT, M_BC_EQ, M_BC_NE, M_BC_CS, M_BC_CC, M_BC_MI, M_BC_PL, M_BC_VS, M_BC_VC, M_BC_HI, M_BC_LS, M_BC_GE, M_BC_LT, M_BC_GT, M_BC_LE, M_BC_AL, - M_BC_NV, M_UXTB, M_UXTH, M_UXTW, M_SXTB, M_SXTH, M_SXTW, M_ADC, M_ADCS, M_SBC, M_SBCS, M_NGC, M_NGCS, M_LDAPUR, M_STLUR, M_LDAPURB, - M_STLURB, M_LDAPURH, M_STLURH, M_LDAPURSB, M_LDAPURSH, M_LDAPURSW, M_BFADD, M_BFSUB, M_BFMUL, M_BFMLA, M_BFMLS, M_SB, M_CSDB, M_DGH, M_PSB_CSYNC, M_TSB_CSYNC, - M_BTI_J, M_BTI_C, M_BTI_JC, M_BFCLAMP, M_BFMAXNM, M_BFMINNM, M_LUTI2, M_LUTI4, M_ZIP, M_UZP, M_TLBI_RPALOS, M_TLBI_RPAOS, M_AT_S1E1A, M_DC_CIPAPA, M_DC_CIGDPAPA, M_TLBI_PAALL, - M_TLBI_PAALLOS, M_AMX_LDX, M_AMX_LDY, M_AMX_STX, M_AMX_STY, M_AMX_LDZ, M_AMX_STZ, M_AMX_LDZI, M_AMX_STZI, M_AMX_EXTRX, M_AMX_EXTRY, M_AMX_FMA64, M_AMX_FMS64, M_AMX_FMA32, M_AMX_FMS32, M_AMX_MAC16, - M_AMX_FMA16, M_AMX_FMS16, M_AMX_SET, M_AMX_CLR, M_AMX_VECINT, M_AMX_VECFP, M_AMX_MATINT, M_AMX_MATFP, M_AMX_GENLUT, M_CPYP, M_CPYM, M_CPYE, M_CPYFP, M_CPYFM, M_CPYFE, M_SETP, - M_SETM, M_SETE, M_DC_IVAC, M_DC_ISW, M_DC_CSW, M_DC_CISW, M_DC_ZVA, M_DC_CVAC, M_DC_CVAU, M_DC_CIVAC, M_IC_IALLUIS, M_IC_IALLU, M_IC_IVAU, M_AT_S1E1R, M_AT_S1E1W, M_AT_S1E0R, - M_AT_S1E0W, M_AT_S1E2R, M_AT_S1E2W, M_AT_S1E3R, M_AT_S1E3W, M_AT_S12E1R, M_AT_S12E1W, M_AT_S12E0R, M_AT_S12E0W, M_TLBI_VMALLE1, M_TLBI_VMALLE1IS, M_TLBI_VAE1, M_TLBI_VAE1IS, M_TLBI_ASIDE1, M_TLBI_ASIDE1IS, M_TLBI_VAAE1, - M_TLBI_VAAE1IS, M_TLBI_VALE1, M_TLBI_VALE1IS, M_TLBI_VAALE1, M_TLBI_VAALE1IS, M_TLBI_ALLE1, M_TLBI_ALLE1IS, M_TLBI_ALLE2, M_TLBI_ALLE2IS, M_TLBI_ALLE3, M_TLBI_ALLE3IS, M_PRFM, M_PRFUM, M_NEGS, M_CMP, M_CMN, - + M_CLZ, M_CLS, M_RBIT, M_REV, M_REV16, M_REV32, M_CSEL, M_CSINC, M_CSINV, M_CSNEG, M_CCMP, M_CCMN, M_CSET, M_CSETM, M_CINC, M_CINV, + M_CNEG, M_EXTR, M_B, M_BL, M_BR, M_BLR, M_RET, M_B_EQ, M_B_NE, M_B_CS, M_B_CC, M_B_MI, M_B_PL, M_B_VS, M_B_VC, M_B_HI, + M_B_LS, M_B_GE, M_B_LT, M_B_GT, M_B_LE, M_B_AL, M_B_NV, M_CBZ, M_CBNZ, M_TBZ, M_TBNZ, M_LDR, M_STR, M_LDRB, M_STRB, M_LDRSB, + M_LDRH, M_STRH, M_LDRSH, M_LDRSW, M_LDP, M_STP, M_LDPSW, M_LDAR, M_STLR, M_LDARB, M_STLRB, M_LDARH, M_STLRH, M_LDXR, M_STXR, M_LDAXR, + M_STLXR, M_NOP, M_YIELD, M_WFE, M_WFI, M_SEV, M_SEVL, M_HINT, M_MRS, M_MSR, M_ISB, M_DSB, M_DMB, M_SVC, M_HVC, M_SMC, + M_BRK, M_HLT, M_ERET, M_FMOV, M_FABS, M_FNEG, M_FSQRT, M_FADD, M_FSUB, M_FMUL, M_FDIV, M_FNMUL, M_FMADD, M_FMSUB, M_FNMADD, M_FNMSUB, + M_FCMP, M_FCMPE, M_FCSEL, M_FMAX, M_FMIN, M_FMAXNM, M_FMINNM, M_FCVT, M_SCVTF, M_UCVTF, M_FCVTZS, M_FCVTZU, M_FCVTAS, M_FCVTAU, M_FCVTNS, M_FCVTNU, + M_FCVTPS, M_FCVTPU, M_FCVTMS, M_FCVTMU, M_FRINTA, M_FRINTI, M_FRINTM, M_FRINTN, M_FRINTP, M_FRINTX, M_FRINTZ, M_TST, M_LDUR, M_STUR, M_LDURB, M_STURB, + M_LDURSB, M_LDURH, M_STURH, M_LDURSH, M_LDURSW, M_LDNP, M_STNP, M_LDXP, M_STXP, M_LDAXP, M_STLXP, M_LDXRB, M_STXRB, M_LDAXRB, M_STLXRB, M_LDXRH, + M_STXRH, M_LDAXRH, M_STLXRH, M_LDAPR, M_LDAPRB, M_LDAPRH, M_LDADD, M_LDADDA, M_LDADDL, M_LDADDAL, M_LDCLR, M_LDCLRA, M_LDCLRL, M_LDCLRAL, M_LDEOR, M_LDEORA, + M_LDEORL, M_LDEORAL, M_LDSET, M_LDSETA, M_LDSETL, M_LDSETAL, M_LDSMAX, M_LDSMAXA, M_LDSMAXL, M_LDSMAXAL, M_LDSMIN, M_LDSMINA, M_LDSMINL, M_LDSMINAL, M_LDUMAX, M_LDUMAXA, + M_LDUMAXL, M_LDUMAXAL, M_LDUMIN, M_LDUMINA, M_LDUMINL, M_LDUMINAL, M_SWP, M_SWPA, M_SWPL, M_SWPAL, M_CAS, M_CASA, M_CASL, M_CASAL, M_CASB, M_CASAB, + M_CASLB, M_CASALB, M_CASH, M_CASAH, M_CASLH, M_CASALH, M_CASP, M_CASPA, M_CASPL, M_CASPAL, M_PACIA, M_PACIB, M_PACDA, M_PACDB, M_PACIZA, M_PACIZB, + M_PACDZA, M_PACDZB, M_AUTIA, M_AUTIB, M_AUTDA, M_AUTDB, M_AUTIZA, M_AUTIZB, M_AUTDZA, M_AUTDZB, M_PACIASP, M_PACIBSP, M_AUTIASP, M_AUTIBSP, M_PACIA1716, M_PACIB1716, + M_AUTIA1716, M_AUTIB1716, M_PACGA, M_XPACI, M_XPACD, M_XPACLRI, M_RETAA, M_RETAB, M_BRAA, M_BRAB, M_BRAAZ, M_BRABZ, M_BLRAA, M_BLRAB, M_BLRAAZ, M_BLRABZ, + M_ERETAA, M_ERETAB, M_BTI, M_IRG, M_ADDG, M_SUBG, M_GMI, M_SUBP, M_SUBPS, M_LDG, M_STG, M_ST2G, M_STZG, M_STZ2G, M_STGP, M_LDGM, + M_STGM, M_STZGM, M_CRC32B, M_CRC32H, M_CRC32W, M_CRC32X, M_CRC32CB, M_CRC32CH, M_CRC32CW, M_CRC32CX, M_AESE, M_AESD, M_AESMC, M_AESIMC, M_SHA1H, M_SHA1C, + M_SHA1P, M_SHA1M, M_SHA1SU0, M_SHA1SU1, M_SHA256H, M_SHA256H2, M_SHA256SU0, M_SHA256SU1, M_SHA512H, M_SHA512H2, M_SHA512SU0, M_SHA512SU1, M_EOR3, M_BCAX, M_RAX1, M_XAR, + M_SM3PARTW1, M_SM3PARTW2, M_SM3SS1, M_SM3TT1A, M_SM3TT1B, M_SM3TT2A, M_SM3TT2B, M_SM4E, M_SM4EKEY, M_PMULL, M_PMULL2, M_BFCVT, M_BFDOT, M_BFMMLA, M_BFMLALB, M_BFMLALT, + M_BFCVTN, M_BFCVTN2, M_MUL, M_MLA, M_MLS, M_NEG, M_ABS, M_SHADD, M_UHADD, M_SHSUB, M_UHSUB, M_SRHADD, M_URHADD, M_SQADD, M_UQADD, M_SQSUB, + M_UQSUB, M_SMAX, M_UMAX, M_SMIN, M_UMIN, M_SABD, M_UABD, M_SABA, M_UABA, M_ADDP, M_ADDV, M_SADDLP, M_UADDLP, M_SADALP, M_UADALP, M_SADDLV, + M_UADDLV, M_SMAXV, M_UMAXV, M_SMINV, M_UMINV, M_SMAXP, M_UMAXP, M_SMINP, M_UMINP, M_SADDL, M_SADDL2, M_UADDL, M_UADDL2, M_SSUBL, M_SSUBL2, M_USUBL, + M_USUBL2, M_SADDW, M_SADDW2, M_UADDW, M_UADDW2, M_SSUBW, M_SSUBW2, M_USUBW, M_USUBW2, M_RADDHN, M_RADDHN2, M_RSUBHN, M_RSUBHN2, M_ADDHN, M_ADDHN2, M_SUBHN, + M_SUBHN2, M_XTN, M_XTN2, M_SQXTN, M_SQXTN2, M_UQXTN, M_UQXTN2, M_SQXTUN, M_SQXTUN2, M_SMULL, M_SMULL2, M_UMULL, M_UMULL2, M_SMLAL, M_SMLAL2, M_UMLAL, + M_UMLAL2, M_SMLSL, M_SMLSL2, M_UMLSL, M_UMLSL2, M_SQDMULL, M_SQDMULL2, M_SQDMLAL, M_SQDMLAL2, M_SQDMLSL, M_SQDMLSL2, M_SQDMULH, M_SQRDMULH, M_SDOT, M_UDOT, M_USDOT, + M_FMLA, M_FMLS, M_FMULX, M_FMAXP, M_FMINP, M_FMAXNMP, M_FMINNMP, M_FMAXV, M_FMINV, M_FMAXNMV, M_FMINNMV, M_FRECPE, M_FRSQRTE, M_FRECPS, M_FRSQRTS, M_FRECPX, + M_FADDP, M_FCVTL, M_FCVTL2, M_FCVTN, M_FCVTN2, M_FCVTXN, M_FCVTXN2, M_FCMEQ, M_FCMGE, M_FCMGT, M_FCMLE, M_FCMLT, M_FACGE, M_FACGT, M_CMEQ, M_CMGE, + M_CMGT, M_CMHI, M_CMHS, M_CMLE, M_CMLT, M_CMTST, M_MVN, M_BIT, M_BIF, M_BSL, M_SHL, M_SQSHL, M_SQSHLU, M_SRSHL, M_URSHL, M_SSHR, + M_USHR, M_SSRA, M_USRA, M_SRSHR, M_URSHR, M_SRSRA, M_URSRA, M_SSHL, M_USHL, M_SLI, M_SRI, M_SSHLL, M_SSHLL2, M_USHLL, M_USHLL2, M_SXTL, + M_SXTL2, M_UXTL, M_UXTL2, M_SHRN, M_SHRN2, M_RSHRN, M_RSHRN2, M_SQSHRN, M_SQSHRN2, M_UQSHRN, M_UQSHRN2, M_SQRSHRN, M_SQRSHRN2, M_UQRSHRN, M_UQRSHRN2, M_SQSHRUN, + M_SQSHRUN2, M_SQRSHRUN, M_SQRSHRUN2, M_DUP, M_INS, M_MOV, M_EXT, M_TBL, M_TBX, M_ZIP1, M_ZIP2, M_UZP1, M_UZP2, M_TRN1, M_TRN2, M_NOT, + M_REV64, M_CNT, M_URECPE, M_URSQRTE, M_MOVI, M_MVNI, M_LD1, M_LD2, M_LD3, M_LD4, M_ST1, M_ST2, M_ST3, M_ST4, M_LD1R, M_LD2R, + M_LD3R, M_LD4R, M_SUBR, M_ASRR, M_LSLR, M_LSRR, M_FTSMUL, M_FSUBR, M_FDIVR, M_FNMLA, M_FNMLS, M_NAND, M_NOR, M_SEL, M_ORRS, M_EORS, + M_NANDS, M_NORS, M_ORNS, M_MOVS, M_PTRUE, M_PTRUES, M_PFALSE, M_PFIRST, M_PNEXT, M_BRKA, M_BRKB, M_BRKAS, M_BRKBS, M_BRKPA, M_BRKPB, M_BRKN, + M_RDFFR, M_WRFFR, M_SETFFR, M_CMPEQ, M_CMPNE, M_CMPGE, M_CMPGT, M_CMPLE, M_CMPLT, M_CMPHI, M_CMPHS, M_CMPLO, M_CMPLS, M_FCMNE, M_FCMUO, M_INSR, + M_CPY, M_COMPACT, M_LD1B, M_LD1H, M_LD1W, M_LD1D, M_LD1SB, M_LD1SH, M_LD1SW, M_ST1B, M_ST1H, M_ST1W, M_ST1D, M_LDFF1B, M_LDFF1H, M_LDFF1W, + M_LDFF1D, M_WHILEGE, M_WHILEGT, M_WHILELE, M_WHILELT, M_WHILEHI, M_WHILEHS, M_WHILELO, M_WHILELS, M_SQRDMLAH, M_SQRDMLSH, M_ADCLB, M_ADCLT, M_SBCLB, M_SBCLT, M_TBL2, + M_MATCH, M_NMATCH, M_HISTCNT, M_HISTSEG, M_SMSTART, M_SMSTOP, M_RDSVL, M_ADDHA, M_ADDVA, M_ZERO, M_FMOPA, M_FMOPS, M_BFMOPA, M_BFMOPS, M_SMOPA, M_SMOPS, + M_UMOPA, M_UMOPS, M_USMOPA, M_SUMOPA, M_LD1Q, M_ST1Q, M_MOVA, M_FCMLA, M_FCADD, M_PRFB, M_PRFH, M_PRFW, M_PRFD, M_LDNT1B, M_LDNT1H, M_LDNT1W, + M_LDNT1D, M_STNT1B, M_STNT1H, M_STNT1W, M_STNT1D, M_SPLICE, M_INDEX, M_BSL1N, M_BSL2N, M_NBSL, M_PMUL, M_PMULLB, M_PMULLT, M_BFCVTNT, M_LDRAA, M_LDRAB, + M_TSTART, M_TCOMMIT, M_TCANCEL, M_TTEST, M_WFET, M_WFIT, M_BC_EQ, M_BC_NE, M_BC_CS, M_BC_CC, M_BC_MI, M_BC_PL, M_BC_VS, M_BC_VC, M_BC_HI, M_BC_LS, + M_BC_GE, M_BC_LT, M_BC_GT, M_BC_LE, M_BC_AL, M_BC_NV, M_UXTB, M_UXTH, M_UXTW, M_SXTB, M_SXTH, M_SXTW, M_ADC, M_ADCS, M_SBC, M_SBCS, + M_NGC, M_NGCS, M_LDAPUR, M_STLUR, M_LDAPURB, M_STLURB, M_LDAPURH, M_STLURH, M_LDAPURSB, M_LDAPURSH, M_LDAPURSW, M_BFADD, M_BFSUB, M_BFMUL, M_BFMLA, M_BFMLS, + M_SB, M_CSDB, M_DGH, M_PSB_CSYNC, M_TSB_CSYNC, M_BTI_J, M_BTI_C, M_BTI_JC, M_BFCLAMP, M_BFMAXNM, M_BFMINNM, M_LUTI2, M_LUTI4, M_ZIP, M_UZP, M_TLBI_RPALOS, + M_TLBI_RPAOS, M_AT_S1E1A, M_DC_CIPAPA, M_DC_CIGDPAPA, M_TLBI_PAALL, M_TLBI_PAALLOS, M_AMX_LDX, M_AMX_LDY, M_AMX_STX, M_AMX_STY, M_AMX_LDZ, M_AMX_STZ, M_AMX_LDZI, M_AMX_STZI, M_AMX_EXTRX, M_AMX_EXTRY, + M_AMX_FMA64, M_AMX_FMS64, M_AMX_FMA32, M_AMX_FMS32, M_AMX_MAC16, M_AMX_FMA16, M_AMX_FMS16, M_AMX_SET, M_AMX_CLR, M_AMX_VECINT, M_AMX_VECFP, M_AMX_MATINT, M_AMX_MATFP, M_AMX_GENLUT, M_CPYP, M_CPYM, + M_CPYE, M_CPYFP, M_CPYFM, M_CPYFE, M_SETP, M_SETM, M_SETE, M_DC_IVAC, M_DC_ISW, M_DC_CSW, M_DC_CISW, M_DC_ZVA, M_DC_CVAC, M_DC_CVAU, M_DC_CIVAC, M_IC_IALLUIS, + M_IC_IALLU, M_IC_IVAU, M_AT_S1E1R, M_AT_S1E1W, M_AT_S1E0R, M_AT_S1E0W, M_AT_S1E2R, M_AT_S1E2W, M_AT_S1E3R, M_AT_S1E3W, M_AT_S12E1R, M_AT_S12E1W, M_AT_S12E0R, M_AT_S12E0W, M_TLBI_VMALLE1, M_TLBI_VMALLE1IS, + M_TLBI_VAE1, M_TLBI_VAE1IS, M_TLBI_ASIDE1, M_TLBI_ASIDE1IS, M_TLBI_VAAE1, M_TLBI_VAAE1IS, M_TLBI_VALE1, M_TLBI_VALE1IS, M_TLBI_VAALE1, M_TLBI_VAALE1IS, M_TLBI_ALLE1, M_TLBI_ALLE1IS, M_TLBI_ALLE2, M_TLBI_ALLE2IS, M_TLBI_ALLE3, M_TLBI_ALLE3IS, + M_PRFM, M_PRFUM, M_NEGS, M_CMP, M_CMN, MNEMONIC_COUNT }; @@ -481,6 +481,7 @@ struct Asm_arm64 { OP_MEM_SVE_VEC, OP_MEM_SVE_VB, OP_COND, + OP_COND_NOT_AL, OP_VEC_SHIFT, OP_VEC_INDEX, }; @@ -495,6 +496,7 @@ struct Asm_arm64 { ENC_RT2, ENC_RA, ENC_RM, + ENC_RN_RM, ENC_IMM12, ENC_IMM16, ENC_IMM6, @@ -507,6 +509,7 @@ struct Asm_arm64 { ENC_EXT_OPT, ENC_EXT_IMM3, ENC_COND_HI, + ENC_COND_HI_INV, ENC_COND_LO, ENC_NZCV_FIELD, ENC_SYS_FIELD, @@ -649,9 +652,9 @@ struct Asm_arm64 { }; - static EncodeRun const raw_encode_runs [816]; - static u8 const raw_encode_forms [49320]; - static u8 const raw_clobber_forms[34524]; + static EncodeRun const raw_encode_runs [821]; + static u8 const raw_encode_forms [49920]; + static u8 const raw_clobber_forms[34944]; StringMap mnemonic_map; StringMap register_map; @@ -1031,56 +1034,56 @@ String const Asm_arm64::prefix_strings[Asm_arm64::PREFIX_COUNT]{}; String const Asm_arm64::mnemonic_strings[Asm_arm64::MNEMONIC_COUNT] { str_lit(""), str_lit("add"), str_lit("adds"), str_lit("sub"), str_lit("subs"), str_lit("movz"), str_lit("movn"), str_lit("movk"), str_lit("adr"), str_lit("adrp"), str_lit("and"), str_lit("ands"), str_lit("orr"), str_lit("eor"), str_lit("bic"), str_lit("bics"), str_lit("orn"), str_lit("eon"), str_lit("lsl"), str_lit("lsr"), str_lit("asr"), str_lit("ror"), str_lit("udiv"), str_lit("sdiv"), str_lit("madd"), str_lit("msub"), str_lit("smaddl"), str_lit("smsubl"), str_lit("umaddl"), str_lit("umsubl"), str_lit("smulh"), str_lit("umulh"), - str_lit("clz"), str_lit("cls"), str_lit("rbit"), str_lit("rev"), str_lit("rev16"), str_lit("rev32"), str_lit("csel"), str_lit("csinc"), str_lit("csinv"), str_lit("csneg"), str_lit("ccmp"), str_lit("ccmn"), str_lit("extr"), str_lit("b"), str_lit("bl"), str_lit("br"), - str_lit("blr"), str_lit("ret"), str_lit("b_eq"), str_lit("b_ne"), str_lit("b_cs"), str_lit("b_cc"), str_lit("b_mi"), str_lit("b_pl"), str_lit("b_vs"), str_lit("b_vc"), str_lit("b_hi"), str_lit("b_ls"), str_lit("b_ge"), str_lit("b_lt"), str_lit("b_gt"), str_lit("b_le"), - str_lit("b_al"), str_lit("b_nv"), str_lit("cbz"), str_lit("cbnz"), str_lit("tbz"), str_lit("tbnz"), str_lit("ldr"), str_lit("str"), str_lit("ldrb"), str_lit("strb"), str_lit("ldrsb"), str_lit("ldrh"), str_lit("strh"), str_lit("ldrsh"), str_lit("ldrsw"), str_lit("ldp"), - str_lit("stp"), str_lit("ldpsw"), str_lit("ldar"), str_lit("stlr"), str_lit("ldarb"), str_lit("stlrb"), str_lit("ldarh"), str_lit("stlrh"), str_lit("ldxr"), str_lit("stxr"), str_lit("ldaxr"), str_lit("stlxr"), str_lit("nop"), str_lit("yield"), str_lit("wfe"), str_lit("wfi"), - str_lit("sev"), str_lit("sevl"), str_lit("hint"), str_lit("mrs"), str_lit("msr"), str_lit("isb"), str_lit("dsb"), str_lit("dmb"), str_lit("svc"), str_lit("hvc"), str_lit("smc"), str_lit("brk"), str_lit("hlt"), str_lit("eret"), str_lit("fmov"), str_lit("fabs"), - str_lit("fneg"), str_lit("fsqrt"), str_lit("fadd"), str_lit("fsub"), str_lit("fmul"), str_lit("fdiv"), str_lit("fnmul"), str_lit("fmadd"), str_lit("fmsub"), str_lit("fnmadd"), str_lit("fnmsub"), str_lit("fcmp"), str_lit("fcmpe"), str_lit("fcsel"), str_lit("fmax"), str_lit("fmin"), - str_lit("fmaxnm"), str_lit("fminnm"), str_lit("fcvt"), str_lit("scvtf"), str_lit("ucvtf"), str_lit("fcvtzs"), str_lit("fcvtzu"), str_lit("fcvtas"), str_lit("fcvtau"), str_lit("fcvtns"), str_lit("fcvtnu"), str_lit("fcvtps"), str_lit("fcvtpu"), str_lit("fcvtms"), str_lit("fcvtmu"), str_lit("frinta"), - str_lit("frinti"), str_lit("frintm"), str_lit("frintn"), str_lit("frintp"), str_lit("frintx"), str_lit("frintz"), str_lit("tst"), str_lit("ldur"), str_lit("stur"), str_lit("ldurb"), str_lit("sturb"), str_lit("ldursb"), str_lit("ldurh"), str_lit("sturh"), str_lit("ldursh"), str_lit("ldursw"), - str_lit("ldnp"), str_lit("stnp"), str_lit("ldxp"), str_lit("stxp"), str_lit("ldaxp"), str_lit("stlxp"), str_lit("ldxrb"), str_lit("stxrb"), str_lit("ldaxrb"), str_lit("stlxrb"), str_lit("ldxrh"), str_lit("stxrh"), str_lit("ldaxrh"), str_lit("stlxrh"), str_lit("ldapr"), str_lit("ldaprb"), - str_lit("ldaprh"), str_lit("ldadd"), str_lit("ldadda"), str_lit("ldaddl"), str_lit("ldaddal"), str_lit("ldclr"), str_lit("ldclra"), str_lit("ldclrl"), str_lit("ldclral"), str_lit("ldeor"), str_lit("ldeora"), str_lit("ldeorl"), str_lit("ldeoral"), str_lit("ldset"), str_lit("ldseta"), str_lit("ldsetl"), - str_lit("ldsetal"), str_lit("ldsmax"), str_lit("ldsmaxa"), str_lit("ldsmaxl"), str_lit("ldsmaxal"), str_lit("ldsmin"), str_lit("ldsmina"), str_lit("ldsminl"), str_lit("ldsminal"), str_lit("ldumax"), str_lit("ldumaxa"), str_lit("ldumaxl"), str_lit("ldumaxal"), str_lit("ldumin"), str_lit("ldumina"), str_lit("lduminl"), - str_lit("lduminal"), str_lit("swp"), str_lit("swpa"), str_lit("swpl"), str_lit("swpal"), str_lit("cas"), str_lit("casa"), str_lit("casl"), str_lit("casal"), str_lit("casb"), str_lit("casab"), str_lit("caslb"), str_lit("casalb"), str_lit("cash"), str_lit("casah"), str_lit("caslh"), - str_lit("casalh"), str_lit("casp"), str_lit("caspa"), str_lit("caspl"), str_lit("caspal"), str_lit("pacia"), str_lit("pacib"), str_lit("pacda"), str_lit("pacdb"), str_lit("paciza"), str_lit("pacizb"), str_lit("pacdza"), str_lit("pacdzb"), str_lit("autia"), str_lit("autib"), str_lit("autda"), - str_lit("autdb"), str_lit("autiza"), str_lit("autizb"), str_lit("autdza"), str_lit("autdzb"), str_lit("paciasp"), str_lit("pacibsp"), str_lit("autiasp"), str_lit("autibsp"), str_lit("pacia1716"), str_lit("pacib1716"), str_lit("autia1716"), str_lit("autib1716"), str_lit("pacga"), str_lit("xpaci"), str_lit("xpacd"), - str_lit("xpaclri"), str_lit("retaa"), str_lit("retab"), str_lit("braa"), str_lit("brab"), str_lit("braaz"), str_lit("brabz"), str_lit("blraa"), str_lit("blrab"), str_lit("blraaz"), str_lit("blrabz"), str_lit("eretaa"), str_lit("eretab"), str_lit("bti"), str_lit("irg"), str_lit("addg"), - str_lit("subg"), str_lit("gmi"), str_lit("subp"), str_lit("subps"), str_lit("ldg"), str_lit("stg"), str_lit("st2g"), str_lit("stzg"), str_lit("stz2g"), str_lit("stgp"), str_lit("ldgm"), str_lit("stgm"), str_lit("stzgm"), str_lit("crc32b"), str_lit("crc32h"), str_lit("crc32w"), - str_lit("crc32x"), str_lit("crc32cb"), str_lit("crc32ch"), str_lit("crc32cw"), str_lit("crc32cx"), str_lit("aese"), str_lit("aesd"), str_lit("aesmc"), str_lit("aesimc"), str_lit("sha1h"), str_lit("sha1c"), str_lit("sha1p"), str_lit("sha1m"), str_lit("sha1su0"), str_lit("sha1su1"), str_lit("sha256h"), - str_lit("sha256h2"), str_lit("sha256su0"), str_lit("sha256su1"), str_lit("sha512h"), str_lit("sha512h2"), str_lit("sha512su0"), str_lit("sha512su1"), str_lit("eor3"), str_lit("bcax"), str_lit("rax1"), str_lit("xar"), str_lit("sm3partw1"), str_lit("sm3partw2"), str_lit("sm3ss1"), str_lit("sm3tt1a"), str_lit("sm3tt1b"), - str_lit("sm3tt2a"), str_lit("sm3tt2b"), str_lit("sm4e"), str_lit("sm4ekey"), str_lit("pmull"), str_lit("pmull2"), str_lit("bfcvt"), str_lit("bfdot"), str_lit("bfmmla"), str_lit("bfmlalb"), str_lit("bfmlalt"), str_lit("bfcvtn"), str_lit("bfcvtn2"), str_lit("mul"), str_lit("mla"), str_lit("mls"), - str_lit("neg"), str_lit("abs"), str_lit("shadd"), str_lit("uhadd"), str_lit("shsub"), str_lit("uhsub"), str_lit("srhadd"), str_lit("urhadd"), str_lit("sqadd"), str_lit("uqadd"), str_lit("sqsub"), str_lit("uqsub"), str_lit("smax"), str_lit("umax"), str_lit("smin"), str_lit("umin"), - str_lit("sabd"), str_lit("uabd"), str_lit("saba"), str_lit("uaba"), str_lit("addp"), str_lit("addv"), str_lit("saddlp"), str_lit("uaddlp"), str_lit("sadalp"), str_lit("uadalp"), str_lit("saddlv"), str_lit("uaddlv"), str_lit("smaxv"), str_lit("umaxv"), str_lit("sminv"), str_lit("uminv"), - str_lit("smaxp"), str_lit("umaxp"), str_lit("sminp"), str_lit("uminp"), str_lit("saddl"), str_lit("saddl2"), str_lit("uaddl"), str_lit("uaddl2"), str_lit("ssubl"), str_lit("ssubl2"), str_lit("usubl"), str_lit("usubl2"), str_lit("saddw"), str_lit("saddw2"), str_lit("uaddw"), str_lit("uaddw2"), - str_lit("ssubw"), str_lit("ssubw2"), str_lit("usubw"), str_lit("usubw2"), str_lit("raddhn"), str_lit("raddhn2"), str_lit("rsubhn"), str_lit("rsubhn2"), str_lit("addhn"), str_lit("addhn2"), str_lit("subhn"), str_lit("subhn2"), str_lit("xtn"), str_lit("xtn2"), str_lit("sqxtn"), str_lit("sqxtn2"), - str_lit("uqxtn"), str_lit("uqxtn2"), str_lit("sqxtun"), str_lit("sqxtun2"), str_lit("smull"), str_lit("smull2"), str_lit("umull"), str_lit("umull2"), str_lit("smlal"), str_lit("smlal2"), str_lit("umlal"), str_lit("umlal2"), str_lit("smlsl"), str_lit("smlsl2"), str_lit("umlsl"), str_lit("umlsl2"), - str_lit("sqdmull"), str_lit("sqdmull2"), str_lit("sqdmlal"), str_lit("sqdmlal2"), str_lit("sqdmlsl"), str_lit("sqdmlsl2"), str_lit("sqdmulh"), str_lit("sqrdmulh"), str_lit("sdot"), str_lit("udot"), str_lit("usdot"), str_lit("fmla"), str_lit("fmls"), str_lit("fmulx"), str_lit("fmaxp"), str_lit("fminp"), - str_lit("fmaxnmp"), str_lit("fminnmp"), str_lit("fmaxv"), str_lit("fminv"), str_lit("fmaxnmv"), str_lit("fminnmv"), str_lit("frecpe"), str_lit("frsqrte"), str_lit("frecps"), str_lit("frsqrts"), str_lit("frecpx"), str_lit("faddp"), str_lit("fcvtl"), str_lit("fcvtl2"), str_lit("fcvtn"), str_lit("fcvtn2"), - str_lit("fcvtxn"), str_lit("fcvtxn2"), str_lit("fcmeq"), str_lit("fcmge"), str_lit("fcmgt"), str_lit("fcmle"), str_lit("fcmlt"), str_lit("facge"), str_lit("facgt"), str_lit("cmeq"), str_lit("cmge"), str_lit("cmgt"), str_lit("cmhi"), str_lit("cmhs"), str_lit("cmle"), str_lit("cmlt"), - str_lit("cmtst"), str_lit("mvn"), str_lit("bit"), str_lit("bif"), str_lit("bsl"), str_lit("shl"), str_lit("sqshl"), str_lit("sqshlu"), str_lit("srshl"), str_lit("urshl"), str_lit("sshr"), str_lit("ushr"), str_lit("ssra"), str_lit("usra"), str_lit("srshr"), str_lit("urshr"), - str_lit("srsra"), str_lit("ursra"), str_lit("sshl"), str_lit("ushl"), str_lit("sli"), str_lit("sri"), str_lit("sshll"), str_lit("sshll2"), str_lit("ushll"), str_lit("ushll2"), str_lit("sxtl"), str_lit("sxtl2"), str_lit("uxtl"), str_lit("uxtl2"), str_lit("shrn"), str_lit("shrn2"), - str_lit("rshrn"), str_lit("rshrn2"), str_lit("sqshrn"), str_lit("sqshrn2"), str_lit("uqshrn"), str_lit("uqshrn2"), str_lit("sqrshrn"), str_lit("sqrshrn2"), str_lit("uqrshrn"), str_lit("uqrshrn2"), str_lit("sqshrun"), str_lit("sqshrun2"), str_lit("sqrshrun"), str_lit("sqrshrun2"), str_lit("dup"), str_lit("ins"), - str_lit("mov"), str_lit("ext"), str_lit("tbl"), str_lit("tbx"), str_lit("zip1"), str_lit("zip2"), str_lit("uzp1"), str_lit("uzp2"), str_lit("trn1"), str_lit("trn2"), str_lit("not"), str_lit("rev64"), str_lit("cnt"), str_lit("urecpe"), str_lit("ursqrte"), str_lit("movi"), - str_lit("mvni"), str_lit("ld1"), str_lit("ld2"), str_lit("ld3"), str_lit("ld4"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("ld1r"), str_lit("ld2r"), str_lit("ld3r"), str_lit("ld4r"), str_lit("subr"), str_lit("asrr"), str_lit("lslr"), - str_lit("lsrr"), str_lit("ftsmul"), str_lit("fsubr"), str_lit("fdivr"), str_lit("fnmla"), str_lit("fnmls"), str_lit("nand"), str_lit("nor"), str_lit("sel"), str_lit("orrs"), str_lit("eors"), str_lit("nands"), str_lit("nors"), str_lit("orns"), str_lit("movs"), str_lit("ptrue"), - str_lit("ptrues"), str_lit("pfalse"), str_lit("pfirst"), str_lit("pnext"), str_lit("brka"), str_lit("brkb"), str_lit("brkas"), str_lit("brkbs"), str_lit("brkpa"), str_lit("brkpb"), str_lit("brkn"), str_lit("rdffr"), str_lit("wrffr"), str_lit("setffr"), str_lit("cmpeq"), str_lit("cmpne"), - str_lit("cmpge"), str_lit("cmpgt"), str_lit("cmple"), str_lit("cmplt"), str_lit("cmphi"), str_lit("cmphs"), str_lit("cmplo"), str_lit("cmpls"), str_lit("fcmne"), str_lit("fcmuo"), str_lit("insr"), str_lit("cpy"), str_lit("compact"), str_lit("ld1b"), str_lit("ld1h"), str_lit("ld1w"), - str_lit("ld1d"), str_lit("ld1sb"), str_lit("ld1sh"), str_lit("ld1sw"), str_lit("st1b"), str_lit("st1h"), str_lit("st1w"), str_lit("st1d"), str_lit("ldff1b"), str_lit("ldff1h"), str_lit("ldff1w"), str_lit("ldff1d"), str_lit("whilege"), str_lit("whilegt"), str_lit("whilele"), str_lit("whilelt"), - str_lit("whilehi"), str_lit("whilehs"), str_lit("whilelo"), str_lit("whilels"), str_lit("sqrdmlah"), str_lit("sqrdmlsh"), str_lit("adclb"), str_lit("adclt"), str_lit("sbclb"), str_lit("sbclt"), str_lit("tbl2"), str_lit("match"), str_lit("nmatch"), str_lit("histcnt"), str_lit("histseg"), str_lit("smstart"), - str_lit("smstop"), str_lit("rdsvl"), str_lit("addha"), str_lit("addva"), str_lit("zero"), str_lit("fmopa"), str_lit("fmops"), str_lit("bfmopa"), str_lit("bfmops"), str_lit("smopa"), str_lit("smops"), str_lit("umopa"), str_lit("umops"), str_lit("usmopa"), str_lit("sumopa"), str_lit("ld1q"), - str_lit("st1q"), str_lit("mova"), str_lit("fcmla"), str_lit("fcadd"), str_lit("prfb"), str_lit("prfh"), str_lit("prfw"), str_lit("prfd"), str_lit("ldnt1b"), str_lit("ldnt1h"), str_lit("ldnt1w"), str_lit("ldnt1d"), str_lit("stnt1b"), str_lit("stnt1h"), str_lit("stnt1w"), str_lit("stnt1d"), - str_lit("splice"), str_lit("index"), str_lit("bsl1n"), str_lit("bsl2n"), str_lit("nbsl"), str_lit("pmul"), str_lit("pmullb"), str_lit("pmullt"), str_lit("bfcvtnt"), str_lit("ldraa"), str_lit("ldrab"), str_lit("tstart"), str_lit("tcommit"), str_lit("tcancel"), str_lit("ttest"), str_lit("wfet"), - str_lit("wfit"), str_lit("bc_eq"), str_lit("bc_ne"), str_lit("bc_cs"), str_lit("bc_cc"), str_lit("bc_mi"), str_lit("bc_pl"), str_lit("bc_vs"), str_lit("bc_vc"), str_lit("bc_hi"), str_lit("bc_ls"), str_lit("bc_ge"), str_lit("bc_lt"), str_lit("bc_gt"), str_lit("bc_le"), str_lit("bc_al"), - str_lit("bc_nv"), str_lit("uxtb"), str_lit("uxth"), str_lit("uxtw"), str_lit("sxtb"), str_lit("sxth"), str_lit("sxtw"), str_lit("adc"), str_lit("adcs"), str_lit("sbc"), str_lit("sbcs"), str_lit("ngc"), str_lit("ngcs"), str_lit("ldapur"), str_lit("stlur"), str_lit("ldapurb"), - str_lit("stlurb"), str_lit("ldapurh"), str_lit("stlurh"), str_lit("ldapursb"), str_lit("ldapursh"), str_lit("ldapursw"), str_lit("bfadd"), str_lit("bfsub"), str_lit("bfmul"), str_lit("bfmla"), str_lit("bfmls"), str_lit("sb"), str_lit("csdb"), str_lit("dgh"), str_lit("psb_csync"), str_lit("tsb_csync"), - str_lit("bti_j"), str_lit("bti_c"), str_lit("bti_jc"), str_lit("bfclamp"), str_lit("bfmaxnm"), str_lit("bfminnm"), str_lit("luti2"), str_lit("luti4"), str_lit("zip"), str_lit("uzp"), str_lit("tlbi_rpalos"), str_lit("tlbi_rpaos"), str_lit("at_s1e1a"), str_lit("dc_cipapa"), str_lit("dc_cigdpapa"), str_lit("tlbi_paall"), - str_lit("tlbi_paallos"), str_lit("amx_ldx"), str_lit("amx_ldy"), str_lit("amx_stx"), str_lit("amx_sty"), str_lit("amx_ldz"), str_lit("amx_stz"), str_lit("amx_ldzi"), str_lit("amx_stzi"), str_lit("amx_extrx"), str_lit("amx_extry"), str_lit("amx_fma64"), str_lit("amx_fms64"), str_lit("amx_fma32"), str_lit("amx_fms32"), str_lit("amx_mac16"), - str_lit("amx_fma16"), str_lit("amx_fms16"), str_lit("amx_set"), str_lit("amx_clr"), str_lit("amx_vecint"), str_lit("amx_vecfp"), str_lit("amx_matint"), str_lit("amx_matfp"), str_lit("amx_genlut"), str_lit("cpyp"), str_lit("cpym"), str_lit("cpye"), str_lit("cpyfp"), str_lit("cpyfm"), str_lit("cpyfe"), str_lit("setp"), - str_lit("setm"), str_lit("sete"), str_lit("dc_ivac"), str_lit("dc_isw"), str_lit("dc_csw"), str_lit("dc_cisw"), str_lit("dc_zva"), str_lit("dc_cvac"), str_lit("dc_cvau"), str_lit("dc_civac"), str_lit("ic_ialluis"), str_lit("ic_iallu"), str_lit("ic_ivau"), str_lit("at_s1e1r"), str_lit("at_s1e1w"), str_lit("at_s1e0r"), - str_lit("at_s1e0w"), str_lit("at_s1e2r"), str_lit("at_s1e2w"), str_lit("at_s1e3r"), str_lit("at_s1e3w"), str_lit("at_s12e1r"), str_lit("at_s12e1w"), str_lit("at_s12e0r"), str_lit("at_s12e0w"), str_lit("tlbi_vmalle1"), str_lit("tlbi_vmalle1is"), str_lit("tlbi_vae1"), str_lit("tlbi_vae1is"), str_lit("tlbi_aside1"), str_lit("tlbi_aside1is"), str_lit("tlbi_vaae1"), - str_lit("tlbi_vaae1is"), str_lit("tlbi_vale1"), str_lit("tlbi_vale1is"), str_lit("tlbi_vaale1"), str_lit("tlbi_vaale1is"), str_lit("tlbi_alle1"), str_lit("tlbi_alle1is"), str_lit("tlbi_alle2"), str_lit("tlbi_alle2is"), str_lit("tlbi_alle3"), str_lit("tlbi_alle3is"), str_lit("prfm"), str_lit("prfum"), str_lit("negs"), str_lit("cmp"), str_lit("cmn"), - + str_lit("clz"), str_lit("cls"), str_lit("rbit"), str_lit("rev"), str_lit("rev16"), str_lit("rev32"), str_lit("csel"), str_lit("csinc"), str_lit("csinv"), str_lit("csneg"), str_lit("ccmp"), str_lit("ccmn"), str_lit("cset"), str_lit("csetm"), str_lit("cinc"), str_lit("cinv"), + str_lit("cneg"), str_lit("extr"), str_lit("b"), str_lit("bl"), str_lit("br"), str_lit("blr"), str_lit("ret"), str_lit("b_eq"), str_lit("b_ne"), str_lit("b_cs"), str_lit("b_cc"), str_lit("b_mi"), str_lit("b_pl"), str_lit("b_vs"), str_lit("b_vc"), str_lit("b_hi"), + str_lit("b_ls"), str_lit("b_ge"), str_lit("b_lt"), str_lit("b_gt"), str_lit("b_le"), str_lit("b_al"), str_lit("b_nv"), str_lit("cbz"), str_lit("cbnz"), str_lit("tbz"), str_lit("tbnz"), str_lit("ldr"), str_lit("str"), str_lit("ldrb"), str_lit("strb"), str_lit("ldrsb"), + str_lit("ldrh"), str_lit("strh"), str_lit("ldrsh"), str_lit("ldrsw"), str_lit("ldp"), str_lit("stp"), str_lit("ldpsw"), str_lit("ldar"), str_lit("stlr"), str_lit("ldarb"), str_lit("stlrb"), str_lit("ldarh"), str_lit("stlrh"), str_lit("ldxr"), str_lit("stxr"), str_lit("ldaxr"), + str_lit("stlxr"), str_lit("nop"), str_lit("yield"), str_lit("wfe"), str_lit("wfi"), str_lit("sev"), str_lit("sevl"), str_lit("hint"), str_lit("mrs"), str_lit("msr"), str_lit("isb"), str_lit("dsb"), str_lit("dmb"), str_lit("svc"), str_lit("hvc"), str_lit("smc"), + str_lit("brk"), str_lit("hlt"), str_lit("eret"), str_lit("fmov"), str_lit("fabs"), str_lit("fneg"), str_lit("fsqrt"), str_lit("fadd"), str_lit("fsub"), str_lit("fmul"), str_lit("fdiv"), str_lit("fnmul"), str_lit("fmadd"), str_lit("fmsub"), str_lit("fnmadd"), str_lit("fnmsub"), + str_lit("fcmp"), str_lit("fcmpe"), str_lit("fcsel"), str_lit("fmax"), str_lit("fmin"), str_lit("fmaxnm"), str_lit("fminnm"), str_lit("fcvt"), str_lit("scvtf"), str_lit("ucvtf"), str_lit("fcvtzs"), str_lit("fcvtzu"), str_lit("fcvtas"), str_lit("fcvtau"), str_lit("fcvtns"), str_lit("fcvtnu"), + str_lit("fcvtps"), str_lit("fcvtpu"), str_lit("fcvtms"), str_lit("fcvtmu"), str_lit("frinta"), str_lit("frinti"), str_lit("frintm"), str_lit("frintn"), str_lit("frintp"), str_lit("frintx"), str_lit("frintz"), str_lit("tst"), str_lit("ldur"), str_lit("stur"), str_lit("ldurb"), str_lit("sturb"), + str_lit("ldursb"), str_lit("ldurh"), str_lit("sturh"), str_lit("ldursh"), str_lit("ldursw"), str_lit("ldnp"), str_lit("stnp"), str_lit("ldxp"), str_lit("stxp"), str_lit("ldaxp"), str_lit("stlxp"), str_lit("ldxrb"), str_lit("stxrb"), str_lit("ldaxrb"), str_lit("stlxrb"), str_lit("ldxrh"), + str_lit("stxrh"), str_lit("ldaxrh"), str_lit("stlxrh"), str_lit("ldapr"), str_lit("ldaprb"), str_lit("ldaprh"), str_lit("ldadd"), str_lit("ldadda"), str_lit("ldaddl"), str_lit("ldaddal"), str_lit("ldclr"), str_lit("ldclra"), str_lit("ldclrl"), str_lit("ldclral"), str_lit("ldeor"), str_lit("ldeora"), + str_lit("ldeorl"), str_lit("ldeoral"), str_lit("ldset"), str_lit("ldseta"), str_lit("ldsetl"), str_lit("ldsetal"), str_lit("ldsmax"), str_lit("ldsmaxa"), str_lit("ldsmaxl"), str_lit("ldsmaxal"), str_lit("ldsmin"), str_lit("ldsmina"), str_lit("ldsminl"), str_lit("ldsminal"), str_lit("ldumax"), str_lit("ldumaxa"), + str_lit("ldumaxl"), str_lit("ldumaxal"), str_lit("ldumin"), str_lit("ldumina"), str_lit("lduminl"), str_lit("lduminal"), str_lit("swp"), str_lit("swpa"), str_lit("swpl"), str_lit("swpal"), str_lit("cas"), str_lit("casa"), str_lit("casl"), str_lit("casal"), str_lit("casb"), str_lit("casab"), + str_lit("caslb"), str_lit("casalb"), str_lit("cash"), str_lit("casah"), str_lit("caslh"), str_lit("casalh"), str_lit("casp"), str_lit("caspa"), str_lit("caspl"), str_lit("caspal"), str_lit("pacia"), str_lit("pacib"), str_lit("pacda"), str_lit("pacdb"), str_lit("paciza"), str_lit("pacizb"), + str_lit("pacdza"), str_lit("pacdzb"), str_lit("autia"), str_lit("autib"), str_lit("autda"), str_lit("autdb"), str_lit("autiza"), str_lit("autizb"), str_lit("autdza"), str_lit("autdzb"), str_lit("paciasp"), str_lit("pacibsp"), str_lit("autiasp"), str_lit("autibsp"), str_lit("pacia1716"), str_lit("pacib1716"), + str_lit("autia1716"), str_lit("autib1716"), str_lit("pacga"), str_lit("xpaci"), str_lit("xpacd"), str_lit("xpaclri"), str_lit("retaa"), str_lit("retab"), str_lit("braa"), str_lit("brab"), str_lit("braaz"), str_lit("brabz"), str_lit("blraa"), str_lit("blrab"), str_lit("blraaz"), str_lit("blrabz"), + str_lit("eretaa"), str_lit("eretab"), str_lit("bti"), str_lit("irg"), str_lit("addg"), str_lit("subg"), str_lit("gmi"), str_lit("subp"), str_lit("subps"), str_lit("ldg"), str_lit("stg"), str_lit("st2g"), str_lit("stzg"), str_lit("stz2g"), str_lit("stgp"), str_lit("ldgm"), + str_lit("stgm"), str_lit("stzgm"), str_lit("crc32b"), str_lit("crc32h"), str_lit("crc32w"), str_lit("crc32x"), str_lit("crc32cb"), str_lit("crc32ch"), str_lit("crc32cw"), str_lit("crc32cx"), str_lit("aese"), str_lit("aesd"), str_lit("aesmc"), str_lit("aesimc"), str_lit("sha1h"), str_lit("sha1c"), + str_lit("sha1p"), str_lit("sha1m"), str_lit("sha1su0"), str_lit("sha1su1"), str_lit("sha256h"), str_lit("sha256h2"), str_lit("sha256su0"), str_lit("sha256su1"), str_lit("sha512h"), str_lit("sha512h2"), str_lit("sha512su0"), str_lit("sha512su1"), str_lit("eor3"), str_lit("bcax"), str_lit("rax1"), str_lit("xar"), + str_lit("sm3partw1"), str_lit("sm3partw2"), str_lit("sm3ss1"), str_lit("sm3tt1a"), str_lit("sm3tt1b"), str_lit("sm3tt2a"), str_lit("sm3tt2b"), str_lit("sm4e"), str_lit("sm4ekey"), str_lit("pmull"), str_lit("pmull2"), str_lit("bfcvt"), str_lit("bfdot"), str_lit("bfmmla"), str_lit("bfmlalb"), str_lit("bfmlalt"), + str_lit("bfcvtn"), str_lit("bfcvtn2"), str_lit("mul"), str_lit("mla"), str_lit("mls"), str_lit("neg"), str_lit("abs"), str_lit("shadd"), str_lit("uhadd"), str_lit("shsub"), str_lit("uhsub"), str_lit("srhadd"), str_lit("urhadd"), str_lit("sqadd"), str_lit("uqadd"), str_lit("sqsub"), + str_lit("uqsub"), str_lit("smax"), str_lit("umax"), str_lit("smin"), str_lit("umin"), str_lit("sabd"), str_lit("uabd"), str_lit("saba"), str_lit("uaba"), str_lit("addp"), str_lit("addv"), str_lit("saddlp"), str_lit("uaddlp"), str_lit("sadalp"), str_lit("uadalp"), str_lit("saddlv"), + str_lit("uaddlv"), str_lit("smaxv"), str_lit("umaxv"), str_lit("sminv"), str_lit("uminv"), str_lit("smaxp"), str_lit("umaxp"), str_lit("sminp"), str_lit("uminp"), str_lit("saddl"), str_lit("saddl2"), str_lit("uaddl"), str_lit("uaddl2"), str_lit("ssubl"), str_lit("ssubl2"), str_lit("usubl"), + str_lit("usubl2"), str_lit("saddw"), str_lit("saddw2"), str_lit("uaddw"), str_lit("uaddw2"), str_lit("ssubw"), str_lit("ssubw2"), str_lit("usubw"), str_lit("usubw2"), str_lit("raddhn"), str_lit("raddhn2"), str_lit("rsubhn"), str_lit("rsubhn2"), str_lit("addhn"), str_lit("addhn2"), str_lit("subhn"), + str_lit("subhn2"), str_lit("xtn"), str_lit("xtn2"), str_lit("sqxtn"), str_lit("sqxtn2"), str_lit("uqxtn"), str_lit("uqxtn2"), str_lit("sqxtun"), str_lit("sqxtun2"), str_lit("smull"), str_lit("smull2"), str_lit("umull"), str_lit("umull2"), str_lit("smlal"), str_lit("smlal2"), str_lit("umlal"), + str_lit("umlal2"), str_lit("smlsl"), str_lit("smlsl2"), str_lit("umlsl"), str_lit("umlsl2"), str_lit("sqdmull"), str_lit("sqdmull2"), str_lit("sqdmlal"), str_lit("sqdmlal2"), str_lit("sqdmlsl"), str_lit("sqdmlsl2"), str_lit("sqdmulh"), str_lit("sqrdmulh"), str_lit("sdot"), str_lit("udot"), str_lit("usdot"), + str_lit("fmla"), str_lit("fmls"), str_lit("fmulx"), str_lit("fmaxp"), str_lit("fminp"), str_lit("fmaxnmp"), str_lit("fminnmp"), str_lit("fmaxv"), str_lit("fminv"), str_lit("fmaxnmv"), str_lit("fminnmv"), str_lit("frecpe"), str_lit("frsqrte"), str_lit("frecps"), str_lit("frsqrts"), str_lit("frecpx"), + str_lit("faddp"), str_lit("fcvtl"), str_lit("fcvtl2"), str_lit("fcvtn"), str_lit("fcvtn2"), str_lit("fcvtxn"), str_lit("fcvtxn2"), str_lit("fcmeq"), str_lit("fcmge"), str_lit("fcmgt"), str_lit("fcmle"), str_lit("fcmlt"), str_lit("facge"), str_lit("facgt"), str_lit("cmeq"), str_lit("cmge"), + str_lit("cmgt"), str_lit("cmhi"), str_lit("cmhs"), str_lit("cmle"), str_lit("cmlt"), str_lit("cmtst"), str_lit("mvn"), str_lit("bit"), str_lit("bif"), str_lit("bsl"), str_lit("shl"), str_lit("sqshl"), str_lit("sqshlu"), str_lit("srshl"), str_lit("urshl"), str_lit("sshr"), + str_lit("ushr"), str_lit("ssra"), str_lit("usra"), str_lit("srshr"), str_lit("urshr"), str_lit("srsra"), str_lit("ursra"), str_lit("sshl"), str_lit("ushl"), str_lit("sli"), str_lit("sri"), str_lit("sshll"), str_lit("sshll2"), str_lit("ushll"), str_lit("ushll2"), str_lit("sxtl"), + str_lit("sxtl2"), str_lit("uxtl"), str_lit("uxtl2"), str_lit("shrn"), str_lit("shrn2"), str_lit("rshrn"), str_lit("rshrn2"), str_lit("sqshrn"), str_lit("sqshrn2"), str_lit("uqshrn"), str_lit("uqshrn2"), str_lit("sqrshrn"), str_lit("sqrshrn2"), str_lit("uqrshrn"), str_lit("uqrshrn2"), str_lit("sqshrun"), + str_lit("sqshrun2"), str_lit("sqrshrun"), str_lit("sqrshrun2"), str_lit("dup"), str_lit("ins"), str_lit("mov"), str_lit("ext"), str_lit("tbl"), str_lit("tbx"), str_lit("zip1"), str_lit("zip2"), str_lit("uzp1"), str_lit("uzp2"), str_lit("trn1"), str_lit("trn2"), str_lit("not"), + str_lit("rev64"), str_lit("cnt"), str_lit("urecpe"), str_lit("ursqrte"), str_lit("movi"), str_lit("mvni"), str_lit("ld1"), str_lit("ld2"), str_lit("ld3"), str_lit("ld4"), str_lit("st1"), str_lit("st2"), str_lit("st3"), str_lit("st4"), str_lit("ld1r"), str_lit("ld2r"), + str_lit("ld3r"), str_lit("ld4r"), str_lit("subr"), str_lit("asrr"), str_lit("lslr"), str_lit("lsrr"), str_lit("ftsmul"), str_lit("fsubr"), str_lit("fdivr"), str_lit("fnmla"), str_lit("fnmls"), str_lit("nand"), str_lit("nor"), str_lit("sel"), str_lit("orrs"), str_lit("eors"), + str_lit("nands"), str_lit("nors"), str_lit("orns"), str_lit("movs"), str_lit("ptrue"), str_lit("ptrues"), str_lit("pfalse"), str_lit("pfirst"), str_lit("pnext"), str_lit("brka"), str_lit("brkb"), str_lit("brkas"), str_lit("brkbs"), str_lit("brkpa"), str_lit("brkpb"), str_lit("brkn"), + str_lit("rdffr"), str_lit("wrffr"), str_lit("setffr"), str_lit("cmpeq"), str_lit("cmpne"), str_lit("cmpge"), str_lit("cmpgt"), str_lit("cmple"), str_lit("cmplt"), str_lit("cmphi"), str_lit("cmphs"), str_lit("cmplo"), str_lit("cmpls"), str_lit("fcmne"), str_lit("fcmuo"), str_lit("insr"), + str_lit("cpy"), str_lit("compact"), str_lit("ld1b"), str_lit("ld1h"), str_lit("ld1w"), str_lit("ld1d"), str_lit("ld1sb"), str_lit("ld1sh"), str_lit("ld1sw"), str_lit("st1b"), str_lit("st1h"), str_lit("st1w"), str_lit("st1d"), str_lit("ldff1b"), str_lit("ldff1h"), str_lit("ldff1w"), + str_lit("ldff1d"), str_lit("whilege"), str_lit("whilegt"), str_lit("whilele"), str_lit("whilelt"), str_lit("whilehi"), str_lit("whilehs"), str_lit("whilelo"), str_lit("whilels"), str_lit("sqrdmlah"), str_lit("sqrdmlsh"), str_lit("adclb"), str_lit("adclt"), str_lit("sbclb"), str_lit("sbclt"), str_lit("tbl2"), + str_lit("match"), str_lit("nmatch"), str_lit("histcnt"), str_lit("histseg"), str_lit("smstart"), str_lit("smstop"), str_lit("rdsvl"), str_lit("addha"), str_lit("addva"), str_lit("zero"), str_lit("fmopa"), str_lit("fmops"), str_lit("bfmopa"), str_lit("bfmops"), str_lit("smopa"), str_lit("smops"), + str_lit("umopa"), str_lit("umops"), str_lit("usmopa"), str_lit("sumopa"), str_lit("ld1q"), str_lit("st1q"), str_lit("mova"), str_lit("fcmla"), str_lit("fcadd"), str_lit("prfb"), str_lit("prfh"), str_lit("prfw"), str_lit("prfd"), str_lit("ldnt1b"), str_lit("ldnt1h"), str_lit("ldnt1w"), + str_lit("ldnt1d"), str_lit("stnt1b"), str_lit("stnt1h"), str_lit("stnt1w"), str_lit("stnt1d"), str_lit("splice"), str_lit("index"), str_lit("bsl1n"), str_lit("bsl2n"), str_lit("nbsl"), str_lit("pmul"), str_lit("pmullb"), str_lit("pmullt"), str_lit("bfcvtnt"), str_lit("ldraa"), str_lit("ldrab"), + str_lit("tstart"), str_lit("tcommit"), str_lit("tcancel"), str_lit("ttest"), str_lit("wfet"), str_lit("wfit"), str_lit("bc_eq"), str_lit("bc_ne"), str_lit("bc_cs"), str_lit("bc_cc"), str_lit("bc_mi"), str_lit("bc_pl"), str_lit("bc_vs"), str_lit("bc_vc"), str_lit("bc_hi"), str_lit("bc_ls"), + str_lit("bc_ge"), str_lit("bc_lt"), str_lit("bc_gt"), str_lit("bc_le"), str_lit("bc_al"), str_lit("bc_nv"), str_lit("uxtb"), str_lit("uxth"), str_lit("uxtw"), str_lit("sxtb"), str_lit("sxth"), str_lit("sxtw"), str_lit("adc"), str_lit("adcs"), str_lit("sbc"), str_lit("sbcs"), + str_lit("ngc"), str_lit("ngcs"), str_lit("ldapur"), str_lit("stlur"), str_lit("ldapurb"), str_lit("stlurb"), str_lit("ldapurh"), str_lit("stlurh"), str_lit("ldapursb"), str_lit("ldapursh"), str_lit("ldapursw"), str_lit("bfadd"), str_lit("bfsub"), str_lit("bfmul"), str_lit("bfmla"), str_lit("bfmls"), + str_lit("sb"), str_lit("csdb"), str_lit("dgh"), str_lit("psb_csync"), str_lit("tsb_csync"), str_lit("bti_j"), str_lit("bti_c"), str_lit("bti_jc"), str_lit("bfclamp"), str_lit("bfmaxnm"), str_lit("bfminnm"), str_lit("luti2"), str_lit("luti4"), str_lit("zip"), str_lit("uzp"), str_lit("tlbi_rpalos"), + str_lit("tlbi_rpaos"), str_lit("at_s1e1a"), str_lit("dc_cipapa"), str_lit("dc_cigdpapa"), str_lit("tlbi_paall"), str_lit("tlbi_paallos"), str_lit("amx_ldx"), str_lit("amx_ldy"), str_lit("amx_stx"), str_lit("amx_sty"), str_lit("amx_ldz"), str_lit("amx_stz"), str_lit("amx_ldzi"), str_lit("amx_stzi"), str_lit("amx_extrx"), str_lit("amx_extry"), + str_lit("amx_fma64"), str_lit("amx_fms64"), str_lit("amx_fma32"), str_lit("amx_fms32"), str_lit("amx_mac16"), str_lit("amx_fma16"), str_lit("amx_fms16"), str_lit("amx_set"), str_lit("amx_clr"), str_lit("amx_vecint"), str_lit("amx_vecfp"), str_lit("amx_matint"), str_lit("amx_matfp"), str_lit("amx_genlut"), str_lit("cpyp"), str_lit("cpym"), + str_lit("cpye"), str_lit("cpyfp"), str_lit("cpyfm"), str_lit("cpyfe"), str_lit("setp"), str_lit("setm"), str_lit("sete"), str_lit("dc_ivac"), str_lit("dc_isw"), str_lit("dc_csw"), str_lit("dc_cisw"), str_lit("dc_zva"), str_lit("dc_cvac"), str_lit("dc_cvau"), str_lit("dc_civac"), str_lit("ic_ialluis"), + str_lit("ic_iallu"), str_lit("ic_ivau"), str_lit("at_s1e1r"), str_lit("at_s1e1w"), str_lit("at_s1e0r"), str_lit("at_s1e0w"), str_lit("at_s1e2r"), str_lit("at_s1e2w"), str_lit("at_s1e3r"), str_lit("at_s1e3w"), str_lit("at_s12e1r"), str_lit("at_s12e1w"), str_lit("at_s12e0r"), str_lit("at_s12e0w"), str_lit("tlbi_vmalle1"), str_lit("tlbi_vmalle1is"), + str_lit("tlbi_vae1"), str_lit("tlbi_vae1is"), str_lit("tlbi_aside1"), str_lit("tlbi_aside1is"), str_lit("tlbi_vaae1"), str_lit("tlbi_vaae1is"), str_lit("tlbi_vale1"), str_lit("tlbi_vale1is"), str_lit("tlbi_vaale1"), str_lit("tlbi_vaale1is"), str_lit("tlbi_alle1"), str_lit("tlbi_alle1is"), str_lit("tlbi_alle2"), str_lit("tlbi_alle2is"), str_lit("tlbi_alle3"), str_lit("tlbi_alle3is"), + str_lit("prfm"), str_lit("prfum"), str_lit("negs"), str_lit("cmp"), str_lit("cmn"), }; u16 const Asm_arm64::register_codes[Asm_arm64::REG_COUNT] { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, @@ -1101,834 +1104,844 @@ String const Asm_arm64::register_strings[Asm_arm64::REG_COUNT] { str_lit("v29"), str_lit("v30"), str_lit("v31"), }; String const Asm_arm64::pseudo_mnemonic_strings[Asm_arm64::PSEUDO_MNEMONIC_COUNT] {}; -Asm_arm64::EncodeRun const Asm_arm64::raw_encode_runs[816] = { +Asm_arm64::EncodeRun const Asm_arm64::raw_encode_runs[821] = { { 0, 0}, { 0, 21}, { 21, 6}, { 27, 18}, { 45, 6}, { 51, 2}, { 53, 2}, { 55, 2}, { 57, 1}, { 58, 1}, { 59, 7}, { 66, 5}, { 71, 7}, { 78, 7}, { 85, 5}, { 90, 3}, { 93, 4}, { 97, 2}, { 99, 8}, { 107, 8}, { 115, 8}, { 123, 4}, { 127, 4}, { 131, 4}, { 135, 2}, { 137, 2}, { 139, 1}, { 140, 1}, { 141, 1}, { 142, 1}, { 143, 5}, { 148, 5}, - { 153, 12}, { 165, 12}, { 177, 4}, { 181, 7}, { 188, 4}, { 192, 5}, { 197, 2}, { 199, 2}, { 201, 2}, { 203, 2}, { 205, 4}, { 209, 4}, { 213, 2}, { 215, 1}, { 216, 1}, { 217, 1}, - { 218, 1}, { 219, 2}, { 221, 1}, { 222, 1}, { 223, 1}, { 224, 1}, { 225, 1}, { 226, 1}, { 227, 1}, { 228, 1}, { 229, 1}, { 230, 1}, { 231, 1}, { 232, 1}, { 233, 1}, { 234, 1}, - { 235, 1}, { 236, 1}, { 237, 2}, { 239, 2}, { 241, 1}, { 242, 1}, { 243, 18}, { 261, 16}, { 277, 4}, { 281, 4}, { 285, 4}, { 289, 4}, { 293, 4}, { 297, 4}, { 301, 2}, { 303, 9}, - { 312, 9}, { 321, 3}, { 324, 2}, { 326, 2}, { 328, 1}, { 329, 1}, { 330, 1}, { 331, 1}, { 332, 2}, { 334, 2}, { 336, 2}, { 338, 2}, { 340, 1}, { 341, 1}, { 342, 1}, { 343, 1}, - { 344, 1}, { 345, 1}, { 346, 1}, { 347, 1}, { 348, 2}, { 350, 1}, { 351, 1}, { 352, 1}, { 353, 1}, { 354, 1}, { 355, 1}, { 356, 1}, { 357, 1}, { 358, 1}, { 359, 15}, { 374, 11}, - { 385, 11}, { 396, 11}, { 407, 12}, { 419, 12}, { 431, 12}, { 443, 9}, { 452, 3}, { 455, 3}, { 458, 3}, { 461, 3}, { 464, 3}, { 467, 3}, { 470, 3}, { 473, 3}, { 476, 11}, { 487, 11}, - { 498, 11}, { 509, 11}, { 520, 6}, { 526, 10}, { 536, 10}, { 546, 10}, { 556, 10}, { 566, 11}, { 577, 11}, { 588, 11}, { 599, 11}, { 610, 11}, { 621, 11}, { 632, 11}, { 643, 11}, { 654, 11}, - { 665, 11}, { 676, 11}, { 687, 11}, { 698, 11}, { 709, 11}, { 720, 11}, { 731, 4}, { 735, 5}, { 740, 5}, { 745, 1}, { 746, 1}, { 747, 2}, { 749, 1}, { 750, 1}, { 751, 2}, { 753, 1}, - { 754, 2}, { 756, 2}, { 758, 2}, { 760, 2}, { 762, 2}, { 764, 2}, { 766, 1}, { 767, 1}, { 768, 1}, { 769, 1}, { 770, 1}, { 771, 1}, { 772, 1}, { 773, 1}, { 774, 2}, { 776, 1}, - { 777, 1}, { 778, 2}, { 780, 2}, { 782, 2}, { 784, 2}, { 786, 2}, { 788, 2}, { 790, 2}, { 792, 2}, { 794, 2}, { 796, 2}, { 798, 2}, { 800, 2}, { 802, 2}, { 804, 2}, { 806, 2}, - { 808, 2}, { 810, 2}, { 812, 2}, { 814, 2}, { 816, 2}, { 818, 2}, { 820, 2}, { 822, 2}, { 824, 2}, { 826, 2}, { 828, 2}, { 830, 2}, { 832, 2}, { 834, 2}, { 836, 2}, { 838, 2}, - { 840, 2}, { 842, 2}, { 844, 2}, { 846, 2}, { 848, 2}, { 850, 2}, { 852, 2}, { 854, 2}, { 856, 2}, { 858, 1}, { 859, 1}, { 860, 1}, { 861, 1}, { 862, 1}, { 863, 1}, { 864, 1}, - { 865, 1}, { 866, 2}, { 868, 2}, { 870, 2}, { 872, 2}, { 874, 1}, { 875, 1}, { 876, 1}, { 877, 1}, { 878, 1}, { 879, 1}, { 880, 1}, { 881, 1}, { 882, 1}, { 883, 1}, { 884, 1}, - { 885, 1}, { 886, 1}, { 887, 1}, { 888, 1}, { 889, 1}, { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 1}, { 897, 1}, { 898, 1}, { 899, 1}, { 900, 1}, - { 901, 1}, { 902, 1}, { 903, 1}, { 904, 1}, { 905, 1}, { 906, 1}, { 907, 1}, { 908, 1}, { 909, 1}, { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, - { 917, 1}, { 918, 1}, { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, { 930, 1}, { 931, 1}, { 932, 1}, - { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, { 937, 1}, { 938, 2}, { 940, 2}, { 942, 2}, { 944, 2}, { 946, 1}, { 947, 1}, { 948, 1}, { 949, 1}, { 950, 1}, { 951, 1}, { 952, 1}, - { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, { 958, 1}, { 959, 1}, { 960, 2}, { 962, 2}, { 964, 1}, { 965, 5}, { 970, 1}, { 971, 1}, { 972, 1}, { 973, 1}, { 974, 1}, - { 975, 1}, { 976, 1}, { 977, 1}, { 978, 1}, { 979, 2}, { 981, 2}, { 983, 2}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 1}, { 991, 7}, { 998, 6}, {1004, 6}, - {1010, 13}, {1023, 11}, {1034, 6}, {1040, 6}, {1046, 6}, {1052, 6}, {1058, 6}, {1064, 6}, {1070, 11}, {1081, 11}, {1092, 11}, {1103, 11}, {1114, 10}, {1124, 10}, {1134, 10}, {1144, 10}, - {1154, 10}, {1164, 10}, {1174, 6}, {1180, 6}, {1186, 7}, {1193, 5}, {1198, 6}, {1204, 6}, {1210, 6}, {1216, 6}, {1222, 5}, {1227, 5}, {1232, 5}, {1237, 5}, {1242, 5}, {1247, 5}, - {1252, 6}, {1258, 6}, {1264, 6}, {1270, 6}, {1276, 3}, {1279, 3}, {1282, 3}, {1285, 3}, {1288, 3}, {1291, 3}, {1294, 3}, {1297, 3}, {1300, 3}, {1303, 3}, {1306, 3}, {1309, 3}, - {1312, 3}, {1315, 3}, {1318, 3}, {1321, 3}, {1324, 3}, {1327, 3}, {1330, 3}, {1333, 3}, {1336, 3}, {1339, 3}, {1342, 3}, {1345, 3}, {1348, 3}, {1351, 3}, {1354, 3}, {1357, 3}, - {1360, 3}, {1363, 3}, {1366, 3}, {1369, 3}, {1372, 3}, {1375, 3}, {1378, 3}, {1381, 3}, {1384, 3}, {1387, 3}, {1390, 3}, {1393, 3}, {1396, 3}, {1399, 3}, {1402, 3}, {1405, 3}, - {1408, 2}, {1410, 2}, {1412, 2}, {1414, 2}, {1416, 2}, {1418, 2}, {1420, 4}, {1424, 4}, {1428, 2}, {1430, 2}, {1432, 2}, {1434, 8}, {1442, 8}, {1450, 5}, {1455, 5}, {1460, 5}, - {1465, 5}, {1470, 5}, {1475, 3}, {1478, 3}, {1481, 3}, {1484, 3}, {1487, 5}, {1492, 5}, {1497, 8}, {1505, 8}, {1513, 6}, {1519, 5}, {1524, 2}, {1526, 2}, {1528, 2}, {1530, 2}, - {1532, 1}, {1533, 1}, {1534, 8}, {1542, 8}, {1550, 8}, {1558, 8}, {1566, 8}, {1574, 5}, {1579, 5}, {1584, 4}, {1588, 7}, {1595, 2}, {1597, 2}, {1599, 7}, {1606, 7}, {1613, 7}, - {1620, 7}, {1627, 4}, {1631, 1}, {1632, 1}, {1633, 2}, {1635, 7}, {1642, 7}, {1649, 7}, {1656, 7}, {1663, 7}, {1670, 7}, {1677, 7}, {1684, 7}, {1691, 7}, {1698, 7}, {1705, 7}, - {1712, 7}, {1719, 7}, {1726, 7}, {1733, 7}, {1740, 7}, {1747, 7}, {1754, 3}, {1757, 3}, {1760, 3}, {1763, 3}, {1766, 3}, {1769, 3}, {1772, 3}, {1775, 3}, {1778, 3}, {1781, 3}, - {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, {1817, 3}, {1820, 3}, {1823, 3}, {1826, 18}, {1844, 8}, - {1852, 12}, {1864, 4}, {1868, 6}, {1874, 3}, {1877, 12}, {1889, 12}, {1901, 12}, {1913, 12}, {1925, 12}, {1937, 12}, {1949, 3}, {1952, 6}, {1958, 6}, {1964, 2}, {1966, 2}, {1968, 7}, - {1975, 4}, {1979, 8}, {1987, 5}, {1992, 5}, {1997, 5}, {2002, 8}, {2010, 5}, {2015, 5}, {2020, 5}, {2025, 1}, {2026, 1}, {2027, 1}, {2028, 1}, {2029, 4}, {2033, 4}, {2037, 4}, - {2041, 4}, {2045, 3}, {2048, 3}, {2051, 3}, {2054, 3}, {2057, 3}, {2060, 1}, {2061, 1}, {2062, 1}, {2063, 1}, {2064, 1}, {2065, 1}, {2066, 1}, {2067, 1}, {2068, 1}, {2069, 1}, - {2070, 1}, {2071, 1}, {2072, 1}, {2073, 1}, {2074, 1}, {2075, 1}, {2076, 1}, {2077, 1}, {2078, 1}, {2079, 1}, {2080, 1}, {2081, 1}, {2082, 1}, {2083, 1}, {2084, 4}, {2088, 4}, - {2092, 4}, {2096, 4}, {2100, 4}, {2104, 4}, {2108, 4}, {2112, 4}, {2116, 4}, {2120, 4}, {2124, 3}, {2127, 3}, {2130, 4}, {2134, 4}, {2138, 2}, {2140, 6}, {2146, 6}, {2152, 6}, - {2158, 5}, {2163, 3}, {2166, 3}, {2169, 2}, {2171, 6}, {2177, 6}, {2183, 6}, {2189, 5}, {2194, 1}, {2195, 1}, {2196, 1}, {2197, 1}, {2198, 1}, {2199, 1}, {2200, 1}, {2201, 1}, - {2202, 1}, {2203, 1}, {2204, 1}, {2205, 1}, {2206, 4}, {2210, 4}, {2214, 2}, {2216, 2}, {2218, 2}, {2220, 2}, {2222, 1}, {2223, 2}, {2225, 2}, {2227, 2}, {2229, 1}, {2230, 1}, - {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, {2235, 1}, {2236, 1}, {2237, 1}, {2238, 1}, {2239, 1}, {2240, 2}, {2242, 2}, {2244, 2}, {2246, 2}, {2248, 1}, {2249, 1}, {2250, 1}, - {2251, 1}, {2252, 2}, {2254, 4}, {2258, 4}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 1}, {2268, 1}, {2269, 1}, {2270, 1}, {2271, 1}, {2272, 1}, {2273, 1}, - {2274, 1}, {2275, 4}, {2279, 1}, {2280, 1}, {2281, 1}, {2282, 1}, {2283, 1}, {2284, 1}, {2285, 1}, {2286, 2}, {2288, 2}, {2290, 1}, {2291, 1}, {2292, 1}, {2293, 1}, {2294, 1}, - {2295, 1}, {2296, 1}, {2297, 1}, {2298, 1}, {2299, 1}, {2300, 1}, {2301, 1}, {2302, 1}, {2303, 1}, {2304, 1}, {2305, 1}, {2306, 1}, {2307, 1}, {2308, 1}, {2309, 1}, {2310, 1}, - {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 1}, {2317, 1}, {2318, 2}, {2320, 2}, {2322, 2}, {2324, 2}, {2326, 2}, {2328, 2}, {2330, 2}, {2332, 2}, {2334, 1}, - {2335, 1}, {2336, 1}, {2337, 1}, {2338, 2}, {2340, 2}, {2342, 1}, {2343, 2}, {2345, 2}, {2347, 2}, {2349, 1}, {2350, 1}, {2351, 1}, {2352, 1}, {2353, 1}, {2354, 1}, {2355, 1}, - {2356, 1}, {2357, 1}, {2358, 1}, {2359, 1}, {2360, 1}, {2361, 1}, {2362, 1}, {2363, 1}, {2364, 2}, {2366, 2}, {2368, 1}, {2369, 1}, {2370, 1}, {2371, 1}, {2372, 1}, {2373, 1}, - {2374, 1}, {2375, 1}, {2376, 1}, {2377, 1}, {2378, 1}, {2379, 1}, {2380, 1}, {2381, 1}, {2382, 1}, {2383, 1}, {2384, 1}, {2385, 1}, {2386, 1}, {2387, 1}, {2388, 1}, {2389, 1}, - {2390, 1}, {2391, 1}, {2392, 1}, {2393, 1}, {2394, 1}, {2395, 1}, {2396, 1}, {2397, 1}, {2398, 1}, {2399, 1}, {2400, 1}, {2401, 1}, {2402, 1}, {2403, 1}, {2404, 1}, {2405, 1}, - {2406, 1}, {2407, 1}, {2408, 1}, {2409, 1}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, {2415, 1}, {2416, 1}, {2417, 1}, {2418, 1}, {2419, 1}, {2420, 1}, {2421, 1}, - {2422, 1}, {2423, 1}, {2424, 1}, {2425, 1}, {2426, 1}, {2427, 1}, {2428, 1}, {2429, 1}, {2430, 1}, {2431, 1}, {2432, 1}, {2433, 1}, {2434, 1}, {2435, 1}, {2436, 1}, {2437, 1}, - {2438, 1}, {2439, 1}, {2440, 1}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 1}, {2445, 1}, {2446, 1}, {2447, 1}, {2448, 1}, {2449, 2}, {2451, 1}, {2452, 2}, {2454, 6}, {2460, 6}, - + { 153, 12}, { 165, 12}, { 177, 4}, { 181, 7}, { 188, 4}, { 192, 5}, { 197, 2}, { 199, 2}, { 201, 2}, { 203, 2}, { 205, 4}, { 209, 4}, { 213, 6}, { 219, 6}, { 225, 6}, { 231, 6}, + { 237, 6}, { 243, 2}, { 245, 1}, { 246, 1}, { 247, 1}, { 248, 1}, { 249, 2}, { 251, 1}, { 252, 1}, { 253, 1}, { 254, 1}, { 255, 1}, { 256, 1}, { 257, 1}, { 258, 1}, { 259, 1}, + { 260, 1}, { 261, 1}, { 262, 1}, { 263, 1}, { 264, 1}, { 265, 1}, { 266, 1}, { 267, 2}, { 269, 2}, { 271, 1}, { 272, 1}, { 273, 18}, { 291, 16}, { 307, 4}, { 311, 4}, { 315, 4}, + { 319, 4}, { 323, 4}, { 327, 4}, { 331, 2}, { 333, 9}, { 342, 9}, { 351, 3}, { 354, 2}, { 356, 2}, { 358, 1}, { 359, 1}, { 360, 1}, { 361, 1}, { 362, 2}, { 364, 2}, { 366, 2}, + { 368, 2}, { 370, 1}, { 371, 1}, { 372, 1}, { 373, 1}, { 374, 1}, { 375, 1}, { 376, 1}, { 377, 1}, { 378, 2}, { 380, 1}, { 381, 1}, { 382, 1}, { 383, 1}, { 384, 1}, { 385, 1}, + { 386, 1}, { 387, 1}, { 388, 1}, { 389, 15}, { 404, 11}, { 415, 11}, { 426, 11}, { 437, 12}, { 449, 12}, { 461, 12}, { 473, 9}, { 482, 3}, { 485, 3}, { 488, 3}, { 491, 3}, { 494, 3}, + { 497, 3}, { 500, 3}, { 503, 3}, { 506, 11}, { 517, 11}, { 528, 11}, { 539, 11}, { 550, 6}, { 556, 10}, { 566, 10}, { 576, 10}, { 586, 10}, { 596, 11}, { 607, 11}, { 618, 11}, { 629, 11}, + { 640, 11}, { 651, 11}, { 662, 11}, { 673, 11}, { 684, 11}, { 695, 11}, { 706, 11}, { 717, 11}, { 728, 11}, { 739, 11}, { 750, 11}, { 761, 4}, { 765, 5}, { 770, 5}, { 775, 1}, { 776, 1}, + { 777, 2}, { 779, 1}, { 780, 1}, { 781, 2}, { 783, 1}, { 784, 2}, { 786, 2}, { 788, 2}, { 790, 2}, { 792, 2}, { 794, 2}, { 796, 1}, { 797, 1}, { 798, 1}, { 799, 1}, { 800, 1}, + { 801, 1}, { 802, 1}, { 803, 1}, { 804, 2}, { 806, 1}, { 807, 1}, { 808, 2}, { 810, 2}, { 812, 2}, { 814, 2}, { 816, 2}, { 818, 2}, { 820, 2}, { 822, 2}, { 824, 2}, { 826, 2}, + { 828, 2}, { 830, 2}, { 832, 2}, { 834, 2}, { 836, 2}, { 838, 2}, { 840, 2}, { 842, 2}, { 844, 2}, { 846, 2}, { 848, 2}, { 850, 2}, { 852, 2}, { 854, 2}, { 856, 2}, { 858, 2}, + { 860, 2}, { 862, 2}, { 864, 2}, { 866, 2}, { 868, 2}, { 870, 2}, { 872, 2}, { 874, 2}, { 876, 2}, { 878, 2}, { 880, 2}, { 882, 2}, { 884, 2}, { 886, 2}, { 888, 1}, { 889, 1}, + { 890, 1}, { 891, 1}, { 892, 1}, { 893, 1}, { 894, 1}, { 895, 1}, { 896, 2}, { 898, 2}, { 900, 2}, { 902, 2}, { 904, 1}, { 905, 1}, { 906, 1}, { 907, 1}, { 908, 1}, { 909, 1}, + { 910, 1}, { 911, 1}, { 912, 1}, { 913, 1}, { 914, 1}, { 915, 1}, { 916, 1}, { 917, 1}, { 918, 1}, { 919, 1}, { 920, 1}, { 921, 1}, { 922, 1}, { 923, 1}, { 924, 1}, { 925, 1}, + { 926, 1}, { 927, 1}, { 928, 1}, { 929, 1}, { 930, 1}, { 931, 1}, { 932, 1}, { 933, 1}, { 934, 1}, { 935, 1}, { 936, 1}, { 937, 1}, { 938, 1}, { 939, 1}, { 940, 1}, { 941, 1}, + { 942, 1}, { 943, 1}, { 944, 1}, { 945, 1}, { 946, 1}, { 947, 1}, { 948, 1}, { 949, 1}, { 950, 1}, { 951, 1}, { 952, 1}, { 953, 1}, { 954, 1}, { 955, 1}, { 956, 1}, { 957, 1}, + { 958, 1}, { 959, 1}, { 960, 1}, { 961, 1}, { 962, 1}, { 963, 1}, { 964, 1}, { 965, 1}, { 966, 1}, { 967, 1}, { 968, 2}, { 970, 2}, { 972, 2}, { 974, 2}, { 976, 1}, { 977, 1}, + { 978, 1}, { 979, 1}, { 980, 1}, { 981, 1}, { 982, 1}, { 983, 1}, { 984, 1}, { 985, 1}, { 986, 1}, { 987, 1}, { 988, 1}, { 989, 1}, { 990, 2}, { 992, 2}, { 994, 1}, { 995, 5}, + {1000, 1}, {1001, 1}, {1002, 1}, {1003, 1}, {1004, 1}, {1005, 1}, {1006, 1}, {1007, 1}, {1008, 1}, {1009, 2}, {1011, 2}, {1013, 2}, {1015, 1}, {1016, 1}, {1017, 1}, {1018, 1}, + {1019, 1}, {1020, 1}, {1021, 7}, {1028, 6}, {1034, 6}, {1040, 13}, {1053, 11}, {1064, 6}, {1070, 6}, {1076, 6}, {1082, 6}, {1088, 6}, {1094, 6}, {1100, 11}, {1111, 11}, {1122, 11}, + {1133, 11}, {1144, 10}, {1154, 10}, {1164, 10}, {1174, 10}, {1184, 10}, {1194, 10}, {1204, 6}, {1210, 6}, {1216, 7}, {1223, 5}, {1228, 6}, {1234, 6}, {1240, 6}, {1246, 6}, {1252, 5}, + {1257, 5}, {1262, 5}, {1267, 5}, {1272, 5}, {1277, 5}, {1282, 6}, {1288, 6}, {1294, 6}, {1300, 6}, {1306, 3}, {1309, 3}, {1312, 3}, {1315, 3}, {1318, 3}, {1321, 3}, {1324, 3}, + {1327, 3}, {1330, 3}, {1333, 3}, {1336, 3}, {1339, 3}, {1342, 3}, {1345, 3}, {1348, 3}, {1351, 3}, {1354, 3}, {1357, 3}, {1360, 3}, {1363, 3}, {1366, 3}, {1369, 3}, {1372, 3}, + {1375, 3}, {1378, 3}, {1381, 3}, {1384, 3}, {1387, 3}, {1390, 3}, {1393, 3}, {1396, 3}, {1399, 3}, {1402, 3}, {1405, 3}, {1408, 3}, {1411, 3}, {1414, 3}, {1417, 3}, {1420, 3}, + {1423, 3}, {1426, 3}, {1429, 3}, {1432, 3}, {1435, 3}, {1438, 2}, {1440, 2}, {1442, 2}, {1444, 2}, {1446, 2}, {1448, 2}, {1450, 4}, {1454, 4}, {1458, 2}, {1460, 2}, {1462, 2}, + {1464, 8}, {1472, 8}, {1480, 5}, {1485, 5}, {1490, 5}, {1495, 5}, {1500, 5}, {1505, 3}, {1508, 3}, {1511, 3}, {1514, 3}, {1517, 5}, {1522, 5}, {1527, 8}, {1535, 8}, {1543, 6}, + {1549, 5}, {1554, 2}, {1556, 2}, {1558, 2}, {1560, 2}, {1562, 1}, {1563, 1}, {1564, 8}, {1572, 8}, {1580, 8}, {1588, 8}, {1596, 8}, {1604, 5}, {1609, 5}, {1614, 4}, {1618, 7}, + {1625, 2}, {1627, 2}, {1629, 7}, {1636, 7}, {1643, 7}, {1650, 7}, {1657, 4}, {1661, 1}, {1662, 1}, {1663, 2}, {1665, 7}, {1672, 7}, {1679, 7}, {1686, 7}, {1693, 7}, {1700, 7}, + {1707, 7}, {1714, 7}, {1721, 7}, {1728, 7}, {1735, 7}, {1742, 7}, {1749, 7}, {1756, 7}, {1763, 7}, {1770, 7}, {1777, 7}, {1784, 3}, {1787, 3}, {1790, 3}, {1793, 3}, {1796, 3}, + {1799, 3}, {1802, 3}, {1805, 3}, {1808, 3}, {1811, 3}, {1814, 3}, {1817, 3}, {1820, 3}, {1823, 3}, {1826, 3}, {1829, 3}, {1832, 3}, {1835, 3}, {1838, 3}, {1841, 3}, {1844, 3}, + {1847, 3}, {1850, 3}, {1853, 3}, {1856, 18}, {1874, 8}, {1882, 12}, {1894, 4}, {1898, 6}, {1904, 3}, {1907, 12}, {1919, 12}, {1931, 12}, {1943, 12}, {1955, 12}, {1967, 12}, {1979, 3}, + {1982, 6}, {1988, 6}, {1994, 2}, {1996, 2}, {1998, 7}, {2005, 4}, {2009, 8}, {2017, 5}, {2022, 5}, {2027, 5}, {2032, 8}, {2040, 5}, {2045, 5}, {2050, 5}, {2055, 1}, {2056, 1}, + {2057, 1}, {2058, 1}, {2059, 4}, {2063, 4}, {2067, 4}, {2071, 4}, {2075, 3}, {2078, 3}, {2081, 3}, {2084, 3}, {2087, 3}, {2090, 1}, {2091, 1}, {2092, 1}, {2093, 1}, {2094, 1}, + {2095, 1}, {2096, 1}, {2097, 1}, {2098, 1}, {2099, 1}, {2100, 1}, {2101, 1}, {2102, 1}, {2103, 1}, {2104, 1}, {2105, 1}, {2106, 1}, {2107, 1}, {2108, 1}, {2109, 1}, {2110, 1}, + {2111, 1}, {2112, 1}, {2113, 1}, {2114, 4}, {2118, 4}, {2122, 4}, {2126, 4}, {2130, 4}, {2134, 4}, {2138, 4}, {2142, 4}, {2146, 4}, {2150, 4}, {2154, 3}, {2157, 3}, {2160, 4}, + {2164, 4}, {2168, 2}, {2170, 6}, {2176, 6}, {2182, 6}, {2188, 5}, {2193, 3}, {2196, 3}, {2199, 2}, {2201, 6}, {2207, 6}, {2213, 6}, {2219, 5}, {2224, 1}, {2225, 1}, {2226, 1}, + {2227, 1}, {2228, 1}, {2229, 1}, {2230, 1}, {2231, 1}, {2232, 1}, {2233, 1}, {2234, 1}, {2235, 1}, {2236, 4}, {2240, 4}, {2244, 2}, {2246, 2}, {2248, 2}, {2250, 2}, {2252, 1}, + {2253, 2}, {2255, 2}, {2257, 2}, {2259, 1}, {2260, 1}, {2261, 1}, {2262, 1}, {2263, 1}, {2264, 1}, {2265, 1}, {2266, 1}, {2267, 1}, {2268, 1}, {2269, 1}, {2270, 2}, {2272, 2}, + {2274, 2}, {2276, 2}, {2278, 1}, {2279, 1}, {2280, 1}, {2281, 1}, {2282, 2}, {2284, 4}, {2288, 4}, {2292, 1}, {2293, 1}, {2294, 1}, {2295, 1}, {2296, 1}, {2297, 1}, {2298, 1}, + {2299, 1}, {2300, 1}, {2301, 1}, {2302, 1}, {2303, 1}, {2304, 1}, {2305, 4}, {2309, 1}, {2310, 1}, {2311, 1}, {2312, 1}, {2313, 1}, {2314, 1}, {2315, 1}, {2316, 2}, {2318, 2}, + {2320, 1}, {2321, 1}, {2322, 1}, {2323, 1}, {2324, 1}, {2325, 1}, {2326, 1}, {2327, 1}, {2328, 1}, {2329, 1}, {2330, 1}, {2331, 1}, {2332, 1}, {2333, 1}, {2334, 1}, {2335, 1}, + {2336, 1}, {2337, 1}, {2338, 1}, {2339, 1}, {2340, 1}, {2341, 1}, {2342, 1}, {2343, 1}, {2344, 1}, {2345, 1}, {2346, 1}, {2347, 1}, {2348, 2}, {2350, 2}, {2352, 2}, {2354, 2}, + {2356, 2}, {2358, 2}, {2360, 2}, {2362, 2}, {2364, 1}, {2365, 1}, {2366, 1}, {2367, 1}, {2368, 2}, {2370, 2}, {2372, 1}, {2373, 2}, {2375, 2}, {2377, 2}, {2379, 1}, {2380, 1}, + {2381, 1}, {2382, 1}, {2383, 1}, {2384, 1}, {2385, 1}, {2386, 1}, {2387, 1}, {2388, 1}, {2389, 1}, {2390, 1}, {2391, 1}, {2392, 1}, {2393, 1}, {2394, 2}, {2396, 2}, {2398, 1}, + {2399, 1}, {2400, 1}, {2401, 1}, {2402, 1}, {2403, 1}, {2404, 1}, {2405, 1}, {2406, 1}, {2407, 1}, {2408, 1}, {2409, 1}, {2410, 1}, {2411, 1}, {2412, 1}, {2413, 1}, {2414, 1}, + {2415, 1}, {2416, 1}, {2417, 1}, {2418, 1}, {2419, 1}, {2420, 1}, {2421, 1}, {2422, 1}, {2423, 1}, {2424, 1}, {2425, 1}, {2426, 1}, {2427, 1}, {2428, 1}, {2429, 1}, {2430, 1}, + {2431, 1}, {2432, 1}, {2433, 1}, {2434, 1}, {2435, 1}, {2436, 1}, {2437, 1}, {2438, 1}, {2439, 1}, {2440, 1}, {2441, 1}, {2442, 1}, {2443, 1}, {2444, 1}, {2445, 1}, {2446, 1}, + {2447, 1}, {2448, 1}, {2449, 1}, {2450, 1}, {2451, 1}, {2452, 1}, {2453, 1}, {2454, 1}, {2455, 1}, {2456, 1}, {2457, 1}, {2458, 1}, {2459, 1}, {2460, 1}, {2461, 1}, {2462, 1}, + {2463, 1}, {2464, 1}, {2465, 1}, {2466, 1}, {2467, 1}, {2468, 1}, {2469, 1}, {2470, 1}, {2471, 1}, {2472, 1}, {2473, 1}, {2474, 1}, {2475, 1}, {2476, 1}, {2477, 1}, {2478, 1}, + {2479, 2}, {2481, 1}, {2482, 2}, {2484, 6}, {2490, 6}, }; -u8 const Asm_arm64::raw_encode_forms[49320] = { - 0x01, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x80, 0xff, 0x00, 0x70, 0x01, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x60, 0x01, 0x00, 0x02, 0x02, - 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x70, 0x01, 0x00, 0x03, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x0b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x8b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x01, 0x00, 0x10, 0x10, 0x10, 0x00, 0x28, 0x29, - 0x2a, 0x00, 0x00, 0x84, 0x20, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x12, 0x12, 0x12, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x60, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x14, 0x14, 0x14, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xa0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x16, 0x16, 0x16, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, - 0xe0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x0f, 0x0f, 0x0f, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x20, 0x0e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x11, 0x11, 0x11, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x60, 0x0e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x13, 0x13, 0x13, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xa0, 0x0e, 0x00, 0xfc, - 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x1d, 0x1d, 0x1d, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x01, 0x00, 0x1e, 0x1e, 0x1e, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x00, 0x60, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x01, 0x00, 0x1f, 0x1f, 0x1f, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x00, 0xa0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, - 0x01, 0x00, 0x20, 0x20, 0x20, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x00, 0xe0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x70, 0x01, 0x00, 0x1d, 0x22, 0x1d, 0x1d, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0x00, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x1e, 0x22, 0x1e, 0x1e, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0x40, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x1f, 0x22, - 0x1f, 0x1f, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0x80, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x20, 0x22, 0x20, 0x20, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0xc0, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x90, 0x02, 0x00, 0x01, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x80, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x04, 0x3a, 0x00, 0x02, 0x04, - 0x08, 0x00, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x80, 0xff, 0x00, 0x78, 0x02, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x2b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x02, 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0xab, 0x00, 0x00, 0x20, 0xff, 0x00, 0x78, 0x02, 0x00, 0x01, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, - 0x20, 0x2b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0xab, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x78, 0x03, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x03, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0xd1, 0x00, 0x00, +u8 const Asm_arm64::raw_encode_forms[49920] = { + 0x01, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, 0x91, 0x00, 0x00, 0x80, 0xff, 0x00, 0x70, 0x01, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x60, 0x01, 0x00, 0x02, 0x02, + 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x8b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x70, 0x01, 0x00, 0x03, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x0b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x60, 0x01, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x8b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x01, 0x00, 0x10, 0x10, 0x10, 0x00, 0x2a, 0x2b, + 0x2c, 0x00, 0x00, 0x84, 0x20, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x12, 0x12, 0x12, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0x60, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x14, 0x14, 0x14, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0xa0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x16, 0x16, 0x16, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, + 0xe0, 0x4e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x0f, 0x0f, 0x0f, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0x20, 0x0e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x11, 0x11, 0x11, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0x60, 0x0e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x13, 0x13, 0x13, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0xa0, 0x0e, 0x00, 0xfc, + 0xe0, 0xff, 0x02, 0x60, 0x01, 0x00, 0x1d, 0x1d, 0x1d, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x00, 0x20, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x01, 0x00, 0x1e, 0x1e, 0x1e, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x00, 0x60, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x01, 0x00, 0x1f, 0x1f, 0x1f, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x00, 0xa0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, + 0x01, 0x00, 0x20, 0x20, 0x20, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x00, 0xe0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x70, 0x01, 0x00, 0x1d, 0x22, 0x1d, 0x1d, 0x2a, 0x4d, 0x2a, 0x2c, 0x00, 0x00, 0x00, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x1e, 0x22, 0x1e, 0x1e, 0x2a, 0x4d, 0x2a, 0x2c, 0x00, 0x00, 0x40, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x1f, 0x22, + 0x1f, 0x1f, 0x2a, 0x4d, 0x2a, 0x2c, 0x00, 0x00, 0x80, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x01, 0x00, 0x20, 0x22, 0x20, 0x20, 0x2a, 0x4d, 0x2a, 0x2c, 0x00, 0x00, 0xc0, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x90, 0x02, 0x00, 0x01, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, 0x31, 0x00, 0x00, 0x80, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x04, 0x3a, 0x00, 0x02, 0x04, + 0x09, 0x00, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x00, 0x80, 0xff, 0x00, 0x78, 0x02, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x2b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x02, 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0xab, 0x00, 0x00, 0x20, 0xff, 0x00, 0x78, 0x02, 0x00, 0x01, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, + 0x20, 0x2b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x68, 0x02, 0x00, 0x02, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0xab, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x78, 0x03, 0x00, 0x03, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x80, 0xff, 0x00, 0x60, 0x03, 0x00, 0x04, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x09, 0x00, 0x00, 0x00, 0x00, 0xd1, 0x00, 0x00, 0x80, 0xff, 0x00, 0x70, 0x03, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x60, 0x03, 0x00, 0x02, 0x02, 0x06, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0xcb, 0x00, 0x00, 0x20, 0xff, 0x00, 0x70, 0x03, 0x00, 0x03, 0x03, 0x07, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0x4b, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x60, - 0x03, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0xcb, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x03, 0x00, 0x10, 0x10, 0x10, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x20, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x12, 0x12, 0x12, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0x60, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x14, 0x14, - 0x14, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xa0, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x16, 0x16, 0x16, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x84, 0xe0, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x1d, 0x1d, 0x1d, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x04, 0x20, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x1e, 0x1e, 0x1e, 0x00, 0x28, 0x29, - 0x2a, 0x00, 0x00, 0x04, 0x60, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x1f, 0x1f, 0x1f, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x04, 0xa0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x20, 0x20, 0x20, 0x00, 0x28, 0x29, 0x2a, 0x00, 0x00, 0x04, 0xe0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x70, 0x03, 0x00, 0x1d, 0x22, 0x1d, 0x1d, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, - 0x01, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x03, 0x00, 0x1e, 0x22, 0x1e, 0x1e, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0x41, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x03, 0x00, 0x1f, 0x22, 0x1f, 0x1f, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0x81, 0x04, 0x00, 0xe0, 0xe0, 0xff, 0x0d, 0x80, 0x03, 0x00, 0x20, 0x22, 0x20, 0x20, 0x28, 0x4b, 0x28, 0x2a, 0x00, 0x00, 0xc1, 0x04, 0x00, 0xe0, - 0xe0, 0xff, 0x0d, 0x90, 0x04, 0x00, 0x01, 0x03, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0x71, 0x00, 0x00, 0x80, 0xff, 0x00, 0x68, 0x04, 0x00, 0x02, 0x04, 0x3a, 0x00, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0xf1, 0x00, 0x00, 0x80, 0xff, 0x00, 0x78, 0x04, 0x00, 0x01, 0x01, 0x05, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x6b, 0x00, 0x00, 0x20, 0xff, 0x00, 0x68, + 0x03, 0x00, 0x04, 0x04, 0x08, 0x00, 0x02, 0x04, 0x07, 0x00, 0x00, 0x00, 0x20, 0xcb, 0x00, 0x00, 0xe0, 0xff, 0x00, 0x70, 0x03, 0x00, 0x10, 0x10, 0x10, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0x20, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x12, 0x12, 0x12, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0x60, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x14, 0x14, + 0x14, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0xa0, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x16, 0x16, 0x16, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x84, 0xe0, 0x6e, 0x00, 0xfc, 0xe0, 0xff, 0x02, 0x60, 0x03, 0x00, 0x1d, 0x1d, 0x1d, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x04, 0x20, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x1e, 0x1e, 0x1e, 0x00, 0x2a, 0x2b, + 0x2c, 0x00, 0x00, 0x04, 0x60, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x1f, 0x1f, 0x1f, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x04, 0xa0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 0x0d, 0x60, 0x03, 0x00, 0x20, 0x20, 0x20, 0x00, 0x2a, 0x2b, 0x2c, 0x00, 0x00, 0x04, 0xe0, 0x04, 0x00, 0xfc, 0xe0, 0xff, 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0x80, 0xff, 0x00, 0x58, + }; -u8 const Asm_arm64::raw_clobber_forms[34524] = { +u8 const Asm_arm64::raw_clobber_forms[34944] = { 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -1975,80 +1988,87 @@ u8 const Asm_arm64::raw_clobber_forms[34524] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x00, 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0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, @@ -2328,18 +2348,18 @@ u8 const Asm_arm64::raw_clobber_forms[34524] = { 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; From 47b637e862bd1fbd8142ad319c1c89ac14c742c0 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 09:50:43 -0400 Subject: [PATCH 31/89] rexcode/arm64: fold sysregs.odin into registers.odin arm64 was the only arch carrying a second register file; registers belong in one place. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/registers.odin | 673 +++++++++++++++++++++++++ core/rexcode/isa/arm64/sysregs.odin | 676 -------------------------- 2 files changed, 673 insertions(+), 676 deletions(-) delete mode 100644 core/rexcode/isa/arm64/sysregs.odin diff --git a/core/rexcode/isa/arm64/registers.odin b/core/rexcode/isa/arm64/registers.odin index 857880864..2ae17eaa1 100644 --- a/core/rexcode/isa/arm64/registers.odin +++ b/core/rexcode/isa/arm64/registers.odin @@ -101,3 +101,676 @@ V28 :: Register(REG_V | 28); V29 :: Register(REG_V | 29); V30 :: Register(REG_V @(require_results) v_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_V | u16(n & 0x1F)) } @(require_results) x_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_X | u16(n & 0x1F)) } @(require_results) w_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_W | u16(n & 0x1F)) } + +// ============================================================================= +// AArch64 SYSTEM REGISTERS (named constants for MRS / MSR) +// ============================================================================= +// +// The MRS / MSR instructions encode the target system register as a 15-bit +// field at bits 19:5 of the instruction word: +// +// o0 (1 bit) : op0 - 2 (op0 = 2 -> o0=0; op0 = 3 -> o0=1) +// op1 (3 bit) : op1 +// CRn (4 bit) : CRn +// CRm (4 bit) : CRm +// op2 (3 bit) : op2 +// +// concatenated MSB-first: o0 || op1 || CRn || CRm || op2. +// +// Users pass these as the immediate operand to `inst_*` builders or by +// hand, e.g.: +// +// MRS X0, NZCV -> op_imm(arm64.NZCV, 2) +// +// The encoder packs the field into SYS_FIELD at bits 19:5 via the standard +// `(imm & 0x7FFF) << 5` mask, so callers can pass either the raw 15-bit +// field value (preferred) or the historical 0x_DA10-style 16-bit form +// (top bit gets masked off). + +// ----------------------------------------------------------------------------- +// Helper for building sysreg field values at compile time. +// sysreg_field(op0, op1, CRn, CRm, op2) = packed 15-bit field +// op0 must be 2 or 3 (the o0 bit = op0 - 2). +// ----------------------------------------------------------------------------- + +sysreg_field :: #force_inline proc "contextless" (op0, op1, CRn, CRm, op2: u32) -> i64 { + o0 := (op0 - 2) & 0x1 + return i64( + (o0 << 14) | + (op1 << 11) | + (CRn << 7) | + (CRm << 3) | + op2, + ) +} + +// ----------------------------------------------------------------------------- +// Commonly-used named registers (the ones every disassembler knows about). +// ----------------------------------------------------------------------------- + +// op0 op1 CRn CRm op2 +NZCV :: i64(0x5A10) // 3 3 4 2 0 +DAIF :: i64(0x5A11) // 3 3 4 2 1 +FPCR :: i64(0x5A20) // 3 3 4 4 0 +FPSR :: i64(0x5A21) // 3 3 4 4 1 +CURRENT_EL :: i64(0x4212) // 3 0 4 2 2 +SP_EL0 :: i64(0x4208) // 3 0 4 1 0 +SP_EL1 :: i64(0x6208) // 3 4 4 1 0 +ELR_EL1 :: i64(0x4201) // 3 0 4 0 1 +ELR_EL2 :: i64(0x6201) // 3 4 4 0 1 +SPSR_EL1 :: i64(0x4200) // 3 0 4 0 0 +SPSR_EL2 :: i64(0x6200) // 3 4 4 0 0 +ESR_EL1 :: i64(0x4290) // 3 0 5 2 0 +ESR_EL2 :: i64(0x6290) // 3 4 5 2 0 +FAR_EL1 :: i64(0x4300) // 3 0 6 0 0 +FAR_EL2 :: i64(0x6300) // 3 4 6 0 0 +TPIDR_EL0 :: i64(0x5E82) // 3 3 13 0 2 +TPIDRRO_EL0 :: i64(0x5E83) // 3 3 13 0 3 +TPIDR_EL1 :: i64(0x4684) // 3 0 13 0 4 (corrected: 3 0 13 0 4 -> 4684 hmm let me recompute) + +// Counters / system identity +CNTFRQ_EL0 :: i64(0x5F00) // 3 3 14 0 0 +CNTPCT_EL0 :: i64(0x5F01) // 3 3 14 0 1 +CNTVCT_EL0 :: i64(0x5F02) // 3 3 14 0 2 +MIDR_EL1 :: i64(0x4000) // 3 0 0 0 0 +MPIDR_EL1 :: i64(0x4005) // 3 0 0 0 5 +DCZID_EL0 :: i64(0x5807) // 3 3 0 0 7 (used by __sve_max_vl-style probes too) +CTR_EL0 :: i64(0x5801) // 3 3 0 0 1 +TCR_EL1 :: i64(0x4102) // 3 0 2 0 2 +SCTLR_EL1 :: i64(0x4080) // 3 0 1 0 0 +VBAR_EL1 :: i64(0x4600) // 3 0 12 0 0 +HCR_EL2 :: i64(0x6088) // 3 4 1 1 0 +TTBR0_EL1 :: i64(0x4100) // 3 0 2 0 0 +TTBR1_EL1 :: i64(0x4101) // 3 0 2 0 1 + +// ----------------------------------------------------------------------------- +// Identification registers (ID_AA64*_EL1) -- read-only feature bitmaps +// ----------------------------------------------------------------------------- +ID_AA64ISAR0_EL1 :: i64(0x4030) // 3 0 0 6 0 +ID_AA64ISAR1_EL1 :: i64(0x4031) // 3 0 0 6 1 +ID_AA64ISAR2_EL1 :: i64(0x4032) // 3 0 0 6 2 +ID_AA64PFR0_EL1 :: i64(0x4020) // 3 0 0 4 0 +ID_AA64PFR1_EL1 :: i64(0x4021) // 3 0 0 4 1 +ID_AA64DFR0_EL1 :: i64(0x4028) // 3 0 0 5 0 +ID_AA64DFR1_EL1 :: i64(0x4029) // 3 0 0 5 1 +ID_AA64MMFR0_EL1 :: i64(0x4038) // 3 0 0 7 0 +ID_AA64MMFR1_EL1 :: i64(0x4039) // 3 0 0 7 1 +ID_AA64MMFR2_EL1 :: i64(0x403A) // 3 0 0 7 2 + +// ----------------------------------------------------------------------------- +// Performance Monitor Unit (PMU) +// ----------------------------------------------------------------------------- +PMCR_EL0 :: i64(0x5CE0) // 3 3 9 12 0 +PMCNTENSET_EL0 :: i64(0x5CE1) // 3 3 9 12 1 +PMCNTENCLR_EL0 :: i64(0x5CE2) // 3 3 9 12 2 +PMOVSCLR_EL0 :: i64(0x5CE3) // 3 3 9 12 3 +PMSWINC_EL0 :: i64(0x5CE4) // 3 3 9 12 4 +PMSELR_EL0 :: i64(0x5CE5) // 3 3 9 12 5 +PMCEID0_EL0 :: i64(0x5CE6) // 3 3 9 12 6 +PMCEID1_EL0 :: i64(0x5CE7) // 3 3 9 12 7 +PMCCNTR_EL0 :: i64(0x5CE8) // 3 3 9 13 0 +PMUSERENR_EL0 :: i64(0x5CF0) // 3 3 9 14 0 + +// ----------------------------------------------------------------------------- +// Memory attribute / context / control registers +// ----------------------------------------------------------------------------- +CONTEXTIDR_EL1 :: i64(0x4681) // 3 0 13 0 1 +CPACR_EL1 :: i64(0x4082) // 3 0 1 0 2 +MAIR_EL1 :: i64(0x4510) // 3 0 10 2 0 +AMAIR_EL1 :: i64(0x4518) // 3 0 10 3 0 +VTCR_EL2 :: i64(0x610A) // 3 4 2 1 2 +VTTBR_EL2 :: i64(0x6108) // 3 4 2 1 0 +ACTLR_EL1 :: i64(0x4081) // 3 0 1 0 1 +AFSR0_EL1 :: i64(0x4288) // 3 0 5 1 0 +AFSR1_EL1 :: i64(0x4289) // 3 0 5 1 1 +ISR_EL1 :: i64(0x4608) // 3 0 12 1 0 + +// ----------------------------------------------------------------------------- +// Random number registers (v8.5-A FEAT_RNG) +// ----------------------------------------------------------------------------- +RNDR :: i64(0x5920) // 3 3 2 4 0 +RNDRRS :: i64(0x5921) // 3 3 2 4 1 + +// ----------------------------------------------------------------------------- +// More ID registers +// ----------------------------------------------------------------------------- +ID_AA64ZFR0_EL1 :: i64(0x4024) // 3 0 0 4 4 (SVE feature ID) +ID_AA64SMFR0_EL1 :: i64(0x4025) // 3 0 0 4 5 (SME feature ID) +ID_AA64AFR0_EL1 :: i64(0x402C) // 3 0 0 5 4 (auxiliary) +ID_AA64AFR1_EL1 :: i64(0x402D) // 3 0 0 5 5 + +// ----------------------------------------------------------------------------- +// Cache hierarchy + selection +// ----------------------------------------------------------------------------- +CCSIDR_EL1 :: i64(0x4800) // 3 1 0 0 0 +CLIDR_EL1 :: i64(0x4801) // 3 1 0 0 1 +CSSELR_EL1 :: i64(0x5000) // 3 2 0 0 0 + +// ----------------------------------------------------------------------------- +// EL2 / EL3 control + return registers +// ----------------------------------------------------------------------------- +SCTLR_EL2 :: i64(0x6080) // 3 4 1 0 0 +SCTLR_EL3 :: i64(0x7080) // 3 6 1 0 0 +SPSR_EL3 :: i64(0x7200) // 3 6 4 0 0 +ELR_EL3 :: i64(0x7201) // 3 6 4 0 1 +TPIDR_EL2 :: i64(0x6682) // 3 4 13 0 2 +TPIDR_EL3 :: i64(0x7682) // 3 6 13 0 2 -- err, EL3 needs op1=6 +HSTR_EL2 :: i64(0x608B) // 3 4 1 1 3 +MDCR_EL2 :: i64(0x6089) // 3 4 1 1 1 +CNTHCTL_EL2 :: i64(0x6708) // 3 4 14 1 0 +DACR32_EL2 :: i64(0x6180) // 3 4 3 0 0 +FPEXC32_EL2 :: i64(0x6298) // 3 4 5 3 0 +VBAR_EL2 :: i64(0x6600) // 3 4 12 0 0 +VBAR_EL3 :: i64(0x7600) // 3 6 12 0 0 +TPIDR2_EL0 :: i64(0x5E85) // 3 3 13 0 5 (SME thread pointer 2) + +// ----------------------------------------------------------------------------- +// Debug registers (op0 = 2) +// ----------------------------------------------------------------------------- +MDSCR_EL1 :: i64(0x0012) // 2 0 0 2 2 +DSPSR_EL0 :: i64(0x5A28) // 3 3 4 5 0 +DLR_EL0 :: i64(0x5A29) // 3 3 4 5 1 +OSLAR_EL1 :: i64(0x0084) // 2 0 1 0 4 (op0=2 -> o0=0) +OSLSR_EL1 :: i64(0x008C) // 2 0 1 1 4 + +// ----------------------------------------------------------------------------- +// Cache / Memory feature extras +// ----------------------------------------------------------------------------- +RGSR_EL1 :: i64(0x4085) // 3 0 1 0 5 (FEAT_MTE) +GCR_EL1 :: i64(0x4086) // 3 0 1 0 6 (FEAT_MTE) +TFSR_EL1 :: i64(0x42B0) // 3 0 5 6 0 (FEAT_MTE) +TFSRE0_EL1 :: i64(0x42B1) // 3 0 5 6 1 (FEAT_MTE) +GMID_EL1 :: i64(0x4804) // 3 1 0 0 4 (FEAT_MTE) + +// ----------------------------------------------------------------------------- +// SME / SVE configuration +// ----------------------------------------------------------------------------- +SVCR :: i64(0x5A12) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) +SMCR_EL1 :: i64(0x4096) // 3 0 1 2 6 (FEAT_SME) +SMCR_EL2 :: i64(0x6096) // 3 4 1 2 6 +ZCR_EL1 :: i64(0x4090) // 3 0 1 2 0 (FEAT_SVE) +ZCR_EL2 :: i64(0x6090) // 3 4 1 2 0 +ZCR_EL3 :: i64(0x7090) // 3 6 1 2 0 + +// ----------------------------------------------------------------------------- +// Cache / data prefetch hint controls +// ----------------------------------------------------------------------------- +PRSELR_EL1 :: i64(0x4311) // 3 0 6 2 1 +APIAKEYLO_EL1 :: i64(0x4108) // 3 0 2 1 0 (FEAT_PAuth) +APIAKEYHI_EL1 :: i64(0x4109) // 3 0 2 1 1 +APIBKEYLO_EL1 :: i64(0x410A) // 3 0 2 1 2 +APIBKEYHI_EL1 :: i64(0x410B) // 3 0 2 1 3 +APDAKEYLO_EL1 :: i64(0x4110) // 3 0 2 2 0 +APDAKEYHI_EL1 :: i64(0x4111) // 3 0 2 2 1 +APDBKEYLO_EL1 :: i64(0x4112) // 3 0 2 2 2 +APDBKEYHI_EL1 :: i64(0x4113) // 3 0 2 2 3 +APGAKEYLO_EL1 :: i64(0x4118) // 3 0 2 3 0 +APGAKEYHI_EL1 :: i64(0x4119) // 3 0 2 3 1 + +// ============================================================================= +// Batch 5: comprehensive sysreg sweep +// ============================================================================= + +// ---- More ID registers (AArch32 + extras) ---- +ID_AA64DFR2_EL1 :: i64(0x402A) // 3 0 0 5 2 +ID_AA64ISAR3_EL1 :: i64(0x4033) // 3 0 0 6 3 +ID_PFR0_EL1 :: i64(0x4008) // 3 0 0 1 0 +ID_PFR1_EL1 :: i64(0x4009) // 3 0 0 1 1 +ID_DFR0_EL1 :: i64(0x400A) // 3 0 0 1 2 +ID_AFR0_EL1 :: i64(0x400B) // 3 0 0 1 3 +ID_MMFR0_EL1 :: i64(0x400C) // 3 0 0 1 4 +ID_MMFR1_EL1 :: i64(0x400D) // 3 0 0 1 5 +ID_MMFR2_EL1 :: i64(0x400E) // 3 0 0 1 6 +ID_MMFR3_EL1 :: i64(0x400F) // 3 0 0 1 7 +ID_MMFR4_EL1 :: i64(0x4016) // 3 0 0 2 6 +ID_MMFR5_EL1 :: i64(0x401E) // 3 0 0 3 6 +ID_ISAR0_EL1 :: i64(0x4010) // 3 0 0 2 0 +ID_ISAR1_EL1 :: i64(0x4011) // 3 0 0 2 1 +ID_ISAR2_EL1 :: i64(0x4012) // 3 0 0 2 2 +ID_ISAR3_EL1 :: i64(0x4013) // 3 0 0 2 3 +ID_ISAR4_EL1 :: i64(0x4014) // 3 0 0 2 4 +ID_ISAR5_EL1 :: i64(0x4015) // 3 0 0 2 5 +ID_ISAR6_EL1 :: i64(0x4017) // 3 0 0 2 7 +ID_PFR2_EL1 :: i64(0x401C) // 3 0 0 3 4 +MVFR0_EL1 :: i64(0x4018) // 3 0 0 3 0 +MVFR1_EL1 :: i64(0x4019) // 3 0 0 3 1 +MVFR2_EL1 :: i64(0x401A) // 3 0 0 3 2 + +// ---- Counter / Timer (full set) ---- +CNTKCTL_EL1 :: i64(0x4708) // 3 0 14 1 0 +CNTP_TVAL_EL0 :: i64(0x5F10) // 3 3 14 2 0 +CNTP_CTL_EL0 :: i64(0x5F11) // 3 3 14 2 1 +CNTP_CVAL_EL0 :: i64(0x5F12) // 3 3 14 2 2 +CNTV_TVAL_EL0 :: i64(0x5F18) // 3 3 14 3 0 +CNTV_CTL_EL0 :: i64(0x5F19) // 3 3 14 3 1 +CNTV_CVAL_EL0 :: i64(0x5F1A) // 3 3 14 3 2 +CNTHP_TVAL_EL2 :: i64(0x6710) // 3 4 14 2 0 +CNTHP_CTL_EL2 :: i64(0x6711) // 3 4 14 2 1 +CNTHP_CVAL_EL2 :: i64(0x6712) // 3 4 14 2 2 +CNTHV_TVAL_EL2 :: i64(0x6718) // 3 4 14 3 0 +CNTHV_CTL_EL2 :: i64(0x6719) // 3 4 14 3 1 +CNTHV_CVAL_EL2 :: i64(0x671A) // 3 4 14 3 2 +CNTPS_TVAL_EL1 :: i64(0x7F10) // 3 7 14 2 0 +CNTPS_CTL_EL1 :: i64(0x7F11) // 3 7 14 2 1 +CNTPS_CVAL_EL1 :: i64(0x7F12) // 3 7 14 2 2 +CNTVOFF_EL2 :: i64(0x6703) // 3 4 14 0 3 + +// ---- Debug breakpoints (DBGB*) and watchpoints (DBGW*), numbered ---- +// +// Each register file is 16 deep: DBGBVR0..15, DBGBCR0..15, DBGWVR0..15, +// DBGWCR0..15. Use the helper: +// sysreg_debug_breakpoint_value(n) -- DBGBVRn_EL1 = (2, 0, 0, n, 4) +// sysreg_debug_breakpoint_control(n) -- DBGBCRn_EL1 = (2, 0, 0, n, 5) +// sysreg_debug_watchpoint_value(n) -- DBGWVRn_EL1 = (2, 0, 0, n, 6) +// sysreg_debug_watchpoint_control(n) -- DBGWCRn_EL1 = (2, 0, 0, n, 7) + +sysreg_debug_breakpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(2, 0, 0, n & 0xF, 4) +} +sysreg_debug_breakpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(2, 0, 0, n & 0xF, 5) +} +sysreg_debug_watchpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(2, 0, 0, n & 0xF, 6) +} +sysreg_debug_watchpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(2, 0, 0, n & 0xF, 7) +} + +// Other debug registers +DBGDTR_EL0 :: i64(0x1820) // 2 3 0 4 0 +DBGDTRRX_EL0 :: i64(0x1828) // 2 3 0 5 0 +DBGDTRTX_EL0 :: i64(0x1828) // 2 3 0 5 0 (write view of DBGDTRRX_EL0) +DBGPRCR_EL1 :: i64(0x00A4) // 2 0 1 4 4 +DBGCLAIMSET_EL1 :: i64(0x03C6) // 2 0 7 8 6 +DBGCLAIMCLR_EL1 :: i64(0x03CE) // 2 0 7 9 6 +DBGAUTHSTATUS_EL1:: i64(0x03F6) // 2 0 7 14 6 +MDCCINT_EL1 :: i64(0x0010) // 2 0 0 2 0 +MDRAR_EL1 :: i64(0x0080) // 2 0 1 0 0 + +// PMU event counters (PMEVCNTRn_EL0 / PMEVTYPERn_EL0). Up to n=30. +// PMEVCNTRn_EL0 = sysreg(3, 3, 14, 8+(n>>3), n & 7) +// PMEVTYPERn_EL0 = sysreg(3, 3, 14, 12+(n>>3), n & 7) + +sysreg_pmu_event_counter :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(3, 3, 14, 8 + ((n >> 3) & 0x3), n & 0x7) +} +sysreg_pmu_event_typer :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(3, 3, 14, 12 + ((n >> 3) & 0x3), n & 0x7) +} + +PMINTENSET_EL1 :: i64(0x44F1) // 3 0 9 14 1 +PMINTENCLR_EL1 :: i64(0x44F2) // 3 0 9 14 2 + +// ---- GICv3 (ICC_*) -- CPU interface ---- +ICC_IAR0_EL1 :: i64(0x4640) // 3 0 12 8 0 +ICC_IAR1_EL1 :: i64(0x4660) // 3 0 12 12 0 +ICC_EOIR0_EL1 :: i64(0x4641) // 3 0 12 8 1 +ICC_EOIR1_EL1 :: i64(0x4661) // 3 0 12 12 1 +ICC_HPPIR0_EL1 :: i64(0x4642) // 3 0 12 8 2 +ICC_HPPIR1_EL1 :: i64(0x4662) // 3 0 12 12 2 +ICC_BPR0_EL1 :: i64(0x4643) // 3 0 12 8 3 +ICC_BPR1_EL1 :: i64(0x4663) // 3 0 12 12 3 +ICC_DIR_EL1 :: i64(0x4659) // 3 0 12 11 1 +ICC_PMR_EL1 :: i64(0x4230) // 3 0 4 6 0 +ICC_RPR_EL1 :: i64(0x465B) // 3 0 12 11 3 +ICC_SGI0R_EL1 :: i64(0x465F) // 3 0 12 11 7 +ICC_SGI1R_EL1 :: i64(0x465D) // 3 0 12 11 5 +ICC_ASGI1R_EL1 :: i64(0x465E) // 3 0 12 11 6 +ICC_SRE_EL1 :: i64(0x4665) // 3 0 12 12 5 +ICC_SRE_EL2 :: i64(0x664D) // 3 4 12 9 5 +ICC_SRE_EL3 :: i64(0x7665) // 3 6 12 12 5 +ICC_CTLR_EL1 :: i64(0x4664) // 3 0 12 12 4 +ICC_CTLR_EL3 :: i64(0x7664) // 3 6 12 12 4 +ICC_IGRPEN0_EL1 :: i64(0x4666) // 3 0 12 12 6 +ICC_IGRPEN1_EL1 :: i64(0x4667) // 3 0 12 12 7 +ICC_IGRPEN1_EL3 :: i64(0x7667) // 3 6 12 12 7 + +// ---- GICv3 hypervisor (ICH_*) ---- +ICH_HCR_EL2 :: i64(0x6658) // 3 4 12 11 0 +ICH_VTR_EL2 :: i64(0x6659) // 3 4 12 11 1 +ICH_MISR_EL2 :: i64(0x665A) // 3 4 12 11 2 +ICH_EISR_EL2 :: i64(0x665B) // 3 4 12 11 3 +ICH_ELRSR_EL2 :: i64(0x665D) // 3 4 12 11 5 +ICH_VMCR_EL2 :: i64(0x665F) // 3 4 12 11 7 + +// ICH_LR0_EL2 .. ICH_LR15_EL2 = sysreg(3, 4, 12, 12+(n>>3), n & 7) +sysreg_ich_lr :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(3, 4, 12, 12 + ((n >> 3) & 0x1), n & 0x7) +} + +// ICH_AP0Rn_EL2 (n=0..3) and ICH_AP1Rn_EL2 (n=0..3) +sysreg_ich_ap0r :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(3, 4, 12, 8, n & 0x3) +} +sysreg_ich_ap1r :: #force_inline proc "contextless" (n: u32) -> i64 { + return sysreg_field(3, 4, 12, 9, n & 0x3) +} + +// ---- TRBE (Trace Buffer Extension, FEAT_TRBE) ---- +TRBLIMITR_EL1 :: i64(0x44D8) // 3 0 9 11 0 +TRBPTR_EL1 :: i64(0x44D9) // 3 0 9 11 1 +TRBBASER_EL1 :: i64(0x44DA) // 3 0 9 11 2 +TRBSR_EL1 :: i64(0x44DB) // 3 0 9 11 3 +TRBMAR_EL1 :: i64(0x44DC) // 3 0 9 11 4 +TRBTRG_EL1 :: i64(0x44DE) // 3 0 9 11 6 +TRBIDR_EL1 :: i64(0x44DF) // 3 0 9 11 7 + +// ---- SPE (Statistical Profiling Extension, FEAT_SPE) ---- +PMSCR_EL1 :: i64(0x44C8) // 3 0 9 9 0 +PMSICR_EL1 :: i64(0x44CA) // 3 0 9 9 2 +PMSIRR_EL1 :: i64(0x44CB) // 3 0 9 9 3 +PMSFCR_EL1 :: i64(0x44CC) // 3 0 9 9 4 +PMSEVFR_EL1 :: i64(0x44CD) // 3 0 9 9 5 +PMSLATFR_EL1 :: i64(0x44CE) // 3 0 9 9 6 +PMSIDR_EL1 :: i64(0x44CF) // 3 0 9 9 7 +PMBLIMITR_EL1 :: i64(0x44D0) // 3 0 9 10 0 +PMBPTR_EL1 :: i64(0x44D1) // 3 0 9 10 1 +PMBSR_EL1 :: i64(0x44D3) // 3 0 9 10 3 +PMBIDR_EL1 :: i64(0x44D7) // 3 0 9 10 7 + +// ---- RAS (Reliability, Availability, Serviceability) ---- +ERRSELR_EL1 :: i64(0x4299) // 3 0 5 3 1 +ERRIDR_EL1 :: i64(0x4298) // 3 0 5 3 0 +ERXADDR_EL1 :: i64(0x42A3) // 3 0 5 4 3 +ERXCTLR_EL1 :: i64(0x42A1) // 3 0 5 4 1 +ERXFR_EL1 :: i64(0x42A0) // 3 0 5 4 0 +ERXSTATUS_EL1 :: i64(0x42A2) // 3 0 5 4 2 +ERXMISC0_EL1 :: i64(0x42A8) // 3 0 5 5 0 +ERXMISC1_EL1 :: i64(0x42A9) // 3 0 5 5 1 +ERXMISC2_EL1 :: i64(0x42AA) // 3 0 5 5 2 +ERXMISC3_EL1 :: i64(0x42AB) // 3 0 5 5 3 +DISR_EL1 :: i64(0x4609) // 3 0 12 1 1 +VDISR_EL2 :: i64(0x6609) // 3 4 12 1 1 +VSESR_EL2 :: i64(0x6293) // 3 4 5 2 3 + +// ---- LOR (Limited Ordering Region) ---- +LORC_EL1 :: i64(0x4523) // 3 0 10 4 3 +LOREA_EL1 :: i64(0x4521) // 3 0 10 4 1 +LORID_EL1 :: i64(0x4527) // 3 0 10 4 7 +LORN_EL1 :: i64(0x4522) // 3 0 10 4 2 +LORSA_EL1 :: i64(0x4520) // 3 0 10 4 0 + +// ---- Translation result (returned by AT) ---- +PAR_EL1 :: i64(0x43A0) // 3 0 7 4 0 + +// ---- RME (Realm Management Extension) sysregs ---- +GPCCR_EL3 :: i64(0x710E) // 3 6 2 1 6 (Granule Protection Control) +GPTBR_EL3 :: i64(0x710C) // 3 6 2 1 4 (Granule Protection Table Base) +MFAR_EL3 :: i64(0x7305) // 3 6 6 0 5 (Multiple FAR) + +// ---- TPIDRRO_EL0 alias / extra thread pointers ---- +// (TPIDRRO_EL0 already added above) + +// ---- Performance Monitor extras ---- +PMCCFILTR_EL0 :: i64(0x5F7F) // 3 3 14 15 7 +PMUSERENR_EL0_REPEAT :: PMUSERENR_EL0 // re-export alias placeholder + +// ----------------------------------------------------------------------------- +// Value -> name, for printing +// ----------------------------------------------------------------------------- +// +// MRS/MSR carry the system register as a packed 15-bit field, so a disassembly +// has a number where an assembler wants a name. Sorted by value; binary search. +// +// 1 encodings carry two names. Where the pair is a read view and a write +// view of one register (DBGDTRRX/DBGDTRTX) the read name wins, since MRS is +// the direction that has to print; the rest are genuine aliases and either +// name assembles, so a round-trip can come back spelled as the sibling. + +Sysreg_Name :: struct { + value: u16, + name: string, +} + +@(rodata) +SYSREG_NAMES := [?]Sysreg_Name{ + {0x0010, "mdccint_el1"}, + {0x0012, "mdscr_el1"}, + {0x0080, "mdrar_el1"}, + {0x0084, "oslar_el1"}, + {0x008C, "oslsr_el1"}, + {0x00A4, "dbgprcr_el1"}, + {0x03C6, "dbgclaimset_el1"}, + {0x03CE, "dbgclaimclr_el1"}, + {0x03F6, "dbgauthstatus_el1"}, + {0x1820, "dbgdtr_el0"}, + {0x1828, "dbgdtrrx_el0"}, + {0x4000, "midr_el1"}, + {0x4005, "mpidr_el1"}, + {0x4008, "id_pfr0_el1"}, + {0x4009, "id_pfr1_el1"}, + {0x400A, "id_dfr0_el1"}, + {0x400B, "id_afr0_el1"}, + {0x400C, "id_mmfr0_el1"}, + {0x400D, "id_mmfr1_el1"}, + {0x400E, "id_mmfr2_el1"}, + {0x400F, "id_mmfr3_el1"}, + {0x4010, "id_isar0_el1"}, + {0x4011, "id_isar1_el1"}, + {0x4012, "id_isar2_el1"}, + {0x4013, "id_isar3_el1"}, + {0x4014, "id_isar4_el1"}, + {0x4015, "id_isar5_el1"}, + {0x4016, "id_mmfr4_el1"}, + {0x4017, "id_isar6_el1"}, + {0x4018, "mvfr0_el1"}, + {0x4019, "mvfr1_el1"}, + {0x401A, "mvfr2_el1"}, + {0x401C, "id_pfr2_el1"}, + {0x401E, "id_mmfr5_el1"}, + {0x4020, "id_aa64pfr0_el1"}, + {0x4021, "id_aa64pfr1_el1"}, + {0x4024, "id_aa64zfr0_el1"}, + {0x4025, "id_aa64smfr0_el1"}, + {0x4028, "id_aa64dfr0_el1"}, + {0x4029, "id_aa64dfr1_el1"}, + {0x402A, "id_aa64dfr2_el1"}, + {0x402C, "id_aa64afr0_el1"}, + {0x402D, "id_aa64afr1_el1"}, + {0x4030, "id_aa64isar0_el1"}, + {0x4031, "id_aa64isar1_el1"}, + {0x4032, "id_aa64isar2_el1"}, + {0x4033, "id_aa64isar3_el1"}, + {0x4038, "id_aa64mmfr0_el1"}, + {0x4039, "id_aa64mmfr1_el1"}, + {0x403A, "id_aa64mmfr2_el1"}, + {0x4080, "sctlr_el1"}, + {0x4081, "actlr_el1"}, + {0x4082, "cpacr_el1"}, + {0x4085, "rgsr_el1"}, + {0x4086, "gcr_el1"}, + {0x4090, "zcr_el1"}, + {0x4096, "smcr_el1"}, + {0x4100, "ttbr0_el1"}, + {0x4101, "ttbr1_el1"}, + {0x4102, "tcr_el1"}, + {0x4108, "apiakeylo_el1"}, + {0x4109, "apiakeyhi_el1"}, + {0x410A, "apibkeylo_el1"}, + {0x410B, "apibkeyhi_el1"}, + {0x4110, "apdakeylo_el1"}, + {0x4111, "apdakeyhi_el1"}, + {0x4112, "apdbkeylo_el1"}, + {0x4113, "apdbkeyhi_el1"}, + {0x4118, "apgakeylo_el1"}, + {0x4119, "apgakeyhi_el1"}, + {0x4200, "spsr_el1"}, + {0x4201, "elr_el1"}, + {0x4208, "sp_el0"}, + {0x4212, "currentel"}, + {0x4230, "icc_pmr_el1"}, + {0x4288, "afsr0_el1"}, + {0x4289, "afsr1_el1"}, + {0x4290, "esr_el1"}, + {0x4298, "erridr_el1"}, + {0x4299, "errselr_el1"}, + {0x42A0, "erxfr_el1"}, + {0x42A1, "erxctlr_el1"}, + {0x42A2, "erxstatus_el1"}, + {0x42A3, "erxaddr_el1"}, + {0x42A8, "erxmisc0_el1"}, + {0x42A9, "erxmisc1_el1"}, + {0x42AA, "erxmisc2_el1"}, + {0x42AB, "erxmisc3_el1"}, + {0x42B0, "tfsr_el1"}, + {0x42B1, "tfsre0_el1"}, + {0x4300, "far_el1"}, + {0x4311, "prselr_el1"}, + {0x43A0, "par_el1"}, + {0x44C8, "pmscr_el1"}, + {0x44CA, "pmsicr_el1"}, + {0x44CB, "pmsirr_el1"}, + {0x44CC, "pmsfcr_el1"}, + {0x44CD, "pmsevfr_el1"}, + {0x44CE, "pmslatfr_el1"}, + {0x44CF, "pmsidr_el1"}, + {0x44D0, "pmblimitr_el1"}, + {0x44D1, "pmbptr_el1"}, + {0x44D3, "pmbsr_el1"}, + {0x44D7, "pmbidr_el1"}, + {0x44D8, "trblimitr_el1"}, + {0x44D9, "trbptr_el1"}, + {0x44DA, "trbbaser_el1"}, + {0x44DB, "trbsr_el1"}, + {0x44DC, "trbmar_el1"}, + {0x44DE, "trbtrg_el1"}, + {0x44DF, "trbidr_el1"}, + {0x44F1, "pmintenset_el1"}, + {0x44F2, "pmintenclr_el1"}, + {0x4510, "mair_el1"}, + {0x4518, "amair_el1"}, + {0x4520, "lorsa_el1"}, + {0x4521, "lorea_el1"}, + {0x4522, "lorn_el1"}, + {0x4523, "lorc_el1"}, + {0x4527, "lorid_el1"}, + {0x4600, "vbar_el1"}, + {0x4608, "isr_el1"}, + {0x4609, "disr_el1"}, + {0x4640, "icc_iar0_el1"}, + {0x4641, "icc_eoir0_el1"}, + {0x4642, "icc_hppir0_el1"}, + {0x4643, "icc_bpr0_el1"}, + {0x4659, "icc_dir_el1"}, + {0x465B, "icc_rpr_el1"}, + {0x465D, "icc_sgi1r_el1"}, + {0x465E, "icc_asgi1r_el1"}, + {0x465F, "icc_sgi0r_el1"}, + {0x4660, "icc_iar1_el1"}, + {0x4661, "icc_eoir1_el1"}, + {0x4662, "icc_hppir1_el1"}, + {0x4663, "icc_bpr1_el1"}, + {0x4664, "icc_ctlr_el1"}, + {0x4665, "icc_sre_el1"}, + {0x4666, "icc_igrpen0_el1"}, + {0x4667, "icc_igrpen1_el1"}, + {0x4681, "contextidr_el1"}, + {0x4684, "tpidr_el1"}, + {0x4708, "cntkctl_el1"}, + {0x4800, "ccsidr_el1"}, + {0x4801, "clidr_el1"}, + {0x4804, "gmid_el1"}, + {0x5000, "csselr_el1"}, + {0x5801, "ctr_el0"}, + {0x5807, "dczid_el0"}, + {0x5920, "rndr"}, + {0x5921, "rndrrs"}, + {0x5A10, "nzcv"}, + {0x5A11, "daif"}, + {0x5A12, "svcr"}, + {0x5A20, "fpcr"}, + {0x5A21, "fpsr"}, + {0x5A28, "dspsr_el0"}, + {0x5A29, "dlr_el0"}, + {0x5CE0, "pmcr_el0"}, + {0x5CE1, "pmcntenset_el0"}, + {0x5CE2, "pmcntenclr_el0"}, + {0x5CE3, "pmovsclr_el0"}, + {0x5CE4, "pmswinc_el0"}, + {0x5CE5, "pmselr_el0"}, + {0x5CE6, "pmceid0_el0"}, + {0x5CE7, "pmceid1_el0"}, + {0x5CE8, "pmccntr_el0"}, + {0x5CF0, "pmuserenr_el0"}, + {0x5E82, "tpidr_el0"}, + {0x5E83, "tpidrro_el0"}, + {0x5E85, "tpidr2_el0"}, + {0x5F00, "cntfrq_el0"}, + {0x5F01, "cntpct_el0"}, + {0x5F02, "cntvct_el0"}, + {0x5F10, "cntp_tval_el0"}, + {0x5F11, "cntp_ctl_el0"}, + {0x5F12, "cntp_cval_el0"}, + {0x5F18, "cntv_tval_el0"}, + {0x5F19, "cntv_ctl_el0"}, + {0x5F1A, "cntv_cval_el0"}, + {0x5F7F, "pmccfiltr_el0"}, + {0x6080, "sctlr_el2"}, + {0x6088, "hcr_el2"}, + {0x6089, "mdcr_el2"}, + {0x608B, "hstr_el2"}, + {0x6090, "zcr_el2"}, + {0x6096, "smcr_el2"}, + {0x6108, "vttbr_el2"}, + {0x610A, "vtcr_el2"}, + {0x6180, "dacr32_el2"}, + {0x6200, "spsr_el2"}, + {0x6201, "elr_el2"}, + {0x6208, "sp_el1"}, + {0x6290, "esr_el2"}, + {0x6293, "vsesr_el2"}, + {0x6298, "fpexc32_el2"}, + {0x6300, "far_el2"}, + {0x6600, "vbar_el2"}, + {0x6609, "vdisr_el2"}, + {0x664D, "icc_sre_el2"}, + {0x6658, "ich_hcr_el2"}, + {0x6659, "ich_vtr_el2"}, + {0x665A, "ich_misr_el2"}, + {0x665B, "ich_eisr_el2"}, + {0x665D, "ich_elrsr_el2"}, + {0x665F, "ich_vmcr_el2"}, + {0x6682, "tpidr_el2"}, + {0x6703, "cntvoff_el2"}, + {0x6708, "cnthctl_el2"}, + {0x6710, "cnthp_tval_el2"}, + {0x6711, "cnthp_ctl_el2"}, + {0x6712, "cnthp_cval_el2"}, + {0x6718, "cnthv_tval_el2"}, + {0x6719, "cnthv_ctl_el2"}, + {0x671A, "cnthv_cval_el2"}, + {0x7080, "sctlr_el3"}, + {0x7090, "zcr_el3"}, + {0x710C, "gptbr_el3"}, + {0x710E, "gpccr_el3"}, + {0x7200, "spsr_el3"}, + {0x7201, "elr_el3"}, + {0x7305, "mfar_el3"}, + {0x7600, "vbar_el3"}, + {0x7664, "icc_ctlr_el3"}, + {0x7665, "icc_sre_el3"}, + {0x7667, "icc_igrpen1_el3"}, + {0x7682, "tpidr_el3"}, + {0x7F10, "cntps_tval_el1"}, + {0x7F11, "cntps_ctl_el1"}, + {0x7F12, "cntps_cval_el1"}, +} + +// Name for a packed system-register field, or ok=false when it is not one we +// know -- callers should fall back to printing the raw immediate. +@(require_results) +sysreg_name :: proc "contextless" (value: i64) -> (name: string, ok: bool) { + v := u16(value & 0x7FFF) + lo, hi := 0, len(SYSREG_NAMES) - 1 + for lo <= hi { + mid := (lo + hi) / 2 + e := SYSREG_NAMES[mid] + switch { + case e.value == v: return e.name, true + case e.value < v: lo = mid + 1 + case: hi = mid - 1 + } + } + return "", false +} diff --git a/core/rexcode/isa/arm64/sysregs.odin b/core/rexcode/isa/arm64/sysregs.odin deleted file mode 100644 index 33dff77cb..000000000 --- a/core/rexcode/isa/arm64/sysregs.odin +++ /dev/null @@ -1,676 +0,0 @@ -// rexcode ยท Brendan Punsky (dotbmp@github), original author - -package rexcode_arm64 - -// ============================================================================= -// AArch64 SYSTEM REGISTERS (named constants for MRS / MSR) -// ============================================================================= -// -// The MRS / MSR instructions encode the target system register as a 15-bit -// field at bits 19:5 of the instruction word: -// -// o0 (1 bit) : op0 - 2 (op0 = 2 -> o0=0; op0 = 3 -> o0=1) -// op1 (3 bit) : op1 -// CRn (4 bit) : CRn -// CRm (4 bit) : CRm -// op2 (3 bit) : op2 -// -// concatenated MSB-first: o0 || op1 || CRn || CRm || op2. -// -// Users pass these as the immediate operand to `inst_*` builders or by -// hand, e.g.: -// -// MRS X0, NZCV -> op_imm(arm64.NZCV, 2) -// -// The encoder packs the field into SYS_FIELD at bits 19:5 via the standard -// `(imm & 0x7FFF) << 5` mask, so callers can pass either the raw 15-bit -// field value (preferred) or the historical 0x_DA10-style 16-bit form -// (top bit gets masked off). - -// ----------------------------------------------------------------------------- -// Helper for building sysreg field values at compile time. -// sysreg_field(op0, op1, CRn, CRm, op2) = packed 15-bit field -// op0 must be 2 or 3 (the o0 bit = op0 - 2). -// ----------------------------------------------------------------------------- - -sysreg_field :: #force_inline proc "contextless" (op0, op1, CRn, CRm, op2: u32) -> i64 { - o0 := (op0 - 2) & 0x1 - return i64( - (o0 << 14) | - (op1 << 11) | - (CRn << 7) | - (CRm << 3) | - op2, - ) -} - -// ----------------------------------------------------------------------------- -// Commonly-used named registers (the ones every disassembler knows about). -// ----------------------------------------------------------------------------- - -// op0 op1 CRn CRm op2 -NZCV :: i64(0x5A10) // 3 3 4 2 0 -DAIF :: i64(0x5A11) // 3 3 4 2 1 -FPCR :: i64(0x5A20) // 3 3 4 4 0 -FPSR :: i64(0x5A21) // 3 3 4 4 1 -CURRENT_EL :: i64(0x4212) // 3 0 4 2 2 -SP_EL0 :: i64(0x4208) // 3 0 4 1 0 -SP_EL1 :: i64(0x6208) // 3 4 4 1 0 -ELR_EL1 :: i64(0x4201) // 3 0 4 0 1 -ELR_EL2 :: i64(0x6201) // 3 4 4 0 1 -SPSR_EL1 :: i64(0x4200) // 3 0 4 0 0 -SPSR_EL2 :: i64(0x6200) // 3 4 4 0 0 -ESR_EL1 :: i64(0x4290) // 3 0 5 2 0 -ESR_EL2 :: i64(0x6290) // 3 4 5 2 0 -FAR_EL1 :: i64(0x4300) // 3 0 6 0 0 -FAR_EL2 :: i64(0x6300) // 3 4 6 0 0 -TPIDR_EL0 :: i64(0x5E82) // 3 3 13 0 2 -TPIDRRO_EL0 :: i64(0x5E83) // 3 3 13 0 3 -TPIDR_EL1 :: i64(0x4684) // 3 0 13 0 4 (corrected: 3 0 13 0 4 -> 4684 hmm let me recompute) - -// Counters / system identity -CNTFRQ_EL0 :: i64(0x5F00) // 3 3 14 0 0 -CNTPCT_EL0 :: i64(0x5F01) // 3 3 14 0 1 -CNTVCT_EL0 :: i64(0x5F02) // 3 3 14 0 2 -MIDR_EL1 :: i64(0x4000) // 3 0 0 0 0 -MPIDR_EL1 :: i64(0x4005) // 3 0 0 0 5 -DCZID_EL0 :: i64(0x5807) // 3 3 0 0 7 (used by __sve_max_vl-style probes too) -CTR_EL0 :: i64(0x5801) // 3 3 0 0 1 -TCR_EL1 :: i64(0x4102) // 3 0 2 0 2 -SCTLR_EL1 :: i64(0x4080) // 3 0 1 0 0 -VBAR_EL1 :: i64(0x4600) // 3 0 12 0 0 -HCR_EL2 :: i64(0x6088) // 3 4 1 1 0 -TTBR0_EL1 :: i64(0x4100) // 3 0 2 0 0 -TTBR1_EL1 :: i64(0x4101) // 3 0 2 0 1 - -// ----------------------------------------------------------------------------- -// Identification registers (ID_AA64*_EL1) -- read-only feature bitmaps -// ----------------------------------------------------------------------------- -ID_AA64ISAR0_EL1 :: i64(0x4030) // 3 0 0 6 0 -ID_AA64ISAR1_EL1 :: i64(0x4031) // 3 0 0 6 1 -ID_AA64ISAR2_EL1 :: i64(0x4032) // 3 0 0 6 2 -ID_AA64PFR0_EL1 :: i64(0x4020) // 3 0 0 4 0 -ID_AA64PFR1_EL1 :: i64(0x4021) // 3 0 0 4 1 -ID_AA64DFR0_EL1 :: i64(0x4028) // 3 0 0 5 0 -ID_AA64DFR1_EL1 :: i64(0x4029) // 3 0 0 5 1 -ID_AA64MMFR0_EL1 :: i64(0x4038) // 3 0 0 7 0 -ID_AA64MMFR1_EL1 :: i64(0x4039) // 3 0 0 7 1 -ID_AA64MMFR2_EL1 :: i64(0x403A) // 3 0 0 7 2 - -// ----------------------------------------------------------------------------- -// Performance Monitor Unit (PMU) -// ----------------------------------------------------------------------------- -PMCR_EL0 :: i64(0x5CE0) // 3 3 9 12 0 -PMCNTENSET_EL0 :: i64(0x5CE1) // 3 3 9 12 1 -PMCNTENCLR_EL0 :: i64(0x5CE2) // 3 3 9 12 2 -PMOVSCLR_EL0 :: i64(0x5CE3) // 3 3 9 12 3 -PMSWINC_EL0 :: i64(0x5CE4) // 3 3 9 12 4 -PMSELR_EL0 :: i64(0x5CE5) // 3 3 9 12 5 -PMCEID0_EL0 :: i64(0x5CE6) // 3 3 9 12 6 -PMCEID1_EL0 :: i64(0x5CE7) // 3 3 9 12 7 -PMCCNTR_EL0 :: i64(0x5CE8) // 3 3 9 13 0 -PMUSERENR_EL0 :: i64(0x5CF0) // 3 3 9 14 0 - -// ----------------------------------------------------------------------------- -// Memory attribute / context / control registers -// ----------------------------------------------------------------------------- -CONTEXTIDR_EL1 :: i64(0x4681) // 3 0 13 0 1 -CPACR_EL1 :: i64(0x4082) // 3 0 1 0 2 -MAIR_EL1 :: i64(0x4510) // 3 0 10 2 0 -AMAIR_EL1 :: i64(0x4518) // 3 0 10 3 0 -VTCR_EL2 :: i64(0x610A) // 3 4 2 1 2 -VTTBR_EL2 :: i64(0x6108) // 3 4 2 1 0 -ACTLR_EL1 :: i64(0x4081) // 3 0 1 0 1 -AFSR0_EL1 :: i64(0x4288) // 3 0 5 1 0 -AFSR1_EL1 :: i64(0x4289) // 3 0 5 1 1 -ISR_EL1 :: i64(0x4608) // 3 0 12 1 0 - -// ----------------------------------------------------------------------------- -// Random number registers (v8.5-A FEAT_RNG) -// ----------------------------------------------------------------------------- -RNDR :: i64(0x5920) // 3 3 2 4 0 -RNDRRS :: i64(0x5921) // 3 3 2 4 1 - -// ----------------------------------------------------------------------------- -// More ID registers -// ----------------------------------------------------------------------------- -ID_AA64ZFR0_EL1 :: i64(0x4024) // 3 0 0 4 4 (SVE feature ID) -ID_AA64SMFR0_EL1 :: i64(0x4025) // 3 0 0 4 5 (SME feature ID) -ID_AA64AFR0_EL1 :: i64(0x402C) // 3 0 0 5 4 (auxiliary) -ID_AA64AFR1_EL1 :: i64(0x402D) // 3 0 0 5 5 - -// ----------------------------------------------------------------------------- -// Cache hierarchy + selection -// ----------------------------------------------------------------------------- -CCSIDR_EL1 :: i64(0x4800) // 3 1 0 0 0 -CLIDR_EL1 :: i64(0x4801) // 3 1 0 0 1 -CSSELR_EL1 :: i64(0x5000) // 3 2 0 0 0 - -// ----------------------------------------------------------------------------- -// EL2 / EL3 control + return registers -// ----------------------------------------------------------------------------- -SCTLR_EL2 :: i64(0x6080) // 3 4 1 0 0 -SCTLR_EL3 :: i64(0x7080) // 3 6 1 0 0 -SPSR_EL3 :: i64(0x7200) // 3 6 4 0 0 -ELR_EL3 :: i64(0x7201) // 3 6 4 0 1 -TPIDR_EL2 :: i64(0x6682) // 3 4 13 0 2 -TPIDR_EL3 :: i64(0x7682) // 3 6 13 0 2 -- err, EL3 needs op1=6 -HSTR_EL2 :: i64(0x608B) // 3 4 1 1 3 -MDCR_EL2 :: i64(0x6089) // 3 4 1 1 1 -CNTHCTL_EL2 :: i64(0x6708) // 3 4 14 1 0 -DACR32_EL2 :: i64(0x6180) // 3 4 3 0 0 -FPEXC32_EL2 :: i64(0x6298) // 3 4 5 3 0 -VBAR_EL2 :: i64(0x6600) // 3 4 12 0 0 -VBAR_EL3 :: i64(0x7600) // 3 6 12 0 0 -TPIDR2_EL0 :: i64(0x5E85) // 3 3 13 0 5 (SME thread pointer 2) - -// ----------------------------------------------------------------------------- -// Debug registers (op0 = 2) -// ----------------------------------------------------------------------------- -MDSCR_EL1 :: i64(0x0012) // 2 0 0 2 2 -DSPSR_EL0 :: i64(0x5A28) // 3 3 4 5 0 -DLR_EL0 :: i64(0x5A29) // 3 3 4 5 1 -OSLAR_EL1 :: i64(0x0084) // 2 0 1 0 4 (op0=2 -> o0=0) -OSLSR_EL1 :: i64(0x008C) // 2 0 1 1 4 - -// ----------------------------------------------------------------------------- -// Cache / Memory feature extras -// ----------------------------------------------------------------------------- -RGSR_EL1 :: i64(0x4085) // 3 0 1 0 5 (FEAT_MTE) -GCR_EL1 :: i64(0x4086) // 3 0 1 0 6 (FEAT_MTE) -TFSR_EL1 :: i64(0x42B0) // 3 0 5 6 0 (FEAT_MTE) -TFSRE0_EL1 :: i64(0x42B1) // 3 0 5 6 1 (FEAT_MTE) -GMID_EL1 :: i64(0x4804) // 3 1 0 0 4 (FEAT_MTE) - -// ----------------------------------------------------------------------------- -// SME / SVE configuration -// ----------------------------------------------------------------------------- -SVCR :: i64(0x5A12) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) -SMCR_EL1 :: i64(0x4096) // 3 0 1 2 6 (FEAT_SME) -SMCR_EL2 :: i64(0x6096) // 3 4 1 2 6 -ZCR_EL1 :: i64(0x4090) // 3 0 1 2 0 (FEAT_SVE) -ZCR_EL2 :: i64(0x6090) // 3 4 1 2 0 -ZCR_EL3 :: i64(0x7090) // 3 6 1 2 0 - -// ----------------------------------------------------------------------------- -// Cache / data prefetch hint controls -// ----------------------------------------------------------------------------- -PRSELR_EL1 :: i64(0x4311) // 3 0 6 2 1 -APIAKEYLO_EL1 :: i64(0x4108) // 3 0 2 1 0 (FEAT_PAuth) -APIAKEYHI_EL1 :: i64(0x4109) // 3 0 2 1 1 -APIBKEYLO_EL1 :: i64(0x410A) // 3 0 2 1 2 -APIBKEYHI_EL1 :: i64(0x410B) // 3 0 2 1 3 -APDAKEYLO_EL1 :: i64(0x4110) // 3 0 2 2 0 -APDAKEYHI_EL1 :: i64(0x4111) // 3 0 2 2 1 -APDBKEYLO_EL1 :: i64(0x4112) // 3 0 2 2 2 -APDBKEYHI_EL1 :: i64(0x4113) // 3 0 2 2 3 -APGAKEYLO_EL1 :: i64(0x4118) // 3 0 2 3 0 -APGAKEYHI_EL1 :: i64(0x4119) // 3 0 2 3 1 - -// ============================================================================= -// Batch 5: comprehensive sysreg sweep -// ============================================================================= - -// ---- More ID registers (AArch32 + extras) ---- -ID_AA64DFR2_EL1 :: i64(0x402A) // 3 0 0 5 2 -ID_AA64ISAR3_EL1 :: i64(0x4033) // 3 0 0 6 3 -ID_PFR0_EL1 :: i64(0x4008) // 3 0 0 1 0 -ID_PFR1_EL1 :: i64(0x4009) // 3 0 0 1 1 -ID_DFR0_EL1 :: i64(0x400A) // 3 0 0 1 2 -ID_AFR0_EL1 :: i64(0x400B) // 3 0 0 1 3 -ID_MMFR0_EL1 :: i64(0x400C) // 3 0 0 1 4 -ID_MMFR1_EL1 :: i64(0x400D) // 3 0 0 1 5 -ID_MMFR2_EL1 :: i64(0x400E) // 3 0 0 1 6 -ID_MMFR3_EL1 :: i64(0x400F) // 3 0 0 1 7 -ID_MMFR4_EL1 :: i64(0x4016) // 3 0 0 2 6 -ID_MMFR5_EL1 :: i64(0x401E) // 3 0 0 3 6 -ID_ISAR0_EL1 :: i64(0x4010) // 3 0 0 2 0 -ID_ISAR1_EL1 :: i64(0x4011) // 3 0 0 2 1 -ID_ISAR2_EL1 :: i64(0x4012) // 3 0 0 2 2 -ID_ISAR3_EL1 :: i64(0x4013) // 3 0 0 2 3 -ID_ISAR4_EL1 :: i64(0x4014) // 3 0 0 2 4 -ID_ISAR5_EL1 :: i64(0x4015) // 3 0 0 2 5 -ID_ISAR6_EL1 :: i64(0x4017) // 3 0 0 2 7 -ID_PFR2_EL1 :: i64(0x401C) // 3 0 0 3 4 -MVFR0_EL1 :: i64(0x4018) // 3 0 0 3 0 -MVFR1_EL1 :: i64(0x4019) // 3 0 0 3 1 -MVFR2_EL1 :: i64(0x401A) // 3 0 0 3 2 - -// ---- Counter / Timer (full set) ---- -CNTKCTL_EL1 :: i64(0x4708) // 3 0 14 1 0 -CNTP_TVAL_EL0 :: i64(0x5F10) // 3 3 14 2 0 -CNTP_CTL_EL0 :: i64(0x5F11) // 3 3 14 2 1 -CNTP_CVAL_EL0 :: i64(0x5F12) // 3 3 14 2 2 -CNTV_TVAL_EL0 :: i64(0x5F18) // 3 3 14 3 0 -CNTV_CTL_EL0 :: i64(0x5F19) // 3 3 14 3 1 -CNTV_CVAL_EL0 :: i64(0x5F1A) // 3 3 14 3 2 -CNTHP_TVAL_EL2 :: i64(0x6710) // 3 4 14 2 0 -CNTHP_CTL_EL2 :: i64(0x6711) // 3 4 14 2 1 -CNTHP_CVAL_EL2 :: i64(0x6712) // 3 4 14 2 2 -CNTHV_TVAL_EL2 :: i64(0x6718) // 3 4 14 3 0 -CNTHV_CTL_EL2 :: i64(0x6719) // 3 4 14 3 1 -CNTHV_CVAL_EL2 :: i64(0x671A) // 3 4 14 3 2 -CNTPS_TVAL_EL1 :: i64(0x7F10) // 3 7 14 2 0 -CNTPS_CTL_EL1 :: i64(0x7F11) // 3 7 14 2 1 -CNTPS_CVAL_EL1 :: i64(0x7F12) // 3 7 14 2 2 -CNTVOFF_EL2 :: i64(0x6703) // 3 4 14 0 3 - -// ---- Debug breakpoints (DBGB*) and watchpoints (DBGW*), numbered ---- -// -// Each register file is 16 deep: DBGBVR0..15, DBGBCR0..15, DBGWVR0..15, -// DBGWCR0..15. Use the helper: -// sysreg_debug_breakpoint_value(n) -- DBGBVRn_EL1 = (2, 0, 0, n, 4) -// sysreg_debug_breakpoint_control(n) -- DBGBCRn_EL1 = (2, 0, 0, n, 5) -// sysreg_debug_watchpoint_value(n) -- DBGWVRn_EL1 = (2, 0, 0, n, 6) -// sysreg_debug_watchpoint_control(n) -- DBGWCRn_EL1 = (2, 0, 0, n, 7) - -sysreg_debug_breakpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 4) -} -sysreg_debug_breakpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 5) -} -sysreg_debug_watchpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 6) -} -sysreg_debug_watchpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 7) -} - -// Other debug registers -DBGDTR_EL0 :: i64(0x1820) // 2 3 0 4 0 -DBGDTRRX_EL0 :: i64(0x1828) // 2 3 0 5 0 -DBGDTRTX_EL0 :: i64(0x1828) // 2 3 0 5 0 (write view of DBGDTRRX_EL0) -DBGPRCR_EL1 :: i64(0x00A4) // 2 0 1 4 4 -DBGCLAIMSET_EL1 :: i64(0x03C6) // 2 0 7 8 6 -DBGCLAIMCLR_EL1 :: i64(0x03CE) // 2 0 7 9 6 -DBGAUTHSTATUS_EL1:: i64(0x03F6) // 2 0 7 14 6 -MDCCINT_EL1 :: i64(0x0010) // 2 0 0 2 0 -MDRAR_EL1 :: i64(0x0080) // 2 0 1 0 0 - -// PMU event counters (PMEVCNTRn_EL0 / PMEVTYPERn_EL0). Up to n=30. -// PMEVCNTRn_EL0 = sysreg(3, 3, 14, 8+(n>>3), n & 7) -// PMEVTYPERn_EL0 = sysreg(3, 3, 14, 12+(n>>3), n & 7) - -sysreg_pmu_event_counter :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 3, 14, 8 + ((n >> 3) & 0x3), n & 0x7) -} -sysreg_pmu_event_typer :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 3, 14, 12 + ((n >> 3) & 0x3), n & 0x7) -} - -PMINTENSET_EL1 :: i64(0x44F1) // 3 0 9 14 1 -PMINTENCLR_EL1 :: i64(0x44F2) // 3 0 9 14 2 - -// ---- GICv3 (ICC_*) -- CPU interface ---- -ICC_IAR0_EL1 :: i64(0x4640) // 3 0 12 8 0 -ICC_IAR1_EL1 :: i64(0x4660) // 3 0 12 12 0 -ICC_EOIR0_EL1 :: i64(0x4641) // 3 0 12 8 1 -ICC_EOIR1_EL1 :: i64(0x4661) // 3 0 12 12 1 -ICC_HPPIR0_EL1 :: i64(0x4642) // 3 0 12 8 2 -ICC_HPPIR1_EL1 :: i64(0x4662) // 3 0 12 12 2 -ICC_BPR0_EL1 :: i64(0x4643) // 3 0 12 8 3 -ICC_BPR1_EL1 :: i64(0x4663) // 3 0 12 12 3 -ICC_DIR_EL1 :: i64(0x4659) // 3 0 12 11 1 -ICC_PMR_EL1 :: i64(0x4230) // 3 0 4 6 0 -ICC_RPR_EL1 :: i64(0x465B) // 3 0 12 11 3 -ICC_SGI0R_EL1 :: i64(0x465F) // 3 0 12 11 7 -ICC_SGI1R_EL1 :: i64(0x465D) // 3 0 12 11 5 -ICC_ASGI1R_EL1 :: i64(0x465E) // 3 0 12 11 6 -ICC_SRE_EL1 :: i64(0x4665) // 3 0 12 12 5 -ICC_SRE_EL2 :: i64(0x664D) // 3 4 12 9 5 -ICC_SRE_EL3 :: i64(0x7665) // 3 6 12 12 5 -ICC_CTLR_EL1 :: i64(0x4664) // 3 0 12 12 4 -ICC_CTLR_EL3 :: i64(0x7664) // 3 6 12 12 4 -ICC_IGRPEN0_EL1 :: i64(0x4666) // 3 0 12 12 6 -ICC_IGRPEN1_EL1 :: i64(0x4667) // 3 0 12 12 7 -ICC_IGRPEN1_EL3 :: i64(0x7667) // 3 6 12 12 7 - -// ---- GICv3 hypervisor (ICH_*) ---- -ICH_HCR_EL2 :: i64(0x6658) // 3 4 12 11 0 -ICH_VTR_EL2 :: i64(0x6659) // 3 4 12 11 1 -ICH_MISR_EL2 :: i64(0x665A) // 3 4 12 11 2 -ICH_EISR_EL2 :: i64(0x665B) // 3 4 12 11 3 -ICH_ELRSR_EL2 :: i64(0x665D) // 3 4 12 11 5 -ICH_VMCR_EL2 :: i64(0x665F) // 3 4 12 11 7 - -// ICH_LR0_EL2 .. ICH_LR15_EL2 = sysreg(3, 4, 12, 12+(n>>3), n & 7) -sysreg_ich_lr :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 12 + ((n >> 3) & 0x1), n & 0x7) -} - -// ICH_AP0Rn_EL2 (n=0..3) and ICH_AP1Rn_EL2 (n=0..3) -sysreg_ich_ap0r :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 8, n & 0x3) -} -sysreg_ich_ap1r :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 9, n & 0x3) -} - -// ---- TRBE (Trace Buffer Extension, FEAT_TRBE) ---- -TRBLIMITR_EL1 :: i64(0x44D8) // 3 0 9 11 0 -TRBPTR_EL1 :: i64(0x44D9) // 3 0 9 11 1 -TRBBASER_EL1 :: i64(0x44DA) // 3 0 9 11 2 -TRBSR_EL1 :: i64(0x44DB) // 3 0 9 11 3 -TRBMAR_EL1 :: i64(0x44DC) // 3 0 9 11 4 -TRBTRG_EL1 :: i64(0x44DE) // 3 0 9 11 6 -TRBIDR_EL1 :: i64(0x44DF) // 3 0 9 11 7 - -// ---- SPE (Statistical Profiling Extension, FEAT_SPE) ---- -PMSCR_EL1 :: i64(0x44C8) // 3 0 9 9 0 -PMSICR_EL1 :: i64(0x44CA) // 3 0 9 9 2 -PMSIRR_EL1 :: i64(0x44CB) // 3 0 9 9 3 -PMSFCR_EL1 :: i64(0x44CC) // 3 0 9 9 4 -PMSEVFR_EL1 :: i64(0x44CD) // 3 0 9 9 5 -PMSLATFR_EL1 :: i64(0x44CE) // 3 0 9 9 6 -PMSIDR_EL1 :: i64(0x44CF) // 3 0 9 9 7 -PMBLIMITR_EL1 :: i64(0x44D0) // 3 0 9 10 0 -PMBPTR_EL1 :: i64(0x44D1) // 3 0 9 10 1 -PMBSR_EL1 :: i64(0x44D3) // 3 0 9 10 3 -PMBIDR_EL1 :: i64(0x44D7) // 3 0 9 10 7 - -// ---- RAS (Reliability, Availability, Serviceability) ---- -ERRSELR_EL1 :: i64(0x4299) // 3 0 5 3 1 -ERRIDR_EL1 :: i64(0x4298) // 3 0 5 3 0 -ERXADDR_EL1 :: i64(0x42A3) // 3 0 5 4 3 -ERXCTLR_EL1 :: i64(0x42A1) // 3 0 5 4 1 -ERXFR_EL1 :: i64(0x42A0) // 3 0 5 4 0 -ERXSTATUS_EL1 :: i64(0x42A2) // 3 0 5 4 2 -ERXMISC0_EL1 :: i64(0x42A8) // 3 0 5 5 0 -ERXMISC1_EL1 :: i64(0x42A9) // 3 0 5 5 1 -ERXMISC2_EL1 :: i64(0x42AA) // 3 0 5 5 2 -ERXMISC3_EL1 :: i64(0x42AB) // 3 0 5 5 3 -DISR_EL1 :: i64(0x4609) // 3 0 12 1 1 -VDISR_EL2 :: i64(0x6609) // 3 4 12 1 1 -VSESR_EL2 :: i64(0x6293) // 3 4 5 2 3 - -// ---- LOR (Limited Ordering Region) ---- -LORC_EL1 :: i64(0x4523) // 3 0 10 4 3 -LOREA_EL1 :: i64(0x4521) // 3 0 10 4 1 -LORID_EL1 :: i64(0x4527) // 3 0 10 4 7 -LORN_EL1 :: i64(0x4522) // 3 0 10 4 2 -LORSA_EL1 :: i64(0x4520) // 3 0 10 4 0 - -// ---- Translation result (returned by AT) ---- -PAR_EL1 :: i64(0x43A0) // 3 0 7 4 0 - -// ---- RME (Realm Management Extension) sysregs ---- -GPCCR_EL3 :: i64(0x710E) // 3 6 2 1 6 (Granule Protection Control) -GPTBR_EL3 :: i64(0x710C) // 3 6 2 1 4 (Granule Protection Table Base) -MFAR_EL3 :: i64(0x7305) // 3 6 6 0 5 (Multiple FAR) - -// ---- TPIDRRO_EL0 alias / extra thread pointers ---- -// (TPIDRRO_EL0 already added above) - -// ---- Performance Monitor extras ---- -PMCCFILTR_EL0 :: i64(0x5F7F) // 3 3 14 15 7 -PMUSERENR_EL0_REPEAT :: PMUSERENR_EL0 // re-export alias placeholder - -// ----------------------------------------------------------------------------- -// Value -> name, for printing -// ----------------------------------------------------------------------------- -// -// MRS/MSR carry the system register as a packed 15-bit field, so a disassembly -// has a number where an assembler wants a name. Sorted by value; binary search. -// -// 1 encodings carry two names. Where the pair is a read view and a write -// view of one register (DBGDTRRX/DBGDTRTX) the read name wins, since MRS is -// the direction that has to print; the rest are genuine aliases and either -// name assembles, so a round-trip can come back spelled as the sibling. - -Sysreg_Name :: struct { - value: u16, - name: string, -} - -@(rodata) -SYSREG_NAMES := [?]Sysreg_Name{ - {0x0010, "mdccint_el1"}, - {0x0012, "mdscr_el1"}, - {0x0080, "mdrar_el1"}, - {0x0084, "oslar_el1"}, - {0x008C, "oslsr_el1"}, - {0x00A4, "dbgprcr_el1"}, - {0x03C6, "dbgclaimset_el1"}, - {0x03CE, "dbgclaimclr_el1"}, - {0x03F6, "dbgauthstatus_el1"}, - {0x1820, "dbgdtr_el0"}, - {0x1828, "dbgdtrrx_el0"}, - {0x4000, "midr_el1"}, - {0x4005, "mpidr_el1"}, - {0x4008, "id_pfr0_el1"}, - {0x4009, "id_pfr1_el1"}, - {0x400A, "id_dfr0_el1"}, - {0x400B, "id_afr0_el1"}, - {0x400C, "id_mmfr0_el1"}, - {0x400D, "id_mmfr1_el1"}, - {0x400E, "id_mmfr2_el1"}, - {0x400F, "id_mmfr3_el1"}, - {0x4010, "id_isar0_el1"}, - {0x4011, "id_isar1_el1"}, - {0x4012, "id_isar2_el1"}, - {0x4013, "id_isar3_el1"}, - {0x4014, "id_isar4_el1"}, - {0x4015, "id_isar5_el1"}, - {0x4016, "id_mmfr4_el1"}, - {0x4017, "id_isar6_el1"}, - {0x4018, "mvfr0_el1"}, - {0x4019, "mvfr1_el1"}, - {0x401A, "mvfr2_el1"}, - {0x401C, "id_pfr2_el1"}, - {0x401E, "id_mmfr5_el1"}, - {0x4020, "id_aa64pfr0_el1"}, - {0x4021, "id_aa64pfr1_el1"}, - {0x4024, "id_aa64zfr0_el1"}, - {0x4025, "id_aa64smfr0_el1"}, - {0x4028, "id_aa64dfr0_el1"}, - {0x4029, "id_aa64dfr1_el1"}, - {0x402A, "id_aa64dfr2_el1"}, - {0x402C, "id_aa64afr0_el1"}, - {0x402D, "id_aa64afr1_el1"}, - {0x4030, "id_aa64isar0_el1"}, - {0x4031, "id_aa64isar1_el1"}, - {0x4032, "id_aa64isar2_el1"}, - {0x4033, "id_aa64isar3_el1"}, - {0x4038, "id_aa64mmfr0_el1"}, - {0x4039, "id_aa64mmfr1_el1"}, - {0x403A, "id_aa64mmfr2_el1"}, - {0x4080, "sctlr_el1"}, - {0x4081, "actlr_el1"}, - {0x4082, "cpacr_el1"}, - {0x4085, "rgsr_el1"}, - {0x4086, "gcr_el1"}, - {0x4090, "zcr_el1"}, - {0x4096, "smcr_el1"}, - {0x4100, "ttbr0_el1"}, - {0x4101, "ttbr1_el1"}, - {0x4102, "tcr_el1"}, - {0x4108, "apiakeylo_el1"}, - {0x4109, "apiakeyhi_el1"}, - {0x410A, "apibkeylo_el1"}, - {0x410B, "apibkeyhi_el1"}, - {0x4110, "apdakeylo_el1"}, - {0x4111, "apdakeyhi_el1"}, - {0x4112, "apdbkeylo_el1"}, - {0x4113, "apdbkeyhi_el1"}, - {0x4118, "apgakeylo_el1"}, - {0x4119, "apgakeyhi_el1"}, - {0x4200, "spsr_el1"}, - {0x4201, "elr_el1"}, - {0x4208, "sp_el0"}, - {0x4212, "currentel"}, - {0x4230, "icc_pmr_el1"}, - {0x4288, "afsr0_el1"}, - {0x4289, "afsr1_el1"}, - {0x4290, "esr_el1"}, - {0x4298, "erridr_el1"}, - {0x4299, "errselr_el1"}, - {0x42A0, "erxfr_el1"}, - {0x42A1, "erxctlr_el1"}, - {0x42A2, "erxstatus_el1"}, - {0x42A3, "erxaddr_el1"}, - {0x42A8, "erxmisc0_el1"}, - {0x42A9, "erxmisc1_el1"}, - {0x42AA, "erxmisc2_el1"}, - {0x42AB, "erxmisc3_el1"}, - {0x42B0, "tfsr_el1"}, - {0x42B1, "tfsre0_el1"}, - {0x4300, "far_el1"}, - {0x4311, "prselr_el1"}, - {0x43A0, "par_el1"}, - {0x44C8, "pmscr_el1"}, - {0x44CA, "pmsicr_el1"}, - {0x44CB, "pmsirr_el1"}, - {0x44CC, "pmsfcr_el1"}, - {0x44CD, "pmsevfr_el1"}, - {0x44CE, "pmslatfr_el1"}, - {0x44CF, "pmsidr_el1"}, - {0x44D0, "pmblimitr_el1"}, - {0x44D1, "pmbptr_el1"}, - {0x44D3, "pmbsr_el1"}, - {0x44D7, "pmbidr_el1"}, - {0x44D8, "trblimitr_el1"}, - {0x44D9, "trbptr_el1"}, - {0x44DA, "trbbaser_el1"}, - {0x44DB, "trbsr_el1"}, - {0x44DC, "trbmar_el1"}, - {0x44DE, "trbtrg_el1"}, - {0x44DF, "trbidr_el1"}, - {0x44F1, "pmintenset_el1"}, - {0x44F2, "pmintenclr_el1"}, - {0x4510, "mair_el1"}, - {0x4518, "amair_el1"}, - {0x4520, "lorsa_el1"}, - {0x4521, "lorea_el1"}, - {0x4522, "lorn_el1"}, - {0x4523, "lorc_el1"}, - {0x4527, "lorid_el1"}, - {0x4600, "vbar_el1"}, - {0x4608, "isr_el1"}, - {0x4609, "disr_el1"}, - {0x4640, "icc_iar0_el1"}, - {0x4641, "icc_eoir0_el1"}, - {0x4642, "icc_hppir0_el1"}, - {0x4643, "icc_bpr0_el1"}, - {0x4659, "icc_dir_el1"}, - {0x465B, "icc_rpr_el1"}, - {0x465D, "icc_sgi1r_el1"}, - {0x465E, "icc_asgi1r_el1"}, - {0x465F, "icc_sgi0r_el1"}, - {0x4660, "icc_iar1_el1"}, - {0x4661, "icc_eoir1_el1"}, - {0x4662, "icc_hppir1_el1"}, - {0x4663, "icc_bpr1_el1"}, - {0x4664, "icc_ctlr_el1"}, - {0x4665, "icc_sre_el1"}, - {0x4666, "icc_igrpen0_el1"}, - {0x4667, "icc_igrpen1_el1"}, - {0x4681, "contextidr_el1"}, - {0x4684, "tpidr_el1"}, - {0x4708, "cntkctl_el1"}, - {0x4800, "ccsidr_el1"}, - {0x4801, "clidr_el1"}, - {0x4804, "gmid_el1"}, - {0x5000, "csselr_el1"}, - {0x5801, "ctr_el0"}, - {0x5807, "dczid_el0"}, - {0x5920, "rndr"}, - {0x5921, "rndrrs"}, - {0x5A10, "nzcv"}, - {0x5A11, "daif"}, - {0x5A12, "svcr"}, - {0x5A20, "fpcr"}, - {0x5A21, "fpsr"}, - {0x5A28, "dspsr_el0"}, - {0x5A29, "dlr_el0"}, - {0x5CE0, "pmcr_el0"}, - {0x5CE1, "pmcntenset_el0"}, - {0x5CE2, "pmcntenclr_el0"}, - {0x5CE3, "pmovsclr_el0"}, - {0x5CE4, "pmswinc_el0"}, - {0x5CE5, "pmselr_el0"}, - {0x5CE6, "pmceid0_el0"}, - {0x5CE7, "pmceid1_el0"}, - {0x5CE8, "pmccntr_el0"}, - {0x5CF0, "pmuserenr_el0"}, - {0x5E82, "tpidr_el0"}, - {0x5E83, "tpidrro_el0"}, - {0x5E85, "tpidr2_el0"}, - {0x5F00, "cntfrq_el0"}, - {0x5F01, "cntpct_el0"}, - {0x5F02, "cntvct_el0"}, - {0x5F10, "cntp_tval_el0"}, - {0x5F11, "cntp_ctl_el0"}, - {0x5F12, "cntp_cval_el0"}, - {0x5F18, "cntv_tval_el0"}, - {0x5F19, "cntv_ctl_el0"}, - {0x5F1A, "cntv_cval_el0"}, - {0x5F7F, "pmccfiltr_el0"}, - {0x6080, "sctlr_el2"}, - {0x6088, "hcr_el2"}, - {0x6089, "mdcr_el2"}, - {0x608B, "hstr_el2"}, - {0x6090, "zcr_el2"}, - {0x6096, "smcr_el2"}, - {0x6108, "vttbr_el2"}, - {0x610A, "vtcr_el2"}, - {0x6180, "dacr32_el2"}, - {0x6200, "spsr_el2"}, - {0x6201, "elr_el2"}, - {0x6208, "sp_el1"}, - {0x6290, "esr_el2"}, - {0x6293, "vsesr_el2"}, - {0x6298, "fpexc32_el2"}, - {0x6300, "far_el2"}, - {0x6600, "vbar_el2"}, - {0x6609, "vdisr_el2"}, - {0x664D, "icc_sre_el2"}, - {0x6658, "ich_hcr_el2"}, - {0x6659, "ich_vtr_el2"}, - {0x665A, "ich_misr_el2"}, - {0x665B, "ich_eisr_el2"}, - {0x665D, "ich_elrsr_el2"}, - {0x665F, "ich_vmcr_el2"}, - {0x6682, "tpidr_el2"}, - {0x6703, "cntvoff_el2"}, - {0x6708, "cnthctl_el2"}, - {0x6710, "cnthp_tval_el2"}, - {0x6711, "cnthp_ctl_el2"}, - {0x6712, "cnthp_cval_el2"}, - {0x6718, "cnthv_tval_el2"}, - {0x6719, "cnthv_ctl_el2"}, - {0x671A, "cnthv_cval_el2"}, - {0x7080, "sctlr_el3"}, - {0x7090, "zcr_el3"}, - {0x710C, "gptbr_el3"}, - {0x710E, "gpccr_el3"}, - {0x7200, "spsr_el3"}, - {0x7201, "elr_el3"}, - {0x7305, "mfar_el3"}, - {0x7600, "vbar_el3"}, - {0x7664, "icc_ctlr_el3"}, - {0x7665, "icc_sre_el3"}, - {0x7667, "icc_igrpen1_el3"}, - {0x7682, "tpidr_el3"}, - {0x7F10, "cntps_tval_el1"}, - {0x7F11, "cntps_ctl_el1"}, - {0x7F12, "cntps_cval_el1"}, -} - -// Name for a packed system-register field, or ok=false when it is not one we -// know -- callers should fall back to printing the raw immediate. -@(require_results) -sysreg_name :: proc "contextless" (value: i64) -> (name: string, ok: bool) { - v := u16(value & 0x7FFF) - lo, hi := 0, len(SYSREG_NAMES) - 1 - for lo <= hi { - mid := (lo + hi) / 2 - e := SYSREG_NAMES[mid] - switch { - case e.value == v: return e.name, true - case e.value < v: lo = mid + 1 - case: hi = mid - 1 - } - } - return "", false -} From dcaab1aa8501b75c19f3b2ee908547ac2facabc0 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 09:59:15 -0400 Subject: [PATCH 32/89] rexcode/arm64: system registers get a type instead of being bare i64 They were plain i64 constants handed to op_imm, so any integer typed as one and `inst_mrs(X0, 999999)` compiled fine. Worse, the printer could not tell a system register from an immediate and had to recover the distinction by mnemonic and slot -- MSR's other form holds a PSTATE field selector in the same position, so it keyed off whether operand 1 was a register. System_Register is now its own type with its own Operand_Kind, union member and op_sysreg constructor, exactly as Cond is. The printer's slot logic is gone: the operand knows what it is, so naming it is a case in the same switch that prints every other operand kind. MSR's PSTATE selector is typed PSTATE_FIELD, which is what it always was. It cannot join `Register` itself: that is a u16 with the class in its high byte, leaving 8 bits for the number, and a system register needs 15. Widening it would break `Memory`, which packs two registers plus a displacement and a mode into exactly 64 bits. The constants are also reorganised. They had accreted into overlapping sections -- two "ID registers" groups, three cache groups, a "Batch 5: comprehensive sysreg sweep" banner, and a "hmm let me recompute" note left in a comment. All 231 are now grouped by architectural function (18 groups, alphabetical within each) with their five fields aligned. Verified unchanged against llvm-mc: 222 registers byte-exact through MRS, 8 write-only through MSR, and the PSTATE form still decodes as an immediate rather than a register. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 2 +- core/rexcode/isa/arm64/encoder.odin | 8 +- core/rexcode/isa/arm64/encoding_types.odin | 4 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 16 +- core/rexcode/isa/arm64/operands.odin | 6 + core/rexcode/isa/arm64/printer.odin | 25 +- core/rexcode/isa/arm64/registers.odin | 670 +++++++++--------- .../tablegen/generated/decode_tables.odin | 2 +- .../tablegen/generated/encode_tables.odin | 2 +- .../isa/arm64/tablegen/instruction_table.odin | 2 +- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49920 -> 49920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49960 -> 49960 bytes .../isa/arm64/tests/pipeline_smoke.odin | 12 +- .../arm64/tools/gen_mnemonic_builders.odin | 17 +- 14 files changed, 375 insertions(+), 391 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 057065941..2784cc8f2 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -203,7 +203,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .NZCV_FIELD: return Operand{immediate = i64(word & 0xF), kind = .IMMEDIATE, size = 1} case .SYS_FIELD: - return Operand{immediate = i64((word >> 5) & 0x7FFF), kind = .IMMEDIATE, size = 2} + return Operand{sysreg = System_Register((word >> 5) & 0x7FFF), kind = .SYSTEM_REGISTER, size = 2} case .HINT_FIELD: return Operand{immediate = i64((word >> 5) & 0x7F), kind = .IMMEDIATE, size = 1} case .BARRIER_FIELD: diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 5c567489d..d7b5fecab 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -277,8 +277,10 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .IMMEDIATE case .IMM_12, .IMM_16, .IMM_8, .IMM_6, .IMM_5, .IMM_4, .IMM_3, .IMM_2, - .NZCV_IMM, .SYS_REG, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX: + .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX: return op.kind == .IMMEDIATE + case .SYS_REG: + return op.kind == .SYSTEM_REGISTER case .BITMASK_IMM: // The user passes the raw logical mask value; we validate that it // fits the AArch64 bitmask-immediate encoding at the form's width. @@ -390,7 +392,7 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.extended.reg)) & 0x1F) << 16 | (u32(op.extended.extend) & 0x7) << 13 | (u32(op.extended.amount) & 0x7) << 10 - case .NONE, .IMMEDIATE, .MEMORY, .RELATIVE, .COND: + case .NONE, .IMMEDIATE, .MEMORY, .RELATIVE, .COND, .SYSTEM_REGISTER: return 0 } @@ -417,7 +419,7 @@ pack_operand_inline :: #force_inline proc( case .NZCV_FIELD: return (u32(op.immediate) & 0xF) << 0 case .SYS_FIELD: - return (u32(op.immediate) & 0x7FFF) << 5 + return (u32(op.sysreg) & 0x7FFF) << 5 case .HINT_FIELD: return (u32(op.immediate) & 0x7F) << 5 case .BARRIER_FIELD: diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index a4fe99f41..46d6e8495 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -150,7 +150,9 @@ Operand_Type :: enum u8 { IMM_4, // 4-bit (HINT, DMB/DSB barrier types, NZCV flags) IMM_2, // 2-bit (FP rounding mode / NEON cmode bits 14:13 etc.) NZCV_IMM, // 4-bit NZCV for CCMP/CCMN immediate forms - SYS_REG, // 16-bit system register encoding (MSR/MRS) + SYS_REG, // MRS/MSR target system register + PSTATE_FIELD, // MSR immediate form: a PSTATE field selector, + // a different namespace from the system registers HW_SHIFT, // 2-bit LSL hw (0/16/32/48) for MOV-immediate BITMASK_IMM, // Logical immediate (bitmask-encoded N:imms:immr) LSE_SIZE, // 2-bit size selector for LSE atomics (00=B 01=H 10=W 11=X) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 113adcf76..8557d62f2 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -345,12 +345,12 @@ inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } -inst_mrs_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MRS, dst, imm) } -emit_mrs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_i(dst, imm)) } +inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}}} } +emit_mrs_r_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, sysreg: System_Register) { append(instructions, inst_mrs_r_s(dst, sysreg)) } inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } -inst_msr_i_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_reg(src), {}, {}}} } +inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}}} } emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } -emit_msr_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_i_r(imm, src)) } +emit_msr_s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, sysreg: System_Register, src: Register) { append(instructions, inst_msr_s_r(sysreg, src)) } inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } @@ -2216,10 +2216,10 @@ inst_sevl :: inst_sevl_none emit_sevl :: emit_sevl_none inst_hint :: inst_hint_i emit_hint :: emit_hint_i -inst_mrs :: inst_mrs_r_i -emit_mrs :: emit_mrs_r_i -inst_msr :: proc{ inst_msr_i_i, inst_msr_i_r } -emit_msr :: proc{ emit_msr_i_i, emit_msr_i_r } +inst_mrs :: inst_mrs_r_s +emit_mrs :: emit_mrs_r_s +inst_msr :: proc{ inst_msr_i_i, inst_msr_s_r } +emit_msr :: proc{ emit_msr_i_i, emit_msr_s_r } inst_isb :: inst_isb_i emit_isb :: emit_isb_i inst_dsb :: inst_dsb_i diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index f1fee81db..86e20675e 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -28,6 +28,7 @@ Operand_Kind :: enum u8 { SHIFTED_REG, // X reg + shift type + shift amount EXTENDED_REG, // X/W reg + extend + amount COND, // 4-bit condition code (EQ/NE/.../AL/NV) + SYSTEM_REGISTER, // MRS/MSR target, as a packed 15-bit field } Shift_Type :: enum u8 { @@ -104,6 +105,7 @@ Operand :: struct #packed { shifted: Shifted_Reg, // 8 extended: Extended_Reg, // 8 cond: u8, // 1 + sysreg: System_Register, // 2 }, // 12 total because of alignment kind: Operand_Kind, // 1 size: u8, // 1 -- carried width info; meaning varies @@ -151,6 +153,10 @@ op_cond :: #force_inline proc "contextless" (c: Cond) -> Operand { return Operand{cond = u8(c), kind = .COND, size = 1} } +op_sysreg :: #force_inline proc "contextless" (sr: System_Register) -> Operand { + return Operand{sysreg = sr, kind = .SYSTEM_REGISTER, size = 2} +} + // ----------------------------------------------------------------------------- // SVE Z-register builders -- encode the element arrangement in op.size // (B=1, H=2, S=4, D=8). Matcher uses op.size to disambiguate the right diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 85d8c21c9..0e12ed44a 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -118,20 +118,6 @@ sbprint :: proc( // MOVZ/MOVN/MOVK store the shift as an hw index (0..3 = LSL #0/16/32/48), // which assemblers write as `lsl #16` and omit entirely when it is zero. - // MRS/MSR carry the system register as a packed field, so it has to be - // printed by name -- a bare number is not something an assembler takes. - // MSR's other form takes a PSTATE field selector in the same slot, - // which is a different namespace; it is the one whose second operand - // is an immediate rather than a register. - sysreg_slot, sysreg_ok := -1, false - #partial switch inst.mnemonic { - case .MRS: - sysreg_slot, sysreg_ok = 1, inst.operand_count >= 2 - case .MSR: - sysreg_slot = 0 - sysreg_ok = inst.operand_count >= 2 && inst.ops[1].kind == .REGISTER - } - mov_wide := inst.mnemonic == .MOVZ || inst.mnemonic == .MOVN || inst.mnemonic == .MOVK end_slot := int(inst.operand_count) if mov_wide && end_slot == 3 && inst.ops[2].kind == .IMMEDIATE && inst.ops[2].immediate == 0 { @@ -148,8 +134,6 @@ sbprint :: proc( if mov_wide && slot == 2 { strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) - } else if slot == sysreg_slot && sysreg_ok { - write_sysreg(sb, inst.ops[slot].immediate, opts.uppercase) } else { write_operand(sb, &inst.ops[slot], &display, opts) } @@ -359,11 +343,11 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { // A system register by name (`cntvct_el0`), falling back to the raw field // when it is not one we know. @(private="file") -write_sysreg :: proc(sb: ^strings.Builder, value: i64, uppercase: bool) { - name, ok := sysreg_name(value) +write_sysreg :: proc(sb: ^strings.Builder, sr: System_Register, uppercase: bool) { + name, ok := sysreg_name(sr) if !ok { strings.write_byte(sb, '#') - write_signed_decimal(sb, value) + write_signed_decimal(sb, i64(sr)) return } for i in 0 ..< len(name) { @@ -490,6 +474,9 @@ write_operand :: proc( strings.write_byte(sb, '#') write_signed_decimal(sb, op.immediate) + case .SYSTEM_REGISTER: + write_sysreg(sb, op.sysreg, opts.uppercase) + case .COND: c := op.cond & 0xF s := COND_NAMES[c] diff --git a/core/rexcode/isa/arm64/registers.odin b/core/rexcode/isa/arm64/registers.odin index 2ae17eaa1..10e6040d5 100644 --- a/core/rexcode/isa/arm64/registers.odin +++ b/core/rexcode/isa/arm64/registers.odin @@ -103,41 +103,41 @@ V28 :: Register(REG_V | 28); V29 :: Register(REG_V | 29); V30 :: Register(REG_V @(require_results) w_reg :: #force_inline proc "contextless" (n: u8) -> Register { return Register(REG_W | u16(n & 0x1F)) } // ============================================================================= -// AArch64 SYSTEM REGISTERS (named constants for MRS / MSR) +// AArch64 SYSTEM REGISTERS (MRS / MSR) // ============================================================================= // -// The MRS / MSR instructions encode the target system register as a 15-bit -// field at bits 19:5 of the instruction word: +// A system register does not fit `Register`: that is a u16 carrying the class +// in its high byte, which leaves 8 bits for the number, and a system register +// needs 15. Widening it is not free either -- `Memory` packs two of them plus +// a displacement and a mode into exactly 64 bits. So this is its own type +// alongside `Register`, the way `Cond` is, with its own Operand_Kind and its +// own `op_sysreg` constructor. // -// o0 (1 bit) : op0 - 2 (op0 = 2 -> o0=0; op0 = 3 -> o0=1) -// op1 (3 bit) : op1 -// CRn (4 bit) : CRn -// CRm (4 bit) : CRm -// op2 (3 bit) : op2 +// MRS / MSR name their target as a 15-bit field at bits 19:5 of the word, +// packed MSB-first as o0 || op1 || CRn || CRm || op2: // -// concatenated MSB-first: o0 || op1 || CRn || CRm || op2. +// o0 (1 bit) op0 - 2 (op0 = 2 -> 0, op0 = 3 -> 1) +// op1 (3 bits) +// CRn (4 bits) +// CRm (4 bits) +// op2 (3 bits) // -// Users pass these as the immediate operand to `inst_*` builders or by -// hand, e.g.: -// -// MRS X0, NZCV -> op_imm(arm64.NZCV, 2) -// -// The encoder packs the field into SYS_FIELD at bits 19:5 via the standard -// `(imm & 0x7FFF) << 5` mask, so callers can pass either the raw 15-bit -// field value (preferred) or the historical 0x_DA10-style 16-bit form -// (top bit gets masked off). +// Each constant below carries those five fields in its comment, and every +// value is verified byte-exact against llvm-mc. + +System_Register :: distinct u16 // ----------------------------------------------------------------------------- -// Helper for building sysreg field values at compile time. -// sysreg_field(op0, op1, CRn, CRm, op2) = packed 15-bit field -// op0 must be 2 or 3 (the o0 bit = op0 - 2). +// Build a field value from the five architectural numbers, for a register this +// list does not name. op0 must be 2 or 3. // ----------------------------------------------------------------------------- -sysreg_field :: #force_inline proc "contextless" (op0, op1, CRn, CRm, op2: u32) -> i64 { +@(require_results) +sysreg_field :: #force_inline proc "contextless" (op0, op1, CRn, CRm, op2: u16) -> System_Register { o0 := (op0 - 2) & 0x1 - return i64( + return System_Register( (o0 << 14) | - (op1 << 11) | + (op1 << 11) | (CRn << 7) | (CRm << 3) | op2, @@ -145,381 +145,357 @@ sysreg_field :: #force_inline proc "contextless" (op0, op1, CRn, CRm, op2: u32) } // ----------------------------------------------------------------------------- -// Commonly-used named registers (the ones every disassembler knows about). +// Process state, exceptions and stack pointers // ----------------------------------------------------------------------------- -// op0 op1 CRn CRm op2 -NZCV :: i64(0x5A10) // 3 3 4 2 0 -DAIF :: i64(0x5A11) // 3 3 4 2 1 -FPCR :: i64(0x5A20) // 3 3 4 4 0 -FPSR :: i64(0x5A21) // 3 3 4 4 1 -CURRENT_EL :: i64(0x4212) // 3 0 4 2 2 -SP_EL0 :: i64(0x4208) // 3 0 4 1 0 -SP_EL1 :: i64(0x6208) // 3 4 4 1 0 -ELR_EL1 :: i64(0x4201) // 3 0 4 0 1 -ELR_EL2 :: i64(0x6201) // 3 4 4 0 1 -SPSR_EL1 :: i64(0x4200) // 3 0 4 0 0 -SPSR_EL2 :: i64(0x6200) // 3 4 4 0 0 -ESR_EL1 :: i64(0x4290) // 3 0 5 2 0 -ESR_EL2 :: i64(0x6290) // 3 4 5 2 0 -FAR_EL1 :: i64(0x4300) // 3 0 6 0 0 -FAR_EL2 :: i64(0x6300) // 3 4 6 0 0 -TPIDR_EL0 :: i64(0x5E82) // 3 3 13 0 2 -TPIDRRO_EL0 :: i64(0x5E83) // 3 3 13 0 3 -TPIDR_EL1 :: i64(0x4684) // 3 0 13 0 4 (corrected: 3 0 13 0 4 -> 4684 hmm let me recompute) - -// Counters / system identity -CNTFRQ_EL0 :: i64(0x5F00) // 3 3 14 0 0 -CNTPCT_EL0 :: i64(0x5F01) // 3 3 14 0 1 -CNTVCT_EL0 :: i64(0x5F02) // 3 3 14 0 2 -MIDR_EL1 :: i64(0x4000) // 3 0 0 0 0 -MPIDR_EL1 :: i64(0x4005) // 3 0 0 0 5 -DCZID_EL0 :: i64(0x5807) // 3 3 0 0 7 (used by __sve_max_vl-style probes too) -CTR_EL0 :: i64(0x5801) // 3 3 0 0 1 -TCR_EL1 :: i64(0x4102) // 3 0 2 0 2 -SCTLR_EL1 :: i64(0x4080) // 3 0 1 0 0 -VBAR_EL1 :: i64(0x4600) // 3 0 12 0 0 -HCR_EL2 :: i64(0x6088) // 3 4 1 1 0 -TTBR0_EL1 :: i64(0x4100) // 3 0 2 0 0 -TTBR1_EL1 :: i64(0x4101) // 3 0 2 0 1 +// op0 op1 CRn CRm op2 +AFSR0_EL1 :: System_Register(0x4288) // 3 0 5 1 0 +AFSR1_EL1 :: System_Register(0x4289) // 3 0 5 1 1 +CURRENT_EL :: System_Register(0x4212) // 3 0 4 2 2 +DAIF :: System_Register(0x5A11) // 3 3 4 2 1 +ELR_EL1 :: System_Register(0x4201) // 3 0 4 0 1 +ELR_EL2 :: System_Register(0x6201) // 3 4 4 0 1 +ELR_EL3 :: System_Register(0x7201) // 3 6 4 0 1 +ESR_EL1 :: System_Register(0x4290) // 3 0 5 2 0 +ESR_EL2 :: System_Register(0x6290) // 3 4 5 2 0 +FAR_EL1 :: System_Register(0x4300) // 3 0 6 0 0 +FAR_EL2 :: System_Register(0x6300) // 3 4 6 0 0 +ISR_EL1 :: System_Register(0x4608) // 3 0 12 1 0 +NZCV :: System_Register(0x5A10) // 3 3 4 2 0 +SPSR_EL1 :: System_Register(0x4200) // 3 0 4 0 0 +SPSR_EL2 :: System_Register(0x6200) // 3 4 4 0 0 +SPSR_EL3 :: System_Register(0x7200) // 3 6 4 0 0 +SP_EL0 :: System_Register(0x4208) // 3 0 4 1 0 +SP_EL1 :: System_Register(0x6208) // 3 4 4 1 0 +VBAR_EL1 :: System_Register(0x4600) // 3 0 12 0 0 +VBAR_EL2 :: System_Register(0x6600) // 3 4 12 0 0 +VBAR_EL3 :: System_Register(0x7600) // 3 6 12 0 0 // ----------------------------------------------------------------------------- -// Identification registers (ID_AA64*_EL1) -- read-only feature bitmaps +// Floating-point control // ----------------------------------------------------------------------------- -ID_AA64ISAR0_EL1 :: i64(0x4030) // 3 0 0 6 0 -ID_AA64ISAR1_EL1 :: i64(0x4031) // 3 0 0 6 1 -ID_AA64ISAR2_EL1 :: i64(0x4032) // 3 0 0 6 2 -ID_AA64PFR0_EL1 :: i64(0x4020) // 3 0 0 4 0 -ID_AA64PFR1_EL1 :: i64(0x4021) // 3 0 0 4 1 -ID_AA64DFR0_EL1 :: i64(0x4028) // 3 0 0 5 0 -ID_AA64DFR1_EL1 :: i64(0x4029) // 3 0 0 5 1 -ID_AA64MMFR0_EL1 :: i64(0x4038) // 3 0 0 7 0 -ID_AA64MMFR1_EL1 :: i64(0x4039) // 3 0 0 7 1 -ID_AA64MMFR2_EL1 :: i64(0x403A) // 3 0 0 7 2 + +// op0 op1 CRn CRm op2 +FPCR :: System_Register(0x5A20) // 3 3 4 4 0 +FPSR :: System_Register(0x5A21) // 3 3 4 4 1 +MVFR0_EL1 :: System_Register(0x4018) // 3 0 0 3 0 +MVFR1_EL1 :: System_Register(0x4019) // 3 0 0 3 1 +MVFR2_EL1 :: System_Register(0x401A) // 3 0 0 3 2 // ----------------------------------------------------------------------------- -// Performance Monitor Unit (PMU) +// Thread and process identity // ----------------------------------------------------------------------------- -PMCR_EL0 :: i64(0x5CE0) // 3 3 9 12 0 -PMCNTENSET_EL0 :: i64(0x5CE1) // 3 3 9 12 1 -PMCNTENCLR_EL0 :: i64(0x5CE2) // 3 3 9 12 2 -PMOVSCLR_EL0 :: i64(0x5CE3) // 3 3 9 12 3 -PMSWINC_EL0 :: i64(0x5CE4) // 3 3 9 12 4 -PMSELR_EL0 :: i64(0x5CE5) // 3 3 9 12 5 -PMCEID0_EL0 :: i64(0x5CE6) // 3 3 9 12 6 -PMCEID1_EL0 :: i64(0x5CE7) // 3 3 9 12 7 -PMCCNTR_EL0 :: i64(0x5CE8) // 3 3 9 13 0 -PMUSERENR_EL0 :: i64(0x5CF0) // 3 3 9 14 0 + +// op0 op1 CRn CRm op2 +CONTEXTIDR_EL1 :: System_Register(0x4681) // 3 0 13 0 1 +TPIDR2_EL0 :: System_Register(0x5E85) // 3 3 13 0 5 (SME thread pointer 2) +TPIDRRO_EL0 :: System_Register(0x5E83) // 3 3 13 0 3 +TPIDR_EL0 :: System_Register(0x5E82) // 3 3 13 0 2 +TPIDR_EL1 :: System_Register(0x4684) // 3 0 13 0 4 +TPIDR_EL2 :: System_Register(0x6682) // 3 4 13 0 2 +TPIDR_EL3 :: System_Register(0x7682) // 3 6 13 0 2 // ----------------------------------------------------------------------------- -// Memory attribute / context / control registers +// Identification -- read-only feature bitmaps // ----------------------------------------------------------------------------- -CONTEXTIDR_EL1 :: i64(0x4681) // 3 0 13 0 1 -CPACR_EL1 :: i64(0x4082) // 3 0 1 0 2 -MAIR_EL1 :: i64(0x4510) // 3 0 10 2 0 -AMAIR_EL1 :: i64(0x4518) // 3 0 10 3 0 -VTCR_EL2 :: i64(0x610A) // 3 4 2 1 2 -VTTBR_EL2 :: i64(0x6108) // 3 4 2 1 0 -ACTLR_EL1 :: i64(0x4081) // 3 0 1 0 1 -AFSR0_EL1 :: i64(0x4288) // 3 0 5 1 0 -AFSR1_EL1 :: i64(0x4289) // 3 0 5 1 1 -ISR_EL1 :: i64(0x4608) // 3 0 12 1 0 + +// op0 op1 CRn CRm op2 +CCSIDR_EL1 :: System_Register(0x4800) // 3 1 0 0 0 +CLIDR_EL1 :: System_Register(0x4801) // 3 1 0 0 1 +CSSELR_EL1 :: System_Register(0x5000) // 3 2 0 0 0 +CTR_EL0 :: System_Register(0x5801) // 3 3 0 0 1 +DCZID_EL0 :: System_Register(0x5807) // 3 3 0 0 7 (used by __sve_max_vl-style probes too) +GMID_EL1 :: System_Register(0x4804) // 3 1 0 0 4 (FEAT_MTE) +ID_AA64AFR0_EL1 :: System_Register(0x402C) // 3 0 0 5 4 (auxiliary) +ID_AA64AFR1_EL1 :: System_Register(0x402D) // 3 0 0 5 5 +ID_AA64DFR0_EL1 :: System_Register(0x4028) // 3 0 0 5 0 +ID_AA64DFR1_EL1 :: System_Register(0x4029) // 3 0 0 5 1 +ID_AA64DFR2_EL1 :: System_Register(0x402A) // 3 0 0 5 2 +ID_AA64ISAR0_EL1 :: System_Register(0x4030) // 3 0 0 6 0 +ID_AA64ISAR1_EL1 :: System_Register(0x4031) // 3 0 0 6 1 +ID_AA64ISAR2_EL1 :: System_Register(0x4032) // 3 0 0 6 2 +ID_AA64ISAR3_EL1 :: System_Register(0x4033) // 3 0 0 6 3 +ID_AA64MMFR0_EL1 :: System_Register(0x4038) // 3 0 0 7 0 +ID_AA64MMFR1_EL1 :: System_Register(0x4039) // 3 0 0 7 1 +ID_AA64MMFR2_EL1 :: System_Register(0x403A) // 3 0 0 7 2 +ID_AA64PFR0_EL1 :: System_Register(0x4020) // 3 0 0 4 0 +ID_AA64PFR1_EL1 :: System_Register(0x4021) // 3 0 0 4 1 +ID_AA64SMFR0_EL1 :: System_Register(0x4025) // 3 0 0 4 5 (SME feature ID) +ID_AA64ZFR0_EL1 :: System_Register(0x4024) // 3 0 0 4 4 (SVE feature ID) +ID_AFR0_EL1 :: System_Register(0x400B) // 3 0 0 1 3 +ID_DFR0_EL1 :: System_Register(0x400A) // 3 0 0 1 2 +ID_ISAR0_EL1 :: System_Register(0x4010) // 3 0 0 2 0 +ID_ISAR1_EL1 :: System_Register(0x4011) // 3 0 0 2 1 +ID_ISAR2_EL1 :: System_Register(0x4012) // 3 0 0 2 2 +ID_ISAR3_EL1 :: System_Register(0x4013) // 3 0 0 2 3 +ID_ISAR4_EL1 :: System_Register(0x4014) // 3 0 0 2 4 +ID_ISAR5_EL1 :: System_Register(0x4015) // 3 0 0 2 5 +ID_ISAR6_EL1 :: System_Register(0x4017) // 3 0 0 2 7 +ID_MMFR0_EL1 :: System_Register(0x400C) // 3 0 0 1 4 +ID_MMFR1_EL1 :: System_Register(0x400D) // 3 0 0 1 5 +ID_MMFR2_EL1 :: System_Register(0x400E) // 3 0 0 1 6 +ID_MMFR3_EL1 :: System_Register(0x400F) // 3 0 0 1 7 +ID_MMFR4_EL1 :: System_Register(0x4016) // 3 0 0 2 6 +ID_MMFR5_EL1 :: System_Register(0x401E) // 3 0 0 3 6 +ID_PFR0_EL1 :: System_Register(0x4008) // 3 0 0 1 0 +ID_PFR1_EL1 :: System_Register(0x4009) // 3 0 0 1 1 +ID_PFR2_EL1 :: System_Register(0x401C) // 3 0 0 3 4 +MIDR_EL1 :: System_Register(0x4000) // 3 0 0 0 0 +MPIDR_EL1 :: System_Register(0x4005) // 3 0 0 0 5 // ----------------------------------------------------------------------------- -// Random number registers (v8.5-A FEAT_RNG) +// Pointer authentication keys (FEAT_PAuth) // ----------------------------------------------------------------------------- -RNDR :: i64(0x5920) // 3 3 2 4 0 -RNDRRS :: i64(0x5921) // 3 3 2 4 1 + +// op0 op1 CRn CRm op2 +APDAKEYHI_EL1 :: System_Register(0x4111) // 3 0 2 2 1 +APDAKEYLO_EL1 :: System_Register(0x4110) // 3 0 2 2 0 +APDBKEYHI_EL1 :: System_Register(0x4113) // 3 0 2 2 3 +APDBKEYLO_EL1 :: System_Register(0x4112) // 3 0 2 2 2 +APGAKEYHI_EL1 :: System_Register(0x4119) // 3 0 2 3 1 +APGAKEYLO_EL1 :: System_Register(0x4118) // 3 0 2 3 0 +APIAKEYHI_EL1 :: System_Register(0x4109) // 3 0 2 1 1 +APIAKEYLO_EL1 :: System_Register(0x4108) // 3 0 2 1 0 (FEAT_PAuth) +APIBKEYHI_EL1 :: System_Register(0x410B) // 3 0 2 1 3 +APIBKEYLO_EL1 :: System_Register(0x410A) // 3 0 2 1 2 // ----------------------------------------------------------------------------- -// More ID registers +// Memory tagging (FEAT_MTE) // ----------------------------------------------------------------------------- -ID_AA64ZFR0_EL1 :: i64(0x4024) // 3 0 0 4 4 (SVE feature ID) -ID_AA64SMFR0_EL1 :: i64(0x4025) // 3 0 0 4 5 (SME feature ID) -ID_AA64AFR0_EL1 :: i64(0x402C) // 3 0 0 5 4 (auxiliary) -ID_AA64AFR1_EL1 :: i64(0x402D) // 3 0 0 5 5 + +// op0 op1 CRn CRm op2 +GCR_EL1 :: System_Register(0x4086) // 3 0 1 0 6 (FEAT_MTE) +RGSR_EL1 :: System_Register(0x4085) // 3 0 1 0 5 (FEAT_MTE) +TFSRE0_EL1 :: System_Register(0x42B1) // 3 0 5 6 1 (FEAT_MTE) +TFSR_EL1 :: System_Register(0x42B0) // 3 0 5 6 0 (FEAT_MTE) // ----------------------------------------------------------------------------- -// Cache hierarchy + selection +// SVE and SME configuration // ----------------------------------------------------------------------------- -CCSIDR_EL1 :: i64(0x4800) // 3 1 0 0 0 -CLIDR_EL1 :: i64(0x4801) // 3 1 0 0 1 -CSSELR_EL1 :: i64(0x5000) // 3 2 0 0 0 + +// op0 op1 CRn CRm op2 +SMCR_EL1 :: System_Register(0x4096) // 3 0 1 2 6 (FEAT_SME) +SMCR_EL2 :: System_Register(0x6096) // 3 4 1 2 6 +SVCR :: System_Register(0x5A12) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) +ZCR_EL1 :: System_Register(0x4090) // 3 0 1 2 0 (FEAT_SVE) +ZCR_EL2 :: System_Register(0x6090) // 3 4 1 2 0 +ZCR_EL3 :: System_Register(0x7090) // 3 6 1 2 0 // ----------------------------------------------------------------------------- -// EL2 / EL3 control + return registers +// System control and memory management // ----------------------------------------------------------------------------- -SCTLR_EL2 :: i64(0x6080) // 3 4 1 0 0 -SCTLR_EL3 :: i64(0x7080) // 3 6 1 0 0 -SPSR_EL3 :: i64(0x7200) // 3 6 4 0 0 -ELR_EL3 :: i64(0x7201) // 3 6 4 0 1 -TPIDR_EL2 :: i64(0x6682) // 3 4 13 0 2 -TPIDR_EL3 :: i64(0x7682) // 3 6 13 0 2 -- err, EL3 needs op1=6 -HSTR_EL2 :: i64(0x608B) // 3 4 1 1 3 -MDCR_EL2 :: i64(0x6089) // 3 4 1 1 1 -CNTHCTL_EL2 :: i64(0x6708) // 3 4 14 1 0 -DACR32_EL2 :: i64(0x6180) // 3 4 3 0 0 -FPEXC32_EL2 :: i64(0x6298) // 3 4 5 3 0 -VBAR_EL2 :: i64(0x6600) // 3 4 12 0 0 -VBAR_EL3 :: i64(0x7600) // 3 6 12 0 0 -TPIDR2_EL0 :: i64(0x5E85) // 3 3 13 0 5 (SME thread pointer 2) + +// op0 op1 CRn CRm op2 +ACTLR_EL1 :: System_Register(0x4081) // 3 0 1 0 1 +AMAIR_EL1 :: System_Register(0x4518) // 3 0 10 3 0 +CPACR_EL1 :: System_Register(0x4082) // 3 0 1 0 2 +LORC_EL1 :: System_Register(0x4523) // 3 0 10 4 3 +LOREA_EL1 :: System_Register(0x4521) // 3 0 10 4 1 +LORID_EL1 :: System_Register(0x4527) // 3 0 10 4 7 +LORN_EL1 :: System_Register(0x4522) // 3 0 10 4 2 +LORSA_EL1 :: System_Register(0x4520) // 3 0 10 4 0 +MAIR_EL1 :: System_Register(0x4510) // 3 0 10 2 0 +PAR_EL1 :: System_Register(0x43A0) // 3 0 7 4 0 +SCTLR_EL1 :: System_Register(0x4080) // 3 0 1 0 0 +SCTLR_EL2 :: System_Register(0x6080) // 3 4 1 0 0 +SCTLR_EL3 :: System_Register(0x7080) // 3 6 1 0 0 +TCR_EL1 :: System_Register(0x4102) // 3 0 2 0 2 +TTBR0_EL1 :: System_Register(0x4100) // 3 0 2 0 0 +TTBR1_EL1 :: System_Register(0x4101) // 3 0 2 0 1 // ----------------------------------------------------------------------------- -// Debug registers (op0 = 2) +// Generic timer // ----------------------------------------------------------------------------- -MDSCR_EL1 :: i64(0x0012) // 2 0 0 2 2 -DSPSR_EL0 :: i64(0x5A28) // 3 3 4 5 0 -DLR_EL0 :: i64(0x5A29) // 3 3 4 5 1 -OSLAR_EL1 :: i64(0x0084) // 2 0 1 0 4 (op0=2 -> o0=0) -OSLSR_EL1 :: i64(0x008C) // 2 0 1 1 4 + +// op0 op1 CRn CRm op2 +CNTFRQ_EL0 :: System_Register(0x5F00) // 3 3 14 0 0 +CNTHCTL_EL2 :: System_Register(0x6708) // 3 4 14 1 0 +CNTHP_CTL_EL2 :: System_Register(0x6711) // 3 4 14 2 1 +CNTHP_CVAL_EL2 :: System_Register(0x6712) // 3 4 14 2 2 +CNTHP_TVAL_EL2 :: System_Register(0x6710) // 3 4 14 2 0 +CNTHV_CTL_EL2 :: System_Register(0x6719) // 3 4 14 3 1 +CNTHV_CVAL_EL2 :: System_Register(0x671A) // 3 4 14 3 2 +CNTHV_TVAL_EL2 :: System_Register(0x6718) // 3 4 14 3 0 +CNTKCTL_EL1 :: System_Register(0x4708) // 3 0 14 1 0 +CNTPCT_EL0 :: System_Register(0x5F01) // 3 3 14 0 1 +CNTPS_CTL_EL1 :: System_Register(0x7F11) // 3 7 14 2 1 +CNTPS_CVAL_EL1 :: System_Register(0x7F12) // 3 7 14 2 2 +CNTPS_TVAL_EL1 :: System_Register(0x7F10) // 3 7 14 2 0 +CNTP_CTL_EL0 :: System_Register(0x5F11) // 3 3 14 2 1 +CNTP_CVAL_EL0 :: System_Register(0x5F12) // 3 3 14 2 2 +CNTP_TVAL_EL0 :: System_Register(0x5F10) // 3 3 14 2 0 +CNTVCT_EL0 :: System_Register(0x5F02) // 3 3 14 0 2 +CNTVOFF_EL2 :: System_Register(0x6703) // 3 4 14 0 3 +CNTV_CTL_EL0 :: System_Register(0x5F19) // 3 3 14 3 1 +CNTV_CVAL_EL0 :: System_Register(0x5F1A) // 3 3 14 3 2 +CNTV_TVAL_EL0 :: System_Register(0x5F18) // 3 3 14 3 0 // ----------------------------------------------------------------------------- -// Cache / Memory feature extras +// Statistical profiling (FEAT_SPE) // ----------------------------------------------------------------------------- -RGSR_EL1 :: i64(0x4085) // 3 0 1 0 5 (FEAT_MTE) -GCR_EL1 :: i64(0x4086) // 3 0 1 0 6 (FEAT_MTE) -TFSR_EL1 :: i64(0x42B0) // 3 0 5 6 0 (FEAT_MTE) -TFSRE0_EL1 :: i64(0x42B1) // 3 0 5 6 1 (FEAT_MTE) -GMID_EL1 :: i64(0x4804) // 3 1 0 0 4 (FEAT_MTE) + +// op0 op1 CRn CRm op2 +PMBIDR_EL1 :: System_Register(0x44D7) // 3 0 9 10 7 +PMBLIMITR_EL1 :: System_Register(0x44D0) // 3 0 9 10 0 +PMBPTR_EL1 :: System_Register(0x44D1) // 3 0 9 10 1 +PMBSR_EL1 :: System_Register(0x44D3) // 3 0 9 10 3 +PMSCR_EL1 :: System_Register(0x44C8) // 3 0 9 9 0 +PMSELR_EL0 :: System_Register(0x5CE5) // 3 3 9 12 5 +PMSEVFR_EL1 :: System_Register(0x44CD) // 3 0 9 9 5 +PMSFCR_EL1 :: System_Register(0x44CC) // 3 0 9 9 4 +PMSICR_EL1 :: System_Register(0x44CA) // 3 0 9 9 2 +PMSIDR_EL1 :: System_Register(0x44CF) // 3 0 9 9 7 +PMSIRR_EL1 :: System_Register(0x44CB) // 3 0 9 9 3 +PMSLATFR_EL1 :: System_Register(0x44CE) // 3 0 9 9 6 +PMSWINC_EL0 :: System_Register(0x5CE4) // 3 3 9 12 4 // ----------------------------------------------------------------------------- -// SME / SVE configuration +// Performance monitors // ----------------------------------------------------------------------------- -SVCR :: i64(0x5A12) // 3 3 4 2 2 (FEAT_SME: SM + ZA bits) -SMCR_EL1 :: i64(0x4096) // 3 0 1 2 6 (FEAT_SME) -SMCR_EL2 :: i64(0x6096) // 3 4 1 2 6 -ZCR_EL1 :: i64(0x4090) // 3 0 1 2 0 (FEAT_SVE) -ZCR_EL2 :: i64(0x6090) // 3 4 1 2 0 -ZCR_EL3 :: i64(0x7090) // 3 6 1 2 0 + +// op0 op1 CRn CRm op2 +PMCCFILTR_EL0 :: System_Register(0x5F7F) // 3 3 14 15 7 +PMCCNTR_EL0 :: System_Register(0x5CE8) // 3 3 9 13 0 +PMCEID0_EL0 :: System_Register(0x5CE6) // 3 3 9 12 6 +PMCEID1_EL0 :: System_Register(0x5CE7) // 3 3 9 12 7 +PMCNTENCLR_EL0 :: System_Register(0x5CE2) // 3 3 9 12 2 +PMCNTENSET_EL0 :: System_Register(0x5CE1) // 3 3 9 12 1 +PMCR_EL0 :: System_Register(0x5CE0) // 3 3 9 12 0 +PMINTENCLR_EL1 :: System_Register(0x44F2) // 3 0 9 14 2 +PMINTENSET_EL1 :: System_Register(0x44F1) // 3 0 9 14 1 +PMOVSCLR_EL0 :: System_Register(0x5CE3) // 3 3 9 12 3 +PMUSERENR_EL0 :: System_Register(0x5CF0) // 3 3 9 14 0 // ----------------------------------------------------------------------------- -// Cache / data prefetch hint controls +// Trace // ----------------------------------------------------------------------------- -PRSELR_EL1 :: i64(0x4311) // 3 0 6 2 1 -APIAKEYLO_EL1 :: i64(0x4108) // 3 0 2 1 0 (FEAT_PAuth) -APIAKEYHI_EL1 :: i64(0x4109) // 3 0 2 1 1 -APIBKEYLO_EL1 :: i64(0x410A) // 3 0 2 1 2 -APIBKEYHI_EL1 :: i64(0x410B) // 3 0 2 1 3 -APDAKEYLO_EL1 :: i64(0x4110) // 3 0 2 2 0 -APDAKEYHI_EL1 :: i64(0x4111) // 3 0 2 2 1 -APDBKEYLO_EL1 :: i64(0x4112) // 3 0 2 2 2 -APDBKEYHI_EL1 :: i64(0x4113) // 3 0 2 2 3 -APGAKEYLO_EL1 :: i64(0x4118) // 3 0 2 3 0 -APGAKEYHI_EL1 :: i64(0x4119) // 3 0 2 3 1 -// ============================================================================= -// Batch 5: comprehensive sysreg sweep -// ============================================================================= +// op0 op1 CRn CRm op2 +TRBBASER_EL1 :: System_Register(0x44DA) // 3 0 9 11 2 +TRBIDR_EL1 :: System_Register(0x44DF) // 3 0 9 11 7 +TRBLIMITR_EL1 :: System_Register(0x44D8) // 3 0 9 11 0 +TRBMAR_EL1 :: System_Register(0x44DC) // 3 0 9 11 4 +TRBPTR_EL1 :: System_Register(0x44D9) // 3 0 9 11 1 +TRBSR_EL1 :: System_Register(0x44DB) // 3 0 9 11 3 +TRBTRG_EL1 :: System_Register(0x44DE) // 3 0 9 11 6 -// ---- More ID registers (AArch32 + extras) ---- -ID_AA64DFR2_EL1 :: i64(0x402A) // 3 0 0 5 2 -ID_AA64ISAR3_EL1 :: i64(0x4033) // 3 0 0 6 3 -ID_PFR0_EL1 :: i64(0x4008) // 3 0 0 1 0 -ID_PFR1_EL1 :: i64(0x4009) // 3 0 0 1 1 -ID_DFR0_EL1 :: i64(0x400A) // 3 0 0 1 2 -ID_AFR0_EL1 :: i64(0x400B) // 3 0 0 1 3 -ID_MMFR0_EL1 :: i64(0x400C) // 3 0 0 1 4 -ID_MMFR1_EL1 :: i64(0x400D) // 3 0 0 1 5 -ID_MMFR2_EL1 :: i64(0x400E) // 3 0 0 1 6 -ID_MMFR3_EL1 :: i64(0x400F) // 3 0 0 1 7 -ID_MMFR4_EL1 :: i64(0x4016) // 3 0 0 2 6 -ID_MMFR5_EL1 :: i64(0x401E) // 3 0 0 3 6 -ID_ISAR0_EL1 :: i64(0x4010) // 3 0 0 2 0 -ID_ISAR1_EL1 :: i64(0x4011) // 3 0 0 2 1 -ID_ISAR2_EL1 :: i64(0x4012) // 3 0 0 2 2 -ID_ISAR3_EL1 :: i64(0x4013) // 3 0 0 2 3 -ID_ISAR4_EL1 :: i64(0x4014) // 3 0 0 2 4 -ID_ISAR5_EL1 :: i64(0x4015) // 3 0 0 2 5 -ID_ISAR6_EL1 :: i64(0x4017) // 3 0 0 2 7 -ID_PFR2_EL1 :: i64(0x401C) // 3 0 0 3 4 -MVFR0_EL1 :: i64(0x4018) // 3 0 0 3 0 -MVFR1_EL1 :: i64(0x4019) // 3 0 0 3 1 -MVFR2_EL1 :: i64(0x401A) // 3 0 0 3 2 +// ----------------------------------------------------------------------------- +// Debug +// ----------------------------------------------------------------------------- -// ---- Counter / Timer (full set) ---- -CNTKCTL_EL1 :: i64(0x4708) // 3 0 14 1 0 -CNTP_TVAL_EL0 :: i64(0x5F10) // 3 3 14 2 0 -CNTP_CTL_EL0 :: i64(0x5F11) // 3 3 14 2 1 -CNTP_CVAL_EL0 :: i64(0x5F12) // 3 3 14 2 2 -CNTV_TVAL_EL0 :: i64(0x5F18) // 3 3 14 3 0 -CNTV_CTL_EL0 :: i64(0x5F19) // 3 3 14 3 1 -CNTV_CVAL_EL0 :: i64(0x5F1A) // 3 3 14 3 2 -CNTHP_TVAL_EL2 :: i64(0x6710) // 3 4 14 2 0 -CNTHP_CTL_EL2 :: i64(0x6711) // 3 4 14 2 1 -CNTHP_CVAL_EL2 :: i64(0x6712) // 3 4 14 2 2 -CNTHV_TVAL_EL2 :: i64(0x6718) // 3 4 14 3 0 -CNTHV_CTL_EL2 :: i64(0x6719) // 3 4 14 3 1 -CNTHV_CVAL_EL2 :: i64(0x671A) // 3 4 14 3 2 -CNTPS_TVAL_EL1 :: i64(0x7F10) // 3 7 14 2 0 -CNTPS_CTL_EL1 :: i64(0x7F11) // 3 7 14 2 1 -CNTPS_CVAL_EL1 :: i64(0x7F12) // 3 7 14 2 2 -CNTVOFF_EL2 :: i64(0x6703) // 3 4 14 0 3 +// op0 op1 CRn CRm op2 +DBGAUTHSTATUS_EL1 :: System_Register(0x03F6) // 2 0 7 14 6 +DBGCLAIMCLR_EL1 :: System_Register(0x03CE) // 2 0 7 9 6 +DBGCLAIMSET_EL1 :: System_Register(0x03C6) // 2 0 7 8 6 +DBGDTRRX_EL0 :: System_Register(0x1828) // 2 3 0 5 0 +DBGDTRTX_EL0 :: System_Register(0x1828) // 2 3 0 5 0 (write view of DBGDTRRX_EL0) +DBGDTR_EL0 :: System_Register(0x1820) // 2 3 0 4 0 +DBGPRCR_EL1 :: System_Register(0x00A4) // 2 0 1 4 4 +DLR_EL0 :: System_Register(0x5A29) // 3 3 4 5 1 +DSPSR_EL0 :: System_Register(0x5A28) // 3 3 4 5 0 +MDCCINT_EL1 :: System_Register(0x0010) // 2 0 0 2 0 +MDRAR_EL1 :: System_Register(0x0080) // 2 0 1 0 0 +MDSCR_EL1 :: System_Register(0x0012) // 2 0 0 2 2 +OSLAR_EL1 :: System_Register(0x0084) // 2 0 1 0 4 (op0=2 -> o0=0) +OSLSR_EL1 :: System_Register(0x008C) // 2 0 1 1 4 +PRSELR_EL1 :: System_Register(0x4311) // 3 0 6 2 1 -// ---- Debug breakpoints (DBGB*) and watchpoints (DBGW*), numbered ---- -// -// Each register file is 16 deep: DBGBVR0..15, DBGBCR0..15, DBGWVR0..15, -// DBGWCR0..15. Use the helper: -// sysreg_debug_breakpoint_value(n) -- DBGBVRn_EL1 = (2, 0, 0, n, 4) -// sysreg_debug_breakpoint_control(n) -- DBGBCRn_EL1 = (2, 0, 0, n, 5) -// sysreg_debug_watchpoint_value(n) -- DBGWVRn_EL1 = (2, 0, 0, n, 6) -// sysreg_debug_watchpoint_control(n) -- DBGWCRn_EL1 = (2, 0, 0, n, 7) +// ----------------------------------------------------------------------------- +// Generic interrupt controller +// ----------------------------------------------------------------------------- -sysreg_debug_breakpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 4) -} -sysreg_debug_breakpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 5) -} -sysreg_debug_watchpoint_value :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 6) -} -sysreg_debug_watchpoint_control :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(2, 0, 0, n & 0xF, 7) -} +// op0 op1 CRn CRm op2 +ICC_ASGI1R_EL1 :: System_Register(0x465E) // 3 0 12 11 6 +ICC_BPR0_EL1 :: System_Register(0x4643) // 3 0 12 8 3 +ICC_BPR1_EL1 :: System_Register(0x4663) // 3 0 12 12 3 +ICC_CTLR_EL1 :: System_Register(0x4664) // 3 0 12 12 4 +ICC_CTLR_EL3 :: System_Register(0x7664) // 3 6 12 12 4 +ICC_DIR_EL1 :: System_Register(0x4659) // 3 0 12 11 1 +ICC_EOIR0_EL1 :: System_Register(0x4641) // 3 0 12 8 1 +ICC_EOIR1_EL1 :: System_Register(0x4661) // 3 0 12 12 1 +ICC_HPPIR0_EL1 :: System_Register(0x4642) // 3 0 12 8 2 +ICC_HPPIR1_EL1 :: System_Register(0x4662) // 3 0 12 12 2 +ICC_IAR0_EL1 :: System_Register(0x4640) // 3 0 12 8 0 +ICC_IAR1_EL1 :: System_Register(0x4660) // 3 0 12 12 0 +ICC_IGRPEN0_EL1 :: System_Register(0x4666) // 3 0 12 12 6 +ICC_IGRPEN1_EL1 :: System_Register(0x4667) // 3 0 12 12 7 +ICC_IGRPEN1_EL3 :: System_Register(0x7667) // 3 6 12 12 7 +ICC_PMR_EL1 :: System_Register(0x4230) // 3 0 4 6 0 +ICC_RPR_EL1 :: System_Register(0x465B) // 3 0 12 11 3 +ICC_SGI0R_EL1 :: System_Register(0x465F) // 3 0 12 11 7 +ICC_SGI1R_EL1 :: System_Register(0x465D) // 3 0 12 11 5 +ICC_SRE_EL1 :: System_Register(0x4665) // 3 0 12 12 5 +ICC_SRE_EL2 :: System_Register(0x664D) // 3 4 12 9 5 +ICC_SRE_EL3 :: System_Register(0x7665) // 3 6 12 12 5 +ICH_EISR_EL2 :: System_Register(0x665B) // 3 4 12 11 3 +ICH_ELRSR_EL2 :: System_Register(0x665D) // 3 4 12 11 5 +ICH_HCR_EL2 :: System_Register(0x6658) // 3 4 12 11 0 +ICH_MISR_EL2 :: System_Register(0x665A) // 3 4 12 11 2 +ICH_VMCR_EL2 :: System_Register(0x665F) // 3 4 12 11 7 +ICH_VTR_EL2 :: System_Register(0x6659) // 3 4 12 11 1 -// Other debug registers -DBGDTR_EL0 :: i64(0x1820) // 2 3 0 4 0 -DBGDTRRX_EL0 :: i64(0x1828) // 2 3 0 5 0 -DBGDTRTX_EL0 :: i64(0x1828) // 2 3 0 5 0 (write view of DBGDTRRX_EL0) -DBGPRCR_EL1 :: i64(0x00A4) // 2 0 1 4 4 -DBGCLAIMSET_EL1 :: i64(0x03C6) // 2 0 7 8 6 -DBGCLAIMCLR_EL1 :: i64(0x03CE) // 2 0 7 9 6 -DBGAUTHSTATUS_EL1:: i64(0x03F6) // 2 0 7 14 6 -MDCCINT_EL1 :: i64(0x0010) // 2 0 0 2 0 -MDRAR_EL1 :: i64(0x0080) // 2 0 1 0 0 +// ----------------------------------------------------------------------------- +// RAS -- error record registers +// ----------------------------------------------------------------------------- -// PMU event counters (PMEVCNTRn_EL0 / PMEVTYPERn_EL0). Up to n=30. -// PMEVCNTRn_EL0 = sysreg(3, 3, 14, 8+(n>>3), n & 7) -// PMEVTYPERn_EL0 = sysreg(3, 3, 14, 12+(n>>3), n & 7) +// op0 op1 CRn CRm op2 +DISR_EL1 :: System_Register(0x4609) // 3 0 12 1 1 +ERRIDR_EL1 :: System_Register(0x4298) // 3 0 5 3 0 +ERRSELR_EL1 :: System_Register(0x4299) // 3 0 5 3 1 +ERXADDR_EL1 :: System_Register(0x42A3) // 3 0 5 4 3 +ERXCTLR_EL1 :: System_Register(0x42A1) // 3 0 5 4 1 +ERXFR_EL1 :: System_Register(0x42A0) // 3 0 5 4 0 +ERXMISC0_EL1 :: System_Register(0x42A8) // 3 0 5 5 0 +ERXMISC1_EL1 :: System_Register(0x42A9) // 3 0 5 5 1 +ERXMISC2_EL1 :: System_Register(0x42AA) // 3 0 5 5 2 +ERXMISC3_EL1 :: System_Register(0x42AB) // 3 0 5 5 3 +ERXSTATUS_EL1 :: System_Register(0x42A2) // 3 0 5 4 2 +VDISR_EL2 :: System_Register(0x6609) // 3 4 12 1 1 +VSESR_EL2 :: System_Register(0x6293) // 3 4 5 2 3 -sysreg_pmu_event_counter :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 3, 14, 8 + ((n >> 3) & 0x3), n & 0x7) -} -sysreg_pmu_event_typer :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 3, 14, 12 + ((n >> 3) & 0x3), n & 0x7) -} +// ----------------------------------------------------------------------------- +// Virtualisation (EL2) and secure monitor (EL3) +// ----------------------------------------------------------------------------- -PMINTENSET_EL1 :: i64(0x44F1) // 3 0 9 14 1 -PMINTENCLR_EL1 :: i64(0x44F2) // 3 0 9 14 2 +// op0 op1 CRn CRm op2 +GPCCR_EL3 :: System_Register(0x710E) // 3 6 2 1 6 (Granule Protection Control) +GPTBR_EL3 :: System_Register(0x710C) // 3 6 2 1 4 (Granule Protection Table Base) +HCR_EL2 :: System_Register(0x6088) // 3 4 1 1 0 +HSTR_EL2 :: System_Register(0x608B) // 3 4 1 1 3 +MDCR_EL2 :: System_Register(0x6089) // 3 4 1 1 1 +MFAR_EL3 :: System_Register(0x7305) // 3 6 6 0 5 (Multiple FAR) +VTCR_EL2 :: System_Register(0x610A) // 3 4 2 1 2 +VTTBR_EL2 :: System_Register(0x6108) // 3 4 2 1 0 -// ---- GICv3 (ICC_*) -- CPU interface ---- -ICC_IAR0_EL1 :: i64(0x4640) // 3 0 12 8 0 -ICC_IAR1_EL1 :: i64(0x4660) // 3 0 12 12 0 -ICC_EOIR0_EL1 :: i64(0x4641) // 3 0 12 8 1 -ICC_EOIR1_EL1 :: i64(0x4661) // 3 0 12 12 1 -ICC_HPPIR0_EL1 :: i64(0x4642) // 3 0 12 8 2 -ICC_HPPIR1_EL1 :: i64(0x4662) // 3 0 12 12 2 -ICC_BPR0_EL1 :: i64(0x4643) // 3 0 12 8 3 -ICC_BPR1_EL1 :: i64(0x4663) // 3 0 12 12 3 -ICC_DIR_EL1 :: i64(0x4659) // 3 0 12 11 1 -ICC_PMR_EL1 :: i64(0x4230) // 3 0 4 6 0 -ICC_RPR_EL1 :: i64(0x465B) // 3 0 12 11 3 -ICC_SGI0R_EL1 :: i64(0x465F) // 3 0 12 11 7 -ICC_SGI1R_EL1 :: i64(0x465D) // 3 0 12 11 5 -ICC_ASGI1R_EL1 :: i64(0x465E) // 3 0 12 11 6 -ICC_SRE_EL1 :: i64(0x4665) // 3 0 12 12 5 -ICC_SRE_EL2 :: i64(0x664D) // 3 4 12 9 5 -ICC_SRE_EL3 :: i64(0x7665) // 3 6 12 12 5 -ICC_CTLR_EL1 :: i64(0x4664) // 3 0 12 12 4 -ICC_CTLR_EL3 :: i64(0x7664) // 3 6 12 12 4 -ICC_IGRPEN0_EL1 :: i64(0x4666) // 3 0 12 12 6 -ICC_IGRPEN1_EL1 :: i64(0x4667) // 3 0 12 12 7 -ICC_IGRPEN1_EL3 :: i64(0x7667) // 3 6 12 12 7 +// ----------------------------------------------------------------------------- +// AArch32 compatibility +// ----------------------------------------------------------------------------- -// ---- GICv3 hypervisor (ICH_*) ---- -ICH_HCR_EL2 :: i64(0x6658) // 3 4 12 11 0 -ICH_VTR_EL2 :: i64(0x6659) // 3 4 12 11 1 -ICH_MISR_EL2 :: i64(0x665A) // 3 4 12 11 2 -ICH_EISR_EL2 :: i64(0x665B) // 3 4 12 11 3 -ICH_ELRSR_EL2 :: i64(0x665D) // 3 4 12 11 5 -ICH_VMCR_EL2 :: i64(0x665F) // 3 4 12 11 7 +// op0 op1 CRn CRm op2 +DACR32_EL2 :: System_Register(0x6180) // 3 4 3 0 0 +FPEXC32_EL2 :: System_Register(0x6298) // 3 4 5 3 0 -// ICH_LR0_EL2 .. ICH_LR15_EL2 = sysreg(3, 4, 12, 12+(n>>3), n & 7) -sysreg_ich_lr :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 12 + ((n >> 3) & 0x1), n & 0x7) -} +// ----------------------------------------------------------------------------- +// Random number (FEAT_RNG) +// ----------------------------------------------------------------------------- -// ICH_AP0Rn_EL2 (n=0..3) and ICH_AP1Rn_EL2 (n=0..3) -sysreg_ich_ap0r :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 8, n & 0x3) -} -sysreg_ich_ap1r :: #force_inline proc "contextless" (n: u32) -> i64 { - return sysreg_field(3, 4, 12, 9, n & 0x3) -} - -// ---- TRBE (Trace Buffer Extension, FEAT_TRBE) ---- -TRBLIMITR_EL1 :: i64(0x44D8) // 3 0 9 11 0 -TRBPTR_EL1 :: i64(0x44D9) // 3 0 9 11 1 -TRBBASER_EL1 :: i64(0x44DA) // 3 0 9 11 2 -TRBSR_EL1 :: i64(0x44DB) // 3 0 9 11 3 -TRBMAR_EL1 :: i64(0x44DC) // 3 0 9 11 4 -TRBTRG_EL1 :: i64(0x44DE) // 3 0 9 11 6 -TRBIDR_EL1 :: i64(0x44DF) // 3 0 9 11 7 - -// ---- SPE (Statistical Profiling Extension, FEAT_SPE) ---- -PMSCR_EL1 :: i64(0x44C8) // 3 0 9 9 0 -PMSICR_EL1 :: i64(0x44CA) // 3 0 9 9 2 -PMSIRR_EL1 :: i64(0x44CB) // 3 0 9 9 3 -PMSFCR_EL1 :: i64(0x44CC) // 3 0 9 9 4 -PMSEVFR_EL1 :: i64(0x44CD) // 3 0 9 9 5 -PMSLATFR_EL1 :: i64(0x44CE) // 3 0 9 9 6 -PMSIDR_EL1 :: i64(0x44CF) // 3 0 9 9 7 -PMBLIMITR_EL1 :: i64(0x44D0) // 3 0 9 10 0 -PMBPTR_EL1 :: i64(0x44D1) // 3 0 9 10 1 -PMBSR_EL1 :: i64(0x44D3) // 3 0 9 10 3 -PMBIDR_EL1 :: i64(0x44D7) // 3 0 9 10 7 - -// ---- RAS (Reliability, Availability, Serviceability) ---- -ERRSELR_EL1 :: i64(0x4299) // 3 0 5 3 1 -ERRIDR_EL1 :: i64(0x4298) // 3 0 5 3 0 -ERXADDR_EL1 :: i64(0x42A3) // 3 0 5 4 3 -ERXCTLR_EL1 :: i64(0x42A1) // 3 0 5 4 1 -ERXFR_EL1 :: i64(0x42A0) // 3 0 5 4 0 -ERXSTATUS_EL1 :: i64(0x42A2) // 3 0 5 4 2 -ERXMISC0_EL1 :: i64(0x42A8) // 3 0 5 5 0 -ERXMISC1_EL1 :: i64(0x42A9) // 3 0 5 5 1 -ERXMISC2_EL1 :: i64(0x42AA) // 3 0 5 5 2 -ERXMISC3_EL1 :: i64(0x42AB) // 3 0 5 5 3 -DISR_EL1 :: i64(0x4609) // 3 0 12 1 1 -VDISR_EL2 :: i64(0x6609) // 3 4 12 1 1 -VSESR_EL2 :: i64(0x6293) // 3 4 5 2 3 - -// ---- LOR (Limited Ordering Region) ---- -LORC_EL1 :: i64(0x4523) // 3 0 10 4 3 -LOREA_EL1 :: i64(0x4521) // 3 0 10 4 1 -LORID_EL1 :: i64(0x4527) // 3 0 10 4 7 -LORN_EL1 :: i64(0x4522) // 3 0 10 4 2 -LORSA_EL1 :: i64(0x4520) // 3 0 10 4 0 - -// ---- Translation result (returned by AT) ---- -PAR_EL1 :: i64(0x43A0) // 3 0 7 4 0 - -// ---- RME (Realm Management Extension) sysregs ---- -GPCCR_EL3 :: i64(0x710E) // 3 6 2 1 6 (Granule Protection Control) -GPTBR_EL3 :: i64(0x710C) // 3 6 2 1 4 (Granule Protection Table Base) -MFAR_EL3 :: i64(0x7305) // 3 6 6 0 5 (Multiple FAR) - -// ---- TPIDRRO_EL0 alias / extra thread pointers ---- -// (TPIDRRO_EL0 already added above) - -// ---- Performance Monitor extras ---- -PMCCFILTR_EL0 :: i64(0x5F7F) // 3 3 14 15 7 -PMUSERENR_EL0_REPEAT :: PMUSERENR_EL0 // re-export alias placeholder +// op0 op1 CRn CRm op2 +RNDR :: System_Register(0x5920) // 3 3 2 4 0 +RNDRRS :: System_Register(0x5921) // 3 3 2 4 1 // ----------------------------------------------------------------------------- // Value -> name, for printing // ----------------------------------------------------------------------------- // -// MRS/MSR carry the system register as a packed 15-bit field, so a disassembly -// has a number where an assembler wants a name. Sorted by value; binary search. +// A disassembly has the packed field where an assembler wants a name. Sorted +// by value; binary search. // -// 1 encodings carry two names. Where the pair is a read view and a write -// view of one register (DBGDTRRX/DBGDTRTX) the read name wins, since MRS is -// the direction that has to print; the rest are genuine aliases and either -// name assembles, so a round-trip can come back spelled as the sibling. +// 1 encoding carries two names: DBGDTRRX_EL0 and DBGDTRTX_EL0 are the read +// and write views of one register. The read name wins, since MRS is the +// direction that has to print. Sysreg_Name :: struct { - value: u16, + value: System_Register, name: string, } @@ -757,11 +733,11 @@ SYSREG_NAMES := [?]Sysreg_Name{ {0x7F12, "cntps_cval_el1"}, } -// Name for a packed system-register field, or ok=false when it is not one we -// know -- callers should fall back to printing the raw immediate. +// Name for a system register, or ok=false when it is not one we know -- +// callers should fall back to printing the raw field. @(require_results) -sysreg_name :: proc "contextless" (value: i64) -> (name: string, ok: bool) { - v := u16(value & 0x7FFF) +sysreg_name :: proc "contextless" (sr: System_Register) -> (name: string, ok: bool) { + v := System_Register(u16(sr) & 0x7FFF) lo, hi := 0, len(SYSREG_NAMES) - 1 for lo <= hi { mid := (lo + hi) / 2 diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index e01c4b843..a1b37e39f 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -1955,7 +1955,7 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, - { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, + { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index f0feb9801..77fa940bf 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -492,7 +492,7 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .MRS { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, // .MSR - { .MSR, {.SYS_REG,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, + { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, // .ISB { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 13fb3296c..a32b04759 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -691,7 +691,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.SYS_REG, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index d8d681632c109e5157a8dded583d4ff48bcd65d4..6d8f7d751c7186b621f891c4351a7ac0e1d60e52 100644 GIT binary patch delta 11764 zcmZXae{@vknaAIIXMg~~Ofn&mNkS%tRT4ykjk_QQZ!jQYfC&K-5X+_YoNdpZx?>OL ztlJaMTuM-?*(%=rv2{Z;Y-20_s&TZHR?AROu+?>Gw_61~On~4*)ymddw1e5_dEfVW zpZ9G4;153cx!>>eect!}$jk)yM}qq!*{HKTbfWRr<-(mZO$ZVE8vc!o^hDt-F|0x| zf1+@iJ*w&^VO`i6jn6gJ|ErFa2={g&+_@ksL=65732!p6us?d!^cBL5-i8N2IzKM_ zDI)5w2;YtV6Ce48Jo444!i6JWo3NITT(8b4mFK)U!8&K1Ix-E9GlmWBZh|_)K9lTUp>8R#MNn5_)iKj`^K88v<++*N^K8MNDnTgZ zlT{(sG1GO|3TGoM;dCJilZFz7hsVc-XR!x>z4iatQDA>i%!P9^`sByt$*F4vLdhN& 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(suffix p) // all immediates (incl ZA tile, SME slice, -> i64 / op_imm (suffix i) -// patterns, bitmask, sysreg, HW, NZCV, ...) +// patterns, bitmask, HW, NZCV, ...) +// MRS/MSR system register -> System_Register / op_sysreg (suffix s) // PC-relative label -> u32 / op_label (suffix l) // memory -> Memory / op_mem (suffix m) // condition code -> Cond / op_cond (suffix c) @@ -69,6 +70,7 @@ Operand_Category :: enum { REL, // u32 label -> op_label (1 param, suffix l) MEM, // Memory -> op_mem (1 param, suffix m) COND, // Cond -> op_cond (1 param, suffix c) + SYSREG, // System_Register -> op_sysreg (1 param, suffix s) SHIFTED, // Register + Shift_Type + u8 -> op_shifted (3 params, suffix sh) EXTENDED, // Register + Extend + u8 -> op_extended (3 params, suffix ex) } @@ -133,6 +135,8 @@ operand_category :: proc(t: a.Operand_Type) -> Operand_Category { return .MEM case .COND, .COND_NOT_AL: return .COND + case .SYS_REG: + return .SYSREG case .W_SHIFTED, .X_SHIFTED: return .SHIFTED case .W_EXTENDED, .X_EXTENDED: @@ -177,6 +181,7 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { case .REL: return "l" case .MEM: return "m" case .COND: return "c" + case .SYSREG: return "s" case .SHIFTED: return "sh" case .EXTENDED: return "ex" } @@ -255,6 +260,8 @@ operand_primary_names :: proc(sig: Operand_Signature) -> [4][3]string { result[i][0] = "mem" case .COND: result[i][0] = "cond" + case .SYSREG: + result[i][0] = "sysreg" case .SHIFTED: rn := reg_name(i, ®_count) result[i][0] = rn @@ -290,6 +297,8 @@ param_list :: proc(sig: Operand_Signature) -> [dynamic]Param { append(¶ms, Param{decl = fmt.tprintf("%s: Memory", names[i][0]), name = names[i][0]}) case .COND: append(¶ms, Param{decl = fmt.tprintf("%s: Cond", names[i][0]), name = names[i][0]}) + case .SYSREG: + append(¶ms, Param{decl = fmt.tprintf("%s: System_Register", names[i][0]), name = names[i][0]}) case .SHIFTED: append(¶ms, Param{decl = fmt.tprintf("%s: Register", names[i][0]), name = names[i][0]}) append(¶ms, Param{decl = fmt.tprintf("%s: Shift_Type", names[i][1]), name = names[i][1]}) @@ -363,6 +372,8 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]st fmt.sbprintf(sb, "op_mem(%s)", names[0]) case .COND: fmt.sbprintf(sb, "op_cond(%s)", names[0]) + case .SYSREG: + fmt.sbprintf(sb, "op_sysreg(%s)", names[0]) case .SHIFTED: fmt.sbprintf(sb, "op_shifted(%s, %s, %s)", names[0], names[1], names[2]) case .EXTENDED: @@ -398,7 +409,7 @@ uses_plain_constructors :: proc(sig: Operand_Signature) -> bool { .V_4H_FP16, .V_8H_FP16: return false // needs op_v_* } - case .IMM, .REL, .MEM, .COND: + case .IMM, .REL, .MEM, .COND, .SYSREG: // fine case: return false // ZREG / PREG / SHIFTED / EXTENDED From 1d4887ccb6aa618ee407c4a94d80a06141af3739 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 21:26:11 -0400 Subject: [PATCH 33/89] rexcode/arm64: vector builders relabelled the caller's register inst_add(X0, X1, X2) encoded `add v0.16b, v1.16b, v2.16b`. It built the operand as op_v_16b(u8(reg_hw(dst))), which throws away the register's class and rebuilds a V register from the bare number -- so an X register became a V register before the matcher, whose whole job is to reject that, ever saw it. It encoded, round-tripped, and printed cleanly. Seven mnemonics with both a scalar and a vector three-register form were affected: add, and, bic, eor, orn, orr, sub. The vector constructors now take the register the caller actually has and put the arrangement in op.size, so the class survives. A wrong class matches no form and encode reports it; the right class picks the right form, which is what the matcher was always supposed to do. The same laundering hid a second bug. Because every arrangement built the same Odin signature, all of a mnemonic's arrangements collapsed onto one builder name and only the first survived -- ADD has seven NEON forms and six were unreachable. 229 mnemonics were in that state. The arrangement is now part of the builder name (inst_add_v8b_v8b_v8b), so they are all reachable: 992 builders becomes 1847. The overload group is unchanged, since it still dedups by Odin signature, so inst_add(V0, V1, V2) still means .16b as before. Making them reachable exposed two pre-existing bugs, both fixed here: CMLE/CMLT/FCMLE/FCMLT compare against zero and the zero is part of the syntax rather than an encoded operand, so their disassembly was missing the trailing `#0`/`#0.0` and no assembler would take it; and BFCVTN was typed .8h at the destination where the architecture says .4h (BFCVTN2 is the .8h one, and was already right). Verified against llvm-mc: of the 874 all-register vector builders, 803 are byte-exact and none disagree. The 10 that llvm cannot assemble are the already-known modelling gaps -- SM3TT lane indices, TBL/TBX register lists, and PMULL's .1q destination, which the arrangement encoding cannot represent since 1 lane * 16 bytes collides with 16B. The other 61 are the harness passing V registers where a scalar B/H/S/D/Q view is required, which is the class check doing its job. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/mnemonic_builders.odin | 8958 ++++++++++------- core/rexcode/isa/arm64/operands.odin | 56 +- core/rexcode/isa/arm64/printer.odin | 8 + .../tablegen/generated/decode_tables.odin | 2 +- .../tablegen/generated/encode_tables.odin | 2 +- .../isa/arm64/tablegen/instruction_table.odin | 2 +- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49920 -> 49920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49960 -> 49960 bytes .../isa/arm64/tests/pipeline_smoke.odin | 2 +- .../arm64/tools/gen_mnemonic_builders.odin | 43 +- 10 files changed, 5408 insertions(+), 3665 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 8557d62f2..49cd46203 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -21,3632 +21,5342 @@ package rexcode_arm64 // Individual Typed Builder Procedures // ============================================================================= -inst_add_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD, dst, src, imm) } -inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_add_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_add_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_add_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } -emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -emit_add_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_r_r_r(dst, src, src2)) } -emit_add_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_z_z_z(rz, rz2, rz3)) } -emit_add_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } -inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_adds_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_r_r_i(dst, src, imm)) } -emit_adds_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_adds_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_sub_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB, dst, src, imm) } -inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_sub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_sub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } -emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -emit_sub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_r_r_r(dst, src, src2)) } -emit_sub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_z_z_z(rz, rz2, rz3)) } -emit_sub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } -inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -emit_subs_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_r_r_i(dst, src, imm)) } -emit_subs_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_subs_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } -inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } -inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } -inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } -inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } -inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } -inst_and_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_and_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_and_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } -emit_and_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_r_r_r(dst, src, src2)) } -emit_and_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_and_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } -emit_ands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } -inst_orr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_orr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } -emit_orr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_r_r_r(dst, src, src2)) } -emit_orr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_orr_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } -inst_eor_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_eor_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_eor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } -emit_eor_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_r_r_r(dst, src, src2)) } -emit_eor_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_eor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bic_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_bic_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_bic_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_bic_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_r_r_r(dst, src, src2)) } -emit_bic_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bic_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_bics_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_orn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_orn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_orn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_r_r_r(dst, src, src2)) } -emit_orn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } -inst_lsl_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } -emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } -emit_lsl_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } -inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } -inst_lsr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } -emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } -emit_lsr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } -inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } -inst_asr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } -emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } -emit_asr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_asr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_i(dst, src, imm)) } -inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ROR, dst, src, src2) } -inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR, dst, src, imm) } -emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } -emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } -inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -inst_udiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -emit_udiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -inst_sdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -emit_sdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } -emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } -inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } -emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } -inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } -emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } -inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } -emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } -inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } -emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } -inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } -emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } -inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -inst_smulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } -emit_smulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -inst_umulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } -emit_umulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } -inst_clz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } -emit_clz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_z_p_z(rz, rz2, rz3)) } -inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } -inst_cls_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } -emit_cls_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_z_p_z(rz, rz2, rz3)) } -inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } -emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } -inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -inst_rev_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -inst_rev_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -emit_rev_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_z_z(rz, rz2)) } -emit_rev_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_p_p(rz, rz2)) } -inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } -emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } -inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } -emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } -inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } -inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } -inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } -inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } -inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } -emit_ccmp_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_r_r_i_c(dst, src, imm, cond)) } -emit_ccmp_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_r_i_i_c(dst, imm, imm2, cond)) } -inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } -emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } -emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } -inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } -emit_cset_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_cset_r_c(dst, cond)) } -inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } -emit_csetm_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_csetm_r_c(dst, cond)) } -inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } -emit_cinc_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinc_r_r_c(dst, src, cond)) } -inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } -emit_cinv_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinv_r_r_c(dst, src, cond)) } -inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } -emit_cneg_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cneg_r_r_c(dst, src, cond)) } -inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } -emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } -inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } -emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } -inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } -emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } -inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } -emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } -inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } -emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } -inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } -inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } -emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } -emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } -inst_b_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_EQ, label) } -emit_b_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_eq_l(label)) } -inst_b_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NE, label) } -emit_b_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ne_l(label)) } -inst_b_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CS, label) } -emit_b_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cs_l(label)) } -inst_b_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CC, label) } -emit_b_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cc_l(label)) } -inst_b_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_MI, label) } -emit_b_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_mi_l(label)) } -inst_b_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_PL, label) } -emit_b_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_pl_l(label)) } -inst_b_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VS, label) } -emit_b_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vs_l(label)) } -inst_b_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VC, label) } -emit_b_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vc_l(label)) } -inst_b_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_HI, label) } -emit_b_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_hi_l(label)) } -inst_b_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LS, label) } -emit_b_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ls_l(label)) } -inst_b_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GE, label) } -emit_b_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ge_l(label)) } -inst_b_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LT, label) } -emit_b_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_lt_l(label)) } -inst_b_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GT, label) } -emit_b_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_gt_l(label)) } -inst_b_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LE, label) } -emit_b_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_le_l(label)) } -inst_b_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_AL, label) } -emit_b_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_al_l(label)) } -inst_b_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NV, label) } -emit_b_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_nv_l(label)) } -inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } -inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } -inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } -emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } -inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } -emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } -inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } -inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } -emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } -emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } -emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } -emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } -inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } -emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } -emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } -emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } -inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } -emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } -inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } -emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } -inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } -emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } -inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } -emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } -inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } -emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } -inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } -emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } -inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } -emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } -inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } -emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } -inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } -emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } -inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } -emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } -inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } -emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } -inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } -emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } -inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } -emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } -inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } -emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } -inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } -emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } -inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } -emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } -inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } -emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } -inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } -emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } -inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } -emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } -inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } -emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } -emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } -inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } -emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } -inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } -emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } -inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } -emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } -inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } -emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } -inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } -emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } -inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}}} } -emit_mrs_r_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, sysreg: System_Register) { append(instructions, inst_mrs_r_s(dst, sysreg)) } -inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } -inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}}} } -emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } -emit_msr_s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, sysreg: System_Register, src: Register) { append(instructions, inst_msr_s_r(sysreg, src)) } -inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } -inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } -inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } -inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } -inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } -inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } -inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } -inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } -inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } -emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } -inst_fmov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV, dst, src) } -inst_fmov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV, dst, imm) } -emit_fmov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_r_r(dst, src)) } -emit_fmov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_r_i(dst, imm)) } -inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } -inst_fabs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } -emit_fabs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_z_p_z(rz, rz2, rz3)) } -inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } -inst_fneg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } -emit_fneg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_z_p_z(rz, rz2, rz3)) } -inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } -inst_fsqrt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } -emit_fsqrt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_z_p_z(rz, rz2, rz3)) } -inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } -inst_fadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } -emit_fadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_z_z_z(rz, rz2, rz3)) } -emit_fadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } -inst_fsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } -emit_fsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_z_z_z(rz, rz2, rz3)) } -emit_fsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } -inst_fmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } -emit_fmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_z_z_z(rz, rz2, rz3)) } -emit_fmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } -inst_fdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } -emit_fdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } -emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } -inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } -emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } -emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } -emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } -emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } -emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } -inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } -emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } -inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } -inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } -inst_fmax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } -emit_fmax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } -inst_fmin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } -emit_fmin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } -inst_fmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } -emit_fmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } -inst_fminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } -emit_fminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } -emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } -inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } -emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } -inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } -emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } -inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } -emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } -inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } -emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } -inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } -emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } -inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } -emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } -inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } -emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } -inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } -emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } -inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } -emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } -inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } -emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } -inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } -emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } -inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } -emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } -inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } -inst_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } -emit_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_z_p_z(rz, rz2, rz3)) } -inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } -inst_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } -emit_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_z_p_z(rz, rz2, rz3)) } -inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } -inst_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } -emit_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_z_p_z(rz, rz2, rz3)) } -inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } -inst_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } -emit_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_z_p_z(rz, rz2, rz3)) } -inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } -inst_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } -emit_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_z_p_z(rz, rz2, rz3)) } -inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } -inst_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } -emit_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_z_p_z(rz, rz2, rz3)) } -inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } -inst_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } -emit_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_z_p_z(rz, rz2, rz3)) } -inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } -inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } -emit_tst_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_r_sh(dst, src, src_shift, src_amount)) } -inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } -emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } -inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } -emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } -inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } -emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } -inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } -emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } -inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } -emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } -inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } -emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } -inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } -emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } -inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } -emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } -inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } -emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } -inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } -emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } -inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } -emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } -inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } -emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } -inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } -emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } -inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } -emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } -inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } -emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } -inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } -emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } -inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } -emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } -inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } -emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } -inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } -emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } -inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } -emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } -inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } -emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } -inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } -emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } -inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } -emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } -inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } -emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } -inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } -emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } -inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } -emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } -inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } -emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } -inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } -emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } -inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } -emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } -inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } -emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } -inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } -emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } -inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } -emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } -inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } -emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } -inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } -emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } -inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } -emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } -inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } -emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } -inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } -emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } -inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } -emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } -inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } -emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } -inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } -emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } -inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } -emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } -inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } -emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } -inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } -emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } -inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } -emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } -inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } -emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } -inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } -emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } -inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } -emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } -inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } -emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } -inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } -emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } -inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } -emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } -inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } -emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } -inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } -emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } -inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } -emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } -inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } -emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } -inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } -emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } -inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } -emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } -inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } -emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } -inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } -emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } -inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } -emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } -inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } -emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } -inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } -emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } -inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } -emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } -inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } -emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } -inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } -emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } -inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } -emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } -inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } -emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } -inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } -emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } -inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } -emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } -inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } -emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } -inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } -emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } -inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } -emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } -inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } -emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } -inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } -emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } -inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } -emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } -inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } -emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } -inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } -emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } -inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } -emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } -inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } -emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } -inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } -emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } -inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } -emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } -inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } -emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } -inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } -emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } -inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } -emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } -inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } -emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } -inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } -emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } -inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } -emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } -inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } -emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } -inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } -emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } -inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } -emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } -inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } -emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } -inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } -emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } -inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } -emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } -inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } -emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } -inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } -emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } -inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } -emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } -inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } -emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } -inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } -emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } -inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } -emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } -inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } -emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } -inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } -emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } -inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } -emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } -inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } -emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } -inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } -emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } -inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } -emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } -inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } -emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } -inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } -emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } -inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } -emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } -inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } -emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } -inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } -emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } -inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } -emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } -inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } -emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } -inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } -emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } -inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } -emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } -inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } -emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } -inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } -emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } -inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } -emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } -inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } -inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } -emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } -inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } -inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } -inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } -emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } -inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } -emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } -inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } -emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } -inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } -emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } -inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } -emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } -inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } -emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } -inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } -emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } -inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } -emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } -inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } -emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } -inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } -emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } -inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } -emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } -inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } -emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } -inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } -emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } -inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } -emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } -inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } -emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } -inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } -emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } -inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } -emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } -inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } -emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } -inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } -emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } -inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } -emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } -inst_aese_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -inst_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -emit_aese_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_r_r(dst, src)) } -emit_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_z_z(rz, rz2)) } -inst_aesd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -inst_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -emit_aesd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_r_r(dst, src)) } -emit_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_z_z(rz, rz2)) } -inst_aesmc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -inst_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } -emit_aesmc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_r_r(dst, src)) } -emit_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_z(rz)) } -inst_aesimc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -inst_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } -emit_aesimc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_r_r(dst, src)) } -emit_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_z(rz)) } -inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } -emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } -inst_sha1c_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1c_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_r(dst, src, src2)) } -inst_sha1p_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1p_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_r(dst, src, src2)) } -inst_sha1m_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1m_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_r(dst, src, src2)) } -inst_sha1su0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha1su0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_r_r_r(dst, src, src2)) } -inst_sha1su1_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sha1su1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_r_r(dst, src)) } -inst_sha256h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_r(dst, src, src2)) } -inst_sha256h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_r(dst, src, src2)) } -inst_sha256su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sha256su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_r_r(dst, src)) } -inst_sha256su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sha256su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_r_r_r(dst, src, src2)) } -inst_sha512h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_r(dst, src, src2)) } -inst_sha512h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_r(dst, src, src2)) } -inst_sha512su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_sha512su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_r_r(dst, src)) } -inst_sha512su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_sha512su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_r_r_r(dst, src, src2)) } -inst_eor3_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } -inst_eor3_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_eor3_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_r_r_r_r(dst, src, src2, src3)) } -emit_eor3_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_bcax_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } -inst_bcax_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bcax_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_r_r_r_r(dst, src, src2, src3)) } -emit_bcax_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_rax1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } -emit_rax1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_r_r_r(dst, src, src2)) } -inst_xar_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } -inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } -emit_xar_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_r_r_r_i(dst, src, src2, imm)) } -emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sm3partw1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm3partw1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_r_r_r(dst, src, src2)) } -inst_sm3partw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm3partw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_r_r_r(dst, src, src2)) } -inst_sm3ss1_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_v_4s(u8(reg_hw(src3)))}} } -emit_sm3ss1_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_r_r_r_r(dst, src, src2, src3)) } -inst_sm3tt1a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt1a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_r_r_r(dst, src, src2)) } -inst_sm3tt1b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt1b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_r_r_r(dst, src, src2)) } -inst_sm3tt2a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt2a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_r_r_r(dst, src, src2)) } -inst_sm3tt2b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_elem_s(u8(reg_hw(src2))), {}}} } -emit_sm3tt2b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_r_r_r(dst, src, src2)) } -inst_sm4e_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_sm4e_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_r_r(dst, src)) } -inst_sm4ekey_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -emit_sm4ekey_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_r_r_r(dst, src, src2)) } -inst_pmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_pmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_r_r_r(dst, src, src2)) } -inst_pmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_pmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_r_r_r(dst, src, src2)) } -inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -inst_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } -emit_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_z_p_z(rz, rz2, rz3)) } -inst_bfdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_r_r_r(dst, src, src2)) } -inst_bfmmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_r_r_r(dst, src, src2)) } -inst_bfmlalb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmlalb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_r_r_r(dst, src, src2)) } -inst_bfmlalt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_bfmlalt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_r_r_r(dst, src, src2)) } -inst_bfcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_bfcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_r_r(dst, src)) } -inst_bfcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_bfcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_r_r(dst, src)) } -inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_mul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } -emit_mul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_mla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_mla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_r_r_r(dst, src, src2)) } -inst_mls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_mls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_r_r_r(dst, src, src2)) } -inst_neg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -inst_neg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_neg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_r_r(dst, src)) } -emit_neg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_z_p_z(rz, rz2, rz3)) } -emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } -inst_abs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -inst_abs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_abs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_r_r(dst, src)) } -emit_abs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_z_p_z(rz, rz2, rz3)) } -inst_shadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_shadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_r_r_r(dst, src, src2)) } -inst_uhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_r_r_r(dst, src, src2)) } -inst_shsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_shsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_r_r_r(dst, src, src2)) } -inst_uhsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uhsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_r_r_r(dst, src, src2)) } -inst_srhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_srhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_r_r_r(dst, src, src2)) } -inst_urhadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_urhadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_r_r_r(dst, src, src2)) } -inst_sqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_sqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_r_r_r(dst, src, src2)) } -emit_sqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_z_z_z(rz, rz2, rz3)) } -inst_uqadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_uqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_uqadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_r_r_r(dst, src, src2)) } -emit_uqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_z_z_z(rz, rz2, rz3)) } -inst_sqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_sqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_r_r_r(dst, src, src2)) } -emit_sqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_z_z_z(rz, rz2, rz3)) } -inst_uqsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_uqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_uqsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_r_r_r(dst, src, src2)) } -emit_uqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_z_z_z(rz, rz2, rz3)) } -inst_smax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_smax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_smax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_r_r_r(dst, src, src2)) } -emit_smax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_umax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_umax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_umax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_r_r_r(dst, src, src2)) } -emit_umax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_smin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_smin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_smin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_r_r_r(dst, src, src2)) } -emit_smin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_umin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_umin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_umin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_r_r_r(dst, src, src2)) } -emit_umin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_sabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_sabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_r_r_r(dst, src, src2)) } -emit_sabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_uabd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_uabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_uabd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_r_r_r(dst, src, src2)) } -emit_uabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_saba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_r_r_r(dst, src, src2)) } -inst_uaba_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaba_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_r_r_r(dst, src, src2)) } -inst_addp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_addp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_r_r_r(dst, src, src2)) } -inst_addv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_addv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_r(dst, src)) } -inst_saddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_saddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_r_r(dst, src)) } -inst_uaddlp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uaddlp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_r_r(dst, src)) } -inst_sadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_r_r(dst, src)) } -inst_uadalp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uadalp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_r_r(dst, src)) } -inst_saddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_saddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_r(dst, src)) } -inst_uaddlv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uaddlv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_r(dst, src)) } -inst_smaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_smaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_r(dst, src)) } -inst_umaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_umaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_r(dst, src)) } -inst_sminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_r(dst, src)) } -inst_uminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_r(dst, src)) } -inst_smaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_r_r_r(dst, src, src2)) } -inst_umaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_r_r_r(dst, src, src2)) } -inst_sminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_r_r_r(dst, src, src2)) } -inst_uminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_r_r_r(dst, src, src2)) } -inst_saddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_r_r_r(dst, src, src2)) } -inst_saddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_saddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_r_r_r(dst, src, src2)) } -inst_uaddl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaddl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_r_r_r(dst, src, src2)) } -inst_uaddl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_uaddl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_r_r_r(dst, src, src2)) } -inst_ssubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ssubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_r_r_r(dst, src, src2)) } -inst_ssubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_ssubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_r_r_r(dst, src, src2)) } -inst_usubl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_r_r_r(dst, src, src2)) } -inst_usubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_usubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_r_r_r(dst, src, src2)) } -inst_saddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_saddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_r_r_r(dst, src, src2)) } -inst_saddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_saddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_r_r_r(dst, src, src2)) } -inst_uaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_uaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_r_r_r(dst, src, src2)) } -inst_uaddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_uaddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_r_r_r(dst, src, src2)) } -inst_ssubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ssubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_r_r_r(dst, src, src2)) } -inst_ssubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_ssubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_r_r_r(dst, src, src2)) } -inst_usubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_r_r_r(dst, src, src2)) } -inst_usubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_usubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_r_r_r(dst, src, src2)) } -inst_raddhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_raddhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_r_r_r(dst, src, src2)) } -inst_raddhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_raddhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_r_r_r(dst, src, src2)) } -inst_rsubhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_rsubhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_r_r_r(dst, src, src2)) } -inst_rsubhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_rsubhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_r_r_r(dst, src, src2)) } -inst_addhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_addhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_r_r_r(dst, src, src2)) } -inst_addhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_addhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_r_r_r(dst, src, src2)) } -inst_subhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_subhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_r_r_r(dst, src, src2)) } -inst_subhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_subhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_r_r_r(dst, src, src2)) } -inst_xtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_xtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_r_r(dst, src)) } -inst_xtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_xtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_r_r(dst, src)) } -inst_sqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_r_r(dst, src)) } -inst_sqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_r_r(dst, src)) } -inst_uqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_uqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_r_r(dst, src)) } -inst_uqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_uqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_r_r(dst, src)) } -inst_sqxtun_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtun_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_r_r(dst, src)) } -inst_sqxtun2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_sqxtun2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_r_r(dst, src)) } -inst_smull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_r_r_r(dst, src, src2)) } -inst_smull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_r_r_r(dst, src, src2)) } -inst_umull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_r_r_r(dst, src, src2)) } -inst_umull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_r_r_r(dst, src, src2)) } -inst_smlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_r_r_r(dst, src, src2)) } -inst_smlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_r_r_r(dst, src, src2)) } -inst_umlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_r_r_r(dst, src, src2)) } -inst_umlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_r_r_r(dst, src, src2)) } -inst_smlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_smlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_r_r_r(dst, src, src2)) } -inst_smlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_smlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_r_r_r(dst, src, src2)) } -inst_umlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_umlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_r_r_r(dst, src, src2)) } -inst_umlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_umlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_r_r_r(dst, src, src2)) } -inst_sqdmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_r_r_r(dst, src, src2)) } -inst_sqdmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_r_r_r(dst, src, src2)) } -inst_sqdmlal_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmlal_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_r_r_r(dst, src, src2)) } -inst_sqdmlal2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmlal2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_r_r_r(dst, src, src2)) } -inst_sqdmlsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmlsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_r_r_r(dst, src, src2)) } -inst_sqdmlsl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } -emit_sqdmlsl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_r_r_r(dst, src, src2)) } -inst_sqdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_r_r_r(dst, src, src2)) } -inst_sqrdmulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), {}}} } -emit_sqrdmulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_r_r_r(dst, src, src2)) } -inst_sdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_r_r_r(dst, src, src2)) } -inst_udot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_udot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_r_r_r(dst, src, src2)) } -inst_usdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_usdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_r_r_r(dst, src, src2)) } -inst_fmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -inst_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmla_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } -emit_fmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_r_r_r(dst, src, src2)) } -emit_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_fmla_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_z_z_z_i(rz, rz2, rz3, imm)) } -inst_fmls_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } -inst_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmls_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } -emit_fmls_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_r_r_r(dst, src, src2)) } -emit_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_fmls_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_z_z_z_i(rz, rz2, rz3, imm)) } -inst_fmulx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmulx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_r_r_r(dst, src, src2)) } -inst_fmaxp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmaxp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_r_r_r(dst, src, src2)) } -inst_fminp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fminp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_r_r_r(dst, src, src2)) } -inst_fmaxnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fmaxnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_r_r_r(dst, src, src2)) } -inst_fminnmp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_fminnmp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_r_r_r(dst, src, src2)) } -inst_fmaxv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fmaxv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_r(dst, src)) } -inst_fminv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fminv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_r(dst, src)) } -inst_fmaxnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fmaxnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_r(dst, src)) } -inst_fminnmv_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fminnmv_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_r(dst, src)) } -inst_frecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_r_r(dst, src)) } -inst_frsqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_frsqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_r_r(dst, src)) } -inst_frecps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -inst_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_frecps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_r_r_r(dst, src, src2)) } -emit_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_z_z_z(rz, rz2, rz3)) } -inst_frsqrts_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -inst_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_frsqrts_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_r_r_r(dst, src, src2)) } -emit_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_z_z_z(rz, rz2, rz3)) } -inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } -inst_frecpx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } -emit_frecpx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_z_p_z(rz, rz2, rz3)) } -inst_faddp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_faddp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_r_r_r(dst, src, src2)) } -inst_fcvtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), {}, {}}} } -emit_fcvtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_r_r(dst, src)) } -inst_fcvtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } -emit_fcvtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_r_r(dst, src)) } -inst_fcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_r_r(dst, src)) } -inst_fcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } -emit_fcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_r_r(dst, src)) } -inst_fcvtxn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_fcvtxn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_r_r(dst, src)) } -inst_fcvtxn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } -emit_fcvtxn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_r_r(dst, src)) } -inst_fcmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -inst_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_r_r_r(dst, src, src2)) } -emit_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -inst_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_r_r_r(dst, src, src2)) } -emit_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -inst_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_r_r_r(dst, src, src2)) } -emit_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -inst_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_fcmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_r_r(dst, src)) } -emit_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_p_p_z(rz, rz2, rz3)) } -inst_fcmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -inst_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -emit_fcmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_r_r(dst, src)) } -emit_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_p_p_z(rz, rz2, rz3)) } -inst_facge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_facge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_r_r_r(dst, src, src2)) } -inst_facgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } -emit_facgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_r_r_r(dst, src, src2)) } -inst_cmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_r_r_r(dst, src, src2)) } -inst_cmge_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmge_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_r_r_r(dst, src, src2)) } -inst_cmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_r_r_r(dst, src, src2)) } -inst_cmhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_cmhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_r_r_r(dst, src, src2)) } -inst_cmhs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmhs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_r_r_r(dst, src, src2)) } -inst_cmle_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cmle_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_r_r(dst, src)) } -inst_cmlt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_cmlt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_r_r(dst, src)) } -inst_cmtst_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_cmtst_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_r_r_r(dst, src, src2)) } -inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } -inst_bit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_r_r_r(dst, src, src2)) } -inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) } -inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } -inst_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) } -emit_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_shl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_r_r_i(dst, src, imm)) } -inst_sqshl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_r_r_i(dst, src, imm)) } -inst_sqshlu_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshlu_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_r_r_i(dst, src, imm)) } -inst_srshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_srshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_r_r_r(dst, src, src2)) } -inst_urshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_urshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_r_r_r(dst, src, src2)) } -inst_sshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_r_r_i(dst, src, imm)) } -inst_ushr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_r_r_i(dst, src, imm)) } -inst_ssra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ssra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_r_r_i(dst, src, imm)) } -inst_usra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_usra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_r_r_i(dst, src, imm)) } -inst_srshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_srshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_r_r_i(dst, src, imm)) } -inst_urshr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_urshr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_r_r_i(dst, src, imm)) } -inst_srsra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_srsra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_r_r_i(dst, src, imm)) } -inst_ursra_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ursra_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_r_r_i(dst, src, imm)) } -inst_sshl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_sshl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_r_r_r(dst, src, src2)) } -inst_ushl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -emit_ushl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_r_r_r(dst, src, src2)) } -inst_sli_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sli_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_r_r_i(dst, src, imm)) } -inst_sri_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sri_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_r_r_i(dst, src, imm)) } -inst_sshll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_r_r_i(dst, src, imm)) } -inst_sshll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sshll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_r_r_i(dst, src, imm)) } -inst_ushll_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushll_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_r_r_i(dst, src, imm)) } -inst_ushll2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_ushll2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_r_r_i(dst, src, imm)) } -inst_sxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_sxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_r_r(dst, src)) } -inst_sxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_sxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_r_r(dst, src)) } -inst_uxtl_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_uxtl_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_r_r(dst, src)) } -inst_uxtl2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } -emit_uxtl2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_r_r(dst, src)) } -inst_shrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_r_r_i(dst, src, imm)) } -inst_shrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_shrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_r_r_i(dst, src, imm)) } -inst_rshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_rshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_r_r_i(dst, src, imm)) } -inst_rshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_rshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_r_r_i(dst, src, imm)) } -inst_sqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_r_r_i(dst, src, imm)) } -inst_sqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_r_r_i(dst, src, imm)) } -inst_uqshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_r_r_i(dst, src, imm)) } -inst_uqshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_r_r_i(dst, src, imm)) } -inst_sqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_r_r_i(dst, src, imm)) } -inst_sqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_r_r_i(dst, src, imm)) } -inst_uqrshrn_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqrshrn_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_r_r_i(dst, src, imm)) } -inst_uqrshrn2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_uqrshrn2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_r_r_i(dst, src, imm)) } -inst_sqshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_r_r_i(dst, src, imm)) } -inst_sqshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_r_r_i(dst, src, imm)) } -inst_sqrshrun_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrun_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_r_r_i(dst, src, imm)) } -inst_sqrshrun2_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -emit_sqrshrun2_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_r_r_i(dst, src, imm)) } -inst_dup_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_elem_b(u8(reg_hw(src))), op_imm(imm, 4), {}}} } -inst_dup_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_reg(src), {}, {}}} } -inst_dup_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -emit_dup_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_r_r_i(dst, src, imm)) } -emit_dup_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_r_r(dst, src)) } -emit_dup_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_z_r(rz, src)) } -inst_ins_r_i_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_v_elem_b(u8(reg_hw(src))), op_imm(imm2, 4)}} } -inst_ins_r_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_reg(src), {}}} } -emit_ins_r_i_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_r_i_r_i(dst, imm, src, imm2)) } -emit_ins_r_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_r_i_r(dst, imm, src)) } -inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -inst_mov_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_mov_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } -emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } -emit_mov_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_z_p_z(rz, rz2, rz3)) } -emit_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_p_p_p(rz, rz2, rz3)) } -emit_mov_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_p_p(rz, rz2)) } -emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } -inst_ext_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), op_imm(imm, 4)}} } -inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } -emit_ext_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_r_r_r_i(dst, src, src2, imm)) } -emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } -inst_tbl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_r_r_r(dst, src, src2)) } -emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } -inst_tbx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_r_r_r(dst, src, src2)) } -emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } -inst_zip1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_zip1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_zip1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_r_r_r(dst, src, src2)) } -emit_zip1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_z_z_z(rz, rz2, rz3)) } -emit_zip1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_p_p_p(rz, rz2, rz3)) } -inst_zip2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_zip2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_zip2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_r_r_r(dst, src, src2)) } -emit_zip2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_z_z_z(rz, rz2, rz3)) } -emit_zip2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_p_p_p(rz, rz2, rz3)) } -inst_uzp1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_uzp1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_uzp1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_r_r_r(dst, src, src2)) } -emit_uzp1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_z_z_z(rz, rz2, rz3)) } -emit_uzp1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_p_p_p(rz, rz2, rz3)) } -inst_uzp2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_uzp2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_uzp2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_r_r_r(dst, src, src2)) } -emit_uzp2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_z_z_z(rz, rz2, rz3)) } -emit_uzp2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_p_p_p(rz, rz2, rz3)) } -inst_trn1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_trn1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_trn1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_r_r_r(dst, src, src2)) } -emit_trn1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_z_z_z(rz, rz2, rz3)) } -emit_trn1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_p_p_p(rz, rz2, rz3)) } -inst_trn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } -inst_trn2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_trn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_r_r_r(dst, src, src2)) } -emit_trn2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_z_z_z(rz, rz2, rz3)) } -emit_trn2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_p_p_p(rz, rz2, rz3)) } -inst_not_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -inst_not_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_not_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_r_r(dst, src)) } -emit_not_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_p_p_p(rz, rz2, rz3)) } -inst_rev64_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -emit_rev64_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_r_r(dst, src)) } -inst_cnt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } -inst_cnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -emit_cnt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_r_r(dst, src)) } -emit_cnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_z_p_z(rz, rz2, rz3)) } -inst_urecpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_urecpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_r_r(dst, src)) } -inst_ursqrte_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), {}, {}}} } -emit_ursqrte_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_r_r(dst, src)) } -inst_movi_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } -emit_movi_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_r_i(dst, imm)) } -inst_mvni_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_imm(imm, 1), {}, {}}} } -emit_mvni_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_r_i(dst, imm)) } -inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_ld1_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) } -emit_ld1_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_r_i_m(dst, imm, mem)) } -inst_ld2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_ld2_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_r_m(dst, mem)) } -emit_ld2_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_r_i_m(dst, imm, mem)) } -inst_ld3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_ld3_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_r_m(dst, mem)) } -emit_ld3_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_r_i_m(dst, imm, mem)) } -inst_ld4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_ld4_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_ld4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_r_m(dst, mem)) } -emit_ld4_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_r_i_m(dst, imm, mem)) } -inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_st1_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_r_m(dst, mem)) } -emit_st1_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_r_i_m(dst, imm, mem)) } -inst_st2_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_st2_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st2_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_r_m(dst, mem)) } -emit_st2_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_r_i_m(dst, imm, mem)) } -inst_st3_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_st3_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st3_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_r_m(dst, mem)) } -emit_st3_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_r_i_m(dst, imm, mem)) } -inst_st4_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -inst_st4_r_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(u8(reg_hw(dst))), op_imm(imm, 4), op_mem(mem), {}}} } -emit_st4_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_r_m(dst, mem)) } -emit_st4_r_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_r_i_m(dst, imm, mem)) } -inst_ld1r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld1r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_r_m(dst, mem)) } -inst_ld2r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld2r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_r_m(dst, mem)) } -inst_ld3r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld3r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_r_m(dst, mem)) } -inst_ld4r_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } -emit_ld4r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_r_m(dst, mem)) } -inst_subr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_subr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_asrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_asrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_lslr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_lslr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_lsrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_lsrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_z_z_z(rz, rz2, rz3)) } -inst_fsubr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fsubr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fdivr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fdivr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_nand_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nand_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sel_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sel_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orrs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orrs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_eors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_eors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orns_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orns_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_movs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_movs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_p_p_p(rz, rz2, rz3)) } -inst_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_p_i(rz, imm)) } -inst_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_p_i(rz, imm)) } -inst_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_p(rz)) } -inst_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_p_p_p(rz, rz2, rz3)) } -inst_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_p_p_p(rz, rz2, rz3)) } -inst_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_p_p_p(rz, rz2, rz3)) } -inst_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_p_p_p(rz, rz2, rz3)) } -inst_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_p_p_p(rz, rz2, rz3)) } -inst_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_p_p_p(rz, rz2, rz3)) } -inst_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_p(rz)) } -inst_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_p(rz)) } -inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } -emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } -inst_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -emit_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_z_r(rz, src)) } -inst_cpy_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -emit_cpy_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_z_p_r(rz, rz2, src)) } -inst_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_z_p_z(rz, rz2, rz3)) } -inst_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_z_p_m(rz, rz2, mem)) } -emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } -inst_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_z_p_m(rz, rz2, mem)) } -emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } -inst_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_z_p_m(rz, rz2, mem)) } -emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } -inst_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_z_p_m(rz, rz2, mem)) } -emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } -inst_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_z_p_m(rz, rz2, mem)) } -inst_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_z_p_m(rz, rz2, mem)) } -inst_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_z_p_m(rz, rz2, mem)) } -inst_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_z_p_m(rz, rz2, mem)) } -emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } -inst_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_z_p_m(rz, rz2, mem)) } -emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } -inst_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_z_p_m(rz, rz2, mem)) } -emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } -inst_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_z_p_m(rz, rz2, mem)) } -emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } -inst_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_z_p_m(rz, rz2, mem)) } -inst_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_z_p_m(rz, rz2, mem)) } -inst_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_z_p_m(rz, rz2, mem)) } -inst_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_z_p_m(rz, rz2, mem)) } -inst_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_p_r_r(rz, src, src2)) } -inst_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_p_r_r(rz, src, src2)) } -inst_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_p_r_r(rz, src, src2)) } -inst_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_p_r_r(rz, src, src2)) } -inst_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_p_r_r(rz, src, src2)) } -inst_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_p_r_r(rz, src, src2)) } -inst_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_p_r_r(rz, src, src2)) } -inst_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_p_r_r(rz, src, src2)) } -inst_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_z_z_z(rz, rz2, rz3)) } -inst_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_z_z_z(rz, rz2, rz3)) } -inst_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_z_z_z(rz, rz2, rz3)) } -inst_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_z_z_z(rz, rz2, rz3)) } -inst_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_z_z_z(rz, rz2, rz3)) } -inst_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_z_z_z(rz, rz2, rz3)) } -inst_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_z_z_z(rz, rz2, rz3)) } -inst_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_z_z_z(rz, rz2, rz3)) } -inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } -emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } -inst_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTOP) } -emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } -inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } -emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } -inst_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } -emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } -inst_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } -inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } -inst_mova_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } -inst_mova_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } -emit_mova_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_z_p_i(rz, rz2, imm)) } -emit_mova_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_z(imm, rz1, rz2)) } -inst_fcmla_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcmla_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_r_r_r_i(dst, src, src2, imm)) } -inst_fcadd_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } -emit_fcadd_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_r_r_r_i(dst, src, src2, imm)) } -inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfb_i_p_m(imm, rz1, mem)) } -inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfh_i_p_m(imm, rz1, mem)) } -inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } -inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } -inst_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_z_p_m(rz, rz2, mem)) } -inst_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_z_p_m(rz, rz2, mem)) } -inst_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_z_p_m(rz, rz2, mem)) } -inst_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_z_p_m(rz, rz2, mem)) } -inst_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_z_p_m(rz, rz2, mem)) } -inst_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_z_p_m(rz, rz2, mem)) } -inst_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_z_p_m(rz, rz2, mem)) } -inst_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_z_p_m(rz, rz2, mem)) } -inst_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_index_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } -emit_index_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_z_i_i(rz, imm, imm2)) } -emit_index_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_z_i_r(rz, imm, src)) } -emit_index_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_z_r_i(rz, src, imm)) } -emit_index_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_z_r_r(rz, src, src2)) } -inst_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_pmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_pmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_z_z_z(rz, rz2, rz3)) } -inst_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_z_z_z(rz, rz2, rz3)) } -inst_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_z_z_z(rz, rz2, rz3)) } -inst_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_z_p_z(rz, rz2, rz3)) } -inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } -emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } -inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } -emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } -inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } -emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } -inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } -emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } -inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } -inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } -emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } -inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } -emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } -inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } -emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } -inst_bc_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_EQ, label) } -emit_bc_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_eq_l(label)) } -inst_bc_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NE, label) } -emit_bc_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ne_l(label)) } -inst_bc_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CS, label) } -emit_bc_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cs_l(label)) } -inst_bc_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CC, label) } -emit_bc_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cc_l(label)) } -inst_bc_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_MI, label) } -emit_bc_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_mi_l(label)) } -inst_bc_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_PL, label) } -emit_bc_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_pl_l(label)) } -inst_bc_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VS, label) } -emit_bc_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vs_l(label)) } -inst_bc_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VC, label) } -emit_bc_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vc_l(label)) } -inst_bc_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_HI, label) } -emit_bc_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_hi_l(label)) } -inst_bc_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LS, label) } -emit_bc_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ls_l(label)) } -inst_bc_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GE, label) } -emit_bc_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ge_l(label)) } -inst_bc_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LT, label) } -emit_bc_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_lt_l(label)) } -inst_bc_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GT, label) } -emit_bc_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_gt_l(label)) } -inst_bc_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LE, label) } -emit_bc_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_le_l(label)) } -inst_bc_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_AL, label) } -emit_bc_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_al_l(label)) } -inst_bc_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NV, label) } -emit_bc_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_nv_l(label)) } -inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } -emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } -inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } -emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } -inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } -emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } -inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } -emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } -inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } -emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } -inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } -emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } -inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } -emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } -inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } -emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } -inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } -emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } -inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } -emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } -inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } -emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } -inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } -emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } -inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } -emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } -inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } -emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } -inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } -emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } -inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } -emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } -inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } -emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } -inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } -emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } -inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } -emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } -inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } -emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } -inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } -emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_z_z_z(rz, rz2, rz3)) } -inst_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_z_z_z(rz, rz2, rz3)) } -inst_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_z_z_z(rz, rz2, rz3)) } -inst_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } -emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } -inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } -emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } -inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } -emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } -inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } -emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } -inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } -emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } -inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } -emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } -inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } -emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } -inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } -emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_z_z_z(rz, rz2, rz3)) } -inst_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_luti2_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti2_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_z_z_z_i(rz, rz2, rz3, imm)) } -inst_luti4_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti4_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_z_z_z_i(rz, rz2, rz3, imm)) } -inst_zip_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_zip_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_z_z_z(rz, rz2, rz3)) } -emit_zip_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_z_z(rz, rz2)) } -inst_uzp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_uzp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_z_z_z(rz, rz2, rz3)) } -emit_uzp_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_z_z(rz, rz2)) } -inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } -emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } -inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } -emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } -inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } -emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } -inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } -emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } -inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } -emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } -inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } -emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } -inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } -emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } -inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } -emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } -inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } -emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } -inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } -emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } -inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } -emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } -inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } -emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } -inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } -emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } -inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } -emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } -inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } -emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } -inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } -emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } -inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } -emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } -inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } -emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } -inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } -emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } -inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } -emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } -inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } -emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } -inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } -emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } -inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } -emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } -inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } -emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } -inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } -emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } -inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } -emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } -inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } -emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } -inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } -emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } -inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } -emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } -inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } -emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } -inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } -emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } -inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } -emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } -inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } -emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } -inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } -emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } -inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } -emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } -inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } -emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } -inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } -emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } -inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } -emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } -inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } -emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } -inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } -emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } -inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } -emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } -inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } -emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } -inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } -emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } -inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } -emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } -inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } -emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } -inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } -emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } -inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } -emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } -inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } -emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } -inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } -emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } -inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } -emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } -inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } -emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } -inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } -emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } -inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } -emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } -inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } -emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } -inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } -emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } -inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } -emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } -inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } -emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } -inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } -emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } -inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } -emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } -inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } -emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } -inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } -emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } -inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } -emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } -inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } -emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } -inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } -emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } -inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } -emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } -inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } -emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } -inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } -emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } -inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } -emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } -inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } -emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } -inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } -emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } -inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } -emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } -inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } -emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } -inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } -emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } -inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } -emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } -inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } -emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } -inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } -emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } -inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } -emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } -inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } -emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } -inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } -emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } -inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } -emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } -inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } -emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } -inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } -emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } -emit_prfm_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_i_l(imm, label)) } -inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } -inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } -inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } -inst_cmp_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP, dst, imm) } -emit_cmp_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_r_sh(dst, src, src_shift, src_amount)) } -emit_cmp_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_r_ex(dst, src, src_ext, src_amount)) } -emit_cmp_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_i(dst, imm)) } -inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } -inst_cmn_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN, dst, imm) } -emit_cmn_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_r_sh(dst, src, src_shift, src_amount)) } -emit_cmn_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_r_ex(dst, src, src_ext, src_amount)) } -emit_cmn_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_i(dst, imm)) } +inst_add_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD, dst, src, imm) } +inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_add_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_add_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_add_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_add_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_add_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } +emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +emit_add_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v16b_v16b_v16b(dst, src, src2)) } +emit_add_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v8h_v8h_v8h(dst, src, src2)) } +emit_add_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v4s_v4s_v4s(dst, src, src2)) } +emit_add_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v2d_v2d_v2d(dst, src, src2)) } +emit_add_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v8b_v8b_v8b(dst, src, src2)) } +emit_add_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v4h_v4h_v4h(dst, src, src2)) } +emit_add_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v2s_v2s_v2s(dst, src, src2)) } +emit_add_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_z_z_z(rz, rz2, rz3)) } +emit_add_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } +inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_adds_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_r_r_i(dst, src, imm)) } +emit_adds_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_adds_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_sub_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB, dst, src, imm) } +inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } +emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +emit_sub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v16b_v16b_v16b(dst, src, src2)) } +emit_sub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v8h_v8h_v8h(dst, src, src2)) } +emit_sub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v4s_v4s_v4s(dst, src, src2)) } +emit_sub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v2d_v2d_v2d(dst, src, src2)) } +emit_sub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_z_z_z(rz, rz2, rz3)) } +emit_sub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } +inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_subs_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_r_r_i(dst, src, imm)) } +emit_subs_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_subs_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } +inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } +inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } +inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } +inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } +inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } +inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_and_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_and_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } +emit_and_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v16b_v16b_v16b(dst, src, src2)) } +emit_and_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_and_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } +inst_ands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } +emit_ands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } +inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_orr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_orr_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } +emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } +emit_orr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_orr_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } +inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_eor_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } +emit_eor_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v16b_v16b_v16b(dst, src, src2)) } +emit_eor_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_eor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bic_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_bic_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_bic_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v16b_v16b_v16b(dst, src, src2)) } +emit_bic_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bic_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_bics_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_bics_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_orn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } +emit_orn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } +inst_lsl_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } +emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } +emit_lsl_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } +inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } +inst_lsr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } +emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } +emit_lsr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } +inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } +inst_asr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } +emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } +emit_asr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_asr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_i(dst, src, imm)) } +inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ROR, dst, src, src2) } +inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR, dst, src, imm) } +emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } +emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } +inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } +inst_udiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } +emit_udiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } +inst_sdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } +emit_sdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } +emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } +inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } +emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } +inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } +emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } +inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } +emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } +inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } +emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } +inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } +emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } +inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } +inst_smulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } +emit_smulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } +inst_umulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } +emit_umulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } +inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_clz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } +emit_clz_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8b_v8b(dst, src)) } +emit_clz_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v16b_v16b(dst, src)) } +emit_clz_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v4h_v4h(dst, src)) } +emit_clz_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8h_v8h(dst, src)) } +emit_clz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v2s_v2s(dst, src)) } +emit_clz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v4s_v4s(dst, src)) } +emit_clz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_z_p_z(rz, rz2, rz3)) } +inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } +inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_cls_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } +emit_cls_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8b_v8b(dst, src)) } +emit_cls_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v16b_v16b(dst, src)) } +emit_cls_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v4h_v4h(dst, src)) } +emit_cls_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8h_v8h(dst, src)) } +emit_cls_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v2s_v2s(dst, src)) } +emit_cls_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v4s_v4s(dst, src)) } +emit_cls_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_z_p_z(rz, rz2, rz3)) } +inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } +inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } +emit_rbit_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v8b_v8b(dst, src)) } +emit_rbit_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v16b_v16b(dst, src)) } +inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } +inst_rev_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_rev_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } +emit_rev_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_z_z(rz, rz2)) } +emit_rev_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_p_p(rz, rz2)) } +inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } +inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } +emit_rev16_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v8b_v8b(dst, src)) } +emit_rev16_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v16b_v16b(dst, src)) } +inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } +inst_rev32_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_rev32_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rev32_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_rev32_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } +emit_rev32_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8b_v8b(dst, src)) } +emit_rev32_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v16b_v16b(dst, src)) } +emit_rev32_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v4h_v4h(dst, src)) } +emit_rev32_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8h_v8h(dst, src)) } +inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } +inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } +inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } +inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } +inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } +inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +emit_ccmp_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_r_r_i_c(dst, src, imm, cond)) } +emit_ccmp_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_r_i_i_c(dst, imm, imm2, cond)) } +inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } +inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } +emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } +inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +emit_cset_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_cset_r_c(dst, cond)) } +inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +emit_csetm_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_csetm_r_c(dst, cond)) } +inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cinc_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinc_r_r_c(dst, src, cond)) } +inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cinv_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinv_r_r_c(dst, src, cond)) } +inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +emit_cneg_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cneg_r_r_c(dst, src, cond)) } +inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } +emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } +inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } +emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } +inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } +emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } +inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } +emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } +inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } +emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } +inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } +inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } +emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } +emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } +inst_b_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_EQ, label) } +emit_b_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_eq_l(label)) } +inst_b_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NE, label) } +emit_b_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ne_l(label)) } +inst_b_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CS, label) } +emit_b_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cs_l(label)) } +inst_b_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_CC, label) } +emit_b_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_cc_l(label)) } +inst_b_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_MI, label) } +emit_b_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_mi_l(label)) } +inst_b_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_PL, label) } +emit_b_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_pl_l(label)) } +inst_b_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VS, label) } +emit_b_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vs_l(label)) } +inst_b_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_VC, label) } +emit_b_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_vc_l(label)) } +inst_b_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_HI, label) } +emit_b_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_hi_l(label)) } +inst_b_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LS, label) } +emit_b_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ls_l(label)) } +inst_b_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GE, label) } +emit_b_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_ge_l(label)) } +inst_b_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LT, label) } +emit_b_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_lt_l(label)) } +inst_b_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_GT, label) } +emit_b_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_gt_l(label)) } +inst_b_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_LE, label) } +emit_b_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_le_l(label)) } +inst_b_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_AL, label) } +emit_b_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_al_l(label)) } +inst_b_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NV, label) } +emit_b_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_nv_l(label)) } +inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } +inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } +inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } +inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } +inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } +inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } +emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } +emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } +emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } +emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } +inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } +inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } +emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } +emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } +emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } +inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } +emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } +inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } +emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } +inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } +emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } +inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } +emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } +inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } +emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } +inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } +emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } +inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } +emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } +inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } +emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } +inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } +emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } +inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } +emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } +inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } +emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } +inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } +emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } +inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } +emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } +inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } +emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } +inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } +emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } +inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } +emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } +inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } +emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } +inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } +emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } +inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } +emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } +inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } +emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } +emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } +inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } +emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } +inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } +emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } +inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } +emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } +inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } +emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } +inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } +emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } +inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } +inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}}} } +emit_mrs_r_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, sysreg: System_Register) { append(instructions, inst_mrs_r_s(dst, sysreg)) } +inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } +inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}}} } +emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } +emit_msr_s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, sysreg: System_Register, src: Register) { append(instructions, inst_msr_s_r(sysreg, src)) } +inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } +inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } +inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } +inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } +inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } +inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } +inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } +inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } +inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } +emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } +inst_fmov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV, dst, src) } +inst_fmov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV, dst, imm) } +inst_fmov_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } +emit_fmov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_r_r(dst, src)) } +emit_fmov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_r_i(dst, imm)) } +emit_fmov_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v2s_i(dst, imm)) } +emit_fmov_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v4s_i(dst, imm)) } +emit_fmov_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v2d_i(dst, imm)) } +emit_fmov_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v4h_i(dst, imm)) } +emit_fmov_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v8h_i(dst, imm)) } +inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } +inst_fabs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fabs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } +emit_fabs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2s_v2s(dst, src)) } +emit_fabs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4s_v4s(dst, src)) } +emit_fabs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2d_v2d(dst, src)) } +emit_fabs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4h_v4h(dst, src)) } +emit_fabs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v8h_v8h(dst, src)) } +emit_fabs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_z_p_z(rz, rz2, rz3)) } +inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } +inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fneg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } +emit_fneg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2s_v2s(dst, src)) } +emit_fneg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4s_v4s(dst, src)) } +emit_fneg_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2d_v2d(dst, src)) } +emit_fneg_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4h_v4h(dst, src)) } +emit_fneg_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v8h_v8h(dst, src)) } +emit_fneg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_z_p_z(rz, rz2, rz3)) } +inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } +inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fsqrt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } +emit_fsqrt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2s_v2s(dst, src)) } +emit_fsqrt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4s_v4s(dst, src)) } +emit_fsqrt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2d_v2d(dst, src)) } +emit_fsqrt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4h_v4h(dst, src)) } +emit_fsqrt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v8h_v8h(dst, src)) } +emit_fsqrt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_z_p_z(rz, rz2, rz3)) } +inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } +inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } +emit_fadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2s_v2s_v2s(dst, src, src2)) } +emit_fadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v4s_v4s_v4s(dst, src, src2)) } +emit_fadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2d_v2d_v2d(dst, src, src2)) } +emit_fadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_z_z_z(rz, rz2, rz3)) } +emit_fadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } +inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } +emit_fsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2s_v2s_v2s(dst, src, src2)) } +emit_fsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v4s_v4s_v4s(dst, src, src2)) } +emit_fsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2d_v2d_v2d(dst, src, src2)) } +emit_fsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_z_z_z(rz, rz2, rz3)) } +emit_fsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } +inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } +emit_fmul_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2s_v2s_v2s(dst, src, src2)) } +emit_fmul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v4s_v4s_v4s(dst, src, src2)) } +emit_fmul_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2d_v2d_v2d(dst, src, src2)) } +emit_fmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_z_z_z(rz, rz2, rz3)) } +emit_fmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } +inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } +emit_fdiv_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2s_v2s_v2s(dst, src, src2)) } +emit_fdiv_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v4s_v4s_v4s(dst, src, src2)) } +emit_fdiv_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2d_v2d_v2d(dst, src, src2)) } +emit_fdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } +emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } +inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } +emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } +emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } +emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } +emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } +emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } +inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } +emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } +inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } +inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } +inst_fmax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } +emit_fmax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2s_v2s_v2s(dst, src, src2)) } +emit_fmax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4s_v4s_v4s(dst, src, src2)) } +emit_fmax_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2d_v2d_v2d(dst, src, src2)) } +emit_fmax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4h_v4h_v4h(dst, src, src2)) } +emit_fmax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v8h_v8h_v8h(dst, src, src2)) } +emit_fmax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } +inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } +emit_fmin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2s_v2s_v2s(dst, src, src2)) } +emit_fmin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4s_v4s_v4s(dst, src, src2)) } +emit_fmin_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2d_v2d_v2d(dst, src, src2)) } +emit_fmin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4h_v4h_v4h(dst, src, src2)) } +emit_fmin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v8h_v8h_v8h(dst, src, src2)) } +emit_fmin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } +inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } +emit_fmaxnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2s_v2s_v2s(dst, src, src2)) } +emit_fmaxnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4s_v4s_v4s(dst, src, src2)) } +emit_fmaxnm_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2d_v2d_v2d(dst, src, src2)) } +emit_fmaxnm_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4h_v4h_v4h(dst, src, src2)) } +emit_fmaxnm_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v8h_v8h_v8h(dst, src, src2)) } +emit_fmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } +inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } +emit_fminnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2s_v2s_v2s(dst, src, src2)) } +emit_fminnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4s_v4s_v4s(dst, src, src2)) } +emit_fminnm_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2d_v2d_v2d(dst, src, src2)) } +emit_fminnm_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4h_v4h_v4h(dst, src, src2)) } +emit_fminnm_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v8h_v8h_v8h(dst, src, src2)) } +emit_fminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } +emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } +inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } +inst_scvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_scvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_scvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_scvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_scvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } +emit_scvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v2s_v2s(dst, src)) } +emit_scvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4s_v4s(dst, src)) } +emit_scvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v2d_v2d(dst, src)) } +emit_scvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4h_v4h(dst, src)) } +emit_scvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v8h_v8h(dst, src)) } +inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } +inst_ucvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_ucvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_ucvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_ucvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_ucvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } +emit_ucvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v2s_v2s(dst, src)) } +emit_ucvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4s_v4s(dst, src)) } +emit_ucvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v2d_v2d(dst, src)) } +emit_ucvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4h_v4h(dst, src)) } +emit_ucvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v8h_v8h(dst, src)) } +inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } +inst_fcvtzs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtzs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtzs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtzs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtzs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } +emit_fcvtzs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v2s_v2s(dst, src)) } +emit_fcvtzs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4s_v4s(dst, src)) } +emit_fcvtzs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v2d_v2d(dst, src)) } +emit_fcvtzs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4h_v4h(dst, src)) } +emit_fcvtzs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v8h_v8h(dst, src)) } +inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } +inst_fcvtzu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtzu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtzu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtzu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtzu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } +emit_fcvtzu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v2s_v2s(dst, src)) } +emit_fcvtzu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4s_v4s(dst, src)) } +emit_fcvtzu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v2d_v2d(dst, src)) } +emit_fcvtzu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4h_v4h(dst, src)) } +emit_fcvtzu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v8h_v8h(dst, src)) } +inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } +inst_fcvtas_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtas_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtas_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtas_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtas_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } +emit_fcvtas_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v2s_v2s(dst, src)) } +emit_fcvtas_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4s_v4s(dst, src)) } +emit_fcvtas_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v2d_v2d(dst, src)) } +emit_fcvtas_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4h_v4h(dst, src)) } +emit_fcvtas_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v8h_v8h(dst, src)) } +inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } +inst_fcvtau_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtau_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtau_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtau_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtau_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } +emit_fcvtau_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v2s_v2s(dst, src)) } +emit_fcvtau_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4s_v4s(dst, src)) } +emit_fcvtau_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v2d_v2d(dst, src)) } +emit_fcvtau_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4h_v4h(dst, src)) } +emit_fcvtau_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v8h_v8h(dst, src)) } +inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } +inst_fcvtns_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtns_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtns_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtns_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtns_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } +emit_fcvtns_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v2s_v2s(dst, src)) } +emit_fcvtns_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4s_v4s(dst, src)) } +emit_fcvtns_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v2d_v2d(dst, src)) } +emit_fcvtns_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4h_v4h(dst, src)) } +emit_fcvtns_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v8h_v8h(dst, src)) } +inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } +inst_fcvtnu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtnu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtnu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtnu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtnu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } +emit_fcvtnu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v2s_v2s(dst, src)) } +emit_fcvtnu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4s_v4s(dst, src)) } +emit_fcvtnu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v2d_v2d(dst, src)) } +emit_fcvtnu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4h_v4h(dst, src)) } +emit_fcvtnu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v8h_v8h(dst, src)) } +inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } +inst_fcvtps_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtps_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtps_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtps_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtps_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } +emit_fcvtps_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v2s_v2s(dst, src)) } +emit_fcvtps_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4s_v4s(dst, src)) } +emit_fcvtps_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v2d_v2d(dst, src)) } +emit_fcvtps_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4h_v4h(dst, src)) } +emit_fcvtps_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v8h_v8h(dst, src)) } +inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } +inst_fcvtpu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtpu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtpu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtpu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtpu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } +emit_fcvtpu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v2s_v2s(dst, src)) } +emit_fcvtpu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4s_v4s(dst, src)) } +emit_fcvtpu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v2d_v2d(dst, src)) } +emit_fcvtpu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4h_v4h(dst, src)) } +emit_fcvtpu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v8h_v8h(dst, src)) } +inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } +inst_fcvtms_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtms_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtms_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtms_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtms_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } +emit_fcvtms_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v2s_v2s(dst, src)) } +emit_fcvtms_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4s_v4s(dst, src)) } +emit_fcvtms_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v2d_v2d(dst, src)) } +emit_fcvtms_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4h_v4h(dst, src)) } +emit_fcvtms_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v8h_v8h(dst, src)) } +inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } +inst_fcvtmu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcvtmu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcvtmu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcvtmu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcvtmu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } +emit_fcvtmu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v2s_v2s(dst, src)) } +emit_fcvtmu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4s_v4s(dst, src)) } +emit_fcvtmu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v2d_v2d(dst, src)) } +emit_fcvtmu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4h_v4h(dst, src)) } +emit_fcvtmu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v8h_v8h(dst, src)) } +inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } +inst_frinta_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } +emit_frinta_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2s_v2s(dst, src)) } +emit_frinta_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4s_v4s(dst, src)) } +emit_frinta_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2d_v2d(dst, src)) } +emit_frinta_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4h_v4h(dst, src)) } +emit_frinta_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v8h_v8h(dst, src)) } +emit_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_z_p_z(rz, rz2, rz3)) } +inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } +inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } +emit_frinti_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2s_v2s(dst, src)) } +emit_frinti_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4s_v4s(dst, src)) } +emit_frinti_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2d_v2d(dst, src)) } +emit_frinti_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4h_v4h(dst, src)) } +emit_frinti_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v8h_v8h(dst, src)) } +emit_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_z_p_z(rz, rz2, rz3)) } +inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } +inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } +emit_frintm_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2s_v2s(dst, src)) } +emit_frintm_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4s_v4s(dst, src)) } +emit_frintm_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2d_v2d(dst, src)) } +emit_frintm_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4h_v4h(dst, src)) } +emit_frintm_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v8h_v8h(dst, src)) } +emit_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_z_p_z(rz, rz2, rz3)) } +inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } +inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } +emit_frintn_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2s_v2s(dst, src)) } +emit_frintn_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4s_v4s(dst, src)) } +emit_frintn_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2d_v2d(dst, src)) } +emit_frintn_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4h_v4h(dst, src)) } +emit_frintn_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v8h_v8h(dst, src)) } +emit_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_z_p_z(rz, rz2, rz3)) } +inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } +inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } +emit_frintp_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2s_v2s(dst, src)) } +emit_frintp_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4s_v4s(dst, src)) } +emit_frintp_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2d_v2d(dst, src)) } +emit_frintp_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4h_v4h(dst, src)) } +emit_frintp_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v8h_v8h(dst, src)) } +emit_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_z_p_z(rz, rz2, rz3)) } +inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } +inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } +emit_frintx_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2s_v2s(dst, src)) } +emit_frintx_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4s_v4s(dst, src)) } +emit_frintx_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2d_v2d(dst, src)) } +emit_frintx_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4h_v4h(dst, src)) } +emit_frintx_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v8h_v8h(dst, src)) } +emit_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_z_p_z(rz, rz2, rz3)) } +inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } +inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } +emit_frintz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2s_v2s(dst, src)) } +emit_frintz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4s_v4s(dst, src)) } +emit_frintz_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2d_v2d(dst, src)) } +emit_frintz_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4h_v4h(dst, src)) } +emit_frintz_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v8h_v8h(dst, src)) } +emit_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_z_p_z(rz, rz2, rz3)) } +inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } +inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } +emit_tst_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_r_sh(dst, src, src_shift, src_amount)) } +inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } +emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } +inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } +emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } +inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } +emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } +inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } +emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } +inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } +emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } +inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } +emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } +inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } +emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } +inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } +emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } +inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } +emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } +inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } +emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } +inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } +emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } +inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } +emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } +inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } +emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } +inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } +emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } +inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } +emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } +inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } +emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } +inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } +emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } +inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } +emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } +inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } +emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } +inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } +emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } +inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } +emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } +inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } +emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } +inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } +emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } +inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } +emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } +inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } +emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } +inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } +emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } +inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } +emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } +inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } +emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } +inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } +emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } +inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } +emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } +inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } +emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } +inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } +emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } +inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } +emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } +inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } +emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } +inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } +emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } +inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } +emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } +inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } +emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } +inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } +emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } +inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } +emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } +inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } +emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } +inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } +emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } +inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } +emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } +inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } +emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } +inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } +emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } +inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } +emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } +inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } +emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } +inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } +emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } +inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } +emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } +inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } +emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } +inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } +emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } +inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } +emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } +inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } +emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } +inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } +emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } +inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } +emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } +inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } +emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } +inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } +emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } +inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } +emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } +inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } +emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } +inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } +emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } +inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } +emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } +inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } +emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } +inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } +emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } +inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } +emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } +inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } +emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } +inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } +emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } +inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } +emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } +inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } +emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } +inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } +emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } +inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } +emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } +inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } +emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } +inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } +emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } +inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } +emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } +inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } +emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } +inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } +emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } +inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } +emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } +inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } +emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } +inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } +emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } +inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } +emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } +inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } +emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } +inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } +emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } +inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } +emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } +inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } +emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } +inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } +emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } +inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } +emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } +inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } +emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } +inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } +emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } +inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } +emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } +inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } +emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } +inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } +emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } +inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } +emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } +inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } +emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } +inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } +emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } +inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } +emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } +inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } +emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } +inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } +emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } +inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } +emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } +inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } +emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } +inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } +emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } +inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } +emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } +inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } +emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } +inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } +emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } +inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } +emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } +inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } +emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } +inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } +emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } +inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } +emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } +inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } +emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } +inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } +emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } +inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } +emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } +inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } +emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } +inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } +emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } +inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } +emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } +inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } +emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } +inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } +emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } +inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } +emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } +inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } +emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } +inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } +emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } +inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } +inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } +emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } +inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } +inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } +inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } +emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } +inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } +emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } +inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } +emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } +inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } +emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } +inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } +emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } +inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } +emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } +inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } +emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } +inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } +emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } +inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } +emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } +inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } +emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } +inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } +emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } +inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } +emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } +inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } +emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } +inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } +emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } +inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } +emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } +inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } +emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } +inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } +emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } +inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } +emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } +inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } +emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } +inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } +emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } +inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_aese_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_v16b_v16b(dst, src)) } +emit_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_z_z(rz, rz2)) } +inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_aesd_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_v16b_v16b(dst, src)) } +emit_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_z_z(rz, rz2)) } +inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_aesmc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_v16b_v16b(dst, src)) } +emit_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_z(rz)) } +inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_aesimc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_v16b_v16b(dst, src)) } +emit_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_z(rz)) } +inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } +emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } +inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +emit_sha1c_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_v4s(dst, src, src2)) } +inst_sha1p_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +emit_sha1p_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_v4s(dst, src, src2)) } +inst_sha1m_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +emit_sha1m_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_v4s(dst, src, src2)) } +inst_sha1su0_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sha1su0_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_v4s_v4s_v4s(dst, src, src2)) } +inst_sha1su1_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_sha1su1_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_v4s_v4s(dst, src)) } +inst_sha256h_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +emit_sha256h_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_v4s(dst, src, src2)) } +inst_sha256h2_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +emit_sha256h2_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_v4s(dst, src, src2)) } +inst_sha256su0_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_sha256su0_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_v4s_v4s(dst, src)) } +inst_sha256su1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sha256su1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_v4s_v4s_v4s(dst, src, src2)) } +inst_sha512h_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +emit_sha512h_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_v2d(dst, src, src2)) } +inst_sha512h2_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +emit_sha512h2_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_v2d(dst, src, src2)) } +inst_sha512su0_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +emit_sha512su0_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_v2d_v2d(dst, src)) } +inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_sha512su1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_v2d_v2d_v2d(dst, src, src2)) } +inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } +inst_eor3_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_eor3_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } +emit_eor3_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } +inst_bcax_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bcax_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } +emit_bcax_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_rax1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_v2d_v2d_v2d(dst, src, src2)) } +inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +emit_xar_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_v2d_v2d_v2d_i(dst, src, src2, imm)) } +emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sm3partw1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_v4s_v4s_v4s(dst, src, src2)) } +inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sm3partw2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_v4s_v4s_v4s(dst, src, src2)) } +inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3)}} } +emit_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_v4s_v4s_v4s_v4s(dst, src, src2, src3)) } +inst_sm3tt1a_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } +emit_sm3tt1a_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_v4s_v4s_ves(dst, src, src2)) } +inst_sm3tt1b_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } +emit_sm3tt1b_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_v4s_v4s_ves(dst, src, src2)) } +inst_sm3tt2a_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } +emit_sm3tt2a_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_v4s_v4s_ves(dst, src, src2)) } +inst_sm3tt2b_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } +emit_sm3tt2b_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_v4s_v4s_ves(dst, src, src2)) } +inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_sm4e_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_v4s_v4s(dst, src)) } +inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sm4ekey_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_v4s_v4s_v4s(dst, src, src2)) } +inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_pmull_v2d_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_1d(src), op_v_1d(src2), {}}} } +emit_pmull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v8h_v8b_v8b(dst, src, src2)) } +emit_pmull_v2d_v1d_v1d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v2d_v1d_v1d(dst, src, src2)) } +inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_pmull2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_pmull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v8h_v16b_v16b(dst, src, src2)) } +emit_pmull2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v2d_v2d_v2d(dst, src, src2)) } +inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } +inst_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } +emit_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_z_p_z(rz, rz2, rz3)) } +inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_bfdot_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_v4s_v8h_v8h(dst, src, src2)) } +inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_bfmmla_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_v4s_v8h_v8h(dst, src, src2)) } +inst_bfmlalb_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_bfmlalb_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_v4s_v8h_v8h(dst, src, src2)) } +inst_bfmlalt_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_bfmlalt_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_v4s_v8h_v8h(dst, src, src2)) } +inst_bfcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +emit_bfcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_v4h_v4s(dst, src)) } +inst_bfcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +emit_bfcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_v8h_v4s(dst, src)) } +inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_mul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_mul_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v16b_v16b_v16b(dst, src, src2)) } +emit_mul_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v8h_v8h_v8h(dst, src, src2)) } +emit_mul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v4s_v4s_v4s(dst, src, src2)) } +emit_mul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_mla_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_mla_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_mla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_mla_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8b_v8b_v8b(dst, src, src2)) } +emit_mla_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v16b_v16b_v16b(dst, src, src2)) } +emit_mla_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4h_v4h_v4h(dst, src, src2)) } +emit_mla_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8h_v8h_v8h(dst, src, src2)) } +emit_mla_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v2s_v2s_v2s(dst, src, src2)) } +emit_mla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4s_v4s_v4s(dst, src, src2)) } +inst_mls_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_mls_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_mls_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_mls_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_mls_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_mls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_mls_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8b_v8b_v8b(dst, src, src2)) } +emit_mls_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v16b_v16b_v16b(dst, src, src2)) } +emit_mls_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4h_v4h_v4h(dst, src, src2)) } +emit_mls_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8h_v8h_v8h(dst, src, src2)) } +emit_mls_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v2s_v2s_v2s(dst, src, src2)) } +emit_mls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4s_v4s_v4s(dst, src, src2)) } +inst_neg_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_neg_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_neg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_neg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_neg_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v8b_v8b(dst, src)) } +emit_neg_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v16b_v16b(dst, src)) } +emit_neg_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v4h_v4h(dst, src)) } +emit_neg_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v8h_v8h(dst, src)) } +emit_neg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v2s_v2s(dst, src)) } +emit_neg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v4s_v4s(dst, src)) } +emit_neg_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v2d_v2d(dst, src)) } +emit_neg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_z_p_z(rz, rz2, rz3)) } +emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } +inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_abs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_abs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_abs_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v8b_v8b(dst, src)) } +emit_abs_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v16b_v16b(dst, src)) } +emit_abs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4h_v4h(dst, src)) } +emit_abs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v8h_v8h(dst, src)) } +emit_abs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v2s_v2s(dst, src)) } +emit_abs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4s_v4s(dst, src)) } +emit_abs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v2d_v2d(dst, src)) } +emit_abs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_z_p_z(rz, rz2, rz3)) } +inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_shadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_shadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_shadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_shadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8b_v8b_v8b(dst, src, src2)) } +emit_shadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v16b_v16b_v16b(dst, src, src2)) } +emit_shadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4h_v4h_v4h(dst, src, src2)) } +emit_shadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8h_v8h_v8h(dst, src, src2)) } +emit_shadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v2s_v2s_v2s(dst, src, src2)) } +emit_shadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4s_v4s_v4s(dst, src, src2)) } +inst_uhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_uhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8b_v8b_v8b(dst, src, src2)) } +emit_uhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v16b_v16b_v16b(dst, src, src2)) } +emit_uhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4h_v4h_v4h(dst, src, src2)) } +emit_uhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8h_v8h_v8h(dst, src, src2)) } +emit_uhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v2s_v2s_v2s(dst, src, src2)) } +emit_uhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4s_v4s_v4s(dst, src, src2)) } +inst_shsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_shsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_shsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_shsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_shsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_shsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_shsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8b_v8b_v8b(dst, src, src2)) } +emit_shsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v16b_v16b_v16b(dst, src, src2)) } +emit_shsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4h_v4h_v4h(dst, src, src2)) } +emit_shsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8h_v8h_v8h(dst, src, src2)) } +emit_shsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v2s_v2s_v2s(dst, src, src2)) } +emit_shsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4s_v4s_v4s(dst, src, src2)) } +inst_uhsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uhsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uhsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uhsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uhsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uhsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_uhsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8b_v8b_v8b(dst, src, src2)) } +emit_uhsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v16b_v16b_v16b(dst, src, src2)) } +emit_uhsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4h_v4h_v4h(dst, src, src2)) } +emit_uhsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8h_v8h_v8h(dst, src, src2)) } +emit_uhsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v2s_v2s_v2s(dst, src, src2)) } +emit_uhsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4s_v4s_v4s(dst, src, src2)) } +inst_srhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_srhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_srhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_srhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_srhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_srhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_srhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8b_v8b_v8b(dst, src, src2)) } +emit_srhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v16b_v16b_v16b(dst, src, src2)) } +emit_srhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4h_v4h_v4h(dst, src, src2)) } +emit_srhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8h_v8h_v8h(dst, src, src2)) } +emit_srhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v2s_v2s_v2s(dst, src, src2)) } +emit_srhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4s_v4s_v4s(dst, src, src2)) } +inst_urhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_urhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_urhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_urhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_urhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_urhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_urhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8b_v8b_v8b(dst, src, src2)) } +emit_urhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v16b_v16b_v16b(dst, src, src2)) } +emit_urhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4h_v4h_v4h(dst, src, src2)) } +emit_urhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8h_v8h_v8h(dst, src, src2)) } +emit_urhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v2s_v2s_v2s(dst, src, src2)) } +emit_urhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4s_v4s_v4s(dst, src, src2)) } +inst_sqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v8b_v8b_v8b(dst, src, src2)) } +emit_sqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v16b_v16b_v16b(dst, src, src2)) } +emit_sqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4h_v4h_v4h(dst, src, src2)) } +emit_sqadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v8h_v8h_v8h(dst, src, src2)) } +emit_sqadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v2s_v2s_v2s(dst, src, src2)) } +emit_sqadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4s_v4s_v4s(dst, src, src2)) } +emit_sqadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v2d_v2d_v2d(dst, src, src2)) } +emit_sqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_z_z_z(rz, rz2, rz3)) } +inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_uqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_uqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v8b_v8b_v8b(dst, src, src2)) } +emit_uqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v16b_v16b_v16b(dst, src, src2)) } +emit_uqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4h_v4h_v4h(dst, src, src2)) } +emit_uqadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v8h_v8h_v8h(dst, src, src2)) } +emit_uqadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v2s_v2s_v2s(dst, src, src2)) } +emit_uqadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4s_v4s_v4s(dst, src, src2)) } +emit_uqadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v2d_v2d_v2d(dst, src, src2)) } +emit_uqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_z_z_z(rz, rz2, rz3)) } +inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v8b_v8b_v8b(dst, src, src2)) } +emit_sqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v16b_v16b_v16b(dst, src, src2)) } +emit_sqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4h_v4h_v4h(dst, src, src2)) } +emit_sqsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v8h_v8h_v8h(dst, src, src2)) } +emit_sqsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v2s_v2s_v2s(dst, src, src2)) } +emit_sqsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4s_v4s_v4s(dst, src, src2)) } +emit_sqsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v2d_v2d_v2d(dst, src, src2)) } +emit_sqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_z_z_z(rz, rz2, rz3)) } +inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_uqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_uqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v8b_v8b_v8b(dst, src, src2)) } +emit_uqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v16b_v16b_v16b(dst, src, src2)) } +emit_uqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4h_v4h_v4h(dst, src, src2)) } +emit_uqsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v8h_v8h_v8h(dst, src, src2)) } +emit_uqsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v2s_v2s_v2s(dst, src, src2)) } +emit_uqsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4s_v4s_v4s(dst, src, src2)) } +emit_uqsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v2d_v2d_v2d(dst, src, src2)) } +emit_uqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_z_z_z(rz, rz2, rz3)) } +inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8b_v8b_v8b(dst, src, src2)) } +emit_smax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v16b_v16b_v16b(dst, src, src2)) } +emit_smax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4h_v4h_v4h(dst, src, src2)) } +emit_smax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8h_v8h_v8h(dst, src, src2)) } +emit_smax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v2s_v2s_v2s(dst, src, src2)) } +emit_smax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4s_v4s_v4s(dst, src, src2)) } +emit_smax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8b_v8b_v8b(dst, src, src2)) } +emit_umax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v16b_v16b_v16b(dst, src, src2)) } +emit_umax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4h_v4h_v4h(dst, src, src2)) } +emit_umax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8h_v8h_v8h(dst, src, src2)) } +emit_umax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v2s_v2s_v2s(dst, src, src2)) } +emit_umax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4s_v4s_v4s(dst, src, src2)) } +emit_umax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_smin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8b_v8b_v8b(dst, src, src2)) } +emit_smin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v16b_v16b_v16b(dst, src, src2)) } +emit_smin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4h_v4h_v4h(dst, src, src2)) } +emit_smin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8h_v8h_v8h(dst, src, src2)) } +emit_smin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v2s_v2s_v2s(dst, src, src2)) } +emit_smin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4s_v4s_v4s(dst, src, src2)) } +emit_smin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_umin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8b_v8b_v8b(dst, src, src2)) } +emit_umin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v16b_v16b_v16b(dst, src, src2)) } +emit_umin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4h_v4h_v4h(dst, src, src2)) } +emit_umin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8h_v8h_v8h(dst, src, src2)) } +emit_umin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v2s_v2s_v2s(dst, src, src2)) } +emit_umin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4s_v4s_v4s(dst, src, src2)) } +emit_umin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8b_v8b_v8b(dst, src, src2)) } +emit_sabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v16b_v16b_v16b(dst, src, src2)) } +emit_sabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4h_v4h_v4h(dst, src, src2)) } +emit_sabd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8h_v8h_v8h(dst, src, src2)) } +emit_sabd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v2s_v2s_v2s(dst, src, src2)) } +emit_sabd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4s_v4s_v4s(dst, src, src2)) } +emit_sabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_uabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8b_v8b_v8b(dst, src, src2)) } +emit_uabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v16b_v16b_v16b(dst, src, src2)) } +emit_uabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4h_v4h_v4h(dst, src, src2)) } +emit_uabd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8h_v8h_v8h(dst, src, src2)) } +emit_uabd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v2s_v2s_v2s(dst, src, src2)) } +emit_uabd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4s_v4s_v4s(dst, src, src2)) } +emit_uabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_saba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_saba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_saba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_saba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8b_v8b_v8b(dst, src, src2)) } +emit_saba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v16b_v16b_v16b(dst, src, src2)) } +emit_saba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4h_v4h_v4h(dst, src, src2)) } +emit_saba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8h_v8h_v8h(dst, src, src2)) } +emit_saba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v2s_v2s_v2s(dst, src, src2)) } +emit_saba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4s_v4s_v4s(dst, src, src2)) } +inst_uaba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uaba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uaba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uaba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uaba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uaba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_uaba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8b_v8b_v8b(dst, src, src2)) } +emit_uaba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v16b_v16b_v16b(dst, src, src2)) } +emit_uaba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4h_v4h_v4h(dst, src, src2)) } +emit_uaba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8h_v8h_v8h(dst, src, src2)) } +emit_uaba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v2s_v2s_v2s(dst, src, src2)) } +emit_uaba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4s_v4s_v4s(dst, src, src2)) } +inst_addp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_addp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_addp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_addp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_addp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_addp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_addp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_addp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v8b_v8b_v8b(dst, src, src2)) } +emit_addp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v16b_v16b_v16b(dst, src, src2)) } +emit_addp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4h_v4h_v4h(dst, src, src2)) } +emit_addp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v8h_v8h_v8h(dst, src, src2)) } +emit_addp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2s_v2s_v2s(dst, src, src2)) } +emit_addp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4s_v4s_v4s(dst, src, src2)) } +emit_addp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2d_v2d_v2d(dst, src, src2)) } +inst_addv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_addv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_addv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_addv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_addv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_addv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8b(dst, src)) } +emit_addv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v16b(dst, src)) } +emit_addv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4h(dst, src)) } +emit_addv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8h(dst, src)) } +emit_addv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4s(dst, src)) } +inst_saddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } +inst_saddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_saddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } +inst_saddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_saddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } +inst_saddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_saddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4h_v8b(dst, src)) } +emit_saddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v8h_v16b(dst, src)) } +emit_saddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2s_v4h(dst, src)) } +emit_saddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4s_v8h(dst, src)) } +emit_saddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v1d_v2s(dst, src)) } +emit_saddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2d_v4s(dst, src)) } +inst_uaddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } +inst_uaddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_uaddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } +inst_uaddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_uaddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } +inst_uaddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_uaddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4h_v8b(dst, src)) } +emit_uaddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v8h_v16b(dst, src)) } +emit_uaddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2s_v4h(dst, src)) } +emit_uaddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4s_v8h(dst, src)) } +emit_uaddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v1d_v2s(dst, src)) } +emit_uaddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2d_v4s(dst, src)) } +inst_sadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } +inst_sadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_sadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } +inst_sadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_sadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } +inst_sadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_sadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4h_v8b(dst, src)) } +emit_sadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v8h_v16b(dst, src)) } +emit_sadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2s_v4h(dst, src)) } +emit_sadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4s_v8h(dst, src)) } +emit_sadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v1d_v2s(dst, src)) } +emit_sadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2d_v4s(dst, src)) } +inst_uadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } +inst_uadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_uadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } +inst_uadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_uadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } +inst_uadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_uadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4h_v8b(dst, src)) } +emit_uadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v8h_v16b(dst, src)) } +emit_uadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2s_v4h(dst, src)) } +emit_uadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4s_v8h(dst, src)) } +emit_uadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v1d_v2s(dst, src)) } +emit_uadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2d_v4s(dst, src)) } +inst_saddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_saddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_saddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_saddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_saddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_saddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8b(dst, src)) } +emit_saddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v16b(dst, src)) } +emit_saddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4h(dst, src)) } +emit_saddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8h(dst, src)) } +emit_saddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4s(dst, src)) } +inst_uaddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_uaddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_uaddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_uaddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_uaddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_uaddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8b(dst, src)) } +emit_uaddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v16b(dst, src)) } +emit_uaddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4h(dst, src)) } +emit_uaddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8h(dst, src)) } +emit_uaddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4s(dst, src)) } +inst_smaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_smaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_smaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_smaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_smaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_smaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8b(dst, src)) } +emit_smaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v16b(dst, src)) } +emit_smaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4h(dst, src)) } +emit_smaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8h(dst, src)) } +emit_smaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4s(dst, src)) } +inst_umaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_umaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_umaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_umaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_umaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_umaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8b(dst, src)) } +emit_umaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v16b(dst, src)) } +emit_umaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4h(dst, src)) } +emit_umaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8h(dst, src)) } +emit_umaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4s(dst, src)) } +inst_sminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_sminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_sminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_sminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_sminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_sminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8b(dst, src)) } +emit_sminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v16b(dst, src)) } +emit_sminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4h(dst, src)) } +emit_sminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8h(dst, src)) } +emit_sminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4s(dst, src)) } +inst_uminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } +inst_uminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } +inst_uminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_uminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_uminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +emit_uminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8b(dst, src)) } +emit_uminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v16b(dst, src)) } +emit_uminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4h(dst, src)) } +emit_uminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8h(dst, src)) } +emit_uminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4s(dst, src)) } +inst_smaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_smaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8b_v8b_v8b(dst, src, src2)) } +emit_smaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v16b_v16b_v16b(dst, src, src2)) } +emit_smaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4h_v4h_v4h(dst, src, src2)) } +emit_smaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8h_v8h_v8h(dst, src, src2)) } +emit_smaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v2s_v2s_v2s(dst, src, src2)) } +emit_smaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4s_v4s_v4s(dst, src, src2)) } +inst_umaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_umaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8b_v8b_v8b(dst, src, src2)) } +emit_umaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v16b_v16b_v16b(dst, src, src2)) } +emit_umaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4h_v4h_v4h(dst, src, src2)) } +emit_umaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8h_v8h_v8h(dst, src, src2)) } +emit_umaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v2s_v2s_v2s(dst, src, src2)) } +emit_umaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4s_v4s_v4s(dst, src, src2)) } +inst_sminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8b_v8b_v8b(dst, src, src2)) } +emit_sminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v16b_v16b_v16b(dst, src, src2)) } +emit_sminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4h_v4h_v4h(dst, src, src2)) } +emit_sminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8h_v8h_v8h(dst, src, src2)) } +emit_sminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v2s_v2s_v2s(dst, src, src2)) } +emit_sminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4s_v4s_v4s(dst, src, src2)) } +inst_uminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_uminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8b_v8b_v8b(dst, src, src2)) } +emit_uminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v16b_v16b_v16b(dst, src, src2)) } +emit_uminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4h_v4h_v4h(dst, src, src2)) } +emit_uminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8h_v8h_v8h(dst, src, src2)) } +emit_uminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v2s_v2s_v2s(dst, src, src2)) } +emit_uminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4s_v4s_v4s(dst, src, src2)) } +inst_saddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_saddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_saddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_saddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v8h_v8b_v8b(dst, src, src2)) } +emit_saddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v4s_v4h_v4h(dst, src, src2)) } +emit_saddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v2d_v2s_v2s(dst, src, src2)) } +inst_saddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_saddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_saddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_saddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v8h_v16b_v16b(dst, src, src2)) } +emit_saddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v4s_v8h_v8h(dst, src, src2)) } +emit_saddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v2d_v4s_v4s(dst, src, src2)) } +inst_uaddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uaddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uaddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_uaddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v8h_v8b_v8b(dst, src, src2)) } +emit_uaddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v4s_v4h_v4h(dst, src, src2)) } +emit_uaddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v2d_v2s_v2s(dst, src, src2)) } +inst_uaddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uaddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uaddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_uaddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v8h_v16b_v16b(dst, src, src2)) } +emit_uaddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v4s_v8h_v8h(dst, src, src2)) } +emit_uaddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v2d_v4s_v4s(dst, src, src2)) } +inst_ssubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_ssubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_ssubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_ssubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v8h_v8b_v8b(dst, src, src2)) } +emit_ssubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v4s_v4h_v4h(dst, src, src2)) } +emit_ssubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v2d_v2s_v2s(dst, src, src2)) } +inst_ssubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_ssubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_ssubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_ssubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v8h_v16b_v16b(dst, src, src2)) } +emit_ssubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v4s_v8h_v8h(dst, src, src2)) } +emit_ssubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v2d_v4s_v4s(dst, src, src2)) } +inst_usubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_usubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_usubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_usubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v8h_v8b_v8b(dst, src, src2)) } +emit_usubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v4s_v4h_v4h(dst, src, src2)) } +emit_usubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v2d_v2s_v2s(dst, src, src2)) } +inst_usubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_usubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_usubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_usubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v8h_v16b_v16b(dst, src, src2)) } +emit_usubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v4s_v8h_v8h(dst, src, src2)) } +emit_usubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v2d_v4s_v4s(dst, src, src2)) } +inst_saddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } +inst_saddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } +inst_saddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +emit_saddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v8h_v8h_v8b(dst, src, src2)) } +emit_saddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v4s_v4s_v4h(dst, src, src2)) } +emit_saddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v2d_v2d_v2s(dst, src, src2)) } +inst_saddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } +inst_saddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } +inst_saddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +emit_saddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v8h_v8h_v16b(dst, src, src2)) } +emit_saddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v4s_v4s_v8h(dst, src, src2)) } +emit_saddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v2d_v2d_v4s(dst, src, src2)) } +inst_uaddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } +inst_uaddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } +inst_uaddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +emit_uaddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v8h_v8h_v8b(dst, src, src2)) } +emit_uaddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v4s_v4s_v4h(dst, src, src2)) } +emit_uaddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v2d_v2d_v2s(dst, src, src2)) } +inst_uaddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } +inst_uaddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } +inst_uaddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +emit_uaddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v8h_v8h_v16b(dst, src, src2)) } +emit_uaddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v4s_v4s_v8h(dst, src, src2)) } +emit_uaddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v2d_v2d_v4s(dst, src, src2)) } +inst_ssubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } +inst_ssubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } +inst_ssubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +emit_ssubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v8h_v8h_v8b(dst, src, src2)) } +emit_ssubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v4s_v4s_v4h(dst, src, src2)) } +emit_ssubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v2d_v2d_v2s(dst, src, src2)) } +inst_ssubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } +inst_ssubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } +inst_ssubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +emit_ssubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v8h_v8h_v16b(dst, src, src2)) } +emit_ssubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v4s_v4s_v8h(dst, src, src2)) } +emit_ssubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v2d_v2d_v4s(dst, src, src2)) } +inst_usubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } +inst_usubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } +inst_usubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +emit_usubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v8h_v8h_v8b(dst, src, src2)) } +emit_usubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v4s_v4s_v4h(dst, src, src2)) } +emit_usubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v2d_v2d_v2s(dst, src, src2)) } +inst_usubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } +inst_usubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } +inst_usubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +emit_usubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v8h_v8h_v16b(dst, src, src2)) } +emit_usubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v4s_v4s_v8h(dst, src, src2)) } +emit_usubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v2d_v2d_v4s(dst, src, src2)) } +inst_raddhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_raddhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_raddhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_raddhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v8b_v8h_v8h(dst, src, src2)) } +emit_raddhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v4h_v4s_v4s(dst, src, src2)) } +emit_raddhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v2s_v2d_v2d(dst, src, src2)) } +inst_raddhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_raddhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_raddhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_raddhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v16b_v8h_v8h(dst, src, src2)) } +emit_raddhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v8h_v4s_v4s(dst, src, src2)) } +emit_raddhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v4s_v2d_v2d(dst, src, src2)) } +inst_rsubhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_rsubhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_rsubhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_rsubhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v8b_v8h_v8h(dst, src, src2)) } +emit_rsubhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v4h_v4s_v4s(dst, src, src2)) } +emit_rsubhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v2s_v2d_v2d(dst, src, src2)) } +inst_rsubhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_rsubhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_rsubhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_rsubhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v16b_v8h_v8h(dst, src, src2)) } +emit_rsubhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v8h_v4s_v4s(dst, src, src2)) } +emit_rsubhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v4s_v2d_v2d(dst, src, src2)) } +inst_addhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_addhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_addhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_addhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v8b_v8h_v8h(dst, src, src2)) } +emit_addhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v4h_v4s_v4s(dst, src, src2)) } +emit_addhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v2s_v2d_v2d(dst, src, src2)) } +inst_addhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_addhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_addhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_addhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v16b_v8h_v8h(dst, src, src2)) } +emit_addhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v8h_v4s_v4s(dst, src, src2)) } +emit_addhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v4s_v2d_v2d(dst, src, src2)) } +inst_subhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_subhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_subhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_subhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v8b_v8h_v8h(dst, src, src2)) } +emit_subhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v4h_v4s_v4s(dst, src, src2)) } +emit_subhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v2s_v2d_v2d(dst, src, src2)) } +inst_subhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_subhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_subhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_subhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v16b_v8h_v8h(dst, src, src2)) } +emit_subhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v8h_v4s_v4s(dst, src, src2)) } +emit_subhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v4s_v2d_v2d(dst, src, src2)) } +inst_xtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } +inst_xtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_xtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_xtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v8b_v8h(dst, src)) } +emit_xtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v4h_v4s(dst, src)) } +emit_xtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v2s_v2d(dst, src)) } +inst_xtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } +inst_xtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_xtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_xtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v16b_v8h(dst, src)) } +emit_xtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v8h_v4s(dst, src)) } +emit_xtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v4s_v2d(dst, src)) } +inst_sqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } +inst_sqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_sqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_sqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v8b_v8h(dst, src)) } +emit_sqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v4h_v4s(dst, src)) } +emit_sqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v2s_v2d(dst, src)) } +inst_sqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } +inst_sqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_sqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_sqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v16b_v8h(dst, src)) } +emit_sqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v8h_v4s(dst, src)) } +emit_sqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v4s_v2d(dst, src)) } +inst_uqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } +inst_uqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_uqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_uqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v8b_v8h(dst, src)) } +emit_uqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v4h_v4s(dst, src)) } +emit_uqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v2s_v2d(dst, src)) } +inst_uqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } +inst_uqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_uqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_uqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v16b_v8h(dst, src)) } +emit_uqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v8h_v4s(dst, src)) } +emit_uqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v4s_v2d(dst, src)) } +inst_sqxtun_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } +inst_sqxtun_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_sqxtun_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_sqxtun_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v8b_v8h(dst, src)) } +emit_sqxtun_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v4h_v4s(dst, src)) } +emit_sqxtun_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v2s_v2d(dst, src)) } +inst_sqxtun2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } +inst_sqxtun2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_sqxtun2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_sqxtun2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v16b_v8h(dst, src)) } +emit_sqxtun2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v8h_v4s(dst, src)) } +emit_sqxtun2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v4s_v2d(dst, src)) } +inst_smull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_smull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v8h_v8b_v8b(dst, src, src2)) } +emit_smull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v4s_v4h_v4h(dst, src, src2)) } +emit_smull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v2d_v2s_v2s(dst, src, src2)) } +inst_smull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_smull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v8h_v16b_v16b(dst, src, src2)) } +emit_smull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v4s_v8h_v8h(dst, src, src2)) } +emit_smull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v2d_v4s_v4s(dst, src, src2)) } +inst_umull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_umull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v8h_v8b_v8b(dst, src, src2)) } +emit_umull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v4s_v4h_v4h(dst, src, src2)) } +emit_umull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v2d_v2s_v2s(dst, src, src2)) } +inst_umull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_umull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v8h_v16b_v16b(dst, src, src2)) } +emit_umull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v4s_v8h_v8h(dst, src, src2)) } +emit_umull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v2d_v4s_v4s(dst, src, src2)) } +inst_smlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_smlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v8h_v8b_v8b(dst, src, src2)) } +emit_smlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v4s_v4h_v4h(dst, src, src2)) } +emit_smlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v2d_v2s_v2s(dst, src, src2)) } +inst_smlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_smlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v8h_v16b_v16b(dst, src, src2)) } +emit_smlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v4s_v8h_v8h(dst, src, src2)) } +emit_smlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v2d_v4s_v4s(dst, src, src2)) } +inst_umlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_umlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v8h_v8b_v8b(dst, src, src2)) } +emit_umlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v4s_v4h_v4h(dst, src, src2)) } +emit_umlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v2d_v2s_v2s(dst, src, src2)) } +inst_umlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_umlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v8h_v16b_v16b(dst, src, src2)) } +emit_umlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v4s_v8h_v8h(dst, src, src2)) } +emit_umlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v2d_v4s_v4s(dst, src, src2)) } +inst_smlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_smlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_smlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_smlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v8h_v8b_v8b(dst, src, src2)) } +emit_smlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v4s_v4h_v4h(dst, src, src2)) } +emit_smlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v2d_v2s_v2s(dst, src, src2)) } +inst_smlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_smlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_smlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_smlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v8h_v16b_v16b(dst, src, src2)) } +emit_smlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v4s_v8h_v8h(dst, src, src2)) } +emit_smlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v2d_v4s_v4s(dst, src, src2)) } +inst_umlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_umlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_umlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_umlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v8h_v8b_v8b(dst, src, src2)) } +emit_umlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v4s_v4h_v4h(dst, src, src2)) } +emit_umlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v2d_v2s_v2s(dst, src, src2)) } +inst_umlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_umlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_umlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_umlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v8h_v16b_v16b(dst, src, src2)) } +emit_umlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v4s_v8h_v8h(dst, src, src2)) } +emit_umlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v2d_v4s_v4s(dst, src, src2)) } +inst_sqdmull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqdmull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_sqdmull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v4s_v4h_v4h(dst, src, src2)) } +emit_sqdmull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v2d_v2s_v2s(dst, src, src2)) } +inst_sqdmull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqdmull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sqdmull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v4s_v8h_v8h(dst, src, src2)) } +emit_sqdmull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v2d_v4s_v4s(dst, src, src2)) } +inst_sqdmlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqdmlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_sqdmlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v4s_v4h_v4h(dst, src, src2)) } +emit_sqdmlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v2d_v2s_v2s(dst, src, src2)) } +inst_sqdmlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqdmlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sqdmlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v4s_v8h_v8h(dst, src, src2)) } +emit_sqdmlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v2d_v4s_v4s(dst, src, src2)) } +inst_sqdmlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqdmlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +emit_sqdmlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v4s_v4h_v4h(dst, src, src2)) } +emit_sqdmlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v2d_v2s_v2s(dst, src, src2)) } +inst_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v4s_v8h_v8h(dst, src, src2)) } +emit_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v2d_v4s_v4s(dst, src, src2)) } +inst_sqdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sqdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4h_v4h_v4h(dst, src, src2)) } +emit_sqdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v8h_v8h_v8h(dst, src, src2)) } +emit_sqdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v2s_v2s_v2s(dst, src, src2)) } +emit_sqdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4s_v4s_v4s(dst, src, src2)) } +inst_sqrdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sqrdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sqrdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqrdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +emit_sqrdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4h_v4h_v4h(dst, src, src2)) } +emit_sqrdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v8h_v8h_v8h(dst, src, src2)) } +emit_sqrdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v2s_v2s_v2s(dst, src, src2)) } +emit_sqrdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4s_v4s_v4s(dst, src, src2)) } +inst_sdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +emit_sdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v2s_v8b_v8b(dst, src, src2)) } +emit_sdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v4s_v16b_v16b(dst, src, src2)) } +inst_udot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_udot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +emit_udot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v2s_v8b_v8b(dst, src, src2)) } +emit_udot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v4s_v16b_v16b(dst, src, src2)) } +inst_usdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_usdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +emit_usdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v2s_v8b_v8b(dst, src, src2)) } +emit_usdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v4s_v16b_v16b(dst, src, src2)) } +inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmla_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_fmla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v4s_v4s_v4s(dst, src, src2)) } +emit_fmla_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v2d_v2d_v2d(dst, src, src2)) } +emit_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmla_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_z_z_z_i(rz, rz2, rz3, imm)) } +inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmls_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_fmls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v4s_v4s_v4s(dst, src, src2)) } +emit_fmls_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v2d_v2d_v2d(dst, src, src2)) } +emit_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmls_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_z_z_z_i(rz, rz2, rz3, imm)) } +inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmulx_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmulx_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_fmulx_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2s_v2s_v2s(dst, src, src2)) } +emit_fmulx_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4s_v4s_v4s(dst, src, src2)) } +emit_fmulx_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2d_v2d_v2d(dst, src, src2)) } +emit_fmulx_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4h_v4h_v4h(dst, src, src2)) } +emit_fmulx_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v8h_v8h_v8h(dst, src, src2)) } +inst_fmaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmaxp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_fmaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2s_v2s_v2s(dst, src, src2)) } +emit_fmaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4s_v4s_v4s(dst, src, src2)) } +emit_fmaxp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2d_v2d_v2d(dst, src, src2)) } +emit_fmaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4h_v4h_v4h(dst, src, src2)) } +emit_fmaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v8h_v8h_v8h(dst, src, src2)) } +inst_fminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fminp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_fminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2s_v2s_v2s(dst, src, src2)) } +emit_fminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4s_v4s_v4s(dst, src, src2)) } +emit_fminp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2d_v2d_v2d(dst, src, src2)) } +emit_fminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4h_v4h_v4h(dst, src, src2)) } +emit_fminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v8h_v8h_v8h(dst, src, src2)) } +inst_fmaxnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fmaxnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fmaxnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fmaxnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fmaxnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_fmaxnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2s_v2s_v2s(dst, src, src2)) } +emit_fmaxnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4s_v4s_v4s(dst, src, src2)) } +emit_fmaxnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2d_v2d_v2d(dst, src, src2)) } +emit_fmaxnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4h_v4h_v4h(dst, src, src2)) } +emit_fmaxnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v8h_v8h_v8h(dst, src, src2)) } +inst_fminnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fminnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fminnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fminnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fminnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_fminnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2s_v2s_v2s(dst, src, src2)) } +emit_fminnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4s_v4s_v4s(dst, src, src2)) } +emit_fminnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2d_v2d_v2d(dst, src, src2)) } +emit_fminnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4h_v4h_v4h(dst, src, src2)) } +emit_fminnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v8h_v8h_v8h(dst, src, src2)) } +inst_fmaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_fmaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_fmaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +emit_fmaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4s(dst, src)) } +emit_fmaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4h(dst, src)) } +emit_fmaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v8h(dst, src)) } +inst_fminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_fminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_fminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +emit_fminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4s(dst, src)) } +emit_fminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4h(dst, src)) } +emit_fminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v8h(dst, src)) } +inst_fmaxnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_fmaxnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_fmaxnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +emit_fmaxnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4s(dst, src)) } +emit_fmaxnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4h(dst, src)) } +emit_fmaxnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v8h(dst, src)) } +inst_fminnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_fminnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } +inst_fminnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +emit_fminnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4s(dst, src)) } +emit_fminnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4h(dst, src)) } +emit_fminnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v8h(dst, src)) } +inst_frecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frecpe_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frecpe_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frecpe_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_frecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2s_v2s(dst, src)) } +emit_frecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4s_v4s(dst, src)) } +emit_frecpe_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2d_v2d(dst, src)) } +emit_frecpe_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4h_v4h(dst, src)) } +emit_frecpe_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v8h_v8h(dst, src)) } +inst_frsqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_frsqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_frsqrte_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_frsqrte_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_frsqrte_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +emit_frsqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2s_v2s(dst, src)) } +emit_frsqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4s_v4s(dst, src)) } +emit_frsqrte_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2d_v2d(dst, src)) } +emit_frsqrte_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4h_v4h(dst, src)) } +emit_frsqrte_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v8h_v8h(dst, src)) } +inst_frecps_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_frecps_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2s_v2s_v2s(dst, src, src2)) } +emit_frecps_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4s_v4s_v4s(dst, src, src2)) } +emit_frecps_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2d_v2d_v2d(dst, src, src2)) } +emit_frecps_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4h_v4h_v4h(dst, src, src2)) } +emit_frecps_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v8h_v8h_v8h(dst, src, src2)) } +emit_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_z_z_z(rz, rz2, rz3)) } +inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_frsqrts_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2s_v2s_v2s(dst, src, src2)) } +emit_frsqrts_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4s_v4s_v4s(dst, src, src2)) } +emit_frsqrts_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2d_v2d_v2d(dst, src, src2)) } +emit_frsqrts_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4h_v4h_v4h(dst, src, src2)) } +emit_frsqrts_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v8h_v8h_v8h(dst, src, src2)) } +emit_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_z_z_z(rz, rz2, rz3)) } +inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } +inst_frecpx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } +emit_frecpx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_z_p_z(rz, rz2, rz3)) } +inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_faddp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_faddp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_faddp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2s_v2s_v2s(dst, src, src2)) } +emit_faddp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4s_v4s_v4s(dst, src, src2)) } +emit_faddp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2d_v2d_v2d(dst, src, src2)) } +emit_faddp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4h_v4h_v4h(dst, src, src2)) } +emit_faddp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v8h_v8h_v8h(dst, src, src2)) } +inst_fcvtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } +inst_fcvtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +emit_fcvtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v4s_v4h(dst, src)) } +emit_fcvtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v2d_v2s(dst, src)) } +inst_fcvtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_fcvtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_fcvtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v4s_v8h(dst, src)) } +emit_fcvtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v2d_v4s(dst, src)) } +inst_fcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_fcvtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_fcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v4h_v4s(dst, src)) } +emit_fcvtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v2s_v2d(dst, src)) } +inst_fcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_fcvtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_fcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v8h_v4s(dst, src)) } +emit_fcvtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v4s_v2d(dst, src)) } +inst_fcvtxn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +emit_fcvtxn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_v2s_v2d(dst, src)) } +inst_fcvtxn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +emit_fcvtxn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_v4s_v2d(dst, src)) } +inst_fcmeq_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmeq_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2s_v2s_v2s(dst, src, src2)) } +emit_fcmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4s_v4s_v4s(dst, src, src2)) } +emit_fcmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2d_v2d_v2d(dst, src, src2)) } +emit_fcmeq_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4h_v4h_v4h(dst, src, src2)) } +emit_fcmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v8h_v8h_v8h(dst, src, src2)) } +emit_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2s_v2s_v2s(dst, src, src2)) } +emit_fcmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4s_v4s_v4s(dst, src, src2)) } +emit_fcmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2d_v2d_v2d(dst, src, src2)) } +emit_fcmge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4h_v4h_v4h(dst, src, src2)) } +emit_fcmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v8h_v8h_v8h(dst, src, src2)) } +emit_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2s_v2s_v2s(dst, src, src2)) } +emit_fcmgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4s_v4s_v4s(dst, src, src2)) } +emit_fcmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2d_v2d_v2d(dst, src, src2)) } +emit_fcmgt_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4h_v4h_v4h(dst, src, src2)) } +emit_fcmgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v8h_v8h_v8h(dst, src, src2)) } +emit_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fcmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2s_v2s(dst, src)) } +emit_fcmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4s_v4s(dst, src)) } +emit_fcmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2d_v2d(dst, src)) } +emit_fcmle_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4h_v4h(dst, src)) } +emit_fcmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v8h_v8h(dst, src)) } +emit_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_p_p_z(rz, rz2, rz3)) } +inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_fcmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2s_v2s(dst, src)) } +emit_fcmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4s_v4s(dst, src)) } +emit_fcmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2d_v2d(dst, src)) } +emit_fcmlt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4h_v4h(dst, src)) } +emit_fcmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v8h_v8h(dst, src)) } +emit_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_p_p_z(rz, rz2, rz3)) } +inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_facge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_facge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_facge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2s_v2s_v2s(dst, src, src2)) } +emit_facge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4s_v4s_v4s(dst, src, src2)) } +emit_facge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2d_v2d_v2d(dst, src, src2)) } +emit_facge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4h_v4h_v4h(dst, src, src2)) } +emit_facge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v8h_v8h_v8h(dst, src, src2)) } +inst_facgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_facgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_facgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_facgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_facgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +emit_facgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2s_v2s_v2s(dst, src, src2)) } +emit_facgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4s_v4s_v4s(dst, src, src2)) } +emit_facgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2d_v2d_v2d(dst, src, src2)) } +emit_facgt_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4h_v4h_v4h(dst, src, src2)) } +emit_facgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v8h_v8h_v8h(dst, src, src2)) } +inst_cmeq_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_cmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_cmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmeq_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v16b_v16b_v16b(dst, src, src2)) } +emit_cmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v8h_v8h_v8h(dst, src, src2)) } +emit_cmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v4s_v4s_v4s(dst, src, src2)) } +emit_cmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v2d_v2d_v2d(dst, src, src2)) } +inst_cmge_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_cmge_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_cmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_cmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_cmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_cmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmge_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v8b_v8b_v8b(dst, src, src2)) } +emit_cmge_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v16b_v16b_v16b(dst, src, src2)) } +emit_cmge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4h_v4h_v4h(dst, src, src2)) } +emit_cmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v8h_v8h_v8h(dst, src, src2)) } +emit_cmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2s_v2s_v2s(dst, src, src2)) } +emit_cmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4s_v4s_v4s(dst, src, src2)) } +emit_cmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2d_v2d_v2d(dst, src, src2)) } +inst_cmgt_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmgt_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v16b_v16b_v16b(dst, src, src2)) } +emit_cmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v2d_v2d_v2d(dst, src, src2)) } +inst_cmhi_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmhi_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmhi_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v16b_v16b_v16b(dst, src, src2)) } +emit_cmhi_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v2d_v2d_v2d(dst, src, src2)) } +inst_cmhs_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_cmhs_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmhs_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_cmhs_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_cmhs_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_cmhs_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_cmhs_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmhs_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v8b_v8b_v8b(dst, src, src2)) } +emit_cmhs_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v16b_v16b_v16b(dst, src, src2)) } +emit_cmhs_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4h_v4h_v4h(dst, src, src2)) } +emit_cmhs_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v8h_v8h_v8h(dst, src, src2)) } +emit_cmhs_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2s_v2s_v2s(dst, src, src2)) } +emit_cmhs_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4s_v4s_v4s(dst, src, src2)) } +emit_cmhs_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2d_v2d_v2d(dst, src, src2)) } +inst_cmle_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_cmle_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_cmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_cmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_cmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_cmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_cmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +emit_cmle_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v8b_v8b(dst, src)) } +emit_cmle_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v16b_v16b(dst, src)) } +emit_cmle_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4h_v4h(dst, src)) } +emit_cmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v8h_v8h(dst, src)) } +emit_cmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2s_v2s(dst, src)) } +emit_cmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4s_v4s(dst, src)) } +emit_cmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2d_v2d(dst, src)) } +inst_cmlt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_cmlt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_cmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_cmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_cmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_cmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_cmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +emit_cmlt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v8b_v8b(dst, src)) } +emit_cmlt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v16b_v16b(dst, src)) } +emit_cmlt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4h_v4h(dst, src)) } +emit_cmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v8h_v8h(dst, src)) } +emit_cmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2s_v2s(dst, src)) } +emit_cmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4s_v4s(dst, src)) } +emit_cmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2d_v2d(dst, src)) } +inst_cmtst_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_cmtst_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_cmtst_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_cmtst_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_cmtst_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_cmtst_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_cmtst_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_cmtst_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v8b_v8b_v8b(dst, src, src2)) } +emit_cmtst_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v16b_v16b_v16b(dst, src, src2)) } +emit_cmtst_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4h_v4h_v4h(dst, src, src2)) } +emit_cmtst_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v8h_v8h_v8h(dst, src, src2)) } +emit_cmtst_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2s_v2s_v2s(dst, src, src2)) } +emit_cmtst_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4s_v4s_v4s(dst, src, src2)) } +emit_cmtst_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2d_v2d_v2d(dst, src, src2)) } +inst_mvn_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_mvn_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } +emit_mvn_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v8b_v8b(dst, src)) } +emit_mvn_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v16b_v16b(dst, src)) } +emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } +inst_bit_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +emit_bit_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_v16b_v16b_v16b(dst, src, src2)) } +inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +emit_bif_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_v16b_v16b_v16b(dst, src, src2)) } +inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_v16b_v16b_v16b(dst, src, src2)) } +emit_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_shl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_shl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_shl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_shl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_shl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v8b_v8b_i(dst, src, imm)) } +emit_shl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v16b_v16b_i(dst, src, imm)) } +emit_shl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4h_v4h_i(dst, src, imm)) } +emit_shl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v8h_v8h_i(dst, src, imm)) } +emit_shl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2s_v2s_i(dst, src, imm)) } +emit_shl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4s_v4s_i(dst, src, imm)) } +emit_shl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2d_v2d_i(dst, src, imm)) } +inst_sqshl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sqshl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sqshl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sqshl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sqshl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v8b_v8b_i(dst, src, imm)) } +emit_sqshl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v16b_v16b_i(dst, src, imm)) } +emit_sqshl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4h_v4h_i(dst, src, imm)) } +emit_sqshl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v8h_v8h_i(dst, src, imm)) } +emit_sqshl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2s_v2s_i(dst, src, imm)) } +emit_sqshl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4s_v4s_i(dst, src, imm)) } +emit_sqshl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2d_v2d_i(dst, src, imm)) } +inst_sqshlu_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshlu_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v8b_v8b_i(dst, src, imm)) } +emit_sqshlu_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v16b_v16b_i(dst, src, imm)) } +emit_sqshlu_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4h_v4h_i(dst, src, imm)) } +emit_sqshlu_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v8h_v8h_i(dst, src, imm)) } +emit_sqshlu_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2s_v2s_i(dst, src, imm)) } +emit_sqshlu_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4s_v4s_i(dst, src, imm)) } +emit_sqshlu_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2d_v2d_i(dst, src, imm)) } +inst_srshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_srshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_srshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_srshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_srshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_srshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_srshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_srshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v8b_v8b_v8b(dst, src, src2)) } +emit_srshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v16b_v16b_v16b(dst, src, src2)) } +emit_srshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4h_v4h_v4h(dst, src, src2)) } +emit_srshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v8h_v8h_v8h(dst, src, src2)) } +emit_srshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2s_v2s_v2s(dst, src, src2)) } +emit_srshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4s_v4s_v4s(dst, src, src2)) } +emit_srshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2d_v2d_v2d(dst, src, src2)) } +inst_urshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_urshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_urshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_urshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_urshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_urshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_urshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_urshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v8b_v8b_v8b(dst, src, src2)) } +emit_urshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v16b_v16b_v16b(dst, src, src2)) } +emit_urshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4h_v4h_v4h(dst, src, src2)) } +emit_urshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v8h_v8h_v8h(dst, src, src2)) } +emit_urshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2s_v2s_v2s(dst, src, src2)) } +emit_urshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4s_v4s_v4s(dst, src, src2)) } +emit_urshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2d_v2d_v2d(dst, src, src2)) } +inst_sshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v8b_v8b_i(dst, src, imm)) } +emit_sshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v16b_v16b_i(dst, src, imm)) } +emit_sshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4h_v4h_i(dst, src, imm)) } +emit_sshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v8h_v8h_i(dst, src, imm)) } +emit_sshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2s_v2s_i(dst, src, imm)) } +emit_sshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4s_v4s_i(dst, src, imm)) } +emit_sshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2d_v2d_i(dst, src, imm)) } +inst_ushr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_ushr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_ushr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_ushr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_ushr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_ushr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_ushr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_ushr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v8b_v8b_i(dst, src, imm)) } +emit_ushr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v16b_v16b_i(dst, src, imm)) } +emit_ushr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4h_v4h_i(dst, src, imm)) } +emit_ushr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v8h_v8h_i(dst, src, imm)) } +emit_ushr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2s_v2s_i(dst, src, imm)) } +emit_ushr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4s_v4s_i(dst, src, imm)) } +emit_ushr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2d_v2d_i(dst, src, imm)) } +inst_ssra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_ssra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_ssra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_ssra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_ssra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_ssra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_ssra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_ssra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v8b_v8b_i(dst, src, imm)) } +emit_ssra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v16b_v16b_i(dst, src, imm)) } +emit_ssra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4h_v4h_i(dst, src, imm)) } +emit_ssra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v8h_v8h_i(dst, src, imm)) } +emit_ssra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2s_v2s_i(dst, src, imm)) } +emit_ssra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4s_v4s_i(dst, src, imm)) } +emit_ssra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2d_v2d_i(dst, src, imm)) } +inst_usra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_usra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_usra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_usra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_usra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_usra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_usra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_usra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v8b_v8b_i(dst, src, imm)) } +emit_usra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v16b_v16b_i(dst, src, imm)) } +emit_usra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4h_v4h_i(dst, src, imm)) } +emit_usra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v8h_v8h_i(dst, src, imm)) } +emit_usra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2s_v2s_i(dst, src, imm)) } +emit_usra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4s_v4s_i(dst, src, imm)) } +emit_usra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2d_v2d_i(dst, src, imm)) } +inst_srshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_srshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_srshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_srshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_srshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_srshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_srshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_srshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v8b_v8b_i(dst, src, imm)) } +emit_srshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v16b_v16b_i(dst, src, imm)) } +emit_srshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4h_v4h_i(dst, src, imm)) } +emit_srshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v8h_v8h_i(dst, src, imm)) } +emit_srshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2s_v2s_i(dst, src, imm)) } +emit_srshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4s_v4s_i(dst, src, imm)) } +emit_srshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2d_v2d_i(dst, src, imm)) } +inst_urshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_urshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_urshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_urshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_urshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_urshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_urshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_urshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v8b_v8b_i(dst, src, imm)) } +emit_urshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v16b_v16b_i(dst, src, imm)) } +emit_urshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4h_v4h_i(dst, src, imm)) } +emit_urshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v8h_v8h_i(dst, src, imm)) } +emit_urshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2s_v2s_i(dst, src, imm)) } +emit_urshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4s_v4s_i(dst, src, imm)) } +emit_urshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2d_v2d_i(dst, src, imm)) } +inst_srsra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_srsra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_srsra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_srsra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_srsra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_srsra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_srsra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_srsra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v8b_v8b_i(dst, src, imm)) } +emit_srsra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v16b_v16b_i(dst, src, imm)) } +emit_srsra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4h_v4h_i(dst, src, imm)) } +emit_srsra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v8h_v8h_i(dst, src, imm)) } +emit_srsra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2s_v2s_i(dst, src, imm)) } +emit_srsra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4s_v4s_i(dst, src, imm)) } +emit_srsra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2d_v2d_i(dst, src, imm)) } +inst_ursra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_ursra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_ursra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_ursra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_ursra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_ursra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_ursra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_ursra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v8b_v8b_i(dst, src, imm)) } +emit_ursra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v16b_v16b_i(dst, src, imm)) } +emit_ursra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4h_v4h_i(dst, src, imm)) } +emit_ursra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v8h_v8h_i(dst, src, imm)) } +emit_ursra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2s_v2s_i(dst, src, imm)) } +emit_ursra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4s_v4s_i(dst, src, imm)) } +emit_ursra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2d_v2d_i(dst, src, imm)) } +inst_sshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_sshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_sshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_sshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_sshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v8b_v8b_v8b(dst, src, src2)) } +emit_sshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v16b_v16b_v16b(dst, src, src2)) } +emit_sshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4h_v4h_v4h(dst, src, src2)) } +emit_sshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v8h_v8h_v8h(dst, src, src2)) } +emit_sshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2s_v2s_v2s(dst, src, src2)) } +emit_sshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4s_v4s_v4s(dst, src, src2)) } +emit_sshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2d_v2d_v2d(dst, src, src2)) } +inst_ushl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_ushl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_ushl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_ushl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_ushl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_ushl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_ushl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +emit_ushl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v8b_v8b_v8b(dst, src, src2)) } +emit_ushl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v16b_v16b_v16b(dst, src, src2)) } +emit_ushl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4h_v4h_v4h(dst, src, src2)) } +emit_ushl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v8h_v8h_v8h(dst, src, src2)) } +emit_ushl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2s_v2s_v2s(dst, src, src2)) } +emit_ushl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4s_v4s_v4s(dst, src, src2)) } +emit_ushl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2d_v2d_v2d(dst, src, src2)) } +inst_sli_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sli_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sli_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sli_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sli_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sli_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sli_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sli_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v8b_v8b_i(dst, src, imm)) } +emit_sli_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v16b_v16b_i(dst, src, imm)) } +emit_sli_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4h_v4h_i(dst, src, imm)) } +emit_sli_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v8h_v8h_i(dst, src, imm)) } +emit_sli_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2s_v2s_i(dst, src, imm)) } +emit_sli_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4s_v4s_i(dst, src, imm)) } +emit_sli_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2d_v2d_i(dst, src, imm)) } +inst_sri_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sri_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sri_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sri_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sri_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sri_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sri_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sri_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v8b_v8b_i(dst, src, imm)) } +emit_sri_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v16b_v16b_i(dst, src, imm)) } +emit_sri_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4h_v4h_i(dst, src, imm)) } +emit_sri_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v8h_v8h_i(dst, src, imm)) } +emit_sri_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2s_v2s_i(dst, src, imm)) } +emit_sri_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4s_v4s_i(dst, src, imm)) } +emit_sri_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2d_v2d_i(dst, src, imm)) } +inst_sshll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_sshll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_sshll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +emit_sshll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v8h_v8b_i(dst, src, imm)) } +emit_sshll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v4s_v4h_i(dst, src, imm)) } +emit_sshll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v2d_v2s_i(dst, src, imm)) } +inst_sshll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_sshll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sshll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +emit_sshll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v8h_v16b_i(dst, src, imm)) } +emit_sshll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v4s_v8h_i(dst, src, imm)) } +emit_sshll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v2d_v4s_i(dst, src, imm)) } +inst_ushll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } +inst_ushll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } +inst_ushll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +emit_ushll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v8h_v8b_i(dst, src, imm)) } +emit_ushll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v4s_v4h_i(dst, src, imm)) } +emit_ushll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v2d_v2s_i(dst, src, imm)) } +inst_ushll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } +inst_ushll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_ushll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +emit_ushll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v8h_v16b_i(dst, src, imm)) } +emit_ushll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v4s_v8h_i(dst, src, imm)) } +emit_ushll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v2d_v4s_i(dst, src, imm)) } +inst_sxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } +inst_sxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } +inst_sxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +emit_sxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v8h_v8b(dst, src)) } +emit_sxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v4s_v4h(dst, src)) } +emit_sxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v2d_v2s(dst, src)) } +inst_sxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_sxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_sxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_sxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v8h_v16b(dst, src)) } +emit_sxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v4s_v8h(dst, src)) } +emit_sxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v2d_v4s(dst, src)) } +inst_uxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } +inst_uxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } +inst_uxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +emit_uxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v8h_v8b(dst, src)) } +emit_uxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v4s_v4h(dst, src)) } +emit_uxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v2d_v2s(dst, src)) } +inst_uxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } +inst_uxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } +inst_uxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +emit_uxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v8h_v16b(dst, src)) } +emit_uxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v4s_v8h(dst, src)) } +emit_uxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v2d_v4s(dst, src)) } +inst_shrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_shrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_shrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_shrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v8b_v8h_i(dst, src, imm)) } +emit_shrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v4h_v4s_i(dst, src, imm)) } +emit_shrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v2s_v2d_i(dst, src, imm)) } +inst_shrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_shrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_shrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_shrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v16b_v8h_i(dst, src, imm)) } +emit_shrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v8h_v4s_i(dst, src, imm)) } +emit_shrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v4s_v2d_i(dst, src, imm)) } +inst_rshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_rshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_rshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_rshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v8b_v8h_i(dst, src, imm)) } +emit_rshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v4h_v4s_i(dst, src, imm)) } +emit_rshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v2s_v2d_i(dst, src, imm)) } +inst_rshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_rshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_rshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_rshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v16b_v8h_i(dst, src, imm)) } +emit_rshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v8h_v4s_i(dst, src, imm)) } +emit_rshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v4s_v2d_i(dst, src, imm)) } +inst_sqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v8b_v8h_i(dst, src, imm)) } +emit_sqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v4h_v4s_i(dst, src, imm)) } +emit_sqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v2s_v2d_i(dst, src, imm)) } +inst_sqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v16b_v8h_i(dst, src, imm)) } +emit_sqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v8h_v4s_i(dst, src, imm)) } +emit_sqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v4s_v2d_i(dst, src, imm)) } +inst_uqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_uqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_uqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_uqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v8b_v8h_i(dst, src, imm)) } +emit_uqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v4h_v4s_i(dst, src, imm)) } +emit_uqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v2s_v2d_i(dst, src, imm)) } +inst_uqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_uqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_uqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_uqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v16b_v8h_i(dst, src, imm)) } +emit_uqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v8h_v4s_i(dst, src, imm)) } +emit_uqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v4s_v2d_i(dst, src, imm)) } +inst_sqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v8b_v8h_i(dst, src, imm)) } +emit_sqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v4h_v4s_i(dst, src, imm)) } +emit_sqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v2s_v2d_i(dst, src, imm)) } +inst_sqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v16b_v8h_i(dst, src, imm)) } +emit_sqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v8h_v4s_i(dst, src, imm)) } +emit_sqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v4s_v2d_i(dst, src, imm)) } +inst_uqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_uqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_uqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_uqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v8b_v8h_i(dst, src, imm)) } +emit_uqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v4h_v4s_i(dst, src, imm)) } +emit_uqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v2s_v2d_i(dst, src, imm)) } +inst_uqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_uqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_uqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_uqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v16b_v8h_i(dst, src, imm)) } +emit_uqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v8h_v4s_i(dst, src, imm)) } +emit_uqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v4s_v2d_i(dst, src, imm)) } +inst_sqshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v8b_v8h_i(dst, src, imm)) } +emit_sqshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v4h_v4s_i(dst, src, imm)) } +emit_sqshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v2s_v2d_i(dst, src, imm)) } +inst_sqshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v16b_v8h_i(dst, src, imm)) } +emit_sqshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v8h_v4s_i(dst, src, imm)) } +emit_sqshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v4s_v2d_i(dst, src, imm)) } +inst_sqrshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqrshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqrshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqrshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v8b_v8h_i(dst, src, imm)) } +emit_sqrshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v4h_v4s_i(dst, src, imm)) } +emit_sqrshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v2s_v2d_i(dst, src, imm)) } +inst_sqrshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } +inst_sqrshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +emit_sqrshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v16b_v8h_i(dst, src, imm)) } +emit_sqrshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v8h_v4s_i(dst, src, imm)) } +emit_sqrshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v4s_v2d_i(dst, src, imm)) } +inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_imm(imm, 4), {}}} } +inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_imm(imm, 4), {}}} } +inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_imm(imm, 4), {}}} } +inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_imm(imm, 4), {}}} } +inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_imm(imm, 4), {}}} } +inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_imm(imm, 4), {}}} } +inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_imm(imm, 4), {}}} } +inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}}} } +inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}}} } +inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}}} } +inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_reg(src), {}, {}}} } +inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}}} } +inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}}} } +inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}}} } +inst_dup_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_dup_v8b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v8b_veb_i(dst, src, imm)) } +emit_dup_v16b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v16b_veb_i(dst, src, imm)) } +emit_dup_v4h_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v4h_veh_i(dst, src, imm)) } +emit_dup_v8h_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v8h_veh_i(dst, src, imm)) } +emit_dup_v2s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v2s_ves_i(dst, src, imm)) } +emit_dup_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v4s_ves_i(dst, src, imm)) } +emit_dup_v2d_ved_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v2d_ved_i(dst, src, imm)) } +emit_dup_v8b_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v8b_r(dst, src)) } +emit_dup_v16b_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v16b_r(dst, src)) } +emit_dup_v4h_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v4h_r(dst, src)) } +emit_dup_v8h_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v8h_r(dst, src)) } +emit_dup_v2s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v2s_r(dst, src)) } +emit_dup_v4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v4s_r(dst, src)) } +emit_dup_v2d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v2d_r(dst, src)) } +emit_dup_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_z_r(rz, src)) } +inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_v_elem_b(src), op_imm(imm2, 4)}} } +inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_v_elem_h(src), op_imm(imm2, 4)}} } +inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_v_elem_s(src), op_imm(imm2, 4)}} } +inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_v_elem_d(src), op_imm(imm2, 4)}} } +inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_reg(src), {}}} } +inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_reg(src), {}}} } +inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_reg(src), {}}} } +inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_reg(src), {}}} } +emit_ins_veb_i_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veb_i_veb_i(dst, imm, src, imm2)) } +emit_ins_veh_i_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veh_i_veh_i(dst, imm, src, imm2)) } +emit_ins_ves_i_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_ves_i_ves_i(dst, imm, src, imm2)) } +emit_ins_ved_i_ved_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_ved_i_ved_i(dst, imm, src, imm2)) } +emit_ins_veb_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_veb_i_r(dst, imm, src)) } +emit_ins_veh_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_veh_i_r(dst, imm, src)) } +emit_ins_ves_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ves_i_r(dst, imm, src)) } +emit_ins_ved_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ved_i_r(dst, imm, src)) } +inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_mov_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_mov_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV, dst, src) } +inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } +emit_mov_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v8b_v8b(dst, src)) } +emit_mov_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v16b_v16b(dst, src)) } +emit_mov_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_z_p_z(rz, rz2, rz3)) } +emit_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_p_p_p(rz, rz2, rz3)) } +emit_mov_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_p_p(rz, rz2)) } +emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } +emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } +inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4)}} } +inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4)}} } +inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } +emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } +emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } +inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_16b(src), op_v_8b(src2), {}}} } +inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } +emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } +emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } +inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_16b(src), op_v_8b(src2), {}}} } +inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } +emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } +emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } +inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_zip1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_zip1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8b_v8b_v8b(dst, src, src2)) } +emit_zip1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v16b_v16b_v16b(dst, src, src2)) } +emit_zip1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4h_v4h_v4h(dst, src, src2)) } +emit_zip1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8h_v8h_v8h(dst, src, src2)) } +emit_zip1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v2s_v2s_v2s(dst, src, src2)) } +emit_zip1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4s_v4s_v4s(dst, src, src2)) } +emit_zip1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v2d_v2d_v2d(dst, src, src2)) } +emit_zip1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_z_z_z(rz, rz2, rz3)) } +emit_zip1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_p_p_p(rz, rz2, rz3)) } +inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_zip2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_zip2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8b_v8b_v8b(dst, src, src2)) } +emit_zip2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v16b_v16b_v16b(dst, src, src2)) } +emit_zip2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4h_v4h_v4h(dst, src, src2)) } +emit_zip2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8h_v8h_v8h(dst, src, src2)) } +emit_zip2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v2s_v2s_v2s(dst, src, src2)) } +emit_zip2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4s_v4s_v4s(dst, src, src2)) } +emit_zip2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v2d_v2d_v2d(dst, src, src2)) } +emit_zip2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_z_z_z(rz, rz2, rz3)) } +emit_zip2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_p_p_p(rz, rz2, rz3)) } +inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_uzp1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_uzp1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8b_v8b_v8b(dst, src, src2)) } +emit_uzp1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v16b_v16b_v16b(dst, src, src2)) } +emit_uzp1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4h_v4h_v4h(dst, src, src2)) } +emit_uzp1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8h_v8h_v8h(dst, src, src2)) } +emit_uzp1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v2s_v2s_v2s(dst, src, src2)) } +emit_uzp1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4s_v4s_v4s(dst, src, src2)) } +emit_uzp1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v2d_v2d_v2d(dst, src, src2)) } +emit_uzp1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_z_z_z(rz, rz2, rz3)) } +emit_uzp1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_p_p_p(rz, rz2, rz3)) } +inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_uzp2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_uzp2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8b_v8b_v8b(dst, src, src2)) } +emit_uzp2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v16b_v16b_v16b(dst, src, src2)) } +emit_uzp2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4h_v4h_v4h(dst, src, src2)) } +emit_uzp2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8h_v8h_v8h(dst, src, src2)) } +emit_uzp2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v2s_v2s_v2s(dst, src, src2)) } +emit_uzp2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4s_v4s_v4s(dst, src, src2)) } +emit_uzp2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v2d_v2d_v2d(dst, src, src2)) } +emit_uzp2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_z_z_z(rz, rz2, rz3)) } +emit_uzp2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_p_p_p(rz, rz2, rz3)) } +inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_trn1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_trn1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8b_v8b_v8b(dst, src, src2)) } +emit_trn1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v16b_v16b_v16b(dst, src, src2)) } +emit_trn1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4h_v4h_v4h(dst, src, src2)) } +emit_trn1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8h_v8h_v8h(dst, src, src2)) } +emit_trn1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v2s_v2s_v2s(dst, src, src2)) } +emit_trn1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4s_v4s_v4s(dst, src, src2)) } +emit_trn1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v2d_v2d_v2d(dst, src, src2)) } +emit_trn1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_z_z_z(rz, rz2, rz3)) } +emit_trn1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_p_p_p(rz, rz2, rz3)) } +inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } +inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } +inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_trn2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_trn2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8b_v8b_v8b(dst, src, src2)) } +emit_trn2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v16b_v16b_v16b(dst, src, src2)) } +emit_trn2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4h_v4h_v4h(dst, src, src2)) } +emit_trn2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8h_v8h_v8h(dst, src, src2)) } +emit_trn2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v2s_v2s_v2s(dst, src, src2)) } +emit_trn2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4s_v4s_v4s(dst, src, src2)) } +emit_trn2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v2d_v2d_v2d(dst, src, src2)) } +emit_trn2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_z_z_z(rz, rz2, rz3)) } +emit_trn2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_p_p_p(rz, rz2, rz3)) } +inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_not_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_not_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v8b_v8b(dst, src)) } +emit_not_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v16b_v16b(dst, src)) } +emit_not_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_p_p_p(rz, rz2, rz3)) } +inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } +inst_rev64_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_rev64_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_rev64_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_rev64_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8b_v8b(dst, src)) } +emit_rev64_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v16b_v16b(dst, src)) } +emit_rev64_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4h_v4h(dst, src)) } +emit_rev64_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8h_v8h(dst, src)) } +emit_rev64_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v2s_v2s(dst, src)) } +emit_rev64_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4s_v4s(dst, src)) } +inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } +inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_cnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_cnt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v8b_v8b(dst, src)) } +emit_cnt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v16b_v16b(dst, src)) } +emit_cnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_z_p_z(rz, rz2, rz3)) } +inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_urecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v2s_v2s(dst, src)) } +emit_urecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v4s_v4s(dst, src)) } +inst_ursqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } +inst_ursqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +emit_ursqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v2s_v2s(dst, src)) } +emit_ursqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v4s_v4s(dst, src)) } +inst_movi_v8b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v16b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } +emit_movi_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v8b_i(dst, imm)) } +emit_movi_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v16b_i(dst, imm)) } +emit_movi_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4h_i(dst, imm)) } +emit_movi_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v8h_i(dst, imm)) } +emit_movi_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2s_i(dst, imm)) } +emit_movi_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4s_i(dst, imm)) } +emit_movi_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2d_i(dst, imm)) } +inst_mvni_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } +inst_mvni_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } +inst_mvni_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } +inst_mvni_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } +emit_mvni_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4h_i(dst, imm)) } +emit_mvni_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v8h_i(dst, imm)) } +emit_mvni_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v2s_i(dst, imm)) } +emit_mvni_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4s_i(dst, imm)) } +inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } +inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } +inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } +inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v16b_m(dst, mem)) } +emit_ld1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v8h_m(dst, mem)) } +emit_ld1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v4s_m(dst, mem)) } +emit_ld1_v2d_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v2d_m(dst, mem)) } +emit_ld1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_veb_i_m(dst, imm, mem)) } +emit_ld1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_veh_i_m(dst, imm, mem)) } +emit_ld1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ves_i_m(dst, imm, mem)) } +emit_ld1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ved_i_m(dst, imm, mem)) } +inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_v16b_m(dst, mem)) } +emit_ld2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veb_i_m(dst, imm, mem)) } +emit_ld2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veh_i_m(dst, imm, mem)) } +emit_ld2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ves_i_m(dst, imm, mem)) } +emit_ld2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ved_i_m(dst, imm, mem)) } +inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_v16b_m(dst, mem)) } +emit_ld3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veb_i_m(dst, imm, mem)) } +emit_ld3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veh_i_m(dst, imm, mem)) } +emit_ld3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ves_i_m(dst, imm, mem)) } +emit_ld3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ved_i_m(dst, imm, mem)) } +inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_ld4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_v16b_m(dst, mem)) } +emit_ld4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veb_i_m(dst, imm, mem)) } +emit_ld4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veh_i_m(dst, imm, mem)) } +emit_ld4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ves_i_m(dst, imm, mem)) } +emit_ld4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ved_i_m(dst, imm, mem)) } +inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } +inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } +inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } +inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v16b_m(dst, mem)) } +emit_st1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v8h_m(dst, mem)) } +emit_st1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v4s_m(dst, mem)) } +emit_st1_v2d_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v2d_m(dst, mem)) } +emit_st1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_veb_i_m(dst, imm, mem)) } +emit_st1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_veh_i_m(dst, imm, mem)) } +emit_st1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ves_i_m(dst, imm, mem)) } +emit_st1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ved_i_m(dst, imm, mem)) } +inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_v16b_m(dst, mem)) } +emit_st2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veb_i_m(dst, imm, mem)) } +emit_st2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veh_i_m(dst, imm, mem)) } +emit_st2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ves_i_m(dst, imm, mem)) } +emit_st2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ved_i_m(dst, imm, mem)) } +inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_v16b_m(dst, mem)) } +emit_st3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veb_i_m(dst, imm, mem)) } +emit_st3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veh_i_m(dst, imm, mem)) } +emit_st3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ves_i_m(dst, imm, mem)) } +emit_st3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ved_i_m(dst, imm, mem)) } +inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +emit_st4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_v16b_m(dst, mem)) } +emit_st4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veb_i_m(dst, imm, mem)) } +emit_st4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veh_i_m(dst, imm, mem)) } +emit_st4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ves_i_m(dst, imm, mem)) } +emit_st4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ved_i_m(dst, imm, mem)) } +inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +emit_ld1r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_v16b_m(dst, mem)) } +inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +emit_ld2r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_v16b_m(dst, mem)) } +inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +emit_ld3r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_v16b_m(dst, mem)) } +inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +emit_ld4r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_v16b_m(dst, mem)) } +inst_subr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_subr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_asrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_asrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_lslr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_lslr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_lsrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_lsrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_z_z_z(rz, rz2, rz3)) } +inst_fsubr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fsubr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fdivr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fdivr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_nand_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nand_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sel_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sel_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orrs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orrs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_eors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_nors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_orns_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orns_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_movs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_movs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_p_p_p(rz, rz2, rz3)) } +inst_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_p_i(rz, imm)) } +inst_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_p_i(rz, imm)) } +inst_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_p(rz)) } +inst_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_p_p_p(rz, rz2, rz3)) } +inst_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_p_p_p(rz, rz2, rz3)) } +inst_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_p_p_p(rz, rz2, rz3)) } +inst_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_p_p_p(rz, rz2, rz3)) } +inst_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_p_p_p(rz, rz2, rz3)) } +inst_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_p_p_p(rz, rz2, rz3)) } +inst_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_p(rz)) } +inst_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_p(rz)) } +inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } +emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } +inst_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_z_r(rz, src)) } +inst_cpy_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +emit_cpy_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_z_p_r(rz, rz2, src)) } +inst_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_z_p_z(rz, rz2, rz3)) } +inst_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_z_p_m(rz, rz2, mem)) } +emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } +inst_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_z_p_m(rz, rz2, mem)) } +emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } +inst_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_z_p_m(rz, rz2, mem)) } +emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } +inst_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_z_p_m(rz, rz2, mem)) } +emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } +inst_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_z_p_m(rz, rz2, mem)) } +inst_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_z_p_m(rz, rz2, mem)) } +inst_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_z_p_m(rz, rz2, mem)) } +inst_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_z_p_m(rz, rz2, mem)) } +emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } +inst_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_z_p_m(rz, rz2, mem)) } +emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } +inst_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_z_p_m(rz, rz2, mem)) } +emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } +inst_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_z_p_m(rz, rz2, mem)) } +emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } +inst_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_z_p_m(rz, rz2, mem)) } +inst_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_z_p_m(rz, rz2, mem)) } +inst_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_z_p_m(rz, rz2, mem)) } +inst_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_z_p_m(rz, rz2, mem)) } +inst_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_p_r_r(rz, src, src2)) } +inst_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_p_r_r(rz, src, src2)) } +inst_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_p_r_r(rz, src, src2)) } +inst_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_p_r_r(rz, src, src2)) } +inst_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_p_r_r(rz, src, src2)) } +inst_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_p_r_r(rz, src, src2)) } +inst_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_p_r_r(rz, src, src2)) } +inst_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_p_r_r(rz, src, src2)) } +inst_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_z_z_z(rz, rz2, rz3)) } +inst_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_z_z_z(rz, rz2, rz3)) } +inst_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_z_z_z(rz, rz2, rz3)) } +inst_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_z_z_z(rz, rz2, rz3)) } +inst_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_z_z_z(rz, rz2, rz3)) } +inst_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_z_z_z(rz, rz2, rz3)) } +inst_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_z_z_z(rz, rz2, rz3)) } +inst_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_z_z_z(rz, rz2, rz3)) } +inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } +emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } +inst_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTOP) } +emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } +inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } +emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } +inst_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } +emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } +inst_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } +inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } +inst_mova_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } +inst_mova_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +emit_mova_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_z_p_i(rz, rz2, imm)) } +emit_mova_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_z(imm, rz1, rz2)) } +inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } +inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } +inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } +inst_fcmla_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +emit_fcmla_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4h_v4h_v4h_i(dst, src, src2, imm)) } +emit_fcmla_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v8h_v8h_v8h_i(dst, src, src2, imm)) } +emit_fcmla_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4s_v4s_v4s_i(dst, src, src2, imm)) } +emit_fcmla_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v2d_v2d_v2d_i(dst, src, src2, imm)) } +inst_fcadd_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } +inst_fcadd_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } +inst_fcadd_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } +inst_fcadd_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +emit_fcadd_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4h_v4h_v4h_i(dst, src, src2, imm)) } +emit_fcadd_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v8h_v8h_v8h_i(dst, src, src2, imm)) } +emit_fcadd_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4s_v4s_v4s_i(dst, src, src2, imm)) } +emit_fcadd_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v2d_v2d_v2d_i(dst, src, src2, imm)) } +inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfb_i_p_m(imm, rz1, mem)) } +inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfh_i_p_m(imm, rz1, mem)) } +inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } +inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } +inst_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_z_p_m(rz, rz2, mem)) } +inst_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_z_p_m(rz, rz2, mem)) } +inst_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_z_p_m(rz, rz2, mem)) } +inst_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_z_p_m(rz, rz2, mem)) } +inst_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_z_p_m(rz, rz2, mem)) } +inst_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_z_p_m(rz, rz2, mem)) } +inst_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_z_p_m(rz, rz2, mem)) } +inst_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_z_p_m(rz, rz2, mem)) } +inst_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_index_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } +emit_index_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_z_i_i(rz, imm, imm2)) } +emit_index_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_z_i_r(rz, imm, src)) } +emit_index_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_z_r_i(rz, src, imm)) } +emit_index_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_z_r_r(rz, src, src2)) } +inst_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_pmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_pmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_z_z_z(rz, rz2, rz3)) } +inst_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_z_z_z(rz, rz2, rz3)) } +inst_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_z_z_z(rz, rz2, rz3)) } +inst_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_z_p_z(rz, rz2, rz3)) } +inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } +emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } +inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } +emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } +inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } +emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } +inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } +emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } +inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } +inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } +emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } +inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } +emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } +inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } +emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } +inst_bc_eq_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_EQ, label) } +emit_bc_eq_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_eq_l(label)) } +inst_bc_ne_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NE, label) } +emit_bc_ne_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ne_l(label)) } +inst_bc_cs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CS, label) } +emit_bc_cs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cs_l(label)) } +inst_bc_cc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_CC, label) } +emit_bc_cc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_cc_l(label)) } +inst_bc_mi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_MI, label) } +emit_bc_mi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_mi_l(label)) } +inst_bc_pl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_PL, label) } +emit_bc_pl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_pl_l(label)) } +inst_bc_vs_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VS, label) } +emit_bc_vs_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vs_l(label)) } +inst_bc_vc_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_VC, label) } +emit_bc_vc_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_vc_l(label)) } +inst_bc_hi_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_HI, label) } +emit_bc_hi_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_hi_l(label)) } +inst_bc_ls_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LS, label) } +emit_bc_ls_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ls_l(label)) } +inst_bc_ge_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GE, label) } +emit_bc_ge_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_ge_l(label)) } +inst_bc_lt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LT, label) } +emit_bc_lt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_lt_l(label)) } +inst_bc_gt_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_GT, label) } +emit_bc_gt_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_gt_l(label)) } +inst_bc_le_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_LE, label) } +emit_bc_le_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_le_l(label)) } +inst_bc_al_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_AL, label) } +emit_bc_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_al_l(label)) } +inst_bc_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BC_NV, label) } +emit_bc_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bc_nv_l(label)) } +inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } +emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } +inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } +emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } +inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } +emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } +inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } +emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } +inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } +emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } +inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } +emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } +inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } +emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } +inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } +emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } +inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } +emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } +inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } +emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } +inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } +emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } +inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } +emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } +inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } +emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } +inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } +emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } +inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } +emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } +inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } +emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } +inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } +emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } +inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } +emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } +inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } +emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } +inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } +emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } +inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } +emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } +inst_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_z_z_z(rz, rz2, rz3)) } +inst_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_z_z_z(rz, rz2, rz3)) } +inst_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_bfmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_z_z_z(rz, rz2, rz3)) } +inst_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } +emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } +inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } +emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } +inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } +emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } +inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } +emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } +inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } +emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } +inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } +emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } +inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } +emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } +inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } +emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } +inst_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_z_z_z(rz, rz2, rz3)) } +inst_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_luti2_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti2_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_z_z_z_i(rz, rz2, rz3, imm)) } +inst_luti4_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti4_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_z_z_z_i(rz, rz2, rz3, imm)) } +inst_zip_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_zip_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_z_z_z(rz, rz2, rz3)) } +emit_zip_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_z_z(rz, rz2)) } +inst_uzp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_uzp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_z_z_z(rz, rz2, rz3)) } +emit_uzp_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_z_z(rz, rz2)) } +inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } +emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } +inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } +emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } +inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } +emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } +inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } +emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } +inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } +emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } +inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } +emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } +inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } +emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } +inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } +emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } +inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } +emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } +inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } +emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } +inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } +emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } +inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } +emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } +inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } +emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } +inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } +emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } +inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } +emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } +inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } +emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } +inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } +emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } +inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } +emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } +inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } +emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } +inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } +emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } +inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } +emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } +inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } +emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } +inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } +emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } +inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } +emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } +inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } +emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } +inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } +emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } +inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } +emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } +inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } +emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } +inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } +emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } +inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } +emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } +inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } +emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } +inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } +emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } +inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } +emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } +inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } +emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } +inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } +emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } +inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } +emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } +inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } +emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } +inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } +emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } +inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } +emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } +inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } +emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } +inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } +emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } +inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } +emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } +inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } +emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } +inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } +emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } +inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } +emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } +inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } +emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } +inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } +emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } +inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } +emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } +inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } +emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } +inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } +emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } +inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } +emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } +inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } +emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } +inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } +emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } +inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } +emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } +inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } +emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } +inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } +emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } +inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } +emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } +inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } +emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } +inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } +emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } +inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } +emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } +inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } +emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } +inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } +emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } +inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } +emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } +inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } +emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } +inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } +emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } +inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } +emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } +inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } +emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } +inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } +emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } +inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } +emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } +inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } +emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } +inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } +emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } +inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } +emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } +inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } +emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } +inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } +emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } +inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } +emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } +inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } +emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } +inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } +emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } +inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } +emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } +inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } +emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } +inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } +emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } +inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } +emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } +inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } +emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } +emit_prfm_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_i_l(imm, label)) } +inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } +inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } +inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmp_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP, dst, imm) } +emit_cmp_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_r_sh(dst, src, src_shift, src_amount)) } +emit_cmp_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_r_ex(dst, src, src_ext, src_amount)) } +emit_cmp_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_i(dst, imm)) } +inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmn_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN, dst, imm) } +emit_cmn_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_r_sh(dst, src, src_shift, src_amount)) } +emit_cmn_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_r_ex(dst, src, src_ext, src_amount)) } +emit_cmn_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_i(dst, imm)) } // ============================================================================= // Overload Groups // ============================================================================= -inst_add :: proc{ inst_add_r_r_i, inst_add_r_r_sh, inst_add_r_r_ex, inst_add_r_r_r, inst_add_z_z_z, inst_add_z_p_z_z } -emit_add :: proc{ emit_add_r_r_i, emit_add_r_r_sh, emit_add_r_r_ex, emit_add_r_r_r, emit_add_z_z_z, emit_add_z_p_z_z } -inst_adds :: proc{ inst_adds_r_r_i, inst_adds_r_r_sh, inst_adds_r_r_ex } -emit_adds :: proc{ emit_adds_r_r_i, emit_adds_r_r_sh, emit_adds_r_r_ex } -inst_sub :: proc{ inst_sub_r_r_i, inst_sub_r_r_sh, inst_sub_r_r_ex, inst_sub_r_r_r, inst_sub_z_z_z, inst_sub_z_p_z_z } -emit_sub :: proc{ emit_sub_r_r_i, emit_sub_r_r_sh, emit_sub_r_r_ex, emit_sub_r_r_r, emit_sub_z_z_z, emit_sub_z_p_z_z } -inst_subs :: proc{ inst_subs_r_r_i, inst_subs_r_r_sh, inst_subs_r_r_ex } -emit_subs :: proc{ emit_subs_r_r_i, emit_subs_r_r_sh, emit_subs_r_r_ex } -inst_movz :: inst_movz_r_i_i -emit_movz :: emit_movz_r_i_i -inst_movn :: inst_movn_r_i_i -emit_movn :: emit_movn_r_i_i -inst_movk :: inst_movk_r_i_i -emit_movk :: emit_movk_r_i_i -inst_adr :: inst_adr_r_l -emit_adr :: emit_adr_r_l -inst_adrp :: inst_adrp_r_l -emit_adrp :: emit_adrp_r_l -inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_r_r_r, inst_and_z_p_z_z } -emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_r_r_r, emit_and_z_p_z_z } -inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_p_p_p_p } -emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_p_p_p_p } -inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_r_r_r, inst_orr_z_p_z_z } -emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_r_r_r, emit_orr_z_p_z_z } -inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_r_r_r, inst_eor_z_p_z_z } -emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_r_r_r, emit_eor_z_p_z_z } -inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_r_r_r, inst_bic_z_p_z_z } -emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_r_r_r, emit_bic_z_p_z_z } -inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_p_p_p_p } -emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_p_p_p_p } -inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_r_r_r, inst_orn_p_p_p_p } -emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_r_r_r, emit_orn_p_p_p_p } -inst_eon :: inst_eon_r_r_sh -emit_eon :: emit_eon_r_r_sh -inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_z_p_z_z, inst_lsl_r_r_i } -emit_lsl :: proc{ emit_lsl_r_r_r, emit_lsl_z_p_z_z, emit_lsl_r_r_i } -inst_lsr :: proc{ inst_lsr_r_r_r, inst_lsr_z_p_z_z, inst_lsr_r_r_i } -emit_lsr :: proc{ emit_lsr_r_r_r, emit_lsr_z_p_z_z, emit_lsr_r_r_i } -inst_asr :: proc{ inst_asr_r_r_r, inst_asr_z_p_z_z, inst_asr_r_r_i } -emit_asr :: proc{ emit_asr_r_r_r, emit_asr_z_p_z_z, emit_asr_r_r_i } -inst_ror :: proc{ inst_ror_r_r_r, inst_ror_r_r_i } -emit_ror :: proc{ emit_ror_r_r_r, emit_ror_r_r_i } -inst_udiv :: proc{ inst_udiv_r_r_r, inst_udiv_z_p_z_z } -emit_udiv :: proc{ emit_udiv_r_r_r, emit_udiv_z_p_z_z } -inst_sdiv :: proc{ inst_sdiv_r_r_r, inst_sdiv_z_p_z_z } -emit_sdiv :: proc{ emit_sdiv_r_r_r, emit_sdiv_z_p_z_z } -inst_madd :: inst_madd_r_r_r_r -emit_madd :: emit_madd_r_r_r_r -inst_msub :: inst_msub_r_r_r_r -emit_msub :: emit_msub_r_r_r_r -inst_smaddl :: inst_smaddl_r_r_r_r -emit_smaddl :: emit_smaddl_r_r_r_r -inst_smsubl :: inst_smsubl_r_r_r_r -emit_smsubl :: emit_smsubl_r_r_r_r -inst_umaddl :: inst_umaddl_r_r_r_r -emit_umaddl :: emit_umaddl_r_r_r_r -inst_umsubl :: inst_umsubl_r_r_r_r -emit_umsubl :: emit_umsubl_r_r_r_r -inst_smulh :: proc{ inst_smulh_r_r_r, inst_smulh_z_p_z_z } -emit_smulh :: proc{ emit_smulh_r_r_r, emit_smulh_z_p_z_z } -inst_umulh :: proc{ inst_umulh_r_r_r, inst_umulh_z_p_z_z } -emit_umulh :: proc{ emit_umulh_r_r_r, emit_umulh_z_p_z_z } -inst_clz :: proc{ inst_clz_r_r, inst_clz_z_p_z } -emit_clz :: proc{ emit_clz_r_r, emit_clz_z_p_z } -inst_cls :: proc{ inst_cls_r_r, inst_cls_z_p_z } -emit_cls :: proc{ emit_cls_r_r, emit_cls_z_p_z } -inst_rbit :: inst_rbit_r_r -emit_rbit :: emit_rbit_r_r -inst_rev :: proc{ inst_rev_r_r, inst_rev_z_z } -emit_rev :: proc{ emit_rev_r_r, emit_rev_z_z } -inst_rev16 :: inst_rev16_r_r -emit_rev16 :: emit_rev16_r_r -inst_rev32 :: inst_rev32_r_r -emit_rev32 :: emit_rev32_r_r -inst_csel :: inst_csel_r_r_r_c -emit_csel :: emit_csel_r_r_r_c -inst_csinc :: inst_csinc_r_r_r_c -emit_csinc :: emit_csinc_r_r_r_c -inst_csinv :: inst_csinv_r_r_r_c -emit_csinv :: emit_csinv_r_r_r_c -inst_csneg :: inst_csneg_r_r_r_c -emit_csneg :: emit_csneg_r_r_r_c -inst_ccmp :: proc{ inst_ccmp_r_r_i_c, inst_ccmp_r_i_i_c } -emit_ccmp :: proc{ emit_ccmp_r_r_i_c, emit_ccmp_r_i_i_c } -inst_ccmn :: proc{ inst_ccmn_r_r_i_c, inst_ccmn_r_i_i_c } -emit_ccmn :: proc{ emit_ccmn_r_r_i_c, emit_ccmn_r_i_i_c } -inst_cset :: inst_cset_r_c -emit_cset :: emit_cset_r_c -inst_csetm :: inst_csetm_r_c -emit_csetm :: emit_csetm_r_c -inst_cinc :: inst_cinc_r_r_c -emit_cinc :: emit_cinc_r_r_c -inst_cinv :: inst_cinv_r_r_c -emit_cinv :: emit_cinv_r_r_c -inst_cneg :: inst_cneg_r_r_c -emit_cneg :: emit_cneg_r_r_c -inst_extr :: inst_extr_r_r_r_i -emit_extr :: emit_extr_r_r_r_i -inst_b :: inst_b_l -emit_b :: emit_b_l -inst_bl :: inst_bl_l -emit_bl :: emit_bl_l -inst_br :: inst_br_r -emit_br :: emit_br_r -inst_blr :: inst_blr_r -emit_blr :: emit_blr_r -inst_ret :: proc{ inst_ret_r, inst_ret_none } -emit_ret :: proc{ emit_ret_r, emit_ret_none } -inst_b_eq :: inst_b_eq_l -emit_b_eq :: emit_b_eq_l -inst_b_ne :: inst_b_ne_l -emit_b_ne :: emit_b_ne_l -inst_b_cs :: inst_b_cs_l -emit_b_cs :: emit_b_cs_l -inst_b_cc :: inst_b_cc_l -emit_b_cc :: emit_b_cc_l -inst_b_mi :: inst_b_mi_l -emit_b_mi :: emit_b_mi_l -inst_b_pl :: inst_b_pl_l -emit_b_pl :: emit_b_pl_l -inst_b_vs :: inst_b_vs_l -emit_b_vs :: emit_b_vs_l -inst_b_vc :: inst_b_vc_l -emit_b_vc :: emit_b_vc_l -inst_b_hi :: inst_b_hi_l -emit_b_hi :: emit_b_hi_l -inst_b_ls :: inst_b_ls_l -emit_b_ls :: emit_b_ls_l -inst_b_ge :: inst_b_ge_l -emit_b_ge :: emit_b_ge_l -inst_b_lt :: inst_b_lt_l -emit_b_lt :: emit_b_lt_l -inst_b_gt :: inst_b_gt_l -emit_b_gt :: emit_b_gt_l -inst_b_le :: inst_b_le_l -emit_b_le :: emit_b_le_l -inst_b_al :: inst_b_al_l -emit_b_al :: emit_b_al_l -inst_b_nv :: inst_b_nv_l -emit_b_nv :: emit_b_nv_l -inst_cbz :: inst_cbz_r_l -emit_cbz :: emit_cbz_r_l -inst_cbnz :: inst_cbnz_r_l -emit_cbnz :: emit_cbnz_r_l -inst_tbz :: inst_tbz_r_i_l -emit_tbz :: emit_tbz_r_i_l -inst_tbnz :: inst_tbnz_r_i_l -emit_tbnz :: emit_tbnz_r_i_l -inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_z_m, inst_ldr_i_m } -emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_z_m, emit_ldr_i_m } -inst_str :: proc{ inst_str_r_m, inst_str_z_m, inst_str_i_m } -emit_str :: proc{ emit_str_r_m, emit_str_z_m, emit_str_i_m } -inst_ldrb :: inst_ldrb_r_m -emit_ldrb :: emit_ldrb_r_m -inst_strb :: inst_strb_r_m -emit_strb :: emit_strb_r_m -inst_ldrsb :: inst_ldrsb_r_m -emit_ldrsb :: emit_ldrsb_r_m -inst_ldrh :: inst_ldrh_r_m -emit_ldrh :: emit_ldrh_r_m -inst_strh :: inst_strh_r_m -emit_strh :: emit_strh_r_m -inst_ldrsh :: inst_ldrsh_r_m -emit_ldrsh :: emit_ldrsh_r_m -inst_ldrsw :: inst_ldrsw_r_m -emit_ldrsw :: emit_ldrsw_r_m -inst_ldp :: inst_ldp_r_r_m -emit_ldp :: emit_ldp_r_r_m -inst_stp :: inst_stp_r_r_m -emit_stp :: emit_stp_r_r_m -inst_ldpsw :: inst_ldpsw_r_r_m -emit_ldpsw :: emit_ldpsw_r_r_m -inst_ldar :: inst_ldar_r_m -emit_ldar :: emit_ldar_r_m -inst_stlr :: inst_stlr_r_m -emit_stlr :: emit_stlr_r_m -inst_ldarb :: inst_ldarb_r_m -emit_ldarb :: emit_ldarb_r_m -inst_stlrb :: inst_stlrb_r_m -emit_stlrb :: emit_stlrb_r_m -inst_ldarh :: inst_ldarh_r_m -emit_ldarh :: emit_ldarh_r_m -inst_stlrh :: inst_stlrh_r_m -emit_stlrh :: emit_stlrh_r_m -inst_ldxr :: inst_ldxr_r_m -emit_ldxr :: emit_ldxr_r_m -inst_stxr :: inst_stxr_r_r_m -emit_stxr :: emit_stxr_r_r_m -inst_ldaxr :: inst_ldaxr_r_m -emit_ldaxr :: emit_ldaxr_r_m -inst_stlxr :: inst_stlxr_r_r_m -emit_stlxr :: emit_stlxr_r_r_m -inst_nop :: inst_nop_none -emit_nop :: emit_nop_none -inst_yield :: inst_yield_none -emit_yield :: emit_yield_none -inst_wfe :: inst_wfe_none -emit_wfe :: emit_wfe_none -inst_wfi :: inst_wfi_none -emit_wfi :: emit_wfi_none -inst_sev :: inst_sev_none -emit_sev :: emit_sev_none -inst_sevl :: inst_sevl_none -emit_sevl :: emit_sevl_none -inst_hint :: inst_hint_i -emit_hint :: emit_hint_i -inst_mrs :: inst_mrs_r_s -emit_mrs :: emit_mrs_r_s -inst_msr :: proc{ inst_msr_i_i, inst_msr_s_r } -emit_msr :: proc{ emit_msr_i_i, emit_msr_s_r } -inst_isb :: inst_isb_i -emit_isb :: emit_isb_i -inst_dsb :: inst_dsb_i -emit_dsb :: emit_dsb_i -inst_dmb :: inst_dmb_i -emit_dmb :: emit_dmb_i -inst_svc :: inst_svc_i -emit_svc :: emit_svc_i -inst_hvc :: inst_hvc_i -emit_hvc :: emit_hvc_i -inst_smc :: inst_smc_i -emit_smc :: emit_smc_i -inst_brk :: inst_brk_i -emit_brk :: emit_brk_i -inst_hlt :: inst_hlt_i -emit_hlt :: emit_hlt_i -inst_eret :: inst_eret_none -emit_eret :: emit_eret_none -inst_fmov :: proc{ inst_fmov_r_r, inst_fmov_r_i } -emit_fmov :: proc{ emit_fmov_r_r, emit_fmov_r_i } -inst_fabs :: proc{ inst_fabs_r_r, inst_fabs_z_p_z } -emit_fabs :: proc{ emit_fabs_r_r, emit_fabs_z_p_z } -inst_fneg :: proc{ inst_fneg_r_r, inst_fneg_z_p_z } -emit_fneg :: proc{ emit_fneg_r_r, emit_fneg_z_p_z } -inst_fsqrt :: proc{ inst_fsqrt_r_r, inst_fsqrt_z_p_z } -emit_fsqrt :: proc{ emit_fsqrt_r_r, emit_fsqrt_z_p_z } -inst_fadd :: proc{ inst_fadd_r_r_r, inst_fadd_z_z_z, inst_fadd_z_p_z_z } -emit_fadd :: proc{ emit_fadd_r_r_r, emit_fadd_z_z_z, emit_fadd_z_p_z_z } -inst_fsub :: proc{ inst_fsub_r_r_r, inst_fsub_z_z_z, inst_fsub_z_p_z_z } -emit_fsub :: proc{ emit_fsub_r_r_r, emit_fsub_z_z_z, emit_fsub_z_p_z_z } -inst_fmul :: proc{ inst_fmul_r_r_r, inst_fmul_z_z_z, inst_fmul_z_p_z_z } -emit_fmul :: proc{ emit_fmul_r_r_r, emit_fmul_z_z_z, emit_fmul_z_p_z_z } -inst_fdiv :: proc{ inst_fdiv_r_r_r, inst_fdiv_z_p_z_z } -emit_fdiv :: proc{ emit_fdiv_r_r_r, emit_fdiv_z_p_z_z } -inst_fnmul :: inst_fnmul_r_r_r -emit_fnmul :: emit_fnmul_r_r_r -inst_fmadd :: inst_fmadd_r_r_r_r -emit_fmadd :: emit_fmadd_r_r_r_r -inst_fmsub :: inst_fmsub_r_r_r_r -emit_fmsub :: emit_fmsub_r_r_r_r -inst_fnmadd :: inst_fnmadd_r_r_r_r -emit_fnmadd :: emit_fnmadd_r_r_r_r -inst_fnmsub :: inst_fnmsub_r_r_r_r -emit_fnmsub :: emit_fnmsub_r_r_r_r -inst_fcmp :: inst_fcmp_r_r -emit_fcmp :: emit_fcmp_r_r -inst_fcmpe :: inst_fcmpe_r_r -emit_fcmpe :: emit_fcmpe_r_r -inst_fcsel :: inst_fcsel_r_r_r_c -emit_fcsel :: emit_fcsel_r_r_r_c -inst_fmax :: proc{ inst_fmax_r_r_r, inst_fmax_z_p_z_z } -emit_fmax :: proc{ emit_fmax_r_r_r, emit_fmax_z_p_z_z } -inst_fmin :: proc{ inst_fmin_r_r_r, inst_fmin_z_p_z_z } -emit_fmin :: proc{ emit_fmin_r_r_r, emit_fmin_z_p_z_z } -inst_fmaxnm :: proc{ inst_fmaxnm_r_r_r, inst_fmaxnm_z_p_z_z } -emit_fmaxnm :: proc{ emit_fmaxnm_r_r_r, emit_fmaxnm_z_p_z_z } -inst_fminnm :: proc{ inst_fminnm_r_r_r, inst_fminnm_z_p_z_z } -emit_fminnm :: proc{ emit_fminnm_r_r_r, emit_fminnm_z_p_z_z } -inst_fcvt :: inst_fcvt_r_r -emit_fcvt :: emit_fcvt_r_r -inst_scvtf :: inst_scvtf_r_r -emit_scvtf :: emit_scvtf_r_r -inst_ucvtf :: inst_ucvtf_r_r -emit_ucvtf :: emit_ucvtf_r_r -inst_fcvtzs :: inst_fcvtzs_r_r -emit_fcvtzs :: emit_fcvtzs_r_r -inst_fcvtzu :: inst_fcvtzu_r_r -emit_fcvtzu :: emit_fcvtzu_r_r -inst_fcvtas :: inst_fcvtas_r_r -emit_fcvtas :: emit_fcvtas_r_r -inst_fcvtau :: inst_fcvtau_r_r -emit_fcvtau :: emit_fcvtau_r_r -inst_fcvtns :: inst_fcvtns_r_r -emit_fcvtns :: emit_fcvtns_r_r -inst_fcvtnu :: inst_fcvtnu_r_r -emit_fcvtnu :: emit_fcvtnu_r_r -inst_fcvtps :: inst_fcvtps_r_r -emit_fcvtps :: emit_fcvtps_r_r -inst_fcvtpu :: inst_fcvtpu_r_r -emit_fcvtpu :: emit_fcvtpu_r_r -inst_fcvtms :: inst_fcvtms_r_r -emit_fcvtms :: emit_fcvtms_r_r -inst_fcvtmu :: inst_fcvtmu_r_r -emit_fcvtmu :: emit_fcvtmu_r_r -inst_frinta :: proc{ inst_frinta_r_r, inst_frinta_z_p_z } -emit_frinta :: proc{ emit_frinta_r_r, emit_frinta_z_p_z } -inst_frinti :: proc{ inst_frinti_r_r, inst_frinti_z_p_z } -emit_frinti :: proc{ emit_frinti_r_r, emit_frinti_z_p_z } -inst_frintm :: proc{ inst_frintm_r_r, inst_frintm_z_p_z } -emit_frintm :: proc{ emit_frintm_r_r, emit_frintm_z_p_z } -inst_frintn :: proc{ inst_frintn_r_r, inst_frintn_z_p_z } -emit_frintn :: proc{ emit_frintn_r_r, emit_frintn_z_p_z } -inst_frintp :: proc{ inst_frintp_r_r, inst_frintp_z_p_z } -emit_frintp :: proc{ emit_frintp_r_r, emit_frintp_z_p_z } -inst_frintx :: proc{ inst_frintx_r_r, inst_frintx_z_p_z } -emit_frintx :: proc{ emit_frintx_r_r, emit_frintx_z_p_z } -inst_frintz :: proc{ inst_frintz_r_r, inst_frintz_z_p_z } -emit_frintz :: proc{ emit_frintz_r_r, emit_frintz_z_p_z } -inst_tst :: proc{ inst_tst_r_i, inst_tst_r_sh } -emit_tst :: proc{ emit_tst_r_i, emit_tst_r_sh } -inst_ldur :: inst_ldur_r_m -emit_ldur :: emit_ldur_r_m -inst_stur :: inst_stur_r_m -emit_stur :: emit_stur_r_m -inst_ldurb :: inst_ldurb_r_m -emit_ldurb :: emit_ldurb_r_m -inst_sturb :: inst_sturb_r_m -emit_sturb :: emit_sturb_r_m -inst_ldursb :: inst_ldursb_r_m -emit_ldursb :: emit_ldursb_r_m -inst_ldurh :: inst_ldurh_r_m -emit_ldurh :: emit_ldurh_r_m -inst_sturh :: inst_sturh_r_m -emit_sturh :: emit_sturh_r_m -inst_ldursh :: inst_ldursh_r_m -emit_ldursh :: emit_ldursh_r_m -inst_ldursw :: inst_ldursw_r_m -emit_ldursw :: emit_ldursw_r_m -inst_ldnp :: inst_ldnp_r_r_m -emit_ldnp :: emit_ldnp_r_r_m -inst_stnp :: inst_stnp_r_r_m -emit_stnp :: emit_stnp_r_r_m -inst_ldxp :: inst_ldxp_r_r_m -emit_ldxp :: emit_ldxp_r_r_m -inst_stxp :: inst_stxp_r_r_r_m -emit_stxp :: emit_stxp_r_r_r_m -inst_ldaxp :: inst_ldaxp_r_r_m -emit_ldaxp :: emit_ldaxp_r_r_m -inst_stlxp :: inst_stlxp_r_r_r_m -emit_stlxp :: emit_stlxp_r_r_r_m -inst_ldxrb :: inst_ldxrb_r_m -emit_ldxrb :: emit_ldxrb_r_m -inst_stxrb :: inst_stxrb_r_r_m -emit_stxrb :: emit_stxrb_r_r_m -inst_ldaxrb :: inst_ldaxrb_r_m -emit_ldaxrb :: emit_ldaxrb_r_m -inst_stlxrb :: inst_stlxrb_r_r_m -emit_stlxrb :: emit_stlxrb_r_r_m -inst_ldxrh :: inst_ldxrh_r_m -emit_ldxrh :: emit_ldxrh_r_m -inst_stxrh :: inst_stxrh_r_r_m -emit_stxrh :: emit_stxrh_r_r_m -inst_ldaxrh :: inst_ldaxrh_r_m -emit_ldaxrh :: emit_ldaxrh_r_m -inst_stlxrh :: inst_stlxrh_r_r_m -emit_stlxrh :: emit_stlxrh_r_r_m -inst_ldapr :: inst_ldapr_r_m -emit_ldapr :: emit_ldapr_r_m -inst_ldaprb :: inst_ldaprb_r_m -emit_ldaprb :: emit_ldaprb_r_m -inst_ldaprh :: inst_ldaprh_r_m -emit_ldaprh :: emit_ldaprh_r_m -inst_ldadd :: inst_ldadd_r_r_m -emit_ldadd :: emit_ldadd_r_r_m -inst_ldadda :: inst_ldadda_r_r_m -emit_ldadda :: emit_ldadda_r_r_m -inst_ldaddl :: inst_ldaddl_r_r_m -emit_ldaddl :: emit_ldaddl_r_r_m -inst_ldaddal :: inst_ldaddal_r_r_m -emit_ldaddal :: emit_ldaddal_r_r_m -inst_ldclr :: inst_ldclr_r_r_m -emit_ldclr :: emit_ldclr_r_r_m -inst_ldclra :: inst_ldclra_r_r_m -emit_ldclra :: emit_ldclra_r_r_m -inst_ldclrl :: inst_ldclrl_r_r_m -emit_ldclrl :: emit_ldclrl_r_r_m -inst_ldclral :: inst_ldclral_r_r_m -emit_ldclral :: emit_ldclral_r_r_m -inst_ldeor :: inst_ldeor_r_r_m -emit_ldeor :: emit_ldeor_r_r_m -inst_ldeora :: inst_ldeora_r_r_m -emit_ldeora :: emit_ldeora_r_r_m -inst_ldeorl :: inst_ldeorl_r_r_m -emit_ldeorl :: emit_ldeorl_r_r_m -inst_ldeoral :: inst_ldeoral_r_r_m -emit_ldeoral :: emit_ldeoral_r_r_m -inst_ldset :: inst_ldset_r_r_m -emit_ldset :: emit_ldset_r_r_m -inst_ldseta :: inst_ldseta_r_r_m -emit_ldseta :: emit_ldseta_r_r_m -inst_ldsetl :: inst_ldsetl_r_r_m -emit_ldsetl :: emit_ldsetl_r_r_m -inst_ldsetal :: inst_ldsetal_r_r_m -emit_ldsetal :: emit_ldsetal_r_r_m -inst_ldsmax :: inst_ldsmax_r_r_m -emit_ldsmax :: emit_ldsmax_r_r_m -inst_ldsmaxa :: inst_ldsmaxa_r_r_m -emit_ldsmaxa :: emit_ldsmaxa_r_r_m -inst_ldsmaxl :: inst_ldsmaxl_r_r_m -emit_ldsmaxl :: emit_ldsmaxl_r_r_m -inst_ldsmaxal :: inst_ldsmaxal_r_r_m -emit_ldsmaxal :: emit_ldsmaxal_r_r_m -inst_ldsmin :: inst_ldsmin_r_r_m -emit_ldsmin :: emit_ldsmin_r_r_m -inst_ldsmina :: inst_ldsmina_r_r_m -emit_ldsmina :: emit_ldsmina_r_r_m -inst_ldsminl :: inst_ldsminl_r_r_m -emit_ldsminl :: emit_ldsminl_r_r_m -inst_ldsminal :: inst_ldsminal_r_r_m -emit_ldsminal :: emit_ldsminal_r_r_m -inst_ldumax :: inst_ldumax_r_r_m -emit_ldumax :: emit_ldumax_r_r_m -inst_ldumaxa :: inst_ldumaxa_r_r_m -emit_ldumaxa :: emit_ldumaxa_r_r_m -inst_ldumaxl :: inst_ldumaxl_r_r_m -emit_ldumaxl :: emit_ldumaxl_r_r_m -inst_ldumaxal :: inst_ldumaxal_r_r_m -emit_ldumaxal :: emit_ldumaxal_r_r_m -inst_ldumin :: inst_ldumin_r_r_m -emit_ldumin :: emit_ldumin_r_r_m -inst_ldumina :: inst_ldumina_r_r_m -emit_ldumina :: emit_ldumina_r_r_m -inst_lduminl :: inst_lduminl_r_r_m -emit_lduminl :: emit_lduminl_r_r_m -inst_lduminal :: inst_lduminal_r_r_m -emit_lduminal :: emit_lduminal_r_r_m -inst_swp :: inst_swp_r_r_m -emit_swp :: emit_swp_r_r_m -inst_swpa :: inst_swpa_r_r_m -emit_swpa :: emit_swpa_r_r_m -inst_swpl :: inst_swpl_r_r_m -emit_swpl :: emit_swpl_r_r_m -inst_swpal :: inst_swpal_r_r_m -emit_swpal :: emit_swpal_r_r_m -inst_cas :: inst_cas_r_r_m -emit_cas :: emit_cas_r_r_m -inst_casa :: inst_casa_r_r_m -emit_casa :: emit_casa_r_r_m -inst_casl :: inst_casl_r_r_m -emit_casl :: emit_casl_r_r_m -inst_casal :: inst_casal_r_r_m -emit_casal :: emit_casal_r_r_m -inst_casb :: inst_casb_r_r_m -emit_casb :: emit_casb_r_r_m -inst_casab :: inst_casab_r_r_m -emit_casab :: emit_casab_r_r_m -inst_caslb :: inst_caslb_r_r_m -emit_caslb :: emit_caslb_r_r_m -inst_casalb :: inst_casalb_r_r_m -emit_casalb :: emit_casalb_r_r_m -inst_cash :: inst_cash_r_r_m -emit_cash :: emit_cash_r_r_m -inst_casah :: inst_casah_r_r_m -emit_casah :: emit_casah_r_r_m -inst_caslh :: inst_caslh_r_r_m -emit_caslh :: emit_caslh_r_r_m -inst_casalh :: inst_casalh_r_r_m -emit_casalh :: emit_casalh_r_r_m -inst_casp :: inst_casp_r_r_m -emit_casp :: emit_casp_r_r_m -inst_caspa :: inst_caspa_r_r_m -emit_caspa :: emit_caspa_r_r_m -inst_caspl :: inst_caspl_r_r_m -emit_caspl :: emit_caspl_r_r_m -inst_caspal :: inst_caspal_r_r_m -emit_caspal :: emit_caspal_r_r_m -inst_pacia :: inst_pacia_r_r -emit_pacia :: emit_pacia_r_r -inst_pacib :: inst_pacib_r_r -emit_pacib :: emit_pacib_r_r -inst_pacda :: inst_pacda_r_r -emit_pacda :: emit_pacda_r_r -inst_pacdb :: inst_pacdb_r_r -emit_pacdb :: emit_pacdb_r_r -inst_paciza :: inst_paciza_r -emit_paciza :: emit_paciza_r -inst_pacizb :: inst_pacizb_r -emit_pacizb :: emit_pacizb_r -inst_pacdza :: inst_pacdza_r -emit_pacdza :: emit_pacdza_r -inst_pacdzb :: inst_pacdzb_r -emit_pacdzb :: emit_pacdzb_r -inst_autia :: inst_autia_r_r -emit_autia :: emit_autia_r_r -inst_autib :: inst_autib_r_r -emit_autib :: emit_autib_r_r -inst_autda :: inst_autda_r_r -emit_autda :: emit_autda_r_r -inst_autdb :: inst_autdb_r_r -emit_autdb :: emit_autdb_r_r -inst_autiza :: inst_autiza_r -emit_autiza :: emit_autiza_r -inst_autizb :: inst_autizb_r -emit_autizb :: emit_autizb_r -inst_autdza :: inst_autdza_r -emit_autdza :: emit_autdza_r -inst_autdzb :: inst_autdzb_r -emit_autdzb :: emit_autdzb_r -inst_paciasp :: inst_paciasp_none -emit_paciasp :: emit_paciasp_none -inst_pacibsp :: inst_pacibsp_none -emit_pacibsp :: emit_pacibsp_none -inst_autiasp :: inst_autiasp_none -emit_autiasp :: emit_autiasp_none -inst_autibsp :: inst_autibsp_none -emit_autibsp :: emit_autibsp_none -inst_pacia1716 :: inst_pacia1716_none -emit_pacia1716 :: emit_pacia1716_none -inst_pacib1716 :: inst_pacib1716_none -emit_pacib1716 :: emit_pacib1716_none -inst_autia1716 :: inst_autia1716_none -emit_autia1716 :: emit_autia1716_none -inst_autib1716 :: inst_autib1716_none -emit_autib1716 :: emit_autib1716_none -inst_pacga :: inst_pacga_r_r_r -emit_pacga :: emit_pacga_r_r_r -inst_xpaci :: inst_xpaci_r -emit_xpaci :: emit_xpaci_r -inst_xpacd :: inst_xpacd_r -emit_xpacd :: emit_xpacd_r -inst_xpaclri :: inst_xpaclri_none -emit_xpaclri :: emit_xpaclri_none -inst_retaa :: inst_retaa_none -emit_retaa :: emit_retaa_none -inst_retab :: inst_retab_none -emit_retab :: emit_retab_none -inst_braa :: inst_braa_r_r -emit_braa :: emit_braa_r_r -inst_brab :: inst_brab_r_r -emit_brab :: emit_brab_r_r -inst_braaz :: inst_braaz_r -emit_braaz :: emit_braaz_r -inst_brabz :: inst_brabz_r -emit_brabz :: emit_brabz_r -inst_blraa :: inst_blraa_r_r -emit_blraa :: emit_blraa_r_r -inst_blrab :: inst_blrab_r_r -emit_blrab :: emit_blrab_r_r -inst_blraaz :: inst_blraaz_r -emit_blraaz :: emit_blraaz_r -inst_blrabz :: inst_blrabz_r -emit_blrabz :: emit_blrabz_r -inst_eretaa :: inst_eretaa_none -emit_eretaa :: emit_eretaa_none -inst_eretab :: inst_eretab_none -emit_eretab :: emit_eretab_none -inst_bti :: inst_bti_i -emit_bti :: emit_bti_i -inst_irg :: inst_irg_r_r_r -emit_irg :: emit_irg_r_r_r -inst_addg :: inst_addg_r_r_i_i -emit_addg :: emit_addg_r_r_i_i -inst_subg :: inst_subg_r_r_i_i -emit_subg :: emit_subg_r_r_i_i -inst_gmi :: inst_gmi_r_r_r -emit_gmi :: emit_gmi_r_r_r -inst_subp :: inst_subp_r_r_r -emit_subp :: emit_subp_r_r_r -inst_subps :: inst_subps_r_r_r -emit_subps :: emit_subps_r_r_r -inst_ldg :: inst_ldg_r_m -emit_ldg :: emit_ldg_r_m -inst_stg :: inst_stg_r_m -emit_stg :: emit_stg_r_m -inst_st2g :: inst_st2g_r_m -emit_st2g :: emit_st2g_r_m -inst_stzg :: inst_stzg_r_m -emit_stzg :: emit_stzg_r_m -inst_stz2g :: inst_stz2g_r_m -emit_stz2g :: emit_stz2g_r_m -inst_stgp :: inst_stgp_r_r_m -emit_stgp :: emit_stgp_r_r_m -inst_ldgm :: inst_ldgm_r_m -emit_ldgm :: emit_ldgm_r_m -inst_stgm :: inst_stgm_r_m -emit_stgm :: emit_stgm_r_m -inst_stzgm :: inst_stzgm_r_m -emit_stzgm :: emit_stzgm_r_m -inst_crc32b :: inst_crc32b_r_r_r -emit_crc32b :: emit_crc32b_r_r_r -inst_crc32h :: inst_crc32h_r_r_r -emit_crc32h :: emit_crc32h_r_r_r -inst_crc32w :: inst_crc32w_r_r_r -emit_crc32w :: emit_crc32w_r_r_r -inst_crc32x :: inst_crc32x_r_r_r -emit_crc32x :: emit_crc32x_r_r_r -inst_crc32cb :: inst_crc32cb_r_r_r -emit_crc32cb :: emit_crc32cb_r_r_r -inst_crc32ch :: inst_crc32ch_r_r_r -emit_crc32ch :: emit_crc32ch_r_r_r -inst_crc32cw :: inst_crc32cw_r_r_r -emit_crc32cw :: emit_crc32cw_r_r_r -inst_crc32cx :: inst_crc32cx_r_r_r -emit_crc32cx :: emit_crc32cx_r_r_r -inst_aese :: proc{ inst_aese_r_r, inst_aese_z_z } -emit_aese :: proc{ emit_aese_r_r, emit_aese_z_z } -inst_aesd :: proc{ inst_aesd_r_r, inst_aesd_z_z } -emit_aesd :: proc{ emit_aesd_r_r, emit_aesd_z_z } -inst_aesmc :: proc{ inst_aesmc_r_r, inst_aesmc_z } -emit_aesmc :: proc{ emit_aesmc_r_r, emit_aesmc_z } -inst_aesimc :: proc{ inst_aesimc_r_r, inst_aesimc_z } -emit_aesimc :: proc{ emit_aesimc_r_r, emit_aesimc_z } -inst_sha1h :: inst_sha1h_r_r -emit_sha1h :: emit_sha1h_r_r -inst_sha1c :: inst_sha1c_r_r_r -emit_sha1c :: emit_sha1c_r_r_r -inst_sha1p :: inst_sha1p_r_r_r -emit_sha1p :: emit_sha1p_r_r_r -inst_sha1m :: inst_sha1m_r_r_r -emit_sha1m :: emit_sha1m_r_r_r -inst_sha1su0 :: inst_sha1su0_r_r_r -emit_sha1su0 :: emit_sha1su0_r_r_r -inst_sha1su1 :: inst_sha1su1_r_r -emit_sha1su1 :: emit_sha1su1_r_r -inst_sha256h :: inst_sha256h_r_r_r -emit_sha256h :: emit_sha256h_r_r_r -inst_sha256h2 :: inst_sha256h2_r_r_r -emit_sha256h2 :: emit_sha256h2_r_r_r -inst_sha256su0 :: inst_sha256su0_r_r -emit_sha256su0 :: emit_sha256su0_r_r -inst_sha256su1 :: inst_sha256su1_r_r_r -emit_sha256su1 :: emit_sha256su1_r_r_r -inst_sha512h :: inst_sha512h_r_r_r -emit_sha512h :: emit_sha512h_r_r_r -inst_sha512h2 :: inst_sha512h2_r_r_r -emit_sha512h2 :: emit_sha512h2_r_r_r -inst_sha512su0 :: inst_sha512su0_r_r -emit_sha512su0 :: emit_sha512su0_r_r -inst_sha512su1 :: inst_sha512su1_r_r_r -emit_sha512su1 :: emit_sha512su1_r_r_r -inst_eor3 :: proc{ inst_eor3_r_r_r_r, inst_eor3_z_z_z_z } -emit_eor3 :: proc{ emit_eor3_r_r_r_r, emit_eor3_z_z_z_z } -inst_bcax :: proc{ inst_bcax_r_r_r_r, inst_bcax_z_z_z_z } -emit_bcax :: proc{ emit_bcax_r_r_r_r, emit_bcax_z_z_z_z } -inst_rax1 :: inst_rax1_r_r_r -emit_rax1 :: emit_rax1_r_r_r -inst_xar :: proc{ inst_xar_r_r_r_i, inst_xar_z_z_z_i } -emit_xar :: proc{ emit_xar_r_r_r_i, emit_xar_z_z_z_i } -inst_sm3partw1 :: inst_sm3partw1_r_r_r -emit_sm3partw1 :: emit_sm3partw1_r_r_r -inst_sm3partw2 :: inst_sm3partw2_r_r_r -emit_sm3partw2 :: emit_sm3partw2_r_r_r -inst_sm3ss1 :: inst_sm3ss1_r_r_r_r -emit_sm3ss1 :: emit_sm3ss1_r_r_r_r -inst_sm3tt1a :: inst_sm3tt1a_r_r_r -emit_sm3tt1a :: emit_sm3tt1a_r_r_r -inst_sm3tt1b :: inst_sm3tt1b_r_r_r -emit_sm3tt1b :: emit_sm3tt1b_r_r_r -inst_sm3tt2a :: inst_sm3tt2a_r_r_r -emit_sm3tt2a :: emit_sm3tt2a_r_r_r -inst_sm3tt2b :: inst_sm3tt2b_r_r_r -emit_sm3tt2b :: emit_sm3tt2b_r_r_r -inst_sm4e :: inst_sm4e_r_r -emit_sm4e :: emit_sm4e_r_r -inst_sm4ekey :: inst_sm4ekey_r_r_r -emit_sm4ekey :: emit_sm4ekey_r_r_r -inst_pmull :: inst_pmull_r_r_r -emit_pmull :: emit_pmull_r_r_r -inst_pmull2 :: inst_pmull2_r_r_r -emit_pmull2 :: emit_pmull2_r_r_r -inst_bfcvt :: proc{ inst_bfcvt_r_r, inst_bfcvt_z_p_z } -emit_bfcvt :: proc{ emit_bfcvt_r_r, emit_bfcvt_z_p_z } -inst_bfdot :: inst_bfdot_r_r_r -emit_bfdot :: emit_bfdot_r_r_r -inst_bfmmla :: inst_bfmmla_r_r_r -emit_bfmmla :: emit_bfmmla_r_r_r -inst_bfmlalb :: inst_bfmlalb_r_r_r -emit_bfmlalb :: emit_bfmlalb_r_r_r -inst_bfmlalt :: inst_bfmlalt_r_r_r -emit_bfmlalt :: emit_bfmlalt_r_r_r -inst_bfcvtn :: inst_bfcvtn_r_r -emit_bfcvtn :: emit_bfcvtn_r_r -inst_bfcvtn2 :: inst_bfcvtn2_r_r -emit_bfcvtn2 :: emit_bfcvtn2_r_r -inst_mul :: proc{ inst_mul_r_r_r, inst_mul_z_p_z_z } -emit_mul :: proc{ emit_mul_r_r_r, emit_mul_z_p_z_z } -inst_mla :: inst_mla_r_r_r -emit_mla :: emit_mla_r_r_r -inst_mls :: inst_mls_r_r_r -emit_mls :: emit_mls_r_r_r -inst_neg :: proc{ inst_neg_r_r, inst_neg_z_p_z, inst_neg_r_sh } -emit_neg :: proc{ emit_neg_r_r, emit_neg_z_p_z, emit_neg_r_sh } -inst_abs :: proc{ inst_abs_r_r, inst_abs_z_p_z } -emit_abs :: proc{ emit_abs_r_r, emit_abs_z_p_z } -inst_shadd :: inst_shadd_r_r_r -emit_shadd :: emit_shadd_r_r_r -inst_uhadd :: inst_uhadd_r_r_r -emit_uhadd :: emit_uhadd_r_r_r -inst_shsub :: inst_shsub_r_r_r -emit_shsub :: emit_shsub_r_r_r -inst_uhsub :: inst_uhsub_r_r_r -emit_uhsub :: emit_uhsub_r_r_r -inst_srhadd :: inst_srhadd_r_r_r -emit_srhadd :: emit_srhadd_r_r_r -inst_urhadd :: inst_urhadd_r_r_r -emit_urhadd :: emit_urhadd_r_r_r -inst_sqadd :: proc{ inst_sqadd_r_r_r, inst_sqadd_z_z_z } -emit_sqadd :: proc{ emit_sqadd_r_r_r, emit_sqadd_z_z_z } -inst_uqadd :: proc{ inst_uqadd_r_r_r, inst_uqadd_z_z_z } -emit_uqadd :: proc{ emit_uqadd_r_r_r, emit_uqadd_z_z_z } -inst_sqsub :: proc{ inst_sqsub_r_r_r, inst_sqsub_z_z_z } -emit_sqsub :: proc{ emit_sqsub_r_r_r, emit_sqsub_z_z_z } -inst_uqsub :: proc{ inst_uqsub_r_r_r, inst_uqsub_z_z_z } -emit_uqsub :: proc{ emit_uqsub_r_r_r, emit_uqsub_z_z_z } -inst_smax :: proc{ inst_smax_r_r_r, inst_smax_z_p_z_z } -emit_smax :: proc{ emit_smax_r_r_r, emit_smax_z_p_z_z } -inst_umax :: proc{ inst_umax_r_r_r, inst_umax_z_p_z_z } -emit_umax :: proc{ emit_umax_r_r_r, emit_umax_z_p_z_z } -inst_smin :: proc{ inst_smin_r_r_r, inst_smin_z_p_z_z } -emit_smin :: proc{ emit_smin_r_r_r, emit_smin_z_p_z_z } -inst_umin :: proc{ inst_umin_r_r_r, inst_umin_z_p_z_z } -emit_umin :: proc{ emit_umin_r_r_r, emit_umin_z_p_z_z } -inst_sabd :: proc{ inst_sabd_r_r_r, inst_sabd_z_p_z_z } -emit_sabd :: proc{ emit_sabd_r_r_r, emit_sabd_z_p_z_z } -inst_uabd :: proc{ inst_uabd_r_r_r, inst_uabd_z_p_z_z } -emit_uabd :: proc{ emit_uabd_r_r_r, emit_uabd_z_p_z_z } -inst_saba :: inst_saba_r_r_r -emit_saba :: emit_saba_r_r_r -inst_uaba :: inst_uaba_r_r_r -emit_uaba :: emit_uaba_r_r_r -inst_addp :: inst_addp_r_r_r -emit_addp :: emit_addp_r_r_r -inst_addv :: inst_addv_r_r -emit_addv :: emit_addv_r_r -inst_saddlp :: inst_saddlp_r_r -emit_saddlp :: emit_saddlp_r_r -inst_uaddlp :: inst_uaddlp_r_r -emit_uaddlp :: emit_uaddlp_r_r -inst_sadalp :: inst_sadalp_r_r -emit_sadalp :: emit_sadalp_r_r -inst_uadalp :: inst_uadalp_r_r -emit_uadalp :: emit_uadalp_r_r -inst_saddlv :: inst_saddlv_r_r -emit_saddlv :: emit_saddlv_r_r -inst_uaddlv :: inst_uaddlv_r_r -emit_uaddlv :: emit_uaddlv_r_r -inst_smaxv :: inst_smaxv_r_r -emit_smaxv :: emit_smaxv_r_r -inst_umaxv :: inst_umaxv_r_r -emit_umaxv :: emit_umaxv_r_r -inst_sminv :: inst_sminv_r_r -emit_sminv :: emit_sminv_r_r -inst_uminv :: inst_uminv_r_r -emit_uminv :: emit_uminv_r_r -inst_smaxp :: inst_smaxp_r_r_r -emit_smaxp :: emit_smaxp_r_r_r -inst_umaxp :: inst_umaxp_r_r_r -emit_umaxp :: emit_umaxp_r_r_r -inst_sminp :: inst_sminp_r_r_r -emit_sminp :: emit_sminp_r_r_r -inst_uminp :: inst_uminp_r_r_r -emit_uminp :: emit_uminp_r_r_r -inst_saddl :: inst_saddl_r_r_r -emit_saddl :: emit_saddl_r_r_r -inst_saddl2 :: inst_saddl2_r_r_r -emit_saddl2 :: emit_saddl2_r_r_r -inst_uaddl :: inst_uaddl_r_r_r -emit_uaddl :: emit_uaddl_r_r_r -inst_uaddl2 :: inst_uaddl2_r_r_r -emit_uaddl2 :: emit_uaddl2_r_r_r -inst_ssubl :: inst_ssubl_r_r_r -emit_ssubl :: emit_ssubl_r_r_r -inst_ssubl2 :: inst_ssubl2_r_r_r -emit_ssubl2 :: emit_ssubl2_r_r_r -inst_usubl :: inst_usubl_r_r_r -emit_usubl :: emit_usubl_r_r_r -inst_usubl2 :: inst_usubl2_r_r_r -emit_usubl2 :: emit_usubl2_r_r_r -inst_saddw :: inst_saddw_r_r_r -emit_saddw :: emit_saddw_r_r_r -inst_saddw2 :: inst_saddw2_r_r_r -emit_saddw2 :: emit_saddw2_r_r_r -inst_uaddw :: inst_uaddw_r_r_r -emit_uaddw :: emit_uaddw_r_r_r -inst_uaddw2 :: inst_uaddw2_r_r_r -emit_uaddw2 :: emit_uaddw2_r_r_r -inst_ssubw :: inst_ssubw_r_r_r -emit_ssubw :: emit_ssubw_r_r_r -inst_ssubw2 :: inst_ssubw2_r_r_r -emit_ssubw2 :: emit_ssubw2_r_r_r -inst_usubw :: inst_usubw_r_r_r -emit_usubw :: emit_usubw_r_r_r -inst_usubw2 :: inst_usubw2_r_r_r -emit_usubw2 :: emit_usubw2_r_r_r -inst_raddhn :: inst_raddhn_r_r_r -emit_raddhn :: emit_raddhn_r_r_r -inst_raddhn2 :: inst_raddhn2_r_r_r -emit_raddhn2 :: emit_raddhn2_r_r_r -inst_rsubhn :: inst_rsubhn_r_r_r -emit_rsubhn :: emit_rsubhn_r_r_r -inst_rsubhn2 :: inst_rsubhn2_r_r_r -emit_rsubhn2 :: emit_rsubhn2_r_r_r -inst_addhn :: inst_addhn_r_r_r -emit_addhn :: emit_addhn_r_r_r -inst_addhn2 :: inst_addhn2_r_r_r -emit_addhn2 :: emit_addhn2_r_r_r -inst_subhn :: inst_subhn_r_r_r -emit_subhn :: emit_subhn_r_r_r -inst_subhn2 :: inst_subhn2_r_r_r -emit_subhn2 :: emit_subhn2_r_r_r -inst_xtn :: inst_xtn_r_r -emit_xtn :: emit_xtn_r_r -inst_xtn2 :: inst_xtn2_r_r -emit_xtn2 :: emit_xtn2_r_r -inst_sqxtn :: inst_sqxtn_r_r -emit_sqxtn :: emit_sqxtn_r_r -inst_sqxtn2 :: inst_sqxtn2_r_r -emit_sqxtn2 :: emit_sqxtn2_r_r -inst_uqxtn :: inst_uqxtn_r_r -emit_uqxtn :: emit_uqxtn_r_r -inst_uqxtn2 :: inst_uqxtn2_r_r -emit_uqxtn2 :: emit_uqxtn2_r_r -inst_sqxtun :: inst_sqxtun_r_r -emit_sqxtun :: emit_sqxtun_r_r -inst_sqxtun2 :: inst_sqxtun2_r_r -emit_sqxtun2 :: emit_sqxtun2_r_r -inst_smull :: inst_smull_r_r_r -emit_smull :: emit_smull_r_r_r -inst_smull2 :: inst_smull2_r_r_r -emit_smull2 :: emit_smull2_r_r_r -inst_umull :: inst_umull_r_r_r -emit_umull :: emit_umull_r_r_r -inst_umull2 :: inst_umull2_r_r_r -emit_umull2 :: emit_umull2_r_r_r -inst_smlal :: inst_smlal_r_r_r -emit_smlal :: emit_smlal_r_r_r -inst_smlal2 :: inst_smlal2_r_r_r -emit_smlal2 :: emit_smlal2_r_r_r -inst_umlal :: inst_umlal_r_r_r -emit_umlal :: emit_umlal_r_r_r -inst_umlal2 :: inst_umlal2_r_r_r -emit_umlal2 :: emit_umlal2_r_r_r -inst_smlsl :: inst_smlsl_r_r_r -emit_smlsl :: emit_smlsl_r_r_r -inst_smlsl2 :: inst_smlsl2_r_r_r -emit_smlsl2 :: emit_smlsl2_r_r_r -inst_umlsl :: inst_umlsl_r_r_r -emit_umlsl :: emit_umlsl_r_r_r -inst_umlsl2 :: inst_umlsl2_r_r_r -emit_umlsl2 :: emit_umlsl2_r_r_r -inst_sqdmull :: inst_sqdmull_r_r_r -emit_sqdmull :: emit_sqdmull_r_r_r -inst_sqdmull2 :: inst_sqdmull2_r_r_r -emit_sqdmull2 :: emit_sqdmull2_r_r_r -inst_sqdmlal :: inst_sqdmlal_r_r_r -emit_sqdmlal :: emit_sqdmlal_r_r_r -inst_sqdmlal2 :: inst_sqdmlal2_r_r_r -emit_sqdmlal2 :: emit_sqdmlal2_r_r_r -inst_sqdmlsl :: inst_sqdmlsl_r_r_r -emit_sqdmlsl :: emit_sqdmlsl_r_r_r -inst_sqdmlsl2 :: inst_sqdmlsl2_r_r_r -emit_sqdmlsl2 :: emit_sqdmlsl2_r_r_r -inst_sqdmulh :: inst_sqdmulh_r_r_r -emit_sqdmulh :: emit_sqdmulh_r_r_r -inst_sqrdmulh :: inst_sqrdmulh_r_r_r -emit_sqrdmulh :: emit_sqrdmulh_r_r_r -inst_sdot :: inst_sdot_r_r_r -emit_sdot :: emit_sdot_r_r_r -inst_udot :: inst_udot_r_r_r -emit_udot :: emit_udot_r_r_r -inst_usdot :: inst_usdot_r_r_r -emit_usdot :: emit_usdot_r_r_r -inst_fmla :: proc{ inst_fmla_r_r_r, inst_fmla_z_p_z_z, inst_fmla_z_z_z_i } -emit_fmla :: proc{ emit_fmla_r_r_r, emit_fmla_z_p_z_z, emit_fmla_z_z_z_i } -inst_fmls :: proc{ inst_fmls_r_r_r, inst_fmls_z_p_z_z, inst_fmls_z_z_z_i } -emit_fmls :: proc{ emit_fmls_r_r_r, emit_fmls_z_p_z_z, emit_fmls_z_z_z_i } -inst_fmulx :: inst_fmulx_r_r_r -emit_fmulx :: emit_fmulx_r_r_r -inst_fmaxp :: inst_fmaxp_r_r_r -emit_fmaxp :: emit_fmaxp_r_r_r -inst_fminp :: inst_fminp_r_r_r -emit_fminp :: emit_fminp_r_r_r -inst_fmaxnmp :: inst_fmaxnmp_r_r_r -emit_fmaxnmp :: emit_fmaxnmp_r_r_r -inst_fminnmp :: inst_fminnmp_r_r_r -emit_fminnmp :: emit_fminnmp_r_r_r -inst_fmaxv :: inst_fmaxv_r_r -emit_fmaxv :: emit_fmaxv_r_r -inst_fminv :: inst_fminv_r_r -emit_fminv :: emit_fminv_r_r -inst_fmaxnmv :: inst_fmaxnmv_r_r -emit_fmaxnmv :: emit_fmaxnmv_r_r -inst_fminnmv :: inst_fminnmv_r_r -emit_fminnmv :: emit_fminnmv_r_r -inst_frecpe :: inst_frecpe_r_r -emit_frecpe :: emit_frecpe_r_r -inst_frsqrte :: inst_frsqrte_r_r -emit_frsqrte :: emit_frsqrte_r_r -inst_frecps :: proc{ inst_frecps_r_r_r, inst_frecps_z_z_z } -emit_frecps :: proc{ emit_frecps_r_r_r, emit_frecps_z_z_z } -inst_frsqrts :: proc{ inst_frsqrts_r_r_r, inst_frsqrts_z_z_z } -emit_frsqrts :: proc{ emit_frsqrts_r_r_r, emit_frsqrts_z_z_z } -inst_frecpx :: proc{ inst_frecpx_r_r, inst_frecpx_z_p_z } -emit_frecpx :: proc{ emit_frecpx_r_r, emit_frecpx_z_p_z } -inst_faddp :: inst_faddp_r_r_r -emit_faddp :: emit_faddp_r_r_r -inst_fcvtl :: inst_fcvtl_r_r -emit_fcvtl :: emit_fcvtl_r_r -inst_fcvtl2 :: inst_fcvtl2_r_r -emit_fcvtl2 :: emit_fcvtl2_r_r -inst_fcvtn :: inst_fcvtn_r_r -emit_fcvtn :: emit_fcvtn_r_r -inst_fcvtn2 :: inst_fcvtn2_r_r -emit_fcvtn2 :: emit_fcvtn2_r_r -inst_fcvtxn :: inst_fcvtxn_r_r -emit_fcvtxn :: emit_fcvtxn_r_r -inst_fcvtxn2 :: inst_fcvtxn2_r_r -emit_fcvtxn2 :: emit_fcvtxn2_r_r -inst_fcmeq :: proc{ inst_fcmeq_r_r_r, inst_fcmeq_p_p_z_z } -emit_fcmeq :: proc{ emit_fcmeq_r_r_r, emit_fcmeq_p_p_z_z } -inst_fcmge :: proc{ inst_fcmge_r_r_r, inst_fcmge_p_p_z_z } -emit_fcmge :: proc{ emit_fcmge_r_r_r, emit_fcmge_p_p_z_z } -inst_fcmgt :: proc{ inst_fcmgt_r_r_r, inst_fcmgt_p_p_z_z } -emit_fcmgt :: proc{ emit_fcmgt_r_r_r, emit_fcmgt_p_p_z_z } -inst_fcmle :: proc{ inst_fcmle_r_r, inst_fcmle_p_p_z } -emit_fcmle :: proc{ emit_fcmle_r_r, emit_fcmle_p_p_z } -inst_fcmlt :: proc{ inst_fcmlt_r_r, inst_fcmlt_p_p_z } -emit_fcmlt :: proc{ emit_fcmlt_r_r, emit_fcmlt_p_p_z } -inst_facge :: inst_facge_r_r_r -emit_facge :: emit_facge_r_r_r -inst_facgt :: inst_facgt_r_r_r -emit_facgt :: emit_facgt_r_r_r -inst_cmeq :: inst_cmeq_r_r_r -emit_cmeq :: emit_cmeq_r_r_r -inst_cmge :: inst_cmge_r_r_r -emit_cmge :: emit_cmge_r_r_r -inst_cmgt :: inst_cmgt_r_r_r -emit_cmgt :: emit_cmgt_r_r_r -inst_cmhi :: inst_cmhi_r_r_r -emit_cmhi :: emit_cmhi_r_r_r -inst_cmhs :: inst_cmhs_r_r_r -emit_cmhs :: emit_cmhs_r_r_r -inst_cmle :: inst_cmle_r_r -emit_cmle :: emit_cmle_r_r -inst_cmlt :: inst_cmlt_r_r -emit_cmlt :: emit_cmlt_r_r -inst_cmtst :: inst_cmtst_r_r_r -emit_cmtst :: emit_cmtst_r_r_r -inst_mvn :: inst_mvn_r_r -emit_mvn :: emit_mvn_r_r -inst_bit :: inst_bit_r_r_r -emit_bit :: emit_bit_r_r_r -inst_bif :: inst_bif_r_r_r -emit_bif :: emit_bif_r_r_r -inst_bsl :: proc{ inst_bsl_r_r_r, inst_bsl_z_z_z_z } -emit_bsl :: proc{ emit_bsl_r_r_r, emit_bsl_z_z_z_z } -inst_shl :: inst_shl_r_r_i -emit_shl :: emit_shl_r_r_i -inst_sqshl :: inst_sqshl_r_r_i -emit_sqshl :: emit_sqshl_r_r_i -inst_sqshlu :: inst_sqshlu_r_r_i -emit_sqshlu :: emit_sqshlu_r_r_i -inst_srshl :: inst_srshl_r_r_r -emit_srshl :: emit_srshl_r_r_r -inst_urshl :: inst_urshl_r_r_r -emit_urshl :: emit_urshl_r_r_r -inst_sshr :: inst_sshr_r_r_i -emit_sshr :: emit_sshr_r_r_i -inst_ushr :: inst_ushr_r_r_i -emit_ushr :: emit_ushr_r_r_i -inst_ssra :: inst_ssra_r_r_i -emit_ssra :: emit_ssra_r_r_i -inst_usra :: inst_usra_r_r_i -emit_usra :: emit_usra_r_r_i -inst_srshr :: inst_srshr_r_r_i -emit_srshr :: emit_srshr_r_r_i -inst_urshr :: inst_urshr_r_r_i -emit_urshr :: emit_urshr_r_r_i -inst_srsra :: inst_srsra_r_r_i -emit_srsra :: emit_srsra_r_r_i -inst_ursra :: inst_ursra_r_r_i -emit_ursra :: emit_ursra_r_r_i -inst_sshl :: inst_sshl_r_r_r -emit_sshl :: emit_sshl_r_r_r -inst_ushl :: inst_ushl_r_r_r -emit_ushl :: emit_ushl_r_r_r -inst_sli :: inst_sli_r_r_i -emit_sli :: emit_sli_r_r_i -inst_sri :: inst_sri_r_r_i -emit_sri :: emit_sri_r_r_i -inst_sshll :: inst_sshll_r_r_i -emit_sshll :: emit_sshll_r_r_i -inst_sshll2 :: inst_sshll2_r_r_i -emit_sshll2 :: emit_sshll2_r_r_i -inst_ushll :: inst_ushll_r_r_i -emit_ushll :: emit_ushll_r_r_i -inst_ushll2 :: inst_ushll2_r_r_i -emit_ushll2 :: emit_ushll2_r_r_i -inst_sxtl :: inst_sxtl_r_r -emit_sxtl :: emit_sxtl_r_r -inst_sxtl2 :: inst_sxtl2_r_r -emit_sxtl2 :: emit_sxtl2_r_r -inst_uxtl :: inst_uxtl_r_r -emit_uxtl :: emit_uxtl_r_r -inst_uxtl2 :: inst_uxtl2_r_r -emit_uxtl2 :: emit_uxtl2_r_r -inst_shrn :: inst_shrn_r_r_i -emit_shrn :: emit_shrn_r_r_i -inst_shrn2 :: inst_shrn2_r_r_i -emit_shrn2 :: emit_shrn2_r_r_i -inst_rshrn :: inst_rshrn_r_r_i -emit_rshrn :: emit_rshrn_r_r_i -inst_rshrn2 :: inst_rshrn2_r_r_i -emit_rshrn2 :: emit_rshrn2_r_r_i -inst_sqshrn :: inst_sqshrn_r_r_i -emit_sqshrn :: emit_sqshrn_r_r_i -inst_sqshrn2 :: inst_sqshrn2_r_r_i -emit_sqshrn2 :: emit_sqshrn2_r_r_i -inst_uqshrn :: inst_uqshrn_r_r_i -emit_uqshrn :: emit_uqshrn_r_r_i -inst_uqshrn2 :: inst_uqshrn2_r_r_i -emit_uqshrn2 :: emit_uqshrn2_r_r_i -inst_sqrshrn :: inst_sqrshrn_r_r_i -emit_sqrshrn :: emit_sqrshrn_r_r_i -inst_sqrshrn2 :: inst_sqrshrn2_r_r_i -emit_sqrshrn2 :: emit_sqrshrn2_r_r_i -inst_uqrshrn :: inst_uqrshrn_r_r_i -emit_uqrshrn :: emit_uqrshrn_r_r_i -inst_uqrshrn2 :: inst_uqrshrn2_r_r_i -emit_uqrshrn2 :: emit_uqrshrn2_r_r_i -inst_sqshrun :: inst_sqshrun_r_r_i -emit_sqshrun :: emit_sqshrun_r_r_i -inst_sqshrun2 :: inst_sqshrun2_r_r_i -emit_sqshrun2 :: emit_sqshrun2_r_r_i -inst_sqrshrun :: inst_sqrshrun_r_r_i -emit_sqrshrun :: emit_sqrshrun_r_r_i -inst_sqrshrun2 :: inst_sqrshrun2_r_r_i -emit_sqrshrun2 :: emit_sqrshrun2_r_r_i -inst_dup :: proc{ inst_dup_r_r_i, inst_dup_r_r, inst_dup_z_r } -emit_dup :: proc{ emit_dup_r_r_i, emit_dup_r_r, emit_dup_z_r } -inst_ins :: proc{ inst_ins_r_i_r_i, inst_ins_r_i_r } -emit_ins :: proc{ emit_ins_r_i_r_i, emit_ins_r_i_r } -inst_mov :: proc{ inst_mov_r_r, inst_mov_z_p_z, inst_mov_p_p, inst_mov_r_i } -emit_mov :: proc{ emit_mov_r_r, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } -inst_ext :: proc{ inst_ext_r_r_r_i, inst_ext_z_z_z_i } -emit_ext :: proc{ emit_ext_r_r_r_i, emit_ext_z_z_z_i } -inst_tbl :: proc{ inst_tbl_r_r_r, inst_tbl_z_z_z } -emit_tbl :: proc{ emit_tbl_r_r_r, emit_tbl_z_z_z } -inst_tbx :: proc{ inst_tbx_r_r_r, inst_tbx_z_z_z } -emit_tbx :: proc{ emit_tbx_r_r_r, emit_tbx_z_z_z } -inst_zip1 :: proc{ inst_zip1_r_r_r, inst_zip1_z_z_z } -emit_zip1 :: proc{ emit_zip1_r_r_r, emit_zip1_z_z_z } -inst_zip2 :: proc{ inst_zip2_r_r_r, inst_zip2_z_z_z } -emit_zip2 :: proc{ emit_zip2_r_r_r, emit_zip2_z_z_z } -inst_uzp1 :: proc{ inst_uzp1_r_r_r, inst_uzp1_z_z_z } -emit_uzp1 :: proc{ emit_uzp1_r_r_r, emit_uzp1_z_z_z } -inst_uzp2 :: proc{ inst_uzp2_r_r_r, inst_uzp2_z_z_z } -emit_uzp2 :: proc{ emit_uzp2_r_r_r, emit_uzp2_z_z_z } -inst_trn1 :: proc{ inst_trn1_r_r_r, inst_trn1_z_z_z } -emit_trn1 :: proc{ emit_trn1_r_r_r, emit_trn1_z_z_z } -inst_trn2 :: proc{ inst_trn2_r_r_r, inst_trn2_z_z_z } -emit_trn2 :: proc{ emit_trn2_r_r_r, emit_trn2_z_z_z } -inst_not :: proc{ inst_not_r_r, inst_not_p_p_p } -emit_not :: proc{ emit_not_r_r, emit_not_p_p_p } -inst_rev64 :: inst_rev64_r_r -emit_rev64 :: emit_rev64_r_r -inst_cnt :: proc{ inst_cnt_r_r, inst_cnt_z_p_z } -emit_cnt :: proc{ emit_cnt_r_r, emit_cnt_z_p_z } -inst_urecpe :: inst_urecpe_r_r -emit_urecpe :: emit_urecpe_r_r -inst_ursqrte :: inst_ursqrte_r_r -emit_ursqrte :: emit_ursqrte_r_r -inst_movi :: inst_movi_r_i -emit_movi :: emit_movi_r_i -inst_mvni :: inst_mvni_r_i -emit_mvni :: emit_mvni_r_i -inst_ld1 :: proc{ inst_ld1_r_m, inst_ld1_r_i_m } -emit_ld1 :: proc{ emit_ld1_r_m, emit_ld1_r_i_m } -inst_ld2 :: proc{ inst_ld2_r_m, inst_ld2_r_i_m } -emit_ld2 :: proc{ emit_ld2_r_m, emit_ld2_r_i_m } -inst_ld3 :: proc{ inst_ld3_r_m, inst_ld3_r_i_m } -emit_ld3 :: proc{ emit_ld3_r_m, emit_ld3_r_i_m } -inst_ld4 :: proc{ inst_ld4_r_m, inst_ld4_r_i_m } -emit_ld4 :: proc{ emit_ld4_r_m, emit_ld4_r_i_m } -inst_st1 :: proc{ inst_st1_r_m, inst_st1_r_i_m } -emit_st1 :: proc{ emit_st1_r_m, emit_st1_r_i_m } -inst_st2 :: proc{ inst_st2_r_m, inst_st2_r_i_m } -emit_st2 :: proc{ emit_st2_r_m, emit_st2_r_i_m } -inst_st3 :: proc{ inst_st3_r_m, inst_st3_r_i_m } -emit_st3 :: proc{ emit_st3_r_m, emit_st3_r_i_m } -inst_st4 :: proc{ inst_st4_r_m, inst_st4_r_i_m } -emit_st4 :: proc{ emit_st4_r_m, emit_st4_r_i_m } -inst_ld1r :: inst_ld1r_r_m -emit_ld1r :: emit_ld1r_r_m -inst_ld2r :: inst_ld2r_r_m -emit_ld2r :: emit_ld2r_r_m -inst_ld3r :: inst_ld3r_r_m -emit_ld3r :: emit_ld3r_r_m -inst_ld4r :: inst_ld4r_r_m -emit_ld4r :: emit_ld4r_r_m -inst_subr :: inst_subr_z_p_z_z -emit_subr :: emit_subr_z_p_z_z -inst_asrr :: inst_asrr_z_p_z_z -emit_asrr :: emit_asrr_z_p_z_z -inst_lslr :: inst_lslr_z_p_z_z -emit_lslr :: emit_lslr_z_p_z_z -inst_lsrr :: inst_lsrr_z_p_z_z -emit_lsrr :: emit_lsrr_z_p_z_z -inst_ftsmul :: inst_ftsmul_z_z_z -emit_ftsmul :: emit_ftsmul_z_z_z -inst_fsubr :: inst_fsubr_z_p_z_z -emit_fsubr :: emit_fsubr_z_p_z_z -inst_fdivr :: inst_fdivr_z_p_z_z -emit_fdivr :: emit_fdivr_z_p_z_z -inst_fnmla :: inst_fnmla_z_p_z_z -emit_fnmla :: emit_fnmla_z_p_z_z -inst_fnmls :: inst_fnmls_z_p_z_z -emit_fnmls :: emit_fnmls_z_p_z_z -inst_nand :: inst_nand_p_p_p_p -emit_nand :: emit_nand_p_p_p_p -inst_nor :: inst_nor_p_p_p_p -emit_nor :: emit_nor_p_p_p_p -inst_sel :: inst_sel_p_p_p_p -emit_sel :: emit_sel_p_p_p_p -inst_orrs :: inst_orrs_p_p_p_p -emit_orrs :: emit_orrs_p_p_p_p -inst_eors :: inst_eors_p_p_p_p -emit_eors :: emit_eors_p_p_p_p -inst_nands :: inst_nands_p_p_p_p -emit_nands :: emit_nands_p_p_p_p -inst_nors :: inst_nors_p_p_p_p -emit_nors :: emit_nors_p_p_p_p -inst_orns :: inst_orns_p_p_p_p -emit_orns :: emit_orns_p_p_p_p -inst_movs :: inst_movs_p_p_p -emit_movs :: emit_movs_p_p_p -inst_ptrue :: inst_ptrue_p_i -emit_ptrue :: emit_ptrue_p_i -inst_ptrues :: inst_ptrues_p_i -emit_ptrues :: emit_ptrues_p_i -inst_pfalse :: inst_pfalse_p -emit_pfalse :: emit_pfalse_p -inst_pfirst :: inst_pfirst_p_p_p -emit_pfirst :: emit_pfirst_p_p_p -inst_pnext :: inst_pnext_p_p_p -emit_pnext :: emit_pnext_p_p_p -inst_brka :: inst_brka_p_p_p -emit_brka :: emit_brka_p_p_p -inst_brkb :: inst_brkb_p_p_p -emit_brkb :: emit_brkb_p_p_p -inst_brkas :: inst_brkas_p_p_p -emit_brkas :: emit_brkas_p_p_p -inst_brkbs :: inst_brkbs_p_p_p -emit_brkbs :: emit_brkbs_p_p_p -inst_brkpa :: inst_brkpa_p_p_p_p -emit_brkpa :: emit_brkpa_p_p_p_p -inst_brkpb :: inst_brkpb_p_p_p_p -emit_brkpb :: emit_brkpb_p_p_p_p -inst_brkn :: inst_brkn_p_p_p_p -emit_brkn :: emit_brkn_p_p_p_p -inst_rdffr :: inst_rdffr_p -emit_rdffr :: emit_rdffr_p -inst_wrffr :: inst_wrffr_p -emit_wrffr :: emit_wrffr_p -inst_setffr :: inst_setffr_none -emit_setffr :: emit_setffr_none -inst_cmpeq :: inst_cmpeq_p_p_z_z -emit_cmpeq :: emit_cmpeq_p_p_z_z -inst_cmpne :: inst_cmpne_p_p_z_z -emit_cmpne :: emit_cmpne_p_p_z_z -inst_cmpge :: inst_cmpge_p_p_z_z -emit_cmpge :: emit_cmpge_p_p_z_z -inst_cmpgt :: inst_cmpgt_p_p_z_z -emit_cmpgt :: emit_cmpgt_p_p_z_z -inst_cmple :: inst_cmple_p_p_z_z -emit_cmple :: emit_cmple_p_p_z_z -inst_cmplt :: inst_cmplt_p_p_z_z -emit_cmplt :: emit_cmplt_p_p_z_z -inst_cmphi :: inst_cmphi_p_p_z_z -emit_cmphi :: emit_cmphi_p_p_z_z -inst_cmphs :: inst_cmphs_p_p_z_z -emit_cmphs :: emit_cmphs_p_p_z_z -inst_cmplo :: inst_cmplo_p_p_z_z -emit_cmplo :: emit_cmplo_p_p_z_z -inst_cmpls :: inst_cmpls_p_p_z_z -emit_cmpls :: emit_cmpls_p_p_z_z -inst_fcmne :: inst_fcmne_p_p_z_z -emit_fcmne :: emit_fcmne_p_p_z_z -inst_fcmuo :: inst_fcmuo_p_p_z_z -emit_fcmuo :: emit_fcmuo_p_p_z_z -inst_insr :: inst_insr_z_r -emit_insr :: emit_insr_z_r -inst_cpy :: inst_cpy_z_p_r -emit_cpy :: emit_cpy_z_p_r -inst_compact :: inst_compact_z_p_z -emit_compact :: emit_compact_z_p_z -inst_ld1b :: proc{ inst_ld1b_z_p_m, inst_ld1b_i_p_m } -emit_ld1b :: proc{ emit_ld1b_z_p_m, emit_ld1b_i_p_m } -inst_ld1h :: proc{ inst_ld1h_z_p_m, inst_ld1h_i_p_m } -emit_ld1h :: proc{ emit_ld1h_z_p_m, emit_ld1h_i_p_m } -inst_ld1w :: proc{ inst_ld1w_z_p_m, inst_ld1w_i_p_m } -emit_ld1w :: proc{ emit_ld1w_z_p_m, emit_ld1w_i_p_m } -inst_ld1d :: proc{ inst_ld1d_z_p_m, inst_ld1d_i_p_m } -emit_ld1d :: proc{ emit_ld1d_z_p_m, emit_ld1d_i_p_m } -inst_ld1sb :: inst_ld1sb_z_p_m -emit_ld1sb :: emit_ld1sb_z_p_m -inst_ld1sh :: inst_ld1sh_z_p_m -emit_ld1sh :: emit_ld1sh_z_p_m -inst_ld1sw :: inst_ld1sw_z_p_m -emit_ld1sw :: emit_ld1sw_z_p_m -inst_st1b :: proc{ inst_st1b_z_p_m, inst_st1b_i_p_m } -emit_st1b :: proc{ emit_st1b_z_p_m, emit_st1b_i_p_m } -inst_st1h :: proc{ inst_st1h_z_p_m, inst_st1h_i_p_m } -emit_st1h :: proc{ emit_st1h_z_p_m, emit_st1h_i_p_m } -inst_st1w :: proc{ inst_st1w_z_p_m, inst_st1w_i_p_m } -emit_st1w :: proc{ emit_st1w_z_p_m, emit_st1w_i_p_m } -inst_st1d :: proc{ inst_st1d_z_p_m, inst_st1d_i_p_m } -emit_st1d :: proc{ emit_st1d_z_p_m, emit_st1d_i_p_m } -inst_ldff1b :: inst_ldff1b_z_p_m -emit_ldff1b :: emit_ldff1b_z_p_m -inst_ldff1h :: inst_ldff1h_z_p_m -emit_ldff1h :: emit_ldff1h_z_p_m -inst_ldff1w :: inst_ldff1w_z_p_m -emit_ldff1w :: emit_ldff1w_z_p_m -inst_ldff1d :: inst_ldff1d_z_p_m -emit_ldff1d :: emit_ldff1d_z_p_m -inst_whilege :: inst_whilege_p_r_r -emit_whilege :: emit_whilege_p_r_r -inst_whilegt :: inst_whilegt_p_r_r -emit_whilegt :: emit_whilegt_p_r_r -inst_whilele :: inst_whilele_p_r_r -emit_whilele :: emit_whilele_p_r_r -inst_whilelt :: inst_whilelt_p_r_r -emit_whilelt :: emit_whilelt_p_r_r -inst_whilehi :: inst_whilehi_p_r_r -emit_whilehi :: emit_whilehi_p_r_r -inst_whilehs :: inst_whilehs_p_r_r -emit_whilehs :: emit_whilehs_p_r_r -inst_whilelo :: inst_whilelo_p_r_r -emit_whilelo :: emit_whilelo_p_r_r -inst_whilels :: inst_whilels_p_r_r -emit_whilels :: emit_whilels_p_r_r -inst_sqrdmlah :: inst_sqrdmlah_z_z_z -emit_sqrdmlah :: emit_sqrdmlah_z_z_z -inst_sqrdmlsh :: inst_sqrdmlsh_z_z_z -emit_sqrdmlsh :: emit_sqrdmlsh_z_z_z -inst_adclb :: inst_adclb_z_z_z -emit_adclb :: emit_adclb_z_z_z -inst_adclt :: inst_adclt_z_z_z -emit_adclt :: emit_adclt_z_z_z -inst_sbclb :: inst_sbclb_z_z_z -emit_sbclb :: emit_sbclb_z_z_z -inst_sbclt :: inst_sbclt_z_z_z -emit_sbclt :: emit_sbclt_z_z_z -inst_tbl2 :: inst_tbl2_z_z_z -emit_tbl2 :: emit_tbl2_z_z_z -inst_match :: inst_match_p_p_z_z -emit_match :: emit_match_p_p_z_z -inst_nmatch :: inst_nmatch_p_p_z_z -emit_nmatch :: emit_nmatch_p_p_z_z -inst_histcnt :: inst_histcnt_z_p_z_z -emit_histcnt :: emit_histcnt_z_p_z_z -inst_histseg :: inst_histseg_z_z_z -emit_histseg :: emit_histseg_z_z_z -inst_smstart :: inst_smstart_none -emit_smstart :: emit_smstart_none -inst_smstop :: inst_smstop_none -emit_smstop :: emit_smstop_none -inst_rdsvl :: inst_rdsvl_r_i -emit_rdsvl :: emit_rdsvl_r_i -inst_addha :: inst_addha_i_p_p_z -emit_addha :: emit_addha_i_p_p_z -inst_addva :: inst_addva_i_p_p_z -emit_addva :: emit_addva_i_p_p_z -inst_zero :: inst_zero_i -emit_zero :: emit_zero_i -inst_fmopa :: inst_fmopa_i_p_p_z -emit_fmopa :: emit_fmopa_i_p_p_z -inst_fmops :: inst_fmops_i_p_p_z -emit_fmops :: emit_fmops_i_p_p_z -inst_bfmopa :: inst_bfmopa_i_p_p_z -emit_bfmopa :: emit_bfmopa_i_p_p_z -inst_bfmops :: inst_bfmops_i_p_p_z -emit_bfmops :: emit_bfmops_i_p_p_z -inst_smopa :: inst_smopa_i_p_p_z -emit_smopa :: emit_smopa_i_p_p_z -inst_smops :: inst_smops_i_p_p_z -emit_smops :: emit_smops_i_p_p_z -inst_umopa :: inst_umopa_i_p_p_z -emit_umopa :: emit_umopa_i_p_p_z -inst_umops :: inst_umops_i_p_p_z -emit_umops :: emit_umops_i_p_p_z -inst_usmopa :: inst_usmopa_i_p_p_z -emit_usmopa :: emit_usmopa_i_p_p_z -inst_sumopa :: inst_sumopa_i_p_p_z -emit_sumopa :: emit_sumopa_i_p_p_z -inst_ld1q :: inst_ld1q_i_p_m -emit_ld1q :: emit_ld1q_i_p_m -inst_st1q :: inst_st1q_i_p_m -emit_st1q :: emit_st1q_i_p_m -inst_mova :: proc{ inst_mova_z_p_i, inst_mova_i_p_z } -emit_mova :: proc{ emit_mova_z_p_i, emit_mova_i_p_z } -inst_fcmla :: inst_fcmla_r_r_r_i -emit_fcmla :: emit_fcmla_r_r_r_i -inst_fcadd :: inst_fcadd_r_r_r_i -emit_fcadd :: emit_fcadd_r_r_r_i -inst_prfb :: inst_prfb_i_p_m -emit_prfb :: emit_prfb_i_p_m -inst_prfh :: inst_prfh_i_p_m -emit_prfh :: emit_prfh_i_p_m -inst_prfw :: inst_prfw_i_p_m -emit_prfw :: emit_prfw_i_p_m -inst_prfd :: inst_prfd_i_p_m -emit_prfd :: emit_prfd_i_p_m -inst_ldnt1b :: inst_ldnt1b_z_p_m -emit_ldnt1b :: emit_ldnt1b_z_p_m -inst_ldnt1h :: inst_ldnt1h_z_p_m -emit_ldnt1h :: emit_ldnt1h_z_p_m -inst_ldnt1w :: inst_ldnt1w_z_p_m -emit_ldnt1w :: emit_ldnt1w_z_p_m -inst_ldnt1d :: inst_ldnt1d_z_p_m -emit_ldnt1d :: emit_ldnt1d_z_p_m -inst_stnt1b :: inst_stnt1b_z_p_m -emit_stnt1b :: emit_stnt1b_z_p_m -inst_stnt1h :: inst_stnt1h_z_p_m -emit_stnt1h :: emit_stnt1h_z_p_m -inst_stnt1w :: inst_stnt1w_z_p_m -emit_stnt1w :: emit_stnt1w_z_p_m -inst_stnt1d :: inst_stnt1d_z_p_m -emit_stnt1d :: emit_stnt1d_z_p_m -inst_splice :: inst_splice_z_p_z_z -emit_splice :: emit_splice_z_p_z_z -inst_index :: proc{ inst_index_z_i_i, inst_index_z_i_r, inst_index_z_r_i, inst_index_z_r_r } -emit_index :: proc{ emit_index_z_i_i, emit_index_z_i_r, emit_index_z_r_i, emit_index_z_r_r } -inst_bsl1n :: inst_bsl1n_z_z_z_z -emit_bsl1n :: emit_bsl1n_z_z_z_z -inst_bsl2n :: inst_bsl2n_z_z_z_z -emit_bsl2n :: emit_bsl2n_z_z_z_z -inst_nbsl :: inst_nbsl_z_z_z_z -emit_nbsl :: emit_nbsl_z_z_z_z -inst_pmul :: inst_pmul_z_z_z -emit_pmul :: emit_pmul_z_z_z -inst_pmullb :: inst_pmullb_z_z_z -emit_pmullb :: emit_pmullb_z_z_z -inst_pmullt :: inst_pmullt_z_z_z -emit_pmullt :: emit_pmullt_z_z_z -inst_bfcvtnt :: inst_bfcvtnt_z_p_z -emit_bfcvtnt :: emit_bfcvtnt_z_p_z -inst_ldraa :: inst_ldraa_r_m -emit_ldraa :: emit_ldraa_r_m -inst_ldrab :: inst_ldrab_r_m -emit_ldrab :: emit_ldrab_r_m -inst_tstart :: inst_tstart_r -emit_tstart :: emit_tstart_r -inst_tcommit :: inst_tcommit_none -emit_tcommit :: emit_tcommit_none -inst_tcancel :: inst_tcancel_i -emit_tcancel :: emit_tcancel_i -inst_ttest :: inst_ttest_r -emit_ttest :: emit_ttest_r -inst_wfet :: inst_wfet_r -emit_wfet :: emit_wfet_r -inst_wfit :: inst_wfit_r -emit_wfit :: emit_wfit_r -inst_bc_eq :: inst_bc_eq_l -emit_bc_eq :: emit_bc_eq_l -inst_bc_ne :: inst_bc_ne_l -emit_bc_ne :: emit_bc_ne_l -inst_bc_cs :: inst_bc_cs_l -emit_bc_cs :: emit_bc_cs_l -inst_bc_cc :: inst_bc_cc_l -emit_bc_cc :: emit_bc_cc_l -inst_bc_mi :: inst_bc_mi_l -emit_bc_mi :: emit_bc_mi_l -inst_bc_pl :: inst_bc_pl_l -emit_bc_pl :: emit_bc_pl_l -inst_bc_vs :: inst_bc_vs_l -emit_bc_vs :: emit_bc_vs_l -inst_bc_vc :: inst_bc_vc_l -emit_bc_vc :: emit_bc_vc_l -inst_bc_hi :: inst_bc_hi_l -emit_bc_hi :: emit_bc_hi_l -inst_bc_ls :: inst_bc_ls_l -emit_bc_ls :: emit_bc_ls_l -inst_bc_ge :: inst_bc_ge_l -emit_bc_ge :: emit_bc_ge_l -inst_bc_lt :: inst_bc_lt_l -emit_bc_lt :: emit_bc_lt_l -inst_bc_gt :: inst_bc_gt_l -emit_bc_gt :: emit_bc_gt_l -inst_bc_le :: inst_bc_le_l -emit_bc_le :: emit_bc_le_l -inst_bc_al :: inst_bc_al_l -emit_bc_al :: emit_bc_al_l -inst_bc_nv :: inst_bc_nv_l -emit_bc_nv :: emit_bc_nv_l -inst_uxtb :: inst_uxtb_r_r -emit_uxtb :: emit_uxtb_r_r -inst_uxth :: inst_uxth_r_r -emit_uxth :: emit_uxth_r_r -inst_uxtw :: inst_uxtw_r_r -emit_uxtw :: emit_uxtw_r_r -inst_sxtb :: inst_sxtb_r_r -emit_sxtb :: emit_sxtb_r_r -inst_sxth :: inst_sxth_r_r -emit_sxth :: emit_sxth_r_r -inst_sxtw :: inst_sxtw_r_r -emit_sxtw :: emit_sxtw_r_r -inst_adc :: inst_adc_r_r_r -emit_adc :: emit_adc_r_r_r -inst_adcs :: inst_adcs_r_r_r -emit_adcs :: emit_adcs_r_r_r -inst_sbc :: inst_sbc_r_r_r -emit_sbc :: emit_sbc_r_r_r -inst_sbcs :: inst_sbcs_r_r_r -emit_sbcs :: emit_sbcs_r_r_r -inst_ngc :: inst_ngc_r_r -emit_ngc :: emit_ngc_r_r -inst_ngcs :: inst_ngcs_r_r -emit_ngcs :: emit_ngcs_r_r -inst_ldapur :: inst_ldapur_r_m -emit_ldapur :: emit_ldapur_r_m -inst_stlur :: inst_stlur_r_m -emit_stlur :: emit_stlur_r_m -inst_ldapurb :: inst_ldapurb_r_m -emit_ldapurb :: emit_ldapurb_r_m -inst_stlurb :: inst_stlurb_r_m -emit_stlurb :: emit_stlurb_r_m -inst_ldapurh :: inst_ldapurh_r_m -emit_ldapurh :: emit_ldapurh_r_m -inst_stlurh :: inst_stlurh_r_m -emit_stlurh :: emit_stlurh_r_m -inst_ldapursb :: inst_ldapursb_r_m -emit_ldapursb :: emit_ldapursb_r_m -inst_ldapursh :: inst_ldapursh_r_m -emit_ldapursh :: emit_ldapursh_r_m -inst_ldapursw :: inst_ldapursw_r_m -emit_ldapursw :: emit_ldapursw_r_m -inst_bfadd :: proc{ inst_bfadd_z_p_z_z, inst_bfadd_z_z_z } -emit_bfadd :: proc{ emit_bfadd_z_p_z_z, emit_bfadd_z_z_z } -inst_bfsub :: proc{ inst_bfsub_z_p_z_z, inst_bfsub_z_z_z } -emit_bfsub :: proc{ emit_bfsub_z_p_z_z, emit_bfsub_z_z_z } -inst_bfmul :: proc{ inst_bfmul_z_p_z_z, inst_bfmul_z_z_z } -emit_bfmul :: proc{ emit_bfmul_z_p_z_z, emit_bfmul_z_z_z } -inst_bfmla :: inst_bfmla_z_p_z_z -emit_bfmla :: emit_bfmla_z_p_z_z -inst_bfmls :: inst_bfmls_z_p_z_z -emit_bfmls :: emit_bfmls_z_p_z_z -inst_sb :: inst_sb_none -emit_sb :: emit_sb_none -inst_csdb :: inst_csdb_none -emit_csdb :: emit_csdb_none -inst_dgh :: inst_dgh_none -emit_dgh :: emit_dgh_none -inst_psb_csync :: inst_psb_csync_none -emit_psb_csync :: emit_psb_csync_none -inst_tsb_csync :: inst_tsb_csync_none -emit_tsb_csync :: emit_tsb_csync_none -inst_bti_j :: inst_bti_j_none -emit_bti_j :: emit_bti_j_none -inst_bti_c :: inst_bti_c_none -emit_bti_c :: emit_bti_c_none -inst_bti_jc :: inst_bti_jc_none -emit_bti_jc :: emit_bti_jc_none -inst_bfclamp :: inst_bfclamp_z_z_z -emit_bfclamp :: emit_bfclamp_z_z_z -inst_bfmaxnm :: inst_bfmaxnm_z_p_z_z -emit_bfmaxnm :: emit_bfmaxnm_z_p_z_z -inst_bfminnm :: inst_bfminnm_z_p_z_z -emit_bfminnm :: emit_bfminnm_z_p_z_z -inst_luti2 :: inst_luti2_z_z_z_i -emit_luti2 :: emit_luti2_z_z_z_i -inst_luti4 :: inst_luti4_z_z_z_i -emit_luti4 :: emit_luti4_z_z_z_i -inst_zip :: proc{ inst_zip_z_z_z, inst_zip_z_z } -emit_zip :: proc{ emit_zip_z_z_z, emit_zip_z_z } -inst_uzp :: proc{ inst_uzp_z_z_z, inst_uzp_z_z } -emit_uzp :: proc{ emit_uzp_z_z_z, emit_uzp_z_z } -inst_tlbi_rpalos :: inst_tlbi_rpalos_r -emit_tlbi_rpalos :: emit_tlbi_rpalos_r -inst_tlbi_rpaos :: inst_tlbi_rpaos_r -emit_tlbi_rpaos :: emit_tlbi_rpaos_r -inst_at_s1e1a :: inst_at_s1e1a_r -emit_at_s1e1a :: emit_at_s1e1a_r -inst_dc_cipapa :: inst_dc_cipapa_r -emit_dc_cipapa :: emit_dc_cipapa_r -inst_dc_cigdpapa :: inst_dc_cigdpapa_r -emit_dc_cigdpapa :: emit_dc_cigdpapa_r -inst_tlbi_paall :: inst_tlbi_paall_none -emit_tlbi_paall :: emit_tlbi_paall_none -inst_tlbi_paallos :: inst_tlbi_paallos_none -emit_tlbi_paallos :: emit_tlbi_paallos_none -inst_amx_ldx :: inst_amx_ldx_r -emit_amx_ldx :: emit_amx_ldx_r -inst_amx_ldy :: inst_amx_ldy_r -emit_amx_ldy :: emit_amx_ldy_r -inst_amx_stx :: inst_amx_stx_r -emit_amx_stx :: emit_amx_stx_r -inst_amx_sty :: inst_amx_sty_r -emit_amx_sty :: emit_amx_sty_r -inst_amx_ldz :: inst_amx_ldz_r -emit_amx_ldz :: emit_amx_ldz_r -inst_amx_stz :: inst_amx_stz_r -emit_amx_stz :: emit_amx_stz_r -inst_amx_ldzi :: inst_amx_ldzi_r -emit_amx_ldzi :: emit_amx_ldzi_r -inst_amx_stzi :: inst_amx_stzi_r -emit_amx_stzi :: emit_amx_stzi_r -inst_amx_extrx :: inst_amx_extrx_r -emit_amx_extrx :: emit_amx_extrx_r -inst_amx_extry :: inst_amx_extry_r -emit_amx_extry :: emit_amx_extry_r -inst_amx_fma64 :: inst_amx_fma64_r -emit_amx_fma64 :: emit_amx_fma64_r -inst_amx_fms64 :: inst_amx_fms64_r -emit_amx_fms64 :: emit_amx_fms64_r -inst_amx_fma32 :: inst_amx_fma32_r -emit_amx_fma32 :: emit_amx_fma32_r -inst_amx_fms32 :: inst_amx_fms32_r -emit_amx_fms32 :: emit_amx_fms32_r -inst_amx_mac16 :: inst_amx_mac16_r -emit_amx_mac16 :: emit_amx_mac16_r -inst_amx_fma16 :: inst_amx_fma16_r -emit_amx_fma16 :: emit_amx_fma16_r -inst_amx_fms16 :: inst_amx_fms16_r -emit_amx_fms16 :: emit_amx_fms16_r -inst_amx_set :: inst_amx_set_none -emit_amx_set :: emit_amx_set_none -inst_amx_clr :: inst_amx_clr_none -emit_amx_clr :: emit_amx_clr_none -inst_amx_vecint :: inst_amx_vecint_r -emit_amx_vecint :: emit_amx_vecint_r -inst_amx_vecfp :: inst_amx_vecfp_r -emit_amx_vecfp :: emit_amx_vecfp_r -inst_amx_matint :: inst_amx_matint_r -emit_amx_matint :: emit_amx_matint_r -inst_amx_matfp :: inst_amx_matfp_r -emit_amx_matfp :: emit_amx_matfp_r -inst_amx_genlut :: inst_amx_genlut_r -emit_amx_genlut :: emit_amx_genlut_r -inst_cpyp :: inst_cpyp_r_r_r -emit_cpyp :: emit_cpyp_r_r_r -inst_cpym :: inst_cpym_r_r_r -emit_cpym :: emit_cpym_r_r_r -inst_cpye :: inst_cpye_r_r_r -emit_cpye :: emit_cpye_r_r_r -inst_cpyfp :: inst_cpyfp_r_r_r -emit_cpyfp :: emit_cpyfp_r_r_r -inst_cpyfm :: inst_cpyfm_r_r_r -emit_cpyfm :: emit_cpyfm_r_r_r -inst_cpyfe :: inst_cpyfe_r_r_r -emit_cpyfe :: emit_cpyfe_r_r_r -inst_setp :: inst_setp_r_r_r -emit_setp :: emit_setp_r_r_r -inst_setm :: inst_setm_r_r_r -emit_setm :: emit_setm_r_r_r -inst_sete :: inst_sete_r_r_r -emit_sete :: emit_sete_r_r_r -inst_dc_ivac :: inst_dc_ivac_r -emit_dc_ivac :: emit_dc_ivac_r -inst_dc_isw :: inst_dc_isw_r -emit_dc_isw :: emit_dc_isw_r -inst_dc_csw :: inst_dc_csw_r -emit_dc_csw :: emit_dc_csw_r -inst_dc_cisw :: inst_dc_cisw_r -emit_dc_cisw :: emit_dc_cisw_r -inst_dc_zva :: inst_dc_zva_r -emit_dc_zva :: emit_dc_zva_r -inst_dc_cvac :: inst_dc_cvac_r -emit_dc_cvac :: emit_dc_cvac_r -inst_dc_cvau :: inst_dc_cvau_r -emit_dc_cvau :: emit_dc_cvau_r -inst_dc_civac :: inst_dc_civac_r -emit_dc_civac :: emit_dc_civac_r -inst_ic_ialluis :: inst_ic_ialluis_none -emit_ic_ialluis :: emit_ic_ialluis_none -inst_ic_iallu :: inst_ic_iallu_none -emit_ic_iallu :: emit_ic_iallu_none -inst_ic_ivau :: inst_ic_ivau_r -emit_ic_ivau :: emit_ic_ivau_r -inst_at_s1e1r :: inst_at_s1e1r_r -emit_at_s1e1r :: emit_at_s1e1r_r -inst_at_s1e1w :: inst_at_s1e1w_r -emit_at_s1e1w :: emit_at_s1e1w_r -inst_at_s1e0r :: inst_at_s1e0r_r -emit_at_s1e0r :: emit_at_s1e0r_r -inst_at_s1e0w :: inst_at_s1e0w_r -emit_at_s1e0w :: emit_at_s1e0w_r -inst_at_s1e2r :: inst_at_s1e2r_r -emit_at_s1e2r :: emit_at_s1e2r_r -inst_at_s1e2w :: inst_at_s1e2w_r -emit_at_s1e2w :: emit_at_s1e2w_r -inst_at_s1e3r :: inst_at_s1e3r_r -emit_at_s1e3r :: emit_at_s1e3r_r -inst_at_s1e3w :: inst_at_s1e3w_r -emit_at_s1e3w :: emit_at_s1e3w_r -inst_at_s12e1r :: inst_at_s12e1r_r -emit_at_s12e1r :: emit_at_s12e1r_r -inst_at_s12e1w :: inst_at_s12e1w_r -emit_at_s12e1w :: emit_at_s12e1w_r -inst_at_s12e0r :: inst_at_s12e0r_r -emit_at_s12e0r :: emit_at_s12e0r_r -inst_at_s12e0w :: inst_at_s12e0w_r -emit_at_s12e0w :: emit_at_s12e0w_r -inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none -emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none -inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none -emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none -inst_tlbi_vae1 :: inst_tlbi_vae1_r -emit_tlbi_vae1 :: emit_tlbi_vae1_r -inst_tlbi_vae1is :: inst_tlbi_vae1is_r -emit_tlbi_vae1is :: emit_tlbi_vae1is_r -inst_tlbi_aside1 :: inst_tlbi_aside1_r -emit_tlbi_aside1 :: emit_tlbi_aside1_r -inst_tlbi_aside1is :: inst_tlbi_aside1is_r -emit_tlbi_aside1is :: emit_tlbi_aside1is_r -inst_tlbi_vaae1 :: inst_tlbi_vaae1_r -emit_tlbi_vaae1 :: emit_tlbi_vaae1_r -inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r -emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r -inst_tlbi_vale1 :: inst_tlbi_vale1_r -emit_tlbi_vale1 :: emit_tlbi_vale1_r -inst_tlbi_vale1is :: inst_tlbi_vale1is_r -emit_tlbi_vale1is :: emit_tlbi_vale1is_r -inst_tlbi_vaale1 :: inst_tlbi_vaale1_r -emit_tlbi_vaale1 :: emit_tlbi_vaale1_r -inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r -emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r -inst_tlbi_alle1 :: inst_tlbi_alle1_none -emit_tlbi_alle1 :: emit_tlbi_alle1_none -inst_tlbi_alle1is :: inst_tlbi_alle1is_none -emit_tlbi_alle1is :: emit_tlbi_alle1is_none -inst_tlbi_alle2 :: inst_tlbi_alle2_none -emit_tlbi_alle2 :: emit_tlbi_alle2_none -inst_tlbi_alle2is :: inst_tlbi_alle2is_none -emit_tlbi_alle2is :: emit_tlbi_alle2is_none -inst_tlbi_alle3 :: inst_tlbi_alle3_none -emit_tlbi_alle3 :: emit_tlbi_alle3_none -inst_tlbi_alle3is :: inst_tlbi_alle3is_none -emit_tlbi_alle3is :: emit_tlbi_alle3is_none -inst_prfm :: proc{ inst_prfm_i_m, inst_prfm_i_l } -emit_prfm :: proc{ emit_prfm_i_m, emit_prfm_i_l } -inst_prfum :: inst_prfum_i_m -emit_prfum :: emit_prfum_i_m -inst_negs :: inst_negs_r_sh -emit_negs :: emit_negs_r_sh -inst_cmp :: proc{ inst_cmp_r_sh, inst_cmp_r_ex, inst_cmp_r_i } -emit_cmp :: proc{ emit_cmp_r_sh, emit_cmp_r_ex, emit_cmp_r_i } -inst_cmn :: proc{ inst_cmn_r_sh, inst_cmn_r_ex, inst_cmn_r_i } -emit_cmn :: proc{ emit_cmn_r_sh, emit_cmn_r_ex, emit_cmn_r_i } +inst_add :: proc{ inst_add_r_r_i, inst_add_r_r_sh, inst_add_r_r_ex, inst_add_v16b_v16b_v16b, inst_add_z_z_z, inst_add_z_p_z_z } +emit_add :: proc{ emit_add_r_r_i, emit_add_r_r_sh, emit_add_r_r_ex, emit_add_v16b_v16b_v16b, emit_add_z_z_z, emit_add_z_p_z_z } +inst_adds :: proc{ inst_adds_r_r_i, inst_adds_r_r_sh, inst_adds_r_r_ex } +emit_adds :: proc{ emit_adds_r_r_i, emit_adds_r_r_sh, emit_adds_r_r_ex } +inst_sub :: proc{ inst_sub_r_r_i, inst_sub_r_r_sh, inst_sub_r_r_ex, inst_sub_v16b_v16b_v16b, inst_sub_z_z_z, inst_sub_z_p_z_z } +emit_sub :: proc{ emit_sub_r_r_i, emit_sub_r_r_sh, emit_sub_r_r_ex, emit_sub_v16b_v16b_v16b, emit_sub_z_z_z, emit_sub_z_p_z_z } +inst_subs :: proc{ inst_subs_r_r_i, inst_subs_r_r_sh, inst_subs_r_r_ex } +emit_subs :: proc{ emit_subs_r_r_i, emit_subs_r_r_sh, emit_subs_r_r_ex } +inst_movz :: inst_movz_r_i_i +emit_movz :: emit_movz_r_i_i +inst_movn :: inst_movn_r_i_i +emit_movn :: emit_movn_r_i_i +inst_movk :: inst_movk_r_i_i +emit_movk :: emit_movk_r_i_i +inst_adr :: inst_adr_r_l +emit_adr :: emit_adr_r_l +inst_adrp :: inst_adrp_r_l +emit_adrp :: emit_adrp_r_l +inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_v16b_v16b_v16b, inst_and_z_p_z_z } +emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_v16b_v16b_v16b, emit_and_z_p_z_z } +inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_p_p_p_p } +emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_p_p_p_p } +inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_v16b_v16b_v16b, inst_orr_z_p_z_z } +emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_v16b_v16b_v16b, emit_orr_z_p_z_z } +inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_v16b_v16b_v16b, inst_eor_z_p_z_z } +emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_v16b_v16b_v16b, emit_eor_z_p_z_z } +inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_v16b_v16b_v16b, inst_bic_z_p_z_z } +emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_v16b_v16b_v16b, emit_bic_z_p_z_z } +inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_p_p_p_p } +emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_p_p_p_p } +inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_p_p_p_p } +emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_p_p_p_p } +inst_eon :: inst_eon_r_r_sh +emit_eon :: emit_eon_r_r_sh +inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_z_p_z_z, inst_lsl_r_r_i } +emit_lsl :: proc{ emit_lsl_r_r_r, emit_lsl_z_p_z_z, emit_lsl_r_r_i } +inst_lsr :: proc{ inst_lsr_r_r_r, inst_lsr_z_p_z_z, inst_lsr_r_r_i } +emit_lsr :: proc{ emit_lsr_r_r_r, emit_lsr_z_p_z_z, emit_lsr_r_r_i } +inst_asr :: proc{ inst_asr_r_r_r, inst_asr_z_p_z_z, inst_asr_r_r_i } +emit_asr :: proc{ emit_asr_r_r_r, emit_asr_z_p_z_z, emit_asr_r_r_i } +inst_ror :: proc{ inst_ror_r_r_r, inst_ror_r_r_i } +emit_ror :: proc{ emit_ror_r_r_r, emit_ror_r_r_i } +inst_udiv :: proc{ inst_udiv_r_r_r, inst_udiv_z_p_z_z } +emit_udiv :: proc{ emit_udiv_r_r_r, emit_udiv_z_p_z_z } +inst_sdiv :: proc{ inst_sdiv_r_r_r, inst_sdiv_z_p_z_z } +emit_sdiv :: proc{ emit_sdiv_r_r_r, emit_sdiv_z_p_z_z } +inst_madd :: inst_madd_r_r_r_r +emit_madd :: emit_madd_r_r_r_r +inst_msub :: inst_msub_r_r_r_r +emit_msub :: emit_msub_r_r_r_r +inst_smaddl :: inst_smaddl_r_r_r_r +emit_smaddl :: emit_smaddl_r_r_r_r +inst_smsubl :: inst_smsubl_r_r_r_r +emit_smsubl :: emit_smsubl_r_r_r_r +inst_umaddl :: inst_umaddl_r_r_r_r +emit_umaddl :: emit_umaddl_r_r_r_r +inst_umsubl :: inst_umsubl_r_r_r_r +emit_umsubl :: emit_umsubl_r_r_r_r +inst_smulh :: proc{ inst_smulh_r_r_r, inst_smulh_z_p_z_z } +emit_smulh :: proc{ emit_smulh_r_r_r, emit_smulh_z_p_z_z } +inst_umulh :: proc{ inst_umulh_r_r_r, inst_umulh_z_p_z_z } +emit_umulh :: proc{ emit_umulh_r_r_r, emit_umulh_z_p_z_z } +inst_clz :: proc{ inst_clz_r_r, inst_clz_z_p_z } +emit_clz :: proc{ emit_clz_r_r, emit_clz_z_p_z } +inst_cls :: proc{ inst_cls_r_r, inst_cls_z_p_z } +emit_cls :: proc{ emit_cls_r_r, emit_cls_z_p_z } +inst_rbit :: inst_rbit_r_r +emit_rbit :: emit_rbit_r_r +inst_rev :: proc{ inst_rev_r_r, inst_rev_z_z } +emit_rev :: proc{ emit_rev_r_r, emit_rev_z_z } +inst_rev16 :: inst_rev16_r_r +emit_rev16 :: emit_rev16_r_r +inst_rev32 :: inst_rev32_r_r +emit_rev32 :: emit_rev32_r_r +inst_csel :: inst_csel_r_r_r_c +emit_csel :: emit_csel_r_r_r_c +inst_csinc :: inst_csinc_r_r_r_c +emit_csinc :: emit_csinc_r_r_r_c +inst_csinv :: inst_csinv_r_r_r_c +emit_csinv :: emit_csinv_r_r_r_c +inst_csneg :: inst_csneg_r_r_r_c +emit_csneg :: emit_csneg_r_r_r_c +inst_ccmp :: proc{ inst_ccmp_r_r_i_c, inst_ccmp_r_i_i_c } +emit_ccmp :: proc{ emit_ccmp_r_r_i_c, emit_ccmp_r_i_i_c } +inst_ccmn :: proc{ inst_ccmn_r_r_i_c, inst_ccmn_r_i_i_c } +emit_ccmn :: proc{ emit_ccmn_r_r_i_c, emit_ccmn_r_i_i_c } +inst_cset :: inst_cset_r_c +emit_cset :: emit_cset_r_c +inst_csetm :: inst_csetm_r_c +emit_csetm :: emit_csetm_r_c +inst_cinc :: inst_cinc_r_r_c +emit_cinc :: emit_cinc_r_r_c +inst_cinv :: inst_cinv_r_r_c +emit_cinv :: emit_cinv_r_r_c +inst_cneg :: inst_cneg_r_r_c +emit_cneg :: emit_cneg_r_r_c +inst_extr :: inst_extr_r_r_r_i +emit_extr :: emit_extr_r_r_r_i +inst_b :: inst_b_l +emit_b :: emit_b_l +inst_bl :: inst_bl_l +emit_bl :: emit_bl_l +inst_br :: inst_br_r +emit_br :: emit_br_r +inst_blr :: inst_blr_r +emit_blr :: emit_blr_r +inst_ret :: proc{ inst_ret_r, inst_ret_none } +emit_ret :: proc{ emit_ret_r, emit_ret_none } +inst_b_eq :: inst_b_eq_l +emit_b_eq :: emit_b_eq_l +inst_b_ne :: inst_b_ne_l +emit_b_ne :: emit_b_ne_l +inst_b_cs :: inst_b_cs_l +emit_b_cs :: emit_b_cs_l +inst_b_cc :: inst_b_cc_l +emit_b_cc :: emit_b_cc_l +inst_b_mi :: inst_b_mi_l +emit_b_mi :: emit_b_mi_l +inst_b_pl :: inst_b_pl_l +emit_b_pl :: emit_b_pl_l +inst_b_vs :: inst_b_vs_l +emit_b_vs :: emit_b_vs_l +inst_b_vc :: inst_b_vc_l +emit_b_vc :: emit_b_vc_l +inst_b_hi :: inst_b_hi_l +emit_b_hi :: emit_b_hi_l +inst_b_ls :: inst_b_ls_l +emit_b_ls :: emit_b_ls_l +inst_b_ge :: inst_b_ge_l +emit_b_ge :: emit_b_ge_l +inst_b_lt :: inst_b_lt_l +emit_b_lt :: emit_b_lt_l +inst_b_gt :: inst_b_gt_l +emit_b_gt :: emit_b_gt_l +inst_b_le :: inst_b_le_l +emit_b_le :: emit_b_le_l +inst_b_al :: inst_b_al_l +emit_b_al :: emit_b_al_l +inst_b_nv :: inst_b_nv_l +emit_b_nv :: emit_b_nv_l +inst_cbz :: inst_cbz_r_l +emit_cbz :: emit_cbz_r_l +inst_cbnz :: inst_cbnz_r_l +emit_cbnz :: emit_cbnz_r_l +inst_tbz :: inst_tbz_r_i_l +emit_tbz :: emit_tbz_r_i_l +inst_tbnz :: inst_tbnz_r_i_l +emit_tbnz :: emit_tbnz_r_i_l +inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_z_m, inst_ldr_i_m } +emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_z_m, emit_ldr_i_m } +inst_str :: proc{ inst_str_r_m, inst_str_z_m, inst_str_i_m } +emit_str :: proc{ emit_str_r_m, emit_str_z_m, emit_str_i_m } +inst_ldrb :: inst_ldrb_r_m +emit_ldrb :: emit_ldrb_r_m +inst_strb :: inst_strb_r_m +emit_strb :: emit_strb_r_m +inst_ldrsb :: inst_ldrsb_r_m +emit_ldrsb :: emit_ldrsb_r_m +inst_ldrh :: inst_ldrh_r_m +emit_ldrh :: emit_ldrh_r_m +inst_strh :: inst_strh_r_m +emit_strh :: emit_strh_r_m +inst_ldrsh :: inst_ldrsh_r_m +emit_ldrsh :: emit_ldrsh_r_m +inst_ldrsw :: inst_ldrsw_r_m +emit_ldrsw :: emit_ldrsw_r_m +inst_ldp :: inst_ldp_r_r_m +emit_ldp :: emit_ldp_r_r_m +inst_stp :: inst_stp_r_r_m +emit_stp :: emit_stp_r_r_m +inst_ldpsw :: inst_ldpsw_r_r_m +emit_ldpsw :: emit_ldpsw_r_r_m +inst_ldar :: inst_ldar_r_m +emit_ldar :: emit_ldar_r_m +inst_stlr :: inst_stlr_r_m +emit_stlr :: emit_stlr_r_m +inst_ldarb :: inst_ldarb_r_m +emit_ldarb :: emit_ldarb_r_m +inst_stlrb :: inst_stlrb_r_m +emit_stlrb :: emit_stlrb_r_m +inst_ldarh :: inst_ldarh_r_m +emit_ldarh :: emit_ldarh_r_m +inst_stlrh :: inst_stlrh_r_m +emit_stlrh :: emit_stlrh_r_m +inst_ldxr :: inst_ldxr_r_m +emit_ldxr :: emit_ldxr_r_m +inst_stxr :: inst_stxr_r_r_m +emit_stxr :: emit_stxr_r_r_m +inst_ldaxr :: inst_ldaxr_r_m +emit_ldaxr :: emit_ldaxr_r_m +inst_stlxr :: inst_stlxr_r_r_m +emit_stlxr :: emit_stlxr_r_r_m +inst_nop :: inst_nop_none +emit_nop :: emit_nop_none +inst_yield :: inst_yield_none +emit_yield :: emit_yield_none +inst_wfe :: inst_wfe_none +emit_wfe :: emit_wfe_none +inst_wfi :: inst_wfi_none +emit_wfi :: emit_wfi_none +inst_sev :: inst_sev_none +emit_sev :: emit_sev_none +inst_sevl :: inst_sevl_none +emit_sevl :: emit_sevl_none +inst_hint :: inst_hint_i +emit_hint :: emit_hint_i +inst_mrs :: inst_mrs_r_s +emit_mrs :: emit_mrs_r_s +inst_msr :: proc{ inst_msr_i_i, inst_msr_s_r } +emit_msr :: proc{ emit_msr_i_i, emit_msr_s_r } +inst_isb :: inst_isb_i +emit_isb :: emit_isb_i +inst_dsb :: inst_dsb_i +emit_dsb :: emit_dsb_i +inst_dmb :: inst_dmb_i +emit_dmb :: emit_dmb_i +inst_svc :: inst_svc_i +emit_svc :: emit_svc_i +inst_hvc :: inst_hvc_i +emit_hvc :: emit_hvc_i +inst_smc :: inst_smc_i +emit_smc :: emit_smc_i +inst_brk :: inst_brk_i +emit_brk :: emit_brk_i +inst_hlt :: inst_hlt_i +emit_hlt :: emit_hlt_i +inst_eret :: inst_eret_none +emit_eret :: emit_eret_none +inst_fmov :: proc{ inst_fmov_r_r, inst_fmov_r_i } +emit_fmov :: proc{ emit_fmov_r_r, emit_fmov_r_i } +inst_fabs :: proc{ inst_fabs_r_r, inst_fabs_z_p_z } +emit_fabs :: proc{ emit_fabs_r_r, emit_fabs_z_p_z } +inst_fneg :: proc{ inst_fneg_r_r, inst_fneg_z_p_z } +emit_fneg :: proc{ emit_fneg_r_r, emit_fneg_z_p_z } +inst_fsqrt :: proc{ inst_fsqrt_r_r, inst_fsqrt_z_p_z } +emit_fsqrt :: proc{ emit_fsqrt_r_r, emit_fsqrt_z_p_z } +inst_fadd :: proc{ inst_fadd_r_r_r, inst_fadd_z_z_z, inst_fadd_z_p_z_z } +emit_fadd :: proc{ emit_fadd_r_r_r, emit_fadd_z_z_z, emit_fadd_z_p_z_z } +inst_fsub :: proc{ inst_fsub_r_r_r, inst_fsub_z_z_z, inst_fsub_z_p_z_z } +emit_fsub :: proc{ emit_fsub_r_r_r, emit_fsub_z_z_z, emit_fsub_z_p_z_z } +inst_fmul :: proc{ inst_fmul_r_r_r, inst_fmul_z_z_z, inst_fmul_z_p_z_z } +emit_fmul :: proc{ emit_fmul_r_r_r, emit_fmul_z_z_z, emit_fmul_z_p_z_z } +inst_fdiv :: proc{ inst_fdiv_r_r_r, inst_fdiv_z_p_z_z } +emit_fdiv :: proc{ emit_fdiv_r_r_r, emit_fdiv_z_p_z_z } +inst_fnmul :: inst_fnmul_r_r_r +emit_fnmul :: emit_fnmul_r_r_r +inst_fmadd :: inst_fmadd_r_r_r_r +emit_fmadd :: emit_fmadd_r_r_r_r +inst_fmsub :: inst_fmsub_r_r_r_r +emit_fmsub :: emit_fmsub_r_r_r_r +inst_fnmadd :: inst_fnmadd_r_r_r_r +emit_fnmadd :: emit_fnmadd_r_r_r_r +inst_fnmsub :: inst_fnmsub_r_r_r_r +emit_fnmsub :: emit_fnmsub_r_r_r_r +inst_fcmp :: inst_fcmp_r_r +emit_fcmp :: emit_fcmp_r_r +inst_fcmpe :: inst_fcmpe_r_r +emit_fcmpe :: emit_fcmpe_r_r +inst_fcsel :: inst_fcsel_r_r_r_c +emit_fcsel :: emit_fcsel_r_r_r_c +inst_fmax :: proc{ inst_fmax_r_r_r, inst_fmax_z_p_z_z } +emit_fmax :: proc{ emit_fmax_r_r_r, emit_fmax_z_p_z_z } +inst_fmin :: proc{ inst_fmin_r_r_r, inst_fmin_z_p_z_z } +emit_fmin :: proc{ emit_fmin_r_r_r, emit_fmin_z_p_z_z } +inst_fmaxnm :: proc{ inst_fmaxnm_r_r_r, inst_fmaxnm_z_p_z_z } +emit_fmaxnm :: proc{ emit_fmaxnm_r_r_r, emit_fmaxnm_z_p_z_z } +inst_fminnm :: proc{ inst_fminnm_r_r_r, inst_fminnm_z_p_z_z } +emit_fminnm :: proc{ emit_fminnm_r_r_r, emit_fminnm_z_p_z_z } +inst_fcvt :: inst_fcvt_r_r +emit_fcvt :: emit_fcvt_r_r +inst_scvtf :: inst_scvtf_r_r +emit_scvtf :: emit_scvtf_r_r +inst_ucvtf :: inst_ucvtf_r_r +emit_ucvtf :: emit_ucvtf_r_r +inst_fcvtzs :: inst_fcvtzs_r_r +emit_fcvtzs :: emit_fcvtzs_r_r +inst_fcvtzu :: inst_fcvtzu_r_r +emit_fcvtzu :: emit_fcvtzu_r_r +inst_fcvtas :: inst_fcvtas_r_r +emit_fcvtas :: emit_fcvtas_r_r +inst_fcvtau :: inst_fcvtau_r_r +emit_fcvtau :: emit_fcvtau_r_r +inst_fcvtns :: inst_fcvtns_r_r +emit_fcvtns :: emit_fcvtns_r_r +inst_fcvtnu :: inst_fcvtnu_r_r +emit_fcvtnu :: emit_fcvtnu_r_r +inst_fcvtps :: inst_fcvtps_r_r +emit_fcvtps :: emit_fcvtps_r_r +inst_fcvtpu :: inst_fcvtpu_r_r +emit_fcvtpu :: emit_fcvtpu_r_r +inst_fcvtms :: inst_fcvtms_r_r +emit_fcvtms :: emit_fcvtms_r_r +inst_fcvtmu :: inst_fcvtmu_r_r +emit_fcvtmu :: emit_fcvtmu_r_r +inst_frinta :: proc{ inst_frinta_r_r, inst_frinta_z_p_z } +emit_frinta :: proc{ emit_frinta_r_r, emit_frinta_z_p_z } +inst_frinti :: proc{ inst_frinti_r_r, inst_frinti_z_p_z } +emit_frinti :: proc{ emit_frinti_r_r, emit_frinti_z_p_z } +inst_frintm :: proc{ inst_frintm_r_r, inst_frintm_z_p_z } +emit_frintm :: proc{ emit_frintm_r_r, emit_frintm_z_p_z } +inst_frintn :: proc{ inst_frintn_r_r, inst_frintn_z_p_z } +emit_frintn :: proc{ emit_frintn_r_r, emit_frintn_z_p_z } +inst_frintp :: proc{ inst_frintp_r_r, inst_frintp_z_p_z } +emit_frintp :: proc{ emit_frintp_r_r, emit_frintp_z_p_z } +inst_frintx :: proc{ inst_frintx_r_r, inst_frintx_z_p_z } +emit_frintx :: proc{ emit_frintx_r_r, emit_frintx_z_p_z } +inst_frintz :: proc{ inst_frintz_r_r, inst_frintz_z_p_z } +emit_frintz :: proc{ emit_frintz_r_r, emit_frintz_z_p_z } +inst_tst :: proc{ inst_tst_r_i, inst_tst_r_sh } +emit_tst :: proc{ emit_tst_r_i, emit_tst_r_sh } +inst_ldur :: inst_ldur_r_m +emit_ldur :: emit_ldur_r_m +inst_stur :: inst_stur_r_m +emit_stur :: emit_stur_r_m +inst_ldurb :: inst_ldurb_r_m +emit_ldurb :: emit_ldurb_r_m +inst_sturb :: inst_sturb_r_m +emit_sturb :: emit_sturb_r_m +inst_ldursb :: inst_ldursb_r_m +emit_ldursb :: emit_ldursb_r_m +inst_ldurh :: inst_ldurh_r_m +emit_ldurh :: emit_ldurh_r_m +inst_sturh :: inst_sturh_r_m +emit_sturh :: emit_sturh_r_m +inst_ldursh :: inst_ldursh_r_m +emit_ldursh :: emit_ldursh_r_m +inst_ldursw :: inst_ldursw_r_m +emit_ldursw :: emit_ldursw_r_m +inst_ldnp :: inst_ldnp_r_r_m +emit_ldnp :: emit_ldnp_r_r_m +inst_stnp :: inst_stnp_r_r_m +emit_stnp :: emit_stnp_r_r_m +inst_ldxp :: inst_ldxp_r_r_m +emit_ldxp :: emit_ldxp_r_r_m +inst_stxp :: inst_stxp_r_r_r_m +emit_stxp :: emit_stxp_r_r_r_m +inst_ldaxp :: inst_ldaxp_r_r_m +emit_ldaxp :: emit_ldaxp_r_r_m +inst_stlxp :: inst_stlxp_r_r_r_m +emit_stlxp :: emit_stlxp_r_r_r_m +inst_ldxrb :: inst_ldxrb_r_m +emit_ldxrb :: emit_ldxrb_r_m +inst_stxrb :: inst_stxrb_r_r_m +emit_stxrb :: emit_stxrb_r_r_m +inst_ldaxrb :: inst_ldaxrb_r_m +emit_ldaxrb :: emit_ldaxrb_r_m +inst_stlxrb :: inst_stlxrb_r_r_m +emit_stlxrb :: emit_stlxrb_r_r_m +inst_ldxrh :: inst_ldxrh_r_m +emit_ldxrh :: emit_ldxrh_r_m +inst_stxrh :: inst_stxrh_r_r_m +emit_stxrh :: emit_stxrh_r_r_m +inst_ldaxrh :: inst_ldaxrh_r_m +emit_ldaxrh :: emit_ldaxrh_r_m +inst_stlxrh :: inst_stlxrh_r_r_m +emit_stlxrh :: emit_stlxrh_r_r_m +inst_ldapr :: inst_ldapr_r_m +emit_ldapr :: emit_ldapr_r_m +inst_ldaprb :: inst_ldaprb_r_m +emit_ldaprb :: emit_ldaprb_r_m +inst_ldaprh :: inst_ldaprh_r_m +emit_ldaprh :: emit_ldaprh_r_m +inst_ldadd :: inst_ldadd_r_r_m +emit_ldadd :: emit_ldadd_r_r_m +inst_ldadda :: inst_ldadda_r_r_m +emit_ldadda :: emit_ldadda_r_r_m +inst_ldaddl :: inst_ldaddl_r_r_m +emit_ldaddl :: emit_ldaddl_r_r_m +inst_ldaddal :: inst_ldaddal_r_r_m +emit_ldaddal :: emit_ldaddal_r_r_m +inst_ldclr :: inst_ldclr_r_r_m +emit_ldclr :: emit_ldclr_r_r_m +inst_ldclra :: inst_ldclra_r_r_m +emit_ldclra :: emit_ldclra_r_r_m +inst_ldclrl :: inst_ldclrl_r_r_m +emit_ldclrl :: emit_ldclrl_r_r_m +inst_ldclral :: inst_ldclral_r_r_m +emit_ldclral :: emit_ldclral_r_r_m +inst_ldeor :: inst_ldeor_r_r_m +emit_ldeor :: emit_ldeor_r_r_m +inst_ldeora :: inst_ldeora_r_r_m +emit_ldeora :: emit_ldeora_r_r_m +inst_ldeorl :: inst_ldeorl_r_r_m +emit_ldeorl :: emit_ldeorl_r_r_m +inst_ldeoral :: inst_ldeoral_r_r_m +emit_ldeoral :: emit_ldeoral_r_r_m +inst_ldset :: inst_ldset_r_r_m +emit_ldset :: emit_ldset_r_r_m +inst_ldseta :: inst_ldseta_r_r_m +emit_ldseta :: emit_ldseta_r_r_m +inst_ldsetl :: inst_ldsetl_r_r_m +emit_ldsetl :: emit_ldsetl_r_r_m +inst_ldsetal :: inst_ldsetal_r_r_m +emit_ldsetal :: emit_ldsetal_r_r_m +inst_ldsmax :: inst_ldsmax_r_r_m +emit_ldsmax :: emit_ldsmax_r_r_m +inst_ldsmaxa :: inst_ldsmaxa_r_r_m +emit_ldsmaxa :: emit_ldsmaxa_r_r_m +inst_ldsmaxl :: inst_ldsmaxl_r_r_m +emit_ldsmaxl :: emit_ldsmaxl_r_r_m +inst_ldsmaxal :: inst_ldsmaxal_r_r_m +emit_ldsmaxal :: emit_ldsmaxal_r_r_m +inst_ldsmin :: inst_ldsmin_r_r_m +emit_ldsmin :: emit_ldsmin_r_r_m +inst_ldsmina :: inst_ldsmina_r_r_m +emit_ldsmina :: emit_ldsmina_r_r_m +inst_ldsminl :: inst_ldsminl_r_r_m +emit_ldsminl :: emit_ldsminl_r_r_m +inst_ldsminal :: inst_ldsminal_r_r_m +emit_ldsminal :: emit_ldsminal_r_r_m +inst_ldumax :: inst_ldumax_r_r_m +emit_ldumax :: emit_ldumax_r_r_m +inst_ldumaxa :: inst_ldumaxa_r_r_m +emit_ldumaxa :: emit_ldumaxa_r_r_m +inst_ldumaxl :: inst_ldumaxl_r_r_m +emit_ldumaxl :: emit_ldumaxl_r_r_m +inst_ldumaxal :: inst_ldumaxal_r_r_m +emit_ldumaxal :: emit_ldumaxal_r_r_m +inst_ldumin :: inst_ldumin_r_r_m +emit_ldumin :: emit_ldumin_r_r_m +inst_ldumina :: inst_ldumina_r_r_m +emit_ldumina :: emit_ldumina_r_r_m +inst_lduminl :: inst_lduminl_r_r_m +emit_lduminl :: emit_lduminl_r_r_m +inst_lduminal :: inst_lduminal_r_r_m +emit_lduminal :: emit_lduminal_r_r_m +inst_swp :: inst_swp_r_r_m +emit_swp :: emit_swp_r_r_m +inst_swpa :: inst_swpa_r_r_m +emit_swpa :: emit_swpa_r_r_m +inst_swpl :: inst_swpl_r_r_m +emit_swpl :: emit_swpl_r_r_m +inst_swpal :: inst_swpal_r_r_m +emit_swpal :: emit_swpal_r_r_m +inst_cas :: inst_cas_r_r_m +emit_cas :: emit_cas_r_r_m +inst_casa :: inst_casa_r_r_m +emit_casa :: emit_casa_r_r_m +inst_casl :: inst_casl_r_r_m +emit_casl :: emit_casl_r_r_m +inst_casal :: inst_casal_r_r_m +emit_casal :: emit_casal_r_r_m +inst_casb :: inst_casb_r_r_m +emit_casb :: emit_casb_r_r_m +inst_casab :: inst_casab_r_r_m +emit_casab :: emit_casab_r_r_m +inst_caslb :: inst_caslb_r_r_m +emit_caslb :: emit_caslb_r_r_m +inst_casalb :: inst_casalb_r_r_m +emit_casalb :: emit_casalb_r_r_m +inst_cash :: inst_cash_r_r_m +emit_cash :: emit_cash_r_r_m +inst_casah :: inst_casah_r_r_m +emit_casah :: emit_casah_r_r_m +inst_caslh :: inst_caslh_r_r_m +emit_caslh :: emit_caslh_r_r_m +inst_casalh :: inst_casalh_r_r_m +emit_casalh :: emit_casalh_r_r_m +inst_casp :: inst_casp_r_r_m +emit_casp :: emit_casp_r_r_m +inst_caspa :: inst_caspa_r_r_m +emit_caspa :: emit_caspa_r_r_m +inst_caspl :: inst_caspl_r_r_m +emit_caspl :: emit_caspl_r_r_m +inst_caspal :: inst_caspal_r_r_m +emit_caspal :: emit_caspal_r_r_m +inst_pacia :: inst_pacia_r_r +emit_pacia :: emit_pacia_r_r +inst_pacib :: inst_pacib_r_r +emit_pacib :: emit_pacib_r_r +inst_pacda :: inst_pacda_r_r +emit_pacda :: emit_pacda_r_r +inst_pacdb :: inst_pacdb_r_r +emit_pacdb :: emit_pacdb_r_r +inst_paciza :: inst_paciza_r +emit_paciza :: emit_paciza_r +inst_pacizb :: inst_pacizb_r +emit_pacizb :: emit_pacizb_r +inst_pacdza :: inst_pacdza_r +emit_pacdza :: emit_pacdza_r +inst_pacdzb :: inst_pacdzb_r +emit_pacdzb :: emit_pacdzb_r +inst_autia :: inst_autia_r_r +emit_autia :: emit_autia_r_r +inst_autib :: inst_autib_r_r +emit_autib :: emit_autib_r_r +inst_autda :: inst_autda_r_r +emit_autda :: emit_autda_r_r +inst_autdb :: inst_autdb_r_r +emit_autdb :: emit_autdb_r_r +inst_autiza :: inst_autiza_r +emit_autiza :: emit_autiza_r +inst_autizb :: inst_autizb_r +emit_autizb :: emit_autizb_r +inst_autdza :: inst_autdza_r +emit_autdza :: emit_autdza_r +inst_autdzb :: inst_autdzb_r +emit_autdzb :: emit_autdzb_r +inst_paciasp :: inst_paciasp_none +emit_paciasp :: emit_paciasp_none +inst_pacibsp :: inst_pacibsp_none +emit_pacibsp :: emit_pacibsp_none +inst_autiasp :: inst_autiasp_none +emit_autiasp :: emit_autiasp_none +inst_autibsp :: inst_autibsp_none +emit_autibsp :: emit_autibsp_none +inst_pacia1716 :: inst_pacia1716_none +emit_pacia1716 :: emit_pacia1716_none +inst_pacib1716 :: inst_pacib1716_none +emit_pacib1716 :: emit_pacib1716_none +inst_autia1716 :: inst_autia1716_none +emit_autia1716 :: emit_autia1716_none +inst_autib1716 :: inst_autib1716_none +emit_autib1716 :: emit_autib1716_none +inst_pacga :: inst_pacga_r_r_r +emit_pacga :: emit_pacga_r_r_r +inst_xpaci :: inst_xpaci_r +emit_xpaci :: emit_xpaci_r +inst_xpacd :: inst_xpacd_r +emit_xpacd :: emit_xpacd_r +inst_xpaclri :: inst_xpaclri_none +emit_xpaclri :: emit_xpaclri_none +inst_retaa :: inst_retaa_none +emit_retaa :: emit_retaa_none +inst_retab :: inst_retab_none +emit_retab :: emit_retab_none +inst_braa :: inst_braa_r_r +emit_braa :: emit_braa_r_r +inst_brab :: inst_brab_r_r +emit_brab :: emit_brab_r_r +inst_braaz :: inst_braaz_r +emit_braaz :: emit_braaz_r +inst_brabz :: inst_brabz_r +emit_brabz :: emit_brabz_r +inst_blraa :: inst_blraa_r_r +emit_blraa :: emit_blraa_r_r +inst_blrab :: inst_blrab_r_r +emit_blrab :: emit_blrab_r_r +inst_blraaz :: inst_blraaz_r +emit_blraaz :: emit_blraaz_r +inst_blrabz :: inst_blrabz_r +emit_blrabz :: emit_blrabz_r +inst_eretaa :: inst_eretaa_none +emit_eretaa :: emit_eretaa_none +inst_eretab :: inst_eretab_none +emit_eretab :: emit_eretab_none +inst_bti :: inst_bti_i +emit_bti :: emit_bti_i +inst_irg :: inst_irg_r_r_r +emit_irg :: emit_irg_r_r_r +inst_addg :: inst_addg_r_r_i_i +emit_addg :: emit_addg_r_r_i_i +inst_subg :: inst_subg_r_r_i_i +emit_subg :: emit_subg_r_r_i_i +inst_gmi :: inst_gmi_r_r_r +emit_gmi :: emit_gmi_r_r_r +inst_subp :: inst_subp_r_r_r +emit_subp :: emit_subp_r_r_r +inst_subps :: inst_subps_r_r_r +emit_subps :: emit_subps_r_r_r +inst_ldg :: inst_ldg_r_m +emit_ldg :: emit_ldg_r_m +inst_stg :: inst_stg_r_m +emit_stg :: emit_stg_r_m +inst_st2g :: inst_st2g_r_m +emit_st2g :: emit_st2g_r_m +inst_stzg :: inst_stzg_r_m +emit_stzg :: emit_stzg_r_m +inst_stz2g :: inst_stz2g_r_m +emit_stz2g :: emit_stz2g_r_m +inst_stgp :: inst_stgp_r_r_m +emit_stgp :: emit_stgp_r_r_m +inst_ldgm :: inst_ldgm_r_m +emit_ldgm :: emit_ldgm_r_m +inst_stgm :: inst_stgm_r_m +emit_stgm :: emit_stgm_r_m +inst_stzgm :: inst_stzgm_r_m +emit_stzgm :: emit_stzgm_r_m +inst_crc32b :: inst_crc32b_r_r_r +emit_crc32b :: emit_crc32b_r_r_r +inst_crc32h :: inst_crc32h_r_r_r +emit_crc32h :: emit_crc32h_r_r_r +inst_crc32w :: inst_crc32w_r_r_r +emit_crc32w :: emit_crc32w_r_r_r +inst_crc32x :: inst_crc32x_r_r_r +emit_crc32x :: emit_crc32x_r_r_r +inst_crc32cb :: inst_crc32cb_r_r_r +emit_crc32cb :: emit_crc32cb_r_r_r +inst_crc32ch :: inst_crc32ch_r_r_r +emit_crc32ch :: emit_crc32ch_r_r_r +inst_crc32cw :: inst_crc32cw_r_r_r +emit_crc32cw :: emit_crc32cw_r_r_r +inst_crc32cx :: inst_crc32cx_r_r_r +emit_crc32cx :: emit_crc32cx_r_r_r +inst_aese :: proc{ inst_aese_v16b_v16b, inst_aese_z_z } +emit_aese :: proc{ emit_aese_v16b_v16b, emit_aese_z_z } +inst_aesd :: proc{ inst_aesd_v16b_v16b, inst_aesd_z_z } +emit_aesd :: proc{ emit_aesd_v16b_v16b, emit_aesd_z_z } +inst_aesmc :: proc{ inst_aesmc_v16b_v16b, inst_aesmc_z } +emit_aesmc :: proc{ emit_aesmc_v16b_v16b, emit_aesmc_z } +inst_aesimc :: proc{ inst_aesimc_v16b_v16b, inst_aesimc_z } +emit_aesimc :: proc{ emit_aesimc_v16b_v16b, emit_aesimc_z } +inst_sha1h :: inst_sha1h_r_r +emit_sha1h :: emit_sha1h_r_r +inst_sha1c :: inst_sha1c_r_r_v4s +emit_sha1c :: emit_sha1c_r_r_v4s +inst_sha1p :: inst_sha1p_r_r_v4s +emit_sha1p :: emit_sha1p_r_r_v4s +inst_sha1m :: inst_sha1m_r_r_v4s +emit_sha1m :: emit_sha1m_r_r_v4s +inst_sha1su0 :: inst_sha1su0_v4s_v4s_v4s +emit_sha1su0 :: emit_sha1su0_v4s_v4s_v4s +inst_sha1su1 :: inst_sha1su1_v4s_v4s +emit_sha1su1 :: emit_sha1su1_v4s_v4s +inst_sha256h :: inst_sha256h_r_r_v4s +emit_sha256h :: emit_sha256h_r_r_v4s +inst_sha256h2 :: inst_sha256h2_r_r_v4s +emit_sha256h2 :: emit_sha256h2_r_r_v4s +inst_sha256su0 :: inst_sha256su0_v4s_v4s +emit_sha256su0 :: emit_sha256su0_v4s_v4s +inst_sha256su1 :: inst_sha256su1_v4s_v4s_v4s +emit_sha256su1 :: emit_sha256su1_v4s_v4s_v4s +inst_sha512h :: inst_sha512h_r_r_v2d +emit_sha512h :: emit_sha512h_r_r_v2d +inst_sha512h2 :: inst_sha512h2_r_r_v2d +emit_sha512h2 :: emit_sha512h2_r_r_v2d +inst_sha512su0 :: inst_sha512su0_v2d_v2d +emit_sha512su0 :: emit_sha512su0_v2d_v2d +inst_sha512su1 :: inst_sha512su1_v2d_v2d_v2d +emit_sha512su1 :: emit_sha512su1_v2d_v2d_v2d +inst_eor3 :: proc{ inst_eor3_v16b_v16b_v16b_v16b, inst_eor3_z_z_z_z } +emit_eor3 :: proc{ emit_eor3_v16b_v16b_v16b_v16b, emit_eor3_z_z_z_z } +inst_bcax :: proc{ inst_bcax_v16b_v16b_v16b_v16b, inst_bcax_z_z_z_z } +emit_bcax :: proc{ emit_bcax_v16b_v16b_v16b_v16b, emit_bcax_z_z_z_z } +inst_rax1 :: inst_rax1_v2d_v2d_v2d +emit_rax1 :: emit_rax1_v2d_v2d_v2d +inst_xar :: proc{ inst_xar_v2d_v2d_v2d_i, inst_xar_z_z_z_i } +emit_xar :: proc{ emit_xar_v2d_v2d_v2d_i, emit_xar_z_z_z_i } +inst_sm3partw1 :: inst_sm3partw1_v4s_v4s_v4s +emit_sm3partw1 :: emit_sm3partw1_v4s_v4s_v4s +inst_sm3partw2 :: inst_sm3partw2_v4s_v4s_v4s +emit_sm3partw2 :: emit_sm3partw2_v4s_v4s_v4s +inst_sm3ss1 :: inst_sm3ss1_v4s_v4s_v4s_v4s +emit_sm3ss1 :: emit_sm3ss1_v4s_v4s_v4s_v4s +inst_sm3tt1a :: inst_sm3tt1a_v4s_v4s_ves +emit_sm3tt1a :: emit_sm3tt1a_v4s_v4s_ves +inst_sm3tt1b :: inst_sm3tt1b_v4s_v4s_ves +emit_sm3tt1b :: emit_sm3tt1b_v4s_v4s_ves +inst_sm3tt2a :: inst_sm3tt2a_v4s_v4s_ves +emit_sm3tt2a :: emit_sm3tt2a_v4s_v4s_ves +inst_sm3tt2b :: inst_sm3tt2b_v4s_v4s_ves +emit_sm3tt2b :: emit_sm3tt2b_v4s_v4s_ves +inst_sm4e :: inst_sm4e_v4s_v4s +emit_sm4e :: emit_sm4e_v4s_v4s +inst_sm4ekey :: inst_sm4ekey_v4s_v4s_v4s +emit_sm4ekey :: emit_sm4ekey_v4s_v4s_v4s +inst_pmull :: inst_pmull_v8h_v8b_v8b +emit_pmull :: emit_pmull_v8h_v8b_v8b +inst_pmull2 :: inst_pmull2_v8h_v16b_v16b +emit_pmull2 :: emit_pmull2_v8h_v16b_v16b +inst_bfcvt :: proc{ inst_bfcvt_r_r, inst_bfcvt_z_p_z } +emit_bfcvt :: proc{ emit_bfcvt_r_r, emit_bfcvt_z_p_z } +inst_bfdot :: inst_bfdot_v4s_v8h_v8h +emit_bfdot :: emit_bfdot_v4s_v8h_v8h +inst_bfmmla :: inst_bfmmla_v4s_v8h_v8h +emit_bfmmla :: emit_bfmmla_v4s_v8h_v8h +inst_bfmlalb :: inst_bfmlalb_v4s_v8h_v8h +emit_bfmlalb :: emit_bfmlalb_v4s_v8h_v8h +inst_bfmlalt :: inst_bfmlalt_v4s_v8h_v8h +emit_bfmlalt :: emit_bfmlalt_v4s_v8h_v8h +inst_bfcvtn :: inst_bfcvtn_v4h_v4s +emit_bfcvtn :: emit_bfcvtn_v4h_v4s +inst_bfcvtn2 :: inst_bfcvtn2_v8h_v4s +emit_bfcvtn2 :: emit_bfcvtn2_v8h_v4s +inst_mul :: proc{ inst_mul_v16b_v16b_v16b, inst_mul_z_p_z_z } +emit_mul :: proc{ emit_mul_v16b_v16b_v16b, emit_mul_z_p_z_z } +inst_mla :: inst_mla_v8b_v8b_v8b +emit_mla :: emit_mla_v8b_v8b_v8b +inst_mls :: inst_mls_v8b_v8b_v8b +emit_mls :: emit_mls_v8b_v8b_v8b +inst_neg :: proc{ inst_neg_v8b_v8b, inst_neg_z_p_z, inst_neg_r_sh } +emit_neg :: proc{ emit_neg_v8b_v8b, emit_neg_z_p_z, emit_neg_r_sh } +inst_abs :: proc{ inst_abs_v8b_v8b, inst_abs_z_p_z } +emit_abs :: proc{ emit_abs_v8b_v8b, emit_abs_z_p_z } +inst_shadd :: inst_shadd_v8b_v8b_v8b +emit_shadd :: emit_shadd_v8b_v8b_v8b +inst_uhadd :: inst_uhadd_v8b_v8b_v8b +emit_uhadd :: emit_uhadd_v8b_v8b_v8b +inst_shsub :: inst_shsub_v8b_v8b_v8b +emit_shsub :: emit_shsub_v8b_v8b_v8b +inst_uhsub :: inst_uhsub_v8b_v8b_v8b +emit_uhsub :: emit_uhsub_v8b_v8b_v8b +inst_srhadd :: inst_srhadd_v8b_v8b_v8b +emit_srhadd :: emit_srhadd_v8b_v8b_v8b +inst_urhadd :: inst_urhadd_v8b_v8b_v8b +emit_urhadd :: emit_urhadd_v8b_v8b_v8b +inst_sqadd :: proc{ inst_sqadd_v8b_v8b_v8b, inst_sqadd_z_z_z } +emit_sqadd :: proc{ emit_sqadd_v8b_v8b_v8b, emit_sqadd_z_z_z } +inst_uqadd :: proc{ inst_uqadd_v8b_v8b_v8b, inst_uqadd_z_z_z } +emit_uqadd :: proc{ emit_uqadd_v8b_v8b_v8b, emit_uqadd_z_z_z } +inst_sqsub :: proc{ inst_sqsub_v8b_v8b_v8b, inst_sqsub_z_z_z } +emit_sqsub :: proc{ emit_sqsub_v8b_v8b_v8b, emit_sqsub_z_z_z } +inst_uqsub :: proc{ inst_uqsub_v8b_v8b_v8b, inst_uqsub_z_z_z } +emit_uqsub :: proc{ emit_uqsub_v8b_v8b_v8b, emit_uqsub_z_z_z } +inst_smax :: proc{ inst_smax_v8b_v8b_v8b, inst_smax_z_p_z_z } +emit_smax :: proc{ emit_smax_v8b_v8b_v8b, emit_smax_z_p_z_z } +inst_umax :: proc{ inst_umax_v8b_v8b_v8b, inst_umax_z_p_z_z } +emit_umax :: proc{ emit_umax_v8b_v8b_v8b, emit_umax_z_p_z_z } +inst_smin :: proc{ inst_smin_v8b_v8b_v8b, inst_smin_z_p_z_z } +emit_smin :: proc{ emit_smin_v8b_v8b_v8b, emit_smin_z_p_z_z } +inst_umin :: proc{ inst_umin_v8b_v8b_v8b, inst_umin_z_p_z_z } +emit_umin :: proc{ emit_umin_v8b_v8b_v8b, emit_umin_z_p_z_z } +inst_sabd :: proc{ inst_sabd_v8b_v8b_v8b, inst_sabd_z_p_z_z } +emit_sabd :: proc{ emit_sabd_v8b_v8b_v8b, emit_sabd_z_p_z_z } +inst_uabd :: proc{ inst_uabd_v8b_v8b_v8b, inst_uabd_z_p_z_z } +emit_uabd :: proc{ emit_uabd_v8b_v8b_v8b, emit_uabd_z_p_z_z } +inst_saba :: inst_saba_v8b_v8b_v8b +emit_saba :: emit_saba_v8b_v8b_v8b +inst_uaba :: inst_uaba_v8b_v8b_v8b +emit_uaba :: emit_uaba_v8b_v8b_v8b +inst_addp :: inst_addp_v8b_v8b_v8b +emit_addp :: emit_addp_v8b_v8b_v8b +inst_addv :: inst_addv_r_v8b +emit_addv :: emit_addv_r_v8b +inst_saddlp :: inst_saddlp_v4h_v8b +emit_saddlp :: emit_saddlp_v4h_v8b +inst_uaddlp :: inst_uaddlp_v4h_v8b +emit_uaddlp :: emit_uaddlp_v4h_v8b +inst_sadalp :: inst_sadalp_v4h_v8b +emit_sadalp :: emit_sadalp_v4h_v8b +inst_uadalp :: inst_uadalp_v4h_v8b +emit_uadalp :: emit_uadalp_v4h_v8b +inst_saddlv :: inst_saddlv_r_v8b +emit_saddlv :: emit_saddlv_r_v8b +inst_uaddlv :: inst_uaddlv_r_v8b +emit_uaddlv :: emit_uaddlv_r_v8b +inst_smaxv :: inst_smaxv_r_v8b +emit_smaxv :: emit_smaxv_r_v8b +inst_umaxv :: inst_umaxv_r_v8b +emit_umaxv :: emit_umaxv_r_v8b +inst_sminv :: inst_sminv_r_v8b +emit_sminv :: emit_sminv_r_v8b +inst_uminv :: inst_uminv_r_v8b +emit_uminv :: emit_uminv_r_v8b +inst_smaxp :: inst_smaxp_v8b_v8b_v8b +emit_smaxp :: emit_smaxp_v8b_v8b_v8b +inst_umaxp :: inst_umaxp_v8b_v8b_v8b +emit_umaxp :: emit_umaxp_v8b_v8b_v8b +inst_sminp :: inst_sminp_v8b_v8b_v8b +emit_sminp :: emit_sminp_v8b_v8b_v8b +inst_uminp :: inst_uminp_v8b_v8b_v8b +emit_uminp :: emit_uminp_v8b_v8b_v8b +inst_saddl :: inst_saddl_v8h_v8b_v8b +emit_saddl :: emit_saddl_v8h_v8b_v8b +inst_saddl2 :: inst_saddl2_v8h_v16b_v16b +emit_saddl2 :: emit_saddl2_v8h_v16b_v16b +inst_uaddl :: inst_uaddl_v8h_v8b_v8b +emit_uaddl :: emit_uaddl_v8h_v8b_v8b +inst_uaddl2 :: inst_uaddl2_v8h_v16b_v16b +emit_uaddl2 :: emit_uaddl2_v8h_v16b_v16b +inst_ssubl :: inst_ssubl_v8h_v8b_v8b +emit_ssubl :: emit_ssubl_v8h_v8b_v8b +inst_ssubl2 :: inst_ssubl2_v8h_v16b_v16b +emit_ssubl2 :: emit_ssubl2_v8h_v16b_v16b +inst_usubl :: inst_usubl_v8h_v8b_v8b +emit_usubl :: emit_usubl_v8h_v8b_v8b +inst_usubl2 :: inst_usubl2_v8h_v16b_v16b +emit_usubl2 :: emit_usubl2_v8h_v16b_v16b +inst_saddw :: inst_saddw_v8h_v8h_v8b +emit_saddw :: emit_saddw_v8h_v8h_v8b +inst_saddw2 :: inst_saddw2_v8h_v8h_v16b +emit_saddw2 :: emit_saddw2_v8h_v8h_v16b +inst_uaddw :: inst_uaddw_v8h_v8h_v8b +emit_uaddw :: emit_uaddw_v8h_v8h_v8b +inst_uaddw2 :: inst_uaddw2_v8h_v8h_v16b +emit_uaddw2 :: emit_uaddw2_v8h_v8h_v16b +inst_ssubw :: inst_ssubw_v8h_v8h_v8b +emit_ssubw :: emit_ssubw_v8h_v8h_v8b +inst_ssubw2 :: inst_ssubw2_v8h_v8h_v16b +emit_ssubw2 :: emit_ssubw2_v8h_v8h_v16b +inst_usubw :: inst_usubw_v8h_v8h_v8b +emit_usubw :: emit_usubw_v8h_v8h_v8b +inst_usubw2 :: inst_usubw2_v8h_v8h_v16b +emit_usubw2 :: emit_usubw2_v8h_v8h_v16b +inst_raddhn :: inst_raddhn_v8b_v8h_v8h +emit_raddhn :: emit_raddhn_v8b_v8h_v8h +inst_raddhn2 :: inst_raddhn2_v16b_v8h_v8h +emit_raddhn2 :: emit_raddhn2_v16b_v8h_v8h +inst_rsubhn :: inst_rsubhn_v8b_v8h_v8h +emit_rsubhn :: emit_rsubhn_v8b_v8h_v8h +inst_rsubhn2 :: inst_rsubhn2_v16b_v8h_v8h +emit_rsubhn2 :: emit_rsubhn2_v16b_v8h_v8h +inst_addhn :: inst_addhn_v8b_v8h_v8h +emit_addhn :: emit_addhn_v8b_v8h_v8h +inst_addhn2 :: inst_addhn2_v16b_v8h_v8h +emit_addhn2 :: emit_addhn2_v16b_v8h_v8h +inst_subhn :: inst_subhn_v8b_v8h_v8h +emit_subhn :: emit_subhn_v8b_v8h_v8h +inst_subhn2 :: inst_subhn2_v16b_v8h_v8h +emit_subhn2 :: emit_subhn2_v16b_v8h_v8h +inst_xtn :: inst_xtn_v8b_v8h +emit_xtn :: emit_xtn_v8b_v8h +inst_xtn2 :: inst_xtn2_v16b_v8h +emit_xtn2 :: emit_xtn2_v16b_v8h +inst_sqxtn :: inst_sqxtn_v8b_v8h +emit_sqxtn :: emit_sqxtn_v8b_v8h +inst_sqxtn2 :: inst_sqxtn2_v16b_v8h +emit_sqxtn2 :: emit_sqxtn2_v16b_v8h +inst_uqxtn :: inst_uqxtn_v8b_v8h +emit_uqxtn :: emit_uqxtn_v8b_v8h +inst_uqxtn2 :: inst_uqxtn2_v16b_v8h +emit_uqxtn2 :: emit_uqxtn2_v16b_v8h +inst_sqxtun :: inst_sqxtun_v8b_v8h +emit_sqxtun :: emit_sqxtun_v8b_v8h +inst_sqxtun2 :: inst_sqxtun2_v16b_v8h +emit_sqxtun2 :: emit_sqxtun2_v16b_v8h +inst_smull :: inst_smull_v8h_v8b_v8b +emit_smull :: emit_smull_v8h_v8b_v8b +inst_smull2 :: inst_smull2_v8h_v16b_v16b +emit_smull2 :: emit_smull2_v8h_v16b_v16b +inst_umull :: inst_umull_v8h_v8b_v8b +emit_umull :: emit_umull_v8h_v8b_v8b +inst_umull2 :: inst_umull2_v8h_v16b_v16b +emit_umull2 :: emit_umull2_v8h_v16b_v16b +inst_smlal :: inst_smlal_v8h_v8b_v8b +emit_smlal :: emit_smlal_v8h_v8b_v8b +inst_smlal2 :: inst_smlal2_v8h_v16b_v16b +emit_smlal2 :: emit_smlal2_v8h_v16b_v16b +inst_umlal :: inst_umlal_v8h_v8b_v8b +emit_umlal :: emit_umlal_v8h_v8b_v8b +inst_umlal2 :: inst_umlal2_v8h_v16b_v16b +emit_umlal2 :: emit_umlal2_v8h_v16b_v16b +inst_smlsl :: inst_smlsl_v8h_v8b_v8b +emit_smlsl :: emit_smlsl_v8h_v8b_v8b +inst_smlsl2 :: inst_smlsl2_v8h_v16b_v16b +emit_smlsl2 :: emit_smlsl2_v8h_v16b_v16b +inst_umlsl :: inst_umlsl_v8h_v8b_v8b +emit_umlsl :: emit_umlsl_v8h_v8b_v8b +inst_umlsl2 :: inst_umlsl2_v8h_v16b_v16b +emit_umlsl2 :: emit_umlsl2_v8h_v16b_v16b +inst_sqdmull :: inst_sqdmull_v4s_v4h_v4h +emit_sqdmull :: emit_sqdmull_v4s_v4h_v4h +inst_sqdmull2 :: inst_sqdmull2_v4s_v8h_v8h +emit_sqdmull2 :: emit_sqdmull2_v4s_v8h_v8h +inst_sqdmlal :: inst_sqdmlal_v4s_v4h_v4h +emit_sqdmlal :: emit_sqdmlal_v4s_v4h_v4h +inst_sqdmlal2 :: inst_sqdmlal2_v4s_v8h_v8h +emit_sqdmlal2 :: emit_sqdmlal2_v4s_v8h_v8h +inst_sqdmlsl :: inst_sqdmlsl_v4s_v4h_v4h +emit_sqdmlsl :: emit_sqdmlsl_v4s_v4h_v4h +inst_sqdmlsl2 :: inst_sqdmlsl2_v4s_v8h_v8h +emit_sqdmlsl2 :: emit_sqdmlsl2_v4s_v8h_v8h +inst_sqdmulh :: inst_sqdmulh_v4h_v4h_v4h +emit_sqdmulh :: emit_sqdmulh_v4h_v4h_v4h +inst_sqrdmulh :: inst_sqrdmulh_v4h_v4h_v4h +emit_sqrdmulh :: emit_sqrdmulh_v4h_v4h_v4h +inst_sdot :: inst_sdot_v2s_v8b_v8b +emit_sdot :: emit_sdot_v2s_v8b_v8b +inst_udot :: inst_udot_v2s_v8b_v8b +emit_udot :: emit_udot_v2s_v8b_v8b +inst_usdot :: inst_usdot_v2s_v8b_v8b +emit_usdot :: emit_usdot_v2s_v8b_v8b +inst_fmla :: proc{ inst_fmla_v4s_v4s_v4s, inst_fmla_z_p_z_z, inst_fmla_z_z_z_i } +emit_fmla :: proc{ emit_fmla_v4s_v4s_v4s, emit_fmla_z_p_z_z, emit_fmla_z_z_z_i } +inst_fmls :: proc{ inst_fmls_v4s_v4s_v4s, inst_fmls_z_p_z_z, inst_fmls_z_z_z_i } +emit_fmls :: proc{ emit_fmls_v4s_v4s_v4s, emit_fmls_z_p_z_z, emit_fmls_z_z_z_i } +inst_fmulx :: inst_fmulx_v2s_v2s_v2s +emit_fmulx :: emit_fmulx_v2s_v2s_v2s +inst_fmaxp :: inst_fmaxp_v2s_v2s_v2s +emit_fmaxp :: emit_fmaxp_v2s_v2s_v2s +inst_fminp :: inst_fminp_v2s_v2s_v2s +emit_fminp :: emit_fminp_v2s_v2s_v2s +inst_fmaxnmp :: inst_fmaxnmp_v2s_v2s_v2s +emit_fmaxnmp :: emit_fmaxnmp_v2s_v2s_v2s +inst_fminnmp :: inst_fminnmp_v2s_v2s_v2s +emit_fminnmp :: emit_fminnmp_v2s_v2s_v2s +inst_fmaxv :: inst_fmaxv_r_v4s +emit_fmaxv :: emit_fmaxv_r_v4s +inst_fminv :: inst_fminv_r_v4s +emit_fminv :: emit_fminv_r_v4s +inst_fmaxnmv :: inst_fmaxnmv_r_v4s +emit_fmaxnmv :: emit_fmaxnmv_r_v4s +inst_fminnmv :: inst_fminnmv_r_v4s +emit_fminnmv :: emit_fminnmv_r_v4s +inst_frecpe :: inst_frecpe_v2s_v2s +emit_frecpe :: emit_frecpe_v2s_v2s +inst_frsqrte :: inst_frsqrte_v2s_v2s +emit_frsqrte :: emit_frsqrte_v2s_v2s +inst_frecps :: proc{ inst_frecps_v2s_v2s_v2s, inst_frecps_z_z_z } +emit_frecps :: proc{ emit_frecps_v2s_v2s_v2s, emit_frecps_z_z_z } +inst_frsqrts :: proc{ inst_frsqrts_v2s_v2s_v2s, inst_frsqrts_z_z_z } +emit_frsqrts :: proc{ emit_frsqrts_v2s_v2s_v2s, emit_frsqrts_z_z_z } +inst_frecpx :: proc{ inst_frecpx_r_r, inst_frecpx_z_p_z } +emit_frecpx :: proc{ emit_frecpx_r_r, emit_frecpx_z_p_z } +inst_faddp :: inst_faddp_v2s_v2s_v2s +emit_faddp :: emit_faddp_v2s_v2s_v2s +inst_fcvtl :: inst_fcvtl_v4s_v4h +emit_fcvtl :: emit_fcvtl_v4s_v4h +inst_fcvtl2 :: inst_fcvtl2_v4s_v8h +emit_fcvtl2 :: emit_fcvtl2_v4s_v8h +inst_fcvtn :: inst_fcvtn_v4h_v4s +emit_fcvtn :: emit_fcvtn_v4h_v4s +inst_fcvtn2 :: inst_fcvtn2_v8h_v4s +emit_fcvtn2 :: emit_fcvtn2_v8h_v4s +inst_fcvtxn :: inst_fcvtxn_v2s_v2d +emit_fcvtxn :: emit_fcvtxn_v2s_v2d +inst_fcvtxn2 :: inst_fcvtxn2_v4s_v2d +emit_fcvtxn2 :: emit_fcvtxn2_v4s_v2d +inst_fcmeq :: proc{ inst_fcmeq_v2s_v2s_v2s, inst_fcmeq_p_p_z_z } +emit_fcmeq :: proc{ emit_fcmeq_v2s_v2s_v2s, emit_fcmeq_p_p_z_z } +inst_fcmge :: proc{ inst_fcmge_v2s_v2s_v2s, inst_fcmge_p_p_z_z } +emit_fcmge :: proc{ emit_fcmge_v2s_v2s_v2s, emit_fcmge_p_p_z_z } +inst_fcmgt :: proc{ inst_fcmgt_v2s_v2s_v2s, inst_fcmgt_p_p_z_z } +emit_fcmgt :: proc{ emit_fcmgt_v2s_v2s_v2s, emit_fcmgt_p_p_z_z } +inst_fcmle :: proc{ inst_fcmle_v2s_v2s, inst_fcmle_p_p_z } +emit_fcmle :: proc{ emit_fcmle_v2s_v2s, emit_fcmle_p_p_z } +inst_fcmlt :: proc{ inst_fcmlt_v2s_v2s, inst_fcmlt_p_p_z } +emit_fcmlt :: proc{ emit_fcmlt_v2s_v2s, emit_fcmlt_p_p_z } +inst_facge :: inst_facge_v2s_v2s_v2s +emit_facge :: emit_facge_v2s_v2s_v2s +inst_facgt :: inst_facgt_v2s_v2s_v2s +emit_facgt :: emit_facgt_v2s_v2s_v2s +inst_cmeq :: inst_cmeq_v16b_v16b_v16b +emit_cmeq :: emit_cmeq_v16b_v16b_v16b +inst_cmge :: inst_cmge_v8b_v8b_v8b +emit_cmge :: emit_cmge_v8b_v8b_v8b +inst_cmgt :: inst_cmgt_v16b_v16b_v16b +emit_cmgt :: emit_cmgt_v16b_v16b_v16b +inst_cmhi :: inst_cmhi_v16b_v16b_v16b +emit_cmhi :: emit_cmhi_v16b_v16b_v16b +inst_cmhs :: inst_cmhs_v8b_v8b_v8b +emit_cmhs :: emit_cmhs_v8b_v8b_v8b +inst_cmle :: inst_cmle_v8b_v8b +emit_cmle :: emit_cmle_v8b_v8b +inst_cmlt :: inst_cmlt_v8b_v8b +emit_cmlt :: emit_cmlt_v8b_v8b +inst_cmtst :: inst_cmtst_v8b_v8b_v8b +emit_cmtst :: emit_cmtst_v8b_v8b_v8b +inst_mvn :: inst_mvn_v8b_v8b +emit_mvn :: emit_mvn_v8b_v8b +inst_bit :: inst_bit_v16b_v16b_v16b +emit_bit :: emit_bit_v16b_v16b_v16b +inst_bif :: inst_bif_v16b_v16b_v16b +emit_bif :: emit_bif_v16b_v16b_v16b +inst_bsl :: proc{ inst_bsl_v16b_v16b_v16b, inst_bsl_z_z_z_z } +emit_bsl :: proc{ emit_bsl_v16b_v16b_v16b, emit_bsl_z_z_z_z } +inst_shl :: inst_shl_v8b_v8b_i +emit_shl :: emit_shl_v8b_v8b_i +inst_sqshl :: inst_sqshl_v8b_v8b_i +emit_sqshl :: emit_sqshl_v8b_v8b_i +inst_sqshlu :: inst_sqshlu_v8b_v8b_i +emit_sqshlu :: emit_sqshlu_v8b_v8b_i +inst_srshl :: inst_srshl_v8b_v8b_v8b +emit_srshl :: emit_srshl_v8b_v8b_v8b +inst_urshl :: inst_urshl_v8b_v8b_v8b +emit_urshl :: emit_urshl_v8b_v8b_v8b +inst_sshr :: inst_sshr_v8b_v8b_i +emit_sshr :: emit_sshr_v8b_v8b_i +inst_ushr :: inst_ushr_v8b_v8b_i +emit_ushr :: emit_ushr_v8b_v8b_i +inst_ssra :: inst_ssra_v8b_v8b_i +emit_ssra :: emit_ssra_v8b_v8b_i +inst_usra :: inst_usra_v8b_v8b_i +emit_usra :: emit_usra_v8b_v8b_i +inst_srshr :: inst_srshr_v8b_v8b_i +emit_srshr :: emit_srshr_v8b_v8b_i +inst_urshr :: inst_urshr_v8b_v8b_i +emit_urshr :: emit_urshr_v8b_v8b_i +inst_srsra :: inst_srsra_v8b_v8b_i +emit_srsra :: emit_srsra_v8b_v8b_i +inst_ursra :: inst_ursra_v8b_v8b_i +emit_ursra :: emit_ursra_v8b_v8b_i +inst_sshl :: inst_sshl_v8b_v8b_v8b +emit_sshl :: emit_sshl_v8b_v8b_v8b +inst_ushl :: inst_ushl_v8b_v8b_v8b +emit_ushl :: emit_ushl_v8b_v8b_v8b +inst_sli :: inst_sli_v8b_v8b_i +emit_sli :: emit_sli_v8b_v8b_i +inst_sri :: inst_sri_v8b_v8b_i +emit_sri :: emit_sri_v8b_v8b_i +inst_sshll :: inst_sshll_v8h_v8b_i +emit_sshll :: emit_sshll_v8h_v8b_i +inst_sshll2 :: inst_sshll2_v8h_v16b_i +emit_sshll2 :: emit_sshll2_v8h_v16b_i +inst_ushll :: inst_ushll_v8h_v8b_i +emit_ushll :: emit_ushll_v8h_v8b_i +inst_ushll2 :: inst_ushll2_v8h_v16b_i +emit_ushll2 :: emit_ushll2_v8h_v16b_i +inst_sxtl :: inst_sxtl_v8h_v8b +emit_sxtl :: emit_sxtl_v8h_v8b +inst_sxtl2 :: inst_sxtl2_v8h_v16b +emit_sxtl2 :: emit_sxtl2_v8h_v16b +inst_uxtl :: inst_uxtl_v8h_v8b +emit_uxtl :: emit_uxtl_v8h_v8b +inst_uxtl2 :: inst_uxtl2_v8h_v16b +emit_uxtl2 :: emit_uxtl2_v8h_v16b +inst_shrn :: inst_shrn_v8b_v8h_i +emit_shrn :: emit_shrn_v8b_v8h_i +inst_shrn2 :: inst_shrn2_v16b_v8h_i +emit_shrn2 :: emit_shrn2_v16b_v8h_i +inst_rshrn :: inst_rshrn_v8b_v8h_i +emit_rshrn :: emit_rshrn_v8b_v8h_i +inst_rshrn2 :: inst_rshrn2_v16b_v8h_i +emit_rshrn2 :: emit_rshrn2_v16b_v8h_i +inst_sqshrn :: inst_sqshrn_v8b_v8h_i +emit_sqshrn :: emit_sqshrn_v8b_v8h_i +inst_sqshrn2 :: inst_sqshrn2_v16b_v8h_i +emit_sqshrn2 :: emit_sqshrn2_v16b_v8h_i +inst_uqshrn :: inst_uqshrn_v8b_v8h_i +emit_uqshrn :: emit_uqshrn_v8b_v8h_i +inst_uqshrn2 :: inst_uqshrn2_v16b_v8h_i +emit_uqshrn2 :: emit_uqshrn2_v16b_v8h_i +inst_sqrshrn :: inst_sqrshrn_v8b_v8h_i +emit_sqrshrn :: emit_sqrshrn_v8b_v8h_i +inst_sqrshrn2 :: inst_sqrshrn2_v16b_v8h_i +emit_sqrshrn2 :: emit_sqrshrn2_v16b_v8h_i +inst_uqrshrn :: inst_uqrshrn_v8b_v8h_i +emit_uqrshrn :: emit_uqrshrn_v8b_v8h_i +inst_uqrshrn2 :: inst_uqrshrn2_v16b_v8h_i +emit_uqrshrn2 :: emit_uqrshrn2_v16b_v8h_i +inst_sqshrun :: inst_sqshrun_v8b_v8h_i +emit_sqshrun :: emit_sqshrun_v8b_v8h_i +inst_sqshrun2 :: inst_sqshrun2_v16b_v8h_i +emit_sqshrun2 :: emit_sqshrun2_v16b_v8h_i +inst_sqrshrun :: inst_sqrshrun_v8b_v8h_i +emit_sqrshrun :: emit_sqrshrun_v8b_v8h_i +inst_sqrshrun2 :: inst_sqrshrun2_v16b_v8h_i +emit_sqrshrun2 :: emit_sqrshrun2_v16b_v8h_i +inst_dup :: proc{ inst_dup_v8b_veb_i, inst_dup_v8b_r, inst_dup_z_r } +emit_dup :: proc{ emit_dup_v8b_veb_i, emit_dup_v8b_r, emit_dup_z_r } +inst_ins :: proc{ inst_ins_veb_i_veb_i, inst_ins_veb_i_r } +emit_ins :: proc{ emit_ins_veb_i_veb_i, emit_ins_veb_i_r } +inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_z_p_z, inst_mov_p_p, inst_mov_r_i } +emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } +inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_z_z_z_i } +emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_z_z_z_i } +inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_z_z_z } +emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_z_z_z } +inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_z_z_z } +emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_z_z_z } +inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_z_z_z } +emit_zip1 :: proc{ emit_zip1_v8b_v8b_v8b, emit_zip1_z_z_z } +inst_zip2 :: proc{ inst_zip2_v8b_v8b_v8b, inst_zip2_z_z_z } +emit_zip2 :: proc{ emit_zip2_v8b_v8b_v8b, emit_zip2_z_z_z } +inst_uzp1 :: proc{ inst_uzp1_v8b_v8b_v8b, inst_uzp1_z_z_z } +emit_uzp1 :: proc{ emit_uzp1_v8b_v8b_v8b, emit_uzp1_z_z_z } +inst_uzp2 :: proc{ inst_uzp2_v8b_v8b_v8b, inst_uzp2_z_z_z } +emit_uzp2 :: proc{ emit_uzp2_v8b_v8b_v8b, emit_uzp2_z_z_z } +inst_trn1 :: proc{ inst_trn1_v8b_v8b_v8b, inst_trn1_z_z_z } +emit_trn1 :: proc{ emit_trn1_v8b_v8b_v8b, emit_trn1_z_z_z } +inst_trn2 :: proc{ inst_trn2_v8b_v8b_v8b, inst_trn2_z_z_z } +emit_trn2 :: proc{ emit_trn2_v8b_v8b_v8b, emit_trn2_z_z_z } +inst_not :: proc{ inst_not_v8b_v8b, inst_not_p_p_p } +emit_not :: proc{ emit_not_v8b_v8b, emit_not_p_p_p } +inst_rev64 :: inst_rev64_v8b_v8b +emit_rev64 :: emit_rev64_v8b_v8b +inst_cnt :: proc{ inst_cnt_v8b_v8b, inst_cnt_z_p_z } +emit_cnt :: proc{ emit_cnt_v8b_v8b, emit_cnt_z_p_z } +inst_urecpe :: inst_urecpe_v2s_v2s +emit_urecpe :: emit_urecpe_v2s_v2s +inst_ursqrte :: inst_ursqrte_v2s_v2s +emit_ursqrte :: emit_ursqrte_v2s_v2s +inst_movi :: inst_movi_v8b_i +emit_movi :: emit_movi_v8b_i +inst_mvni :: inst_mvni_v4h_i +emit_mvni :: emit_mvni_v4h_i +inst_ld1 :: proc{ inst_ld1_v16b_m, inst_ld1_veb_i_m } +emit_ld1 :: proc{ emit_ld1_v16b_m, emit_ld1_veb_i_m } +inst_ld2 :: proc{ inst_ld2_v16b_m, inst_ld2_veb_i_m } +emit_ld2 :: proc{ emit_ld2_v16b_m, emit_ld2_veb_i_m } +inst_ld3 :: proc{ inst_ld3_v16b_m, inst_ld3_veb_i_m } +emit_ld3 :: proc{ emit_ld3_v16b_m, emit_ld3_veb_i_m } +inst_ld4 :: proc{ inst_ld4_v16b_m, inst_ld4_veb_i_m } +emit_ld4 :: proc{ emit_ld4_v16b_m, emit_ld4_veb_i_m } +inst_st1 :: proc{ inst_st1_v16b_m, inst_st1_veb_i_m } +emit_st1 :: proc{ emit_st1_v16b_m, emit_st1_veb_i_m } +inst_st2 :: proc{ inst_st2_v16b_m, inst_st2_veb_i_m } +emit_st2 :: proc{ emit_st2_v16b_m, emit_st2_veb_i_m } +inst_st3 :: proc{ inst_st3_v16b_m, inst_st3_veb_i_m } +emit_st3 :: proc{ emit_st3_v16b_m, emit_st3_veb_i_m } +inst_st4 :: proc{ inst_st4_v16b_m, inst_st4_veb_i_m } +emit_st4 :: proc{ emit_st4_v16b_m, emit_st4_veb_i_m } +inst_ld1r :: inst_ld1r_v16b_m +emit_ld1r :: emit_ld1r_v16b_m +inst_ld2r :: inst_ld2r_v16b_m +emit_ld2r :: emit_ld2r_v16b_m +inst_ld3r :: inst_ld3r_v16b_m +emit_ld3r :: emit_ld3r_v16b_m +inst_ld4r :: inst_ld4r_v16b_m +emit_ld4r :: emit_ld4r_v16b_m +inst_subr :: inst_subr_z_p_z_z +emit_subr :: emit_subr_z_p_z_z +inst_asrr :: inst_asrr_z_p_z_z +emit_asrr :: emit_asrr_z_p_z_z +inst_lslr :: inst_lslr_z_p_z_z +emit_lslr :: emit_lslr_z_p_z_z +inst_lsrr :: inst_lsrr_z_p_z_z +emit_lsrr :: emit_lsrr_z_p_z_z +inst_ftsmul :: inst_ftsmul_z_z_z +emit_ftsmul :: emit_ftsmul_z_z_z +inst_fsubr :: inst_fsubr_z_p_z_z +emit_fsubr :: emit_fsubr_z_p_z_z +inst_fdivr :: inst_fdivr_z_p_z_z +emit_fdivr :: emit_fdivr_z_p_z_z +inst_fnmla :: inst_fnmla_z_p_z_z +emit_fnmla :: emit_fnmla_z_p_z_z +inst_fnmls :: inst_fnmls_z_p_z_z +emit_fnmls :: emit_fnmls_z_p_z_z +inst_nand :: inst_nand_p_p_p_p +emit_nand :: emit_nand_p_p_p_p +inst_nor :: inst_nor_p_p_p_p +emit_nor :: emit_nor_p_p_p_p +inst_sel :: inst_sel_p_p_p_p +emit_sel :: emit_sel_p_p_p_p +inst_orrs :: inst_orrs_p_p_p_p +emit_orrs :: emit_orrs_p_p_p_p +inst_eors :: inst_eors_p_p_p_p +emit_eors :: emit_eors_p_p_p_p +inst_nands :: inst_nands_p_p_p_p +emit_nands :: emit_nands_p_p_p_p +inst_nors :: inst_nors_p_p_p_p +emit_nors :: emit_nors_p_p_p_p +inst_orns :: inst_orns_p_p_p_p +emit_orns :: emit_orns_p_p_p_p +inst_movs :: inst_movs_p_p_p +emit_movs :: emit_movs_p_p_p +inst_ptrue :: inst_ptrue_p_i +emit_ptrue :: emit_ptrue_p_i +inst_ptrues :: inst_ptrues_p_i +emit_ptrues :: emit_ptrues_p_i +inst_pfalse :: inst_pfalse_p +emit_pfalse :: emit_pfalse_p +inst_pfirst :: inst_pfirst_p_p_p +emit_pfirst :: emit_pfirst_p_p_p +inst_pnext :: inst_pnext_p_p_p +emit_pnext :: emit_pnext_p_p_p +inst_brka :: inst_brka_p_p_p +emit_brka :: emit_brka_p_p_p +inst_brkb :: inst_brkb_p_p_p +emit_brkb :: emit_brkb_p_p_p +inst_brkas :: inst_brkas_p_p_p +emit_brkas :: emit_brkas_p_p_p +inst_brkbs :: inst_brkbs_p_p_p +emit_brkbs :: emit_brkbs_p_p_p +inst_brkpa :: inst_brkpa_p_p_p_p +emit_brkpa :: emit_brkpa_p_p_p_p +inst_brkpb :: inst_brkpb_p_p_p_p +emit_brkpb :: emit_brkpb_p_p_p_p +inst_brkn :: inst_brkn_p_p_p_p +emit_brkn :: emit_brkn_p_p_p_p +inst_rdffr :: inst_rdffr_p +emit_rdffr :: emit_rdffr_p +inst_wrffr :: inst_wrffr_p +emit_wrffr :: emit_wrffr_p +inst_setffr :: inst_setffr_none +emit_setffr :: emit_setffr_none +inst_cmpeq :: inst_cmpeq_p_p_z_z +emit_cmpeq :: emit_cmpeq_p_p_z_z +inst_cmpne :: inst_cmpne_p_p_z_z +emit_cmpne :: emit_cmpne_p_p_z_z +inst_cmpge :: inst_cmpge_p_p_z_z +emit_cmpge :: emit_cmpge_p_p_z_z +inst_cmpgt :: inst_cmpgt_p_p_z_z +emit_cmpgt :: emit_cmpgt_p_p_z_z +inst_cmple :: inst_cmple_p_p_z_z +emit_cmple :: emit_cmple_p_p_z_z +inst_cmplt :: inst_cmplt_p_p_z_z +emit_cmplt :: emit_cmplt_p_p_z_z +inst_cmphi :: inst_cmphi_p_p_z_z +emit_cmphi :: emit_cmphi_p_p_z_z +inst_cmphs :: inst_cmphs_p_p_z_z +emit_cmphs :: emit_cmphs_p_p_z_z +inst_cmplo :: inst_cmplo_p_p_z_z +emit_cmplo :: emit_cmplo_p_p_z_z +inst_cmpls :: inst_cmpls_p_p_z_z +emit_cmpls :: emit_cmpls_p_p_z_z +inst_fcmne :: inst_fcmne_p_p_z_z +emit_fcmne :: emit_fcmne_p_p_z_z +inst_fcmuo :: inst_fcmuo_p_p_z_z +emit_fcmuo :: emit_fcmuo_p_p_z_z +inst_insr :: inst_insr_z_r +emit_insr :: emit_insr_z_r +inst_cpy :: inst_cpy_z_p_r +emit_cpy :: emit_cpy_z_p_r +inst_compact :: inst_compact_z_p_z +emit_compact :: emit_compact_z_p_z +inst_ld1b :: proc{ inst_ld1b_z_p_m, inst_ld1b_i_p_m } +emit_ld1b :: proc{ emit_ld1b_z_p_m, emit_ld1b_i_p_m } +inst_ld1h :: proc{ inst_ld1h_z_p_m, inst_ld1h_i_p_m } +emit_ld1h :: proc{ emit_ld1h_z_p_m, emit_ld1h_i_p_m } +inst_ld1w :: proc{ inst_ld1w_z_p_m, inst_ld1w_i_p_m } +emit_ld1w :: proc{ emit_ld1w_z_p_m, emit_ld1w_i_p_m } +inst_ld1d :: proc{ inst_ld1d_z_p_m, inst_ld1d_i_p_m } +emit_ld1d :: proc{ emit_ld1d_z_p_m, emit_ld1d_i_p_m } +inst_ld1sb :: inst_ld1sb_z_p_m +emit_ld1sb :: emit_ld1sb_z_p_m +inst_ld1sh :: inst_ld1sh_z_p_m +emit_ld1sh :: emit_ld1sh_z_p_m +inst_ld1sw :: inst_ld1sw_z_p_m +emit_ld1sw :: emit_ld1sw_z_p_m +inst_st1b :: proc{ inst_st1b_z_p_m, inst_st1b_i_p_m } +emit_st1b :: proc{ emit_st1b_z_p_m, emit_st1b_i_p_m } +inst_st1h :: proc{ inst_st1h_z_p_m, inst_st1h_i_p_m } +emit_st1h :: proc{ emit_st1h_z_p_m, emit_st1h_i_p_m } +inst_st1w :: proc{ inst_st1w_z_p_m, inst_st1w_i_p_m } +emit_st1w :: proc{ emit_st1w_z_p_m, emit_st1w_i_p_m } +inst_st1d :: proc{ inst_st1d_z_p_m, inst_st1d_i_p_m } +emit_st1d :: proc{ emit_st1d_z_p_m, emit_st1d_i_p_m } +inst_ldff1b :: inst_ldff1b_z_p_m +emit_ldff1b :: emit_ldff1b_z_p_m +inst_ldff1h :: inst_ldff1h_z_p_m +emit_ldff1h :: emit_ldff1h_z_p_m +inst_ldff1w :: inst_ldff1w_z_p_m +emit_ldff1w :: emit_ldff1w_z_p_m +inst_ldff1d :: inst_ldff1d_z_p_m +emit_ldff1d :: emit_ldff1d_z_p_m +inst_whilege :: inst_whilege_p_r_r +emit_whilege :: emit_whilege_p_r_r +inst_whilegt :: inst_whilegt_p_r_r +emit_whilegt :: emit_whilegt_p_r_r +inst_whilele :: inst_whilele_p_r_r +emit_whilele :: emit_whilele_p_r_r +inst_whilelt :: inst_whilelt_p_r_r +emit_whilelt :: emit_whilelt_p_r_r +inst_whilehi :: inst_whilehi_p_r_r +emit_whilehi :: emit_whilehi_p_r_r +inst_whilehs :: inst_whilehs_p_r_r +emit_whilehs :: emit_whilehs_p_r_r +inst_whilelo :: inst_whilelo_p_r_r +emit_whilelo :: emit_whilelo_p_r_r +inst_whilels :: inst_whilels_p_r_r +emit_whilels :: emit_whilels_p_r_r +inst_sqrdmlah :: inst_sqrdmlah_z_z_z +emit_sqrdmlah :: emit_sqrdmlah_z_z_z +inst_sqrdmlsh :: inst_sqrdmlsh_z_z_z +emit_sqrdmlsh :: emit_sqrdmlsh_z_z_z +inst_adclb :: inst_adclb_z_z_z +emit_adclb :: emit_adclb_z_z_z +inst_adclt :: inst_adclt_z_z_z +emit_adclt :: emit_adclt_z_z_z +inst_sbclb :: inst_sbclb_z_z_z +emit_sbclb :: emit_sbclb_z_z_z +inst_sbclt :: inst_sbclt_z_z_z +emit_sbclt :: emit_sbclt_z_z_z +inst_tbl2 :: inst_tbl2_z_z_z +emit_tbl2 :: emit_tbl2_z_z_z +inst_match :: inst_match_p_p_z_z +emit_match :: emit_match_p_p_z_z +inst_nmatch :: inst_nmatch_p_p_z_z +emit_nmatch :: emit_nmatch_p_p_z_z +inst_histcnt :: inst_histcnt_z_p_z_z +emit_histcnt :: emit_histcnt_z_p_z_z +inst_histseg :: inst_histseg_z_z_z +emit_histseg :: emit_histseg_z_z_z +inst_smstart :: inst_smstart_none +emit_smstart :: emit_smstart_none +inst_smstop :: inst_smstop_none +emit_smstop :: emit_smstop_none +inst_rdsvl :: inst_rdsvl_r_i +emit_rdsvl :: emit_rdsvl_r_i +inst_addha :: inst_addha_i_p_p_z +emit_addha :: emit_addha_i_p_p_z +inst_addva :: inst_addva_i_p_p_z +emit_addva :: emit_addva_i_p_p_z +inst_zero :: inst_zero_i +emit_zero :: emit_zero_i +inst_fmopa :: inst_fmopa_i_p_p_z +emit_fmopa :: emit_fmopa_i_p_p_z +inst_fmops :: inst_fmops_i_p_p_z +emit_fmops :: emit_fmops_i_p_p_z +inst_bfmopa :: inst_bfmopa_i_p_p_z +emit_bfmopa :: emit_bfmopa_i_p_p_z +inst_bfmops :: inst_bfmops_i_p_p_z +emit_bfmops :: emit_bfmops_i_p_p_z +inst_smopa :: inst_smopa_i_p_p_z +emit_smopa :: emit_smopa_i_p_p_z +inst_smops :: inst_smops_i_p_p_z +emit_smops :: emit_smops_i_p_p_z +inst_umopa :: inst_umopa_i_p_p_z +emit_umopa :: emit_umopa_i_p_p_z +inst_umops :: inst_umops_i_p_p_z +emit_umops :: emit_umops_i_p_p_z +inst_usmopa :: inst_usmopa_i_p_p_z +emit_usmopa :: emit_usmopa_i_p_p_z +inst_sumopa :: inst_sumopa_i_p_p_z +emit_sumopa :: emit_sumopa_i_p_p_z +inst_ld1q :: inst_ld1q_i_p_m +emit_ld1q :: emit_ld1q_i_p_m +inst_st1q :: inst_st1q_i_p_m +emit_st1q :: emit_st1q_i_p_m +inst_mova :: proc{ inst_mova_z_p_i, inst_mova_i_p_z } +emit_mova :: proc{ emit_mova_z_p_i, emit_mova_i_p_z } +inst_fcmla :: inst_fcmla_v4h_v4h_v4h_i +emit_fcmla :: emit_fcmla_v4h_v4h_v4h_i +inst_fcadd :: inst_fcadd_v4h_v4h_v4h_i +emit_fcadd :: emit_fcadd_v4h_v4h_v4h_i +inst_prfb :: inst_prfb_i_p_m +emit_prfb :: emit_prfb_i_p_m +inst_prfh :: inst_prfh_i_p_m +emit_prfh :: emit_prfh_i_p_m +inst_prfw :: inst_prfw_i_p_m +emit_prfw :: emit_prfw_i_p_m +inst_prfd :: inst_prfd_i_p_m +emit_prfd :: emit_prfd_i_p_m +inst_ldnt1b :: inst_ldnt1b_z_p_m +emit_ldnt1b :: emit_ldnt1b_z_p_m +inst_ldnt1h :: inst_ldnt1h_z_p_m +emit_ldnt1h :: emit_ldnt1h_z_p_m +inst_ldnt1w :: inst_ldnt1w_z_p_m +emit_ldnt1w :: emit_ldnt1w_z_p_m +inst_ldnt1d :: inst_ldnt1d_z_p_m +emit_ldnt1d :: emit_ldnt1d_z_p_m +inst_stnt1b :: inst_stnt1b_z_p_m +emit_stnt1b :: emit_stnt1b_z_p_m +inst_stnt1h :: inst_stnt1h_z_p_m +emit_stnt1h :: emit_stnt1h_z_p_m +inst_stnt1w :: inst_stnt1w_z_p_m +emit_stnt1w :: emit_stnt1w_z_p_m +inst_stnt1d :: inst_stnt1d_z_p_m +emit_stnt1d :: emit_stnt1d_z_p_m +inst_splice :: inst_splice_z_p_z_z +emit_splice :: emit_splice_z_p_z_z +inst_index :: proc{ inst_index_z_i_i, inst_index_z_i_r, inst_index_z_r_i, inst_index_z_r_r } +emit_index :: proc{ emit_index_z_i_i, emit_index_z_i_r, emit_index_z_r_i, emit_index_z_r_r } +inst_bsl1n :: inst_bsl1n_z_z_z_z +emit_bsl1n :: emit_bsl1n_z_z_z_z +inst_bsl2n :: inst_bsl2n_z_z_z_z +emit_bsl2n :: emit_bsl2n_z_z_z_z +inst_nbsl :: inst_nbsl_z_z_z_z +emit_nbsl :: emit_nbsl_z_z_z_z +inst_pmul :: inst_pmul_z_z_z +emit_pmul :: emit_pmul_z_z_z +inst_pmullb :: inst_pmullb_z_z_z +emit_pmullb :: emit_pmullb_z_z_z +inst_pmullt :: inst_pmullt_z_z_z +emit_pmullt :: emit_pmullt_z_z_z +inst_bfcvtnt :: inst_bfcvtnt_z_p_z +emit_bfcvtnt :: emit_bfcvtnt_z_p_z +inst_ldraa :: inst_ldraa_r_m +emit_ldraa :: emit_ldraa_r_m +inst_ldrab :: inst_ldrab_r_m +emit_ldrab :: emit_ldrab_r_m +inst_tstart :: inst_tstart_r +emit_tstart :: emit_tstart_r +inst_tcommit :: inst_tcommit_none +emit_tcommit :: emit_tcommit_none +inst_tcancel :: inst_tcancel_i +emit_tcancel :: emit_tcancel_i +inst_ttest :: inst_ttest_r +emit_ttest :: emit_ttest_r +inst_wfet :: inst_wfet_r +emit_wfet :: emit_wfet_r +inst_wfit :: inst_wfit_r +emit_wfit :: emit_wfit_r +inst_bc_eq :: inst_bc_eq_l +emit_bc_eq :: emit_bc_eq_l +inst_bc_ne :: inst_bc_ne_l +emit_bc_ne :: emit_bc_ne_l +inst_bc_cs :: inst_bc_cs_l +emit_bc_cs :: emit_bc_cs_l +inst_bc_cc :: inst_bc_cc_l +emit_bc_cc :: emit_bc_cc_l +inst_bc_mi :: inst_bc_mi_l +emit_bc_mi :: emit_bc_mi_l +inst_bc_pl :: inst_bc_pl_l +emit_bc_pl :: emit_bc_pl_l +inst_bc_vs :: inst_bc_vs_l +emit_bc_vs :: emit_bc_vs_l +inst_bc_vc :: inst_bc_vc_l +emit_bc_vc :: emit_bc_vc_l +inst_bc_hi :: inst_bc_hi_l +emit_bc_hi :: emit_bc_hi_l +inst_bc_ls :: inst_bc_ls_l +emit_bc_ls :: emit_bc_ls_l +inst_bc_ge :: inst_bc_ge_l +emit_bc_ge :: emit_bc_ge_l +inst_bc_lt :: inst_bc_lt_l +emit_bc_lt :: emit_bc_lt_l +inst_bc_gt :: inst_bc_gt_l +emit_bc_gt :: emit_bc_gt_l +inst_bc_le :: inst_bc_le_l +emit_bc_le :: emit_bc_le_l +inst_bc_al :: inst_bc_al_l +emit_bc_al :: emit_bc_al_l +inst_bc_nv :: inst_bc_nv_l +emit_bc_nv :: emit_bc_nv_l +inst_uxtb :: inst_uxtb_r_r +emit_uxtb :: emit_uxtb_r_r +inst_uxth :: inst_uxth_r_r +emit_uxth :: emit_uxth_r_r +inst_uxtw :: inst_uxtw_r_r +emit_uxtw :: emit_uxtw_r_r +inst_sxtb :: inst_sxtb_r_r +emit_sxtb :: emit_sxtb_r_r +inst_sxth :: inst_sxth_r_r +emit_sxth :: emit_sxth_r_r +inst_sxtw :: inst_sxtw_r_r +emit_sxtw :: emit_sxtw_r_r +inst_adc :: inst_adc_r_r_r +emit_adc :: emit_adc_r_r_r +inst_adcs :: inst_adcs_r_r_r +emit_adcs :: emit_adcs_r_r_r +inst_sbc :: inst_sbc_r_r_r +emit_sbc :: emit_sbc_r_r_r +inst_sbcs :: inst_sbcs_r_r_r +emit_sbcs :: emit_sbcs_r_r_r +inst_ngc :: inst_ngc_r_r +emit_ngc :: emit_ngc_r_r +inst_ngcs :: inst_ngcs_r_r +emit_ngcs :: emit_ngcs_r_r +inst_ldapur :: inst_ldapur_r_m +emit_ldapur :: emit_ldapur_r_m +inst_stlur :: inst_stlur_r_m +emit_stlur :: emit_stlur_r_m +inst_ldapurb :: inst_ldapurb_r_m +emit_ldapurb :: emit_ldapurb_r_m +inst_stlurb :: inst_stlurb_r_m +emit_stlurb :: emit_stlurb_r_m +inst_ldapurh :: inst_ldapurh_r_m +emit_ldapurh :: emit_ldapurh_r_m +inst_stlurh :: inst_stlurh_r_m +emit_stlurh :: emit_stlurh_r_m +inst_ldapursb :: inst_ldapursb_r_m +emit_ldapursb :: emit_ldapursb_r_m +inst_ldapursh :: inst_ldapursh_r_m +emit_ldapursh :: emit_ldapursh_r_m +inst_ldapursw :: inst_ldapursw_r_m +emit_ldapursw :: emit_ldapursw_r_m +inst_bfadd :: proc{ inst_bfadd_z_p_z_z, inst_bfadd_z_z_z } +emit_bfadd :: proc{ emit_bfadd_z_p_z_z, emit_bfadd_z_z_z } +inst_bfsub :: proc{ inst_bfsub_z_p_z_z, inst_bfsub_z_z_z } +emit_bfsub :: proc{ emit_bfsub_z_p_z_z, emit_bfsub_z_z_z } +inst_bfmul :: proc{ inst_bfmul_z_p_z_z, inst_bfmul_z_z_z } +emit_bfmul :: proc{ emit_bfmul_z_p_z_z, emit_bfmul_z_z_z } +inst_bfmla :: inst_bfmla_z_p_z_z +emit_bfmla :: emit_bfmla_z_p_z_z +inst_bfmls :: inst_bfmls_z_p_z_z +emit_bfmls :: emit_bfmls_z_p_z_z +inst_sb :: inst_sb_none +emit_sb :: emit_sb_none +inst_csdb :: inst_csdb_none +emit_csdb :: emit_csdb_none +inst_dgh :: inst_dgh_none +emit_dgh :: emit_dgh_none +inst_psb_csync :: inst_psb_csync_none +emit_psb_csync :: emit_psb_csync_none +inst_tsb_csync :: inst_tsb_csync_none +emit_tsb_csync :: emit_tsb_csync_none +inst_bti_j :: inst_bti_j_none +emit_bti_j :: emit_bti_j_none +inst_bti_c :: inst_bti_c_none +emit_bti_c :: emit_bti_c_none +inst_bti_jc :: inst_bti_jc_none +emit_bti_jc :: emit_bti_jc_none +inst_bfclamp :: inst_bfclamp_z_z_z +emit_bfclamp :: emit_bfclamp_z_z_z +inst_bfmaxnm :: inst_bfmaxnm_z_p_z_z +emit_bfmaxnm :: emit_bfmaxnm_z_p_z_z +inst_bfminnm :: inst_bfminnm_z_p_z_z +emit_bfminnm :: emit_bfminnm_z_p_z_z +inst_luti2 :: inst_luti2_z_z_z_i +emit_luti2 :: emit_luti2_z_z_z_i +inst_luti4 :: inst_luti4_z_z_z_i +emit_luti4 :: emit_luti4_z_z_z_i +inst_zip :: proc{ inst_zip_z_z_z, inst_zip_z_z } +emit_zip :: proc{ emit_zip_z_z_z, emit_zip_z_z } +inst_uzp :: proc{ inst_uzp_z_z_z, inst_uzp_z_z } +emit_uzp :: proc{ emit_uzp_z_z_z, emit_uzp_z_z } +inst_tlbi_rpalos :: inst_tlbi_rpalos_r +emit_tlbi_rpalos :: emit_tlbi_rpalos_r +inst_tlbi_rpaos :: inst_tlbi_rpaos_r +emit_tlbi_rpaos :: emit_tlbi_rpaos_r +inst_at_s1e1a :: inst_at_s1e1a_r +emit_at_s1e1a :: emit_at_s1e1a_r +inst_dc_cipapa :: inst_dc_cipapa_r +emit_dc_cipapa :: emit_dc_cipapa_r +inst_dc_cigdpapa :: inst_dc_cigdpapa_r +emit_dc_cigdpapa :: emit_dc_cigdpapa_r +inst_tlbi_paall :: inst_tlbi_paall_none +emit_tlbi_paall :: emit_tlbi_paall_none +inst_tlbi_paallos :: inst_tlbi_paallos_none +emit_tlbi_paallos :: emit_tlbi_paallos_none +inst_amx_ldx :: inst_amx_ldx_r +emit_amx_ldx :: emit_amx_ldx_r +inst_amx_ldy :: inst_amx_ldy_r +emit_amx_ldy :: emit_amx_ldy_r +inst_amx_stx :: inst_amx_stx_r +emit_amx_stx :: emit_amx_stx_r +inst_amx_sty :: inst_amx_sty_r +emit_amx_sty :: emit_amx_sty_r +inst_amx_ldz :: inst_amx_ldz_r +emit_amx_ldz :: emit_amx_ldz_r +inst_amx_stz :: inst_amx_stz_r +emit_amx_stz :: emit_amx_stz_r +inst_amx_ldzi :: inst_amx_ldzi_r +emit_amx_ldzi :: emit_amx_ldzi_r +inst_amx_stzi :: inst_amx_stzi_r +emit_amx_stzi :: emit_amx_stzi_r +inst_amx_extrx :: inst_amx_extrx_r +emit_amx_extrx :: emit_amx_extrx_r +inst_amx_extry :: inst_amx_extry_r +emit_amx_extry :: emit_amx_extry_r +inst_amx_fma64 :: inst_amx_fma64_r +emit_amx_fma64 :: emit_amx_fma64_r +inst_amx_fms64 :: inst_amx_fms64_r +emit_amx_fms64 :: emit_amx_fms64_r +inst_amx_fma32 :: inst_amx_fma32_r +emit_amx_fma32 :: emit_amx_fma32_r +inst_amx_fms32 :: inst_amx_fms32_r +emit_amx_fms32 :: emit_amx_fms32_r +inst_amx_mac16 :: inst_amx_mac16_r +emit_amx_mac16 :: emit_amx_mac16_r +inst_amx_fma16 :: inst_amx_fma16_r +emit_amx_fma16 :: emit_amx_fma16_r +inst_amx_fms16 :: inst_amx_fms16_r +emit_amx_fms16 :: emit_amx_fms16_r +inst_amx_set :: inst_amx_set_none +emit_amx_set :: emit_amx_set_none +inst_amx_clr :: inst_amx_clr_none +emit_amx_clr :: emit_amx_clr_none +inst_amx_vecint :: inst_amx_vecint_r +emit_amx_vecint :: emit_amx_vecint_r +inst_amx_vecfp :: inst_amx_vecfp_r +emit_amx_vecfp :: emit_amx_vecfp_r +inst_amx_matint :: inst_amx_matint_r +emit_amx_matint :: emit_amx_matint_r +inst_amx_matfp :: inst_amx_matfp_r +emit_amx_matfp :: emit_amx_matfp_r +inst_amx_genlut :: inst_amx_genlut_r +emit_amx_genlut :: emit_amx_genlut_r +inst_cpyp :: inst_cpyp_r_r_r +emit_cpyp :: emit_cpyp_r_r_r +inst_cpym :: inst_cpym_r_r_r +emit_cpym :: emit_cpym_r_r_r +inst_cpye :: inst_cpye_r_r_r +emit_cpye :: emit_cpye_r_r_r +inst_cpyfp :: inst_cpyfp_r_r_r +emit_cpyfp :: emit_cpyfp_r_r_r +inst_cpyfm :: inst_cpyfm_r_r_r +emit_cpyfm :: emit_cpyfm_r_r_r +inst_cpyfe :: inst_cpyfe_r_r_r +emit_cpyfe :: emit_cpyfe_r_r_r +inst_setp :: inst_setp_r_r_r +emit_setp :: emit_setp_r_r_r +inst_setm :: inst_setm_r_r_r +emit_setm :: emit_setm_r_r_r +inst_sete :: inst_sete_r_r_r +emit_sete :: emit_sete_r_r_r +inst_dc_ivac :: inst_dc_ivac_r +emit_dc_ivac :: emit_dc_ivac_r +inst_dc_isw :: inst_dc_isw_r +emit_dc_isw :: emit_dc_isw_r +inst_dc_csw :: inst_dc_csw_r +emit_dc_csw :: emit_dc_csw_r +inst_dc_cisw :: inst_dc_cisw_r +emit_dc_cisw :: emit_dc_cisw_r +inst_dc_zva :: inst_dc_zva_r +emit_dc_zva :: emit_dc_zva_r +inst_dc_cvac :: inst_dc_cvac_r +emit_dc_cvac :: emit_dc_cvac_r +inst_dc_cvau :: inst_dc_cvau_r +emit_dc_cvau :: emit_dc_cvau_r +inst_dc_civac :: inst_dc_civac_r +emit_dc_civac :: emit_dc_civac_r +inst_ic_ialluis :: inst_ic_ialluis_none +emit_ic_ialluis :: emit_ic_ialluis_none +inst_ic_iallu :: inst_ic_iallu_none +emit_ic_iallu :: emit_ic_iallu_none +inst_ic_ivau :: inst_ic_ivau_r +emit_ic_ivau :: emit_ic_ivau_r +inst_at_s1e1r :: inst_at_s1e1r_r +emit_at_s1e1r :: emit_at_s1e1r_r +inst_at_s1e1w :: inst_at_s1e1w_r +emit_at_s1e1w :: emit_at_s1e1w_r +inst_at_s1e0r :: inst_at_s1e0r_r +emit_at_s1e0r :: emit_at_s1e0r_r +inst_at_s1e0w :: inst_at_s1e0w_r +emit_at_s1e0w :: emit_at_s1e0w_r +inst_at_s1e2r :: inst_at_s1e2r_r +emit_at_s1e2r :: emit_at_s1e2r_r +inst_at_s1e2w :: inst_at_s1e2w_r +emit_at_s1e2w :: emit_at_s1e2w_r +inst_at_s1e3r :: inst_at_s1e3r_r +emit_at_s1e3r :: emit_at_s1e3r_r +inst_at_s1e3w :: inst_at_s1e3w_r +emit_at_s1e3w :: emit_at_s1e3w_r +inst_at_s12e1r :: inst_at_s12e1r_r +emit_at_s12e1r :: emit_at_s12e1r_r +inst_at_s12e1w :: inst_at_s12e1w_r +emit_at_s12e1w :: emit_at_s12e1w_r +inst_at_s12e0r :: inst_at_s12e0r_r +emit_at_s12e0r :: emit_at_s12e0r_r +inst_at_s12e0w :: inst_at_s12e0w_r +emit_at_s12e0w :: emit_at_s12e0w_r +inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none +emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none +inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none +emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none +inst_tlbi_vae1 :: inst_tlbi_vae1_r +emit_tlbi_vae1 :: emit_tlbi_vae1_r +inst_tlbi_vae1is :: inst_tlbi_vae1is_r +emit_tlbi_vae1is :: emit_tlbi_vae1is_r +inst_tlbi_aside1 :: inst_tlbi_aside1_r +emit_tlbi_aside1 :: emit_tlbi_aside1_r +inst_tlbi_aside1is :: inst_tlbi_aside1is_r +emit_tlbi_aside1is :: emit_tlbi_aside1is_r +inst_tlbi_vaae1 :: inst_tlbi_vaae1_r +emit_tlbi_vaae1 :: emit_tlbi_vaae1_r +inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r +emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r +inst_tlbi_vale1 :: inst_tlbi_vale1_r +emit_tlbi_vale1 :: emit_tlbi_vale1_r +inst_tlbi_vale1is :: inst_tlbi_vale1is_r +emit_tlbi_vale1is :: emit_tlbi_vale1is_r +inst_tlbi_vaale1 :: inst_tlbi_vaale1_r +emit_tlbi_vaale1 :: emit_tlbi_vaale1_r +inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r +emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r +inst_tlbi_alle1 :: inst_tlbi_alle1_none +emit_tlbi_alle1 :: emit_tlbi_alle1_none +inst_tlbi_alle1is :: inst_tlbi_alle1is_none +emit_tlbi_alle1is :: emit_tlbi_alle1is_none +inst_tlbi_alle2 :: inst_tlbi_alle2_none +emit_tlbi_alle2 :: emit_tlbi_alle2_none +inst_tlbi_alle2is :: inst_tlbi_alle2is_none +emit_tlbi_alle2is :: emit_tlbi_alle2is_none +inst_tlbi_alle3 :: inst_tlbi_alle3_none +emit_tlbi_alle3 :: emit_tlbi_alle3_none +inst_tlbi_alle3is :: inst_tlbi_alle3is_none +emit_tlbi_alle3is :: emit_tlbi_alle3is_none +inst_prfm :: proc{ inst_prfm_i_m, inst_prfm_i_l } +emit_prfm :: proc{ emit_prfm_i_m, emit_prfm_i_l } +inst_prfum :: inst_prfum_i_m +emit_prfum :: emit_prfum_i_m +inst_negs :: inst_negs_r_sh +emit_negs :: emit_negs_r_sh +inst_cmp :: proc{ inst_cmp_r_sh, inst_cmp_r_ex, inst_cmp_r_i } +emit_cmp :: proc{ emit_cmp_r_sh, emit_cmp_r_ex, emit_cmp_r_i } +inst_cmn :: proc{ inst_cmn_r_sh, inst_cmn_r_ex, inst_cmn_r_i } +emit_cmn :: proc{ emit_cmn_r_sh, emit_cmn_r_ex, emit_cmn_r_i } diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 86e20675e..782b3e16a 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -181,7 +181,13 @@ op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand { } // ----------------------------------------------------------------------------- -// NEON V-register arrangement builders -- op.size encodes lanes*elem-bytes: +// NEON V-register arrangement builders. These take the register the caller +// actually has, not its number: rebuilding one from `reg_hw` would relabel an +// X register as a V register, and the matcher -- which checks reg_class -- +// would never get to reject it. Passing a non-V register here now simply +// matches no form, and encode reports it. +// +// op.size encodes lanes*elem-bytes: // .8B = 8 .16B = 16 // .4H = 24 .8H = 32 // .2S = 40 .4S = 48 @@ -191,36 +197,36 @@ op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand { // ----------------------------------------------------------------------------- @(require_results) -op_v_8b :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 8} +op_v_8b :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 8} } @(require_results) -op_v_16b :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 16} +op_v_16b :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 16} } @(require_results) -op_v_4h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 24} +op_v_4h :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 24} } @(require_results) -op_v_8h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 32} +op_v_8h :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 32} } @(require_results) -op_v_2s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 40} +op_v_2s :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 40} } @(require_results) -op_v_4s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 48} +op_v_4s :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 48} } @(require_results) -op_v_1d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 56} +op_v_1d :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 56} } @(require_results) -op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 64} +op_v_2d :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 64} } // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides @@ -232,20 +238,20 @@ op_v_2d :: #force_inline proc "contextless" (n: u8) -> Operand { // which made an element-D view indistinguishable from an 8B arrangement -- // the printer cannot tell `.d` from `.8b` if both are size 8. @(require_results) -op_v_elem_b :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 1} +op_v_elem_b :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 1} } @(require_results) -op_v_elem_h :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 3} +op_v_elem_h :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 3} } @(require_results) -op_v_elem_s :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 5} +op_v_elem_s :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 5} } @(require_results) -op_v_elem_d :: #force_inline proc "contextless" (n: u8) -> Operand { - return Operand{reg = Register(REG_V | u16(n & 0x1F)), kind = .REGISTER, size = 7} +op_v_elem_d :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 7} } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 0e12ed44a..41ba8c37d 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -138,6 +138,14 @@ sbprint :: proc( write_operand(sb, &inst.ops[slot], &display, opts) } } + // CMLE/CMLT/FCMLE/FCMLT only ever compare against zero, and the + // zero is part of the syntax rather than an encoded operand -- an + // assembler will not take the instruction without it. + if inst.mnemonic == .CMLE || inst.mnemonic == .CMLT { + strings.write_string(sb, opts.space_after_comma ? ", #0" : ",#0") + } else if inst.mnemonic == .FCMLE || inst.mnemonic == .FCMLT { + strings.write_string(sb, opts.space_after_comma ? ", #0.0" : ",#0.0") + } } strings.write_string(sb, opts.separator) } diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index a1b37e39f..ffac5ebbd 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -900,7 +900,7 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 77fa940bf..fb95c59c3 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -1364,7 +1364,7 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .BFMLALT { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFCVTN - { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .BFCVTN2 { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .MUL diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index a32b04759..95a914800 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -1794,7 +1794,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 6d8f7d751c7186b621f891c4351a7ac0e1d60e52..e8f0c0c7e8cd4f854c5e376848661edee6ff9b1e 100644 GIT binary patch delta 16 XcmZo@V{T|;-Z0OfQE>Bo|HNVdG;Ibq delta 16 XcmZo@V{T|;-Z0OfQE2mg|HNVdG;; u8 { // Odin-type dedup: two forms producing the same name also produce the same // proc signature (which Odin forbids twice in one overload group). operand_suffix :: proc(t: a.Operand_Type) -> string { + // A NEON arrangement is not recoverable from a Register, so it has to live + // in the name: without this every arrangement of a mnemonic collapses onto + // one builder and only the first is reachable. FP16 variants share a token + // with their non-FP16 twin because they build an identical operand -- the + // encoder tells those two apart by the form, not the operand. + #partial switch t { + case .V_8B: return "v8b" + case .V_16B: return "v16b" + case .V_4H, .V_4H_FP16: return "v4h" + case .V_8H, .V_8H_FP16: return "v8h" + case .V_2S: return "v2s" + case .V_4S: return "v4s" + case .V_1D: return "v1d" + case .V_2D: return "v2d" + case .V_ELEM_B: return "veb" + case .V_ELEM_H: return "veh" + case .V_ELEM_S: return "ves" + case .V_ELEM_D: return "ved" + } switch operand_category(t) { case .REG: return "r" case .ZREG: return "z" @@ -340,18 +359,18 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]st #partial switch operand_category(t) { case .REG: #partial switch t { - case .V_8B: fmt.sbprintf(sb, "op_v_8b(u8(reg_hw(%s)))", names[0]) - case .V_16B: fmt.sbprintf(sb, "op_v_16b(u8(reg_hw(%s)))", names[0]) - case .V_4H, .V_4H_FP16: fmt.sbprintf(sb, "op_v_4h(u8(reg_hw(%s)))", names[0]) - case .V_8H, .V_8H_FP16: fmt.sbprintf(sb, "op_v_8h(u8(reg_hw(%s)))", names[0]) - case .V_2S: fmt.sbprintf(sb, "op_v_2s(u8(reg_hw(%s)))", names[0]) - case .V_4S: fmt.sbprintf(sb, "op_v_4s(u8(reg_hw(%s)))", names[0]) - case .V_1D: fmt.sbprintf(sb, "op_v_1d(u8(reg_hw(%s)))", names[0]) - case .V_2D: fmt.sbprintf(sb, "op_v_2d(u8(reg_hw(%s)))", names[0]) - case .V_ELEM_B: fmt.sbprintf(sb, "op_v_elem_b(u8(reg_hw(%s)))", names[0]) - case .V_ELEM_H: fmt.sbprintf(sb, "op_v_elem_h(u8(reg_hw(%s)))", names[0]) - case .V_ELEM_S: fmt.sbprintf(sb, "op_v_elem_s(u8(reg_hw(%s)))", names[0]) - case .V_ELEM_D: fmt.sbprintf(sb, "op_v_elem_d(u8(reg_hw(%s)))", names[0]) + case .V_8B: fmt.sbprintf(sb, "op_v_8b(%s)", names[0]) + case .V_16B: fmt.sbprintf(sb, "op_v_16b(%s)", names[0]) + case .V_4H, .V_4H_FP16: fmt.sbprintf(sb, "op_v_4h(%s)", names[0]) + case .V_8H, .V_8H_FP16: fmt.sbprintf(sb, "op_v_8h(%s)", names[0]) + case .V_2S: fmt.sbprintf(sb, "op_v_2s(%s)", names[0]) + case .V_4S: fmt.sbprintf(sb, "op_v_4s(%s)", names[0]) + case .V_1D: fmt.sbprintf(sb, "op_v_1d(%s)", names[0]) + case .V_2D: fmt.sbprintf(sb, "op_v_2d(%s)", names[0]) + case .V_ELEM_B: fmt.sbprintf(sb, "op_v_elem_b(%s)", names[0]) + case .V_ELEM_H: fmt.sbprintf(sb, "op_v_elem_h(%s)", names[0]) + case .V_ELEM_S: fmt.sbprintf(sb, "op_v_elem_s(%s)", names[0]) + case .V_ELEM_D: fmt.sbprintf(sb, "op_v_elem_d(%s)", names[0]) case: fmt.sbprintf(sb, "op_reg(%s)", names[0]) } case .ZREG: From a99f21922cc466ce7b113ecb549beba2c6e8ef77 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 23:44:13 -0400 Subject: [PATCH 34/89] rexcode/arm64: close the last ten disassembly gaps The three remaining shapes llvm-mc would not accept back, now that making every NEON arrangement reachable had exposed them. PMULL/PMULL2 wrote their destination as .2d where the architecture says .1q. That arrangement had no operand type because the size marker is lanes*elem-bytes and 1*16 collides with 16B, so V_1Q takes the next free multiple of 8 instead. The encodings were already right; only the label was wrong. TBL/TBX write their table register as a list, `{v1.16b}`. The braces belong to the operand rather than the mnemonic, so V_LIST_16B carries them and the printer stays generic. Only one-register lists are modelled -- LD1-4/ST1-4 need a count, which is still open. SM3TT1A/1B/2A/2B were missing their lane index entirely. The mask already left imm2 free at bits 13:12; the operand simply was not in the table, so every one of them decoded as index 0 and printed `v2.s` with no index at all. Printing that index needed the piece that was never there: a lane index is its own immediate operand, so it printed as a separate `#2` rather than glued to the register it indexes. It now carries a marker and the printer writes `v2.s[3]`. The marker is set from the ENCODING, not the operand type -- EXT shares .VEC_INDEX for a byte index that really is written `#3`. That last part reaches further than these ten: of the 51 lane-indexed forms, all 51 used to print an index that no assembler would take. 15 are now byte-exact against llvm-mc (SM3TT, DUP, INS) and the other 36 are LD1-4/ST1-4, which additionally need the register-list braces. The vector sweep is now 809 byte-exact with nothing mismatched and nothing llvm cannot assemble, from 803/10 before. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 18 +- core/rexcode/isa/arm64/encoder.odin | 6 + core/rexcode/isa/arm64/encoding_types.odin | 6 + core/rexcode/isa/arm64/mnemonic_builders.odin | 158 +++++++++--------- core/rexcode/isa/arm64/operands.odin | 22 +++ core/rexcode/isa/arm64/printer.odin | 35 +++- .../tablegen/generated/decode_tables.odin | 20 +-- .../tablegen/generated/encode_tables.odin | 20 +-- .../isa/arm64/tablegen/instruction_table.odin | 20 +-- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49920 -> 49920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49960 -> 49960 bytes .../arm64/tools/gen_mnemonic_builders.odin | 34 +++- 12 files changed, 211 insertions(+), 128 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 2784cc8f2..217780441 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -232,7 +232,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( else if imm5 & 0x2 != 0 { mb = 1 } else if imm5 & 0x4 != 0 { mb = 2 } else { mb = 3 } - return Operand{immediate = i64(imm5 >> (mb + 1)), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(imm5 >> (mb + 1)), kind = .IMMEDIATE, size = LANE_INDEX} case .NEON_IDX4: // imm4 = index << markerbit; recover markerbit from imm5 in the word. imm5 := (word >> 16) & 0x1F @@ -241,7 +241,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( else if imm5 & 0x2 != 0 { mb = 1 } else if imm5 & 0x4 != 0 { mb = 2 } else { mb = 3 } - return Operand{immediate = i64(((word >> 11) & 0xF) >> mb), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(((word >> 11) & 0xF) >> mb), kind = .IMMEDIATE, size = LANE_INDEX} case .NEON_EXT_IDX: return Operand{immediate = i64((word >> 11) & 0xF), kind = .IMMEDIATE, size = 1} case .IMM5_HI: @@ -264,15 +264,15 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64(word & 0x7), kind = .IMMEDIATE, size = 1} case .NEON_LANE_B: i := ((word >> 30) & 0x1) << 3 | ((word >> 12) & 0x1) << 2 | ((word >> 10) & 0x3) - return Operand{immediate = i64(i), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(i), kind = .IMMEDIATE, size = LANE_INDEX} case .NEON_LANE_H: i := ((word >> 30) & 0x1) << 2 | ((word >> 12) & 0x1) << 1 | ((word >> 11) & 0x1) - return Operand{immediate = i64(i), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(i), kind = .IMMEDIATE, size = LANE_INDEX} case .NEON_LANE_S: i := ((word >> 30) & 0x1) << 1 | ((word >> 12) & 0x1) - return Operand{immediate = i64(i), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(i), kind = .IMMEDIATE, size = LANE_INDEX} case .NEON_LANE_D: - return Operand{immediate = i64((word >> 30) & 0x1), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64((word >> 30) & 0x1), kind = .IMMEDIATE, size = LANE_INDEX} case .SVE_XAR_SHIFT: tszh := (word >> 22) & 0x3 tszl := (word >> 19) & 0x3 @@ -626,6 +626,8 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} // ---- Batch 3 misc immediates ---- + case .NEON_IDX2: + return Operand{immediate = i64((word >> 12) & 0x3), kind = .IMMEDIATE, size = LANE_INDEX} case .ENC_FCMLA_ROT: return Operand{immediate = i64((word >> 12) & 0x3), kind = .IMMEDIATE, size = 1} case .ENC_FCADD_ROT: @@ -688,7 +690,7 @@ reg_from_field :: #force_inline proc "contextless" ( case .Q_REG: cls = REG_Q case .V_REG, .V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D, - .V_4H_FP16, .V_8H_FP16, + .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_LIST_16B, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: cls = REG_V case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D: @@ -722,6 +724,8 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .V_4S: return 48 case .V_1D: return 56 case .V_2D: return 64 + case .V_1Q: return 72 + case .V_LIST_16B: return 80 case .V_ELEM_B: return 1 case .V_ELEM_H: return 3 case .V_ELEM_S: return 5 diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index d7b5fecab..96ea5ca3c 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -226,6 +226,10 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 56) case .V_2D: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 64) + case .V_1Q: + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 72) + case .V_LIST_16B: + return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 80) case .V_4H_FP16: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 24) // Element-indexed V views: element size carried in op.size (B=1,H=2,S=4, @@ -774,6 +778,8 @@ pack_operand_inline :: #force_inline proc( return (vflag << 15) | (ws << 13) | tile // ---- Batch 3 misc immediate encodings ---- + case .NEON_IDX2: + return (u32(op.immediate) & 0x3) << 12 case .ENC_FCMLA_ROT: // 2-bit rotation at bits 13:12 (0/1/2/3 = 0ยฐ/90ยฐ/180ยฐ/270ยฐ). return (u32(op.immediate) & 0x3) << 12 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 46d6e8495..de6ccbd37 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -200,6 +200,11 @@ Operand_Type :: enum u8 { // ---- NEON element lane index (DUP/INS/EXT). The element-size marker // lives in the entry `bits`; the operand drives only the index bits. ---- VEC_INDEX, + V_1Q, // NEON .1q -- one 128-bit lane (PMULL's destination). Not + // expressible as lanes*elem-bytes, which is how the other + // arrangements are coded, since 1*16 collides with 16B. + V_LIST_16B, // a .16b register written as a list, `{v1.16b}` (TBL/TBX). + // Only one-register lists are modelled so far. } // Where each operand's bits land in the 32-bit word. @@ -385,6 +390,7 @@ Operand_Encoding :: enum u8 { // ---- Misc new operand-encoding values (batch 3) ---- ENC_FCMLA_ROT, // 2-bit rotation at bits 13:12 (FCMLA) + NEON_IDX2, // 2-bit lane index at bits 13:12 (SM3TT) ENC_FCADD_ROT, // 1-bit rotation at bit 12 (FCADD) ENC_SVE_PRFOP, // 4-bit prefetch op at bits 3:0 (SVE PRFB/H/W/D) ENC_LDRAA_IMM10, // signed 10-bit imm10 at bits 21:12, scaled by 8 (LDRAA/B) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 49cd46203..79c50be06 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -1197,26 +1197,26 @@ inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register emit_sm3partw2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_v4s_v4s_v4s(dst, src, src2)) } inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3)}} } emit_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_v4s_v4s_v4s_v4s(dst, src, src2, src3)) } -inst_sm3tt1a_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } -emit_sm3tt1a_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_v4s_v4s_ves(dst, src, src2)) } -inst_sm3tt1b_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } -emit_sm3tt1b_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_v4s_v4s_ves(dst, src, src2)) } -inst_sm3tt2a_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } -emit_sm3tt2a_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_v4s_v4s_ves(dst, src, src2)) } -inst_sm3tt2b_v4s_v4s_ves :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), {}}} } -emit_sm3tt2b_v4s_v4s_ves :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_v4s_v4s_ves(dst, src, src2)) } +inst_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +emit_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1a_v4s_v4s_ves_i(dst, src, src2, imm)) } +inst_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +emit_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1b_v4s_v4s_ves_i(dst, src, src2, imm)) } +inst_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +emit_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2a_v4s_v4s_ves_i(dst, src, src2, imm)) } +inst_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +emit_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2b_v4s_v4s_ves_i(dst, src, src2, imm)) } inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } emit_sm4e_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_v4s_v4s(dst, src)) } inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } emit_sm4ekey_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_v4s_v4s_v4s(dst, src, src2)) } inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_pmull_v2d_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_1d(src), op_v_1d(src2), {}}} } +inst_pmull_v1q_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_1d(src), op_v_1d(src2), {}}} } emit_pmull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v8h_v8b_v8b(dst, src, src2)) } -emit_pmull_v2d_v1d_v1d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v2d_v1d_v1d(dst, src, src2)) } +emit_pmull_v1q_v1d_v1d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v1q_v1d_v1d(dst, src, src2)) } inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_pmull2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_2d(src), op_v_2d(src2), {}}} } emit_pmull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v8h_v16b_v16b(dst, src, src2)) } -emit_pmull2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v2d_v2d_v2d(dst, src, src2)) } +emit_pmull2_v1q_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v1q_v2d_v2d(dst, src, src2)) } inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } inst_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } @@ -2769,13 +2769,13 @@ inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register emit_sqrshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v16b_v8h_i(dst, src, imm)) } emit_sqrshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v8h_v4s_i(dst, src, imm)) } emit_sqrshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v4s_v2d_i(dst, src, imm)) } -inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_imm(imm, 4), {}}} } -inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_imm(imm, 4), {}}} } -inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_imm(imm, 4), {}}} } -inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_imm(imm, 4), {}}} } -inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_imm(imm, 4), {}}} } -inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_imm(imm, 4), {}}} } -inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_imm(imm, 4), {}}} } +inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } +inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } +inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } +inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } +inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } +inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } +inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_lane_index(imm), {}}} } inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}}} } inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}}} } inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}}} } @@ -2799,14 +2799,14 @@ emit_dup_v2s_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_dup_v4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v4s_r(dst, src)) } emit_dup_v2d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v2d_r(dst, src)) } emit_dup_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_z_r(rz, src)) } -inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_v_elem_b(src), op_imm(imm2, 4)}} } -inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_v_elem_h(src), op_imm(imm2, 4)}} } -inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_v_elem_s(src), op_imm(imm2, 4)}} } -inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_v_elem_d(src), op_imm(imm2, 4)}} } -inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_reg(src), {}}} } -inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_reg(src), {}}} } -inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_reg(src), {}}} } -inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_reg(src), {}}} } +inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2)}} } +inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2)}} } +inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2)}} } +inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_v_elem_d(src), op_lane_index(imm2)}} } +inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_reg(src), {}}} } +inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_reg(src), {}}} } +inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_reg(src), {}}} } +inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_reg(src), {}}} } emit_ins_veb_i_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veb_i_veb_i(dst, imm, src, imm2)) } emit_ins_veh_i_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veh_i_veh_i(dst, imm, src, imm2)) } emit_ins_ves_i_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_ves_i_ves_i(dst, imm, src, imm2)) } @@ -2835,17 +2835,17 @@ inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } -inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_16b(src), op_v_8b(src2), {}}} } -inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_tbl_v8b_vl16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list_16b(src), op_v_8b(src2), {}}} } +inst_tbl_v16b_vl16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list_16b(src), op_v_16b(src2), {}}} } inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } -emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } +emit_tbl_v8b_vl16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_vl16b_v8b(dst, src, src2)) } +emit_tbl_v16b_vl16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_vl16b_v16b(dst, src, src2)) } emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } -inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_16b(src), op_v_8b(src2), {}}} } -inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_tbx_v8b_vl16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list_16b(src), op_v_8b(src2), {}}} } +inst_tbx_v16b_vl16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list_16b(src), op_v_16b(src2), {}}} } inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } -emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } +emit_tbx_v8b_vl16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_vl16b_v8b(dst, src, src2)) } +emit_tbx_v16b_vl16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_vl16b_v16b(dst, src, src2)) } emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -3013,10 +3013,10 @@ inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } -inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_ld1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v16b_m(dst, mem)) } emit_ld1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v8h_m(dst, mem)) } emit_ld1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v4s_m(dst, mem)) } @@ -3026,30 +3026,30 @@ emit_ld1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_ld1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ves_i_m(dst, imm, mem)) } emit_ld1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ved_i_m(dst, imm, mem)) } inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_ld2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_v16b_m(dst, mem)) } emit_ld2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veb_i_m(dst, imm, mem)) } emit_ld2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veh_i_m(dst, imm, mem)) } emit_ld2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ves_i_m(dst, imm, mem)) } emit_ld2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ved_i_m(dst, imm, mem)) } inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_ld3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_v16b_m(dst, mem)) } emit_ld3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veb_i_m(dst, imm, mem)) } emit_ld3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veh_i_m(dst, imm, mem)) } emit_ld3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ves_i_m(dst, imm, mem)) } emit_ld3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ved_i_m(dst, imm, mem)) } inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_ld4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_v16b_m(dst, mem)) } emit_ld4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veb_i_m(dst, imm, mem)) } emit_ld4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veh_i_m(dst, imm, mem)) } @@ -3059,10 +3059,10 @@ inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } -inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_st1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v16b_m(dst, mem)) } emit_st1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v8h_m(dst, mem)) } emit_st1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v4s_m(dst, mem)) } @@ -3072,30 +3072,30 @@ emit_st1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_st1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ves_i_m(dst, imm, mem)) } emit_st1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ved_i_m(dst, imm, mem)) } inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_st2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_v16b_m(dst, mem)) } emit_st2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veb_i_m(dst, imm, mem)) } emit_st2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veh_i_m(dst, imm, mem)) } emit_st2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ves_i_m(dst, imm, mem)) } emit_st2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ved_i_m(dst, imm, mem)) } inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_st3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_v16b_m(dst, mem)) } emit_st3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veb_i_m(dst, imm, mem)) } emit_st3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veh_i_m(dst, imm, mem)) } emit_st3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ves_i_m(dst, imm, mem)) } emit_st3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ved_i_m(dst, imm, mem)) } inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_imm(imm, 4), op_mem(mem), {}}} } -inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_imm(imm, 4), op_mem(mem), {}}} } +inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } emit_st4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_v16b_m(dst, mem)) } emit_st4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veb_i_m(dst, imm, mem)) } emit_st4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veh_i_m(dst, imm, mem)) } @@ -4364,14 +4364,14 @@ inst_sm3partw2 :: inst_sm3partw2_v4s_v4s_v4s emit_sm3partw2 :: emit_sm3partw2_v4s_v4s_v4s inst_sm3ss1 :: inst_sm3ss1_v4s_v4s_v4s_v4s emit_sm3ss1 :: emit_sm3ss1_v4s_v4s_v4s_v4s -inst_sm3tt1a :: inst_sm3tt1a_v4s_v4s_ves -emit_sm3tt1a :: emit_sm3tt1a_v4s_v4s_ves -inst_sm3tt1b :: inst_sm3tt1b_v4s_v4s_ves -emit_sm3tt1b :: emit_sm3tt1b_v4s_v4s_ves -inst_sm3tt2a :: inst_sm3tt2a_v4s_v4s_ves -emit_sm3tt2a :: emit_sm3tt2a_v4s_v4s_ves -inst_sm3tt2b :: inst_sm3tt2b_v4s_v4s_ves -emit_sm3tt2b :: emit_sm3tt2b_v4s_v4s_ves +inst_sm3tt1a :: inst_sm3tt1a_v4s_v4s_ves_i +emit_sm3tt1a :: emit_sm3tt1a_v4s_v4s_ves_i +inst_sm3tt1b :: inst_sm3tt1b_v4s_v4s_ves_i +emit_sm3tt1b :: emit_sm3tt1b_v4s_v4s_ves_i +inst_sm3tt2a :: inst_sm3tt2a_v4s_v4s_ves_i +emit_sm3tt2a :: emit_sm3tt2a_v4s_v4s_ves_i +inst_sm3tt2b :: inst_sm3tt2b_v4s_v4s_ves_i +emit_sm3tt2b :: emit_sm3tt2b_v4s_v4s_ves_i inst_sm4e :: inst_sm4e_v4s_v4s emit_sm4e :: emit_sm4e_v4s_v4s inst_sm4ekey :: inst_sm4ekey_v4s_v4s_v4s @@ -4756,10 +4756,10 @@ inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_z_p_z, in emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_z_z_z_i } emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_z_z_z_i } -inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_z_z_z } -emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_z_z_z } -inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_z_z_z } -emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_z_z_z } +inst_tbl :: proc{ inst_tbl_v8b_vl16b_v8b, inst_tbl_z_z_z } +emit_tbl :: proc{ emit_tbl_v8b_vl16b_v8b, emit_tbl_z_z_z } +inst_tbx :: proc{ inst_tbx_v8b_vl16b_v8b, inst_tbx_z_z_z } +emit_tbx :: proc{ emit_tbx_v8b_vl16b_v8b, emit_tbx_z_z_z } inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_z_z_z } emit_zip1 :: proc{ emit_zip1_v8b_v8b_v8b, emit_zip1_z_z_z } inst_zip2 :: proc{ inst_zip2_v8b_v8b_v8b, inst_zip2_z_z_z } diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 782b3e16a..daf1a3fe7 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -153,6 +153,17 @@ op_cond :: #force_inline proc "contextless" (c: Cond) -> Operand { return Operand{cond = u8(c), kind = .COND, size = 1} } +// A vector lane index. It is a plain immediate in the encoding, but it prints +// glued to the register it indexes (`v2.s[3]`) rather than as a separate +// operand, so it is marked to tell it apart from an immediate that really is +// one -- EXT's byte index, for instance, is written `#3`. +LANE_INDEX :: u8(0xFF) + +@(require_results) +op_lane_index :: #force_inline proc "contextless" (index: i64) -> Operand { + return Operand{immediate = index, kind = .IMMEDIATE, size = LANE_INDEX} +} + op_sysreg :: #force_inline proc "contextless" (sr: System_Register) -> Operand { return Operand{sysreg = sr, kind = .SYSTEM_REGISTER, size = 2} } @@ -228,6 +239,17 @@ op_v_1d :: #force_inline proc "contextless" (r: Register) -> Operand { op_v_2d :: #force_inline proc "contextless" (r: Register) -> Operand { return Operand{reg = r, kind = .REGISTER, size = 64} } +// .1q breaks the lanes*elem-bytes rule the others follow (1*16 would collide +// with 16B), so it gets the next free multiple of 8. +@(require_results) +op_v_1q :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 72} +} +// A .16b register written as a one-element list, `{v1.16b}` (TBL/TBX). +@(require_results) +op_v_list_16b :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER, size = 80} +} // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides // in op.size so the matcher can disambiguate DUP/INS forms; the lane index is diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 41ba8c37d..2dc3d8106 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -127,15 +127,32 @@ sbprint :: proc( if end_slot > 0 { strings.write_byte(sb, ' ') for slot in 0.. 0 { + op := &inst.ops[slot] + // A lane index belongs to the register before it, so it is + // written `[3]` with no separator rather than as an operand. + lane_index := op.kind == .IMMEDIATE && op.size == LANE_INDEX + if slot > 0 && !lane_index { strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } - if mov_wide && slot == 2 { + // A register the syntax writes as a list keeps its braces. + list := op.kind == .REGISTER && op.size == 80 + switch { + case lane_index: + strings.write_byte(sb, '[') + write_decimal_u32(sb, u32(op.immediate)) + strings.write_byte(sb, ']') + case mov_wide && slot == 2: strings.write_string(sb, opts.uppercase ? "LSL #" : "lsl #") - write_decimal_u32(sb, u32(inst.ops[slot].immediate) * 16) - } else { - write_operand(sb, &inst.ops[slot], &display, opts) + write_decimal_u32(sb, u32(op.immediate) * 16) + case list: + strings.write_byte(sb, '{') + if opts.space_after_comma { strings.write_byte(sb, ' ') } + write_operand(sb, op, &display, opts) + if opts.space_after_comma { strings.write_byte(sb, ' ') } + strings.write_byte(sb, '}') + case: + write_operand(sb, op, &display, opts) } } // CMLE/CMLT/FCMLE/FCMLT only ever compare against zero, and the @@ -345,9 +362,9 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { // arrangements are multiples of 8, element views are odd, and the neutral 4 // that every scalar class uses prints nothing. // -// NOTE: an element-indexed operand still prints as `v0.s` -- the lane index -// rides in a separate immediate operand, so `v0.s[2]` needs the printer to -// fold that operand into this one, which it does not yet do. +// A lane index arrives as its own immediate operand carrying the LANE_INDEX +// marker; the operand loop glues it to the register it indexes (`v0.s[2]`) +// instead of writing it as a separate `#2`. // A system register by name (`cntvct_el0`), falling back to the raw field // when it is not one we know. @(private="file") @@ -382,6 +399,8 @@ write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercas case 48: shape = "4s" case 56: shape = "1d" case 64: shape = "2d" + case 72: shape = "1q" + case 80: shape = "16b" // written as a list; the braces are added by the caller case 1: shape = "b" case 3: shape = "h" case 5: shape = "s" diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index ffac5ebbd..7b71636c1 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -1266,10 +1266,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, @@ -1743,10 +1743,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1803,10 +1803,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index fb95c59c3..8a7e69824 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -1335,23 +1335,23 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .SM3SS1 { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, // .SM3TT1A - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT1B - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2A - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2B - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=3} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM4E { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SM4EKEY { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_2D,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL2 { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .BFCVT { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, @@ -2426,15 +2426,15 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .TBX - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .ZIP1 { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 95a914800..2f2a391e6 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -1752,16 +1752,16 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, }, .SM4E = { {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, @@ -1771,11 +1771,11 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .PMULL = { {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .PMULL2 = { {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, }, .BFCVT = { {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -3039,16 +3039,16 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_LIST_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_LIST_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_LIST_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_LIST_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, }, .ZIP1 = { diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index e8f0c0c7e8cd4f854c5e376848661edee6ff9b1e..a794f1ef0a4fbcb3b2ed455195660eb7a95ed472 100644 GIT binary patch delta 673 zcmYk3y-UMD7>D0n)K)}O(j36i`c! zB>nr6v9(PV4gxsT>7Lu#CU5O{e0phMFp>pqKEi|J%6MGTv~G_b3O4c2js=_iXC=Yx ztGO{LZGX=7OKB2JL?`r&0`z(Iu`c*^Tx9uBAY)tQwT1}@S!3(KBS~QkHm7m>%lsFm_zVYaS=X7s;b6mDU9U>(=?4U++c=ba8~8) z1etwF*kJWk;gHqSX`MDP%-LBJgClS{*kH+nBt>jrHop^T2eVX#Z(1>aMbT&|?y*zO tYA6~CL7pw|DSXeCr&u)pkB0Rd4)$p1X&8@3gW_E8A|D9nvw7D+$msLG=JaD}Y8$ zaKdpW$k`kr%?n@YlBwfO>f0k z1zG=!%?UF0#)DDG?V^tYn1nyWM5-OR-MU&&_r=Y{K?J|n$0RAgm9k!?0fu3^)NK@+ zNkCEmy-ri{b4fDEHkl|~QcOOYae9x+q_{%`uiw}Nw#d&G?V`}Mwdk06rN%5$sQ3%CI5=pk6jM+aQLt4o)ge?+(b``kxHUtqrB*2P zAL!Uo$f8@ETtwWJlEKlzS%i4!<#Mi{`@Z+?SEnj=s^Z9fJqx~&cg--(gKchpF2Zb&*J|ASAvUvp-p}!@uup5PC$WDreoQXNh6=f~0i%wz@hzZc zdUo^A;ELuN)GTRwN)`0hLS{+Ot@BLpL_8gYY4WZBo8(=Q(SxM4#B7jSFSj807ED|B z*B62HUEJUhOzj1p9al701X&)TR$;cvt;TGPTZ38avZ2S1;6s~*&$f%q8VZF%3EZDp zj+vq;p4q<1vixV(;B8n`vS;`}<`DkLE*QgrP#jS9td(dU44;s*rtlr&l@MJCoLUdf G{M;|)wfBVp delta 773 zcmYk)ze~eF6bJB^OF>0!LQS(sq2e#7#lb;SrI>=ch(cQ(svSZF#UHIHBDgg}twk#c z{RcXB6td_RCl?WSrDSk)a26rndAXeH=Y8+J`_*lT-G+GgEvRM{0NlAp`0+eR@1ax* zz^t}qv`{NgCjnmLxa4}0(L-7+2E>HG-jJrnmdcgn0O&0TzHrWZCzhdh3woR4%Eq|4H;KRAI}0c z%eU))1{XBfqGn5pDNRt@^QA>WwNFd^6KPq71bJ704f3wY=tGh$F$+`c=O#m7vTWa9 zo`u$E*wSC%+4V$YSx}S_YISBS+?vc*xwV+J&s&A`9(?FC@Y(T@)kKj Operand_Category { case .W_REG, .X_REG, .WSP_REG, .XSP_REG, .B_REG, .H_REG, .S_REG, .D_REG, .Q_REG, .V_REG, .V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D, - .V_4H_FP16, .V_8H_FP16, + .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_LIST_16B, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: return .REG case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_PAIR, .Z_QUAD: @@ -155,6 +160,18 @@ operand_param_count :: proc(t: a.Operand_Type) -> int { return 1 } +// A lane index prints glued to the register it indexes, so it is built with +// op_lane_index rather than op_imm. Keyed on the ENCODING: EXT writes its byte +// index as a plain immediate while sharing the .VEC_INDEX operand type. +is_lane_index :: proc(e: a.Operand_Encoding) -> bool { + #partial switch e { + case .NEON_IDX5, .NEON_IDX4, .NEON_IDX2, + .NEON_LANE_B, .NEON_LANE_H, .NEON_LANE_S, .NEON_LANE_D: + return true + } + return false +} + // Width byte for op_imm / op_label (informational only; the matcher checks // operand kind, not size, so this never affects correctness). operand_imm_size :: proc(t: a.Operand_Type) -> u8 { @@ -187,6 +204,8 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { case .V_4S: return "v4s" case .V_1D: return "v1d" case .V_2D: return "v2d" + case .V_1Q: return "v1q" + case .V_LIST_16B: return "vl16b" case .V_ELEM_B: return "veb" case .V_ELEM_H: return "veh" case .V_ELEM_S: return "ves" @@ -223,6 +242,7 @@ build_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) if form.enc[i] == .IMPL { continue } sig.types[sig.count] = op + sig.encs[sig.count] = form.enc[i] sig.count += 1 } return sig, true @@ -355,7 +375,7 @@ generate_proc_name :: proc(mnemonic: a.Mnemonic, sig: Operand_Signature) -> stri // the produced encoding is valid for the kept form). // ----------------------------------------------------------------------------- -write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]string) { +write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Operand_Encoding, names: [3]string) { #partial switch operand_category(t) { case .REG: #partial switch t { @@ -367,6 +387,8 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]st case .V_4S: fmt.sbprintf(sb, "op_v_4s(%s)", names[0]) case .V_1D: fmt.sbprintf(sb, "op_v_1d(%s)", names[0]) case .V_2D: fmt.sbprintf(sb, "op_v_2d(%s)", names[0]) + case .V_1Q: fmt.sbprintf(sb, "op_v_1q(%s)", names[0]) + case .V_LIST_16B: fmt.sbprintf(sb, "op_v_list_16b(%s)", names[0]) case .V_ELEM_B: fmt.sbprintf(sb, "op_v_elem_b(%s)", names[0]) case .V_ELEM_H: fmt.sbprintf(sb, "op_v_elem_h(%s)", names[0]) case .V_ELEM_S: fmt.sbprintf(sb, "op_v_elem_s(%s)", names[0]) @@ -384,7 +406,11 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]st case .PREG: fmt.sbprintf(sb, "op_reg(Register(REG_P | (u16(%s) & 0xF)))", names[0]) case .IMM: - fmt.sbprintf(sb, "op_imm(%s, %d)", names[0], operand_imm_size(t)) + if is_lane_index(enc) { + fmt.sbprintf(sb, "op_lane_index(%s)", names[0]) + } else { + fmt.sbprintf(sb, "op_imm(%s, %d)", names[0], operand_imm_size(t)) + } case .REL: fmt.sbprintf(sb, "op_label(%s, 4)", names[0]) case .MEM: @@ -499,7 +525,7 @@ write_inst_fallback :: proc(sb: ^strings.Builder, entry: Proc_Entry) { for i in 0..<4 { if i > 0 { strings.write_string(sb, ", ") } if i < sig.count { - write_operand_expr(sb, sig.types[i], pnames[i]) + write_operand_expr(sb, sig.types[i], sig.encs[i], pnames[i]) } else { strings.write_string(sb, "{}") } From bba65df7eefefd46681822f8d16a4e348616aab4 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 27 Aug 2026 23:58:38 -0400 Subject: [PATCH 35/89] rexcode/arm64: model the NEON register lists LD1-4/ST1-4 write their registers as a list -- `ld2 {v0.16b, v1.16b}, [x1]` -- and none of that was modelled. LD2/LD3/LD4 named a single register where the syntax names two, three or four, so every one of their forms disassembled to something no assembler would take. How many registers the list holds is fixed by the instruction form, not chosen by the caller: LD2 always names two. So it rides on the encoding (VD_LIST1..4, VN_LIST1..4, which pack exactly like VD/VN) rather than on the operand type. Putting it in the type would have meant a type per count per arrangement -- 32 of them -- and would have made the matcher check something the caller cannot vary. The operand carries the count, and the printer walks the run from the first register, wrapping at v31. That replaces the V_LIST_16B one-off added with the TBL/TBX fix, which could only ever express a single-register list; TBL/TBX now go through the same path. Operand grows a byte for the count, which comes out of the padding Instruction already had -- it is still exactly one 64-byte cache line, still aligned to one. The arrangement codes were bare numbers repeated across four files, and the generated builders would have grown more of them, so they are now named constants (VSHAPE_16B and friends). Verified against llvm-mc: 50 whole-register list forms byte-exact, and all 51 lane-indexed forms byte-exact -- `ld2 {v0.b, v1.b}[1], [x1]` and `ld1 {v0.16b}, [x1]` included. Before this and the lane-index change, every one of those 101 printed something that would not assemble. The vector sweep holds at 809 byte-exact with nothing unassemblable. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 11 +- core/rexcode/isa/arm64/encoder.odin | 6 +- core/rexcode/isa/arm64/encoding_types.odin | 8 +- core/rexcode/isa/arm64/instructions.odin | 6 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 124 +++++++++--------- core/rexcode/isa/arm64/operands.odin | 32 ++++- core/rexcode/isa/arm64/printer.odin | 17 ++- .../tablegen/generated/decode_tables.odin | 108 +++++++-------- .../tablegen/generated/encode_tables.odin | 108 +++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 108 +++++++-------- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49920 -> 49920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49960 -> 49960 bytes .../arm64/tools/gen_mnemonic_builders.odin | 42 +++++- 13 files changed, 324 insertions(+), 246 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 217780441..22151f0da 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -452,6 +452,14 @@ extract_operand_inline :: #force_inline proc "contextless" ( return reg_from_field(word, 0, ot) case .VN: return reg_from_field(word, 5, ot) + case .VD_LIST1, .VD_LIST2, .VD_LIST3, .VD_LIST4: + op := reg_from_field(word, 0, ot) + op.list_count = u8(int(en) - int(Operand_Encoding.VD_LIST1)) + 1 + return op + case .VN_LIST1, .VN_LIST2, .VN_LIST3, .VN_LIST4: + op := reg_from_field(word, 5, ot) + op.list_count = u8(int(en) - int(Operand_Encoding.VN_LIST1)) + 1 + return op case .VM: return reg_from_field(word, 16, ot) case .VA: @@ -690,7 +698,7 @@ reg_from_field :: #force_inline proc "contextless" ( case .Q_REG: cls = REG_Q case .V_REG, .V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D, - .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_LIST_16B, + .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: cls = REG_V case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D: @@ -725,7 +733,6 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .V_1D: return 56 case .V_2D: return 64 case .V_1Q: return 72 - case .V_LIST_16B: return 80 case .V_ELEM_B: return 1 case .V_ELEM_H: return 3 case .V_ELEM_S: return 5 diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 96ea5ca3c..d1550ba96 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -228,8 +228,6 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 64) case .V_1Q: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 72) - case .V_LIST_16B: - return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 80) case .V_4H_FP16: return op.kind == .REGISTER && reg_class(op.reg) == REG_V && (op.size == 0 || op.size == 24) // Element-indexed V views: element size carried in op.size (B=1,H=2,S=4, @@ -522,9 +520,9 @@ pack_operand_inline :: #force_inline proc( return ((bit >> 5) & 1) << 31 | (bit & 0x1F) << 19 // ---- NEON / SIMD register slots (alias of RD/RN/RM/RA bit positions) -- - case .VD: + case .VD, .VD_LIST1, .VD_LIST2, .VD_LIST3, .VD_LIST4: return (u32(reg_hw(op.reg)) & 0x1F) << 0 - case .VN: + case .VN, .VN_LIST1, .VN_LIST2, .VN_LIST3, .VN_LIST4: return (u32(reg_hw(op.reg)) & 0x1F) << 5 case .VM: return (u32(reg_hw(op.reg)) & 0x1F) << 16 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index de6ccbd37..5c1e6a033 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -203,8 +203,6 @@ Operand_Type :: enum u8 { V_1Q, // NEON .1q -- one 128-bit lane (PMULL's destination). Not // expressible as lanes*elem-bytes, which is how the other // arrangements are coded, since 1*16 collides with 16B. - V_LIST_16B, // a .16b register written as a list, `{v1.16b}` (TBL/TBX). - // Only one-register lists are modelled so far. } // Where each operand's bits land in the 32-bit word. @@ -391,6 +389,12 @@ Operand_Encoding :: enum u8 { // ---- Misc new operand-encoding values (batch 3) ---- ENC_FCMLA_ROT, // 2-bit rotation at bits 13:12 (FCMLA) NEON_IDX2, // 2-bit lane index at bits 13:12 (SM3TT) + // A register the syntax writes as a list of N consecutive registers, + // `{v0.16b, v1.16b}`. Same bits as VD / VN; N is fixed by the form (LD2 + // always names two), so it rides on the encoding rather than the operand + // type -- otherwise every count would need its own type per arrangement. + VD_LIST1, VD_LIST2, VD_LIST3, VD_LIST4, + VN_LIST1, VN_LIST2, VN_LIST3, VN_LIST4, ENC_FCADD_ROT, // 1-bit rotation at bit 12 (FCADD) ENC_SVE_PRFOP, // 4-bit prefetch op at bits 3:0 (SVE PRFB/H/W/D) ENC_LDRAA_IMM10, // signed 10-bit imm10 at bits 21:12, scaled by 8 (LDRAA/B) diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index e52db3d27..26ad8bd3f 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -25,15 +25,15 @@ Instruction_Flags :: bit_field u8 { // Encode is within 1% and a pure read traversal is ~9% slower at working sets // past L2, both of which the decode win dwarfs for real workloads. // -// The 19 spare bytes are free: they cost nothing over a 48-byte struct that +// The spare bytes are free: they cost nothing over a 48-byte struct that // straddles, and new fields land in them without changing the layout. Instruction :: struct #align(64) { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) = 40 + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) = 44 mnemonic: Mnemonic, // 2 operand_count: u8, // 1 flags: Instruction_Flags, // 1 length: u8, // 1 -- always 4 - _: [19]u8, + _: [15]u8, } #assert(size_of(Instruction) == 64) #assert(align_of(Instruction) == 64) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 79c50be06..d0e11ccc6 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -2835,17 +2835,17 @@ inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } -inst_tbl_v8b_vl16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list_16b(src), op_v_8b(src2), {}}} } -inst_tbl_v16b_vl16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list_16b(src), op_v_16b(src2), {}}} } +inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } +inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbl_v8b_vl16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_vl16b_v8b(dst, src, src2)) } -emit_tbl_v16b_vl16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_vl16b_v16b(dst, src, src2)) } +emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } +emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } -inst_tbx_v8b_vl16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list_16b(src), op_v_8b(src2), {}}} } -inst_tbx_v16b_vl16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list_16b(src), op_v_16b(src2), {}}} } +inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } +inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbx_v8b_vl16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_vl16b_v8b(dst, src, src2)) } -emit_tbx_v16b_vl16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_vl16b_v16b(dst, src, src2)) } +emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } +emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -3009,14 +3009,14 @@ emit_mvni_v4h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_mvni_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v8h_i(dst, imm)) } emit_mvni_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v2s_i(dst, imm)) } emit_mvni_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4s_i(dst, imm)) } -inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } -inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } -inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } -inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } +inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } +inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } +inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } +inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } emit_ld1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v16b_m(dst, mem)) } emit_ld1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v8h_m(dst, mem)) } emit_ld1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v4s_m(dst, mem)) } @@ -3025,44 +3025,44 @@ emit_ld1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_ld1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_veh_i_m(dst, imm, mem)) } emit_ld1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ves_i_m(dst, imm, mem)) } emit_ld1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ved_i_m(dst, imm, mem)) } -inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } +inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } emit_ld2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_v16b_m(dst, mem)) } emit_ld2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veb_i_m(dst, imm, mem)) } emit_ld2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veh_i_m(dst, imm, mem)) } emit_ld2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ves_i_m(dst, imm, mem)) } emit_ld2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ved_i_m(dst, imm, mem)) } -inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } +inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } emit_ld3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_v16b_m(dst, mem)) } emit_ld3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veb_i_m(dst, imm, mem)) } emit_ld3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veh_i_m(dst, imm, mem)) } emit_ld3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ves_i_m(dst, imm, mem)) } emit_ld3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ved_i_m(dst, imm, mem)) } -inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } +inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } emit_ld4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_v16b_m(dst, mem)) } emit_ld4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veb_i_m(dst, imm, mem)) } emit_ld4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veh_i_m(dst, imm, mem)) } emit_ld4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ves_i_m(dst, imm, mem)) } emit_ld4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ved_i_m(dst, imm, mem)) } -inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_mem(mem), {}, {}}} } -inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_mem(mem), {}, {}}} } -inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_mem(mem), {}, {}}} } -inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } +inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } +inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } +inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } +inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } emit_st1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v16b_m(dst, mem)) } emit_st1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v8h_m(dst, mem)) } emit_st1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v4s_m(dst, mem)) } @@ -3071,43 +3071,43 @@ emit_st1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_st1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_veh_i_m(dst, imm, mem)) } emit_st1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ves_i_m(dst, imm, mem)) } emit_st1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ved_i_m(dst, imm, mem)) } -inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } +inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } emit_st2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_v16b_m(dst, mem)) } emit_st2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veb_i_m(dst, imm, mem)) } emit_st2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veh_i_m(dst, imm, mem)) } emit_st2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ves_i_m(dst, imm, mem)) } emit_st2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ved_i_m(dst, imm, mem)) } -inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } +inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } emit_st3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_v16b_m(dst, mem)) } emit_st3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veb_i_m(dst, imm, mem)) } emit_st3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veh_i_m(dst, imm, mem)) } emit_st3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ves_i_m(dst, imm, mem)) } emit_st3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ved_i_m(dst, imm, mem)) } -inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } -inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } +inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } emit_st4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_v16b_m(dst, mem)) } emit_st4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veb_i_m(dst, imm, mem)) } emit_st4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veh_i_m(dst, imm, mem)) } emit_st4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ves_i_m(dst, imm, mem)) } emit_st4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ved_i_m(dst, imm, mem)) } -inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } emit_ld1r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_v16b_m(dst, mem)) } -inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } emit_ld2r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_v16b_m(dst, mem)) } -inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } emit_ld3r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_v16b_m(dst, mem)) } -inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_mem(mem), {}, {}}} } +inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } emit_ld4r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_v16b_m(dst, mem)) } inst_subr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } emit_subr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_z_p_z_z(rz, rz2, rz3, rz4)) } @@ -4756,10 +4756,10 @@ inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_z_p_z, in emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_z_z_z_i } emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_z_z_z_i } -inst_tbl :: proc{ inst_tbl_v8b_vl16b_v8b, inst_tbl_z_z_z } -emit_tbl :: proc{ emit_tbl_v8b_vl16b_v8b, emit_tbl_z_z_z } -inst_tbx :: proc{ inst_tbx_v8b_vl16b_v8b, inst_tbx_z_z_z } -emit_tbx :: proc{ emit_tbx_v8b_vl16b_v8b, emit_tbx_z_z_z } +inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_z_z_z } +emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_z_z_z } +inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_z_z_z } +emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_z_z_z } inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_z_z_z } emit_zip1 :: proc{ emit_zip1_v8b_v8b_v8b, emit_zip1_z_z_z } inst_zip2 :: proc{ inst_zip2_v8b_v8b_v8b, inst_zip2_z_z_z } diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index daf1a3fe7..cf4b1c1cc 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -109,8 +109,13 @@ Operand :: struct #packed { }, // 12 total because of alignment kind: Operand_Kind, // 1 size: u8, // 1 -- carried width info; meaning varies + // How many consecutive registers the syntax writes as a list, starting at + // `reg`: `{v0.16b, v1.16b}` is 2. Zero means the operand is a plain + // register. The count belongs to the instruction form rather than to the + // caller -- LD2 always names two -- so it comes from the encoding. + list_count: u8, // 1 } -#assert(size_of(Operand) == 10) +#assert(size_of(Operand) == 11) // ----------------------------------------------------------------------------- // Constructors -- generic @@ -191,6 +196,24 @@ op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 8} } +// Arrangement codes carried in Operand.size. Element views are odd and +// arrangements are multiples of 8, so the two can never be confused; 4 is the +// neutral "no vector shape" value every scalar class uses. +VSHAPE_NONE :: u8(4) +VSHAPE_8B :: u8(8) +VSHAPE_16B :: u8(16) +VSHAPE_4H :: u8(24) +VSHAPE_8H :: u8(32) +VSHAPE_2S :: u8(40) +VSHAPE_4S :: u8(48) +VSHAPE_1D :: u8(56) +VSHAPE_2D :: u8(64) +VSHAPE_1Q :: u8(72) +VSHAPE_ELEM_B :: u8(1) +VSHAPE_ELEM_H :: u8(3) +VSHAPE_ELEM_S :: u8(5) +VSHAPE_ELEM_D :: u8(7) + // ----------------------------------------------------------------------------- // NEON V-register arrangement builders. These take the register the caller // actually has, not its number: rebuilding one from `reg_hw` would relabel an @@ -245,10 +268,11 @@ op_v_2d :: #force_inline proc "contextless" (r: Register) -> Operand { op_v_1q :: #force_inline proc "contextless" (r: Register) -> Operand { return Operand{reg = r, kind = .REGISTER, size = 72} } -// A .16b register written as a one-element list, `{v1.16b}` (TBL/TBX). +// A run of `count` consecutive registers written as a list, `{v0.16b, v1.16b}`. +// `shape` is one of the VSHAPE_* codes. @(require_results) -op_v_list_16b :: #force_inline proc "contextless" (r: Register) -> Operand { - return Operand{reg = r, kind = .REGISTER, size = 80} +op_v_list :: #force_inline proc "contextless" (first: Register, shape, count: u8) -> Operand { + return Operand{reg = first, kind = .REGISTER, size = shape, list_count = count} } // Element-indexed V views (V0.B[i]/.H[i]/.S[i]/.D[i]). The element size rides diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 2dc3d8106..cd1da1b90 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -135,8 +135,9 @@ sbprint :: proc( strings.write_byte(sb, ',') if opts.space_after_comma { strings.write_byte(sb, ' ') } } - // A register the syntax writes as a list keeps its braces. - list := op.kind == .REGISTER && op.size == 80 + // A register the syntax writes as a list keeps its braces, and + // names every register in the run. + list := op.kind == .REGISTER && op.list_count > 0 switch { case lane_index: strings.write_byte(sb, '[') @@ -148,7 +149,16 @@ sbprint :: proc( case list: strings.write_byte(sb, '{') if opts.space_after_comma { strings.write_byte(sb, ' ') } - write_operand(sb, op, &display, opts) + for n in 0 ..< op.list_count { + if n > 0 { + strings.write_byte(sb, ',') + if opts.space_after_comma { strings.write_byte(sb, ' ') } + } + // The run is consecutive and wraps at v31. + member := op^ + member.reg = Register(reg_class(op.reg) | u16((reg_hw(op.reg) + n) & 0x1F)) + write_operand(sb, &member, &display, opts) + } if opts.space_after_comma { strings.write_byte(sb, ' ') } strings.write_byte(sb, '}') case: @@ -400,7 +410,6 @@ write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercas case 56: shape = "1d" case 64: shape = "2d" case 72: shape = "1q" - case 80: shape = "16b" // written as a list; the braces are added by the caller case 1: shape = "b" case 3: shape = "h" case 5: shape = "s" diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 7b71636c1..0e79e5ca1 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -708,56 +708,56 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, @@ -1743,10 +1743,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 8a7e69824..4ca2620c1 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -2426,15 +2426,15 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL - { .TBL, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .TBX - { .TBX, {.V_8B,.V_LIST_16B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_LIST_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .ZIP1 { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2552,67 +2552,67 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .LD1 - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD2 - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD3 - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD4 - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST1 - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST2 - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST3 - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST4 - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD1R - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD2R - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD3R - { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD4R - { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SUBR { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 2f2a391e6..c48c29090 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -3039,16 +3039,16 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_LIST_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_LIST_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_LIST_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_LIST_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, }, .ZIP1 = { @@ -3180,78 +3180,78 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .SUBR = { {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index a794f1ef0a4fbcb3b2ed455195660eb7a95ed472..c5e1fa11395db7ca00ff294a8d9796a3405bc5a8 100644 GIT binary patch delta 1582 zcmYk6Pfrs;7>8d54J8KK)UxevyRbx0(0DX7(PU5)FC_%Q#6Ki%qLH>F+9;q9lidRn zMQ-o`dhjAjVzS;mSU-W@yZ~7vM-C)<@IbP@^Uh2=JwCtLKEpnw;d*bl-uvltYVaxG zX9l31fS(1%t^hmrESgTO_E?KcIECi`V%!Ghwzw4i>Thh=nKXssbGE>pKJ0e9486m7Ry!vh%F-fD_Ksn7s&oeW@+{k*@Eb#p>BkUbsN?TH7er$aZCJwaX2F?u4S3p#W`*%KLE(4h;;oXF^c zMI)zn6a%BDrzAzACo+;0jh@IzQZ#xZBT31~sU;;NCn!fr5Wb{Nv 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b/core/rexcode/isa/arm64/tables/arm64.entries.bin index e237b743c2d8f03db5da9efae2d9087edf16c2d9..28afc0a6fcbcb470842ad653e76a4b22f2cfe42d 100644 GIT binary patch delta 1678 zcmYk7&ubGw6vtmD6%|brV!BN>S-VB?&;}14BqM<4i3#|6A&_k05HfY+~BJ3V& zm0F?De;@}BJqkGqg7M_lyHfVhV-G!e5E0_cn|YbJe)jXe-#4>lbG(;0-b;M?JLGKd z06={A8~p3{Q~ZQgDgfI%M`<=4Zcdc|e)!^1+)o83tn7Ip+0cOfWaYAVZ*!}38TdgD z&V?8KlB}xOzGm~Rd}9taXBR~mbRd>_^QasZmRV(jmhp9OxXj7|s;vn=F=EHCf#(x@YG%1%gOVPx6_Xch)>=`s-S3Gj zw`N-Mf_ktkFD)7DGk$Xp6pJ)_Z!vhIyaUC$smY_O;o7*k_1C;6UoqojEL{VrOBNB! zA!|s+iRF7-akG0a4daA?MUNN*vXxOt# zNOYJhPjX)@!+8=;c|4ka_BWA^M$v9Vjf`=A&IUP2zt1HOa=Oy6|F$>JeAkonjW65 zrqeL_tR#P_kL1Ui1s7Q=ogy}(*d@c#Fkoq%?S6SXdSPZAPWf#(>-1Ulj%6~L>f}^O zvggDc$I+}eVA*UIS$E`vmvGt}Vu|RQ_)Ftkuzh&oHHYR8o-}DWaur5(gO}Na#E?b)O$)0kpU`w0y$yWHh*jQ&p*Y>_=uH2e_ zp)RNoJL=N1!5)g6v!E?9_Q5iEt8@F>db!%+)vz`$Z+%;|)GJ0YhWQpiVi8%1O^}t@ zfXqdQYPZ3hSK(YlR%H_qnxMxB6ui#X7c+XmamxZ@K3hz=3Ck$wV37uVBZvN@77iV( zK50Sik-UZ-k(EupV&Gtbf?G29Ti*=l0+TCo?Ge?MEu);vwgaZt)jdLW{abS5q={=y zC@q<=Vio(QxXN}!2YQxK&cTXW?xAcFi7cGy<r;^>!Q#Ot8eoT`DeHMmd)) z0#obq^>^eVNso$^^G&WAGIpuhvy6fcx@waLauXr4aH=*Lvn()HVhbo&wv2MFF?Ig} zOmT&S!Z%iB3n=GVMmYz|YQUy?pCSvf9*`|CR^ps5b1O-(Y#{|*HULvxvCKDCW%DWL zY3se78lGt`=b@%P)&P&y#~Oo+m|M<~jcB{XmWR~xNp0`TyU`2N&*4 Operand_Category { case .W_REG, .X_REG, .WSP_REG, .XSP_REG, .B_REG, .H_REG, .S_REG, .D_REG, .Q_REG, .V_REG, .V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D, - .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_LIST_16B, + .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: return .REG case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_PAIR, .Z_QUAD: @@ -160,6 +160,38 @@ operand_param_count :: proc(t: a.Operand_Type) -> int { return 1 } +// How many consecutive registers this encoding's operand is written as, or 0 +// when it is a plain register. +list_count :: proc(e: a.Operand_Encoding) -> int { + #partial switch e { + case .VD_LIST1, .VN_LIST1: return 1 + case .VD_LIST2, .VN_LIST2: return 2 + case .VD_LIST3, .VN_LIST3: return 3 + case .VD_LIST4, .VN_LIST4: return 4 + } + return 0 +} + +// The VSHAPE_* constant naming this operand type's arrangement. +vshape_const :: proc(t: a.Operand_Type) -> string { + #partial switch t { + case .V_8B: return "VSHAPE_8B" + case .V_16B: return "VSHAPE_16B" + case .V_4H, .V_4H_FP16: return "VSHAPE_4H" + case .V_8H, .V_8H_FP16: return "VSHAPE_8H" + case .V_2S: return "VSHAPE_2S" + case .V_4S: return "VSHAPE_4S" + case .V_1D: return "VSHAPE_1D" + case .V_2D: return "VSHAPE_2D" + case .V_1Q: return "VSHAPE_1Q" + case .V_ELEM_B: return "VSHAPE_ELEM_B" + case .V_ELEM_H: return "VSHAPE_ELEM_H" + case .V_ELEM_S: return "VSHAPE_ELEM_S" + case .V_ELEM_D: return "VSHAPE_ELEM_D" + } + return "VSHAPE_NONE" +} + // A lane index prints glued to the register it indexes, so it is built with // op_lane_index rather than op_imm. Keyed on the ENCODING: EXT writes its byte // index as a plain immediate while sharing the .VEC_INDEX operand type. @@ -205,7 +237,6 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { case .V_1D: return "v1d" case .V_2D: return "v2d" case .V_1Q: return "v1q" - case .V_LIST_16B: return "vl16b" case .V_ELEM_B: return "veb" case .V_ELEM_H: return "veh" case .V_ELEM_S: return "ves" @@ -376,6 +407,12 @@ generate_proc_name :: proc(mnemonic: a.Mnemonic, sig: Operand_Signature) -> stri // ----------------------------------------------------------------------------- write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Operand_Encoding, names: [3]string) { + // A register the syntax writes as a list carries how many, which is a + // property of the form rather than of the operand type. + if n := list_count(enc); n > 0 { + fmt.sbprintf(sb, "op_v_list(%s, %s, %d)", names[0], vshape_const(t), n) + return + } #partial switch operand_category(t) { case .REG: #partial switch t { @@ -388,7 +425,6 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Opera case .V_1D: fmt.sbprintf(sb, "op_v_1d(%s)", names[0]) case .V_2D: fmt.sbprintf(sb, "op_v_2d(%s)", names[0]) case .V_1Q: fmt.sbprintf(sb, "op_v_1q(%s)", names[0]) - case .V_LIST_16B: fmt.sbprintf(sb, "op_v_list_16b(%s)", names[0]) case .V_ELEM_B: fmt.sbprintf(sb, "op_v_elem_b(%s)", names[0]) case .V_ELEM_H: fmt.sbprintf(sb, "op_v_elem_h(%s)", names[0]) case .V_ELEM_S: fmt.sbprintf(sb, "op_v_elem_s(%s)", names[0]) From 201dfdb454d6c91e8dd5037e94690a5f93831bd4 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 00:08:07 -0400 Subject: [PATCH 36/89] rexcode/arm32: every VFP and NEON register list disassembled wrong `vpush {d8, d9}` came out as `vpush {r2}`. VFP list operands kept only the 8-bit count from the encoding and stored it in a REG_LIST operand, whose immediate the printer reads as a GPR bitmask -- so the register bank was wrong, the start register was gone entirely, and the count was read as a bitmask. `vldm r0, {d1, d2, d3}` printed `{r1-r2}`. A list is now a register plus a shape: how many, and what the run steps by. VLDM/VSTM/VPUSH/VPOP recover their start register from Vd and their count from imm8. A GPR list stays a bitmask, since `{r4, lr}` is not a run at all. The NEON structure loads were wrong in a second way. VLD1-4/ST1-4 encode their register count in the type field at bits 11:8, not in imm8, so writing a count into the low byte overwrote size, alignment and Rm. Rm was left at 0, which is a register post-increment, where the plain form needs 0b1111; every one of those 23 forms encoded a writeback nobody asked for. The count now comes from the form, the encoding writes only Vd, and Rm is fixed in the pattern. Deriving those counts from llvm-mc rather than by hand turned up a dimension that was not modelled at all: the spaced forms step two registers at a time (`vld2.8 {d2, d4}`), and VLD1 has a to-all-lanes form written `{d2[]}`. All 31 A32 list forms are now byte-exact against llvm-mc, from 8. The arm32 sweep holds at 1656/1656. Still open here: those forms only exist for .8 data, because the size field at bits 7:6 is unencoded, and the writeback variants (`[r0]!`, `[r0], r1`) are not modelled. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 39 +++++++-- core/rexcode/isa/arm32/encoder.odin | 18 +++- core/rexcode/isa/arm32/encoding_types.odin | 12 +++ core/rexcode/isa/arm32/instructions.odin | 6 +- core/rexcode/isa/arm32/operands.odin | 21 ++++- core/rexcode/isa/arm32/printer.odin | 13 +++ .../isa/arm32/tablegen/encoding_table.odin | 46 +++++------ .../tablegen/generated/decode_tables.odin | 78 +++++++++--------- .../tablegen/generated/encode_tables.odin | 46 +++++------ .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10758 -> 10758 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38088 -> 38088 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38088 -> 38088 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3312 -> 3312 bytes 13 files changed, 181 insertions(+), 98 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 847beae09..0d22f2113 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -421,11 +421,40 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op case .VFP_IMM8: a := ((word >> 16) & 0xF) << 4 | (word & 0xF) return op_imm(i64(decode_vfp_imm8_f32(a))) - case .VFP_S_LIST, .VFP_D_LIST: - // Register count is encoded in bits 7..0 (count, not bitmask). Wrap - // as a REG_LIST so the encoder's shape_match for SPR_LIST/DPR_LIST - // accepts it; the encoder packs the same 8-bit count back out. - return op_reg_list(u16(word & 0xFF)) + case .NEON_D_LIST_1: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, false) + case .NEON_D_LIST_2: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 2, 1, false) + case .NEON_D_LIST_3: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 3, 1, false) + case .NEON_D_LIST_4: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 4, 1, false) + case .NEON_D_LIST_2X: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 2, 2, false) + case .NEON_D_LIST_3X: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 3, 2, false) + case .NEON_D_LIST_4X: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 4, 2, false) + case .NEON_D_LIST_ALL: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true) + case .VFP_S_LIST: + // {S, ...} -- imm8 counts the registers, and the run starts at Vd. + // Both halves matter: keeping only the count printed the wrong bank + // and the wrong registers. + n := ((word >> 12) & 0xF) << 1 | ((word >> 22) & 1) + return op_reg_run(Register(REG_SPR | u16(n)), u8(word & 0xFF)) + case .VFP_D_LIST: + // {D, ...} -- imm8 counts half-words here, two per D register. + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), u8((word & 0xFF) / 2)) // ---- Branch fields (decoded into RELATIVE) ---- case .BRANCH_24: diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index ec3f358a0..3613d619e 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -287,8 +287,10 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op case .DPR_ELEM: return op.kind == .REGISTER && is_dpr(op.reg) case .QPR_ELEM: return op.kind == .REGISTER && is_qpr(op.reg) case .SPR_ELEM: return op.kind == .REGISTER && is_spr(op.reg) - case .SPR_LIST, .DPR_LIST: - return op.kind == .REG_LIST || (op.kind == .REGISTER && (is_spr(op.reg) || is_dpr(op.reg))) + case .SPR_LIST: + return op.kind == .REGISTER && is_spr(op.reg) + case .DPR_LIST: + return op.kind == .REGISTER && is_dpr(op.reg) case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, @@ -495,8 +497,16 @@ pack_operand_inline :: #force_inline proc( case .NEON_OP_BIT: return (u32(op.immediate) & 1) << 5 // ---- VFP/NEON register lists (LDM/STM/PUSH/POP for FP regs) ------------ - case .VFP_S_LIST, .VFP_D_LIST: - return u32(op.immediate) & 0xFF + case .NEON_D_LIST_1, .NEON_D_LIST_2, .NEON_D_LIST_3, .NEON_D_LIST_4, .NEON_D_LIST_2X, .NEON_D_LIST_3X, .NEON_D_LIST_4X, .NEON_D_LIST_ALL: + // Only Vd; the count lives in the form's type field. + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 + case .VFP_S_LIST: + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF) + case .VFP_D_LIST: + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | ((u32(op.list.count) * 2) & 0xFF) // ---- Memory addressing composites -------------------------------------- case .MEM_IMM12_OFFSET: diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index f0563547f..cf60490c5 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -329,6 +329,18 @@ Operand_Encoding :: enum u8 { // ---- VFP / NEON list ---- VFP_S_LIST, // VLDM/VSTM single-prec list (8-bit count, start in Vd_S) VFP_D_LIST, // VLDM/VSTM double-prec list (8-bit count, start in Vd_D) + // NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list, + // the register count is part of the form's type field at bits 11:8, so the + // encoding writes only Vd; how many registers -- and whether the run steps + // by one or by two -- comes from the form. Verified against llvm-mc. + NEON_D_LIST_1, // {d2} + NEON_D_LIST_2, // {d2, d3} + NEON_D_LIST_3, // {d2, d3, d4} + NEON_D_LIST_4, // {d2, d3, d4, d5} + NEON_D_LIST_2X, // {d2, d4} -- spaced + NEON_D_LIST_3X, // {d2, d4, d6} -- spaced + NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced + NEON_D_LIST_ALL, // {d2[]} -- to all lanes // ---- Memory addressing composites ---- MEM_IMM12_OFFSET, // [Rn, #ยฑimm12] diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index bbe3959cc..5cb3ed3aa 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -25,7 +25,7 @@ Instruction_Flags :: bit_field u8 { // decode, because decode writes whole Instructions and unaligned stores are // expensive enough to outweigh writing more bytes. Instruction :: struct #align(64) { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 10 = 40 + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 11 = 44 mnemonic: Mnemonic, // 2 // cond, operand_count, mode, length and the two flag bits share one // 16-bit word -- together they need 13 bits, and spending six bytes on @@ -53,9 +53,9 @@ Instruction :: struct #align(64) { // every instruction did before this field existed. Set it and the encoder // picks the encoding for that type. dt: Data_Types, - // Spare, and free: a 48-byte struct straddles a cache line, so these 16 + // Spare, and free: a 48-byte struct straddles a cache line, so these // bytes cost nothing. New fields land here without changing the layout. - _: [16]u8, + _: [12]u8, } #assert(size_of(Instruction) == 64) #assert(align_of(Instruction) == 64) diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 2ce1f2d44..5950ff3b1 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -122,8 +122,20 @@ Operand :: struct #packed { }, kind: Operand_Kind, size: u8, + // How the syntax writes this register as a list. `count` 0 means a plain + // register. NEON structure loads also come in a spaced form that steps two + // registers at a time -- `{d2, d4}` -- and a to-all-lanes form written + // `{d2[]}`. A GPR list (`{r4, lr}`) is not a run at all and stays a + // bitmask under REG_LIST. + list: List_Shape, } -#assert(size_of(Operand) == 10) + +List_Shape :: bit_field u8 { + count: u8 | 3, // 0 = not a list, else 1..4 + stride: u8 | 3, // 1 for {d2, d3}, 2 for {d2, d4} + all_lanes: bool | 1, // `{d2[]}` -- loaded to every lane +} +#assert(size_of(Operand) == 11) // ---- Operand builders ------------------------------------------------------ @@ -157,6 +169,13 @@ op_rel_offset :: #force_inline proc "contextless" (off: i64) -> Operand { op_reg_list :: #force_inline proc "contextless" (mask: u16) -> Operand { return Operand{immediate = i64(mask), kind = .REG_LIST, size = 2} } + +// The head of a register list, written `{d1, d2, d3}` (stride 1) or +// `{d2, d4}` (stride 2). +@(require_results) +op_reg_run :: #force_inline proc "contextless" (first: Register, count: u8, stride: u8 = 1, all_lanes := false) -> Operand { + return Operand{reg = first, kind = .REGISTER, list = {count = count, stride = stride, all_lanes = all_lanes}} +} @(require_results) op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand { return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx} diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 9c7c290d3..7c9a0bad9 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -527,6 +527,19 @@ write_operand :: proc( case .NONE: return case .REGISTER: + // A VFP/NEON list is a contiguous run written in braces, and every + // register is named -- `{d1, d2, d3}`, not a range. + if op.list.count > 0 { + strings.write_string(sb, "{") + step := u16(max(op.list.stride, 1)) + for n in 0 ..< u16(op.list.count) { + if n > 0 { strings.write_string(sb, ", ") } + write_register(sb, Register(reg_class(op.reg) | ((reg_hw(op.reg) + n * step) & 0x1F))) + if op.list.all_lanes { strings.write_string(sb, "[]") } + } + strings.write_string(sb, "}") + return + } write_register(sb, op.reg) write_shift(sb, op.shift_type, op.shift_amt) if op.lane != 0 { diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 8f7a78e3a..f8f540c1a 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -2307,16 +2307,16 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // have distinct opcode bits; included as separate entries. .VLD1 = { // VLD1 multiple (1-reg list, type=0111, size=00/01/10/11, D form) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_1, .RN_A32, .NONE, .NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (2-reg list, type=1010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (3-reg list, type=0110) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (4-reg list, type=0010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane to all lanes (VLD1R): 1111 0100 1 D 10 Rn Vd 1100 size T a Rm // size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL, .RN_A32, .NONE, .NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector) {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 @@ -2324,10 +2324,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .VST1 = { // VST1 multiple (1-reg list) - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_1, .RN_A32, .NONE, .NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 @@ -2335,30 +2335,30 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits .VLD2 = { - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST2 = { - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD3 = { - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST3 = { - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD4 = { - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST4 = { - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VMULL / VMLAL / VMLSL (widening multiplies) ---- diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 959620224..7d4bace52 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -212,8 +212,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, @@ -262,8 +262,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -695,8 +695,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -820,30 +820,30 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -866,13 +866,13 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, @@ -1680,13 +1680,13 @@ DECODE_FORM_IDX := [1656]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, @@ -1711,7 +1711,7 @@ DECODE_FORM_IDX := [1656]u16{ 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 4, 7, + 0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 7, 4, 5, 8, 2, 6, 3, 3, 7, 6, 5, 4, 2, 8, 9, 0, 1, 2, 0, 1, 5, 3, 0, 2, 1, 4, 0, 1, 2, 13, 11, 12, 10, 14, 13, 15, 12, 14, 15, 13, 12, 17, 15, 16, 14, 15, 16, 17, 14, 4, @@ -1722,7 +1722,7 @@ DECODE_FORM_IDX := [1656]u16{ 3, 2, 0, 1, 2, 3, 3, 0, 3, 0, 3, 3, 2, 0, 1, 0, 2, 1, 1, 0, 0, 1, 2, 2, 3, 0, 2, 1, 0, 1, 2, 0, 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 5, 4, 6, 0, 2, 1, - 0, 1, 2, 2, 1, 0, 1, 0, 2, 0, 0, 0, 6, 7, 4, 5, + 0, 1, 2, 2, 1, 0, 1, 0, 2, 4, 0, 0, 0, 6, 5, 7, 1, 0, 2, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1892,10 +1892,10 @@ DECODE_BUCKET_LIST := [5379]u16{ 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 827, 825, 826, 830, 829, 828, 831, 832, 834, 833, 835, 836, 837, 838, 839, - 840, 841, 844, 843, 842, 845, 846, 847, 848, 849, 850, 851, 852, 853, 856, 854, - 855, 822, 823, 857, 858, 859, 862, 861, 860, 863, 865, 866, 864, 867, 868, 869, - 870, 871, 872, 874, 875, 873, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850, - 848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 862, 860, 861, + 840, 841, 844, 843, 842, 845, 847, 846, 848, 850, 849, 852, 853, 851, 856, 855, + 854, 822, 823, 857, 858, 859, 860, 862, 861, 863, 865, 866, 864, 867, 869, 868, + 871, 870, 872, 874, 873, 875, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850, + 848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 860, 862, 861, 863, 866, 865, 864, 867, 868, 869, 871, 870, 872, 874, 873, 875, 840, 841, 876, 877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 876, 877, 878, 879, 880, 889, 890, 881, 882, 888, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index ac5d48cde..e6885c0dd 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -1785,42 +1785,42 @@ ENCODE_FORMS := [1656]lib.Encoding{ { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VLD1 - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2 - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD3 - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4 - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST1 - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2 - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST3 - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST4 - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .AESE { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESD diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index b9c14de52346f6219d1b0e22336c394554d4eafe..4745e8f6ad5321d098a1804cf41d4dba0e2d8b9c 100644 GIT binary patch delta 84 zcmWm4HxYn9006<_`Zs_ADmo}}Kzwq}Q3nQ)LBkAs@WQb59`ca)E=(H>2M-rXfKNk%*N=8meK}ADLO~*jb#K_Fb!ggLl`_JfgTL@rnhLR%4+taPHpGiJSoeXcy?vX~4&puM<=%5L zSGqUu@Bf_V`Jd;U<9mJTnCH|nPpRAR+_Q)F7@f<1yaxa#FF>(YYbIfU6+lR*}N0H#j0A>kaux;u3dmMXsbX7$Q z?7zGGWbjyEe2kR_@Zn{!8Nq|FdH~=S1}k{kfV1H^g8#dj;VNDW3FfSq2BiCtTY>6P9gvb((D+NVe%%R+FdU8@-__!;JKU2!4VN0t$B6Z?FW%@fA) z%GiZV7+vGh8lE|EfnyQ|_=6jr(xWvjqv_67{t(NW)#LsshSRB4Lx~|2!LD3Fmo*Rj z{3nRvUEtXThWT!MT3~u^l@$_Vl8Y@Q4DgH;yZbCMR9@dVNkUmn0$`r2eN(Hkm4p|? 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z8Hq2EI*jrd9%Lq*BPiI`e^PL@#1{$UAv7m5NyIsBeTCH5W9$@5$#8a_HXICUy(xPC z!C#TbXzpNnL2v3I>igEE*k)GsB)-?r!n~JkVC`m213)*!ri1aGJ`SsqY_`qIfN~b+!*y6A%z63E`>Na}i(27WZ2%|)A<*-yQbG#2ogg~&LE*vrj2h%8y z-NGH@VkNNF7z{B!j9B=rQgBjY-blIijKmu-gNJ2!=CDEf>BQkF_9=psVjee`=i&3G zq=hE4_QwYHODXaRisGKEF<^VfrTA-m3YFM6DlvcK=UBh(=HcHh9LFVojn5i7huK;8 zfLwf@4I&?j0*FaXOUxD7HYVoKXwoOcA zMccmPw(a+vu8vEOOZ+d^pPjb72+Jlf@qg5Az6i5!UiZ1R_`uqj_8$q7N3D?~_IC#M z;RWo&Y>WXkxm|MdDEsu9!H*(W{GuzKKl&Vbly)AwoE6=0!R?0s!2ZR%AtH(2VOTUl zQ{rn1R;>Sm*zJvIEqdeM6wHE{d5a!jSwPz8sYzq71vd|S7ob3}ao{aii1*Dhh96S! zIf=I`_`Jk@3O*w+t$BezGh9maAU}RaIAw@jPMRqq2DGPVoQEgGY&Sc8W%+A2FIi59` Uk(Y%50@xT>8Q3@PXES620Q(vYJpcdz delta 68 zcmew$`9X3+5+gGg1KZ?OMnh&^2G+?l855bg8CWL&WmE@>Gj3LAGG%6FVPM}J&l=3g U%K!#!4D1Xn46K{?vl+4h0Q*7=Jpcdz From 2d85384a16a3c250a76f87e24579fa07350482ed Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 00:15:56 -0400 Subject: [PATCH 37/89] rexcode/arm32: merge the nine *_LANE mnemonics, and make the lane survive No assembler spells these `vld1_lane` or `vmov_lane`; they are `vld1` and `vmov` with a lane-indexed operand. All nine are now their base mnemonic. Merging them meant fixing what the separate names had been hiding. VLD1_LANE and VST1_LANE were byte-for-byte duplicates of forms VLD1 and VST1 already had, with a looser mask, and neither encoded the lane -- both used .VD_D, which has no lane field. `vld1.8 {d0[3]}, [r0]` disassembled as `vld1.8 d0, [r0]`. VMOV had the same shape: its own DPR_ELEM form dropped the index, while VMOV_LANE's three forms carried the per-size encodings that actually work. The lane-dropping forms are gone and the working ones now sit under the base mnemonic. VLD2-4/VST2-4's single-lane forms left bits 9:8 free, and that field is what separates VLD1/2/3/4 -- so VLD4's encoding matched VLD2's entry and disassembled as the wrong instruction. Two more things the lane could not survive. A lane index of 0 printed nothing, because 0 doubled as "no lane" -- `vmov.32 d0[0], r0` came out as `vmov.32 d0, r0`, a different instruction. And a lane inside a register list was dropped entirely, so `{d0[1], d1[1]}` printed as `{d0, d1}`. The whole set is byte-exact against llvm-mc: 27 single-lane forms across VLD1-4/VST1-4 and all three VMOV element sizes. arm32 is 1649/1649 on the sweep and 436/436 on the table checks, with the stale expectations for the forms this corrected updated to the verified values. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 27 + core/rexcode/isa/arm32/encoder.odin | 25 + core/rexcode/isa/arm32/encoding_types.odin | 8 + core/rexcode/isa/arm32/mnemonic_builders.odin | 44 +- core/rexcode/isa/arm32/mnemonics.odin | 5 +- core/rexcode/isa/arm32/operands.odin | 9 +- core/rexcode/isa/arm32/printer.odin | 10 +- .../isa/arm32/tablegen/encoding_table.odin | 80 +- .../tablegen/generated/decode_tables.odin | 1997 ++++++++--------- .../tablegen/generated/encode_tables.odin | 685 +++--- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10758 -> 10718 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38088 -> 37927 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4760 -> 4688 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38088 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3312 -> 3298 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 28 +- 20 files changed, 1444 insertions(+), 1474 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 0d22f2113..255009b26 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -445,6 +445,12 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op case .NEON_D_LIST_ALL: n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true) + case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + shift, mask, count := neon_lane_shape(enc) + op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) + op.list = {count = count, stride = 1} + return op case .VFP_S_LIST: // {S, ...} -- imm8 counts the registers, and the run starts at Vd. // Both halves matter: keeping only the count printed the wrong bank @@ -604,3 +610,24 @@ decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic if inst_info != nil { reserve(inst_info, len(inst_info) + n) } if label_defs != nil { reserve(label_defs, len(label_defs) + n) } } + +// The lane field's position and the list length for a NEON single-lane +// load/store. The lane sits just above the alignment bits, and how far above +// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32. +@(private="file", require_results) +neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) { + #partial switch e { + case .NEON_LANE_D_8: return 5, 0x7, 1 + case .NEON_LANE_D_16: return 6, 0x3, 1 + case .NEON_LANE_D_32: return 7, 0x1, 1 + case .NEON_LANE_D_8_2: return 5, 0x7, 2 + case .NEON_LANE_D_16_2: return 6, 0x3, 2 + case .NEON_LANE_D_32_2: return 7, 0x1, 2 + case .NEON_LANE_D_8_3: return 5, 0x7, 3 + case .NEON_LANE_D_16_3: return 6, 0x3, 3 + case .NEON_LANE_D_32_3: return 7, 0x1, 3 + case .NEON_LANE_D_8_4: return 5, 0x7, 4 + case .NEON_LANE_D_16_4: return 6, 0x3, 4 + case: return 7, 0x1, 4 + } +} diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 3613d619e..71735a8dd 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -501,6 +501,10 @@ pack_operand_inline :: #force_inline proc( // Only Vd; the count lives in the form's type field. n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 + case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4: + n := u32(reg_hw(op.reg)) & 0x1F + shift, mask, _ := neon_lane_shape(enc) + return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift case .VFP_S_LIST: n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF) @@ -855,3 +859,24 @@ write_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32, word: read_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u16 { return u16(code[offset+0]) | (u16(code[offset+1]) << 8) } + +// The lane field's position and the list length for a NEON single-lane +// load/store. The lane sits just above the alignment bits, and how far above +// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32. +@(private="file", require_results) +neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) { + #partial switch e { + case .NEON_LANE_D_8: return 5, 0x7, 1 + case .NEON_LANE_D_16: return 6, 0x3, 1 + case .NEON_LANE_D_32: return 7, 0x1, 1 + case .NEON_LANE_D_8_2: return 5, 0x7, 2 + case .NEON_LANE_D_16_2: return 6, 0x3, 2 + case .NEON_LANE_D_32_2: return 7, 0x1, 2 + case .NEON_LANE_D_8_3: return 5, 0x7, 3 + case .NEON_LANE_D_16_3: return 6, 0x3, 3 + case .NEON_LANE_D_32_3: return 7, 0x1, 3 + case .NEON_LANE_D_8_4: return 5, 0x7, 4 + case .NEON_LANE_D_16_4: return 6, 0x3, 4 + case: return 7, 0x1, 4 + } +} diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index cf60490c5..b977fe734 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -341,6 +341,14 @@ Operand_Encoding :: enum u8 { NEON_D_LIST_3X, // {d2, d4, d6} -- spaced NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced NEON_D_LIST_ALL, // {d2[]} -- to all lanes + // VLD1/VST1 single-lane: Vd plus the lane index, whose width and position + // follow the element size -- bits 7:5 for .8, 7:6 for .16, bit 7 for .32. + // Verified against llvm-mc. + // ..._N is how many registers the list holds: VLD2 writes `{d0[1], d1[1]}`. + NEON_LANE_D_8, NEON_LANE_D_16, NEON_LANE_D_32, + NEON_LANE_D_8_2, NEON_LANE_D_16_2, NEON_LANE_D_32_2, + NEON_LANE_D_8_3, NEON_LANE_D_16_3, NEON_LANE_D_32_3, + NEON_LANE_D_8_4, NEON_LANE_D_16_4, NEON_LANE_D_32_4, // ---- Memory addressing composites ---- MEM_IMM12_OFFSET, // [Rn, #ยฑimm12] diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index ff246fdd8..c8db616d1 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -737,14 +737,14 @@ inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, i inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } -inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } +inst_vmov_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} } inst_vmov_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} } emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } -emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) } +emit_vmov_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_qlane_r(dst, lane, src)) } emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } @@ -1000,8 +1000,6 @@ emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruc emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) } inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } -inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } -emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) } inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) } @@ -1102,22 +1100,6 @@ inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) } inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) } -inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) } -inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) } -inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) } -inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) } -inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) } -inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) } -inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) } -inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) } inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) } inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -2009,8 +1991,8 @@ inst_vcvtm :: inst_vcvtm_s_s emit_vcvtm :: emit_vcvtm_s_s inst_vcvtr :: inst_vcvtr_s_s emit_vcvtr :: emit_vcvtr_s_s -inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r, inst_vmov_qlane_qlane_r_r } -emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r, emit_vmov_qlane_qlane_r_r } +inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_qlane_r, inst_vmov_qlane_qlane_r_r } +emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_qlane_r, emit_vmov_qlane_qlane_r_r } inst_vmrs :: inst_vmrs_r emit_vmrs :: emit_vmrs_r inst_vmsr :: inst_vmsr_r @@ -2223,8 +2205,6 @@ inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane } emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane } inst_vswp :: inst_vswp_d_d emit_vswp :: emit_vswp_d_d -inst_vmov_lane :: inst_vmov_lane_dlane_r -emit_vmov_lane :: emit_vmov_lane_dlane_r inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem } emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem } inst_vld2 :: inst_vld2_dlist_mem @@ -2311,22 +2291,6 @@ inst_vld3r :: inst_vld3r_dlist_mem emit_vld3r :: emit_vld3r_dlist_mem inst_vld4r :: inst_vld4r_dlist_mem emit_vld4r :: emit_vld4r_dlist_mem -inst_vld1_lane :: inst_vld1_lane_dlane_mem -emit_vld1_lane :: emit_vld1_lane_dlane_mem -inst_vld2_lane :: inst_vld2_lane_dlist_mem -emit_vld2_lane :: emit_vld2_lane_dlist_mem -inst_vld3_lane :: inst_vld3_lane_dlist_mem -emit_vld3_lane :: emit_vld3_lane_dlist_mem -inst_vld4_lane :: inst_vld4_lane_dlist_mem -emit_vld4_lane :: emit_vld4_lane_dlist_mem -inst_vst1_lane :: inst_vst1_lane_dlane_mem -emit_vst1_lane :: emit_vst1_lane_dlane_mem -inst_vst2_lane :: inst_vst2_lane_dlist_mem -emit_vst2_lane :: emit_vst2_lane_dlist_mem -inst_vst3_lane :: inst_vst3_lane_dlist_mem -emit_vst3_lane :: emit_vst3_lane_dlist_mem -inst_vst4_lane :: inst_vst4_lane_dlist_mem -emit_vst4_lane :: emit_vst4_lane_dlist_mem inst_it :: inst_it_cond_imm4 emit_it :: emit_it_cond_imm4 inst_tt :: inst_tt_r_r diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index f922eeaa4..5494705f4 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -300,7 +300,7 @@ Mnemonic :: enum u16 { VSWP, // swap // Lane access - VMOV_LANE, // VMOV.

R, D[i] / VMOV.
D[i], R + // VMOV.
R, D[i] / VMOV.
D[i], R // Load/Store structures (NEON) VLD1, VLD2, VLD3, VLD4, @@ -349,9 +349,6 @@ Mnemonic :: enum u16 { VLD2R, VLD3R, VLD4R, // -- NEON single-element-lane load/store (lane form, not multi-vec) ----- - VLD1_LANE, VLD2_LANE, VLD3_LANE, VLD4_LANE, - VST1_LANE, VST2_LANE, VST3_LANE, VST4_LANE, - // -- VFP fixed-point conversions (with #fbits operand) ------------------ // VCVT.
Sd, Sd, #fbits family diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 5950ff3b1..4914fe0af 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -114,7 +114,10 @@ Operand :: struct #packed { shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain shift_amt: u8 | 5, // 0..31, or the Rs index for RSR lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM - // 3 bits spare + // Whether `lane` means anything. Lane 0 is a real index -- `d0[0]` + // is not `d0` -- so it cannot be spelled by lane == 0. + has_lane: bool | 1, + // 2 bits spare }, mem: Memory, immediate: i64, @@ -178,9 +181,9 @@ op_reg_run :: #force_inline proc "contextless" (first: Register, count: u8, stri } @(require_results) op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand { - return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx} + return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx, has_lane = true} } @(require_results) op_qpr_lane :: #force_inline proc "contextless" (q: Register, idx: u8) -> Operand { - return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx} + return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx, has_lane = true} } diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 7c9a0bad9..492e813ce 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -535,14 +535,20 @@ write_operand :: proc( for n in 0 ..< u16(op.list.count) { if n > 0 { strings.write_string(sb, ", ") } write_register(sb, Register(reg_class(op.reg) | ((reg_hw(op.reg) + n * step) & 0x1F))) - if op.list.all_lanes { strings.write_string(sb, "[]") } + // Every member of a single-lane list carries the index: + // `{d0[1], d1[1]}`. `{d0[]}` is the to-all-lanes form. + if op.list.all_lanes { + strings.write_string(sb, "[]") + } else if op.has_lane { + fmt.sbprintf(sb, "[%d]", op.lane) + } } strings.write_string(sb, "}") return } write_register(sb, op.reg) write_shift(sb, op.shift_type, op.shift_amt) - if op.lane != 0 { + if op.has_lane { fmt.sbprintf(sb, "[%d]", op.lane) } case .IMMEDIATE: diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index f8f540c1a..70ad7ed67 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1465,13 +1465,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // .8 / .16 / .32 selected by opc1+opc2 split bits in encoding. // 32-bit lane move (.32): {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, - {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV. Rt, Qd[i] {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, }, // ---- VMVN NEON modified immediate (op=1 form) ---- // bit 5 = 1 distinguishes VMVN from VMOV @@ -2318,9 +2320,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL, .RN_A32, .NONE, .NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector) - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, .VST1 = { // VST1 multiple (1-reg list) @@ -2329,36 +2331,54 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, // VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits .VLD2 = { {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST2 = { {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD3 = { {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST3 = { {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD4 = { {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST4 = { {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VMULL / VMLAL / VMLSL (widening multiplies) ---- @@ -2882,47 +2902,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1111 0100 1 D 10 Rn Vd size{2} N index_align Rm // N=00 VLDx1, 01 VLDx2, 10 VLDx3, 11 VLDx4 (x = 1..4) // VLD1_LANE Dd[i], [Rn]: size=00 (.8) 0xF4A00000, size=01 (.16) 0xF4A00400, size=10 (.32) 0xF4A00800 - .VLD1_LANE = { - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD2_LANE = { - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD3_LANE = { - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD4_LANE = { - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - // VST1/2/3/4 single-lane: bit 21 = 0 (store, not load) - .VST1_LANE = { - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST2_LANE = { - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST3_LANE = { - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST4_LANE = { - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, // ========================================================================= // ARMv8-M Security Extensions (TrustZone-M) -- TT / TTT / TTA / TTAT @@ -3569,11 +3548,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5. // VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on // the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size. - .VMOV_LANE = { - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, - }, // MVE (M-profile vector) multiply-subtract-across-vector reduce, halving // complex add (saturating), and complex multiply-accumulate. T32; the diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 7d4bace52..11bf858cc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1656]lib.Decode_Entry{ +DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -212,11 +212,11 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -262,13 +262,13 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -370,40 +370,40 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -434,12 +434,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -467,8 +467,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -518,8 +518,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -535,8 +535,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -583,8 +583,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -597,8 +597,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -684,135 +684,135 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 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0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -820,23 +820,23 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -851,40 +851,34 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1037,30 +1031,29 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1094,11 +1087,11 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, @@ -1132,12 +1125,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1173,12 +1166,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1280,8 +1273,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1532,12 +1525,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1668,7 +1661,7 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1656]u16{ +DECODE_FORM_IDX := [1649]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1681,102 +1674,102 @@ DECODE_FORM_IDX := [1656]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, - 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, + 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 25, 24, 22, 21, 23, 0, 0, - 0, 0, 10, 11, 15, 20, 18, 17, 14, 12, 10, 11, 19, 13, 16, 0, - 6, 0, 0, 2, 6, 5, 8, 7, 9, 4, 3, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 23, 25, 22, 21, 0, 0, + 0, 0, 11, 10, 19, 20, 17, 18, 10, 12, 14, 16, 13, 15, 11, 0, + 6, 0, 0, 7, 4, 3, 9, 2, 6, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 6, 1, 2, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 3, 1, 1, 3, 1, 3, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, - 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, + 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, + 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, - 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, + 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 7, 4, - 5, 8, 2, 6, 3, 3, 7, 6, 5, 4, 2, 8, 9, 0, 1, 2, - 0, 1, 5, 3, 0, 2, 1, 4, 0, 1, 2, 13, 11, 12, 10, 14, - 13, 15, 12, 14, 15, 13, 12, 17, 15, 16, 14, 15, 16, 17, 14, 4, - 3, 1, 2, 5, 0, 3, 2, 1, 0, 2, 3, 1, 5, 2, 3, 4, - 0, 1, 1, 0, 4, 5, 2, 3, 0, 1, 1, 0, 3, 0, 2, 1, - 2, 1, 3, 4, 5, 0, 0, 3, 1, 5, 4, 2, 3, 2, 4, 1, - 0, 2, 4, 1, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 3, 2, - 3, 2, 0, 1, 2, 3, 3, 0, 3, 0, 3, 3, 2, 0, 1, 0, - 2, 1, 1, 0, 0, 1, 2, 2, 3, 0, 2, 1, 0, 1, 2, 0, - 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 5, 4, 6, 0, 2, 1, - 0, 1, 2, 2, 1, 0, 1, 0, 2, 4, 0, 0, 0, 6, 5, 7, - 1, 0, 2, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 10, 0, 2, 1, 3, 1, 2, 0, 3, 0, 0, 0, 9, 5, 4, + 7, 8, 3, 2, 6, 5, 7, 6, 3, 4, 8, 9, 2, 1, 0, 0, + 1, 2, 0, 1, 3, 5, 4, 2, 0, 2, 1, 11, 10, 13, 12, 12, + 15, 13, 14, 14, 12, 15, 13, 16, 14, 17, 15, 17, 16, 14, 15, 5, + 2, 1, 0, 4, 3, 1, 0, 3, 2, 2, 1, 3, 1, 5, 4, 0, + 2, 3, 1, 3, 2, 4, 0, 5, 1, 0, 0, 1, 1, 0, 3, 2, + 5, 2, 1, 0, 4, 3, 1, 0, 2, 3, 4, 5, 2, 1, 0, 4, + 3, 2, 1, 0, 4, 3, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, + 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 0, 2, 0, + 2, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, + 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, + 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, + 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, - 3, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, - 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, - 0, 0, 0, 0, 0, 1, 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, - 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, - 1, 0, 1, 0, 4, 2, 1, 3, 2, 0, 1, 27, 2, 2, 0, 1, - 0, 1, 0, 0, 0, 0, 5, 26, 0, 1, 1, 0, 0, 0, 3, 3, - 2, 2, 2, 0, 1, 0, 1, 2, 2, 0, 1, 1, 0, 0, 1, 3, - 1, 0, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, - 0, 1, 1, 0, 5, 2, 3, 3, 2, 1, 0, 1, 0, 1, 0, 0, - 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 2, 0, 1, - 19, 18, 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, - 7, 8, 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 0, 1, 0, 4, 0, 1, 15, 16, 3, 2, 0, 0, 1, 0, - 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, - 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, - 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, - 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 4, 0, 0, 0, 0, 7, 29, 28, 2, 2, 2, 2, 0, 0, 0, - 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, - 8, 8, 2, 10, 10, 12, 12, 8, 4, 6, 0, 0, 2, 2, 2, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 4, 3, 6, 4, 8, 9, 7, 0, 0, 7, 8, 7, 6, 7, 7, - 7, 7, 4, 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, - 1, 1, 10, 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, - 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, + 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 4, 32, + 31, 3, 2, 1, 0, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, + 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, + 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 0, 1, 2, 2, 0, + 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, + 3, 2, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, + 0, 1, 0, 1, 1, 0, 2, 0, 1, 19, 18, 20, 17, 14, 12, 9, + 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, 0, 1, 0, 1, 2, + 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 4, 0, + 1, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, + 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, + 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, + 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, + 27, 28, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, + 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, + 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, + 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, + 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, + 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, + 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, + 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, + 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, - 1, 0, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, - 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, - 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 2, 2, 2, 2, 2, - 2, 0, 0, 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, - 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, - 3, 8, 8, 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, 3, 3, 3, - 2, 0, 2, 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, - 4, 4, 4, 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, - 1, 9, 11, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, - 0, 1, 2, 2, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, + 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, + 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, + 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, + 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, + 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, + 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, + 2, } @(rodata) -DECODE_BUCKET_LIST := [5379]u16{ +DECODE_BUCKET_LIST := [5359]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1892,228 +1885,226 @@ DECODE_BUCKET_LIST := [5379]u16{ 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 827, 825, 826, 830, 829, 828, 831, 832, 834, 833, 835, 836, 837, 838, 839, - 840, 841, 844, 843, 842, 845, 847, 846, 848, 850, 849, 852, 853, 851, 856, 855, - 854, 822, 823, 857, 858, 859, 860, 862, 861, 863, 865, 866, 864, 867, 869, 868, - 871, 870, 872, 874, 873, 875, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850, - 848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 860, 862, 861, - 863, 866, 865, 864, 867, 868, 869, 871, 870, 872, 874, 873, 875, 840, 841, 876, - 877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 876, 877, 878, 879, - 880, 889, 890, 881, 882, 888, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900, - 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 913, 914, 915, 916, - 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, 927, 928, 929, 930, 931, 932, - 933, 934, 935, 936, 937, 938, 939, 935, 940, 941, 942, 943, 944, 945, 946, 947, - 948, 949, 945, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, - 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975, 958, 960, 976, - 976, 977, 978, 966, 977, 978, 973, 979, 980, 979, 981, 982, 983, 981, 982, 983, - 984, 982, 984, 982, 985, 987, 982, 986, 989, 987, 985, 982, 988, 986, 989, 984, - 982, 984, 982, 990, 982, 991, 992, 990, 982, 991, 984, 982, 984, 982, 993, 982, - 994, 993, 982, 994, 984, 982, 984, 982, 995, 996, 995, 996, 995, 996, 995, 996, - 995, 996, 995, 996, 995, 996, 995, 996, 995, 996, 995, 996, 995, 996, 995, 996, - 995, 996, 995, 996, 995, 996, 995, 996, 995, 997, 995, 997, 995, 997, 995, 997, - 995, 997, 995, 997, 995, 997, 995, 997, 995, 997, 995, 997, 995, 997, 995, 997, - 995, 997, 995, 997, 995, 997, 995, 997, 998, 999, 1000, 1013, 1014, 1001, 1002, 1013, - 1014, 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, 1014, 1001, 1002, 1015, - 1013, 1014, 1003, 1004, 998, 999, 1000, 1017, 1016, 1013, 1018, 1014, 1001, 1019, 1002, 1021, - 1020, 1013, 1022, 1014, 1003, 1023, 1004, 1005, 1006, 1007, 1008, 1009, 1010, 1011, 1012, 1013, - 1014, 1001, 1002, 1015, 1013, 1014, 1003, 1004, 1024, 1025, 1026, 1027, 1001, 1002, 1024, 1025, - 1029, 1028, 1003, 1004, 1030, 1031, 1032, 1033, 1034, 1035, 1024, 1025, 1027, 1026, 1001, 1002, - 1037, 1036, 1024, 1025, 1029, 1028, 1003, 1004, 1024, 1025, 1027, 1026, 1001, 1002, 1024, 1025, - 1028, 1029, 1003, 1004, 1030, 1031, 1032, 1033, 1034, 1035, 1024, 1025, 1026, 1027, 1001, 1002, - 1024, 1025, 1029, 1028, 1003, 1004, 1013, 1014, 1038, 1039, 1013, 1014, 1040, 1041, 1042, 1043, - 1013, 1014, 1013, 1014, 1013, 1014, 1038, 1039, 1013, 1014, 1041, 1040, 1013, 1014, 1013, 1014, - 1024, 1025, 1039, 1038, 1024, 1025, 1041, 1040, 1024, 1025, 1024, 1025, 1024, 1025, 1039, 1038, - 1024, 1025, 1040, 1041, 1024, 1025, 1024, 1025, 1044, 1045, 1046, 1047, 1048, 1050, 1049, 1051, - 1052, 1053, 1013, 1055, 1054, 1057, 1056, 1014, 1058, 1059, 1060, 1061, 1062, 1049, 1050, 1063, - 1013, 1064, 1065, 1067, 1066, 1014, 1068, 1059, 1069, 1061, 1045, 1046, 1070, 1071, 1072, 1073, - 1050, 1049, 1051, 1074, 1013, 1075, 1076, 1078, 1077, 1014, 1058, 1059, 1060, 1061, 1050, 1049, - 1063, 1079, 1080, 1013, 1082, 1081, 1083, 1084, 1014, 1068, 1059, 1069, 1061, 1047, 1085, 1048, - 1050, 1049, 1051, 1052, 1053, 1013, 1055, 1054, 1057, 1056, 1014, 1058, 1059, 1060, 1061, 1050, - 1049, 1063, 1013, 1064, 1065, 1066, 1067, 1014, 1068, 1059, 1069, 1061, 1070, 1071, 1085, 1072, - 1073, 1050, 1049, 1051, 1074, 1013, 1075, 1076, 1077, 1078, 1014, 1058, 1059, 1060, 1061, 1050, - 1049, 1063, 1079, 1080, 1013, 1081, 1082, 1084, 1083, 1014, 1068, 1059, 1069, 1061, 1086, 1087, - 1088, 1089, 1091, 1090, 1092, 1051, 1093, 1094, 1095, 1058, 1059, 1060, 1061, 1063, 1096, 1097, - 1099, 1098, 1100, 1101, 1068, 1059, 1069, 1061, 1051, 1102, 1103, 1105, 1104, 1106, 1107, 1058, - 1059, 1060, 1061, 1110, 1108, 1109, 1111, 1112, 1114, 1113, 1115, 1116, 1118, 1117, 1120, 1119, - 1121, 1122, 1123, 1124, 1126, 1125, 1127, 1128, 1130, 1129, 1132, 1131, 1135, 1133, 1134, 1136, - 1151, 1144, 1150, 1140, 1147, 1139, 1148, 1137, 1153, 1152, 1141, 1149, 1146, 1142, 1143, 1145, - 1138, 1155, 1154, 1156, 1157, 1158, 1160, 1161, 1159, 1162, 1163, 1164, 1165, 1166, 1167, 1168, - 1169, 1170, 1173, 1172, 1171, 1175, 1174, 1177, 1176, 1178, 1179, 1063, 1068, 1059, 1069, 1061, - 1086, 1087, 1089, 1088, 1090, 1091, 1092, 1180, 1051, 1093, 1094, 1095, 1058, 1059, 1060, 1061, - 1063, 1096, 1097, 1098, 1099, 1100, 1101, 1068, 1059, 1069, 1061, 1181, 1182, 1051, 1102, 1103, - 1105, 1104, 1107, 1106, 1058, 1059, 1060, 1061, 1183, 1110, 1109, 1108, 1111, 1112, 1114, 1113, - 1115, 1116, 1117, 1118, 1119, 1120, 1122, 1121, 1123, 1124, 1125, 1126, 1128, 1127, 1129, 1130, - 1131, 1132, 1133, 1134, 1135, 1144, 1145, 1143, 1149, 1150, 1148, 1151, 1152, 1153, 1147, 1142, - 1140, 1139, 1137, 1136, 1138, 1141, 1146, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1163, - 1162, 1164, 1165, 1167, 1166, 1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, - 1179, 1063, 1068, 1059, 1069, 1061, 1013, 1014, 1184, 1013, 1014, 1184, 1013, 1014, 1184, 1013, - 1014, 1184, 1013, 1014, 1184, 1013, 1014, 1184, 1013, 1014, 1184, 1013, 1014, 1184, 1184, 1184, - 1184, 1184, 1184, 1184, 1184, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, - 1195, 1196, 1197, 1198, 1199, 1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, - 1211, 1212, 1213, 1214, 1215, 1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, - 1227, 1228, 1229, 1230, 1231, 1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, - 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, - 1259, 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, - 1275, 1276, 1277, 1278, 1279, 1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, - 1291, 1292, 1293, 1294, 1295, 1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, - 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, - 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, - 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, - 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, - 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1383, 1384, 1385, 1386, - 1387, 1388, 1389, 1390, 1391, 1392, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1354, 1355, - 1401, 1402, 1403, 1359, 1360, 1404, 1405, 1406, 1407, 1408, 1369, 1409, 1410, 1379, 1378, 1380, - 1354, 1355, 1359, 1360, 1361, 1362, 1363, 1364, 1366, 1365, 1367, 1369, 1370, 1371, 1372, 1373, - 1374, 1375, 1376, 1377, 1379, 1378, 1380, 1411, 1412, 1413, 1354, 1355, 1359, 1360, 1414, 1369, - 1409, 1410, 1379, 1378, 1380, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425, - 1426, 1427, 1428, 1429, 1430, 1431, 1432, 1433, 1434, 1435, 1436, 1437, 1438, 1439, 1440, 1441, - 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1453, 1454, 1455, 1456, 1457, - 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468, 1469, 1470, 1471, 1472, 1473, - 1474, 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, 1483, 1484, 1485, 1486, 1487, 1488, 1489, - 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, 1503, 1504, 1505, - 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1516, 1517, 1518, 1519, 1520, 1521, - 1522, 1524, 1523, 1526, 1525, 1528, 1527, 1529, 1530, 1246, 1247, 1248, 1249, 1250, 1251, 1531, - 1532, 1533, 1534, 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1258, 1259, - 1260, 1261, 1262, 1263, 1546, 1547, 1548, 1268, 1269, 1270, 1549, 1277, 1278, 1279, 1280, 1281, - 1282, 1284, 1285, 1550, 1286, 1287, 1551, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295, 1296, - 1297, 1298, 1552, 1553, 1554, 1555, 1556, 1557, 1558, 1559, 1299, 1560, 1300, 1301, 1302, 1303, - 1561, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1315, 1316, 1317, 1318, - 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1331, 1332, 1333, 1334, - 1335, 1336, 1337, 1562, 1563, 1564, 1565, 1566, 1567, 1568, 1569, 1340, 1341, 1342, 1343, 1570, - 1571, 1572, 1573, 1574, 1575, 1576, 1576, 1577, 1577, 1578, 1578, 1579, 1580, 1581, 1582, 1583, - 1583, 1584, 1584, 1585, 1585, 1586, 1586, 1587, 1588, 1589, 1590, 1591, 1592, 1593, 1594, 1595, - 1596, 1597, 1598, 1599, 1600, 1601, 1602, 1603, 1604, 1605, 1606, 1607, 1608, 1609, 1610, 1610, - 1611, 1612, 1613, 1614, 1615, 1616, 1617, 1618, 1619, 1619, 1620, 1620, 1621, 1621, 1622, 1622, - 1623, 1623, 1624, 1624, 1625, 1625, 1626, 1626, 1627, 1627, 1628, 1628, 1629, 1630, 1631, 1632, - 1633, 1634, 1635, 1636, 1637, 1638, 1639, 1640, 1641, 1642, 1643, 1644, 1645, 1646, 1647, 1648, - 1649, 1650, 1650, 1651, 1651, 1652, 1652, 1652, 1653, 1654, 1652, 1655, 1655, 1193, 1194, 1195, - 1196, 1201, 1207, 1197, 1206, 1207, 1206, 1203, 1202, 1203, 1200, 1202, 1190, 1191, 1198, 1207, - 1186, 1187, 1188, 1189, 1192, 1206, 1207, 1206, 1205, 1204, 1199, 1205, 1204, 1207, 1206, 1207, - 1185, 1206, 1207, 1206, 1207, 1206, 1220, 1219, 1212, 1220, 1219, 1226, 1226, 1208, 1209, 1210, - 1211, 1217, 1216, 1225, 1208, 1209, 1210, 1211, 1216, 1217, 1225, 1218, 1218, 1221, 1213, 1221, - 1215, 1223, 1223, 1224, 1224, 1214, 1222, 1222, 1237, 1244, 1245, 1237, 1241, 1243, 1240, 1242, - 1237, 1244, 1245, 1227, 1228, 1229, 1230, 1237, 1241, 1243, 1240, 1242, 1244, 1245, 1241, 1243, - 1240, 1242, 1244, 1245, 1241, 1243, 1240, 1242, 1227, 1228, 1229, 1230, 1234, 1235, 1236, 1239, - 1231, 1232, 1233, 1238, 1234, 1235, 1236, 1239, 1231, 1232, 1233, 1238, 1264, 1268, 1269, 1272, - 1283, 1284, 1285, 1286, 1297, 1298, 1301, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, - 1323, 1324, 1325, 1348, 1264, 1268, 1269, 1271, 1283, 1284, 1285, 1286, 1298, 1301, 1304, 1305, - 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1348, 1268, 1269, 1272, 1283, 1284, - 1285, 1286, 1298, 1301, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, - 1348, 1254, 1255, 1256, 1257, 1268, 1269, 1270, 1271, 1283, 1284, 1285, 1286, 1287, 1296, 1298, - 1301, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1348, 1268, 1269, - 1272, 1284, 1285, 1286, 1297, 1298, 1301, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, - 1323, 1324, 1325, 1344, 1348, 1268, 1269, 1271, 1284, 1285, 1286, 1298, 1301, 1304, 1305, 1308, - 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1344, 1348, 1268, 1269, 1272, 1284, 1285, - 1286, 1298, 1301, 1304, 1305, 1308, 1309, 1310, 1311, 1312, 1313, 1322, 1323, 1324, 1325, 1344, - 1348, 1254, 1255, 1256, 1257, 1268, 1269, 1270, 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1555, 1556, 1557, 1558, 1565, 1568, 1272, 1273, 1274, 1275, + 1283, 1284, 1285, 1286, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, + 1312, 1313, 1314, 1559, 1560, 1561, 1562, 1336, 1564, 1566, 1568, 1545, 1546, 1547, 1548, 1554, + 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1241, 1242, 1243, + 1244, 1253, 1254, 1255, 1256, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, + 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1530, 1531, 1251, 1252, 1270, 1271, 1281, 1282, 1287, + 1288, 1545, 1546, 1547, 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, + 1555, 1556, 1557, 1558, 1564, 1566, 1568, 1542, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, + 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, + 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, + 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, + 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1542, 1543, + 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, + 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1544, 1293, 1553, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, + 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, + 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, + 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, + 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, + 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2189,576 +2180,576 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x45 = { 1838, 2}, 0x46 = { 1840, 1}, 0x47 = { 1841, 1}, - 0x48 = { 1842, 16}, - 0x49 = { 1858, 1}, - 0x4A = { 1859, 20}, - 0x4B = { 1879, 1}, - 0x4C = { 1880, 16}, - 0x4D = { 1896, 2}, - 0x4E = { 1898, 20}, - 0x4F = { 1918, 1}, - 0x50 = { 1919, 1}, - 0x51 = { 1920, 1}, - 0x52 = { 1921, 1}, - 0x53 = { 1922, 1}, - 0x54 = { 1923, 1}, - 0x55 = { 1924, 1}, - 0x56 = { 1925, 1}, - 0x57 = { 1926, 6}, - 0x58 = { 1932, 1}, - 0x59 = { 1933, 1}, - 0x5A = { 1934, 1}, - 0x5B = { 1935, 1}, - 0x5C = { 1936, 1}, - 0x5D = { 1937, 3}, - 0x5E = { 1940, 1}, - 0x5F = { 1941, 1}, - 0x61 = { 1942, 6}, - 0x62 = { 1948, 6}, - 0x63 = { 1954, 6}, - 0x65 = { 1960, 6}, - 0x66 = { 1966, 6}, - 0x67 = { 1972, 6}, - 0x68 = { 1978, 5}, - 0x6A = { 1983, 4}, - 0x6B = { 1987, 5}, - 0x6C = { 1992, 2}, - 0x6E = { 1994, 4}, - 0x6F = { 1998, 5}, - 0x70 = { 2003, 9}, - 0x71 = { 2012, 2}, - 0x73 = { 2014, 1}, - 0x74 = { 2015, 5}, - 0x75 = { 2020, 7}, - 0x78 = { 2027, 3}, - 0x79 = { 2030, 1}, - 0x7A = { 2031, 1}, - 0x7B = { 2032, 1}, - 0x7C = { 2033, 3}, - 0x7D = { 2036, 3}, - 0x7E = { 2039, 1}, - 0x7F = { 2040, 2}, - 0x80 = { 2042, 1}, - 0x81 = { 2043, 2}, - 0x82 = { 2045, 1}, - 0x83 = { 2046, 2}, - 0x84 = { 2048, 1}, - 0x85 = { 2049, 1}, - 0x86 = { 2050, 1}, - 0x87 = { 2051, 1}, - 0x88 = { 2052, 2}, - 0x89 = { 2054, 3}, - 0x8A = { 2057, 2}, - 0x8B = { 2059, 4}, - 0x8C = { 2063, 1}, - 0x8D = { 2064, 1}, - 0x8E = { 2065, 1}, - 0x8F = { 2066, 1}, - 0x90 = { 2067, 1}, - 0x91 = { 2068, 2}, - 0x92 = { 2070, 2}, - 0x93 = { 2072, 2}, - 0x94 = { 2074, 1}, - 0x95 = { 2075, 1}, - 0x96 = { 2076, 1}, - 0x97 = { 2077, 1}, - 0x98 = { 2078, 1}, - 0x99 = { 2079, 2}, - 0x9A = { 2081, 1}, - 0x9B = { 2082, 2}, - 0x9C = { 2084, 1}, - 0x9D = { 2085, 1}, - 0x9E = { 2086, 1}, - 0x9F = { 2087, 1}, - 0xA0 = { 2088, 2}, - 0xA1 = { 2090, 2}, - 0xA2 = { 2092, 2}, - 0xA3 = { 2094, 2}, - 0xA4 = { 2096, 2}, - 0xA5 = { 2098, 2}, - 0xA6 = { 2100, 2}, - 0xA7 = { 2102, 2}, - 0xA8 = { 2104, 2}, - 0xA9 = { 2106, 2}, - 0xAA = { 2108, 2}, - 0xAB = { 2110, 2}, - 0xAC = { 2112, 2}, - 0xAD = { 2114, 2}, - 0xAE = { 2116, 2}, - 0xAF = { 2118, 2}, - 0xB0 = { 2120, 2}, - 0xB1 = { 2122, 2}, - 0xB2 = { 2124, 2}, - 0xB3 = { 2126, 2}, - 0xB4 = { 2128, 2}, - 0xB5 = { 2130, 2}, - 0xB6 = { 2132, 2}, - 0xB7 = { 2134, 2}, - 0xB8 = { 2136, 2}, - 0xB9 = { 2138, 2}, - 0xBA = { 2140, 2}, - 0xBB = { 2142, 2}, - 0xBC = { 2144, 2}, - 0xBD = { 2146, 2}, - 0xBE = { 2148, 2}, - 0xBF = { 2150, 2}, - 0xC0 = { 2152, 7}, - 0xC1 = { 2159, 4}, - 0xC2 = { 2163, 12}, - 0xC3 = { 2175, 5}, - 0xC4 = { 2180, 11}, - 0xC5 = { 2191, 8}, - 0xC6 = { 2199, 12}, - 0xC7 = { 2211, 5}, - 0xC8 = { 2216, 6}, - 0xC9 = { 2222, 6}, - 0xCA = { 2228, 12}, - 0xCB = { 2240, 8}, - 0xCC = { 2248, 6}, - 0xCD = { 2254, 6}, - 0xCE = { 2260, 12}, - 0xCF = { 2272, 6}, - 0xD0 = { 2278, 4}, - 0xD1 = { 2282, 4}, - 0xD2 = { 2286, 4}, - 0xD3 = { 2290, 2}, - 0xD4 = { 2292, 4}, - 0xD5 = { 2296, 4}, - 0xD6 = { 2300, 2}, - 0xD7 = { 2302, 2}, - 0xD8 = { 2304, 4}, - 0xD9 = { 2308, 4}, - 0xDA = { 2312, 2}, - 0xDB = { 2314, 2}, - 0xDC = { 2316, 4}, - 0xDD = { 2320, 4}, - 0xDE = { 2324, 2}, - 0xDF = { 2326, 2}, - 0xE0 = { 2328, 20}, - 0xE1 = { 2348, 14}, - 0xE2 = { 2362, 20}, - 0xE3 = { 2382, 15}, - 0xE4 = { 2397, 18}, - 0xE5 = { 2415, 13}, - 0xE6 = { 2428, 19}, - 0xE7 = { 2447, 15}, - 0xE8 = { 2462, 15}, - 0xE9 = { 2477, 11}, - 0xEA = { 2488, 11}, - 0xEB = { 2499, 77}, - 0xEC = { 2576, 16}, - 0xED = { 2592, 11}, - 0xEE = { 2603, 13}, - 0xEF = { 2616, 78}, - 0xF0 = { 2694, 3}, - 0xF1 = { 2697, 3}, - 0xF2 = { 2700, 3}, - 0xF3 = { 2703, 3}, - 0xF4 = { 2706, 3}, - 0xF5 = { 2709, 3}, - 0xF6 = { 2712, 3}, - 0xF7 = { 2715, 3}, - 0xF8 = { 2718, 1}, - 0xF9 = { 2719, 1}, - 0xFA = { 2720, 1}, - 0xFB = { 2721, 1}, - 0xFC = { 2722, 1}, - 0xFD = { 2723, 1}, - 0xFE = { 2724, 1}, - 0xFF = { 2725, 1}, + 0x48 = { 1842, 13}, + 0x49 = { 1855, 1}, + 0x4A = { 1856, 17}, + 0x4B = { 1873, 1}, + 0x4C = { 1874, 13}, + 0x4D = { 1887, 2}, + 0x4E = { 1889, 17}, + 0x4F = { 1906, 1}, + 0x50 = { 1907, 1}, + 0x51 = { 1908, 1}, + 0x52 = { 1909, 1}, + 0x53 = { 1910, 1}, + 0x54 = { 1911, 1}, + 0x55 = { 1912, 1}, + 0x56 = { 1913, 1}, + 0x57 = { 1914, 6}, + 0x58 = { 1920, 1}, + 0x59 = { 1921, 1}, + 0x5A = { 1922, 1}, + 0x5B = { 1923, 1}, + 0x5C = { 1924, 1}, + 0x5D = { 1925, 3}, + 0x5E = { 1928, 1}, + 0x5F = { 1929, 1}, + 0x61 = { 1930, 6}, + 0x62 = { 1936, 6}, + 0x63 = { 1942, 6}, + 0x65 = { 1948, 6}, + 0x66 = { 1954, 6}, + 0x67 = { 1960, 6}, + 0x68 = { 1966, 5}, + 0x6A = { 1971, 4}, + 0x6B = { 1975, 5}, + 0x6C = { 1980, 2}, + 0x6E = { 1982, 4}, + 0x6F = { 1986, 5}, + 0x70 = { 1991, 9}, + 0x71 = { 2000, 2}, + 0x73 = { 2002, 1}, + 0x74 = { 2003, 5}, + 0x75 = { 2008, 7}, + 0x78 = { 2015, 3}, + 0x79 = { 2018, 1}, + 0x7A = { 2019, 1}, + 0x7B = { 2020, 1}, + 0x7C = { 2021, 3}, + 0x7D = { 2024, 3}, + 0x7E = { 2027, 1}, + 0x7F = { 2028, 2}, + 0x80 = { 2030, 1}, + 0x81 = { 2031, 2}, + 0x82 = { 2033, 1}, + 0x83 = { 2034, 2}, + 0x84 = { 2036, 1}, + 0x85 = { 2037, 1}, + 0x86 = { 2038, 1}, + 0x87 = { 2039, 1}, + 0x88 = { 2040, 2}, + 0x89 = { 2042, 3}, + 0x8A = { 2045, 2}, + 0x8B = { 2047, 4}, + 0x8C = { 2051, 1}, + 0x8D = { 2052, 1}, + 0x8E = { 2053, 1}, + 0x8F = { 2054, 1}, + 0x90 = { 2055, 1}, + 0x91 = { 2056, 2}, + 0x92 = { 2058, 2}, + 0x93 = { 2060, 2}, + 0x94 = { 2062, 1}, + 0x95 = { 2063, 1}, + 0x96 = { 2064, 1}, + 0x97 = { 2065, 1}, + 0x98 = { 2066, 1}, + 0x99 = { 2067, 2}, + 0x9A = { 2069, 1}, + 0x9B = { 2070, 2}, + 0x9C = { 2072, 1}, + 0x9D = { 2073, 1}, + 0x9E = { 2074, 1}, + 0x9F = { 2075, 1}, + 0xA0 = { 2076, 2}, + 0xA1 = { 2078, 2}, + 0xA2 = { 2080, 2}, + 0xA3 = { 2082, 2}, + 0xA4 = { 2084, 2}, + 0xA5 = { 2086, 2}, + 0xA6 = { 2088, 2}, + 0xA7 = { 2090, 2}, + 0xA8 = { 2092, 2}, + 0xA9 = { 2094, 2}, + 0xAA = { 2096, 2}, + 0xAB = { 2098, 2}, + 0xAC = { 2100, 2}, + 0xAD = { 2102, 2}, + 0xAE = { 2104, 2}, + 0xAF = { 2106, 2}, + 0xB0 = { 2108, 2}, + 0xB1 = { 2110, 2}, + 0xB2 = { 2112, 2}, + 0xB3 = { 2114, 2}, + 0xB4 = { 2116, 2}, + 0xB5 = { 2118, 2}, + 0xB6 = { 2120, 2}, + 0xB7 = { 2122, 2}, + 0xB8 = { 2124, 2}, + 0xB9 = { 2126, 2}, + 0xBA = { 2128, 2}, + 0xBB = { 2130, 2}, + 0xBC = { 2132, 2}, + 0xBD = { 2134, 2}, + 0xBE = { 2136, 2}, + 0xBF = { 2138, 2}, + 0xC0 = { 2140, 7}, + 0xC1 = { 2147, 4}, + 0xC2 = { 2151, 12}, + 0xC3 = { 2163, 5}, + 0xC4 = { 2168, 11}, + 0xC5 = { 2179, 8}, + 0xC6 = { 2187, 12}, + 0xC7 = { 2199, 5}, + 0xC8 = { 2204, 6}, + 0xC9 = { 2210, 6}, + 0xCA = { 2216, 12}, + 0xCB = { 2228, 8}, + 0xCC = { 2236, 6}, + 0xCD = { 2242, 6}, + 0xCE = { 2248, 12}, + 0xCF = { 2260, 6}, + 0xD0 = { 2266, 4}, + 0xD1 = { 2270, 4}, + 0xD2 = { 2274, 4}, + 0xD3 = { 2278, 2}, + 0xD4 = { 2280, 4}, + 0xD5 = { 2284, 4}, + 0xD6 = { 2288, 2}, + 0xD7 = { 2290, 2}, + 0xD8 = { 2292, 4}, + 0xD9 = { 2296, 4}, + 0xDA = { 2300, 2}, + 0xDB = { 2302, 2}, + 0xDC = { 2304, 4}, + 0xDD = { 2308, 4}, + 0xDE = { 2312, 2}, + 0xDF = { 2314, 2}, + 0xE0 = { 2316, 19}, + 0xE1 = { 2335, 14}, + 0xE2 = { 2349, 19}, + 0xE3 = { 2368, 15}, + 0xE4 = { 2383, 17}, + 0xE5 = { 2400, 13}, + 0xE6 = { 2413, 18}, + 0xE7 = { 2431, 15}, + 0xE8 = { 2446, 14}, + 0xE9 = { 2460, 11}, + 0xEA = { 2471, 10}, + 0xEB = { 2481, 77}, + 0xEC = { 2558, 15}, + 0xED = { 2573, 11}, + 0xEE = { 2584, 12}, + 0xEF = { 2596, 78}, + 0xF0 = { 2674, 3}, + 0xF1 = { 2677, 3}, + 0xF2 = { 2680, 3}, + 0xF3 = { 2683, 3}, + 0xF4 = { 2686, 3}, + 0xF5 = { 2689, 3}, + 0xF6 = { 2692, 3}, + 0xF7 = { 2695, 3}, + 0xF8 = { 2698, 1}, + 0xF9 = { 2699, 1}, + 0xFA = { 2700, 1}, + 0xFB = { 2701, 1}, + 0xFC = { 2702, 1}, + 0xFD = { 2703, 1}, + 0xFE = { 2704, 1}, + 0xFF = { 2705, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2726, 23}, - 0x75 = { 2749, 19}, - 0x76 = { 2768, 19}, - 0x77 = { 2787, 104}, - 0x78 = { 2891, 31}, - 0x79 = { 2922, 38}, - 0x7A = { 2960, 23}, - 0x7B = { 2983, 14}, - 0x7C = { 2997, 20}, - 0x7D = { 3017, 71}, - 0x7E = { 3088, 23}, - 0x7F = { 3111, 126}, + 0x74 = { 2706, 23}, + 0x75 = { 2729, 19}, + 0x76 = { 2748, 19}, + 0x77 = { 2767, 104}, + 0x78 = { 2871, 31}, + 0x79 = { 2902, 38}, + 0x7A = { 2940, 23}, + 0x7B = { 2963, 14}, + 0x7C = { 2977, 20}, + 0x7D = { 2997, 71}, + 0x7E = { 3068, 23}, + 0x7F = { 3091, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3237, 1}, - 0x01 = { 3238, 1}, - 0x02 = { 3239, 1}, - 0x03 = { 3240, 1}, - 0x04 = { 3241, 1}, - 0x05 = { 3242, 1}, - 0x06 = { 3243, 2}, - 0x07 = { 3245, 2}, - 0x08 = { 3247, 1}, - 0x09 = { 3248, 1}, - 0x0A = { 3249, 1}, - 0x0B = { 3250, 1}, - 0x0C = { 3251, 1}, - 0x0D = { 3252, 1}, - 0x0E = { 3253, 1}, - 0x0F = { 3254, 1}, - 0x10 = { 3255, 16}, - 0x11 = { 3271, 7}, - 0x12 = { 3278, 1}, - 0x13 = { 3279, 1}, - 0x14 = { 3280, 2}, - 0x15 = { 3282, 2}, - 0x16 = { 3284, 2}, - 0x17 = { 3286, 2}, - 0x18 = { 3288, 1}, - 0x19 = { 3289, 1}, - 0x1A = { 3290, 1}, - 0x1B = { 3291, 1}, - 0x1C = { 3292, 1}, - 0x1D = { 3293, 1}, - 0x1E = { 3294, 1}, - 0x1F = { 3295, 1}, - 0x20 = { 3296, 1}, - 0x21 = { 3297, 1}, - 0x22 = { 3298, 1}, - 0x23 = { 3299, 1}, - 0x24 = { 3300, 1}, - 0x25 = { 3301, 1}, - 0x26 = { 3302, 1}, - 0x27 = { 3303, 1}, - 0x28 = { 3304, 1}, - 0x29 = { 3305, 1}, - 0x2A = { 3306, 1}, - 0x2B = { 3307, 1}, - 0x2C = { 3308, 7}, - 0x2D = { 3315, 2}, - 0x2E = { 3317, 4}, - 0x2F = { 3321, 8}, - 0x30 = { 3329, 1}, - 0x31 = { 3330, 1}, - 0x32 = { 3331, 1}, - 0x33 = { 3332, 1}, - 0x34 = { 3333, 1}, - 0x35 = { 3334, 1}, - 0x36 = { 3335, 1}, - 0x37 = { 3336, 3}, - 0x38 = { 3339, 1}, - 0x39 = { 3340, 1}, + 0x00 = { 3217, 1}, + 0x01 = { 3218, 1}, + 0x02 = { 3219, 1}, + 0x03 = { 3220, 1}, + 0x04 = { 3221, 1}, + 0x05 = { 3222, 1}, + 0x06 = { 3223, 2}, + 0x07 = { 3225, 2}, + 0x08 = { 3227, 1}, + 0x09 = { 3228, 1}, + 0x0A = { 3229, 1}, + 0x0B = { 3230, 1}, + 0x0C = { 3231, 1}, + 0x0D = { 3232, 1}, + 0x0E = { 3233, 1}, + 0x0F = { 3234, 1}, + 0x10 = { 3235, 16}, + 0x11 = { 3251, 7}, + 0x12 = { 3258, 1}, + 0x13 = { 3259, 1}, + 0x14 = { 3260, 2}, + 0x15 = { 3262, 2}, + 0x16 = { 3264, 2}, + 0x17 = { 3266, 2}, + 0x18 = { 3268, 1}, + 0x19 = { 3269, 1}, + 0x1A = { 3270, 1}, + 0x1B = { 3271, 1}, + 0x1C = { 3272, 1}, + 0x1D = { 3273, 1}, + 0x1E = { 3274, 1}, + 0x1F = { 3275, 1}, + 0x20 = { 3276, 1}, + 0x21 = { 3277, 1}, + 0x22 = { 3278, 1}, + 0x23 = { 3279, 1}, + 0x24 = { 3280, 1}, + 0x25 = { 3281, 1}, + 0x26 = { 3282, 1}, + 0x27 = { 3283, 1}, + 0x28 = { 3284, 1}, + 0x29 = { 3285, 1}, + 0x2A = { 3286, 1}, + 0x2B = { 3287, 1}, + 0x2C = { 3288, 7}, + 0x2D = { 3295, 2}, + 0x2E = { 3297, 4}, + 0x2F = { 3301, 8}, + 0x30 = { 3309, 1}, + 0x31 = { 3310, 1}, + 0x32 = { 3311, 1}, + 0x33 = { 3312, 1}, + 0x34 = { 3313, 1}, + 0x35 = { 3314, 1}, + 0x36 = { 3315, 1}, + 0x37 = { 3316, 3}, + 0x38 = { 3319, 1}, + 0x39 = { 3320, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3341, 6}, - 0xE85 = { 3347, 2}, - 0xE86 = { 3349, 1}, - 0xE87 = { 3350, 1}, - 0xE88 = { 3351, 1}, - 0xE89 = { 3352, 1}, - 0xE8A = { 3353, 1}, - 0xE8B = { 3354, 2}, - 0xE8C = { 3356, 4}, - 0xE8D = { 3360, 6}, - 0xE8E = { 3366, 1}, - 0xE8F = { 3367, 1}, - 0xE90 = { 3368, 1}, - 0xE91 = { 3369, 1}, - 0xE92 = { 3370, 2}, - 0xE93 = { 3372, 1}, - 0xE94 = { 3373, 1}, - 0xE95 = { 3374, 1}, - 0xE96 = { 3375, 1}, - 0xE97 = { 3376, 2}, - 0xE9C = { 3378, 1}, - 0xE9D = { 3379, 1}, - 0xE9E = { 3380, 1}, - 0xE9F = { 3381, 1}, - 0xEA0 = { 3382, 2}, - 0xEA1 = { 3384, 3}, - 0xEA2 = { 3387, 1}, - 0xEA3 = { 3388, 1}, - 0xEA4 = { 3389, 7}, - 0xEA5 = { 3396, 7}, - 0xEA6 = { 3403, 1}, - 0xEA7 = { 3404, 1}, - 0xEA8 = { 3405, 1}, - 0xEA9 = { 3406, 2}, - 0xEB1 = { 3408, 1}, - 0xEB4 = { 3409, 1}, - 0xEB5 = { 3410, 1}, - 0xEB6 = { 3411, 1}, - 0xEB7 = { 3412, 1}, - 0xEBB = { 3413, 1}, - 0xEBC = { 3414, 1}, - 0xEBD = { 3415, 1}, - 0xEC0 = { 3416, 2}, - 0xEC1 = { 3418, 1}, - 0xEC2 = { 3419, 3}, - 0xEC3 = { 3422, 2}, - 0xEC4 = { 3424, 2}, - 0xEC5 = { 3426, 1}, - 0xEC6 = { 3427, 7}, - 0xEC7 = { 3434, 2}, - 0xEC8 = { 3436, 1}, - 0xEC9 = { 3437, 1}, - 0xECA = { 3438, 2}, - 0xECB = { 3440, 2}, - 0xECC = { 3442, 1}, - 0xECD = { 3443, 1}, - 0xECE = { 3444, 2}, - 0xECF = { 3446, 2}, - 0xED6 = { 3448, 4}, - 0xED8 = { 3452, 4}, - 0xED9 = { 3456, 4}, - 0xEDC = { 3460, 4}, - 0xEDD = { 3464, 4}, - 0xEE0 = { 3468, 24}, - 0xEE1 = { 3492, 23}, - 0xEE2 = { 3515, 22}, - 0xEE3 = { 3537, 29}, - 0xEE4 = { 3566, 23}, - 0xEE5 = { 3589, 22}, - 0xEE6 = { 3611, 22}, - 0xEE7 = { 3633, 29}, - 0xEE8 = { 3662, 28}, - 0xEE9 = { 3690, 12}, - 0xEEA = { 3702, 13}, - 0xEEB = { 3715, 18}, - 0xEEC = { 3733, 27}, - 0xEED = { 3760, 13}, - 0xEEE = { 3773, 22}, - 0xEEF = { 3795, 23}, - 0xEF0 = { 3818, 15}, - 0xEF1 = { 3833, 15}, - 0xEF2 = { 3848, 15}, - 0xEF3 = { 3863, 15}, - 0xEF4 = { 3878, 15}, - 0xEF5 = { 3893, 15}, - 0xEF6 = { 3908, 15}, - 0xEF7 = { 3923, 15}, - 0xEF8 = { 3938, 3}, - 0xEF9 = { 3941, 3}, - 0xEFA = { 3944, 3}, - 0xEFB = { 3947, 3}, - 0xEFC = { 3950, 3}, - 0xEFD = { 3953, 3}, - 0xEFE = { 3956, 3}, - 0xEFF = { 3959, 3}, - 0xF00 = { 3962, 12}, - 0xF01 = { 3974, 11}, - 0xF02 = { 3985, 8}, - 0xF03 = { 3993, 8}, - 0xF04 = { 4001, 9}, - 0xF05 = { 4010, 6}, - 0xF06 = { 4016, 5}, - 0xF07 = { 4021, 5}, - 0xF08 = { 4026, 6}, - 0xF09 = { 4032, 6}, - 0xF0A = { 4038, 4}, - 0xF0B = { 4042, 4}, - 0xF0C = { 4046, 4}, - 0xF0D = { 4050, 3}, - 0xF0E = { 4053, 4}, - 0xF0F = { 4057, 4}, - 0xF10 = { 4061, 7}, - 0xF11 = { 4068, 7}, - 0xF12 = { 4075, 6}, - 0xF13 = { 4081, 6}, - 0xF14 = { 4087, 5}, - 0xF15 = { 4092, 4}, - 0xF16 = { 4096, 5}, - 0xF17 = { 4101, 5}, - 0xF18 = { 4106, 5}, - 0xF19 = { 4111, 4}, - 0xF1A = { 4115, 4}, - 0xF1B = { 4119, 5}, - 0xF1C = { 4124, 5}, - 0xF1D = { 4129, 4}, - 0xF1E = { 4133, 4}, - 0xF1F = { 4137, 4}, - 0xF20 = { 4141, 5}, - 0xF21 = { 4146, 4}, - 0xF22 = { 4150, 4}, - 0xF23 = { 4154, 4}, - 0xF24 = { 4158, 5}, - 0xF25 = { 4163, 3}, - 0xF26 = { 4166, 4}, - 0xF27 = { 4170, 4}, - 0xF28 = { 4174, 5}, - 0xF29 = { 4179, 4}, - 0xF2A = { 4183, 4}, - 0xF2B = { 4187, 4}, - 0xF2C = { 4191, 5}, - 0xF2D = { 4196, 3}, - 0xF2E = { 4199, 4}, - 0xF2F = { 4203, 4}, - 0xF30 = { 4207, 6}, - 0xF31 = { 4213, 4}, - 0xF32 = { 4217, 6}, - 0xF33 = { 4223, 4}, - 0xF34 = { 4227, 5}, - 0xF35 = { 4232, 3}, - 0xF36 = { 4235, 6}, - 0xF37 = { 4241, 4}, - 0xF38 = { 4245, 7}, - 0xF39 = { 4252, 4}, - 0xF3A = { 4256, 19}, - 0xF3B = { 4275, 9}, - 0xF3C = { 4284, 5}, - 0xF3D = { 4289, 3}, - 0xF3E = { 4292, 5}, - 0xF3F = { 4297, 4}, - 0xF40 = { 4301, 7}, - 0xF41 = { 4308, 7}, - 0xF42 = { 4315, 5}, - 0xF43 = { 4320, 5}, - 0xF44 = { 4325, 7}, - 0xF45 = { 4332, 6}, - 0xF46 = { 4338, 5}, - 0xF47 = { 4343, 5}, - 0xF48 = { 4348, 6}, - 0xF49 = { 4354, 6}, - 0xF4A = { 4360, 4}, - 0xF4B = { 4364, 4}, - 0xF4C = { 4368, 4}, - 0xF4D = { 4372, 3}, - 0xF4E = { 4375, 4}, - 0xF4F = { 4379, 4}, - 0xF50 = { 4383, 5}, - 0xF51 = { 4388, 5}, - 0xF52 = { 4393, 4}, - 0xF53 = { 4397, 4}, - 0xF54 = { 4401, 5}, - 0xF55 = { 4406, 4}, - 0xF56 = { 4410, 5}, - 0xF57 = { 4415, 5}, - 0xF58 = { 4420, 5}, - 0xF59 = { 4425, 4}, - 0xF5A = { 4429, 4}, - 0xF5B = { 4433, 5}, - 0xF5C = { 4438, 5}, - 0xF5D = { 4443, 4}, - 0xF5E = { 4447, 4}, - 0xF5F = { 4451, 4}, - 0xF60 = { 4455, 5}, - 0xF61 = { 4460, 4}, - 0xF62 = { 4464, 4}, - 0xF63 = { 4468, 4}, - 0xF64 = { 4472, 5}, - 0xF65 = { 4477, 3}, - 0xF66 = { 4480, 4}, - 0xF67 = { 4484, 4}, - 0xF68 = { 4488, 5}, - 0xF69 = { 4493, 4}, - 0xF6A = { 4497, 4}, - 0xF6B = { 4501, 4}, - 0xF6C = { 4505, 5}, - 0xF6D = { 4510, 3}, - 0xF6E = { 4513, 4}, - 0xF6F = { 4517, 4}, - 0xF70 = { 4521, 5}, - 0xF71 = { 4526, 4}, - 0xF72 = { 4530, 4}, - 0xF73 = { 4534, 4}, - 0xF74 = { 4538, 4}, - 0xF75 = { 4542, 3}, - 0xF76 = { 4545, 4}, - 0xF77 = { 4549, 4}, - 0xF78 = { 4553, 8}, - 0xF79 = { 4561, 4}, - 0xF7A = { 4565, 4}, - 0xF7B = { 4569, 4}, - 0xF7C = { 4573, 4}, - 0xF7D = { 4577, 3}, - 0xF7E = { 4580, 4}, - 0xF7F = { 4584, 5}, - 0xF80 = { 4589, 1}, - 0xF81 = { 4590, 1}, - 0xF82 = { 4591, 1}, - 0xF83 = { 4592, 2}, - 0xF84 = { 4594, 1}, - 0xF85 = { 4595, 2}, - 0xF88 = { 4597, 1}, - 0xF89 = { 4598, 2}, - 0xF8A = { 4600, 1}, - 0xF8B = { 4601, 1}, - 0xF8C = { 4602, 1}, - 0xF8D = { 4603, 2}, - 0xF91 = { 4605, 1}, - 0xF93 = { 4606, 1}, - 0xF99 = { 4607, 2}, - 0xF9B = { 4609, 1}, - 0xFA0 = { 4610, 3}, - 0xFA1 = { 4613, 3}, - 0xFA2 = { 4616, 3}, - 0xFA3 = { 4619, 3}, - 0xFA4 = { 4622, 3}, - 0xFA5 = { 4625, 3}, - 0xFA6 = { 4628, 1}, - 0xFA7 = { 4629, 1}, - 0xFA8 = { 4630, 10}, - 0xFA9 = { 4640, 10}, - 0xFAA = { 4650, 6}, - 0xFAB = { 4656, 1}, - 0xFAC = { 4657, 6}, - 0xFAD = { 4663, 6}, - 0xFAE = { 4669, 6}, - 0xFB0 = { 4675, 3}, - 0xFB5 = { 4678, 1}, - 0xFB8 = { 4679, 1}, - 0xFB9 = { 4680, 1}, - 0xFBA = { 4681, 1}, - 0xFBB = { 4682, 1}, - 0xFBC = { 4683, 1}, - 0xFBE = { 4684, 1}, - 0xFC0 = { 4685, 1}, - 0xFC1 = { 4686, 1}, - 0xFC2 = { 4687, 3}, - 0xFC3 = { 4690, 3}, - 0xFC4 = { 4693, 1}, - 0xFC5 = { 4694, 1}, - 0xFC6 = { 4695, 2}, - 0xFC7 = { 4697, 2}, - 0xFC8 = { 4699, 7}, - 0xFC9 = { 4706, 11}, - 0xFCA = { 4717, 3}, - 0xFCB = { 4720, 3}, - 0xFCC = { 4723, 7}, - 0xFCD = { 4730, 7}, - 0xFCE = { 4737, 2}, - 0xFCF = { 4739, 2}, - 0xFD2 = { 4741, 1}, - 0xFD3 = { 4742, 1}, - 0xFD9 = { 4743, 4}, - 0xFDA = { 4747, 1}, - 0xFDB = { 4748, 1}, - 0xFE0 = { 4749, 28}, - 0xFE1 = { 4777, 26}, - 0xFE2 = { 4803, 26}, - 0xFE3 = { 4829, 32}, - 0xFE4 = { 4861, 29}, - 0xFE5 = { 4890, 27}, - 0xFE6 = { 4917, 27}, - 0xFE7 = { 4944, 33}, - 0xFE8 = { 4977, 32}, - 0xFE9 = { 5009, 17}, - 0xFEA = { 5026, 17}, - 0xFEB = { 5043, 29}, - 0xFEC = { 5072, 31}, - 0xFED = { 5103, 18}, - 0xFEE = { 5121, 26}, - 0xFEF = { 5147, 32}, - 0xFF0 = { 5179, 19}, - 0xFF1 = { 5198, 18}, - 0xFF2 = { 5216, 17}, - 0xFF3 = { 5233, 17}, - 0xFF4 = { 5250, 19}, - 0xFF5 = { 5269, 18}, - 0xFF6 = { 5287, 17}, - 0xFF7 = { 5304, 17}, - 0xFF8 = { 5321, 4}, - 0xFF9 = { 5325, 4}, - 0xFFA = { 5329, 4}, - 0xFFB = { 5333, 17}, - 0xFFC = { 5350, 4}, - 0xFFD = { 5354, 4}, - 0xFFE = { 5358, 4}, - 0xFFF = { 5362, 17}, + 0xE84 = { 3321, 6}, + 0xE85 = { 3327, 2}, + 0xE86 = { 3329, 1}, + 0xE87 = { 3330, 1}, + 0xE88 = { 3331, 1}, + 0xE89 = { 3332, 1}, + 0xE8A = { 3333, 1}, + 0xE8B = { 3334, 2}, + 0xE8C = { 3336, 4}, + 0xE8D = { 3340, 6}, + 0xE8E = { 3346, 1}, + 0xE8F = { 3347, 1}, + 0xE90 = { 3348, 1}, + 0xE91 = { 3349, 1}, + 0xE92 = { 3350, 2}, + 0xE93 = { 3352, 1}, + 0xE94 = { 3353, 1}, + 0xE95 = { 3354, 1}, + 0xE96 = { 3355, 1}, + 0xE97 = { 3356, 2}, + 0xE9C = { 3358, 1}, + 0xE9D = { 3359, 1}, + 0xE9E = { 3360, 1}, + 0xE9F = { 3361, 1}, + 0xEA0 = { 3362, 2}, + 0xEA1 = { 3364, 3}, + 0xEA2 = { 3367, 1}, + 0xEA3 = { 3368, 1}, + 0xEA4 = { 3369, 7}, + 0xEA5 = { 3376, 7}, + 0xEA6 = { 3383, 1}, + 0xEA7 = { 3384, 1}, + 0xEA8 = { 3385, 1}, + 0xEA9 = { 3386, 2}, + 0xEB1 = { 3388, 1}, + 0xEB4 = { 3389, 1}, + 0xEB5 = { 3390, 1}, + 0xEB6 = { 3391, 1}, + 0xEB7 = { 3392, 1}, + 0xEBB = { 3393, 1}, + 0xEBC = { 3394, 1}, + 0xEBD = { 3395, 1}, + 0xEC0 = { 3396, 2}, + 0xEC1 = { 3398, 1}, + 0xEC2 = { 3399, 3}, + 0xEC3 = { 3402, 2}, + 0xEC4 = { 3404, 2}, + 0xEC5 = { 3406, 1}, + 0xEC6 = { 3407, 7}, + 0xEC7 = { 3414, 2}, + 0xEC8 = { 3416, 1}, + 0xEC9 = { 3417, 1}, + 0xECA = { 3418, 2}, + 0xECB = { 3420, 2}, + 0xECC = { 3422, 1}, + 0xECD = { 3423, 1}, + 0xECE = { 3424, 2}, + 0xECF = { 3426, 2}, + 0xED6 = { 3428, 4}, + 0xED8 = { 3432, 4}, + 0xED9 = { 3436, 4}, + 0xEDC = { 3440, 4}, + 0xEDD = { 3444, 4}, + 0xEE0 = { 3448, 24}, + 0xEE1 = { 3472, 23}, + 0xEE2 = { 3495, 22}, + 0xEE3 = { 3517, 29}, + 0xEE4 = { 3546, 23}, + 0xEE5 = { 3569, 22}, + 0xEE6 = { 3591, 22}, + 0xEE7 = { 3613, 29}, + 0xEE8 = { 3642, 28}, + 0xEE9 = { 3670, 12}, + 0xEEA = { 3682, 13}, + 0xEEB = { 3695, 18}, + 0xEEC = { 3713, 27}, + 0xEED = { 3740, 13}, + 0xEEE = { 3753, 22}, + 0xEEF = { 3775, 23}, + 0xEF0 = { 3798, 15}, + 0xEF1 = { 3813, 15}, + 0xEF2 = { 3828, 15}, + 0xEF3 = { 3843, 15}, + 0xEF4 = { 3858, 15}, + 0xEF5 = { 3873, 15}, + 0xEF6 = { 3888, 15}, + 0xEF7 = { 3903, 15}, + 0xEF8 = { 3918, 3}, + 0xEF9 = { 3921, 3}, + 0xEFA = { 3924, 3}, + 0xEFB = { 3927, 3}, + 0xEFC = { 3930, 3}, + 0xEFD = { 3933, 3}, + 0xEFE = { 3936, 3}, + 0xEFF = { 3939, 3}, + 0xF00 = { 3942, 12}, + 0xF01 = { 3954, 11}, + 0xF02 = { 3965, 8}, + 0xF03 = { 3973, 8}, + 0xF04 = { 3981, 9}, + 0xF05 = { 3990, 6}, + 0xF06 = { 3996, 5}, + 0xF07 = { 4001, 5}, + 0xF08 = { 4006, 6}, + 0xF09 = { 4012, 6}, + 0xF0A = { 4018, 4}, + 0xF0B = { 4022, 4}, + 0xF0C = { 4026, 4}, + 0xF0D = { 4030, 3}, + 0xF0E = { 4033, 4}, + 0xF0F = { 4037, 4}, + 0xF10 = { 4041, 7}, + 0xF11 = { 4048, 7}, + 0xF12 = { 4055, 6}, + 0xF13 = { 4061, 6}, + 0xF14 = { 4067, 5}, + 0xF15 = { 4072, 4}, + 0xF16 = { 4076, 5}, + 0xF17 = { 4081, 5}, + 0xF18 = { 4086, 5}, + 0xF19 = { 4091, 4}, + 0xF1A = { 4095, 4}, + 0xF1B = { 4099, 5}, + 0xF1C = { 4104, 5}, + 0xF1D = { 4109, 4}, + 0xF1E = { 4113, 4}, + 0xF1F = { 4117, 4}, + 0xF20 = { 4121, 5}, + 0xF21 = { 4126, 4}, + 0xF22 = { 4130, 4}, + 0xF23 = { 4134, 4}, + 0xF24 = { 4138, 5}, + 0xF25 = { 4143, 3}, + 0xF26 = { 4146, 4}, + 0xF27 = { 4150, 4}, + 0xF28 = { 4154, 5}, + 0xF29 = { 4159, 4}, + 0xF2A = { 4163, 4}, + 0xF2B = { 4167, 4}, + 0xF2C = { 4171, 5}, + 0xF2D = { 4176, 3}, + 0xF2E = { 4179, 4}, + 0xF2F = { 4183, 4}, + 0xF30 = { 4187, 6}, + 0xF31 = { 4193, 4}, + 0xF32 = { 4197, 6}, + 0xF33 = { 4203, 4}, + 0xF34 = { 4207, 5}, + 0xF35 = { 4212, 3}, + 0xF36 = { 4215, 6}, + 0xF37 = { 4221, 4}, + 0xF38 = { 4225, 7}, + 0xF39 = { 4232, 4}, + 0xF3A = { 4236, 19}, + 0xF3B = { 4255, 9}, + 0xF3C = { 4264, 5}, + 0xF3D = { 4269, 3}, + 0xF3E = { 4272, 5}, + 0xF3F = { 4277, 4}, + 0xF40 = { 4281, 7}, + 0xF41 = { 4288, 7}, + 0xF42 = { 4295, 5}, + 0xF43 = { 4300, 5}, + 0xF44 = { 4305, 7}, + 0xF45 = { 4312, 6}, + 0xF46 = { 4318, 5}, + 0xF47 = { 4323, 5}, + 0xF48 = { 4328, 6}, + 0xF49 = { 4334, 6}, + 0xF4A = { 4340, 4}, + 0xF4B = { 4344, 4}, + 0xF4C = { 4348, 4}, + 0xF4D = { 4352, 3}, + 0xF4E = { 4355, 4}, + 0xF4F = { 4359, 4}, + 0xF50 = { 4363, 5}, + 0xF51 = { 4368, 5}, + 0xF52 = { 4373, 4}, + 0xF53 = { 4377, 4}, + 0xF54 = { 4381, 5}, + 0xF55 = { 4386, 4}, + 0xF56 = { 4390, 5}, + 0xF57 = { 4395, 5}, + 0xF58 = { 4400, 5}, + 0xF59 = { 4405, 4}, + 0xF5A = { 4409, 4}, + 0xF5B = { 4413, 5}, + 0xF5C = { 4418, 5}, + 0xF5D = { 4423, 4}, + 0xF5E = { 4427, 4}, + 0xF5F = { 4431, 4}, + 0xF60 = { 4435, 5}, + 0xF61 = { 4440, 4}, + 0xF62 = { 4444, 4}, + 0xF63 = { 4448, 4}, + 0xF64 = { 4452, 5}, + 0xF65 = { 4457, 3}, + 0xF66 = { 4460, 4}, + 0xF67 = { 4464, 4}, + 0xF68 = { 4468, 5}, + 0xF69 = { 4473, 4}, + 0xF6A = { 4477, 4}, + 0xF6B = { 4481, 4}, + 0xF6C = { 4485, 5}, + 0xF6D = { 4490, 3}, + 0xF6E = { 4493, 4}, + 0xF6F = { 4497, 4}, + 0xF70 = { 4501, 5}, + 0xF71 = { 4506, 4}, + 0xF72 = { 4510, 4}, + 0xF73 = { 4514, 4}, + 0xF74 = { 4518, 4}, + 0xF75 = { 4522, 3}, + 0xF76 = { 4525, 4}, + 0xF77 = { 4529, 4}, + 0xF78 = { 4533, 8}, + 0xF79 = { 4541, 4}, + 0xF7A = { 4545, 4}, + 0xF7B = { 4549, 4}, + 0xF7C = { 4553, 4}, + 0xF7D = { 4557, 3}, + 0xF7E = { 4560, 4}, + 0xF7F = { 4564, 5}, + 0xF80 = { 4569, 1}, + 0xF81 = { 4570, 1}, + 0xF82 = { 4571, 1}, + 0xF83 = { 4572, 2}, + 0xF84 = { 4574, 1}, + 0xF85 = { 4575, 2}, + 0xF88 = { 4577, 1}, + 0xF89 = { 4578, 2}, + 0xF8A = { 4580, 1}, + 0xF8B = { 4581, 1}, + 0xF8C = { 4582, 1}, + 0xF8D = { 4583, 2}, + 0xF91 = { 4585, 1}, + 0xF93 = { 4586, 1}, + 0xF99 = { 4587, 2}, + 0xF9B = { 4589, 1}, + 0xFA0 = { 4590, 3}, + 0xFA1 = { 4593, 3}, + 0xFA2 = { 4596, 3}, + 0xFA3 = { 4599, 3}, + 0xFA4 = { 4602, 3}, + 0xFA5 = { 4605, 3}, + 0xFA6 = { 4608, 1}, + 0xFA7 = { 4609, 1}, + 0xFA8 = { 4610, 10}, + 0xFA9 = { 4620, 10}, + 0xFAA = { 4630, 6}, + 0xFAB = { 4636, 1}, + 0xFAC = { 4637, 6}, + 0xFAD = { 4643, 6}, + 0xFAE = { 4649, 6}, + 0xFB0 = { 4655, 3}, + 0xFB5 = { 4658, 1}, + 0xFB8 = { 4659, 1}, + 0xFB9 = { 4660, 1}, + 0xFBA = { 4661, 1}, + 0xFBB = { 4662, 1}, + 0xFBC = { 4663, 1}, + 0xFBE = { 4664, 1}, + 0xFC0 = { 4665, 1}, + 0xFC1 = { 4666, 1}, + 0xFC2 = { 4667, 3}, + 0xFC3 = { 4670, 3}, + 0xFC4 = { 4673, 1}, + 0xFC5 = { 4674, 1}, + 0xFC6 = { 4675, 2}, + 0xFC7 = { 4677, 2}, + 0xFC8 = { 4679, 7}, + 0xFC9 = { 4686, 11}, + 0xFCA = { 4697, 3}, + 0xFCB = { 4700, 3}, + 0xFCC = { 4703, 7}, + 0xFCD = { 4710, 7}, + 0xFCE = { 4717, 2}, + 0xFCF = { 4719, 2}, + 0xFD2 = { 4721, 1}, + 0xFD3 = { 4722, 1}, + 0xFD9 = { 4723, 4}, + 0xFDA = { 4727, 1}, + 0xFDB = { 4728, 1}, + 0xFE0 = { 4729, 28}, + 0xFE1 = { 4757, 26}, + 0xFE2 = { 4783, 26}, + 0xFE3 = { 4809, 32}, + 0xFE4 = { 4841, 29}, + 0xFE5 = { 4870, 27}, + 0xFE6 = { 4897, 27}, + 0xFE7 = { 4924, 33}, + 0xFE8 = { 4957, 32}, + 0xFE9 = { 4989, 17}, + 0xFEA = { 5006, 17}, + 0xFEB = { 5023, 29}, + 0xFEC = { 5052, 31}, + 0xFED = { 5083, 18}, + 0xFEE = { 5101, 26}, + 0xFEF = { 5127, 32}, + 0xFF0 = { 5159, 19}, + 0xFF1 = { 5178, 18}, + 0xFF2 = { 5196, 17}, + 0xFF3 = { 5213, 17}, + 0xFF4 = { 5230, 19}, + 0xFF5 = { 5249, 18}, + 0xFF6 = { 5267, 17}, + 0xFF7 = { 5284, 17}, + 0xFF8 = { 5301, 4}, + 0xFF9 = { 5305, 4}, + 0xFFA = { 5309, 4}, + 0xFFB = { 5313, 17}, + 0xFFC = { 5330, 4}, + 0xFFD = { 5334, 4}, + 0xFFE = { 5338, 4}, + 0xFFF = { 5342, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index e6885c0dd..1fed899bc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1656]lib.Encoding{ +ENCODE_FORMS := [1649]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1126,10 +1126,12 @@ ENCODE_FORMS := [1656]lib.Encoding{ { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VMRS { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR @@ -1780,47 +1782,61 @@ ENCODE_FORMS := [1656]lib.Encoding{ // .VSWP { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - // .VMOV_LANE - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VLD1 { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2 { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD3 { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD4 { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST1 { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2 { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST3 { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST4 { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .AESE { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESD @@ -1909,38 +1925,6 @@ ENCODE_FORMS := [1656]lib.Encoding{ { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4R { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - // .VLD1_LANE - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD2_LANE - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD3_LANE - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD4_LANE - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST1_LANE - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST2_LANE - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST3_LANE - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST4_LANE - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .IT { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, // .TT @@ -2545,315 +2529,306 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .VCVTP = { 798, 2}, .VCVTM = { 800, 2}, .VCVTR = { 802, 4}, - .VMOV = { 806, 31}, - .VMRS = { 837, 1}, - .VMSR = { 838, 1}, - .VLDR = { 839, 2}, - .VSTR = { 841, 2}, - .VLDM = { 843, 2}, - .VSTM = { 845, 2}, - .VPUSH = { 847, 2}, - .VPOP = { 849, 2}, - .VSEL = { 851, 2}, - .VMAXNM = { 853, 2}, - .VMINNM = { 855, 2}, - .VRINTA = { 857, 3}, - .VRINTN = { 860, 3}, - .VRINTP = { 863, 3}, - .VRINTM = { 866, 3}, - .VRINTR = { 869, 2}, - .VRINTZ = { 871, 3}, - .VRINTX = { 874, 3}, - .VADDL = { 877, 6}, - .VADDW = { 883, 6}, - .VSUBL = { 889, 6}, - .VSUBW = { 895, 6}, - .VHADD = { 901, 9}, - .VHSUB = { 910, 9}, - .VRHADD = { 919, 3}, - .VQADD = { 922, 11}, - .VQSUB = { 933, 11}, - .VMULL = { 944, 11}, - .VMLAL = { 955, 10}, - .VMLSL = { 965, 10}, - .VQDMULL = { 975, 4}, - .VQDMLAL = { 979, 4}, - .VQDMLSL = { 983, 4}, - .VQDMULH = { 987, 8}, - .VQRDMULH = { 995, 8}, - .VQRDMLAH = { 1003, 8}, - .VQRDMLSH = { 1011, 8}, - .VABA = { 1019, 8}, - .VABAL = { 1027, 6}, - .VABD = { 1033, 10}, - .VABDL = { 1043, 6}, - .VAND = { 1049, 3}, - .VBIC = { 1052, 3}, - .VORR = { 1055, 3}, - .VORN = { 1058, 3}, - .VEOR = { 1061, 3}, - .VBSL = { 1064, 2}, - .VBIT = { 1066, 2}, - .VBIF = { 1068, 2}, - .VMVN = { 1070, 13}, - .VMOVN = { 1083, 3}, - .VQMOVN = { 1086, 6}, - .VQMOVUN = { 1092, 3}, - .VMOVL = { 1095, 6}, - .VTST = { 1101, 6}, - .VCEQ = { 1107, 14}, - .VCGE = { 1121, 16}, - .VCGT = { 1137, 16}, - .VCLE = { 1153, 18}, - .VCLT = { 1171, 18}, - .VACGE = { 1189, 2}, - .VACGT = { 1191, 2}, - .VACLE = { 1193, 2}, - .VACLT = { 1195, 2}, - .VMAX = { 1197, 13}, - .VMIN = { 1210, 13}, - .VPMAX = { 1223, 5}, - .VPMIN = { 1228, 5}, - .VPADD = { 1233, 5}, - .VPADDL = { 1238, 6}, - .VPADAL = { 1244, 4}, - .VRECPE = { 1248, 4}, - .VRECPS = { 1252, 2}, - .VRSQRTE = { 1254, 4}, - .VRSQRTS = { 1258, 2}, - .VSHL = { 1260, 9}, - .VSHR = { 1269, 3}, - .VSRA = { 1272, 3}, - .VRSHL = { 1275, 5}, - .VRSHR = { 1280, 3}, - .VRSRA = { 1283, 2}, - .VSLI = { 1285, 2}, - .VSRI = { 1287, 2}, - .VQSHL = { 1289, 7}, - .VQSHRN = { 1296, 1}, - .VQSHRUN = { 1297, 1}, - .VQRSHL = { 1298, 16}, - .VQRSHRN = { 1314, 1}, - .VQRSHRUN = { 1315, 1}, - .VSHRN = { 1316, 1}, - .VRSHRN = { 1317, 1}, - .VSHLL = { 1318, 4}, - .VCLS = { 1322, 6}, - .VCLZ = { 1328, 6}, - .VCNT = { 1334, 2}, - .VREV16 = { 1336, 2}, - .VREV32 = { 1338, 4}, - .VREV64 = { 1342, 6}, - .VEXT = { 1348, 2}, - .VTBL = { 1350, 4}, - .VTBX = { 1354, 4}, - .VTRN = { 1358, 6}, - .VUZP = { 1364, 5}, - .VZIP = { 1369, 5}, - .VDUP = { 1374, 5}, - .VSWP = { 1379, 2}, - .VMOV_LANE = { 1381, 3}, - .VLD1 = { 1384, 8}, - .VLD2 = { 1392, 3}, - .VLD3 = { 1395, 2}, - .VLD4 = { 1397, 2}, - .VST1 = { 1399, 7}, - .VST2 = { 1406, 3}, - .VST3 = { 1409, 2}, - .VST4 = { 1411, 2}, - .AESE = { 1413, 1}, - .AESD = { 1414, 1}, - .AESMC = { 1415, 1}, - .AESIMC = { 1416, 1}, - .SHA1H = { 1417, 1}, - .SHA1SU0 = { 1418, 1}, - .SHA1SU1 = { 1419, 1}, - .SHA1C = { 1420, 1}, - .SHA1M = { 1421, 1}, - .SHA1P = { 1422, 1}, - .SHA256H = { 1423, 1}, - .SHA256H2 = { 1424, 1}, - .SHA256SU0 = { 1425, 1}, - .SHA256SU1 = { 1426, 1}, - .VJCVT = { 1427, 1}, - .VSDOT = { 1428, 4}, - .VUDOT = { 1432, 4}, - .VDOT = { 1436, 2}, - .VMMLA = { 1438, 1}, - .VFMAL = { 1439, 2}, - .VFMSL = { 1441, 2}, - .VCMLA = { 1443, 5}, - .VCADD = { 1448, 2}, - .VSMMLA = { 1450, 1}, - .VUMMLA = { 1451, 1}, - .VUSMMLA = { 1452, 1}, - .VSUDOT = { 1453, 2}, - .VUSDOT = { 1455, 4}, - .VQABS = { 1459, 1}, - .VQNEG = { 1460, 1}, - .VMOVX = { 1461, 1}, - .VINS = { 1462, 1}, - .VLD2R = { 1463, 1}, - .VLD3R = { 1464, 1}, - .VLD4R = { 1465, 1}, - .VLD1_LANE = { 1466, 3}, - .VLD2_LANE = { 1469, 3}, - .VLD3_LANE = { 1472, 3}, - .VLD4_LANE = { 1475, 3}, - .VST1_LANE = { 1478, 3}, - .VST2_LANE = { 1481, 3}, - .VST3_LANE = { 1484, 3}, - .VST4_LANE = { 1487, 3}, - .IT = { 1490, 1}, - .TT = { 1491, 1}, - .TTT = { 1492, 1}, - .TTA = { 1493, 1}, - .TTAT = { 1494, 1}, - .SG = { 1495, 1}, - .BXNS = { 1496, 1}, - .BLXNS = { 1497, 1}, - .PAC = { 1498, 1}, - .PACBTI = { 1499, 1}, - .AUT = { 1500, 1}, - .AUTG = { 1501, 1}, - .BTI = { 1502, 1}, - .WLS = { 1503, 1}, - .WLSTP = { 1504, 1}, - .DLS = { 1505, 1}, - .DLSTP = { 1506, 1}, - .LE = { 1507, 1}, - .LETP = { 1508, 1}, - .LCTP = { 1509, 1}, - .BF = { 1510, 1}, - .BFX = { 1511, 1}, - .BFL = { 1512, 1}, - .BFLX = { 1513, 1}, - .BFCSEL = { 1514, 1}, - .CX1 = { 1515, 1}, - .CX1A = { 1516, 1}, - .CX1D = { 1517, 1}, - .CX1DA = { 1518, 1}, - .CX2 = { 1519, 1}, - .CX2A = { 1520, 1}, - .CX2D = { 1521, 1}, - .CX2DA = { 1522, 1}, - .CX3 = { 1523, 1}, - .CX3A = { 1524, 1}, - .CX3D = { 1525, 1}, - .CX3DA = { 1526, 1}, - .VCX1 = { 1527, 2}, - .VCX1A = { 1529, 2}, - .VCX2 = { 1531, 2}, - .VCX2A = { 1533, 2}, - .VCX3 = { 1535, 2}, - .VCX3A = { 1537, 2}, - .VPT = { 1539, 1}, - .VPST = { 1540, 1}, - .VPSEL = { 1541, 1}, - .VPNOT = { 1542, 1}, - .VCTP = { 1543, 1}, - .VADDV = { 1544, 1}, - .VADDVA = { 1545, 1}, - .VADDLV = { 1546, 1}, - .VADDLVA = { 1547, 1}, - .VMAXV = { 1548, 1}, - .VMAXAV = { 1549, 1}, - .VMINV = { 1550, 1}, - .VMINAV = { 1551, 1}, - .VMAXNMV = { 1552, 1}, - .VMAXNMAV = { 1553, 1}, - .VMINNMV = { 1554, 1}, - .VMINNMAV = { 1555, 1}, - .VABAV = { 1556, 1}, - .VMLADAV = { 1557, 1}, - .VMLADAVA = { 1558, 1}, - .VMLADAVX = { 1559, 1}, - .VMLADAVAX = { 1560, 1}, - .VMLALDAV = { 1561, 1}, - .VMLALDAVA = { 1562, 1}, - .VMLALDAVX = { 1563, 1}, - .VMLALDAVAX = { 1564, 1}, - .VMLSDAV = { 1565, 1}, - .VMLSDAVA = { 1566, 1}, - .VMLSDAVX = { 1567, 1}, - .VMLSDAVAX = { 1568, 1}, - .VMLSLDAV = { 1569, 1}, - .VMLSLDAVA = { 1570, 1}, - .VMLSLDAVX = { 1571, 1}, - .VMLSLDAVAX = { 1572, 1}, - .VRMLALDAVH = { 1573, 1}, - .VRMLALDAVHA = { 1574, 1}, - .VRMLALDAVHX = { 1575, 1}, - .VRMLALDAVHAX = { 1576, 1}, - .VRMLSLDAVH = { 1577, 1}, - .VRMLSLDAVHA = { 1578, 1}, - .VRMLSLDAVHX = { 1579, 1}, - .VRMLSLDAVHAX = { 1580, 1}, - .VMLAV = { 1581, 1}, - .VMLAVA = { 1582, 1}, - .VMLSV = { 1583, 1}, - .VMLSVA = { 1584, 1}, - .VCMUL = { 1585, 1}, - .VHCADD = { 1586, 2}, - .VBRSR = { 1588, 1}, - .VSHLC = { 1589, 1}, - .VDDUP = { 1590, 1}, - .VIDUP = { 1591, 1}, - .VDWDUP = { 1592, 1}, - .VIWDUP = { 1593, 1}, - .VMOVNB = { 1594, 1}, - .VMOVNT = { 1595, 1}, - .VQMOVNB = { 1596, 1}, - .VQMOVNT = { 1597, 1}, - .VQMOVUNB = { 1598, 1}, - .VQMOVUNT = { 1599, 1}, - .VSHLLB = { 1600, 1}, - .VSHLLT = { 1601, 1}, - .VMULLB = { 1602, 1}, - .VMULLT = { 1603, 1}, - .VMLALB = { 1604, 1}, - .VMLALT = { 1605, 1}, - .VMLSLB = { 1606, 1}, - .VMLSLT = { 1607, 1}, - .VSHRNB = { 1608, 1}, - .VSHRNT = { 1609, 1}, - .VRSHRNB = { 1610, 1}, - .VRSHRNT = { 1611, 1}, - .VQSHRNB = { 1612, 1}, - .VQSHRNT = { 1613, 1}, - .VQRSHRNB = { 1614, 1}, - .VQRSHRNT = { 1615, 1}, - .VQSHRUNB = { 1616, 1}, - .VQSHRUNT = { 1617, 1}, - .VQRSHRUNB = { 1618, 1}, - .VQRSHRUNT = { 1619, 1}, - .VQDMLADH = { 1620, 1}, - .VQDMLADHX = { 1621, 1}, - .VQDMLSDH = { 1622, 1}, - .VQDMLSDHX = { 1623, 1}, - .VQRDMLADH = { 1624, 1}, - .VQRDMLADHX = { 1625, 1}, - .VQRDMLSDH = { 1626, 1}, - .VQRDMLSDHX = { 1627, 1}, - .VLDRB = { 1628, 2}, - .VLDRH = { 1630, 2}, - .VLDRW = { 1632, 2}, - .VLDRD = { 1634, 2}, - .VSTRB = { 1636, 2}, - .VSTRH = { 1638, 2}, - .VSTRW = { 1640, 2}, - .VSTRD = { 1642, 2}, - .VLD20 = { 1644, 1}, - .VLD21 = { 1645, 1}, - .VLD40 = { 1646, 1}, - .VLD41 = { 1647, 1}, - .VLD42 = { 1648, 1}, - .VLD43 = { 1649, 1}, - .VST20 = { 1650, 1}, - .VST21 = { 1651, 1}, - .VST40 = { 1652, 1}, - .VST41 = { 1653, 1}, - .VST42 = { 1654, 1}, - .VST43 = { 1655, 1}, - ._COUNT = { 1656, 0}, + .VMOV = { 806, 33}, + .VMRS = { 839, 1}, + .VMSR = { 840, 1}, + .VLDR = { 841, 2}, + .VSTR = { 843, 2}, + .VLDM = { 845, 2}, + .VSTM = { 847, 2}, + .VPUSH = { 849, 2}, + .VPOP = { 851, 2}, + .VSEL = { 853, 2}, + .VMAXNM = { 855, 2}, + .VMINNM = { 857, 2}, + .VRINTA = { 859, 3}, + .VRINTN = { 862, 3}, + .VRINTP = { 865, 3}, + .VRINTM = { 868, 3}, + .VRINTR = { 871, 2}, + .VRINTZ = { 873, 3}, + .VRINTX = { 876, 3}, + .VADDL = { 879, 6}, + .VADDW = { 885, 6}, + .VSUBL = { 891, 6}, + .VSUBW = { 897, 6}, + .VHADD = { 903, 9}, + .VHSUB = { 912, 9}, + .VRHADD = { 921, 3}, + .VQADD = { 924, 11}, + .VQSUB = { 935, 11}, + .VMULL = { 946, 11}, + .VMLAL = { 957, 10}, + .VMLSL = { 967, 10}, + .VQDMULL = { 977, 4}, + .VQDMLAL = { 981, 4}, + .VQDMLSL = { 985, 4}, + .VQDMULH = { 989, 8}, + .VQRDMULH = { 997, 8}, + .VQRDMLAH = { 1005, 8}, + .VQRDMLSH = { 1013, 8}, + .VABA = { 1021, 8}, + .VABAL = { 1029, 6}, + .VABD = { 1035, 10}, + .VABDL = { 1045, 6}, + .VAND = { 1051, 3}, + .VBIC = { 1054, 3}, + .VORR = { 1057, 3}, + .VORN = { 1060, 3}, + .VEOR = { 1063, 3}, + .VBSL = { 1066, 2}, + .VBIT = { 1068, 2}, + .VBIF = { 1070, 2}, + .VMVN = { 1072, 13}, + .VMOVN = { 1085, 3}, + .VQMOVN = { 1088, 6}, + .VQMOVUN = { 1094, 3}, + .VMOVL = { 1097, 6}, + .VTST = { 1103, 6}, + .VCEQ = { 1109, 14}, + .VCGE = { 1123, 16}, + .VCGT = { 1139, 16}, + .VCLE = { 1155, 18}, + .VCLT = { 1173, 18}, + .VACGE = { 1191, 2}, + .VACGT = { 1193, 2}, + .VACLE = { 1195, 2}, + .VACLT = { 1197, 2}, + .VMAX = { 1199, 13}, + .VMIN = { 1212, 13}, + .VPMAX = { 1225, 5}, + .VPMIN = { 1230, 5}, + .VPADD = { 1235, 5}, + .VPADDL = { 1240, 6}, + .VPADAL = { 1246, 4}, + .VRECPE = { 1250, 4}, + .VRECPS = { 1254, 2}, + .VRSQRTE = { 1256, 4}, + .VRSQRTS = { 1260, 2}, + .VSHL = { 1262, 9}, + .VSHR = { 1271, 3}, + .VSRA = { 1274, 3}, + .VRSHL = { 1277, 5}, + .VRSHR = { 1282, 3}, + .VRSRA = { 1285, 2}, + .VSLI = { 1287, 2}, + .VSRI = { 1289, 2}, + .VQSHL = { 1291, 7}, + .VQSHRN = { 1298, 1}, + .VQSHRUN = { 1299, 1}, + .VQRSHL = { 1300, 16}, + .VQRSHRN = { 1316, 1}, + .VQRSHRUN = { 1317, 1}, + .VSHRN = { 1318, 1}, + .VRSHRN = { 1319, 1}, + .VSHLL = { 1320, 4}, + .VCLS = { 1324, 6}, + .VCLZ = { 1330, 6}, + .VCNT = { 1336, 2}, + .VREV16 = { 1338, 2}, + .VREV32 = { 1340, 4}, + .VREV64 = { 1344, 6}, + .VEXT = { 1350, 2}, + .VTBL = { 1352, 4}, + .VTBX = { 1356, 4}, + .VTRN = { 1360, 6}, + .VUZP = { 1366, 5}, + .VZIP = { 1371, 5}, + .VDUP = { 1376, 5}, + .VSWP = { 1381, 2}, + .VLD1 = { 1383, 8}, + .VLD2 = { 1391, 6}, + .VLD3 = { 1397, 5}, + .VLD4 = { 1402, 5}, + .VST1 = { 1407, 7}, + .VST2 = { 1414, 6}, + .VST3 = { 1420, 5}, + .VST4 = { 1425, 5}, + .AESE = { 1430, 1}, + .AESD = { 1431, 1}, + .AESMC = { 1432, 1}, + .AESIMC = { 1433, 1}, + .SHA1H = { 1434, 1}, + .SHA1SU0 = { 1435, 1}, + .SHA1SU1 = { 1436, 1}, + .SHA1C = { 1437, 1}, + .SHA1M = { 1438, 1}, + .SHA1P = { 1439, 1}, + .SHA256H = { 1440, 1}, + .SHA256H2 = { 1441, 1}, + .SHA256SU0 = { 1442, 1}, + .SHA256SU1 = { 1443, 1}, + .VJCVT = { 1444, 1}, + .VSDOT = { 1445, 4}, + .VUDOT = { 1449, 4}, + .VDOT = { 1453, 2}, + .VMMLA = { 1455, 1}, + .VFMAL = { 1456, 2}, + .VFMSL = { 1458, 2}, + .VCMLA = { 1460, 5}, + .VCADD = { 1465, 2}, + .VSMMLA = { 1467, 1}, + .VUMMLA = { 1468, 1}, + .VUSMMLA = { 1469, 1}, + .VSUDOT = { 1470, 2}, + .VUSDOT = { 1472, 4}, + .VQABS = { 1476, 1}, + .VQNEG = { 1477, 1}, + .VMOVX = { 1478, 1}, + .VINS = { 1479, 1}, + .VLD2R = { 1480, 1}, + .VLD3R = { 1481, 1}, + .VLD4R = { 1482, 1}, + .IT = { 1483, 1}, + .TT = { 1484, 1}, + .TTT = { 1485, 1}, + .TTA = { 1486, 1}, + .TTAT = { 1487, 1}, + .SG = { 1488, 1}, + .BXNS = { 1489, 1}, + .BLXNS = { 1490, 1}, + .PAC = { 1491, 1}, + .PACBTI = { 1492, 1}, + .AUT = { 1493, 1}, + .AUTG = { 1494, 1}, + .BTI = { 1495, 1}, + .WLS = { 1496, 1}, + .WLSTP = { 1497, 1}, + .DLS = { 1498, 1}, + .DLSTP = { 1499, 1}, + .LE = { 1500, 1}, + .LETP = { 1501, 1}, + .LCTP = { 1502, 1}, + .BF = { 1503, 1}, + .BFX = { 1504, 1}, + .BFL = { 1505, 1}, + .BFLX = { 1506, 1}, + .BFCSEL = { 1507, 1}, + .CX1 = { 1508, 1}, + .CX1A = { 1509, 1}, + .CX1D = { 1510, 1}, + .CX1DA = { 1511, 1}, + .CX2 = { 1512, 1}, + .CX2A = { 1513, 1}, + .CX2D = { 1514, 1}, + .CX2DA = { 1515, 1}, + .CX3 = { 1516, 1}, + .CX3A = { 1517, 1}, + .CX3D = { 1518, 1}, + .CX3DA = { 1519, 1}, + .VCX1 = { 1520, 2}, + .VCX1A = { 1522, 2}, + .VCX2 = { 1524, 2}, + .VCX2A = { 1526, 2}, + .VCX3 = { 1528, 2}, + .VCX3A = { 1530, 2}, + .VPT = { 1532, 1}, + .VPST = { 1533, 1}, + .VPSEL = { 1534, 1}, + .VPNOT = { 1535, 1}, + .VCTP = { 1536, 1}, + .VADDV = { 1537, 1}, + .VADDVA = { 1538, 1}, + .VADDLV = { 1539, 1}, + .VADDLVA = { 1540, 1}, + .VMAXV = { 1541, 1}, + .VMAXAV = { 1542, 1}, + .VMINV = { 1543, 1}, + .VMINAV = { 1544, 1}, + .VMAXNMV = { 1545, 1}, + .VMAXNMAV = { 1546, 1}, + .VMINNMV = { 1547, 1}, + .VMINNMAV = { 1548, 1}, + .VABAV = { 1549, 1}, + .VMLADAV = { 1550, 1}, + .VMLADAVA = { 1551, 1}, + .VMLADAVX = { 1552, 1}, + .VMLADAVAX = { 1553, 1}, + .VMLALDAV = { 1554, 1}, + .VMLALDAVA = { 1555, 1}, + .VMLALDAVX = { 1556, 1}, + .VMLALDAVAX = { 1557, 1}, + .VMLSDAV = { 1558, 1}, + .VMLSDAVA = { 1559, 1}, + .VMLSDAVX = { 1560, 1}, + .VMLSDAVAX = { 1561, 1}, + .VMLSLDAV = { 1562, 1}, + .VMLSLDAVA = { 1563, 1}, + .VMLSLDAVX = { 1564, 1}, + .VMLSLDAVAX = { 1565, 1}, + .VRMLALDAVH = { 1566, 1}, + .VRMLALDAVHA = { 1567, 1}, + .VRMLALDAVHX = { 1568, 1}, + .VRMLALDAVHAX = { 1569, 1}, + .VRMLSLDAVH = { 1570, 1}, + .VRMLSLDAVHA = { 1571, 1}, + .VRMLSLDAVHX = { 1572, 1}, + .VRMLSLDAVHAX = { 1573, 1}, + .VMLAV = { 1574, 1}, + .VMLAVA = { 1575, 1}, + .VMLSV = { 1576, 1}, + .VMLSVA = { 1577, 1}, + .VCMUL = { 1578, 1}, + .VHCADD = { 1579, 2}, + .VBRSR = { 1581, 1}, + .VSHLC = { 1582, 1}, + .VDDUP = { 1583, 1}, + .VIDUP = { 1584, 1}, + .VDWDUP = { 1585, 1}, + .VIWDUP = { 1586, 1}, + .VMOVNB = { 1587, 1}, + .VMOVNT = { 1588, 1}, + .VQMOVNB = { 1589, 1}, + .VQMOVNT = { 1590, 1}, + .VQMOVUNB = { 1591, 1}, + .VQMOVUNT = { 1592, 1}, + .VSHLLB = { 1593, 1}, + .VSHLLT = { 1594, 1}, + .VMULLB = { 1595, 1}, + .VMULLT = { 1596, 1}, + .VMLALB = { 1597, 1}, + .VMLALT = { 1598, 1}, + .VMLSLB = { 1599, 1}, + .VMLSLT = { 1600, 1}, + .VSHRNB = { 1601, 1}, + .VSHRNT = { 1602, 1}, + .VRSHRNB = { 1603, 1}, + .VRSHRNT = { 1604, 1}, + .VQSHRNB = { 1605, 1}, + .VQSHRNT = { 1606, 1}, + .VQRSHRNB = { 1607, 1}, + .VQRSHRNT = { 1608, 1}, + .VQSHRUNB = { 1609, 1}, + .VQSHRUNT = { 1610, 1}, + .VQRSHRUNB = { 1611, 1}, + .VQRSHRUNT = { 1612, 1}, + .VQDMLADH = { 1613, 1}, + .VQDMLADHX = { 1614, 1}, + .VQDMLSDH = { 1615, 1}, + .VQDMLSDHX = { 1616, 1}, + .VQRDMLADH = { 1617, 1}, + .VQRDMLADHX = { 1618, 1}, + .VQRDMLSDH = { 1619, 1}, + .VQRDMLSDHX = { 1620, 1}, + .VLDRB = { 1621, 2}, + .VLDRH = { 1623, 2}, + .VLDRW = { 1625, 2}, + .VLDRD = { 1627, 2}, + .VSTRB = { 1629, 2}, + .VSTRH = { 1631, 2}, + .VSTRW = { 1633, 2}, + .VSTRD = { 1635, 2}, + .VLD20 = { 1637, 1}, + .VLD21 = { 1638, 1}, + .VLD40 = { 1639, 1}, + .VLD41 = { 1640, 1}, + .VLD42 = { 1641, 1}, + .VLD43 = { 1642, 1}, + .VST20 = { 1643, 1}, + .VST21 = { 1644, 1}, + .VST40 = { 1645, 1}, + .VST41 = { 1646, 1}, + .VST42 = { 1647, 1}, + .VST43 = { 1648, 1}, + ._COUNT = { 1649, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 4745e8f6ad5321d098a1804cf41d4dba0e2d8b9c..1b4ef0d76fdf0f4fe94248d6e8eae01468d2e2a9 100644 GIT binary patch literal 10718 zcmc&&1-MmJ)1KUPcXxMp*QL9=yE_CFNfl551q+mx7LZ1|8>9q82|~T2 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zZABYaF+atA9sNc;ol58#>a)}rsNL*)*dJi-W$sIr>In6fRHzfF3HpHjDfVZm{XGAi z{WtiQ`8)hTe}Q*L=&#~BeZ)^F>Bm%#6w-cF8EO_&{J3sM4Sg-@=o_fBsSlwMizFrDJJ5xl%+K@v-Sm6W!+eO^i#{A?ewqDI`qy!c`7P?(co!$}5&Kir zPtfltH9#H2Sq$NO_UEWS@$N;xM8mj*%YH;7)L*G%=L++0%)e8w;Sc;-v@hJd!L!2o zYqb756#e*n^nOY3-~ZFGbtH%?jwH(9!bh6BlTZ;%R1VXFgk~_;QD1b`D=J5#MS%H=GEocoQdK_&*soH}wZD!YjZOpsyBD-#kotJoL zAI3ZTgP0DmJ2=k%P*9~~L8VS(D9GtXP_4=^t9mR8r>Zl|sW Date: Fri, 28 Aug 2026 00:37:56 -0400 Subject: [PATCH 38/89] rexcode/arm64: SVE predicates, SME2 pairs and quads Chasing the SME2 gap turned up that the thing blocking it was much larger than SME2. Every predicated SVE instruction printed its predicate bare -- `p0` where the syntax needs `p0/z` or `p0/m` -- and an assembler rejects that outright. 357 forms carried one. A predicate's governing qualifier is fixed by the form, so it comes from the operand type and rides in the operand as a marker the printer reads. Predicated SVE loads and stores also write their vector as a list, so those 42 forms go through the same one-register list path the NEON work added: `ld1b { z0.b }, p0/z, [x0, x0]`. SME2 then needed three things it did not have. A predicate-as-counter register class -- SME2 governs with pn8..pn15, numbered from 8, sharing the field but not the register bank. An element size on the pair and quad operands, which cannot ride on the encoding the way the list length does, because it is what separates LD1B from LD1H. And the list length itself, which the pair/quad encodings now carry. The sweep that verified this found two real encoding bugs behind it: - 97 SVE predicated binary ops read Zm from bits 20:16, where the architecture has the opcode. `add z0.b, p0/m, z0.b, z1.b` encoded 0x04010000, which is SUB. Their masks left that opcode field free too, so each mnemonic's pattern also matched its siblings'. - AND/ORR/EOR/BIC predicated had one form apiece, labelled .d but encoding .b, since the size field at bits 23:22 was never in the pattern. Split into the four sizes. SVE/SME2 decode entries against llvm-mc: 312 byte-exact and 1 mismatched, from 211 and 78. The one left is XAR, whose four forms are legitimately bit-identical -- the element size shares a field with the shift. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 40 +- core/rexcode/isa/arm64/encoder.odin | 23 + core/rexcode/isa/arm64/encoding_types.odin | 9 + core/rexcode/isa/arm64/operands.odin | 8 + core/rexcode/isa/arm64/printer.odin | 14 +- core/rexcode/isa/arm64/registers.odin | 8 + .../tablegen/generated/decode_tables.odin | 1704 +++++++------- .../tablegen/generated/encode_tables.odin | 1972 +++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 334 +-- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 34944 -> 35112 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 49920 -> 50160 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6568 -> 6568 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 49960 -> 50200 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes .../isa/arm64/tests/pipeline_smoke.odin | 4 +- core/rexcode/isa/arm64/tests/smoke.odin | 22 +- 16 files changed, 2136 insertions(+), 2002 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 22151f0da..4fe8a8011 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -501,13 +501,15 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .PN: return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .PM: - return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} + case .PNG: + return Operand{reg = Register(REG_PN | u16(8 + ((word >> 10) & 0x7))), kind = .REGISTER, size = pqual_for_type(ot)} case .PG: - return Operand{reg = Register(REG_P | u16((word >> 10) & 0x7)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16((word >> 10) & 0x7)), kind = .REGISTER, size = pqual_for_type(ot)} case .PG4: - return Operand{reg = Register(REG_P | u16((word >> 10) & 0xF)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16((word >> 10) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .PM3: - return Operand{reg = Register(REG_P | u16((word >> 13) & 0x7)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16((word >> 13) & 0x7)), kind = .REGISTER, size = pqual_for_type(ot)} // ---- SVE immediates ---- case .SVE_IMM8: @@ -668,9 +670,11 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .ENC_ROR_SHIFT: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, + size = reg_size_for_type(ot), list_count = en == .ENC_Z_PAIR_VD ? 2 : 4} case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: - return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} + return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, + size = reg_size_for_type(ot), list_count = en == .ENC_Z_PAIR_VN ? 2 : 4} case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM: return Operand{reg = Register(REG_Z | u16((word >> 16) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot)} } @@ -703,8 +707,13 @@ reg_from_field :: #force_inline proc "contextless" ( cls = REG_V case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D: cls = REG_Z - case .P_REG, .P_REG_MERGE, .P_REG_ZERO: + case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: cls = REG_P + case .PN_REG, .PN_REG_ZERO: + cls = REG_PN + case .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D, + .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: + cls = REG_Z } // SP class needs the special hw=31 marker; everything else uses the // raw hw with the chosen class. @@ -741,10 +750,27 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .Z_REG_H: return 2 case .Z_REG_S: return 4 case .Z_REG_D: return 8 + case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO + case .P_REG_MERGE: return PQUAL_MERGE + case .Z_PAIR_B, .Z_QUAD_B: return 1 + case .Z_PAIR_H, .Z_QUAD_H: return 2 + case .Z_PAIR_S, .Z_QUAD_S: return 4 + case .Z_PAIR_D, .Z_QUAD_D: return 8 } return 4 } +// A predicate operand's governing qualifier, which the form -- not the caller +// -- decides: an SVE load zeroes, a predicated add merges. +@(private="file", require_results) +pqual_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO + case .P_REG_MERGE: return PQUAL_MERGE + } + return PQUAL_NONE +} + // ----------------------------------------------------------------------------- // Buffer-Sizing Helpers (let callers pre-size so the decode hot path never // reallocates; allocates no new buffers -- only the caller's arrays grow). diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index d1550ba96..80a7ac7d9 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -256,6 +256,15 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (op.size == 0 || op.size == 8) case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: return op.kind == .REGISTER && reg_class(op.reg) == REG_P + case .PN_REG, .PN_REG_ZERO: + return op.kind == .REGISTER && reg_class(op.reg) == REG_PN + // The first register of a pair must be even, of a quad a multiple of four. + case .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D: + return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (reg_hw(op.reg) & 0x1) == 0 && + (op.size == 0 || op.size == z_elem_size(ot)) + case .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: + return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (reg_hw(op.reg) & 0x3) == 0 && + (op.size == 0 || op.size == z_elem_size(ot)) // SME tile state (immediate-encoded tile number; user supplies the // tile index as an immediate, e.g. 0 for ZA0.S, 3 for ZA3.S). @@ -641,6 +650,9 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0xF) << 5 case .PM: return (u32(reg_hw(op.reg)) & 0xF) << 16 + case .PNG: + // The field holds pn - 8. + return ((u32(reg_hw(op.reg)) - 8) & 0x7) << 10 case .PG: // Governing predicate (3-bit slot, P0..P7 only). return (u32(reg_hw(op.reg)) & 0x7) << 10 @@ -972,3 +984,14 @@ read_u32 :: #force_inline proc "contextless" ( (u32(code[offset+2]) << 8) | u32(code[offset+3]) } + +// The SVE element-width code an SME2 pair/quad operand type carries. +@(private="file", require_results) +z_elem_size :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .Z_PAIR_B, .Z_QUAD_B: return 1 + case .Z_PAIR_H, .Z_QUAD_H: return 2 + case .Z_PAIR_S, .Z_QUAD_S: return 4 + } + return 8 +} diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 5c1e6a033..f9c559d40 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -192,6 +192,14 @@ Operand_Type :: enum u8 { // preferred spelling when cond != 111x -- with AL or NV the underlying // CSINC/CSINV/CSNEG is what an assembler writes. COND_NOT_AL, + // SME2 vector pairs and quads. The element size cannot come from the + // encoding the way the list length does, because the operand is written + // with it (`{z0.b, z1.b}`) and it is what separates LD1B from LD1H. + Z_PAIR_B, Z_PAIR_H, Z_PAIR_S, Z_PAIR_D, + Z_QUAD_B, Z_QUAD_H, Z_QUAD_S, Z_QUAD_D, + // SME2 predicate-as-counter (PN8..PN15). `_ZERO` prints the `/z` a load + // needs; a store writes it bare. + PN_REG, PN_REG_ZERO, // ---- NEON shift-by-immediate amount (encoded into immh:immb together // with the element size: left = esize+shift, right = 2*esize-shift) ---- @@ -394,6 +402,7 @@ Operand_Encoding :: enum u8 { // always names two), so it rides on the encoding rather than the operand // type -- otherwise every count would need its own type per arrangement. VD_LIST1, VD_LIST2, VD_LIST3, VD_LIST4, + PNG, // bits 10-12, predicate-as-counter (SME2) VN_LIST1, VN_LIST2, VN_LIST3, VN_LIST4, ENC_FCADD_ROT, // 1-bit rotation at bit 12 (FCADD) ENC_SVE_PRFOP, // 4-bit prefetch op at bits 3:0 (SVE PRFB/H/W/D) diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index cf4b1c1cc..f7538d093 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -196,6 +196,14 @@ op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 8} } +// A predicate register's governing qualifier, carried in Operand.size and read +// only when the register's class is REG_P. SVE writes it as a suffix -- `p0/z` +// zeroes the inactive lanes, `p0/m` leaves them alone -- and an assembler will +// not take the instruction without it where the form calls for one. +PQUAL_ZERO :: u8(1) +PQUAL_MERGE :: u8(2) +PQUAL_NONE :: u8(4) + // Arrangement codes carried in Operand.size. Element views are odd and // arrangements are multiples of 8, so the two can never be confused; 4 is the // neutral "no vector shape" value every scalar class uses. diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index cd1da1b90..26ec37a0d 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -398,6 +398,7 @@ write_sysreg :: proc(sb: ^strings.Builder, sr: System_Register, uppercase: bool) @(private="file") write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { shape := "" + sep := byte('.') switch reg_class(r) { case REG_V: switch size { @@ -422,11 +423,19 @@ write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercas case 4: shape = "s" case 8: shape = "d" } + // A predicate's suffix is its governing qualifier, and it hangs off a + // slash rather than a dot. + case REG_P, REG_PN: + sep = '/' + switch size { + case PQUAL_ZERO: shape = "z" + case PQUAL_MERGE: shape = "m" + } } if shape == "" { return } - strings.write_byte(sb, '.') + strings.write_byte(sb, sep) for i in 0..= 'a' && c <= 'z' { @@ -489,6 +498,9 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { case REG_P: strings.write_byte(sb, uppercase ? 'P' : 'p') write_decimal_u32(sb, u32(hw)) + case REG_PN: + strings.write_string(sb, uppercase ? "PN" : "pn") + write_decimal_u32(sb, u32(hw)) } } diff --git a/core/rexcode/isa/arm64/registers.odin b/core/rexcode/isa/arm64/registers.odin index 10e6040d5..b64fc8f36 100644 --- a/core/rexcode/isa/arm64/registers.odin +++ b/core/rexcode/isa/arm64/registers.odin @@ -34,6 +34,7 @@ REG_D :: 0x0900 // D0..D31 (double view) REG_Q :: 0x0A00 // Q0..Q31 (quad view) REG_Z :: 0x0B00 // Z0..Z31 SVE scalable vector (low 128 aliased with V) REG_P :: 0x0C00 // P0..P15 SVE predicate +REG_PN :: 0x0D00 // PN8..PN15 SME2 predicate-as-counter NONE :: Register(0xFFFF) @@ -45,6 +46,13 @@ NONE :: Register(0xFFFF) @(require_results) reg_is_xsp :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_XSP } @(require_results) reg_is_wsp :: #force_inline proc "contextless" (r: Register) -> bool { return reg_class(r) == REG_WSP } +// SME2 addresses its predicates as counters rather than masks, and numbers +// them from 8: the encoding holds pn - 8. +PN8 :: Register(REG_PN | 8); PN9 :: Register(REG_PN | 9) +PN10 :: Register(REG_PN | 10); PN11 :: Register(REG_PN | 11) +PN12 :: Register(REG_PN | 12); PN13 :: Register(REG_PN | 13) +PN14 :: Register(REG_PN | 14); PN15 :: Register(REG_PN | 15) + // ----------------------------------------------------------------------------- // 64-bit GPRs (X0..X30, XZR, SP) // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 0e79e5ca1..264329b69 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2498]lib.Decode_Entry{ +DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -34,46 +34,46 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, - { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, - { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, - { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, - { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .LUTI2, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {explicit_count=3} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, @@ -98,92 +98,197 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, 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{is_64=true, explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .FRINTM, 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{explicit_count=3} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, 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{explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, @@ -195,95 +300,95 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -319,20 +424,20 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, @@ -340,268 +445,175 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, - { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, + { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, @@ -614,8 +626,8 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, @@ -626,50 +638,50 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, - { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, - { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, @@ -696,12 +708,12 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, @@ -720,25 +732,25 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, @@ -759,17 +771,17 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -780,120 +792,120 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, @@ -902,227 +914,227 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, 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0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, @@ -1147,28 +1159,28 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1179,12 +1191,12 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1207,10 +1219,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1228,37 +1240,37 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -1266,190 +1278,190 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1457,266 +1469,266 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 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{explicit_count=3} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, 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{.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1741,54 +1753,54 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, @@ -1808,13 +1820,13 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, @@ -1822,8 +1834,8 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, @@ -1844,10 +1856,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, @@ -1860,8 +1872,8 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, @@ -1996,10 +2008,10 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, - { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, - { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, @@ -2027,40 +2039,40 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, @@ -2069,83 +2081,83 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, @@ -2163,24 +2175,24 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, @@ -2204,24 +2216,24 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, @@ -2233,20 +2245,20 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, @@ -2264,28 +2276,28 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, @@ -2294,20 +2306,20 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, - { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, @@ -2318,136 +2330,136 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, @@ -2455,35 +2467,35 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -2492,38 +2504,38 @@ DECODE_ENTRIES := [2498]lib.Decode_Entry{ { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, } @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 77}, - 0x02 = { 77, 496}, - 0x04 = { 573, 76}, - 0x05 = { 649, 50}, - 0x06 = { 699, 56}, - 0x07 = { 755, 1058}, - 0x08 = {1813, 16}, - 0x09 = {1829, 34}, - 0x0A = {1863, 130}, - 0x0B = {1993, 21}, - 0x0C = {2014, 167}, - 0x0D = {2181, 122}, - 0x0E = {2303, 19}, - 0x0F = {2322, 176}, + 0x02 = { 77, 508}, + 0x04 = { 585, 76}, + 0x05 = { 661, 50}, + 0x06 = { 711, 56}, + 0x07 = { 767, 1058}, + 0x08 = {1825, 16}, + 0x09 = {1841, 34}, + 0x0A = {1875, 130}, + 0x0B = {2005, 21}, + 0x0C = {2026, 167}, + 0x0D = {2193, 122}, + 0x0E = {2315, 19}, + 0x0F = {2334, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 4ca2620c1..91152d575 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2496]lib.Encoding{ +ENCODE_FORMS := [2508]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -27,10 +27,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ADDS { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, @@ -53,10 +53,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SUBS { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, @@ -83,7 +83,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, @@ -97,7 +100,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, @@ -105,13 +111,19 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, @@ -128,28 +140,28 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .LSL { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LSR { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ASR { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ROR @@ -160,13 +172,13 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .UDIV { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SDIV { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MADD { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, @@ -183,16 +195,16 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMULH { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMULH { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .CLZ { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -574,9 +586,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FSUB { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -587,9 +599,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMUL { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -600,9 +612,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIV { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -610,9 +622,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMUL { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -654,9 +666,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMIN { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -666,9 +678,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMAXNM { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -678,9 +690,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMINNM { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -690,9 +702,9 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FCVT { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, @@ -1371,10 +1383,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MLA { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1512,10 +1524,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMAX { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1523,10 +1535,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SMIN { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1534,10 +1546,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMIN { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1545,10 +1557,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABD { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1556,10 +1568,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UABD { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1567,10 +1579,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABA { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2614,10 +2626,10 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .LD4R { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SUBR - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ASRR { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -2773,78 +2785,78 @@ ENCODE_FORMS := [2496]lib.Encoding{ { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1B, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_PAIR,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1B, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_PAIR,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD,.P_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LDFF1B - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1H - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1W - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1D - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT @@ -2958,21 +2970,21 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .PRFD { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1B - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1H - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1W - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1D - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .STNT1B - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1H - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1W - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1D - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SPLICE { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX @@ -3097,13 +3109,13 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .LDAPURSW { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .BFADD - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65008000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFSUB - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65018000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMUL - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65028000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMLA { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, @@ -3128,19 +3140,19 @@ ENCODE_FORMS := [2496]lib.Encoding{ // .BFCLAMP { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMAXNM - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65048000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .BFMINNM - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65058000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .LUTI2 - { .LUTI2, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, // .LUTI4 - { .LUTI4, {.Z_PAIR,.Z_PAIR,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, // .ZIP - { .ZIP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .ZIP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, // .UZP - { .UZP, {.Z_PAIR,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .UZP, {.Z_QUAD,.Z_QUAD,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, // .TLBI_RPALOS { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_RPAOS @@ -3328,7 +3340,7 @@ ENCODE_FORMS := [2496]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2496]lib.Clobber{ +CLOBBER_FORMS := [2508]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -3405,6 +3417,9 @@ CLOBBER_FORMS := [2496]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .ANDS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, @@ -3419,6 +3434,9 @@ CLOBBER_FORMS := [2496]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .EOR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -3427,12 +3445,18 @@ CLOBBER_FORMS := [2496]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .BIC {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2, 3}}, {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, + {written={0}, read={1, 2, 3}}, // .BICS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, @@ -6659,815 +6683,815 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .MOVK = { 55, 2}, .ADR = { 57, 1}, .ADRP = { 58, 1}, - .AND = { 59, 7}, - .ANDS = { 66, 5}, - .ORR = { 71, 7}, - .EOR = { 78, 7}, - .BIC = { 85, 5}, - .BICS = { 90, 3}, - .ORN = { 93, 4}, - .EON = { 97, 2}, - .LSL = { 99, 8}, - .LSR = { 107, 8}, - .ASR = { 115, 8}, - .ROR = { 123, 4}, - .UDIV = { 127, 4}, - .SDIV = { 131, 4}, - .MADD = { 135, 2}, - .MSUB = { 137, 2}, - .SMADDL = { 139, 1}, - .SMSUBL = { 140, 1}, - .UMADDL = { 141, 1}, - .UMSUBL = { 142, 1}, - .SMULH = { 143, 5}, - .UMULH = { 148, 5}, - .CLZ = { 153, 12}, - .CLS = { 165, 12}, - .RBIT = { 177, 4}, - .REV = { 181, 7}, - .REV16 = { 188, 4}, - .REV32 = { 192, 5}, - .CSEL = { 197, 2}, - .CSINC = { 199, 2}, - .CSINV = { 201, 2}, - .CSNEG = { 203, 2}, - .CCMP = { 205, 4}, - .CCMN = { 209, 4}, - .CSET = { 213, 6}, - .CSETM = { 219, 6}, - .CINC = { 225, 6}, - .CINV = { 231, 6}, - .CNEG = { 237, 6}, - .EXTR = { 243, 2}, - .B = { 245, 1}, - .BL = { 246, 1}, - .BR = { 247, 1}, - .BLR = { 248, 1}, - .RET = { 249, 2}, - .B_EQ = { 251, 1}, - .B_NE = { 252, 1}, - .B_CS = { 253, 1}, - .B_CC = { 254, 1}, - .B_MI = { 255, 1}, - .B_PL = { 256, 1}, - .B_VS = { 257, 1}, - .B_VC = { 258, 1}, - .B_HI = { 259, 1}, - .B_LS = { 260, 1}, - .B_GE = { 261, 1}, - .B_LT = { 262, 1}, - .B_GT = { 263, 1}, - .B_LE = { 264, 1}, - .B_AL = { 265, 1}, - .B_NV = { 266, 1}, - .CBZ = { 267, 2}, - .CBNZ = { 269, 2}, - .TBZ = { 271, 1}, - .TBNZ = { 272, 1}, - .LDR = { 273, 18}, - .STR = { 291, 16}, - .LDRB = { 307, 4}, - .STRB = { 311, 4}, - .LDRSB = { 315, 4}, - .LDRH = { 319, 4}, - .STRH = { 323, 4}, - .LDRSH = { 327, 4}, - .LDRSW = { 331, 2}, - .LDP = { 333, 9}, - .STP = { 342, 9}, - .LDPSW = { 351, 3}, - .LDAR = { 354, 2}, - .STLR = { 356, 2}, - .LDARB = { 358, 1}, - .STLRB = { 359, 1}, - .LDARH = { 360, 1}, - .STLRH = { 361, 1}, - .LDXR = { 362, 2}, - .STXR = { 364, 2}, - .LDAXR = { 366, 2}, - .STLXR = { 368, 2}, - .NOP = { 370, 1}, - .YIELD = { 371, 1}, - .WFE = { 372, 1}, - .WFI = { 373, 1}, - .SEV = { 374, 1}, - .SEVL = { 375, 1}, - .HINT = { 376, 1}, - .MRS = { 377, 1}, - .MSR = { 378, 2}, - .ISB = { 380, 1}, - .DSB = { 381, 1}, - .DMB = { 382, 1}, - .SVC = { 383, 1}, - .HVC = { 384, 1}, - .SMC = { 385, 1}, - .BRK = { 386, 1}, - .HLT = { 387, 1}, - .ERET = { 388, 1}, - .FMOV = { 389, 15}, - .FABS = { 404, 11}, - .FNEG = { 415, 11}, - .FSQRT = { 426, 11}, - .FADD = { 437, 12}, - .FSUB = { 449, 12}, - .FMUL = { 461, 12}, - .FDIV = { 473, 9}, - .FNMUL = { 482, 3}, - .FMADD = { 485, 3}, - .FMSUB = { 488, 3}, - .FNMADD = { 491, 3}, - .FNMSUB = { 494, 3}, - .FCMP = { 497, 3}, - .FCMPE = { 500, 3}, - .FCSEL = { 503, 3}, - .FMAX = { 506, 11}, - .FMIN = { 517, 11}, - .FMAXNM = { 528, 11}, - .FMINNM = { 539, 11}, - .FCVT = { 550, 6}, - .SCVTF = { 556, 10}, - .UCVTF = { 566, 10}, - .FCVTZS = { 576, 10}, - .FCVTZU = { 586, 10}, - .FCVTAS = { 596, 11}, - .FCVTAU = { 607, 11}, - .FCVTNS = { 618, 11}, - .FCVTNU = { 629, 11}, - .FCVTPS = { 640, 11}, - .FCVTPU = { 651, 11}, - .FCVTMS = { 662, 11}, - .FCVTMU = { 673, 11}, - .FRINTA = { 684, 11}, - .FRINTI = { 695, 11}, - .FRINTM = { 706, 11}, - .FRINTN = { 717, 11}, - .FRINTP = { 728, 11}, - .FRINTX = { 739, 11}, - .FRINTZ = { 750, 11}, - .TST = { 761, 4}, - .LDUR = { 765, 5}, - .STUR = { 770, 5}, - .LDURB = { 775, 1}, - .STURB = { 776, 1}, - .LDURSB = { 777, 2}, - .LDURH = { 779, 1}, - .STURH = { 780, 1}, - .LDURSH = { 781, 2}, - .LDURSW = { 783, 1}, - .LDNP = { 784, 2}, - .STNP = { 786, 2}, - .LDXP = { 788, 2}, - .STXP = { 790, 2}, - .LDAXP = { 792, 2}, - .STLXP = { 794, 2}, - .LDXRB = { 796, 1}, - .STXRB = { 797, 1}, - .LDAXRB = { 798, 1}, - .STLXRB = { 799, 1}, - .LDXRH = { 800, 1}, - .STXRH = { 801, 1}, - .LDAXRH = { 802, 1}, - .STLXRH = { 803, 1}, - .LDAPR = { 804, 2}, - .LDAPRB = { 806, 1}, - .LDAPRH = { 807, 1}, - .LDADD = { 808, 2}, - .LDADDA = { 810, 2}, - .LDADDL = { 812, 2}, - .LDADDAL = { 814, 2}, - .LDCLR = { 816, 2}, - .LDCLRA = { 818, 2}, - .LDCLRL = { 820, 2}, - .LDCLRAL = { 822, 2}, - .LDEOR = { 824, 2}, - .LDEORA = { 826, 2}, - .LDEORL = { 828, 2}, - .LDEORAL = { 830, 2}, - .LDSET = { 832, 2}, - .LDSETA = { 834, 2}, - .LDSETL = { 836, 2}, - .LDSETAL = { 838, 2}, - .LDSMAX = { 840, 2}, - .LDSMAXA = { 842, 2}, - .LDSMAXL = { 844, 2}, - .LDSMAXAL = { 846, 2}, - .LDSMIN = { 848, 2}, - .LDSMINA = { 850, 2}, - .LDSMINL = { 852, 2}, - .LDSMINAL = { 854, 2}, - .LDUMAX = { 856, 2}, - .LDUMAXA = { 858, 2}, - .LDUMAXL = { 860, 2}, - .LDUMAXAL = { 862, 2}, - .LDUMIN = { 864, 2}, - .LDUMINA = { 866, 2}, - .LDUMINL = { 868, 2}, - .LDUMINAL = { 870, 2}, - .SWP = { 872, 2}, - .SWPA = { 874, 2}, - .SWPL = { 876, 2}, - .SWPAL = { 878, 2}, - .CAS = { 880, 2}, - .CASA = { 882, 2}, - .CASL = { 884, 2}, - .CASAL = { 886, 2}, - .CASB = { 888, 1}, - .CASAB = { 889, 1}, - .CASLB = { 890, 1}, - .CASALB = { 891, 1}, - .CASH = { 892, 1}, - .CASAH = { 893, 1}, - .CASLH = { 894, 1}, - .CASALH = { 895, 1}, - .CASP = { 896, 2}, - .CASPA = { 898, 2}, - .CASPL = { 900, 2}, - .CASPAL = { 902, 2}, - .PACIA = { 904, 1}, - .PACIB = { 905, 1}, - .PACDA = { 906, 1}, - .PACDB = { 907, 1}, - .PACIZA = { 908, 1}, - .PACIZB = { 909, 1}, - .PACDZA = { 910, 1}, - .PACDZB = { 911, 1}, - .AUTIA = { 912, 1}, - .AUTIB = { 913, 1}, - .AUTDA = { 914, 1}, - .AUTDB = { 915, 1}, - .AUTIZA = { 916, 1}, - .AUTIZB = { 917, 1}, - .AUTDZA = { 918, 1}, - .AUTDZB = { 919, 1}, - .PACIASP = { 920, 1}, - .PACIBSP = { 921, 1}, - .AUTIASP = { 922, 1}, - .AUTIBSP = { 923, 1}, - .PACIA1716 = { 924, 1}, - .PACIB1716 = { 925, 1}, - .AUTIA1716 = { 926, 1}, - .AUTIB1716 = { 927, 1}, - .PACGA = { 928, 1}, - .XPACI = { 929, 1}, - .XPACD = { 930, 1}, - .XPACLRI = { 931, 1}, - .RETAA = { 932, 1}, - .RETAB = { 933, 1}, - .BRAA = { 934, 1}, - .BRAB = { 935, 1}, - .BRAAZ = { 936, 1}, - .BRABZ = { 937, 1}, - .BLRAA = { 938, 1}, - .BLRAB = { 939, 1}, - .BLRAAZ = { 940, 1}, - .BLRABZ = { 941, 1}, - .ERETAA = { 942, 1}, - .ERETAB = { 943, 1}, - .BTI = { 944, 1}, - .IRG = { 945, 1}, - .ADDG = { 946, 1}, - .SUBG = { 947, 1}, - .GMI = { 948, 1}, - .SUBP = { 949, 1}, - .SUBPS = { 950, 1}, - .LDG = { 951, 1}, - .STG = { 952, 1}, - .ST2G = { 953, 1}, - .STZG = { 954, 1}, - .STZ2G = { 955, 1}, - .STGP = { 956, 1}, - .LDGM = { 957, 1}, - .STGM = { 958, 1}, - .STZGM = { 959, 1}, - .CRC32B = { 960, 1}, - .CRC32H = { 961, 1}, - .CRC32W = { 962, 1}, - .CRC32X = { 963, 1}, - .CRC32CB = { 964, 1}, - .CRC32CH = { 965, 1}, - .CRC32CW = { 966, 1}, - .CRC32CX = { 967, 1}, - .AESE = { 968, 2}, - .AESD = { 970, 2}, - .AESMC = { 972, 2}, - .AESIMC = { 974, 2}, - .SHA1H = { 976, 1}, - .SHA1C = { 977, 1}, - .SHA1P = { 978, 1}, - .SHA1M = { 979, 1}, - .SHA1SU0 = { 980, 1}, - .SHA1SU1 = { 981, 1}, - .SHA256H = { 982, 1}, - .SHA256H2 = { 983, 1}, - .SHA256SU0 = { 984, 1}, - .SHA256SU1 = { 985, 1}, - .SHA512H = { 986, 1}, - .SHA512H2 = { 987, 1}, - .SHA512SU0 = { 988, 1}, - .SHA512SU1 = { 989, 1}, - .EOR3 = { 990, 2}, - .BCAX = { 992, 2}, - .RAX1 = { 994, 1}, - .XAR = { 995, 5}, - .SM3PARTW1 = { 1000, 1}, - .SM3PARTW2 = { 1001, 1}, - .SM3SS1 = { 1002, 1}, - .SM3TT1A = { 1003, 1}, - .SM3TT1B = { 1004, 1}, - .SM3TT2A = { 1005, 1}, - .SM3TT2B = { 1006, 1}, - .SM4E = { 1007, 1}, - .SM4EKEY = { 1008, 1}, - .PMULL = { 1009, 2}, - .PMULL2 = { 1011, 2}, - .BFCVT = { 1013, 2}, - .BFDOT = { 1015, 1}, - .BFMMLA = { 1016, 1}, - .BFMLALB = { 1017, 1}, - .BFMLALT = { 1018, 1}, - .BFCVTN = { 1019, 1}, - .BFCVTN2 = { 1020, 1}, - .MUL = { 1021, 7}, - .MLA = { 1028, 6}, - .MLS = { 1034, 6}, - .NEG = { 1040, 13}, - .ABS = { 1053, 11}, - .SHADD = { 1064, 6}, - .UHADD = { 1070, 6}, - .SHSUB = { 1076, 6}, - .UHSUB = { 1082, 6}, - .SRHADD = { 1088, 6}, - .URHADD = { 1094, 6}, - .SQADD = { 1100, 11}, - .UQADD = { 1111, 11}, - .SQSUB = { 1122, 11}, - .UQSUB = { 1133, 11}, - .SMAX = { 1144, 10}, - .UMAX = { 1154, 10}, - .SMIN = { 1164, 10}, - .UMIN = { 1174, 10}, - .SABD = { 1184, 10}, - .UABD = { 1194, 10}, - .SABA = { 1204, 6}, - .UABA = { 1210, 6}, - .ADDP = { 1216, 7}, - .ADDV = { 1223, 5}, - .SADDLP = { 1228, 6}, - .UADDLP = { 1234, 6}, - .SADALP = { 1240, 6}, - .UADALP = { 1246, 6}, - .SADDLV = { 1252, 5}, - .UADDLV = { 1257, 5}, - .SMAXV = { 1262, 5}, - .UMAXV = { 1267, 5}, - .SMINV = { 1272, 5}, - .UMINV = { 1277, 5}, - .SMAXP = { 1282, 6}, - .UMAXP = { 1288, 6}, - .SMINP = { 1294, 6}, - .UMINP = { 1300, 6}, - .SADDL = { 1306, 3}, - .SADDL2 = { 1309, 3}, - .UADDL = { 1312, 3}, - .UADDL2 = { 1315, 3}, - .SSUBL = { 1318, 3}, - .SSUBL2 = { 1321, 3}, - .USUBL = { 1324, 3}, - .USUBL2 = { 1327, 3}, - .SADDW = { 1330, 3}, - .SADDW2 = { 1333, 3}, - .UADDW = { 1336, 3}, - .UADDW2 = { 1339, 3}, - .SSUBW = { 1342, 3}, - .SSUBW2 = { 1345, 3}, - .USUBW = { 1348, 3}, - .USUBW2 = { 1351, 3}, - .RADDHN = { 1354, 3}, - .RADDHN2 = { 1357, 3}, - .RSUBHN = { 1360, 3}, - .RSUBHN2 = { 1363, 3}, - .ADDHN = { 1366, 3}, - .ADDHN2 = { 1369, 3}, - .SUBHN = { 1372, 3}, - .SUBHN2 = { 1375, 3}, - .XTN = { 1378, 3}, - .XTN2 = { 1381, 3}, - .SQXTN = { 1384, 3}, - .SQXTN2 = { 1387, 3}, - .UQXTN = { 1390, 3}, - .UQXTN2 = { 1393, 3}, - .SQXTUN = { 1396, 3}, - .SQXTUN2 = { 1399, 3}, - .SMULL = { 1402, 3}, - .SMULL2 = { 1405, 3}, - .UMULL = { 1408, 3}, - .UMULL2 = { 1411, 3}, - .SMLAL = { 1414, 3}, - .SMLAL2 = { 1417, 3}, - .UMLAL = { 1420, 3}, - .UMLAL2 = { 1423, 3}, - .SMLSL = { 1426, 3}, - .SMLSL2 = { 1429, 3}, - .UMLSL = { 1432, 3}, - .UMLSL2 = { 1435, 3}, - .SQDMULL = { 1438, 2}, - .SQDMULL2 = { 1440, 2}, - .SQDMLAL = { 1442, 2}, - .SQDMLAL2 = { 1444, 2}, - .SQDMLSL = { 1446, 2}, - .SQDMLSL2 = { 1448, 2}, - .SQDMULH = { 1450, 4}, - .SQRDMULH = { 1454, 4}, - .SDOT = { 1458, 2}, - .UDOT = { 1460, 2}, - .USDOT = { 1462, 2}, - .FMLA = { 1464, 8}, - .FMLS = { 1472, 8}, - .FMULX = { 1480, 5}, - .FMAXP = { 1485, 5}, - .FMINP = { 1490, 5}, - .FMAXNMP = { 1495, 5}, - .FMINNMP = { 1500, 5}, - .FMAXV = { 1505, 3}, - .FMINV = { 1508, 3}, - .FMAXNMV = { 1511, 3}, - .FMINNMV = { 1514, 3}, - .FRECPE = { 1517, 5}, - .FRSQRTE = { 1522, 5}, - .FRECPS = { 1527, 8}, - .FRSQRTS = { 1535, 8}, - .FRECPX = { 1543, 6}, - .FADDP = { 1549, 5}, - .FCVTL = { 1554, 2}, - .FCVTL2 = { 1556, 2}, - .FCVTN = { 1558, 2}, - .FCVTN2 = { 1560, 2}, - .FCVTXN = { 1562, 1}, - .FCVTXN2 = { 1563, 1}, - .FCMEQ = { 1564, 8}, - .FCMGE = { 1572, 8}, - .FCMGT = { 1580, 8}, - .FCMLE = { 1588, 8}, - .FCMLT = { 1596, 8}, - .FACGE = { 1604, 5}, - .FACGT = { 1609, 5}, - .CMEQ = { 1614, 4}, - .CMGE = { 1618, 7}, - .CMGT = { 1625, 2}, - .CMHI = { 1627, 2}, - .CMHS = { 1629, 7}, - .CMLE = { 1636, 7}, - .CMLT = { 1643, 7}, - .CMTST = { 1650, 7}, - .MVN = { 1657, 4}, - .BIT = { 1661, 1}, - .BIF = { 1662, 1}, - .BSL = { 1663, 2}, - .SHL = { 1665, 7}, - .SQSHL = { 1672, 7}, - .SQSHLU = { 1679, 7}, - .SRSHL = { 1686, 7}, - .URSHL = { 1693, 7}, - .SSHR = { 1700, 7}, - .USHR = { 1707, 7}, - .SSRA = { 1714, 7}, - .USRA = { 1721, 7}, - .SRSHR = { 1728, 7}, - .URSHR = { 1735, 7}, - .SRSRA = { 1742, 7}, - .URSRA = { 1749, 7}, - .SSHL = { 1756, 7}, - .USHL = { 1763, 7}, - .SLI = { 1770, 7}, - .SRI = { 1777, 7}, - .SSHLL = { 1784, 3}, - .SSHLL2 = { 1787, 3}, - .USHLL = { 1790, 3}, - .USHLL2 = { 1793, 3}, - .SXTL = { 1796, 3}, - .SXTL2 = { 1799, 3}, - .UXTL = { 1802, 3}, - .UXTL2 = { 1805, 3}, - .SHRN = { 1808, 3}, - .SHRN2 = { 1811, 3}, - .RSHRN = { 1814, 3}, - .RSHRN2 = { 1817, 3}, - .SQSHRN = { 1820, 3}, - .SQSHRN2 = { 1823, 3}, - .UQSHRN = { 1826, 3}, - .UQSHRN2 = { 1829, 3}, - .SQRSHRN = { 1832, 3}, - .SQRSHRN2 = { 1835, 3}, - .UQRSHRN = { 1838, 3}, - .UQRSHRN2 = { 1841, 3}, - .SQSHRUN = { 1844, 3}, - .SQSHRUN2 = { 1847, 3}, - .SQRSHRUN = { 1850, 3}, - .SQRSHRUN2 = { 1853, 3}, - .DUP = { 1856, 18}, - .INS = { 1874, 8}, - .MOV = { 1882, 12}, - .EXT = { 1894, 4}, - .TBL = { 1898, 6}, - .TBX = { 1904, 3}, - .ZIP1 = { 1907, 12}, - .ZIP2 = { 1919, 12}, - .UZP1 = { 1931, 12}, - .UZP2 = { 1943, 12}, - .TRN1 = { 1955, 12}, - .TRN2 = { 1967, 12}, - .NOT = { 1979, 3}, - .REV64 = { 1982, 6}, - .CNT = { 1988, 6}, - .URECPE = { 1994, 2}, - .URSQRTE = { 1996, 2}, - .MOVI = { 1998, 7}, - .MVNI = { 2005, 4}, - .LD1 = { 2009, 8}, - .LD2 = { 2017, 5}, - .LD3 = { 2022, 5}, - .LD4 = { 2027, 5}, - .ST1 = { 2032, 8}, - .ST2 = { 2040, 5}, - .ST3 = { 2045, 5}, - .ST4 = { 2050, 5}, - .LD1R = { 2055, 1}, - .LD2R = { 2056, 1}, - .LD3R = { 2057, 1}, - .LD4R = { 2058, 1}, - .SUBR = { 2059, 4}, - .ASRR = { 2063, 4}, - .LSLR = { 2067, 4}, - .LSRR = { 2071, 4}, - .FTSMUL = { 2075, 3}, - .FSUBR = { 2078, 3}, - .FDIVR = { 2081, 3}, - .FNMLA = { 2084, 3}, - .FNMLS = { 2087, 3}, - .NAND = { 2090, 1}, - .NOR = { 2091, 1}, - .SEL = { 2092, 1}, - .ORRS = { 2093, 1}, - .EORS = { 2094, 1}, - .NANDS = { 2095, 1}, - .NORS = { 2096, 1}, - .ORNS = { 2097, 1}, - .MOVS = { 2098, 1}, - .PTRUE = { 2099, 1}, - .PTRUES = { 2100, 1}, - .PFALSE = { 2101, 1}, - .PFIRST = { 2102, 1}, - .PNEXT = { 2103, 1}, - .BRKA = { 2104, 1}, - .BRKB = { 2105, 1}, - .BRKAS = { 2106, 1}, - .BRKBS = { 2107, 1}, - .BRKPA = { 2108, 1}, - .BRKPB = { 2109, 1}, - .BRKN = { 2110, 1}, - .RDFFR = { 2111, 1}, - .WRFFR = { 2112, 1}, - .SETFFR = { 2113, 1}, - .CMPEQ = { 2114, 4}, - .CMPNE = { 2118, 4}, - .CMPGE = { 2122, 4}, - .CMPGT = { 2126, 4}, - .CMPLE = { 2130, 4}, - .CMPLT = { 2134, 4}, - .CMPHI = { 2138, 4}, - .CMPHS = { 2142, 4}, - .CMPLO = { 2146, 4}, - .CMPLS = { 2150, 4}, - .FCMNE = { 2154, 3}, - .FCMUO = { 2157, 3}, - .INSR = { 2160, 4}, - .CPY = { 2164, 4}, - .COMPACT = { 2168, 2}, - .LD1B = { 2170, 6}, - .LD1H = { 2176, 6}, - .LD1W = { 2182, 6}, - .LD1D = { 2188, 5}, - .LD1SB = { 2193, 3}, - .LD1SH = { 2196, 3}, - .LD1SW = { 2199, 2}, - .ST1B = { 2201, 6}, - .ST1H = { 2207, 6}, - .ST1W = { 2213, 6}, - .ST1D = { 2219, 5}, - .LDFF1B = { 2224, 1}, - .LDFF1H = { 2225, 1}, - .LDFF1W = { 2226, 1}, - .LDFF1D = { 2227, 1}, - .WHILEGE = { 2228, 1}, - .WHILEGT = { 2229, 1}, - .WHILELE = { 2230, 1}, - .WHILELT = { 2231, 1}, - .WHILEHI = { 2232, 1}, - .WHILEHS = { 2233, 1}, - .WHILELO = { 2234, 1}, - .WHILELS = { 2235, 1}, - .SQRDMLAH = { 2236, 4}, - .SQRDMLSH = { 2240, 4}, - .ADCLB = { 2244, 2}, - .ADCLT = { 2246, 2}, - .SBCLB = { 2248, 2}, - .SBCLT = { 2250, 2}, - .TBL2 = { 2252, 1}, - .MATCH = { 2253, 2}, - .NMATCH = { 2255, 2}, - .HISTCNT = { 2257, 2}, - .HISTSEG = { 2259, 1}, - .SMSTART = { 2260, 1}, - .SMSTOP = { 2261, 1}, - .RDSVL = { 2262, 1}, - .ADDHA = { 2263, 1}, - .ADDVA = { 2264, 1}, - .ZERO = { 2265, 1}, - .FMOPA = { 2266, 1}, - .FMOPS = { 2267, 1}, - .BFMOPA = { 2268, 1}, - .BFMOPS = { 2269, 1}, - .SMOPA = { 2270, 2}, - .SMOPS = { 2272, 2}, - .UMOPA = { 2274, 2}, - .UMOPS = { 2276, 2}, - .USMOPA = { 2278, 1}, - .SUMOPA = { 2279, 1}, - .LD1Q = { 2280, 1}, - .ST1Q = { 2281, 1}, - .MOVA = { 2282, 2}, - .FCMLA = { 2284, 4}, - .FCADD = { 2288, 4}, - .PRFB = { 2292, 1}, - .PRFH = { 2293, 1}, - .PRFW = { 2294, 1}, - .PRFD = { 2295, 1}, - .LDNT1B = { 2296, 1}, - .LDNT1H = { 2297, 1}, - .LDNT1W = { 2298, 1}, - .LDNT1D = { 2299, 1}, - .STNT1B = { 2300, 1}, - .STNT1H = { 2301, 1}, - .STNT1W = { 2302, 1}, - .STNT1D = { 2303, 1}, - .SPLICE = { 2304, 1}, - .INDEX = { 2305, 4}, - .BSL1N = { 2309, 1}, - .BSL2N = { 2310, 1}, - .NBSL = { 2311, 1}, - .PMUL = { 2312, 1}, - .PMULLB = { 2313, 1}, - .PMULLT = { 2314, 1}, - .BFCVTNT = { 2315, 1}, - .LDRAA = { 2316, 2}, - .LDRAB = { 2318, 2}, - .TSTART = { 2320, 1}, - .TCOMMIT = { 2321, 1}, - .TCANCEL = { 2322, 1}, - .TTEST = { 2323, 1}, - .WFET = { 2324, 1}, - .WFIT = { 2325, 1}, - .BC_EQ = { 2326, 1}, - .BC_NE = { 2327, 1}, - .BC_CS = { 2328, 1}, - .BC_CC = { 2329, 1}, - .BC_MI = { 2330, 1}, - .BC_PL = { 2331, 1}, - .BC_VS = { 2332, 1}, - .BC_VC = { 2333, 1}, - .BC_HI = { 2334, 1}, - .BC_LS = { 2335, 1}, - .BC_GE = { 2336, 1}, - .BC_LT = { 2337, 1}, - .BC_GT = { 2338, 1}, - .BC_LE = { 2339, 1}, - .BC_AL = { 2340, 1}, - .BC_NV = { 2341, 1}, - .UXTB = { 2342, 1}, - .UXTH = { 2343, 1}, - .UXTW = { 2344, 1}, - .SXTB = { 2345, 1}, - .SXTH = { 2346, 1}, - .SXTW = { 2347, 1}, - .ADC = { 2348, 2}, - .ADCS = { 2350, 2}, - .SBC = { 2352, 2}, - .SBCS = { 2354, 2}, - .NGC = { 2356, 2}, - .NGCS = { 2358, 2}, - .LDAPUR = { 2360, 2}, - .STLUR = { 2362, 2}, - .LDAPURB = { 2364, 1}, - .STLURB = { 2365, 1}, - .LDAPURH = { 2366, 1}, - .STLURH = { 2367, 1}, - .LDAPURSB = { 2368, 2}, - .LDAPURSH = { 2370, 2}, - .LDAPURSW = { 2372, 1}, - .BFADD = { 2373, 2}, - .BFSUB = { 2375, 2}, - .BFMUL = { 2377, 2}, - .BFMLA = { 2379, 1}, - .BFMLS = { 2380, 1}, - .SB = { 2381, 1}, - .CSDB = { 2382, 1}, - .DGH = { 2383, 1}, - .PSB_CSYNC = { 2384, 1}, - .TSB_CSYNC = { 2385, 1}, - .BTI_J = { 2386, 1}, - .BTI_C = { 2387, 1}, - .BTI_JC = { 2388, 1}, - .BFCLAMP = { 2389, 1}, - .BFMAXNM = { 2390, 1}, - .BFMINNM = { 2391, 1}, - .LUTI2 = { 2392, 1}, - .LUTI4 = { 2393, 1}, - .ZIP = { 2394, 2}, - .UZP = { 2396, 2}, - .TLBI_RPALOS = { 2398, 1}, - .TLBI_RPAOS = { 2399, 1}, - .AT_S1E1A = { 2400, 1}, - .DC_CIPAPA = { 2401, 1}, - .DC_CIGDPAPA = { 2402, 1}, - .TLBI_PAALL = { 2403, 1}, - .TLBI_PAALLOS = { 2404, 1}, - .AMX_LDX = { 2405, 1}, - .AMX_LDY = { 2406, 1}, - .AMX_STX = { 2407, 1}, - .AMX_STY = { 2408, 1}, - .AMX_LDZ = { 2409, 1}, - .AMX_STZ = { 2410, 1}, - .AMX_LDZI = { 2411, 1}, - .AMX_STZI = { 2412, 1}, - .AMX_EXTRX = { 2413, 1}, - .AMX_EXTRY = { 2414, 1}, - .AMX_FMA64 = { 2415, 1}, - .AMX_FMS64 = { 2416, 1}, - .AMX_FMA32 = { 2417, 1}, - .AMX_FMS32 = { 2418, 1}, - .AMX_MAC16 = { 2419, 1}, - .AMX_FMA16 = { 2420, 1}, - .AMX_FMS16 = { 2421, 1}, - .AMX_SET = { 2422, 1}, - .AMX_CLR = { 2423, 1}, - .AMX_VECINT = { 2424, 1}, - .AMX_VECFP = { 2425, 1}, - .AMX_MATINT = { 2426, 1}, - .AMX_MATFP = { 2427, 1}, - .AMX_GENLUT = { 2428, 1}, - .CPYP = { 2429, 1}, - .CPYM = { 2430, 1}, - .CPYE = { 2431, 1}, - .CPYFP = { 2432, 1}, - .CPYFM = { 2433, 1}, - .CPYFE = { 2434, 1}, - .SETP = { 2435, 1}, - .SETM = { 2436, 1}, - .SETE = { 2437, 1}, - .DC_IVAC = { 2438, 1}, - .DC_ISW = { 2439, 1}, - .DC_CSW = { 2440, 1}, - .DC_CISW = { 2441, 1}, - .DC_ZVA = { 2442, 1}, - .DC_CVAC = { 2443, 1}, - .DC_CVAU = { 2444, 1}, - .DC_CIVAC = { 2445, 1}, - .IC_IALLUIS = { 2446, 1}, - .IC_IALLU = { 2447, 1}, - .IC_IVAU = { 2448, 1}, - .AT_S1E1R = { 2449, 1}, - .AT_S1E1W = { 2450, 1}, - .AT_S1E0R = { 2451, 1}, - .AT_S1E0W = { 2452, 1}, - .AT_S1E2R = { 2453, 1}, - .AT_S1E2W = { 2454, 1}, - .AT_S1E3R = { 2455, 1}, - .AT_S1E3W = { 2456, 1}, - .AT_S12E1R = { 2457, 1}, - .AT_S12E1W = { 2458, 1}, - .AT_S12E0R = { 2459, 1}, - .AT_S12E0W = { 2460, 1}, - .TLBI_VMALLE1 = { 2461, 1}, - .TLBI_VMALLE1IS = { 2462, 1}, - .TLBI_VAE1 = { 2463, 1}, - .TLBI_VAE1IS = { 2464, 1}, - .TLBI_ASIDE1 = { 2465, 1}, - .TLBI_ASIDE1IS = { 2466, 1}, - .TLBI_VAAE1 = { 2467, 1}, - .TLBI_VAAE1IS = { 2468, 1}, - .TLBI_VALE1 = { 2469, 1}, - .TLBI_VALE1IS = { 2470, 1}, - .TLBI_VAALE1 = { 2471, 1}, - .TLBI_VAALE1IS = { 2472, 1}, - .TLBI_ALLE1 = { 2473, 1}, - .TLBI_ALLE1IS = { 2474, 1}, - .TLBI_ALLE2 = { 2475, 1}, - .TLBI_ALLE2IS = { 2476, 1}, - .TLBI_ALLE3 = { 2477, 1}, - .TLBI_ALLE3IS = { 2478, 1}, - .PRFM = { 2479, 2}, - .PRFUM = { 2481, 1}, - .NEGS = { 2482, 2}, - .CMP = { 2484, 6}, - .CMN = { 2490, 6}, + .AND = { 59, 10}, + .ANDS = { 69, 5}, + .ORR = { 74, 10}, + .EOR = { 84, 10}, + .BIC = { 94, 8}, + .BICS = { 102, 3}, + .ORN = { 105, 4}, + .EON = { 109, 2}, + .LSL = { 111, 8}, + .LSR = { 119, 8}, + .ASR = { 127, 8}, + .ROR = { 135, 4}, + .UDIV = { 139, 4}, + .SDIV = { 143, 4}, + .MADD = { 147, 2}, + .MSUB = { 149, 2}, + .SMADDL = { 151, 1}, + .SMSUBL = { 152, 1}, + .UMADDL = { 153, 1}, + .UMSUBL = { 154, 1}, + .SMULH = { 155, 5}, + .UMULH = { 160, 5}, + .CLZ = { 165, 12}, + .CLS = { 177, 12}, + .RBIT = { 189, 4}, + .REV = { 193, 7}, + .REV16 = { 200, 4}, + .REV32 = { 204, 5}, + .CSEL = { 209, 2}, + .CSINC = { 211, 2}, + .CSINV = { 213, 2}, + .CSNEG = { 215, 2}, + .CCMP = { 217, 4}, + .CCMN = { 221, 4}, + .CSET = { 225, 6}, + .CSETM = { 231, 6}, + .CINC = { 237, 6}, + .CINV = { 243, 6}, + .CNEG = { 249, 6}, + .EXTR = { 255, 2}, + .B = { 257, 1}, + .BL = { 258, 1}, + .BR = { 259, 1}, + .BLR = { 260, 1}, + .RET = { 261, 2}, + .B_EQ = { 263, 1}, + .B_NE = { 264, 1}, + .B_CS = { 265, 1}, + .B_CC = { 266, 1}, + .B_MI = { 267, 1}, + .B_PL = { 268, 1}, + .B_VS = { 269, 1}, + .B_VC = { 270, 1}, + .B_HI = { 271, 1}, + .B_LS = { 272, 1}, + .B_GE = { 273, 1}, + .B_LT = { 274, 1}, + .B_GT = { 275, 1}, + .B_LE = { 276, 1}, + .B_AL = { 277, 1}, + .B_NV = { 278, 1}, + .CBZ = { 279, 2}, + .CBNZ = { 281, 2}, + .TBZ = { 283, 1}, + .TBNZ = { 284, 1}, + .LDR = { 285, 18}, + .STR = { 303, 16}, + .LDRB = { 319, 4}, + .STRB = { 323, 4}, + .LDRSB = { 327, 4}, + .LDRH = { 331, 4}, + .STRH = { 335, 4}, + .LDRSH = { 339, 4}, + .LDRSW = { 343, 2}, + .LDP = { 345, 9}, + .STP = { 354, 9}, + .LDPSW = { 363, 3}, + .LDAR = { 366, 2}, + .STLR = { 368, 2}, + .LDARB = { 370, 1}, + .STLRB = { 371, 1}, + .LDARH = { 372, 1}, + .STLRH = { 373, 1}, + .LDXR = { 374, 2}, + .STXR = { 376, 2}, + .LDAXR = { 378, 2}, + .STLXR = { 380, 2}, + .NOP = { 382, 1}, + .YIELD = { 383, 1}, + .WFE = { 384, 1}, + .WFI = { 385, 1}, + .SEV = { 386, 1}, + .SEVL = { 387, 1}, + .HINT = { 388, 1}, + .MRS = { 389, 1}, + .MSR = { 390, 2}, + .ISB = { 392, 1}, + .DSB = { 393, 1}, + .DMB = { 394, 1}, + .SVC = { 395, 1}, + .HVC = { 396, 1}, + .SMC = { 397, 1}, + .BRK = { 398, 1}, + .HLT = { 399, 1}, + .ERET = { 400, 1}, + .FMOV = { 401, 15}, + .FABS = { 416, 11}, + .FNEG = { 427, 11}, + .FSQRT = { 438, 11}, + .FADD = { 449, 12}, + .FSUB = { 461, 12}, + .FMUL = { 473, 12}, + .FDIV = { 485, 9}, + .FNMUL = { 494, 3}, + .FMADD = { 497, 3}, + .FMSUB = { 500, 3}, + .FNMADD = { 503, 3}, + .FNMSUB = { 506, 3}, + .FCMP = { 509, 3}, + .FCMPE = { 512, 3}, + .FCSEL = { 515, 3}, + .FMAX = { 518, 11}, + .FMIN = { 529, 11}, + .FMAXNM = { 540, 11}, + .FMINNM = { 551, 11}, + .FCVT = { 562, 6}, + .SCVTF = { 568, 10}, + .UCVTF = { 578, 10}, + .FCVTZS = { 588, 10}, + .FCVTZU = { 598, 10}, + .FCVTAS = { 608, 11}, + .FCVTAU = { 619, 11}, + .FCVTNS = { 630, 11}, + .FCVTNU = { 641, 11}, + .FCVTPS = { 652, 11}, + .FCVTPU = { 663, 11}, + .FCVTMS = { 674, 11}, + .FCVTMU = { 685, 11}, + .FRINTA = { 696, 11}, + .FRINTI = { 707, 11}, + .FRINTM = { 718, 11}, + .FRINTN = { 729, 11}, + .FRINTP = { 740, 11}, + .FRINTX = { 751, 11}, + .FRINTZ = { 762, 11}, + .TST = { 773, 4}, + .LDUR = { 777, 5}, + .STUR = { 782, 5}, + .LDURB = { 787, 1}, + .STURB = { 788, 1}, + .LDURSB = { 789, 2}, + .LDURH = { 791, 1}, + .STURH = { 792, 1}, + .LDURSH = { 793, 2}, + .LDURSW = { 795, 1}, + .LDNP = { 796, 2}, + .STNP = { 798, 2}, + .LDXP = { 800, 2}, + .STXP = { 802, 2}, + .LDAXP = { 804, 2}, + .STLXP = { 806, 2}, + .LDXRB = { 808, 1}, + .STXRB = { 809, 1}, + .LDAXRB = { 810, 1}, + .STLXRB = { 811, 1}, + .LDXRH = { 812, 1}, + .STXRH = { 813, 1}, + .LDAXRH = { 814, 1}, + .STLXRH = { 815, 1}, + .LDAPR = { 816, 2}, + .LDAPRB = { 818, 1}, + .LDAPRH = { 819, 1}, + .LDADD = { 820, 2}, + .LDADDA = { 822, 2}, + .LDADDL = { 824, 2}, + .LDADDAL = { 826, 2}, + .LDCLR = { 828, 2}, + .LDCLRA = { 830, 2}, + .LDCLRL = { 832, 2}, + .LDCLRAL = { 834, 2}, + .LDEOR = { 836, 2}, + .LDEORA = { 838, 2}, + .LDEORL = { 840, 2}, + .LDEORAL = { 842, 2}, + .LDSET = { 844, 2}, + .LDSETA = { 846, 2}, + .LDSETL = { 848, 2}, + .LDSETAL = { 850, 2}, + .LDSMAX = { 852, 2}, + .LDSMAXA = { 854, 2}, + .LDSMAXL = { 856, 2}, + .LDSMAXAL = { 858, 2}, + .LDSMIN = { 860, 2}, + .LDSMINA = { 862, 2}, + .LDSMINL = { 864, 2}, + .LDSMINAL = { 866, 2}, + .LDUMAX = { 868, 2}, + .LDUMAXA = { 870, 2}, + .LDUMAXL = { 872, 2}, + .LDUMAXAL = { 874, 2}, + .LDUMIN = { 876, 2}, + .LDUMINA = { 878, 2}, + .LDUMINL = { 880, 2}, + .LDUMINAL = { 882, 2}, + .SWP = { 884, 2}, + .SWPA = { 886, 2}, + .SWPL = { 888, 2}, + .SWPAL = { 890, 2}, + .CAS = { 892, 2}, + .CASA = { 894, 2}, + .CASL = { 896, 2}, + .CASAL = { 898, 2}, + .CASB = { 900, 1}, + .CASAB = { 901, 1}, + .CASLB = { 902, 1}, + .CASALB = { 903, 1}, + .CASH = { 904, 1}, + .CASAH = { 905, 1}, + .CASLH = { 906, 1}, + .CASALH = { 907, 1}, + .CASP = { 908, 2}, + .CASPA = { 910, 2}, + .CASPL = { 912, 2}, + .CASPAL = { 914, 2}, + .PACIA = { 916, 1}, + .PACIB = { 917, 1}, + .PACDA = { 918, 1}, + .PACDB = { 919, 1}, + .PACIZA = { 920, 1}, + .PACIZB = { 921, 1}, + .PACDZA = { 922, 1}, + .PACDZB = { 923, 1}, + .AUTIA = { 924, 1}, + .AUTIB = { 925, 1}, + .AUTDA = { 926, 1}, + .AUTDB = { 927, 1}, + .AUTIZA = { 928, 1}, + .AUTIZB = { 929, 1}, + .AUTDZA = { 930, 1}, + .AUTDZB = { 931, 1}, + .PACIASP = { 932, 1}, + .PACIBSP = { 933, 1}, + .AUTIASP = { 934, 1}, + .AUTIBSP = { 935, 1}, + .PACIA1716 = { 936, 1}, + .PACIB1716 = { 937, 1}, + .AUTIA1716 = { 938, 1}, + .AUTIB1716 = { 939, 1}, + .PACGA = { 940, 1}, + .XPACI = { 941, 1}, + .XPACD = { 942, 1}, + .XPACLRI = { 943, 1}, + .RETAA = { 944, 1}, + .RETAB = { 945, 1}, + .BRAA = { 946, 1}, + .BRAB = { 947, 1}, + .BRAAZ = { 948, 1}, + .BRABZ = { 949, 1}, + .BLRAA = { 950, 1}, + .BLRAB = { 951, 1}, + .BLRAAZ = { 952, 1}, + .BLRABZ = { 953, 1}, + .ERETAA = { 954, 1}, + .ERETAB = { 955, 1}, + .BTI = { 956, 1}, + .IRG = { 957, 1}, + .ADDG = { 958, 1}, + .SUBG = { 959, 1}, + .GMI = { 960, 1}, + .SUBP = { 961, 1}, + .SUBPS = { 962, 1}, + .LDG = { 963, 1}, + .STG = { 964, 1}, + .ST2G = { 965, 1}, + .STZG = { 966, 1}, + .STZ2G = { 967, 1}, + .STGP = { 968, 1}, + .LDGM = { 969, 1}, + .STGM = { 970, 1}, + .STZGM = { 971, 1}, + .CRC32B = { 972, 1}, + .CRC32H = { 973, 1}, + .CRC32W = { 974, 1}, + .CRC32X = { 975, 1}, + .CRC32CB = { 976, 1}, + .CRC32CH = { 977, 1}, + .CRC32CW = { 978, 1}, + .CRC32CX = { 979, 1}, + .AESE = { 980, 2}, + .AESD = { 982, 2}, + .AESMC = { 984, 2}, + .AESIMC = { 986, 2}, + .SHA1H = { 988, 1}, + .SHA1C = { 989, 1}, + .SHA1P = { 990, 1}, + .SHA1M = { 991, 1}, + .SHA1SU0 = { 992, 1}, + .SHA1SU1 = { 993, 1}, + .SHA256H = { 994, 1}, + .SHA256H2 = { 995, 1}, + .SHA256SU0 = { 996, 1}, + .SHA256SU1 = { 997, 1}, + .SHA512H = { 998, 1}, + .SHA512H2 = { 999, 1}, + .SHA512SU0 = { 1000, 1}, + .SHA512SU1 = { 1001, 1}, + .EOR3 = { 1002, 2}, + .BCAX = { 1004, 2}, + .RAX1 = { 1006, 1}, + .XAR = { 1007, 5}, + .SM3PARTW1 = { 1012, 1}, + .SM3PARTW2 = { 1013, 1}, + .SM3SS1 = { 1014, 1}, + .SM3TT1A = { 1015, 1}, + .SM3TT1B = { 1016, 1}, + .SM3TT2A = { 1017, 1}, + .SM3TT2B = { 1018, 1}, + .SM4E = { 1019, 1}, + .SM4EKEY = { 1020, 1}, + .PMULL = { 1021, 2}, + .PMULL2 = { 1023, 2}, + .BFCVT = { 1025, 2}, + .BFDOT = { 1027, 1}, + .BFMMLA = { 1028, 1}, + .BFMLALB = { 1029, 1}, + .BFMLALT = { 1030, 1}, + .BFCVTN = { 1031, 1}, + .BFCVTN2 = { 1032, 1}, + .MUL = { 1033, 7}, + .MLA = { 1040, 6}, + .MLS = { 1046, 6}, + .NEG = { 1052, 13}, + .ABS = { 1065, 11}, + .SHADD = { 1076, 6}, + .UHADD = { 1082, 6}, + .SHSUB = { 1088, 6}, + .UHSUB = { 1094, 6}, + .SRHADD = { 1100, 6}, + .URHADD = { 1106, 6}, + .SQADD = { 1112, 11}, + .UQADD = { 1123, 11}, + .SQSUB = { 1134, 11}, + .UQSUB = { 1145, 11}, + .SMAX = { 1156, 10}, + .UMAX = { 1166, 10}, + .SMIN = { 1176, 10}, + .UMIN = { 1186, 10}, + .SABD = { 1196, 10}, + .UABD = { 1206, 10}, + .SABA = { 1216, 6}, + .UABA = { 1222, 6}, + .ADDP = { 1228, 7}, + .ADDV = { 1235, 5}, + .SADDLP = { 1240, 6}, + .UADDLP = { 1246, 6}, + .SADALP = { 1252, 6}, + .UADALP = { 1258, 6}, + .SADDLV = { 1264, 5}, + .UADDLV = { 1269, 5}, + .SMAXV = { 1274, 5}, + .UMAXV = { 1279, 5}, + .SMINV = { 1284, 5}, + .UMINV = { 1289, 5}, + .SMAXP = { 1294, 6}, + .UMAXP = { 1300, 6}, + .SMINP = { 1306, 6}, + .UMINP = { 1312, 6}, + .SADDL = { 1318, 3}, + .SADDL2 = { 1321, 3}, + .UADDL = { 1324, 3}, + .UADDL2 = { 1327, 3}, + .SSUBL = { 1330, 3}, + .SSUBL2 = { 1333, 3}, + .USUBL = { 1336, 3}, + .USUBL2 = { 1339, 3}, + .SADDW = { 1342, 3}, + .SADDW2 = { 1345, 3}, + .UADDW = { 1348, 3}, + .UADDW2 = { 1351, 3}, + .SSUBW = { 1354, 3}, + .SSUBW2 = { 1357, 3}, + .USUBW = { 1360, 3}, + .USUBW2 = { 1363, 3}, + .RADDHN = { 1366, 3}, + .RADDHN2 = { 1369, 3}, + .RSUBHN = { 1372, 3}, + .RSUBHN2 = { 1375, 3}, + .ADDHN = { 1378, 3}, + .ADDHN2 = { 1381, 3}, + .SUBHN = { 1384, 3}, + .SUBHN2 = { 1387, 3}, + .XTN = { 1390, 3}, + .XTN2 = { 1393, 3}, + .SQXTN = { 1396, 3}, + .SQXTN2 = { 1399, 3}, + .UQXTN = { 1402, 3}, + .UQXTN2 = { 1405, 3}, + .SQXTUN = { 1408, 3}, + .SQXTUN2 = { 1411, 3}, + .SMULL = { 1414, 3}, + .SMULL2 = { 1417, 3}, + .UMULL = { 1420, 3}, + .UMULL2 = { 1423, 3}, + .SMLAL = { 1426, 3}, + .SMLAL2 = { 1429, 3}, + .UMLAL = { 1432, 3}, + .UMLAL2 = { 1435, 3}, + .SMLSL = { 1438, 3}, + .SMLSL2 = { 1441, 3}, + .UMLSL = { 1444, 3}, + .UMLSL2 = { 1447, 3}, + .SQDMULL = { 1450, 2}, + .SQDMULL2 = { 1452, 2}, + .SQDMLAL = { 1454, 2}, + .SQDMLAL2 = { 1456, 2}, + .SQDMLSL = { 1458, 2}, + .SQDMLSL2 = { 1460, 2}, + .SQDMULH = { 1462, 4}, + .SQRDMULH = { 1466, 4}, + .SDOT = { 1470, 2}, + .UDOT = { 1472, 2}, + .USDOT = { 1474, 2}, + .FMLA = { 1476, 8}, + .FMLS = { 1484, 8}, + .FMULX = { 1492, 5}, + .FMAXP = { 1497, 5}, + .FMINP = { 1502, 5}, + .FMAXNMP = { 1507, 5}, + .FMINNMP = { 1512, 5}, + .FMAXV = { 1517, 3}, + .FMINV = { 1520, 3}, + .FMAXNMV = { 1523, 3}, + .FMINNMV = { 1526, 3}, + .FRECPE = { 1529, 5}, + .FRSQRTE = { 1534, 5}, + .FRECPS = { 1539, 8}, + .FRSQRTS = { 1547, 8}, + .FRECPX = { 1555, 6}, + .FADDP = { 1561, 5}, + .FCVTL = { 1566, 2}, + .FCVTL2 = { 1568, 2}, + .FCVTN = { 1570, 2}, + .FCVTN2 = { 1572, 2}, + .FCVTXN = { 1574, 1}, + .FCVTXN2 = { 1575, 1}, + .FCMEQ = { 1576, 8}, + .FCMGE = { 1584, 8}, + .FCMGT = { 1592, 8}, + .FCMLE = { 1600, 8}, + .FCMLT = { 1608, 8}, + .FACGE = { 1616, 5}, + .FACGT = { 1621, 5}, + .CMEQ = { 1626, 4}, + .CMGE = { 1630, 7}, + .CMGT = { 1637, 2}, + .CMHI = { 1639, 2}, + .CMHS = { 1641, 7}, + .CMLE = { 1648, 7}, + .CMLT = { 1655, 7}, + .CMTST = { 1662, 7}, + .MVN = { 1669, 4}, + .BIT = { 1673, 1}, + .BIF = { 1674, 1}, + .BSL = { 1675, 2}, + .SHL = { 1677, 7}, + .SQSHL = { 1684, 7}, + .SQSHLU = { 1691, 7}, + .SRSHL = { 1698, 7}, + .URSHL = { 1705, 7}, + .SSHR = { 1712, 7}, + .USHR = { 1719, 7}, + .SSRA = { 1726, 7}, + .USRA = { 1733, 7}, + .SRSHR = { 1740, 7}, + .URSHR = { 1747, 7}, + .SRSRA = { 1754, 7}, + .URSRA = { 1761, 7}, + .SSHL = { 1768, 7}, + .USHL = { 1775, 7}, + .SLI = { 1782, 7}, + .SRI = { 1789, 7}, + .SSHLL = { 1796, 3}, + .SSHLL2 = { 1799, 3}, + .USHLL = { 1802, 3}, + .USHLL2 = { 1805, 3}, + .SXTL = { 1808, 3}, + .SXTL2 = { 1811, 3}, + .UXTL = { 1814, 3}, + .UXTL2 = { 1817, 3}, + .SHRN = { 1820, 3}, + .SHRN2 = { 1823, 3}, + .RSHRN = { 1826, 3}, + .RSHRN2 = { 1829, 3}, + .SQSHRN = { 1832, 3}, + .SQSHRN2 = { 1835, 3}, + .UQSHRN = { 1838, 3}, + .UQSHRN2 = { 1841, 3}, + .SQRSHRN = { 1844, 3}, + .SQRSHRN2 = { 1847, 3}, + .UQRSHRN = { 1850, 3}, + .UQRSHRN2 = { 1853, 3}, + .SQSHRUN = { 1856, 3}, + .SQSHRUN2 = { 1859, 3}, + .SQRSHRUN = { 1862, 3}, + .SQRSHRUN2 = { 1865, 3}, + .DUP = { 1868, 18}, + .INS = { 1886, 8}, + .MOV = { 1894, 12}, + .EXT = { 1906, 4}, + .TBL = { 1910, 6}, + .TBX = { 1916, 3}, + .ZIP1 = { 1919, 12}, + .ZIP2 = { 1931, 12}, + .UZP1 = { 1943, 12}, + .UZP2 = { 1955, 12}, + .TRN1 = { 1967, 12}, + .TRN2 = { 1979, 12}, + .NOT = { 1991, 3}, + .REV64 = { 1994, 6}, + .CNT = { 2000, 6}, + .URECPE = { 2006, 2}, + .URSQRTE = { 2008, 2}, + .MOVI = { 2010, 7}, + .MVNI = { 2017, 4}, + .LD1 = { 2021, 8}, + .LD2 = { 2029, 5}, + .LD3 = { 2034, 5}, + .LD4 = { 2039, 5}, + .ST1 = { 2044, 8}, + .ST2 = { 2052, 5}, + .ST3 = { 2057, 5}, + .ST4 = { 2062, 5}, + .LD1R = { 2067, 1}, + .LD2R = { 2068, 1}, + .LD3R = { 2069, 1}, + .LD4R = { 2070, 1}, + .SUBR = { 2071, 4}, + .ASRR = { 2075, 4}, + .LSLR = { 2079, 4}, + .LSRR = { 2083, 4}, + .FTSMUL = { 2087, 3}, + .FSUBR = { 2090, 3}, + .FDIVR = { 2093, 3}, + .FNMLA = { 2096, 3}, + .FNMLS = { 2099, 3}, + .NAND = { 2102, 1}, + .NOR = { 2103, 1}, + .SEL = { 2104, 1}, + .ORRS = { 2105, 1}, + .EORS = { 2106, 1}, + .NANDS = { 2107, 1}, + .NORS = { 2108, 1}, + .ORNS = { 2109, 1}, + .MOVS = { 2110, 1}, + .PTRUE = { 2111, 1}, + .PTRUES = { 2112, 1}, + .PFALSE = { 2113, 1}, + .PFIRST = { 2114, 1}, + .PNEXT = { 2115, 1}, + .BRKA = { 2116, 1}, + .BRKB = { 2117, 1}, + .BRKAS = { 2118, 1}, + .BRKBS = { 2119, 1}, + .BRKPA = { 2120, 1}, + .BRKPB = { 2121, 1}, + .BRKN = { 2122, 1}, + .RDFFR = { 2123, 1}, + .WRFFR = { 2124, 1}, + .SETFFR = { 2125, 1}, + .CMPEQ = { 2126, 4}, + .CMPNE = { 2130, 4}, + .CMPGE = { 2134, 4}, + .CMPGT = { 2138, 4}, + .CMPLE = { 2142, 4}, + .CMPLT = { 2146, 4}, + .CMPHI = { 2150, 4}, + .CMPHS = { 2154, 4}, + .CMPLO = { 2158, 4}, + .CMPLS = { 2162, 4}, + .FCMNE = { 2166, 3}, + .FCMUO = { 2169, 3}, + .INSR = { 2172, 4}, + .CPY = { 2176, 4}, + .COMPACT = { 2180, 2}, + .LD1B = { 2182, 6}, + .LD1H = { 2188, 6}, + .LD1W = { 2194, 6}, + .LD1D = { 2200, 5}, + .LD1SB = { 2205, 3}, + .LD1SH = { 2208, 3}, + .LD1SW = { 2211, 2}, + .ST1B = { 2213, 6}, + .ST1H = { 2219, 6}, + .ST1W = { 2225, 6}, + .ST1D = { 2231, 5}, + .LDFF1B = { 2236, 1}, + .LDFF1H = { 2237, 1}, + .LDFF1W = { 2238, 1}, + .LDFF1D = { 2239, 1}, + .WHILEGE = { 2240, 1}, + .WHILEGT = { 2241, 1}, + .WHILELE = { 2242, 1}, + .WHILELT = { 2243, 1}, + .WHILEHI = { 2244, 1}, + .WHILEHS = { 2245, 1}, + .WHILELO = { 2246, 1}, + .WHILELS = { 2247, 1}, + .SQRDMLAH = { 2248, 4}, + .SQRDMLSH = { 2252, 4}, + .ADCLB = { 2256, 2}, + .ADCLT = { 2258, 2}, + .SBCLB = { 2260, 2}, + .SBCLT = { 2262, 2}, + .TBL2 = { 2264, 1}, + .MATCH = { 2265, 2}, + .NMATCH = { 2267, 2}, + .HISTCNT = { 2269, 2}, + .HISTSEG = { 2271, 1}, + .SMSTART = { 2272, 1}, + .SMSTOP = { 2273, 1}, + .RDSVL = { 2274, 1}, + .ADDHA = { 2275, 1}, + .ADDVA = { 2276, 1}, + .ZERO = { 2277, 1}, + .FMOPA = { 2278, 1}, + .FMOPS = { 2279, 1}, + .BFMOPA = { 2280, 1}, + .BFMOPS = { 2281, 1}, + .SMOPA = { 2282, 2}, + .SMOPS = { 2284, 2}, + .UMOPA = { 2286, 2}, + .UMOPS = { 2288, 2}, + .USMOPA = { 2290, 1}, + .SUMOPA = { 2291, 1}, + .LD1Q = { 2292, 1}, + .ST1Q = { 2293, 1}, + .MOVA = { 2294, 2}, + .FCMLA = { 2296, 4}, + .FCADD = { 2300, 4}, + .PRFB = { 2304, 1}, + .PRFH = { 2305, 1}, + .PRFW = { 2306, 1}, + .PRFD = { 2307, 1}, + .LDNT1B = { 2308, 1}, + .LDNT1H = { 2309, 1}, + .LDNT1W = { 2310, 1}, + .LDNT1D = { 2311, 1}, + .STNT1B = { 2312, 1}, + .STNT1H = { 2313, 1}, + .STNT1W = { 2314, 1}, + .STNT1D = { 2315, 1}, + .SPLICE = { 2316, 1}, + .INDEX = { 2317, 4}, + .BSL1N = { 2321, 1}, + .BSL2N = { 2322, 1}, + .NBSL = { 2323, 1}, + .PMUL = { 2324, 1}, + .PMULLB = { 2325, 1}, + .PMULLT = { 2326, 1}, + .BFCVTNT = { 2327, 1}, + .LDRAA = { 2328, 2}, + .LDRAB = { 2330, 2}, + .TSTART = { 2332, 1}, + .TCOMMIT = { 2333, 1}, + .TCANCEL = { 2334, 1}, + .TTEST = { 2335, 1}, + .WFET = { 2336, 1}, + .WFIT = { 2337, 1}, + .BC_EQ = { 2338, 1}, + .BC_NE = { 2339, 1}, + .BC_CS = { 2340, 1}, + .BC_CC = { 2341, 1}, + .BC_MI = { 2342, 1}, + .BC_PL = { 2343, 1}, + .BC_VS = { 2344, 1}, + .BC_VC = { 2345, 1}, + .BC_HI = { 2346, 1}, + .BC_LS = { 2347, 1}, + .BC_GE = { 2348, 1}, + .BC_LT = { 2349, 1}, + .BC_GT = { 2350, 1}, + .BC_LE = { 2351, 1}, + .BC_AL = { 2352, 1}, + .BC_NV = { 2353, 1}, + .UXTB = { 2354, 1}, + .UXTH = { 2355, 1}, + .UXTW = { 2356, 1}, + .SXTB = { 2357, 1}, + .SXTH = { 2358, 1}, + .SXTW = { 2359, 1}, + .ADC = { 2360, 2}, + .ADCS = { 2362, 2}, + .SBC = { 2364, 2}, + .SBCS = { 2366, 2}, + .NGC = { 2368, 2}, + .NGCS = { 2370, 2}, + .LDAPUR = { 2372, 2}, + .STLUR = { 2374, 2}, + .LDAPURB = { 2376, 1}, + .STLURB = { 2377, 1}, + .LDAPURH = { 2378, 1}, + .STLURH = { 2379, 1}, + .LDAPURSB = { 2380, 2}, + .LDAPURSH = { 2382, 2}, + .LDAPURSW = { 2384, 1}, + .BFADD = { 2385, 2}, + .BFSUB = { 2387, 2}, + .BFMUL = { 2389, 2}, + .BFMLA = { 2391, 1}, + .BFMLS = { 2392, 1}, + .SB = { 2393, 1}, + .CSDB = { 2394, 1}, + .DGH = { 2395, 1}, + .PSB_CSYNC = { 2396, 1}, + .TSB_CSYNC = { 2397, 1}, + .BTI_J = { 2398, 1}, + .BTI_C = { 2399, 1}, + .BTI_JC = { 2400, 1}, + .BFCLAMP = { 2401, 1}, + .BFMAXNM = { 2402, 1}, + .BFMINNM = { 2403, 1}, + .LUTI2 = { 2404, 1}, + .LUTI4 = { 2405, 1}, + .ZIP = { 2406, 2}, + .UZP = { 2408, 2}, + .TLBI_RPALOS = { 2410, 1}, + .TLBI_RPAOS = { 2411, 1}, + .AT_S1E1A = { 2412, 1}, + .DC_CIPAPA = { 2413, 1}, + .DC_CIGDPAPA = { 2414, 1}, + .TLBI_PAALL = { 2415, 1}, + .TLBI_PAALLOS = { 2416, 1}, + .AMX_LDX = { 2417, 1}, + .AMX_LDY = { 2418, 1}, + .AMX_STX = { 2419, 1}, + .AMX_STY = { 2420, 1}, + .AMX_LDZ = { 2421, 1}, + .AMX_STZ = { 2422, 1}, + .AMX_LDZI = { 2423, 1}, + .AMX_STZI = { 2424, 1}, + .AMX_EXTRX = { 2425, 1}, + .AMX_EXTRY = { 2426, 1}, + .AMX_FMA64 = { 2427, 1}, + .AMX_FMS64 = { 2428, 1}, + .AMX_FMA32 = { 2429, 1}, + .AMX_FMS32 = { 2430, 1}, + .AMX_MAC16 = { 2431, 1}, + .AMX_FMA16 = { 2432, 1}, + .AMX_FMS16 = { 2433, 1}, + .AMX_SET = { 2434, 1}, + .AMX_CLR = { 2435, 1}, + .AMX_VECINT = { 2436, 1}, + .AMX_VECFP = { 2437, 1}, + .AMX_MATINT = { 2438, 1}, + .AMX_MATFP = { 2439, 1}, + .AMX_GENLUT = { 2440, 1}, + .CPYP = { 2441, 1}, + .CPYM = { 2442, 1}, + .CPYE = { 2443, 1}, + .CPYFP = { 2444, 1}, + .CPYFM = { 2445, 1}, + .CPYFE = { 2446, 1}, + .SETP = { 2447, 1}, + .SETM = { 2448, 1}, + .SETE = { 2449, 1}, + .DC_IVAC = { 2450, 1}, + .DC_ISW = { 2451, 1}, + .DC_CSW = { 2452, 1}, + .DC_CISW = { 2453, 1}, + .DC_ZVA = { 2454, 1}, + .DC_CVAC = { 2455, 1}, + .DC_CVAU = { 2456, 1}, + .DC_CIVAC = { 2457, 1}, + .IC_IALLUIS = { 2458, 1}, + .IC_IALLU = { 2459, 1}, + .IC_IVAU = { 2460, 1}, + .AT_S1E1R = { 2461, 1}, + .AT_S1E1W = { 2462, 1}, + .AT_S1E0R = { 2463, 1}, + .AT_S1E0W = { 2464, 1}, + .AT_S1E2R = { 2465, 1}, + .AT_S1E2W = { 2466, 1}, + .AT_S1E3R = { 2467, 1}, + .AT_S1E3W = { 2468, 1}, + .AT_S12E1R = { 2469, 1}, + .AT_S12E1W = { 2470, 1}, + .AT_S12E0R = { 2471, 1}, + .AT_S12E0W = { 2472, 1}, + .TLBI_VMALLE1 = { 2473, 1}, + .TLBI_VMALLE1IS = { 2474, 1}, + .TLBI_VAE1 = { 2475, 1}, + .TLBI_VAE1IS = { 2476, 1}, + .TLBI_ASIDE1 = { 2477, 1}, + .TLBI_ASIDE1IS = { 2478, 1}, + .TLBI_VAAE1 = { 2479, 1}, + .TLBI_VAAE1IS = { 2480, 1}, + .TLBI_VALE1 = { 2481, 1}, + .TLBI_VALE1IS = { 2482, 1}, + .TLBI_VAALE1 = { 2483, 1}, + .TLBI_VAALE1IS = { 2484, 1}, + .TLBI_ALLE1 = { 2485, 1}, + .TLBI_ALLE1IS = { 2486, 1}, + .TLBI_ALLE2 = { 2487, 1}, + .TLBI_ALLE2IS = { 2488, 1}, + .TLBI_ALLE3 = { 2489, 1}, + .TLBI_ALLE3IS = { 2490, 1}, + .PRFM = { 2491, 2}, + .PRFUM = { 2493, 1}, + .NEGS = { 2494, 2}, + .CMP = { 2496, 6}, + .CMN = { 2502, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index c48c29090..f1dc7abde 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -122,10 +122,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04000000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04400000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04800000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .ADDS = { {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -150,10 +150,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04010000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04410000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04810000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SUBS = { {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -187,7 +187,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ANDS = { @@ -203,7 +206,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04180000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EOR = { @@ -212,14 +218,20 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04190000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BIC = { {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BICS = { @@ -240,30 +252,30 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .LSL = { {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04138000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04538000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04938000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .LSR = { {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04118000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04518000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04918000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, .ASR = { {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04108000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04508000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04908000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, @@ -276,14 +288,14 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .UDIV = { {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04950000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SDIV = { {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04940000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MADD = { {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, @@ -307,17 +319,17 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .SMULH = { {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04120000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04520000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04920000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMULH = { {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04130000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04530000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04930000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .CLZ = { {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, @@ -787,9 +799,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65408000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65808000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -801,9 +813,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65418000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65818000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -815,9 +827,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65428000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65828000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -826,9 +838,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654D8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658D8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -879,9 +891,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65468000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65868000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, @@ -892,9 +904,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65478000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65878000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, @@ -905,9 +917,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65448000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65848000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, @@ -918,9 +930,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65458000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65858000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -1803,10 +1815,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04100000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04500000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04900000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .MLA = { {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, @@ -1959,10 +1971,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04080000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04480000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04880000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMAX = { {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -1971,10 +1983,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04090000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04490000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04890000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SMIN = { {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -1983,10 +1995,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UMIN = { {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -1995,10 +2007,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABD = { {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -2007,10 +2019,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .UABD = { {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -2019,10 +2031,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .SABA = { {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, @@ -3254,10 +3266,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04030000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04430000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04830000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, }, .ASRR = { {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, @@ -3461,92 +3473,92 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -3705,28 +3717,28 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, @@ -3906,15 +3918,15 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65008000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65018000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65028000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { @@ -3951,24 +3963,24 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65048000, 0xFFFFE000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI2, {.Z_PAIR_B, .Z_PAIR_B, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI4, {.Z_PAIR_B, .Z_PAIR_B, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index 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z=iM6|O9A6PcJDw2_fpg0-sc^aeXze+dE57{(foNpTC>y~`eDBm)PEuq+DqAL*{=PRLn z%O$poVwX#76~!)>-l{0}I}+PNvELD0kLY*?J(O>y=$c5kQt~xXzLio-6UD9)T`TEU ziLO<2+;3})vtKQ-?G(FOV%sTpwba*6u~!T07RJ4GQ|#5^(OtmxJt$QUKlllM-vb-V zoNm{=C~g#%C3di|kl0u3-wXNJMq*RpHvo`D#J(!5h1l06HYRqJt;hc qyUf<-V-t$KT$m|fzRM-ngcy6dc$gU36{1T>cZKK@(TQ&XJ^ml~a!3sT diff --git a/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin b/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin index 0cc877c3a7618282f937affa829bdc71d6d69339..f0773c8f57bf774daf84d4a9bc9ff6329d2acd3f 100644 GIT binary patch literal 64 zcmZQz@MQo2Uxq)7Alj43hhZv{5yNpN3x@wpN-T=(0t|-iN({m5O$=ArMHybPFK3v@ PQN_T`Da;_pxq$%yMUx9C literal 64 zcmZQz@MQo2Uxp8iAljD6hoO_nh+#LA1;b}1B^FV30R~leB?fo)CWe#jq73)gmov0- PR5ASL5M~hK+`s?;JY)-t diff --git a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin index 115c0fe0a..f7d0d8ff8 100644 --- a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin @@ -503,7 +503,7 @@ run_pipeline_tests :: proc() { // ---- 19. SVE predicated: ADD Z0.S, P0/M, Z0.S, Z1.S -------------------- // bits = 0x04800000 | (Pg=0<<10) | (Zm=1<<16) | Zdn=0 - // = 0x04810000 + // = 0x04800020 { clear(&relocs); clear(&errors) for i in 0.. Date: Fri, 28 Aug 2026 04:53:11 -0400 Subject: [PATCH 39/89] rexcode/arm64: XAR was never ambiguous, and the SVE element sizes were unreachable I had this wrong. XAR is fully determined by the word: `tszh:tszl:imm3` holds `2*esize - shift`, and since the shift is in [1, esize] the four element sizes occupy disjoint ranges (.b 8-15, .h 16-31, .s 32-63, .d 64-127), so the highest set bit names the size. Nothing is ambiguous; the table just could not say "the element size is in an operand field". So it was four identical (bits, mask) entries standing in for one. Encode already worked -- the matcher picked among them by the operand -- but decode had four entries tied on every sort key, and which one won was whatever the unstable sort left. It answered `.s`, the fall-through, because reg_size_for_type had no case at all for them. Now there is one form. The Z operands' element size is read out of the word (VD_TSZ/VN_TSZ), and the shift's is taken from the register the caller passed rather than from the form -- which means the packer needs to see the instruction, not just its operand, since this field genuinely couples two of them. The tsz rule itself lived twice, as arithmetic in the encoder and a threshold ladder in the decoder; it is one helper now. Downstream, and much larger: every SVE element size collapsed onto a single builder, exactly as the NEON arrangements did. 264 of the 470 forms with a Z operand were unreachable -- `inst_xar_z_z_z_i` could only ever make .b. The size is in the name now (inst_add_zb_zb_zb and friends), which took the builders from 1847 to 2141. The sweep that verified it found two more: - A predicate that is the destination is written with an element size, not a qualifier: `cmpge p0.b, p1/z, ...`. 106 forms printed a bare `p0`. The two suffixes are told apart by encoding -- PD against PG -- and by disjoint size codes. - SVE's indexed FMLA/FMLS printed their lane as `, #1` rather than `[1]`; those encodings were simply missing from the lane-index set. The decode sort is now total (it ties on table order last), so which entry wins can no longer vary between builds. SVE/SME2 decode entries against llvm-mc: 370 byte-exact and 0 mismatched, from 211 and 78 at the start of the session. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 45 +- core/rexcode/isa/arm64/encoder.odin | 35 +- core/rexcode/isa/arm64/encoding_types.odin | 13 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 2290 +++++++++++------ core/rexcode/isa/arm64/operands.odin | 55 + core/rexcode/isa/arm64/printer.odin | 9 +- core/rexcode/isa/arm64/tablegen/gen.odin | 9 +- .../tablegen/generated/decode_tables.odin | 1681 ++++++------ .../tablegen/generated/encode_tables.odin | 1228 +++++---- .../isa/arm64/tablegen/instruction_table.odin | 217 +- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 35112 -> 35070 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 50160 -> 50100 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6568 -> 6568 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 50200 -> 50140 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes .../arm64/tools/gen_mnemonic_builders.odin | 63 +- 16 files changed, 3182 insertions(+), 2463 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 4fe8a8011..bf406aedb 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -274,15 +274,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .NEON_LANE_D: return Operand{immediate = i64((word >> 30) & 0x1), kind = .IMMEDIATE, size = LANE_INDEX} case .SVE_XAR_SHIFT: - tszh := (word >> 22) & 0x3 - tszl := (word >> 19) & 0x3 - v := i64((tszh << 5) | (tszl << 3) | ((word >> 16) & 0x7)) - tsize := (tszh << 2) | tszl - esize: i64 = 8 - if tsize >= 8 { esize = 64 } - else if tsize >= 4 { esize = 32 } - else if tsize >= 2 { esize = 16 } - return Operand{immediate = 2 * esize - v, kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(sve_tsz_shift(sve_tsz_field(word))), kind = .IMMEDIATE, size = 1} // ---- Memory operand variants ------------------------------------------ case .OFFSET_BASE_U12: @@ -450,6 +442,14 @@ extract_operand_inline :: #force_inline proc "contextless" ( // REG_V here decoded `add z0.d, z0.d, z0.d` as a V register. case .VD: return reg_from_field(word, 0, ot) + // The element size is not in the static pattern -- it shares the tsz field + // with the shift -- so it has to be read out of the word. + case .VD_TSZ: + return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, + size = sve_esize_code(sve_tsz_esize(sve_tsz_field(word)))} + case .VN_TSZ: + return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, + size = sve_esize_code(sve_tsz_esize(sve_tsz_field(word)))} case .VN: return reg_from_field(word, 5, ot) case .VD_LIST1, .VD_LIST2, .VD_LIST3, .VD_LIST4: @@ -497,7 +497,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- SVE predicate slots ---- case .PD: - return Operand{reg = Register(REG_P | u16(word & 0xF)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16(word & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .PN: return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .PM: @@ -588,13 +588,13 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- SVE indexed lane field ---- case .SVE_FMLA_IDX_H: v := ((word >> 22) & 0x1) << 2 | ((word >> 19) & 0x3) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = LANE_INDEX} case .SVE_FMLA_IDX_S: v := (word >> 19) & 0x3 - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = LANE_INDEX} case .SVE_FMLA_IDX_D: v := (word >> 20) & 0x1 - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = LANE_INDEX} // ---- SME tile slice descriptor (round-trip back to the packed form) ---- // @@ -705,9 +705,10 @@ reg_from_field :: #force_inline proc "contextless" ( .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: cls = REG_V - case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D: + case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_REG_ANY: cls = REG_Z - case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: + case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV, + .P_REG_B, .P_REG_H, .P_REG_S, .P_REG_D: cls = REG_P case .PN_REG, .PN_REG_ZERO: cls = REG_PN @@ -752,6 +753,10 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .Z_REG_D: return 8 case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO case .P_REG_MERGE: return PQUAL_MERGE + case .P_REG_B: return PSHAPE_B + case .P_REG_H: return PSHAPE_H + case .P_REG_S: return PSHAPE_S + case .P_REG_D: return PSHAPE_D case .Z_PAIR_B, .Z_QUAD_B: return 1 case .Z_PAIR_H, .Z_QUAD_H: return 2 case .Z_PAIR_S, .Z_QUAD_S: return 4 @@ -767,6 +772,10 @@ pqual_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { #partial switch ot { case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO case .P_REG_MERGE: return PQUAL_MERGE + case .P_REG_B: return PSHAPE_B + case .P_REG_H: return PSHAPE_H + case .P_REG_S: return PSHAPE_S + case .P_REG_D: return PSHAPE_D } return PQUAL_NONE } @@ -796,3 +805,9 @@ decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic if inst_info != nil { reserve(inst_info, len(inst_info) + n) } if label_defs != nil { reserve(label_defs, len(label_defs) + n) } } + +// The packed tszh:tszl:imm3 value an SVE shift-by-immediate carries. +@(private="file", require_results) +sve_tsz_field :: #force_inline proc "contextless" (word: u32) -> u32 { + return ((word >> 22) & 0x3) << 5 | ((word >> 19) & 0x3) << 3 | ((word >> 16) & 0x7) +} diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 80a7ac7d9..48b43bec4 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -141,10 +141,10 @@ encode_one_inline :: #force_inline proc( } word = form.bits - if form.enc[0] != .NONE { word |= pack_operand_inline(&inst.ops[0], form.enc[0], form, pc, inst_idx, relocs) } - if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], form, pc, inst_idx, relocs) } - if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], form, pc, inst_idx, relocs) } - if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], form, pc, inst_idx, relocs) } + if form.enc[0] != .NONE { word |= pack_operand_inline(&inst.ops[0], form.enc[0], form, pc, inst_idx, relocs, inst) } + if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], form, pc, inst_idx, relocs, inst) } + if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], form, pc, inst_idx, relocs, inst) } + if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], form, pc, inst_idx, relocs, inst) } return word, true } @@ -254,11 +254,14 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (op.size == 0 || op.size == 4) case .Z_REG_D: return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (op.size == 0 || op.size == 8) - case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: + case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV, + .P_REG_B, .P_REG_H, .P_REG_S, .P_REG_D: return op.kind == .REGISTER && reg_class(op.reg) == REG_P case .PN_REG, .PN_REG_ZERO: return op.kind == .REGISTER && reg_class(op.reg) == REG_PN // The first register of a pair must be even, of a quad a multiple of four. + case .Z_REG_ANY: + return op.kind == .REGISTER && reg_class(op.reg) == REG_Z case .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D: return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (reg_hw(op.reg) & 0x1) == 0 && (op.size == 0 || op.size == z_elem_size(ot)) @@ -275,12 +278,6 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .IMMEDIATE case .LSL_SHIFT_W, .LSL_SHIFT_X, .ROR_SHIFT: return op.kind == .IMMEDIATE - case .Z_PAIR: - // SME2 vector pair: first reg must be even (Z0, Z2, ..., Z30). - return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (reg_hw(op.reg) & 0x1) == 0 - case .Z_QUAD: - // SME2 vector quad: first reg must be multiple of 4. - return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && (reg_hw(op.reg) & 0x3) == 0 case .SME_PATTERN, .SVE_PATTERN: return op.kind == .IMMEDIATE // SME tile slice (packed immediate descriptor; see encoding_types.odin) @@ -372,6 +369,10 @@ pack_operand_inline :: #force_inline proc( pc: u32, inst_idx: u16, relocs: ^[dynamic]Relocation, + // Most encodings pack one operand in isolation. SVE's tsz field does not: + // it holds an element size and a shift together, and the size belongs to a + // different operand than the shift. + inst: ^Instruction, ) -> u32 { switch enc { case .NONE, .IMPL: @@ -529,9 +530,9 @@ pack_operand_inline :: #force_inline proc( return ((bit >> 5) & 1) << 31 | (bit & 0x1F) << 19 // ---- NEON / SIMD register slots (alias of RD/RN/RM/RA bit positions) -- - case .VD, .VD_LIST1, .VD_LIST2, .VD_LIST3, .VD_LIST4: + case .VD, .VD_TSZ, .VD_LIST1, .VD_LIST2, .VD_LIST3, .VD_LIST4: return (u32(reg_hw(op.reg)) & 0x1F) << 0 - case .VN, .VN_LIST1, .VN_LIST2, .VN_LIST3, .VN_LIST4: + case .VN, .VN_TSZ, .VN_LIST1, .VN_LIST2, .VN_LIST3, .VN_LIST4: return (u32(reg_hw(op.reg)) & 0x1F) << 5 case .VM: return (u32(reg_hw(op.reg)) & 0x1F) << 16 @@ -602,8 +603,12 @@ pack_operand_inline :: #force_inline proc( // SVE2 XAR rotate amount: V = 2*esize - amount, split tszh:tszl:imm3. case .SVE_XAR_SHIFT: - esize := vec_esize(form.ops[0]) - v := (2 * esize - u32(op.immediate)) & 0x7F + // The element size shares this field with the shift, so it cannot also + // select between forms -- there is one form, and the size comes from + // the register the caller passed. + esize := u32(inst.ops[0].size) * 8 + if esize == 0 || esize > 64 { esize = vec_esize(form.ops[0]) } + v := sve_tsz_pack(esize, u32(op.immediate)) return ((v >> 5) & 0x3) << 22 | ((v >> 3) & 0x3) << 19 | (v & 0x7) << 16 // NEON MOVI/FMOV immediate split: abc at bits 18-16, defgh at bits 9-5. diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index f9c559d40..88da7d460 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -137,8 +137,6 @@ Operand_Type :: enum u8 { LSL_SHIFT_W, // shift amount 0..31 for LSL Wd, Wn, #imm (32-bit) LSL_SHIFT_X, // shift amount 0..63 for LSL Xd, Xn, #imm (64-bit) ROR_SHIFT, // shift amount for ROR (alias of EXTR), goes to imms - Z_PAIR, // SME2 vector pair {Zn, Zn+1} โ€” register number must be even - Z_QUAD, // SME2 vector quad {Zn, Zn+1, Zn+2, Zn+3} โ€” number multiple of 4 // ---- Immediates ---- IMM_12, // 12-bit unsigned (ADD/SUB imm; carries optional LSL #12 in size byte) @@ -195,11 +193,17 @@ Operand_Type :: enum u8 { // SME2 vector pairs and quads. The element size cannot come from the // encoding the way the list length does, because the operand is written // with it (`{z0.b, z1.b}`) and it is what separates LD1B from LD1H. + // A Z register of any element size, for the forms where the size is not in + // the static pattern and so cannot select between forms (SVE2 XAR). + Z_REG_ANY, Z_PAIR_B, Z_PAIR_H, Z_PAIR_S, Z_PAIR_D, Z_QUAD_B, Z_QUAD_H, Z_QUAD_S, Z_QUAD_D, // SME2 predicate-as-counter (PN8..PN15). `_ZERO` prints the `/z` a load // needs; a store writes it bare. PN_REG, PN_REG_ZERO, + // A predicate that is written with an element size because it is the + // instruction's destination (`cmpge p0.b, p1/z, ...`). + P_REG_B, P_REG_H, P_REG_S, P_REG_D, // ---- NEON shift-by-immediate amount (encoded into immh:immb together // with the element size: left = esize+shift, right = 2*esize-shift) ---- @@ -403,6 +407,11 @@ Operand_Encoding :: enum u8 { // type -- otherwise every count would need its own type per arrangement. VD_LIST1, VD_LIST2, VD_LIST3, VD_LIST4, PNG, // bits 10-12, predicate-as-counter (SME2) + // A Z register whose element size is not in the static pattern but in the + // instruction's own tsz field, so decode has to read it out of the word + // rather than take it from the form (SVE2 XAR). + VD_TSZ, // bits 0-4 + VN_TSZ, // bits 5-9 VN_LIST1, VN_LIST2, VN_LIST3, VN_LIST4, ENC_FCADD_ROT, // 1-bit rotation at bit 12 (FCADD) ENC_SVE_PRFOP, // 4-bit prefetch op at bits 3:0 (SVE PRFB/H/W/D) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index d0e11ccc6..545d6f969 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -31,8 +31,14 @@ inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_add_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_add_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_add_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_add_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_add_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_add_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_add_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_add_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_add_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_add_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -43,8 +49,14 @@ emit_add_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_add_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v8b_v8b_v8b(dst, src, src2)) } emit_add_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v4h_v4h_v4h(dst, src, src2)) } emit_add_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v2s_v2s_v2s(dst, src, src2)) } -emit_add_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_z_z_z(rz, rz2, rz3)) } -emit_add_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_add_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_zb_zb_zb(rz, rz2, rz3)) } +emit_add_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_zh_zh_zh(rz, rz2, rz3)) } +emit_add_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_zs_zs_zs(rz, rz2, rz3)) } +emit_add_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_add_zd_zd_zd(rz, rz2, rz3)) } +emit_add_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_add_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_add_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_add_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } @@ -58,8 +70,14 @@ inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_sub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_sub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sub_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_sub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_sub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_sub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -67,8 +85,14 @@ emit_sub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Inst emit_sub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v8h_v8h_v8h(dst, src, src2)) } emit_sub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v4s_v4s_v4s(dst, src, src2)) } emit_sub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v2d_v2d_v2d(dst, src, src2)) } -emit_sub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_z_z_z(rz, rz2, rz3)) } -emit_sub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_sub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_zb_zb_zb(rz, rz2, rz3)) } +emit_sub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_zh_zh_zh(rz, rz2, rz3)) } +emit_sub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_zs_zs_zs(rz, rz2, rz3)) } +emit_sub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sub_zd_zd_zd(rz, rz2, rz3)) } +emit_sub_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_sub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_sub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_sub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } @@ -88,89 +112,135 @@ emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Inst inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_and_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_and_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_and_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } emit_and_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v16b_v16b_v16b(dst, src, src2)) } -emit_and_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_and_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_and_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_and_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_and_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_and_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_and_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_p_p(rz, rz2, rz3, rz4)) } inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_ands_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } -emit_ands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_ands_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_ph_p_p_p(rz, rz2, rz3, rz4)) } inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_orr_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } -emit_orr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_orr_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_orr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_orr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_orr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_orr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_orr_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_ps_p_p_p(rz, rz2, rz3, rz4)) } inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_eor_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_eor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } emit_eor_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v16b_v16b_v16b(dst, src, src2)) } -emit_eor_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_eor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_eor_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_eor_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_eor_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_eor_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_eor_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_pb_p_p_p(rz, rz2, rz3, rz4)) } inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bic_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_bic_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_bic_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bic_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v16b_v16b_v16b(dst, src, src2)) } -emit_bic_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bic_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_bic_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_bic_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_bic_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_bic_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_bic_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_p_p(rz, rz2, rz3, rz4)) } inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bics_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_bics_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_bics_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_ph_p_p_p(rz, rz2, rz3, rz4)) } inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orn_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } -emit_orn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_p_p_p_p(rz, rz2, rz3, rz4)) } +emit_orn_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_ps_p_p_p(rz, rz2, rz3, rz4)) } inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } -inst_lsl_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsl_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsl_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_lsl_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_lsl_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } -emit_lsl_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsl_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_lsl_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_lsl_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_lsl_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } -inst_lsr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_lsr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_lsr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } -emit_lsr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_lsr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_lsr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_lsr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_lsr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } -inst_asr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_asr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_asr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_asr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_asr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } -emit_asr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_asr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_asr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_asr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_asr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_asr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_i(dst, src, imm)) } inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ROR, dst, src, src2) } inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR, dst, src, imm) } emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -inst_udiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_udiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_udiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -emit_udiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_udiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_udiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -inst_sdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_sdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_sdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -emit_sdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_sdiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_sdiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } @@ -184,13 +254,25 @@ emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Inst inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -inst_smulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_smulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_smulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } -emit_smulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_smulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_smulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_smulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_smulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -inst_umulh_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_umulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_umulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } -emit_umulh_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_umulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_umulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_umulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_umulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -198,7 +280,10 @@ inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_clz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_clz_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_clz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_clz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_clz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } emit_clz_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8b_v8b(dst, src)) } emit_clz_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v16b_v16b(dst, src)) } @@ -206,7 +291,10 @@ emit_clz_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Inst emit_clz_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8h_v8h(dst, src)) } emit_clz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v2s_v2s(dst, src)) } emit_clz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v4s_v4s(dst, src)) } -emit_clz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_z_p_z(rz, rz2, rz3)) } +emit_clz_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zb_p_zb(rz, rz2, rz3)) } +emit_clz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zh_p_zh(rz, rz2, rz3)) } +emit_clz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zs_p_zs(rz, rz2, rz3)) } +emit_clz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zd_p_zd(rz, rz2, rz3)) } inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -214,7 +302,10 @@ inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cls_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_cls_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_cls_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_cls_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_cls_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } emit_cls_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8b_v8b(dst, src)) } emit_cls_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v16b_v16b(dst, src)) } @@ -222,7 +313,10 @@ emit_cls_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cls_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8h_v8h(dst, src)) } emit_cls_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v2s_v2s(dst, src)) } emit_cls_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v4s_v4s(dst, src)) } -emit_cls_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_z_p_z(rz, rz2, rz3)) } +emit_cls_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zb_p_zb(rz, rz2, rz3)) } +emit_cls_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zh_p_zh(rz, rz2, rz3)) } +emit_cls_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zs_p_zs(rz, rz2, rz3)) } +emit_cls_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zd_p_zd(rz, rz2, rz3)) } inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -230,11 +324,17 @@ emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_rbit_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v8b_v8b(dst, src)) } emit_rbit_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v16b_v16b(dst, src)) } inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -inst_rev_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -inst_rev_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}}} } +inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}}} } +inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}}} } +inst_rev_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -emit_rev_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_z_z(rz, rz2)) } -emit_rev_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_p_p(rz, rz2)) } +emit_rev_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zb_zb(rz, rz2)) } +emit_rev_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zh_zh(rz, rz2)) } +emit_rev_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zs_zs(rz, rz2)) } +emit_rev_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zd_zd(rz, rz2)) } +emit_rev_pb_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_pb_p(rz, rz2)) } inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -333,21 +433,21 @@ inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_zb_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_ldr_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } -emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } -emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } +emit_ldr_zb_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_zb_m(rz, mem)) } +emit_ldr_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_ps_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_zb_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +inst_str_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } -emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } -emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } +emit_str_zb_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_zb_m(rz, mem)) } +emit_str_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_ps_m(rz, mem)) } emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } @@ -447,88 +547,128 @@ inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fabs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fabs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fabs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_fabs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } emit_fabs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2s_v2s(dst, src)) } emit_fabs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4s_v4s(dst, src)) } emit_fabs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2d_v2d(dst, src)) } emit_fabs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4h_v4h(dst, src)) } emit_fabs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v8h_v8h(dst, src)) } -emit_fabs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_z_p_z(rz, rz2, rz3)) } +emit_fabs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zh_p_zh(rz, rz2, rz3)) } +emit_fabs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zs_p_zs(rz, rz2, rz3)) } +emit_fabs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zd_p_zd(rz, rz2, rz3)) } inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fneg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fneg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fneg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_fneg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } emit_fneg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2s_v2s(dst, src)) } emit_fneg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4s_v4s(dst, src)) } emit_fneg_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2d_v2d(dst, src)) } emit_fneg_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4h_v4h(dst, src)) } emit_fneg_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v8h_v8h(dst, src)) } -emit_fneg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_z_p_z(rz, rz2, rz3)) } +emit_fneg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zh_p_zh(rz, rz2, rz3)) } +emit_fneg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zs_p_zs(rz, rz2, rz3)) } +emit_fneg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zd_p_zd(rz, rz2, rz3)) } inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fsqrt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fsqrt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fsqrt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_fsqrt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } emit_fsqrt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2s_v2s(dst, src)) } emit_fsqrt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4s_v4s(dst, src)) } emit_fsqrt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2d_v2d(dst, src)) } emit_fsqrt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4h_v4h(dst, src)) } emit_fsqrt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v8h_v8h(dst, src)) } -emit_fsqrt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_z_p_z(rz, rz2, rz3)) } +emit_fsqrt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zh_p_zh(rz, rz2, rz3)) } +emit_fsqrt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zs_p_zs(rz, rz2, rz3)) } +emit_fsqrt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zd_p_zd(rz, rz2, rz3)) } inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_fadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_fadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fadd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fadd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } emit_fadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2s_v2s_v2s(dst, src, src2)) } emit_fadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v4s_v4s_v4s(dst, src, src2)) } emit_fadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2d_v2d_v2d(dst, src, src2)) } -emit_fadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_z_z_z(rz, rz2, rz3)) } -emit_fadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_zh_zh_zh(rz, rz2, rz3)) } +emit_fadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_zs_zs_zs(rz, rz2, rz3)) } +emit_fadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fadd_zd_zd_zd(rz, rz2, rz3)) } +emit_fadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fadd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fadd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_fsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_fsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fsub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fsub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } emit_fsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2s_v2s_v2s(dst, src, src2)) } emit_fsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v4s_v4s_v4s(dst, src, src2)) } emit_fsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2d_v2d_v2d(dst, src, src2)) } -emit_fsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_z_z_z(rz, rz2, rz3)) } -emit_fsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_zh_zh_zh(rz, rz2, rz3)) } +emit_fsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_zs_zs_zs(rz, rz2, rz3)) } +emit_fsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsub_zd_zd_zd(rz, rz2, rz3)) } +emit_fsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fsub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fsub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_fmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_fmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_fmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } emit_fmul_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2s_v2s_v2s(dst, src, src2)) } emit_fmul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v4s_v4s_v4s(dst, src, src2)) } emit_fmul_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2d_v2d_v2d(dst, src, src2)) } -emit_fmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_z_z_z(rz, rz2, rz3)) } -emit_fmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_zh_zh_zh(rz, rz2, rz3)) } +emit_fmul_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_zs_zs_zs(rz, rz2, rz3)) } +emit_fmul_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmul_zd_zd_zd(rz, rz2, rz3)) } +emit_fmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fdiv_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fdiv_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } emit_fdiv_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2s_v2s_v2s(dst, src, src2)) } emit_fdiv_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v4s_v4s_v4s(dst, src, src2)) } emit_fdiv_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2d_v2d_v2d(dst, src, src2)) } -emit_fdiv_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fdiv_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fdiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fdiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } @@ -551,56 +691,72 @@ inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } emit_fmax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2s_v2s_v2s(dst, src, src2)) } emit_fmax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4s_v4s_v4s(dst, src, src2)) } emit_fmax_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2d_v2d_v2d(dst, src, src2)) } emit_fmax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4h_v4h_v4h(dst, src, src2)) } emit_fmax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v8h_v8h_v8h(dst, src, src2)) } -emit_fmax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } emit_fmin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2s_v2s_v2s(dst, src, src2)) } emit_fmin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4s_v4s_v4s(dst, src, src2)) } emit_fmin_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2d_v2d_v2d(dst, src, src2)) } emit_fmin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4h_v4h_v4h(dst, src, src2)) } emit_fmin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v8h_v8h_v8h(dst, src, src2)) } -emit_fmin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmaxnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmaxnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } emit_fmaxnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4s_v4s_v4s(dst, src, src2)) } emit_fmaxnm_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2d_v2d_v2d(dst, src, src2)) } emit_fmaxnm_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4h_v4h_v4h(dst, src, src2)) } emit_fmaxnm_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v8h_v8h_v8h(dst, src, src2)) } -emit_fmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmaxnm_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmaxnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fminnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fminnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } emit_fminnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2s_v2s_v2s(dst, src, src2)) } emit_fminnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4s_v4s_v4s(dst, src, src2)) } emit_fminnm_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2d_v2d_v2d(dst, src, src2)) } emit_fminnm_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4h_v4h_v4h(dst, src, src2)) } emit_fminnm_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v8h_v8h_v8h(dst, src, src2)) } -emit_fminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_fminnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fminnm_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fminnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fminnm_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } @@ -753,98 +909,126 @@ inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinta_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frinta_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frinta_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frinta_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } emit_frinta_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2s_v2s(dst, src)) } emit_frinta_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4s_v4s(dst, src)) } emit_frinta_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2d_v2d(dst, src)) } emit_frinta_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4h_v4h(dst, src)) } emit_frinta_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v8h_v8h(dst, src)) } -emit_frinta_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_z_p_z(rz, rz2, rz3)) } +emit_frinta_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zh_p_zh(rz, rz2, rz3)) } +emit_frinta_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zs_p_zs(rz, rz2, rz3)) } +emit_frinta_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zd_p_zd(rz, rz2, rz3)) } inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinti_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frinti_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frinti_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frinti_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } emit_frinti_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2s_v2s(dst, src)) } emit_frinti_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4s_v4s(dst, src)) } emit_frinti_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2d_v2d(dst, src)) } emit_frinti_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4h_v4h(dst, src)) } emit_frinti_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v8h_v8h(dst, src)) } -emit_frinti_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_z_p_z(rz, rz2, rz3)) } +emit_frinti_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zh_p_zh(rz, rz2, rz3)) } +emit_frinti_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zs_p_zs(rz, rz2, rz3)) } +emit_frinti_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zd_p_zd(rz, rz2, rz3)) } inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintm_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintm_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintm_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frintm_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } emit_frintm_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2s_v2s(dst, src)) } emit_frintm_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4s_v4s(dst, src)) } emit_frintm_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2d_v2d(dst, src)) } emit_frintm_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4h_v4h(dst, src)) } emit_frintm_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v8h_v8h(dst, src)) } -emit_frintm_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_z_p_z(rz, rz2, rz3)) } +emit_frintm_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zh_p_zh(rz, rz2, rz3)) } +emit_frintm_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zs_p_zs(rz, rz2, rz3)) } +emit_frintm_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zd_p_zd(rz, rz2, rz3)) } inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintn_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintn_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintn_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frintn_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } emit_frintn_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2s_v2s(dst, src)) } emit_frintn_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4s_v4s(dst, src)) } emit_frintn_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2d_v2d(dst, src)) } emit_frintn_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4h_v4h(dst, src)) } emit_frintn_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v8h_v8h(dst, src)) } -emit_frintn_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_z_p_z(rz, rz2, rz3)) } +emit_frintn_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zh_p_zh(rz, rz2, rz3)) } +emit_frintn_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zs_p_zs(rz, rz2, rz3)) } +emit_frintn_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zd_p_zd(rz, rz2, rz3)) } inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintp_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintp_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintp_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frintp_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } emit_frintp_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2s_v2s(dst, src)) } emit_frintp_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4s_v4s(dst, src)) } emit_frintp_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2d_v2d(dst, src)) } emit_frintp_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4h_v4h(dst, src)) } emit_frintp_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v8h_v8h(dst, src)) } -emit_frintp_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_z_p_z(rz, rz2, rz3)) } +emit_frintp_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zh_p_zh(rz, rz2, rz3)) } +emit_frintp_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zs_p_zs(rz, rz2, rz3)) } +emit_frintp_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zd_p_zd(rz, rz2, rz3)) } inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frintx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } emit_frintx_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2s_v2s(dst, src)) } emit_frintx_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4s_v4s(dst, src)) } emit_frintx_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2d_v2d(dst, src)) } emit_frintx_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4h_v4h(dst, src)) } emit_frintx_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v8h_v8h(dst, src)) } -emit_frintx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_z_p_z(rz, rz2, rz3)) } +emit_frintx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zh_p_zh(rz, rz2, rz3)) } +emit_frintx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zs_p_zs(rz, rz2, rz3)) } +emit_frintx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zd_p_zd(rz, rz2, rz3)) } inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintz_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frintz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frintz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } emit_frintz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2s_v2s(dst, src)) } emit_frintz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4s_v4s(dst, src)) } emit_frintz_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2d_v2d(dst, src)) } emit_frintz_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4h_v4h(dst, src)) } emit_frintz_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v8h_v8h(dst, src)) } -emit_frintz_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_z_p_z(rz, rz2, rz3)) } +emit_frintz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zh_p_zh(rz, rz2, rz3)) } +emit_frintz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zs_p_zs(rz, rz2, rz3)) } +emit_frintz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zd_p_zd(rz, rz2, rz3)) } inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } @@ -1134,21 +1318,21 @@ emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Inst inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aese_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_aese_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_v16b_v16b(dst, src)) } -emit_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_z_z(rz, rz2)) } +emit_aese_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_zb_zb(rz, rz2)) } inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesd_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_aesd_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_v16b_v16b(dst, src)) } -emit_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_z_z(rz, rz2)) } +emit_aesd_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_zb_zb(rz, rz2)) } inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +inst_aesmc_zb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } emit_aesmc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_v16b_v16b(dst, src)) } -emit_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_z(rz)) } +emit_aesmc_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_zb(rz)) } inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +inst_aesimc_zb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } emit_aesimc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_v16b_v16b(dst, src)) } -emit_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_z(rz)) } +emit_aesimc_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_zb(rz)) } inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } @@ -1178,17 +1362,17 @@ emit_sha512su0_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } emit_sha512su1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_v2d_v2d_v2d(dst, src, src2)) } inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_eor3_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor3_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } emit_eor3_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } -emit_eor3_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_z_z_z_z(rz, rz2, rz3, rz4)) } +emit_eor3_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_bcax_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bcax_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } emit_bcax_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } -emit_bcax_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_z_z_z_z(rz, rz2, rz3, rz4)) } +emit_bcax_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } emit_rax1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_v2d_v2d_v2d(dst, src, src2)) } inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } -inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4)}} } emit_xar_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_v2d_v2d_v2d_i(dst, src, src2, imm)) } emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } @@ -1218,9 +1402,9 @@ inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register emit_pmull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v8h_v16b_v16b(dst, src, src2)) } emit_pmull2_v1q_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v1q_v2d_v2d(dst, src, src2)) } inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -inst_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_bfcvt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } -emit_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_z_p_z(rz, rz2, rz3)) } +emit_bfcvt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_zh_p_zs(rz, rz2, rz3)) } inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } emit_bfdot_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_v4s_v8h_v8h(dst, src, src2)) } inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } @@ -1236,11 +1420,17 @@ emit_bfcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Inst inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_mul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_mul_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_mul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_mul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_mul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_mul_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v16b_v16b_v16b(dst, src, src2)) } emit_mul_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v8h_v8h_v8h(dst, src, src2)) } emit_mul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v4s_v4s_v4s(dst, src, src2)) } -emit_mul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_mul_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_mul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_mul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_mul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -1272,7 +1462,10 @@ inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_neg_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_neg_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_neg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_neg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_neg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } emit_neg_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v8b_v8b(dst, src)) } emit_neg_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v16b_v16b(dst, src)) } @@ -1281,7 +1474,10 @@ emit_neg_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_neg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v2s_v2s(dst, src)) } emit_neg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v4s_v4s(dst, src)) } emit_neg_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v2d_v2d(dst, src)) } -emit_neg_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_z_p_z(rz, rz2, rz3)) } +emit_neg_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zb_p_zb(rz, rz2, rz3)) } +emit_neg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zh_p_zh(rz, rz2, rz3)) } +emit_neg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zs_p_zs(rz, rz2, rz3)) } +emit_neg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zd_p_zd(rz, rz2, rz3)) } emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -1290,7 +1486,10 @@ inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_abs_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_abs_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_abs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_abs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_abs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_abs_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v8b_v8b(dst, src)) } emit_abs_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v16b_v16b(dst, src)) } emit_abs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4h_v4h(dst, src)) } @@ -1298,7 +1497,10 @@ emit_abs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_abs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v2s_v2s(dst, src)) } emit_abs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4s_v4s(dst, src)) } emit_abs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v2d_v2d(dst, src)) } -emit_abs_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_z_p_z(rz, rz2, rz3)) } +emit_abs_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zb_p_zb(rz, rz2, rz3)) } +emit_abs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zh_p_zh(rz, rz2, rz3)) } +emit_abs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zs_p_zs(rz, rz2, rz3)) } +emit_abs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zd_p_zd(rz, rz2, rz3)) } inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -1378,7 +1580,10 @@ inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_sqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_sqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v8b_v8b_v8b(dst, src, src2)) } emit_sqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v16b_v16b_v16b(dst, src, src2)) } emit_sqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1386,7 +1591,10 @@ emit_sqadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v2s_v2s_v2s(dst, src, src2)) } emit_sqadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4s_v4s_v4s(dst, src, src2)) } emit_sqadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v2d_v2d_v2d(dst, src, src2)) } -emit_sqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_z_z_z(rz, rz2, rz3)) } +emit_sqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zb_zb_zb(rz, rz2, rz3)) } +emit_sqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zh_zh_zh(rz, rz2, rz3)) } +emit_sqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zs_zs_zs(rz, rz2, rz3)) } +emit_sqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zd_zd_zd(rz, rz2, rz3)) } inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -1394,7 +1602,10 @@ inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_uqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_uqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_uqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v8b_v8b_v8b(dst, src, src2)) } emit_uqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v16b_v16b_v16b(dst, src, src2)) } emit_uqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1402,7 +1613,10 @@ emit_uqadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v2s_v2s_v2s(dst, src, src2)) } emit_uqadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4s_v4s_v4s(dst, src, src2)) } emit_uqadd_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v2d_v2d_v2d(dst, src, src2)) } -emit_uqadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_z_z_z(rz, rz2, rz3)) } +emit_uqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zb_zb_zb(rz, rz2, rz3)) } +emit_uqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zh_zh_zh(rz, rz2, rz3)) } +emit_uqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zs_zs_zs(rz, rz2, rz3)) } +emit_uqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zd_zd_zd(rz, rz2, rz3)) } inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -1410,7 +1624,10 @@ inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_sqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_sqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v8b_v8b_v8b(dst, src, src2)) } emit_sqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v16b_v16b_v16b(dst, src, src2)) } emit_sqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1418,7 +1635,10 @@ emit_sqsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v2s_v2s_v2s(dst, src, src2)) } emit_sqsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4s_v4s_v4s(dst, src, src2)) } emit_sqsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v2d_v2d_v2d(dst, src, src2)) } -emit_sqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_z_z_z(rz, rz2, rz3)) } +emit_sqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zb_zb_zb(rz, rz2, rz3)) } +emit_sqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zh_zh_zh(rz, rz2, rz3)) } +emit_sqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zs_zs_zs(rz, rz2, rz3)) } +emit_sqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zd_zd_zd(rz, rz2, rz3)) } inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -1426,7 +1646,10 @@ inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_uqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_uqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_uqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v8b_v8b_v8b(dst, src, src2)) } emit_uqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v16b_v16b_v16b(dst, src, src2)) } emit_uqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1434,91 +1657,130 @@ emit_uqsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v2s_v2s_v2s(dst, src, src2)) } emit_uqsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4s_v4s_v4s(dst, src, src2)) } emit_uqsub_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v2d_v2d_v2d(dst, src, src2)) } -emit_uqsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_z_z_z(rz, rz2, rz3)) } +emit_uqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zb_zb_zb(rz, rz2, rz3)) } +emit_uqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zh_zh_zh(rz, rz2, rz3)) } +emit_uqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zs_zs_zs(rz, rz2, rz3)) } +emit_uqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zd_zd_zd(rz, rz2, rz3)) } inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_smax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_smax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_smax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8b_v8b_v8b(dst, src, src2)) } emit_smax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v16b_v16b_v16b(dst, src, src2)) } emit_smax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4h_v4h_v4h(dst, src, src2)) } emit_smax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8h_v8h_v8h(dst, src, src2)) } emit_smax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v2s_v2s_v2s(dst, src, src2)) } emit_smax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4s_v4s_v4s(dst, src, src2)) } -emit_smax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_smax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_smax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_smax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_smax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umax_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_umax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_umax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_umax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8b_v8b_v8b(dst, src, src2)) } emit_umax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v16b_v16b_v16b(dst, src, src2)) } emit_umax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4h_v4h_v4h(dst, src, src2)) } emit_umax_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8h_v8h_v8h(dst, src, src2)) } emit_umax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v2s_v2s_v2s(dst, src, src2)) } emit_umax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4s_v4s_v4s(dst, src, src2)) } -emit_umax_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_umax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_umax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_umax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_umax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_smin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_smin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_smin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8b_v8b_v8b(dst, src, src2)) } emit_smin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v16b_v16b_v16b(dst, src, src2)) } emit_smin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4h_v4h_v4h(dst, src, src2)) } emit_smin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8h_v8h_v8h(dst, src, src2)) } emit_smin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v2s_v2s_v2s(dst, src, src2)) } emit_smin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4s_v4s_v4s(dst, src, src2)) } -emit_smin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_smin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_smin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_smin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_smin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umin_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_umin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_umin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_umin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8b_v8b_v8b(dst, src, src2)) } emit_umin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v16b_v16b_v16b(dst, src, src2)) } emit_umin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4h_v4h_v4h(dst, src, src2)) } emit_umin_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8h_v8h_v8h(dst, src, src2)) } emit_umin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v2s_v2s_v2s(dst, src, src2)) } emit_umin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4s_v4s_v4s(dst, src, src2)) } -emit_umin_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_umin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_umin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_umin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_umin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_sabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_sabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_sabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_sabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_sabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8b_v8b_v8b(dst, src, src2)) } emit_sabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v16b_v16b_v16b(dst, src, src2)) } emit_sabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4h_v4h_v4h(dst, src, src2)) } emit_sabd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8h_v8h_v8h(dst, src, src2)) } emit_sabd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v2s_v2s_v2s(dst, src, src2)) } emit_sabd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4s_v4s_v4s(dst, src, src2)) } -emit_sabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_sabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_sabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_sabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_sabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uabd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_uabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_uabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_uabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_uabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_uabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8b_v8b_v8b(dst, src, src2)) } emit_uabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v16b_v16b_v16b(dst, src, src2)) } emit_uabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4h_v4h_v4h(dst, src, src2)) } emit_uabd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8h_v8h_v8h(dst, src, src2)) } emit_uabd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v2s_v2s_v2s(dst, src, src2)) } emit_uabd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4s_v4s_v4s(dst, src, src2)) } -emit_uabd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_z_p_z_z(rz, rz2, rz3, rz4)) } +emit_uabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_uabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_uabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_uabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2041,20 +2303,36 @@ emit_usdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Inst emit_usdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v4s_v16b_v16b(dst, src, src2)) } inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmla_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +inst_fmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmla_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } +inst_fmla_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } +inst_fmla_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } emit_fmla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v4s_v4s_v4s(dst, src, src2)) } emit_fmla_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v2d_v2d_v2d(dst, src, src2)) } -emit_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_fmla_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_z_z_z_i(rz, rz2, rz3, imm)) } +emit_fmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmla_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_fmla_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zh_zh_zh_i(rz, rz2, rz3, imm)) } +emit_fmla_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zs_zs_zs_i(rz, rz2, rz3, imm)) } +emit_fmla_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zd_zd_zd_i(rz, rz2, rz3, imm)) } inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmls_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +inst_fmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmls_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } +inst_fmls_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } +inst_fmls_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } emit_fmls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v4s_v4s_v4s(dst, src, src2)) } emit_fmls_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v2d_v2d_v2d(dst, src, src2)) } -emit_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_fmls_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_z_z_z_i(rz, rz2, rz3, imm)) } +emit_fmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +emit_fmls_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zh_zh_zh_i(rz, rz2, rz3, imm)) } +emit_fmls_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zs_zs_zs_i(rz, rz2, rz3, imm)) } +emit_fmls_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zd_zd_zd_i(rz, rz2, rz3, imm)) } inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } @@ -2154,29 +2432,41 @@ inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_frecps_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_frecps_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_frecps_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_frecps_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2s_v2s_v2s(dst, src, src2)) } emit_frecps_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4s_v4s_v4s(dst, src, src2)) } emit_frecps_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2d_v2d_v2d(dst, src, src2)) } emit_frecps_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4h_v4h_v4h(dst, src, src2)) } emit_frecps_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v8h_v8h_v8h(dst, src, src2)) } -emit_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_z_z_z(rz, rz2, rz3)) } +emit_frecps_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zh_zh_zh(rz, rz2, rz3)) } +emit_frecps_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zs_zs_zs(rz, rz2, rz3)) } +emit_frecps_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zd_zd_zd(rz, rz2, rz3)) } inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_frsqrts_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_frsqrts_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_frsqrts_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_frsqrts_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2s_v2s_v2s(dst, src, src2)) } emit_frsqrts_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4s_v4s_v4s(dst, src, src2)) } emit_frsqrts_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2d_v2d_v2d(dst, src, src2)) } emit_frsqrts_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4h_v4h_v4h(dst, src, src2)) } emit_frsqrts_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v8h_v8h_v8h(dst, src, src2)) } -emit_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_z_z_z(rz, rz2, rz3)) } +emit_frsqrts_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zh_zh_zh(rz, rz2, rz3)) } +emit_frsqrts_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zs_zs_zs(rz, rz2, rz3)) } +emit_frsqrts_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zd_zd_zd(rz, rz2, rz3)) } inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } -inst_frecpx_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frecpx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_frecpx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_frecpx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } -emit_frecpx_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_z_p_z(rz, rz2, rz3)) } +emit_frecpx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zh_p_zh(rz, rz2, rz3)) } +emit_frecpx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zs_p_zs(rz, rz2, rz3)) } +emit_frecpx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zd_p_zd(rz, rz2, rz3)) } inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } @@ -2212,61 +2502,81 @@ inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fcmeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fcmeq_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2s_v2s_v2s(dst, src, src2)) } emit_fcmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4s_v4s_v4s(dst, src, src2)) } emit_fcmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2d_v2d_v2d(dst, src, src2)) } emit_fcmeq_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4h_v4h_v4h(dst, src, src2)) } emit_fcmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v8h_v8h_v8h(dst, src, src2)) } -emit_fcmeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_p_p_z_z(rz, rz2, rz3, rz4)) } +emit_fcmeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fcmeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fcmeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fcmge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fcmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2s_v2s_v2s(dst, src, src2)) } emit_fcmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4s_v4s_v4s(dst, src, src2)) } emit_fcmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2d_v2d_v2d(dst, src, src2)) } emit_fcmge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4h_v4h_v4h(dst, src, src2)) } emit_fcmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v8h_v8h_v8h(dst, src, src2)) } -emit_fcmge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_p_p_z_z(rz, rz2, rz3, rz4)) } +emit_fcmge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fcmge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fcmge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fcmgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } emit_fcmgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2s_v2s_v2s(dst, src, src2)) } emit_fcmgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4s_v4s_v4s(dst, src, src2)) } emit_fcmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2d_v2d_v2d(dst, src, src2)) } emit_fcmgt_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4h_v4h_v4h(dst, src, src2)) } emit_fcmgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v8h_v8h_v8h(dst, src, src2)) } -emit_fcmgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_p_p_z_z(rz, rz2, rz3, rz4)) } +emit_fcmgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fcmgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fcmgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmle_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fcmle_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fcmle_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_fcmle_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_fcmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2s_v2s(dst, src)) } emit_fcmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4s_v4s(dst, src)) } emit_fcmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2d_v2d(dst, src)) } emit_fcmle_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4h_v4h(dst, src)) } emit_fcmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v8h_v8h(dst, src)) } -emit_fcmle_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_p_p_z(rz, rz2, rz3)) } +emit_fcmle_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ph_p_zh(rz, rz2, rz3)) } +emit_fcmle_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ps_p_zs(rz, rz2, rz3)) } +emit_fcmle_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_pd_p_zd(rz, rz2, rz3)) } inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmlt_p_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fcmlt_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_fcmlt_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_fcmlt_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_fcmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2s_v2s(dst, src)) } emit_fcmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4s_v4s(dst, src)) } emit_fcmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2d_v2d(dst, src)) } emit_fcmlt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4h_v4h(dst, src)) } emit_fcmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v8h_v8h(dst, src)) } -emit_fcmlt_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_p_p_z(rz, rz2, rz3)) } +emit_fcmlt_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ph_p_zh(rz, rz2, rz3)) } +emit_fcmlt_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ps_p_zs(rz, rz2, rz3)) } +emit_fcmlt_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_pd_p_zd(rz, rz2, rz3)) } inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } @@ -2384,9 +2694,9 @@ emit_bit_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Inst inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } emit_bif_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_v16b_v16b_v16b(dst, src, src2)) } inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } emit_bsl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_v16b_v16b_v16b(dst, src, src2)) } -emit_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } +emit_bsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } @@ -2783,7 +3093,10 @@ inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}}} } inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}}} } inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}}} } -inst_dup_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +inst_dup_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +inst_dup_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } +inst_dup_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } +inst_dup_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } emit_dup_v8b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v8b_veb_i(dst, src, imm)) } emit_dup_v16b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v16b_veb_i(dst, src, imm)) } emit_dup_v4h_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v4h_veh_i(dst, src, imm)) } @@ -2798,7 +3111,10 @@ emit_dup_v8h_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_dup_v2s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v2s_r(dst, src)) } emit_dup_v4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v4s_r(dst, src)) } emit_dup_v2d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_dup_v2d_r(dst, src)) } -emit_dup_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_z_r(rz, src)) } +emit_dup_zb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zb_r(rz, src)) } +emit_dup_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zh_r(rz, src)) } +emit_dup_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zs_r(rz, src)) } +emit_dup_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zd_r(rz, src)) } inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2)}} } inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2)}} } inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2)}} } @@ -2817,36 +3133,48 @@ emit_ins_ves_i_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_ins_ved_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ved_i_r(dst, imm, src)) } inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_mov_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_mov_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_mov_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_mov_ps_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV, dst, src) } inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } emit_mov_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v8b_v8b(dst, src)) } emit_mov_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v16b_v16b(dst, src)) } -emit_mov_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_z_p_z(rz, rz2, rz3)) } -emit_mov_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_p_p_p(rz, rz2, rz3)) } -emit_mov_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_p_p(rz, rz2)) } +emit_mov_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zb_p_zb(rz, rz2, rz3)) } +emit_mov_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zh_p_zh(rz, rz2, rz3)) } +emit_mov_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zs_p_zs(rz, rz2, rz3)) } +emit_mov_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zd_p_zd(rz, rz2, rz3)) } +emit_mov_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_pb_p_p(rz, rz2, rz3)) } +emit_mov_ps_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_ps_p(rz, rz2)) } emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4)}} } inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4)}} } -inst_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +inst_ext_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } -emit_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_z_z_z_i(rz, rz2, rz3, imm)) } +emit_ext_zb_zb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_zb_zb_zb_i(rz, rz2, rz3, imm)) } inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } -emit_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_z_z_z(rz, rz2, rz3)) } +emit_tbl_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zb_zb(rz, rz2, rz3)) } +emit_tbl_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zh_zh_zh(rz, rz2, rz3)) } +emit_tbl_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zs_zs_zs(rz, rz2, rz3)) } +emit_tbl_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zd_zd_zd(rz, rz2, rz3)) } inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } -emit_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_z_z_z(rz, rz2, rz3)) } +emit_tbx_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_zb_zb_zb(rz, rz2, rz3)) } inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2854,8 +3182,11 @@ inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_zip1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_zip1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8b_v8b_v8b(dst, src, src2)) } emit_zip1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v16b_v16b_v16b(dst, src, src2)) } emit_zip1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4h_v4h_v4h(dst, src, src2)) } @@ -2863,8 +3194,11 @@ emit_zip1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v2s_v2s_v2s(dst, src, src2)) } emit_zip1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4s_v4s_v4s(dst, src, src2)) } emit_zip1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v2d_v2d_v2d(dst, src, src2)) } -emit_zip1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_z_z_z(rz, rz2, rz3)) } -emit_zip1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_p_p_p(rz, rz2, rz3)) } +emit_zip1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zb_zb_zb(rz, rz2, rz3)) } +emit_zip1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zh_zh_zh(rz, rz2, rz3)) } +emit_zip1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zs_zs_zs(rz, rz2, rz3)) } +emit_zip1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zd_zd_zd(rz, rz2, rz3)) } +emit_zip1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_pb_p_p(rz, rz2, rz3)) } inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2872,8 +3206,11 @@ inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_zip2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_zip2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8b_v8b_v8b(dst, src, src2)) } emit_zip2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v16b_v16b_v16b(dst, src, src2)) } emit_zip2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4h_v4h_v4h(dst, src, src2)) } @@ -2881,8 +3218,11 @@ emit_zip2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v2s_v2s_v2s(dst, src, src2)) } emit_zip2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4s_v4s_v4s(dst, src, src2)) } emit_zip2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v2d_v2d_v2d(dst, src, src2)) } -emit_zip2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_z_z_z(rz, rz2, rz3)) } -emit_zip2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_p_p_p(rz, rz2, rz3)) } +emit_zip2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zb_zb_zb(rz, rz2, rz3)) } +emit_zip2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zh_zh_zh(rz, rz2, rz3)) } +emit_zip2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zs_zs_zs(rz, rz2, rz3)) } +emit_zip2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zd_zd_zd(rz, rz2, rz3)) } +emit_zip2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_pb_p_p(rz, rz2, rz3)) } inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2890,8 +3230,11 @@ inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uzp1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_uzp1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8b_v8b_v8b(dst, src, src2)) } emit_uzp1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v16b_v16b_v16b(dst, src, src2)) } emit_uzp1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4h_v4h_v4h(dst, src, src2)) } @@ -2899,8 +3242,11 @@ emit_uzp1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v2s_v2s_v2s(dst, src, src2)) } emit_uzp1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4s_v4s_v4s(dst, src, src2)) } emit_uzp1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v2d_v2d_v2d(dst, src, src2)) } -emit_uzp1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_z_z_z(rz, rz2, rz3)) } -emit_uzp1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_p_p_p(rz, rz2, rz3)) } +emit_uzp1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zb_zb_zb(rz, rz2, rz3)) } +emit_uzp1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zh_zh_zh(rz, rz2, rz3)) } +emit_uzp1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zs_zs_zs(rz, rz2, rz3)) } +emit_uzp1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zd_zd_zd(rz, rz2, rz3)) } +emit_uzp1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_pb_p_p(rz, rz2, rz3)) } inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2908,8 +3254,11 @@ inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uzp2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_uzp2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8b_v8b_v8b(dst, src, src2)) } emit_uzp2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v16b_v16b_v16b(dst, src, src2)) } emit_uzp2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4h_v4h_v4h(dst, src, src2)) } @@ -2917,8 +3266,11 @@ emit_uzp2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v2s_v2s_v2s(dst, src, src2)) } emit_uzp2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4s_v4s_v4s(dst, src, src2)) } emit_uzp2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v2d_v2d_v2d(dst, src, src2)) } -emit_uzp2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_z_z_z(rz, rz2, rz3)) } -emit_uzp2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_p_p_p(rz, rz2, rz3)) } +emit_uzp2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zb_zb_zb(rz, rz2, rz3)) } +emit_uzp2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zh_zh_zh(rz, rz2, rz3)) } +emit_uzp2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zs_zs_zs(rz, rz2, rz3)) } +emit_uzp2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zd_zd_zd(rz, rz2, rz3)) } +emit_uzp2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_pb_p_p(rz, rz2, rz3)) } inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2926,8 +3278,11 @@ inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn1_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn1_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_trn1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_trn1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8b_v8b_v8b(dst, src, src2)) } emit_trn1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v16b_v16b_v16b(dst, src, src2)) } emit_trn1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4h_v4h_v4h(dst, src, src2)) } @@ -2935,8 +3290,11 @@ emit_trn1_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn1_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v2s_v2s_v2s(dst, src, src2)) } emit_trn1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4s_v4s_v4s(dst, src, src2)) } emit_trn1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v2d_v2d_v2d(dst, src, src2)) } -emit_trn1_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_z_z_z(rz, rz2, rz3)) } -emit_trn1_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_p_p_p(rz, rz2, rz3)) } +emit_trn1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zb_zb_zb(rz, rz2, rz3)) } +emit_trn1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zh_zh_zh(rz, rz2, rz3)) } +emit_trn1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zs_zs_zs(rz, rz2, rz3)) } +emit_trn1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zd_zd_zd(rz, rz2, rz3)) } +emit_trn1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_pb_p_p(rz, rz2, rz3)) } inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -2944,8 +3302,11 @@ inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn2_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_trn2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_trn2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8b_v8b_v8b(dst, src, src2)) } emit_trn2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v16b_v16b_v16b(dst, src, src2)) } emit_trn2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4h_v4h_v4h(dst, src, src2)) } @@ -2953,14 +3314,17 @@ emit_trn2_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn2_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v2s_v2s_v2s(dst, src, src2)) } emit_trn2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4s_v4s_v4s(dst, src, src2)) } emit_trn2_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v2d_v2d_v2d(dst, src, src2)) } -emit_trn2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_z_z_z(rz, rz2, rz3)) } -emit_trn2_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_p_p_p(rz, rz2, rz3)) } +emit_trn2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zb_zb_zb(rz, rz2, rz3)) } +emit_trn2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zh_zh_zh(rz, rz2, rz3)) } +emit_trn2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zs_zs_zs(rz, rz2, rz3)) } +emit_trn2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zd_zd_zd(rz, rz2, rz3)) } +emit_trn2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_pb_p_p(rz, rz2, rz3)) } inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_not_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_not_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_not_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v8b_v8b(dst, src)) } emit_not_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v16b_v16b(dst, src)) } -emit_not_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_p_p_p(rz, rz2, rz3)) } +emit_not_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_pb_p_p(rz, rz2, rz3)) } inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } @@ -2975,10 +3339,16 @@ emit_rev64_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Inst emit_rev64_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4s_v4s(dst, src)) } inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_cnt_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +inst_cnt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +inst_cnt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_cnt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } emit_cnt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v8b_v8b(dst, src)) } emit_cnt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v16b_v16b(dst, src)) } -emit_cnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_z_p_z(rz, rz2, rz3)) } +emit_cnt_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zb_p_zb(rz, rz2, rz3)) } +emit_cnt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zh_p_zh(rz, rz2, rz3)) } +emit_cnt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zs_p_zs(rz, rz2, rz3)) } +emit_cnt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zd_p_zd(rz, rz2, rz3)) } inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } emit_urecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v2s_v2s(dst, src)) } @@ -3109,148 +3479,332 @@ inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register emit_ld3r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_v16b_m(dst, mem)) } inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } emit_ld4r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_v16b_m(dst, mem)) } -inst_subr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_subr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_asrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_asrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_lslr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_lslr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_lsrr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_lsrr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_z_z_z(rz, rz2, rz3)) } -inst_fsubr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fsubr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fdivr_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fdivr_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_nand_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nand_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nor_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nor_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_sel_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sel_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orrs_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orrs_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_eors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_eors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nands_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nands_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_nors_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nors_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_orns_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orns_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_movs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_movs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_p_p_p(rz, rz2, rz3)) } -inst_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_p_i(rz, imm)) } -inst_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } -emit_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_p_i(rz, imm)) } -inst_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_p(rz)) } -inst_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_p_p_p(rz, rz2, rz3)) } -inst_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_p_p_p(rz, rz2, rz3)) } -inst_brka_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brka_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_p_p_p(rz, rz2, rz3)) } -inst_brkb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_p_p_p(rz, rz2, rz3)) } -inst_brkas_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkas_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_p_p_p(rz, rz2, rz3)) } -inst_brkbs_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkbs_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_p_p_p(rz, rz2, rz3)) } -inst_brkpa_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpa_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkpb_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpb_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkn_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkn_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_p_p_p_p(rz, rz2, rz3, rz4)) } -inst_rdffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_rdffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_p(rz)) } +inst_subr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_subr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_subr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_subr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_subr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_subr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_subr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_subr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_asrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_asrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_asrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_asrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_asrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_asrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_asrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_asrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_lslr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lslr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_lslr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_lslr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_lslr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_lslr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_lslr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_lslr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_lsrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_lsrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_lsrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_lsrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_lsrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_lsrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_lsrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_lsrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_ftsmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_ftsmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_ftsmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_ftsmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zh_zh_zh(rz, rz2, rz3)) } +emit_ftsmul_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zs_zs_zs(rz, rz2, rz3)) } +emit_ftsmul_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zd_zd_zd(rz, rz2, rz3)) } +inst_fsubr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fsubr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fsubr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fsubr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fsubr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fsubr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_fdivr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fdivr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fdivr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fdivr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fdivr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fdivr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_fnmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fnmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fnmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fnmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fnmla_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fnmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_fnmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fnmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fnmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fnmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fnmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_nand_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nand_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_ps_p_p_p(rz, rz2, rz3, rz4)) } +inst_nor_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nor_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_ps_p_p_p(rz, rz2, rz3, rz4)) } +inst_sel_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sel_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_p_p(rz, rz2, rz3, rz4)) } +inst_orrs_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orrs_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pd_p_p_p(rz, rz2, rz3, rz4)) } +inst_eors_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eors_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_ph_p_p_p(rz, rz2, rz3, rz4)) } +inst_nands_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nands_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pd_p_p_p(rz, rz2, rz3, rz4)) } +inst_nors_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nors_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pd_p_p_p(rz, rz2, rz3, rz4)) } +inst_orns_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orns_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pd_p_p_p(rz, rz2, rz3, rz4)) } +inst_movs_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_movs_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_ph_p_p(rz, rz2, rz3)) } +inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrue_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_pb_i(rz, imm)) } +inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } +inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } +inst_pfirst_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_ph_p_p(rz, rz2, rz3)) } +inst_pnext_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_p(rz, rz2, rz3)) } +inst_brka_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brka_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_p(rz, rz2, rz3)) } +inst_brkb_ps_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkb_ps_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_ps_p_p(rz, rz2, rz3)) } +inst_brkas_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkas_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_ph_p_p(rz, rz2, rz3)) } +inst_brkbs_pd_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkbs_pd_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pd_p_p(rz, rz2, rz3)) } +inst_brkpa_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpa_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkpb_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpb_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_pb_p_p_p(rz, rz2, rz3, rz4)) } +inst_brkn_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkn_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_pb_p_p_p(rz, rz2, rz3, rz4)) } +inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_rdffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_pb(rz)) } inst_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_p(rz)) } inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } -inst_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmple_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmple_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmplt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmplt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmplo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmplo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_cmpls_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_cmpls_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_fcmuo_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_fcmuo_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_insr_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -emit_insr_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_z_r(rz, src)) } -inst_cpy_z_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -emit_cpy_z_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_z_p_r(rz, rz2, src)) } -inst_compact_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_compact_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_z_p_z(rz, rz2, rz3)) } -inst_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmpeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmpeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmpeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmpeq_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmpeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmpeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmpeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmpne_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmpne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmpne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmpne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmpne_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmpne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmpne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmpne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmpge_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmpge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmpge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmpge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmpge_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmpge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmpge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmpge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmpgt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmpgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmpgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmpgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmpgt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmpgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmpgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmpgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmple_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmple_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmple_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmple_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmple_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmple_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmple_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmple_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmplt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmplt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmplt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmplt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmplt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmplt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmplt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmplt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmphi_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmphi_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmphi_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmphi_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmphi_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmphi_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmphi_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmphi_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmphs_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmphs_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmphs_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmphs_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmphs_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmphs_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmphs_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmphs_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmplo_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmplo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmplo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmplo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmplo_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmplo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmplo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmplo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_cmpls_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_cmpls_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_cmpls_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_cmpls_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_cmpls_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_cmpls_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_cmpls_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_cmpls_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_fcmne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fcmne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fcmne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fcmne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fcmne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_fcmuo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_fcmuo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_fcmuo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_fcmuo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_fcmuo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_fcmuo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_insr_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +inst_insr_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } +inst_insr_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } +inst_insr_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } +emit_insr_zb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zb_r(rz, src)) } +emit_insr_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zh_r(rz, src)) } +emit_insr_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zs_r(rz, src)) } +emit_insr_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zd_r(rz, src)) } +inst_cpy_zb_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +inst_cpy_zh_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +inst_cpy_zs_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +inst_cpy_zd_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +emit_cpy_zb_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zb_p_r(rz, rz2, src)) } +emit_cpy_zh_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zh_p_r(rz, rz2, src)) } +emit_cpy_zs_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zs_p_r(rz, rz2, src)) } +emit_cpy_zd_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zd_p_r(rz, rz2, src)) } +inst_compact_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_compact_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +emit_compact_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zs_p_zs(rz, rz2, rz3)) } +emit_compact_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zd_p_zd(rz, rz2, rz3)) } +inst_ld1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_z_p_m(rz, rz2, mem)) } +inst_ld1b_zpb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1b_zqb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_ld1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zb_p_m(rz, rz2, mem)) } +emit_ld1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zs_p_m(rz, rz2, mem)) } +emit_ld1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zd_p_m(rz, rz2, mem)) } emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } -inst_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1b_zpb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zpb_pnz_m(rz, rz2, mem)) } +emit_ld1b_zqb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zqb_pnz_m(rz, rz2, mem)) } +inst_ld1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_z_p_m(rz, rz2, mem)) } +inst_ld1h_zph_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1h_zqh_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_ld1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zh_p_m(rz, rz2, mem)) } +emit_ld1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zs_p_m(rz, rz2, mem)) } +emit_ld1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zd_p_m(rz, rz2, mem)) } emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } -inst_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1h_zph_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zph_pnz_m(rz, rz2, mem)) } +emit_ld1h_zqh_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zqh_pnz_m(rz, rz2, mem)) } +inst_ld1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_z_p_m(rz, rz2, mem)) } +inst_ld1w_zps_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1w_zqs_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_ld1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zs_p_m(rz, rz2, mem)) } +emit_ld1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zd_p_m(rz, rz2, mem)) } emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } -inst_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1w_zps_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zps_pnz_m(rz, rz2, mem)) } +emit_ld1w_zqs_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zqs_pnz_m(rz, rz2, mem)) } +inst_ld1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_z_p_m(rz, rz2, mem)) } +inst_ld1d_zpd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1d_zqd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_ld1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zd_p_m(rz, rz2, mem)) } emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } -inst_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_z_p_m(rz, rz2, mem)) } -inst_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_z_p_m(rz, rz2, mem)) } -inst_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_z_p_m(rz, rz2, mem)) } -inst_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1d_zpd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zpd_pnz_m(rz, rz2, mem)) } +emit_ld1d_zqd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zqd_pnz_m(rz, rz2, mem)) } +inst_ld1sb_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sb_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sb_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zh_p_m(rz, rz2, mem)) } +emit_ld1sb_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zs_p_m(rz, rz2, mem)) } +emit_ld1sb_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zd_p_m(rz, rz2, mem)) } +inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sh_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zs_p_m(rz, rz2, mem)) } +emit_ld1sh_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zd_p_m(rz, rz2, mem)) } +inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ld1sw_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_zd_p_m(rz, rz2, mem)) } +inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_z_p_m(rz, rz2, mem)) } +inst_st1b_zpb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1b_zqb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_st1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zb_p_m(rz, rz2, mem)) } +emit_st1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zs_p_m(rz, rz2, mem)) } +emit_st1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zd_p_m(rz, rz2, mem)) } emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } -inst_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_st1b_zpb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zpb_pn_m(rz, rz2, mem)) } +emit_st1b_zqb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zqb_pn_m(rz, rz2, mem)) } +inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_z_p_m(rz, rz2, mem)) } +inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_st1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zh_p_m(rz, rz2, mem)) } +emit_st1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zs_p_m(rz, rz2, mem)) } +emit_st1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zd_p_m(rz, rz2, mem)) } emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } -inst_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_st1h_zph_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zph_pn_m(rz, rz2, mem)) } +emit_st1h_zqh_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zqh_pn_m(rz, rz2, mem)) } +inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_z_p_m(rz, rz2, mem)) } +inst_st1w_zps_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1w_zqs_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_st1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zs_p_m(rz, rz2, mem)) } +emit_st1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zd_p_m(rz, rz2, mem)) } emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } -inst_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_st1w_zps_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zps_pn_m(rz, rz2, mem)) } +emit_st1w_zqs_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zqs_pn_m(rz, rz2, mem)) } +inst_st1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -emit_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_z_p_m(rz, rz2, mem)) } +inst_st1d_zpd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1d_zqd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +emit_st1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zd_p_m(rz, rz2, mem)) } emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } -inst_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_z_p_m(rz, rz2, mem)) } -inst_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_z_p_m(rz, rz2, mem)) } -inst_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_z_p_m(rz, rz2, mem)) } -inst_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_z_p_m(rz, rz2, mem)) } +emit_st1d_zpd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zpd_pn_m(rz, rz2, mem)) } +emit_st1d_zqd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zqd_pn_m(rz, rz2, mem)) } +inst_ldff1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_zb_p_m(rz, rz2, mem)) } +inst_ldff1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_zh_p_m(rz, rz2, mem)) } +inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_zs_p_m(rz, rz2, mem)) } +inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldff1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_zd_p_m(rz, rz2, mem)) } inst_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } emit_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_p_r_r(rz, src, src2)) } inst_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } @@ -3267,68 +3821,102 @@ inst_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: emit_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_p_r_r(rz, src, src2)) } inst_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } emit_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_p_r_r(rz, src, src2)) } -inst_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_z_z_z(rz, rz2, rz3)) } -inst_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_z_z_z(rz, rz2, rz3)) } -inst_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_z_z_z(rz, rz2, rz3)) } -inst_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_z_z_z(rz, rz2, rz3)) } -inst_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_z_z_z(rz, rz2, rz3)) } -inst_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_z_z_z(rz, rz2, rz3)) } -inst_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_z_z_z(rz, rz2, rz3)) } -inst_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } -inst_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -emit_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_z_z_z(rz, rz2, rz3)) } +inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sqrdmlah_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_sqrdmlah_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zb_zb_zb(rz, rz2, rz3)) } +emit_sqrdmlah_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zh_zh_zh(rz, rz2, rz3)) } +emit_sqrdmlah_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zs_zs_zs(rz, rz2, rz3)) } +emit_sqrdmlah_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zd_zd_zd(rz, rz2, rz3)) } +inst_sqrdmlsh_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_sqrdmlsh_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_sqrdmlsh_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sqrdmlsh_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_sqrdmlsh_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zb_zb_zb(rz, rz2, rz3)) } +emit_sqrdmlsh_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zh_zh_zh(rz, rz2, rz3)) } +emit_sqrdmlsh_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zs_zs_zs(rz, rz2, rz3)) } +emit_sqrdmlsh_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zd_zd_zd(rz, rz2, rz3)) } +inst_adclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_adclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_adclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zs_zs_zs(rz, rz2, rz3)) } +emit_adclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zd_zd_zd(rz, rz2, rz3)) } +inst_adclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_adclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_adclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zs_zs_zs(rz, rz2, rz3)) } +emit_adclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zd_zd_zd(rz, rz2, rz3)) } +inst_sbclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sbclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_sbclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zs_zs_zs(rz, rz2, rz3)) } +emit_sbclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zd_zd_zd(rz, rz2, rz3)) } +inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +emit_sbclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zs_zs_zs(rz, rz2, rz3)) } +emit_sbclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zd_zd_zd(rz, rz2, rz3)) } +inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_tbl2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_zb_zb_zb(rz, rz2, rz3)) } +inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_match_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_match_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +inst_nmatch_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_nmatch_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_nmatch_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_pb_p_zb_zb(rz, rz2, rz3, rz4)) } +emit_nmatch_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_ph_p_zh_zh(rz, rz2, rz3, rz4)) } +inst_histcnt_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +inst_histcnt_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_histcnt_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zs_p_zs_zs(rz, rz2, rz3, rz4)) } +emit_histcnt_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zd_p_zd_zd(rz, rz2, rz3, rz4)) } +inst_histseg_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_histseg_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_zb_zb_zb(rz, rz2, rz3)) } inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } inst_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTOP) } emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } -inst_addha_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_addha_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_addva_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_addva_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_addha_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addha_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_zs(imm, rz1, rz2, rz3)) } +inst_addva_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_addva_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_zs(imm, rz1, rz2, rz3)) } inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } -inst_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } -inst_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_fmopa_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmopa_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_zs(imm, rz1, rz2, rz3)) } +inst_fmops_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_fmops_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_zs(imm, rz1, rz2, rz3)) } +inst_bfmopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_bfmops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_bfmops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_smopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +inst_smopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_smopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zb(imm, rz1, rz2, rz3)) } +emit_smopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_smops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +inst_smops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_smops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zb(imm, rz1, rz2, rz3)) } +emit_smops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_umopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +inst_umopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_umopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zb(imm, rz1, rz2, rz3)) } +emit_umopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_umops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +inst_umops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_umops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zb(imm, rz1, rz2, rz3)) } +emit_umops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zh(imm, rz1, rz2, rz3)) } +inst_usmopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_usmopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_zb(imm, rz1, rz2, rz3)) } +inst_sumopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sumopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_zb(imm, rz1, rz2, rz3)) } inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } -inst_mova_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } -inst_mova_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } -emit_mova_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_z_p_i(rz, rz2, imm)) } -emit_mova_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_z(imm, rz1, rz2)) } +inst_mova_zb_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } +inst_mova_i_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +emit_mova_zb_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_zb_p_i(rz, rz2, imm)) } +emit_mova_i_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_zb(imm, rz1, rz2)) } inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } @@ -3353,46 +3941,46 @@ inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1 emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } -inst_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_z_p_m(rz, rz2, mem)) } -inst_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_z_p_m(rz, rz2, mem)) } -inst_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_z_p_m(rz, rz2, mem)) } -inst_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_z_p_m(rz, rz2, mem)) } -inst_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_z_p_m(rz, rz2, mem)) } -inst_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_z_p_m(rz, rz2, mem)) } -inst_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_z_p_m(rz, rz2, mem)) } -inst_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_z_p_m(rz, rz2, mem)) } -inst_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -emit_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_index_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } -emit_index_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_z_i_i(rz, imm, imm2)) } -emit_index_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_z_i_r(rz, imm, src)) } -emit_index_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_z_r_i(rz, src, imm)) } -emit_index_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_z_r_r(rz, src, src2)) } -inst_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } -emit_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } -inst_pmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -emit_pmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_z_z_z(rz, rz2, rz3)) } -inst_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_z_z_z(rz, rz2, rz3)) } -inst_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -emit_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_z_z_z(rz, rz2, rz3)) } -inst_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -emit_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_z_p_z(rz, rz2, rz3)) } +inst_ldnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_zb_p_m(rz, rz2, mem)) } +inst_ldnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_zh_p_m(rz, rz2, mem)) } +inst_ldnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_zs_p_m(rz, rz2, mem)) } +inst_ldnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_ldnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_zd_p_m(rz, rz2, mem)) } +inst_stnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_zb_p_m(rz, rz2, mem)) } +inst_stnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_zh_p_m(rz, rz2, mem)) } +inst_stnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_zs_p_m(rz, rz2, mem)) } +inst_stnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_stnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_zd_p_m(rz, rz2, mem)) } +inst_splice_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_splice_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_zb_p_zb_zb(rz, rz2, rz3, rz4)) } +inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } +emit_index_zb_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zb_i_i(rz, imm, imm2)) } +emit_index_zb_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zb_i_r(rz, imm, src)) } +emit_index_zb_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zb_r_i(rz, src, imm)) } +emit_index_zb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zb_r_r(rz, src, src2)) } +inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl1n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } +inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_bsl2n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } +inst_nbsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_nbsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } +inst_pmul_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_pmul_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_zb_zb_zb(rz, rz2, rz3)) } +inst_pmullb_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullb_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_zd_zs_zs(rz, rz2, rz3)) } +inst_pmullt_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_pmullt_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_zd_zs_zs(rz, rz2, rz3)) } +inst_bfcvtnt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_bfcvtnt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_zh_p_zs(rz, rz2, rz3)) } inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } @@ -3483,22 +4071,22 @@ inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfadd_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfadd_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_z_z_z(rz, rz2, rz3)) } -inst_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfsub_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfsub_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_z_z_z(rz, rz2, rz3)) } -inst_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } -emit_bfmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_z_z_z(rz, rz2, rz3)) } -inst_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_bfadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_bfadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_zh_zh_zh(rz, rz2, rz3)) } +inst_bfsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_bfsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_zh_zh_zh(rz, rz2, rz3)) } +inst_bfmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +emit_bfmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_zh_zh_zh(rz, rz2, rz3)) } +inst_bfmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +inst_bfmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } @@ -3515,24 +4103,24 @@ inst_bti_c_none :: #force_inline proc "contextless" () -> Instruct emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -emit_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_z_z_z(rz, rz2, rz3)) } -inst_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -emit_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } -inst_luti2_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti2_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_z_z_z_i(rz, rz2, rz3, imm)) } -inst_luti4_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti4_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_z_z_z_i(rz, rz2, rz3, imm)) } -inst_zip_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_zip_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_z_z_z(rz, rz2, rz3)) } -emit_zip_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_z_z(rz, rz2)) } -inst_uzp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } -emit_uzp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_z_z_z(rz, rz2, rz3)) } -emit_uzp_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_z_z(rz, rz2)) } +inst_bfclamp_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_bfclamp_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_zh_zh_zh(rz, rz2, rz3)) } +inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfminnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } +inst_luti2_zpb_zpb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti2_zpb_zpb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_zpb_zpb_zb_i(rz, rz2, rz3, imm)) } +inst_luti4_zpb_zpb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } +emit_luti4_zpb_zpb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_zpb_zpb_zb_i(rz, rz2, rz3, imm)) } +inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_zip_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_zpb_zb_zb(rz, rz2, rz3)) } +emit_zip_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_zqb_zqb(rz, rz2)) } +inst_uzp_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_uzp_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_uzp_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_zpb_zb_zb(rz, rz2, rz3)) } +emit_uzp_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_zqb_zqb(rz, rz2)) } inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } @@ -3720,12 +4308,12 @@ emit_cmn_r_i :: #force_inline proc(instructions: ^[dynamic]Inst // Overload Groups // ============================================================================= -inst_add :: proc{ inst_add_r_r_i, inst_add_r_r_sh, inst_add_r_r_ex, inst_add_v16b_v16b_v16b, inst_add_z_z_z, inst_add_z_p_z_z } -emit_add :: proc{ emit_add_r_r_i, emit_add_r_r_sh, emit_add_r_r_ex, emit_add_v16b_v16b_v16b, emit_add_z_z_z, emit_add_z_p_z_z } +inst_add :: proc{ inst_add_r_r_i, inst_add_r_r_sh, inst_add_r_r_ex, inst_add_v16b_v16b_v16b, inst_add_zb_zb_zb, inst_add_zb_p_zb_zb } +emit_add :: proc{ emit_add_r_r_i, emit_add_r_r_sh, emit_add_r_r_ex, emit_add_v16b_v16b_v16b, emit_add_zb_zb_zb, emit_add_zb_p_zb_zb } inst_adds :: proc{ inst_adds_r_r_i, inst_adds_r_r_sh, inst_adds_r_r_ex } emit_adds :: proc{ emit_adds_r_r_i, emit_adds_r_r_sh, emit_adds_r_r_ex } -inst_sub :: proc{ inst_sub_r_r_i, inst_sub_r_r_sh, inst_sub_r_r_ex, inst_sub_v16b_v16b_v16b, inst_sub_z_z_z, inst_sub_z_p_z_z } -emit_sub :: proc{ emit_sub_r_r_i, emit_sub_r_r_sh, emit_sub_r_r_ex, emit_sub_v16b_v16b_v16b, emit_sub_z_z_z, emit_sub_z_p_z_z } +inst_sub :: proc{ inst_sub_r_r_i, inst_sub_r_r_sh, inst_sub_r_r_ex, inst_sub_v16b_v16b_v16b, inst_sub_zb_zb_zb, inst_sub_zb_p_zb_zb } +emit_sub :: proc{ emit_sub_r_r_i, emit_sub_r_r_sh, emit_sub_r_r_ex, emit_sub_v16b_v16b_v16b, emit_sub_zb_zb_zb, emit_sub_zb_p_zb_zb } inst_subs :: proc{ inst_subs_r_r_i, inst_subs_r_r_sh, inst_subs_r_r_ex } emit_subs :: proc{ emit_subs_r_r_i, emit_subs_r_r_sh, emit_subs_r_r_ex } inst_movz :: inst_movz_r_i_i @@ -3738,34 +4326,34 @@ inst_adr :: inst_adr_r_l emit_adr :: emit_adr_r_l inst_adrp :: inst_adrp_r_l emit_adrp :: emit_adrp_r_l -inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_v16b_v16b_v16b, inst_and_z_p_z_z } -emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_v16b_v16b_v16b, emit_and_z_p_z_z } -inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_p_p_p_p } -emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_p_p_p_p } -inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_v16b_v16b_v16b, inst_orr_z_p_z_z } -emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_v16b_v16b_v16b, emit_orr_z_p_z_z } -inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_v16b_v16b_v16b, inst_eor_z_p_z_z } -emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_v16b_v16b_v16b, emit_eor_z_p_z_z } -inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_v16b_v16b_v16b, inst_bic_z_p_z_z } -emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_v16b_v16b_v16b, emit_bic_z_p_z_z } -inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_p_p_p_p } -emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_p_p_p_p } -inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_p_p_p_p } -emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_p_p_p_p } +inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_v16b_v16b_v16b, inst_and_zb_p_zb_zb } +emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_v16b_v16b_v16b, emit_and_zb_p_zb_zb } +inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_ph_p_p_p } +emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_ph_p_p_p } +inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_v16b_v16b_v16b, inst_orr_zb_p_zb_zb } +emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_v16b_v16b_v16b, emit_orr_zb_p_zb_zb } +inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_v16b_v16b_v16b, inst_eor_zb_p_zb_zb } +emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_v16b_v16b_v16b, emit_eor_zb_p_zb_zb } +inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_v16b_v16b_v16b, inst_bic_zb_p_zb_zb } +emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_v16b_v16b_v16b, emit_bic_zb_p_zb_zb } +inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_ph_p_p_p } +emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_ph_p_p_p } +inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_ps_p_p_p } +emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_ps_p_p_p } inst_eon :: inst_eon_r_r_sh emit_eon :: emit_eon_r_r_sh -inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_z_p_z_z, inst_lsl_r_r_i } -emit_lsl :: proc{ emit_lsl_r_r_r, emit_lsl_z_p_z_z, emit_lsl_r_r_i } -inst_lsr :: proc{ inst_lsr_r_r_r, inst_lsr_z_p_z_z, inst_lsr_r_r_i } -emit_lsr :: proc{ emit_lsr_r_r_r, emit_lsr_z_p_z_z, emit_lsr_r_r_i } -inst_asr :: proc{ inst_asr_r_r_r, inst_asr_z_p_z_z, inst_asr_r_r_i } -emit_asr :: proc{ emit_asr_r_r_r, emit_asr_z_p_z_z, emit_asr_r_r_i } +inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_zb_p_zb_zb, inst_lsl_r_r_i } +emit_lsl :: proc{ emit_lsl_r_r_r, emit_lsl_zb_p_zb_zb, emit_lsl_r_r_i } +inst_lsr :: proc{ inst_lsr_r_r_r, inst_lsr_zb_p_zb_zb, inst_lsr_r_r_i } +emit_lsr :: proc{ emit_lsr_r_r_r, emit_lsr_zb_p_zb_zb, emit_lsr_r_r_i } +inst_asr :: proc{ inst_asr_r_r_r, inst_asr_zb_p_zb_zb, inst_asr_r_r_i } +emit_asr :: proc{ emit_asr_r_r_r, emit_asr_zb_p_zb_zb, emit_asr_r_r_i } inst_ror :: proc{ inst_ror_r_r_r, inst_ror_r_r_i } emit_ror :: proc{ emit_ror_r_r_r, emit_ror_r_r_i } -inst_udiv :: proc{ inst_udiv_r_r_r, inst_udiv_z_p_z_z } -emit_udiv :: proc{ emit_udiv_r_r_r, emit_udiv_z_p_z_z } -inst_sdiv :: proc{ inst_sdiv_r_r_r, inst_sdiv_z_p_z_z } -emit_sdiv :: proc{ emit_sdiv_r_r_r, emit_sdiv_z_p_z_z } +inst_udiv :: proc{ inst_udiv_r_r_r, inst_udiv_zs_p_zs_zs } +emit_udiv :: proc{ emit_udiv_r_r_r, emit_udiv_zs_p_zs_zs } +inst_sdiv :: proc{ inst_sdiv_r_r_r, inst_sdiv_zs_p_zs_zs } +emit_sdiv :: proc{ emit_sdiv_r_r_r, emit_sdiv_zs_p_zs_zs } inst_madd :: inst_madd_r_r_r_r emit_madd :: emit_madd_r_r_r_r inst_msub :: inst_msub_r_r_r_r @@ -3778,18 +4366,18 @@ inst_umaddl :: inst_umaddl_r_r_r_r emit_umaddl :: emit_umaddl_r_r_r_r inst_umsubl :: inst_umsubl_r_r_r_r emit_umsubl :: emit_umsubl_r_r_r_r -inst_smulh :: proc{ inst_smulh_r_r_r, inst_smulh_z_p_z_z } -emit_smulh :: proc{ emit_smulh_r_r_r, emit_smulh_z_p_z_z } -inst_umulh :: proc{ inst_umulh_r_r_r, inst_umulh_z_p_z_z } -emit_umulh :: proc{ emit_umulh_r_r_r, emit_umulh_z_p_z_z } -inst_clz :: proc{ inst_clz_r_r, inst_clz_z_p_z } -emit_clz :: proc{ emit_clz_r_r, emit_clz_z_p_z } -inst_cls :: proc{ inst_cls_r_r, inst_cls_z_p_z } -emit_cls :: proc{ emit_cls_r_r, emit_cls_z_p_z } +inst_smulh :: proc{ inst_smulh_r_r_r, inst_smulh_zb_p_zb_zb } +emit_smulh :: proc{ emit_smulh_r_r_r, emit_smulh_zb_p_zb_zb } +inst_umulh :: proc{ inst_umulh_r_r_r, inst_umulh_zb_p_zb_zb } +emit_umulh :: proc{ emit_umulh_r_r_r, emit_umulh_zb_p_zb_zb } +inst_clz :: proc{ inst_clz_r_r, inst_clz_zb_p_zb } +emit_clz :: proc{ emit_clz_r_r, emit_clz_zb_p_zb } +inst_cls :: proc{ inst_cls_r_r, inst_cls_zb_p_zb } +emit_cls :: proc{ emit_cls_r_r, emit_cls_zb_p_zb } inst_rbit :: inst_rbit_r_r emit_rbit :: emit_rbit_r_r -inst_rev :: proc{ inst_rev_r_r, inst_rev_z_z } -emit_rev :: proc{ emit_rev_r_r, emit_rev_z_z } +inst_rev :: proc{ inst_rev_r_r, inst_rev_zb_zb } +emit_rev :: proc{ emit_rev_r_r, emit_rev_zb_zb } inst_rev16 :: inst_rev16_r_r emit_rev16 :: emit_rev16_r_r inst_rev32 :: inst_rev32_r_r @@ -3868,10 +4456,10 @@ inst_tbz :: inst_tbz_r_i_l emit_tbz :: emit_tbz_r_i_l inst_tbnz :: inst_tbnz_r_i_l emit_tbnz :: emit_tbnz_r_i_l -inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_z_m, inst_ldr_i_m } -emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_z_m, emit_ldr_i_m } -inst_str :: proc{ inst_str_r_m, inst_str_z_m, inst_str_i_m } -emit_str :: proc{ emit_str_r_m, emit_str_z_m, emit_str_i_m } +inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_zb_m, inst_ldr_i_m } +emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_zb_m, emit_ldr_i_m } +inst_str :: proc{ inst_str_r_m, inst_str_zb_m, inst_str_i_m } +emit_str :: proc{ emit_str_r_m, emit_str_zb_m, emit_str_i_m } inst_ldrb :: inst_ldrb_r_m emit_ldrb :: emit_ldrb_r_m inst_strb :: inst_strb_r_m @@ -3950,20 +4538,20 @@ inst_eret :: inst_eret_none emit_eret :: emit_eret_none inst_fmov :: proc{ inst_fmov_r_r, inst_fmov_r_i } emit_fmov :: proc{ emit_fmov_r_r, emit_fmov_r_i } -inst_fabs :: proc{ inst_fabs_r_r, inst_fabs_z_p_z } -emit_fabs :: proc{ emit_fabs_r_r, emit_fabs_z_p_z } -inst_fneg :: proc{ inst_fneg_r_r, inst_fneg_z_p_z } -emit_fneg :: proc{ emit_fneg_r_r, emit_fneg_z_p_z } -inst_fsqrt :: proc{ inst_fsqrt_r_r, inst_fsqrt_z_p_z } -emit_fsqrt :: proc{ emit_fsqrt_r_r, emit_fsqrt_z_p_z } -inst_fadd :: proc{ inst_fadd_r_r_r, inst_fadd_z_z_z, inst_fadd_z_p_z_z } -emit_fadd :: proc{ emit_fadd_r_r_r, emit_fadd_z_z_z, emit_fadd_z_p_z_z } -inst_fsub :: proc{ inst_fsub_r_r_r, inst_fsub_z_z_z, inst_fsub_z_p_z_z } -emit_fsub :: proc{ emit_fsub_r_r_r, emit_fsub_z_z_z, emit_fsub_z_p_z_z } -inst_fmul :: proc{ inst_fmul_r_r_r, inst_fmul_z_z_z, inst_fmul_z_p_z_z } -emit_fmul :: proc{ emit_fmul_r_r_r, emit_fmul_z_z_z, emit_fmul_z_p_z_z } -inst_fdiv :: proc{ inst_fdiv_r_r_r, inst_fdiv_z_p_z_z } -emit_fdiv :: proc{ emit_fdiv_r_r_r, emit_fdiv_z_p_z_z } +inst_fabs :: proc{ inst_fabs_r_r, inst_fabs_zh_p_zh } +emit_fabs :: proc{ emit_fabs_r_r, emit_fabs_zh_p_zh } +inst_fneg :: proc{ inst_fneg_r_r, inst_fneg_zh_p_zh } +emit_fneg :: proc{ emit_fneg_r_r, emit_fneg_zh_p_zh } +inst_fsqrt :: proc{ inst_fsqrt_r_r, inst_fsqrt_zh_p_zh } +emit_fsqrt :: proc{ emit_fsqrt_r_r, emit_fsqrt_zh_p_zh } +inst_fadd :: proc{ inst_fadd_r_r_r, inst_fadd_zh_zh_zh, inst_fadd_zh_p_zh_zh } +emit_fadd :: proc{ emit_fadd_r_r_r, emit_fadd_zh_zh_zh, emit_fadd_zh_p_zh_zh } +inst_fsub :: proc{ inst_fsub_r_r_r, inst_fsub_zh_zh_zh, inst_fsub_zh_p_zh_zh } +emit_fsub :: proc{ emit_fsub_r_r_r, emit_fsub_zh_zh_zh, emit_fsub_zh_p_zh_zh } +inst_fmul :: proc{ inst_fmul_r_r_r, inst_fmul_zh_zh_zh, inst_fmul_zh_p_zh_zh } +emit_fmul :: proc{ emit_fmul_r_r_r, emit_fmul_zh_zh_zh, emit_fmul_zh_p_zh_zh } +inst_fdiv :: proc{ inst_fdiv_r_r_r, inst_fdiv_zh_p_zh_zh } +emit_fdiv :: proc{ emit_fdiv_r_r_r, emit_fdiv_zh_p_zh_zh } inst_fnmul :: inst_fnmul_r_r_r emit_fnmul :: emit_fnmul_r_r_r inst_fmadd :: inst_fmadd_r_r_r_r @@ -3980,14 +4568,14 @@ inst_fcmpe :: inst_fcmpe_r_r emit_fcmpe :: emit_fcmpe_r_r inst_fcsel :: inst_fcsel_r_r_r_c emit_fcsel :: emit_fcsel_r_r_r_c -inst_fmax :: proc{ inst_fmax_r_r_r, inst_fmax_z_p_z_z } -emit_fmax :: proc{ emit_fmax_r_r_r, emit_fmax_z_p_z_z } -inst_fmin :: proc{ inst_fmin_r_r_r, inst_fmin_z_p_z_z } -emit_fmin :: proc{ emit_fmin_r_r_r, emit_fmin_z_p_z_z } -inst_fmaxnm :: proc{ inst_fmaxnm_r_r_r, inst_fmaxnm_z_p_z_z } -emit_fmaxnm :: proc{ emit_fmaxnm_r_r_r, emit_fmaxnm_z_p_z_z } -inst_fminnm :: proc{ inst_fminnm_r_r_r, inst_fminnm_z_p_z_z } -emit_fminnm :: proc{ emit_fminnm_r_r_r, emit_fminnm_z_p_z_z } +inst_fmax :: proc{ inst_fmax_r_r_r, inst_fmax_zh_p_zh_zh } +emit_fmax :: proc{ emit_fmax_r_r_r, emit_fmax_zh_p_zh_zh } +inst_fmin :: proc{ inst_fmin_r_r_r, inst_fmin_zh_p_zh_zh } +emit_fmin :: proc{ emit_fmin_r_r_r, emit_fmin_zh_p_zh_zh } +inst_fmaxnm :: proc{ inst_fmaxnm_r_r_r, inst_fmaxnm_zh_p_zh_zh } +emit_fmaxnm :: proc{ emit_fmaxnm_r_r_r, emit_fmaxnm_zh_p_zh_zh } +inst_fminnm :: proc{ inst_fminnm_r_r_r, inst_fminnm_zh_p_zh_zh } +emit_fminnm :: proc{ emit_fminnm_r_r_r, emit_fminnm_zh_p_zh_zh } inst_fcvt :: inst_fcvt_r_r emit_fcvt :: emit_fcvt_r_r inst_scvtf :: inst_scvtf_r_r @@ -4014,20 +4602,20 @@ inst_fcvtms :: inst_fcvtms_r_r emit_fcvtms :: emit_fcvtms_r_r inst_fcvtmu :: inst_fcvtmu_r_r emit_fcvtmu :: emit_fcvtmu_r_r -inst_frinta :: proc{ inst_frinta_r_r, inst_frinta_z_p_z } -emit_frinta :: proc{ emit_frinta_r_r, emit_frinta_z_p_z } -inst_frinti :: proc{ inst_frinti_r_r, inst_frinti_z_p_z } -emit_frinti :: proc{ emit_frinti_r_r, emit_frinti_z_p_z } -inst_frintm :: proc{ inst_frintm_r_r, inst_frintm_z_p_z } -emit_frintm :: proc{ emit_frintm_r_r, emit_frintm_z_p_z } -inst_frintn :: proc{ inst_frintn_r_r, inst_frintn_z_p_z } -emit_frintn :: proc{ emit_frintn_r_r, emit_frintn_z_p_z } -inst_frintp :: proc{ inst_frintp_r_r, inst_frintp_z_p_z } -emit_frintp :: proc{ emit_frintp_r_r, emit_frintp_z_p_z } -inst_frintx :: proc{ inst_frintx_r_r, inst_frintx_z_p_z } -emit_frintx :: proc{ emit_frintx_r_r, emit_frintx_z_p_z } -inst_frintz :: proc{ inst_frintz_r_r, inst_frintz_z_p_z } -emit_frintz :: proc{ emit_frintz_r_r, emit_frintz_z_p_z } +inst_frinta :: proc{ inst_frinta_r_r, inst_frinta_zh_p_zh } +emit_frinta :: proc{ emit_frinta_r_r, emit_frinta_zh_p_zh } +inst_frinti :: proc{ inst_frinti_r_r, inst_frinti_zh_p_zh } +emit_frinti :: proc{ emit_frinti_r_r, emit_frinti_zh_p_zh } +inst_frintm :: proc{ inst_frintm_r_r, inst_frintm_zh_p_zh } +emit_frintm :: proc{ emit_frintm_r_r, emit_frintm_zh_p_zh } +inst_frintn :: proc{ inst_frintn_r_r, inst_frintn_zh_p_zh } +emit_frintn :: proc{ emit_frintn_r_r, emit_frintn_zh_p_zh } +inst_frintp :: proc{ inst_frintp_r_r, inst_frintp_zh_p_zh } +emit_frintp :: proc{ emit_frintp_r_r, emit_frintp_zh_p_zh } +inst_frintx :: proc{ inst_frintx_r_r, inst_frintx_zh_p_zh } +emit_frintx :: proc{ emit_frintx_r_r, emit_frintx_zh_p_zh } +inst_frintz :: proc{ inst_frintz_r_r, inst_frintz_zh_p_zh } +emit_frintz :: proc{ emit_frintz_r_r, emit_frintz_zh_p_zh } inst_tst :: proc{ inst_tst_r_i, inst_tst_r_sh } emit_tst :: proc{ emit_tst_r_i, emit_tst_r_sh } inst_ldur :: inst_ldur_r_m @@ -4314,14 +4902,14 @@ inst_crc32cw :: inst_crc32cw_r_r_r emit_crc32cw :: emit_crc32cw_r_r_r inst_crc32cx :: inst_crc32cx_r_r_r emit_crc32cx :: emit_crc32cx_r_r_r -inst_aese :: proc{ inst_aese_v16b_v16b, inst_aese_z_z } -emit_aese :: proc{ emit_aese_v16b_v16b, emit_aese_z_z } -inst_aesd :: proc{ inst_aesd_v16b_v16b, inst_aesd_z_z } -emit_aesd :: proc{ emit_aesd_v16b_v16b, emit_aesd_z_z } -inst_aesmc :: proc{ inst_aesmc_v16b_v16b, inst_aesmc_z } -emit_aesmc :: proc{ emit_aesmc_v16b_v16b, emit_aesmc_z } -inst_aesimc :: proc{ inst_aesimc_v16b_v16b, inst_aesimc_z } -emit_aesimc :: proc{ emit_aesimc_v16b_v16b, emit_aesimc_z } +inst_aese :: proc{ inst_aese_v16b_v16b, inst_aese_zb_zb } +emit_aese :: proc{ emit_aese_v16b_v16b, emit_aese_zb_zb } +inst_aesd :: proc{ inst_aesd_v16b_v16b, inst_aesd_zb_zb } +emit_aesd :: proc{ emit_aesd_v16b_v16b, emit_aesd_zb_zb } +inst_aesmc :: proc{ inst_aesmc_v16b_v16b, inst_aesmc_zb } +emit_aesmc :: proc{ emit_aesmc_v16b_v16b, emit_aesmc_zb } +inst_aesimc :: proc{ inst_aesimc_v16b_v16b, inst_aesimc_zb } +emit_aesimc :: proc{ emit_aesimc_v16b_v16b, emit_aesimc_zb } inst_sha1h :: inst_sha1h_r_r emit_sha1h :: emit_sha1h_r_r inst_sha1c :: inst_sha1c_r_r_v4s @@ -4350,10 +4938,10 @@ inst_sha512su0 :: inst_sha512su0_v2d_v2d emit_sha512su0 :: emit_sha512su0_v2d_v2d inst_sha512su1 :: inst_sha512su1_v2d_v2d_v2d emit_sha512su1 :: emit_sha512su1_v2d_v2d_v2d -inst_eor3 :: proc{ inst_eor3_v16b_v16b_v16b_v16b, inst_eor3_z_z_z_z } -emit_eor3 :: proc{ emit_eor3_v16b_v16b_v16b_v16b, emit_eor3_z_z_z_z } -inst_bcax :: proc{ inst_bcax_v16b_v16b_v16b_v16b, inst_bcax_z_z_z_z } -emit_bcax :: proc{ emit_bcax_v16b_v16b_v16b_v16b, emit_bcax_z_z_z_z } +inst_eor3 :: proc{ inst_eor3_v16b_v16b_v16b_v16b, inst_eor3_zd_zd_zd_zd } +emit_eor3 :: proc{ emit_eor3_v16b_v16b_v16b_v16b, emit_eor3_zd_zd_zd_zd } +inst_bcax :: proc{ inst_bcax_v16b_v16b_v16b_v16b, inst_bcax_zd_zd_zd_zd } +emit_bcax :: proc{ emit_bcax_v16b_v16b_v16b_v16b, emit_bcax_zd_zd_zd_zd } inst_rax1 :: inst_rax1_v2d_v2d_v2d emit_rax1 :: emit_rax1_v2d_v2d_v2d inst_xar :: proc{ inst_xar_v2d_v2d_v2d_i, inst_xar_z_z_z_i } @@ -4380,8 +4968,8 @@ inst_pmull :: inst_pmull_v8h_v8b_v8b emit_pmull :: emit_pmull_v8h_v8b_v8b inst_pmull2 :: inst_pmull2_v8h_v16b_v16b emit_pmull2 :: emit_pmull2_v8h_v16b_v16b -inst_bfcvt :: proc{ inst_bfcvt_r_r, inst_bfcvt_z_p_z } -emit_bfcvt :: proc{ emit_bfcvt_r_r, emit_bfcvt_z_p_z } +inst_bfcvt :: proc{ inst_bfcvt_r_r, inst_bfcvt_zh_p_zs } +emit_bfcvt :: proc{ emit_bfcvt_r_r, emit_bfcvt_zh_p_zs } inst_bfdot :: inst_bfdot_v4s_v8h_v8h emit_bfdot :: emit_bfdot_v4s_v8h_v8h inst_bfmmla :: inst_bfmmla_v4s_v8h_v8h @@ -4394,16 +4982,16 @@ inst_bfcvtn :: inst_bfcvtn_v4h_v4s emit_bfcvtn :: emit_bfcvtn_v4h_v4s inst_bfcvtn2 :: inst_bfcvtn2_v8h_v4s emit_bfcvtn2 :: emit_bfcvtn2_v8h_v4s -inst_mul :: proc{ inst_mul_v16b_v16b_v16b, inst_mul_z_p_z_z } -emit_mul :: proc{ emit_mul_v16b_v16b_v16b, emit_mul_z_p_z_z } +inst_mul :: proc{ inst_mul_v16b_v16b_v16b, inst_mul_zb_p_zb_zb } +emit_mul :: proc{ emit_mul_v16b_v16b_v16b, emit_mul_zb_p_zb_zb } inst_mla :: inst_mla_v8b_v8b_v8b emit_mla :: emit_mla_v8b_v8b_v8b inst_mls :: inst_mls_v8b_v8b_v8b emit_mls :: emit_mls_v8b_v8b_v8b -inst_neg :: proc{ inst_neg_v8b_v8b, inst_neg_z_p_z, inst_neg_r_sh } -emit_neg :: proc{ emit_neg_v8b_v8b, emit_neg_z_p_z, emit_neg_r_sh } -inst_abs :: proc{ inst_abs_v8b_v8b, inst_abs_z_p_z } -emit_abs :: proc{ emit_abs_v8b_v8b, emit_abs_z_p_z } +inst_neg :: proc{ inst_neg_v8b_v8b, inst_neg_zb_p_zb, inst_neg_r_sh } +emit_neg :: proc{ emit_neg_v8b_v8b, emit_neg_zb_p_zb, emit_neg_r_sh } +inst_abs :: proc{ inst_abs_v8b_v8b, inst_abs_zb_p_zb } +emit_abs :: proc{ emit_abs_v8b_v8b, emit_abs_zb_p_zb } inst_shadd :: inst_shadd_v8b_v8b_v8b emit_shadd :: emit_shadd_v8b_v8b_v8b inst_uhadd :: inst_uhadd_v8b_v8b_v8b @@ -4416,26 +5004,26 @@ inst_srhadd :: inst_srhadd_v8b_v8b_v8b emit_srhadd :: emit_srhadd_v8b_v8b_v8b inst_urhadd :: inst_urhadd_v8b_v8b_v8b emit_urhadd :: emit_urhadd_v8b_v8b_v8b -inst_sqadd :: proc{ inst_sqadd_v8b_v8b_v8b, inst_sqadd_z_z_z } -emit_sqadd :: proc{ emit_sqadd_v8b_v8b_v8b, emit_sqadd_z_z_z } -inst_uqadd :: proc{ inst_uqadd_v8b_v8b_v8b, inst_uqadd_z_z_z } -emit_uqadd :: proc{ emit_uqadd_v8b_v8b_v8b, emit_uqadd_z_z_z } -inst_sqsub :: proc{ inst_sqsub_v8b_v8b_v8b, inst_sqsub_z_z_z } -emit_sqsub :: proc{ emit_sqsub_v8b_v8b_v8b, emit_sqsub_z_z_z } -inst_uqsub :: proc{ inst_uqsub_v8b_v8b_v8b, inst_uqsub_z_z_z } -emit_uqsub :: proc{ emit_uqsub_v8b_v8b_v8b, emit_uqsub_z_z_z } -inst_smax :: proc{ inst_smax_v8b_v8b_v8b, inst_smax_z_p_z_z } -emit_smax :: proc{ emit_smax_v8b_v8b_v8b, emit_smax_z_p_z_z } -inst_umax :: proc{ inst_umax_v8b_v8b_v8b, inst_umax_z_p_z_z } -emit_umax :: proc{ emit_umax_v8b_v8b_v8b, emit_umax_z_p_z_z } -inst_smin :: proc{ inst_smin_v8b_v8b_v8b, inst_smin_z_p_z_z } -emit_smin :: proc{ emit_smin_v8b_v8b_v8b, emit_smin_z_p_z_z } -inst_umin :: proc{ inst_umin_v8b_v8b_v8b, inst_umin_z_p_z_z } -emit_umin :: proc{ emit_umin_v8b_v8b_v8b, emit_umin_z_p_z_z } -inst_sabd :: proc{ inst_sabd_v8b_v8b_v8b, inst_sabd_z_p_z_z } -emit_sabd :: proc{ emit_sabd_v8b_v8b_v8b, emit_sabd_z_p_z_z } -inst_uabd :: proc{ inst_uabd_v8b_v8b_v8b, inst_uabd_z_p_z_z } -emit_uabd :: proc{ emit_uabd_v8b_v8b_v8b, emit_uabd_z_p_z_z } +inst_sqadd :: proc{ inst_sqadd_v8b_v8b_v8b, inst_sqadd_zb_zb_zb } +emit_sqadd :: proc{ emit_sqadd_v8b_v8b_v8b, emit_sqadd_zb_zb_zb } +inst_uqadd :: proc{ inst_uqadd_v8b_v8b_v8b, inst_uqadd_zb_zb_zb } +emit_uqadd :: proc{ emit_uqadd_v8b_v8b_v8b, emit_uqadd_zb_zb_zb } +inst_sqsub :: proc{ inst_sqsub_v8b_v8b_v8b, inst_sqsub_zb_zb_zb } +emit_sqsub :: proc{ emit_sqsub_v8b_v8b_v8b, emit_sqsub_zb_zb_zb } +inst_uqsub :: proc{ inst_uqsub_v8b_v8b_v8b, inst_uqsub_zb_zb_zb } +emit_uqsub :: proc{ emit_uqsub_v8b_v8b_v8b, emit_uqsub_zb_zb_zb } +inst_smax :: proc{ inst_smax_v8b_v8b_v8b, inst_smax_zb_p_zb_zb } +emit_smax :: proc{ emit_smax_v8b_v8b_v8b, emit_smax_zb_p_zb_zb } +inst_umax :: proc{ inst_umax_v8b_v8b_v8b, inst_umax_zb_p_zb_zb } +emit_umax :: proc{ emit_umax_v8b_v8b_v8b, emit_umax_zb_p_zb_zb } +inst_smin :: proc{ inst_smin_v8b_v8b_v8b, inst_smin_zb_p_zb_zb } +emit_smin :: proc{ emit_smin_v8b_v8b_v8b, emit_smin_zb_p_zb_zb } +inst_umin :: proc{ inst_umin_v8b_v8b_v8b, inst_umin_zb_p_zb_zb } +emit_umin :: proc{ emit_umin_v8b_v8b_v8b, emit_umin_zb_p_zb_zb } +inst_sabd :: proc{ inst_sabd_v8b_v8b_v8b, inst_sabd_zb_p_zb_zb } +emit_sabd :: proc{ emit_sabd_v8b_v8b_v8b, emit_sabd_zb_p_zb_zb } +inst_uabd :: proc{ inst_uabd_v8b_v8b_v8b, inst_uabd_zb_p_zb_zb } +emit_uabd :: proc{ emit_uabd_v8b_v8b_v8b, emit_uabd_zb_p_zb_zb } inst_saba :: inst_saba_v8b_v8b_v8b emit_saba :: emit_saba_v8b_v8b_v8b inst_uaba :: inst_uaba_v8b_v8b_v8b @@ -4582,10 +5170,10 @@ inst_udot :: inst_udot_v2s_v8b_v8b emit_udot :: emit_udot_v2s_v8b_v8b inst_usdot :: inst_usdot_v2s_v8b_v8b emit_usdot :: emit_usdot_v2s_v8b_v8b -inst_fmla :: proc{ inst_fmla_v4s_v4s_v4s, inst_fmla_z_p_z_z, inst_fmla_z_z_z_i } -emit_fmla :: proc{ emit_fmla_v4s_v4s_v4s, emit_fmla_z_p_z_z, emit_fmla_z_z_z_i } -inst_fmls :: proc{ inst_fmls_v4s_v4s_v4s, inst_fmls_z_p_z_z, inst_fmls_z_z_z_i } -emit_fmls :: proc{ emit_fmls_v4s_v4s_v4s, emit_fmls_z_p_z_z, emit_fmls_z_z_z_i } +inst_fmla :: proc{ inst_fmla_v4s_v4s_v4s, inst_fmla_zh_p_zh_zh, inst_fmla_zh_zh_zh_i } +emit_fmla :: proc{ emit_fmla_v4s_v4s_v4s, emit_fmla_zh_p_zh_zh, emit_fmla_zh_zh_zh_i } +inst_fmls :: proc{ inst_fmls_v4s_v4s_v4s, inst_fmls_zh_p_zh_zh, inst_fmls_zh_zh_zh_i } +emit_fmls :: proc{ emit_fmls_v4s_v4s_v4s, emit_fmls_zh_p_zh_zh, emit_fmls_zh_zh_zh_i } inst_fmulx :: inst_fmulx_v2s_v2s_v2s emit_fmulx :: emit_fmulx_v2s_v2s_v2s inst_fmaxp :: inst_fmaxp_v2s_v2s_v2s @@ -4608,12 +5196,12 @@ inst_frecpe :: inst_frecpe_v2s_v2s emit_frecpe :: emit_frecpe_v2s_v2s inst_frsqrte :: inst_frsqrte_v2s_v2s emit_frsqrte :: emit_frsqrte_v2s_v2s -inst_frecps :: proc{ inst_frecps_v2s_v2s_v2s, inst_frecps_z_z_z } -emit_frecps :: proc{ emit_frecps_v2s_v2s_v2s, emit_frecps_z_z_z } -inst_frsqrts :: proc{ inst_frsqrts_v2s_v2s_v2s, inst_frsqrts_z_z_z } -emit_frsqrts :: proc{ emit_frsqrts_v2s_v2s_v2s, emit_frsqrts_z_z_z } -inst_frecpx :: proc{ inst_frecpx_r_r, inst_frecpx_z_p_z } -emit_frecpx :: proc{ emit_frecpx_r_r, emit_frecpx_z_p_z } +inst_frecps :: proc{ inst_frecps_v2s_v2s_v2s, inst_frecps_zh_zh_zh } +emit_frecps :: proc{ emit_frecps_v2s_v2s_v2s, emit_frecps_zh_zh_zh } +inst_frsqrts :: proc{ inst_frsqrts_v2s_v2s_v2s, inst_frsqrts_zh_zh_zh } +emit_frsqrts :: proc{ emit_frsqrts_v2s_v2s_v2s, emit_frsqrts_zh_zh_zh } +inst_frecpx :: proc{ inst_frecpx_r_r, inst_frecpx_zh_p_zh } +emit_frecpx :: proc{ emit_frecpx_r_r, emit_frecpx_zh_p_zh } inst_faddp :: inst_faddp_v2s_v2s_v2s emit_faddp :: emit_faddp_v2s_v2s_v2s inst_fcvtl :: inst_fcvtl_v4s_v4h @@ -4628,16 +5216,16 @@ inst_fcvtxn :: inst_fcvtxn_v2s_v2d emit_fcvtxn :: emit_fcvtxn_v2s_v2d inst_fcvtxn2 :: inst_fcvtxn2_v4s_v2d emit_fcvtxn2 :: emit_fcvtxn2_v4s_v2d -inst_fcmeq :: proc{ inst_fcmeq_v2s_v2s_v2s, inst_fcmeq_p_p_z_z } -emit_fcmeq :: proc{ emit_fcmeq_v2s_v2s_v2s, emit_fcmeq_p_p_z_z } -inst_fcmge :: proc{ inst_fcmge_v2s_v2s_v2s, inst_fcmge_p_p_z_z } -emit_fcmge :: proc{ emit_fcmge_v2s_v2s_v2s, emit_fcmge_p_p_z_z } -inst_fcmgt :: proc{ inst_fcmgt_v2s_v2s_v2s, inst_fcmgt_p_p_z_z } -emit_fcmgt :: proc{ emit_fcmgt_v2s_v2s_v2s, emit_fcmgt_p_p_z_z } -inst_fcmle :: proc{ inst_fcmle_v2s_v2s, inst_fcmle_p_p_z } -emit_fcmle :: proc{ emit_fcmle_v2s_v2s, emit_fcmle_p_p_z } -inst_fcmlt :: proc{ inst_fcmlt_v2s_v2s, inst_fcmlt_p_p_z } -emit_fcmlt :: proc{ emit_fcmlt_v2s_v2s, emit_fcmlt_p_p_z } +inst_fcmeq :: proc{ inst_fcmeq_v2s_v2s_v2s, inst_fcmeq_ph_p_zh_zh } +emit_fcmeq :: proc{ emit_fcmeq_v2s_v2s_v2s, emit_fcmeq_ph_p_zh_zh } +inst_fcmge :: proc{ inst_fcmge_v2s_v2s_v2s, inst_fcmge_ph_p_zh_zh } +emit_fcmge :: proc{ emit_fcmge_v2s_v2s_v2s, emit_fcmge_ph_p_zh_zh } +inst_fcmgt :: proc{ inst_fcmgt_v2s_v2s_v2s, inst_fcmgt_ph_p_zh_zh } +emit_fcmgt :: proc{ emit_fcmgt_v2s_v2s_v2s, emit_fcmgt_ph_p_zh_zh } +inst_fcmle :: proc{ inst_fcmle_v2s_v2s, inst_fcmle_ph_p_zh } +emit_fcmle :: proc{ emit_fcmle_v2s_v2s, emit_fcmle_ph_p_zh } +inst_fcmlt :: proc{ inst_fcmlt_v2s_v2s, inst_fcmlt_ph_p_zh } +emit_fcmlt :: proc{ emit_fcmlt_v2s_v2s, emit_fcmlt_ph_p_zh } inst_facge :: inst_facge_v2s_v2s_v2s emit_facge :: emit_facge_v2s_v2s_v2s inst_facgt :: inst_facgt_v2s_v2s_v2s @@ -4664,8 +5252,8 @@ inst_bit :: inst_bit_v16b_v16b_v16b emit_bit :: emit_bit_v16b_v16b_v16b inst_bif :: inst_bif_v16b_v16b_v16b emit_bif :: emit_bif_v16b_v16b_v16b -inst_bsl :: proc{ inst_bsl_v16b_v16b_v16b, inst_bsl_z_z_z_z } -emit_bsl :: proc{ emit_bsl_v16b_v16b_v16b, emit_bsl_z_z_z_z } +inst_bsl :: proc{ inst_bsl_v16b_v16b_v16b, inst_bsl_zd_zd_zd_zd } +emit_bsl :: proc{ emit_bsl_v16b_v16b_v16b, emit_bsl_zd_zd_zd_zd } inst_shl :: inst_shl_v8b_v8b_i emit_shl :: emit_shl_v8b_v8b_i inst_sqshl :: inst_sqshl_v8b_v8b_i @@ -4748,36 +5336,36 @@ inst_sqrshrun :: inst_sqrshrun_v8b_v8h_i emit_sqrshrun :: emit_sqrshrun_v8b_v8h_i inst_sqrshrun2 :: inst_sqrshrun2_v16b_v8h_i emit_sqrshrun2 :: emit_sqrshrun2_v16b_v8h_i -inst_dup :: proc{ inst_dup_v8b_veb_i, inst_dup_v8b_r, inst_dup_z_r } -emit_dup :: proc{ emit_dup_v8b_veb_i, emit_dup_v8b_r, emit_dup_z_r } +inst_dup :: proc{ inst_dup_v8b_veb_i, inst_dup_v8b_r, inst_dup_zb_r } +emit_dup :: proc{ emit_dup_v8b_veb_i, emit_dup_v8b_r, emit_dup_zb_r } inst_ins :: proc{ inst_ins_veb_i_veb_i, inst_ins_veb_i_r } emit_ins :: proc{ emit_ins_veb_i_veb_i, emit_ins_veb_i_r } -inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_z_p_z, inst_mov_p_p, inst_mov_r_i } -emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_z_p_z, emit_mov_p_p, emit_mov_r_i } -inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_z_z_z_i } -emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_z_z_z_i } -inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_z_z_z } -emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_z_z_z } -inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_z_z_z } -emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_z_z_z } -inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_z_z_z } -emit_zip1 :: proc{ emit_zip1_v8b_v8b_v8b, emit_zip1_z_z_z } -inst_zip2 :: proc{ inst_zip2_v8b_v8b_v8b, inst_zip2_z_z_z } -emit_zip2 :: proc{ emit_zip2_v8b_v8b_v8b, emit_zip2_z_z_z } -inst_uzp1 :: proc{ inst_uzp1_v8b_v8b_v8b, inst_uzp1_z_z_z } -emit_uzp1 :: proc{ emit_uzp1_v8b_v8b_v8b, emit_uzp1_z_z_z } -inst_uzp2 :: proc{ inst_uzp2_v8b_v8b_v8b, inst_uzp2_z_z_z } -emit_uzp2 :: proc{ emit_uzp2_v8b_v8b_v8b, emit_uzp2_z_z_z } -inst_trn1 :: proc{ inst_trn1_v8b_v8b_v8b, inst_trn1_z_z_z } -emit_trn1 :: proc{ emit_trn1_v8b_v8b_v8b, emit_trn1_z_z_z } -inst_trn2 :: proc{ inst_trn2_v8b_v8b_v8b, inst_trn2_z_z_z } -emit_trn2 :: proc{ emit_trn2_v8b_v8b_v8b, emit_trn2_z_z_z } -inst_not :: proc{ inst_not_v8b_v8b, inst_not_p_p_p } -emit_not :: proc{ emit_not_v8b_v8b, emit_not_p_p_p } +inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_zb_p_zb, inst_mov_ps_p, inst_mov_r_i } +emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_zb_p_zb, emit_mov_ps_p, emit_mov_r_i } +inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_zb_zb_zb_i } +emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_zb_zb_zb_i } +inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_zb_zb_zb } +emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_zb_zb_zb } +inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_zb_zb_zb } +emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_zb_zb_zb } +inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_zb_zb_zb } +emit_zip1 :: proc{ emit_zip1_v8b_v8b_v8b, emit_zip1_zb_zb_zb } +inst_zip2 :: proc{ inst_zip2_v8b_v8b_v8b, inst_zip2_zb_zb_zb } +emit_zip2 :: proc{ emit_zip2_v8b_v8b_v8b, emit_zip2_zb_zb_zb } +inst_uzp1 :: proc{ inst_uzp1_v8b_v8b_v8b, inst_uzp1_zb_zb_zb } +emit_uzp1 :: proc{ emit_uzp1_v8b_v8b_v8b, emit_uzp1_zb_zb_zb } +inst_uzp2 :: proc{ inst_uzp2_v8b_v8b_v8b, inst_uzp2_zb_zb_zb } +emit_uzp2 :: proc{ emit_uzp2_v8b_v8b_v8b, emit_uzp2_zb_zb_zb } +inst_trn1 :: proc{ inst_trn1_v8b_v8b_v8b, inst_trn1_zb_zb_zb } +emit_trn1 :: proc{ emit_trn1_v8b_v8b_v8b, emit_trn1_zb_zb_zb } +inst_trn2 :: proc{ inst_trn2_v8b_v8b_v8b, inst_trn2_zb_zb_zb } +emit_trn2 :: proc{ emit_trn2_v8b_v8b_v8b, emit_trn2_zb_zb_zb } +inst_not :: proc{ inst_not_v8b_v8b, inst_not_pb_p_p } +emit_not :: proc{ emit_not_v8b_v8b, emit_not_pb_p_p } inst_rev64 :: inst_rev64_v8b_v8b emit_rev64 :: emit_rev64_v8b_v8b -inst_cnt :: proc{ inst_cnt_v8b_v8b, inst_cnt_z_p_z } -emit_cnt :: proc{ emit_cnt_v8b_v8b, emit_cnt_z_p_z } +inst_cnt :: proc{ inst_cnt_v8b_v8b, inst_cnt_zb_p_zb } +emit_cnt :: proc{ emit_cnt_v8b_v8b, emit_cnt_zb_p_zb } inst_urecpe :: inst_urecpe_v2s_v2s emit_urecpe :: emit_urecpe_v2s_v2s inst_ursqrte :: inst_ursqrte_v2s_v2s @@ -4810,132 +5398,132 @@ inst_ld3r :: inst_ld3r_v16b_m emit_ld3r :: emit_ld3r_v16b_m inst_ld4r :: inst_ld4r_v16b_m emit_ld4r :: emit_ld4r_v16b_m -inst_subr :: inst_subr_z_p_z_z -emit_subr :: emit_subr_z_p_z_z -inst_asrr :: inst_asrr_z_p_z_z -emit_asrr :: emit_asrr_z_p_z_z -inst_lslr :: inst_lslr_z_p_z_z -emit_lslr :: emit_lslr_z_p_z_z -inst_lsrr :: inst_lsrr_z_p_z_z -emit_lsrr :: emit_lsrr_z_p_z_z -inst_ftsmul :: inst_ftsmul_z_z_z -emit_ftsmul :: emit_ftsmul_z_z_z -inst_fsubr :: inst_fsubr_z_p_z_z -emit_fsubr :: emit_fsubr_z_p_z_z -inst_fdivr :: inst_fdivr_z_p_z_z -emit_fdivr :: emit_fdivr_z_p_z_z -inst_fnmla :: inst_fnmla_z_p_z_z -emit_fnmla :: emit_fnmla_z_p_z_z -inst_fnmls :: inst_fnmls_z_p_z_z -emit_fnmls :: emit_fnmls_z_p_z_z -inst_nand :: inst_nand_p_p_p_p -emit_nand :: emit_nand_p_p_p_p -inst_nor :: inst_nor_p_p_p_p -emit_nor :: emit_nor_p_p_p_p -inst_sel :: inst_sel_p_p_p_p -emit_sel :: emit_sel_p_p_p_p -inst_orrs :: inst_orrs_p_p_p_p -emit_orrs :: emit_orrs_p_p_p_p -inst_eors :: inst_eors_p_p_p_p -emit_eors :: emit_eors_p_p_p_p -inst_nands :: inst_nands_p_p_p_p -emit_nands :: emit_nands_p_p_p_p -inst_nors :: inst_nors_p_p_p_p -emit_nors :: emit_nors_p_p_p_p -inst_orns :: inst_orns_p_p_p_p -emit_orns :: emit_orns_p_p_p_p -inst_movs :: inst_movs_p_p_p -emit_movs :: emit_movs_p_p_p -inst_ptrue :: inst_ptrue_p_i -emit_ptrue :: emit_ptrue_p_i -inst_ptrues :: inst_ptrues_p_i -emit_ptrues :: emit_ptrues_p_i -inst_pfalse :: inst_pfalse_p -emit_pfalse :: emit_pfalse_p -inst_pfirst :: inst_pfirst_p_p_p -emit_pfirst :: emit_pfirst_p_p_p -inst_pnext :: inst_pnext_p_p_p -emit_pnext :: emit_pnext_p_p_p -inst_brka :: inst_brka_p_p_p -emit_brka :: emit_brka_p_p_p -inst_brkb :: inst_brkb_p_p_p -emit_brkb :: emit_brkb_p_p_p -inst_brkas :: inst_brkas_p_p_p -emit_brkas :: emit_brkas_p_p_p -inst_brkbs :: inst_brkbs_p_p_p -emit_brkbs :: emit_brkbs_p_p_p -inst_brkpa :: inst_brkpa_p_p_p_p -emit_brkpa :: emit_brkpa_p_p_p_p -inst_brkpb :: inst_brkpb_p_p_p_p -emit_brkpb :: emit_brkpb_p_p_p_p -inst_brkn :: inst_brkn_p_p_p_p -emit_brkn :: emit_brkn_p_p_p_p -inst_rdffr :: inst_rdffr_p -emit_rdffr :: emit_rdffr_p +inst_subr :: inst_subr_zb_p_zb_zb +emit_subr :: emit_subr_zb_p_zb_zb +inst_asrr :: inst_asrr_zb_p_zb_zb +emit_asrr :: emit_asrr_zb_p_zb_zb +inst_lslr :: inst_lslr_zb_p_zb_zb +emit_lslr :: emit_lslr_zb_p_zb_zb +inst_lsrr :: inst_lsrr_zb_p_zb_zb +emit_lsrr :: emit_lsrr_zb_p_zb_zb +inst_ftsmul :: inst_ftsmul_zh_zh_zh +emit_ftsmul :: emit_ftsmul_zh_zh_zh +inst_fsubr :: inst_fsubr_zh_p_zh_zh +emit_fsubr :: emit_fsubr_zh_p_zh_zh +inst_fdivr :: inst_fdivr_zh_p_zh_zh +emit_fdivr :: emit_fdivr_zh_p_zh_zh +inst_fnmla :: inst_fnmla_zh_p_zh_zh +emit_fnmla :: emit_fnmla_zh_p_zh_zh +inst_fnmls :: inst_fnmls_zh_p_zh_zh +emit_fnmls :: emit_fnmls_zh_p_zh_zh +inst_nand :: inst_nand_ps_p_p_p +emit_nand :: emit_nand_ps_p_p_p +inst_nor :: inst_nor_ps_p_p_p +emit_nor :: emit_nor_ps_p_p_p +inst_sel :: inst_sel_pb_p_p_p +emit_sel :: emit_sel_pb_p_p_p +inst_orrs :: inst_orrs_pd_p_p_p +emit_orrs :: emit_orrs_pd_p_p_p +inst_eors :: inst_eors_ph_p_p_p +emit_eors :: emit_eors_ph_p_p_p +inst_nands :: inst_nands_pd_p_p_p +emit_nands :: emit_nands_pd_p_p_p +inst_nors :: inst_nors_pd_p_p_p +emit_nors :: emit_nors_pd_p_p_p +inst_orns :: inst_orns_pd_p_p_p +emit_orns :: emit_orns_pd_p_p_p +inst_movs :: inst_movs_ph_p_p +emit_movs :: emit_movs_ph_p_p +inst_ptrue :: inst_ptrue_pb_i +emit_ptrue :: emit_ptrue_pb_i +inst_ptrues :: inst_ptrues_pb_i +emit_ptrues :: emit_ptrues_pb_i +inst_pfalse :: inst_pfalse_pb +emit_pfalse :: emit_pfalse_pb +inst_pfirst :: inst_pfirst_ph_p_p +emit_pfirst :: emit_pfirst_ph_p_p +inst_pnext :: inst_pnext_pb_p_p +emit_pnext :: emit_pnext_pb_p_p +inst_brka :: inst_brka_pb_p_p +emit_brka :: emit_brka_pb_p_p +inst_brkb :: inst_brkb_ps_p_p +emit_brkb :: emit_brkb_ps_p_p +inst_brkas :: inst_brkas_ph_p_p +emit_brkas :: emit_brkas_ph_p_p +inst_brkbs :: inst_brkbs_pd_p_p +emit_brkbs :: emit_brkbs_pd_p_p +inst_brkpa :: inst_brkpa_pb_p_p_p +emit_brkpa :: emit_brkpa_pb_p_p_p +inst_brkpb :: inst_brkpb_pb_p_p_p +emit_brkpb :: emit_brkpb_pb_p_p_p +inst_brkn :: inst_brkn_pb_p_p_p +emit_brkn :: emit_brkn_pb_p_p_p +inst_rdffr :: inst_rdffr_pb +emit_rdffr :: emit_rdffr_pb inst_wrffr :: inst_wrffr_p emit_wrffr :: emit_wrffr_p inst_setffr :: inst_setffr_none emit_setffr :: emit_setffr_none -inst_cmpeq :: inst_cmpeq_p_p_z_z -emit_cmpeq :: emit_cmpeq_p_p_z_z -inst_cmpne :: inst_cmpne_p_p_z_z -emit_cmpne :: emit_cmpne_p_p_z_z -inst_cmpge :: inst_cmpge_p_p_z_z -emit_cmpge :: emit_cmpge_p_p_z_z -inst_cmpgt :: inst_cmpgt_p_p_z_z -emit_cmpgt :: emit_cmpgt_p_p_z_z -inst_cmple :: inst_cmple_p_p_z_z -emit_cmple :: emit_cmple_p_p_z_z -inst_cmplt :: inst_cmplt_p_p_z_z -emit_cmplt :: emit_cmplt_p_p_z_z -inst_cmphi :: inst_cmphi_p_p_z_z -emit_cmphi :: emit_cmphi_p_p_z_z -inst_cmphs :: inst_cmphs_p_p_z_z -emit_cmphs :: emit_cmphs_p_p_z_z -inst_cmplo :: inst_cmplo_p_p_z_z -emit_cmplo :: emit_cmplo_p_p_z_z -inst_cmpls :: inst_cmpls_p_p_z_z -emit_cmpls :: emit_cmpls_p_p_z_z -inst_fcmne :: inst_fcmne_p_p_z_z -emit_fcmne :: emit_fcmne_p_p_z_z -inst_fcmuo :: inst_fcmuo_p_p_z_z -emit_fcmuo :: emit_fcmuo_p_p_z_z -inst_insr :: inst_insr_z_r -emit_insr :: emit_insr_z_r -inst_cpy :: inst_cpy_z_p_r -emit_cpy :: emit_cpy_z_p_r -inst_compact :: inst_compact_z_p_z -emit_compact :: emit_compact_z_p_z -inst_ld1b :: proc{ inst_ld1b_z_p_m, inst_ld1b_i_p_m } -emit_ld1b :: proc{ emit_ld1b_z_p_m, emit_ld1b_i_p_m } -inst_ld1h :: proc{ inst_ld1h_z_p_m, inst_ld1h_i_p_m } -emit_ld1h :: proc{ emit_ld1h_z_p_m, emit_ld1h_i_p_m } -inst_ld1w :: proc{ inst_ld1w_z_p_m, inst_ld1w_i_p_m } -emit_ld1w :: proc{ emit_ld1w_z_p_m, emit_ld1w_i_p_m } -inst_ld1d :: proc{ inst_ld1d_z_p_m, inst_ld1d_i_p_m } -emit_ld1d :: proc{ emit_ld1d_z_p_m, emit_ld1d_i_p_m } -inst_ld1sb :: inst_ld1sb_z_p_m -emit_ld1sb :: emit_ld1sb_z_p_m -inst_ld1sh :: inst_ld1sh_z_p_m -emit_ld1sh :: emit_ld1sh_z_p_m -inst_ld1sw :: inst_ld1sw_z_p_m -emit_ld1sw :: emit_ld1sw_z_p_m -inst_st1b :: proc{ inst_st1b_z_p_m, inst_st1b_i_p_m } -emit_st1b :: proc{ emit_st1b_z_p_m, emit_st1b_i_p_m } -inst_st1h :: proc{ inst_st1h_z_p_m, inst_st1h_i_p_m } -emit_st1h :: proc{ emit_st1h_z_p_m, emit_st1h_i_p_m } -inst_st1w :: proc{ inst_st1w_z_p_m, inst_st1w_i_p_m } -emit_st1w :: proc{ emit_st1w_z_p_m, emit_st1w_i_p_m } -inst_st1d :: proc{ inst_st1d_z_p_m, inst_st1d_i_p_m } -emit_st1d :: proc{ emit_st1d_z_p_m, emit_st1d_i_p_m } -inst_ldff1b :: inst_ldff1b_z_p_m -emit_ldff1b :: emit_ldff1b_z_p_m -inst_ldff1h :: inst_ldff1h_z_p_m -emit_ldff1h :: emit_ldff1h_z_p_m -inst_ldff1w :: inst_ldff1w_z_p_m -emit_ldff1w :: emit_ldff1w_z_p_m -inst_ldff1d :: inst_ldff1d_z_p_m -emit_ldff1d :: emit_ldff1d_z_p_m +inst_cmpeq :: inst_cmpeq_pb_p_zb_zb +emit_cmpeq :: emit_cmpeq_pb_p_zb_zb +inst_cmpne :: inst_cmpne_pb_p_zb_zb +emit_cmpne :: emit_cmpne_pb_p_zb_zb +inst_cmpge :: inst_cmpge_pb_p_zb_zb +emit_cmpge :: emit_cmpge_pb_p_zb_zb +inst_cmpgt :: inst_cmpgt_pb_p_zb_zb +emit_cmpgt :: emit_cmpgt_pb_p_zb_zb +inst_cmple :: inst_cmple_pb_p_zb_zb +emit_cmple :: emit_cmple_pb_p_zb_zb +inst_cmplt :: inst_cmplt_pb_p_zb_zb +emit_cmplt :: emit_cmplt_pb_p_zb_zb +inst_cmphi :: inst_cmphi_pb_p_zb_zb +emit_cmphi :: emit_cmphi_pb_p_zb_zb +inst_cmphs :: inst_cmphs_pb_p_zb_zb +emit_cmphs :: emit_cmphs_pb_p_zb_zb +inst_cmplo :: inst_cmplo_pb_p_zb_zb +emit_cmplo :: emit_cmplo_pb_p_zb_zb +inst_cmpls :: inst_cmpls_pb_p_zb_zb +emit_cmpls :: emit_cmpls_pb_p_zb_zb +inst_fcmne :: inst_fcmne_ph_p_zh_zh +emit_fcmne :: emit_fcmne_ph_p_zh_zh +inst_fcmuo :: inst_fcmuo_ph_p_zh_zh +emit_fcmuo :: emit_fcmuo_ph_p_zh_zh +inst_insr :: inst_insr_zb_r +emit_insr :: emit_insr_zb_r +inst_cpy :: inst_cpy_zb_p_r +emit_cpy :: emit_cpy_zb_p_r +inst_compact :: inst_compact_zs_p_zs +emit_compact :: emit_compact_zs_p_zs +inst_ld1b :: proc{ inst_ld1b_zb_p_m, inst_ld1b_i_p_m } +emit_ld1b :: proc{ emit_ld1b_zb_p_m, emit_ld1b_i_p_m } +inst_ld1h :: proc{ inst_ld1h_zh_p_m, inst_ld1h_i_p_m } +emit_ld1h :: proc{ emit_ld1h_zh_p_m, emit_ld1h_i_p_m } +inst_ld1w :: proc{ inst_ld1w_zs_p_m, inst_ld1w_i_p_m } +emit_ld1w :: proc{ emit_ld1w_zs_p_m, emit_ld1w_i_p_m } +inst_ld1d :: proc{ inst_ld1d_zd_p_m, inst_ld1d_i_p_m } +emit_ld1d :: proc{ emit_ld1d_zd_p_m, emit_ld1d_i_p_m } +inst_ld1sb :: inst_ld1sb_zh_p_m +emit_ld1sb :: emit_ld1sb_zh_p_m +inst_ld1sh :: inst_ld1sh_zs_p_m +emit_ld1sh :: emit_ld1sh_zs_p_m +inst_ld1sw :: inst_ld1sw_zd_p_m +emit_ld1sw :: emit_ld1sw_zd_p_m +inst_st1b :: proc{ inst_st1b_zb_p_m, inst_st1b_i_p_m } +emit_st1b :: proc{ emit_st1b_zb_p_m, emit_st1b_i_p_m } +inst_st1h :: proc{ inst_st1h_zh_p_m, inst_st1h_i_p_m } +emit_st1h :: proc{ emit_st1h_zh_p_m, emit_st1h_i_p_m } +inst_st1w :: proc{ inst_st1w_zs_p_m, inst_st1w_i_p_m } +emit_st1w :: proc{ emit_st1w_zs_p_m, emit_st1w_i_p_m } +inst_st1d :: proc{ inst_st1d_zd_p_m, inst_st1d_i_p_m } +emit_st1d :: proc{ emit_st1d_zd_p_m, emit_st1d_i_p_m } +inst_ldff1b :: inst_ldff1b_zb_p_m +emit_ldff1b :: emit_ldff1b_zb_p_m +inst_ldff1h :: inst_ldff1h_zh_p_m +emit_ldff1h :: emit_ldff1h_zh_p_m +inst_ldff1w :: inst_ldff1w_zs_p_m +emit_ldff1w :: emit_ldff1w_zs_p_m +inst_ldff1d :: inst_ldff1d_zd_p_m +emit_ldff1d :: emit_ldff1d_zd_p_m inst_whilege :: inst_whilege_p_r_r emit_whilege :: emit_whilege_p_r_r inst_whilegt :: inst_whilegt_p_r_r @@ -4952,66 +5540,66 @@ inst_whilelo :: inst_whilelo_p_r_r emit_whilelo :: emit_whilelo_p_r_r inst_whilels :: inst_whilels_p_r_r emit_whilels :: emit_whilels_p_r_r -inst_sqrdmlah :: inst_sqrdmlah_z_z_z -emit_sqrdmlah :: emit_sqrdmlah_z_z_z -inst_sqrdmlsh :: inst_sqrdmlsh_z_z_z -emit_sqrdmlsh :: emit_sqrdmlsh_z_z_z -inst_adclb :: inst_adclb_z_z_z -emit_adclb :: emit_adclb_z_z_z -inst_adclt :: inst_adclt_z_z_z -emit_adclt :: emit_adclt_z_z_z -inst_sbclb :: inst_sbclb_z_z_z -emit_sbclb :: emit_sbclb_z_z_z -inst_sbclt :: inst_sbclt_z_z_z -emit_sbclt :: emit_sbclt_z_z_z -inst_tbl2 :: inst_tbl2_z_z_z -emit_tbl2 :: emit_tbl2_z_z_z -inst_match :: inst_match_p_p_z_z -emit_match :: emit_match_p_p_z_z -inst_nmatch :: inst_nmatch_p_p_z_z -emit_nmatch :: emit_nmatch_p_p_z_z -inst_histcnt :: inst_histcnt_z_p_z_z -emit_histcnt :: emit_histcnt_z_p_z_z -inst_histseg :: inst_histseg_z_z_z -emit_histseg :: emit_histseg_z_z_z +inst_sqrdmlah :: inst_sqrdmlah_zb_zb_zb +emit_sqrdmlah :: emit_sqrdmlah_zb_zb_zb +inst_sqrdmlsh :: inst_sqrdmlsh_zb_zb_zb +emit_sqrdmlsh :: emit_sqrdmlsh_zb_zb_zb +inst_adclb :: inst_adclb_zs_zs_zs +emit_adclb :: emit_adclb_zs_zs_zs +inst_adclt :: inst_adclt_zs_zs_zs +emit_adclt :: emit_adclt_zs_zs_zs +inst_sbclb :: inst_sbclb_zs_zs_zs +emit_sbclb :: emit_sbclb_zs_zs_zs +inst_sbclt :: inst_sbclt_zs_zs_zs +emit_sbclt :: emit_sbclt_zs_zs_zs +inst_tbl2 :: inst_tbl2_zb_zb_zb +emit_tbl2 :: emit_tbl2_zb_zb_zb +inst_match :: inst_match_pb_p_zb_zb +emit_match :: emit_match_pb_p_zb_zb +inst_nmatch :: inst_nmatch_pb_p_zb_zb +emit_nmatch :: emit_nmatch_pb_p_zb_zb +inst_histcnt :: inst_histcnt_zs_p_zs_zs +emit_histcnt :: emit_histcnt_zs_p_zs_zs +inst_histseg :: inst_histseg_zb_zb_zb +emit_histseg :: emit_histseg_zb_zb_zb inst_smstart :: inst_smstart_none emit_smstart :: emit_smstart_none inst_smstop :: inst_smstop_none emit_smstop :: emit_smstop_none inst_rdsvl :: inst_rdsvl_r_i emit_rdsvl :: emit_rdsvl_r_i -inst_addha :: inst_addha_i_p_p_z -emit_addha :: emit_addha_i_p_p_z -inst_addva :: inst_addva_i_p_p_z -emit_addva :: emit_addva_i_p_p_z +inst_addha :: inst_addha_i_p_p_zs +emit_addha :: emit_addha_i_p_p_zs +inst_addva :: inst_addva_i_p_p_zs +emit_addva :: emit_addva_i_p_p_zs inst_zero :: inst_zero_i emit_zero :: emit_zero_i -inst_fmopa :: inst_fmopa_i_p_p_z -emit_fmopa :: emit_fmopa_i_p_p_z -inst_fmops :: inst_fmops_i_p_p_z -emit_fmops :: emit_fmops_i_p_p_z -inst_bfmopa :: inst_bfmopa_i_p_p_z -emit_bfmopa :: emit_bfmopa_i_p_p_z -inst_bfmops :: inst_bfmops_i_p_p_z -emit_bfmops :: emit_bfmops_i_p_p_z -inst_smopa :: inst_smopa_i_p_p_z -emit_smopa :: emit_smopa_i_p_p_z -inst_smops :: inst_smops_i_p_p_z -emit_smops :: emit_smops_i_p_p_z -inst_umopa :: inst_umopa_i_p_p_z -emit_umopa :: emit_umopa_i_p_p_z -inst_umops :: inst_umops_i_p_p_z -emit_umops :: emit_umops_i_p_p_z -inst_usmopa :: inst_usmopa_i_p_p_z -emit_usmopa :: emit_usmopa_i_p_p_z -inst_sumopa :: inst_sumopa_i_p_p_z -emit_sumopa :: emit_sumopa_i_p_p_z +inst_fmopa :: inst_fmopa_i_p_p_zs +emit_fmopa :: emit_fmopa_i_p_p_zs +inst_fmops :: inst_fmops_i_p_p_zs +emit_fmops :: emit_fmops_i_p_p_zs +inst_bfmopa :: inst_bfmopa_i_p_p_zh +emit_bfmopa :: emit_bfmopa_i_p_p_zh +inst_bfmops :: inst_bfmops_i_p_p_zh +emit_bfmops :: emit_bfmops_i_p_p_zh +inst_smopa :: inst_smopa_i_p_p_zb +emit_smopa :: emit_smopa_i_p_p_zb +inst_smops :: inst_smops_i_p_p_zb +emit_smops :: emit_smops_i_p_p_zb +inst_umopa :: inst_umopa_i_p_p_zb +emit_umopa :: emit_umopa_i_p_p_zb +inst_umops :: inst_umops_i_p_p_zb +emit_umops :: emit_umops_i_p_p_zb +inst_usmopa :: inst_usmopa_i_p_p_zb +emit_usmopa :: emit_usmopa_i_p_p_zb +inst_sumopa :: inst_sumopa_i_p_p_zb +emit_sumopa :: emit_sumopa_i_p_p_zb inst_ld1q :: inst_ld1q_i_p_m emit_ld1q :: emit_ld1q_i_p_m inst_st1q :: inst_st1q_i_p_m emit_st1q :: emit_st1q_i_p_m -inst_mova :: proc{ inst_mova_z_p_i, inst_mova_i_p_z } -emit_mova :: proc{ emit_mova_z_p_i, emit_mova_i_p_z } +inst_mova :: proc{ inst_mova_zb_p_i, inst_mova_i_p_zb } +emit_mova :: proc{ emit_mova_zb_p_i, emit_mova_i_p_zb } inst_fcmla :: inst_fcmla_v4h_v4h_v4h_i emit_fcmla :: emit_fcmla_v4h_v4h_v4h_i inst_fcadd :: inst_fcadd_v4h_v4h_v4h_i @@ -5024,40 +5612,40 @@ inst_prfw :: inst_prfw_i_p_m emit_prfw :: emit_prfw_i_p_m inst_prfd :: inst_prfd_i_p_m emit_prfd :: emit_prfd_i_p_m -inst_ldnt1b :: inst_ldnt1b_z_p_m -emit_ldnt1b :: emit_ldnt1b_z_p_m -inst_ldnt1h :: inst_ldnt1h_z_p_m -emit_ldnt1h :: emit_ldnt1h_z_p_m -inst_ldnt1w :: inst_ldnt1w_z_p_m -emit_ldnt1w :: emit_ldnt1w_z_p_m -inst_ldnt1d :: inst_ldnt1d_z_p_m -emit_ldnt1d :: emit_ldnt1d_z_p_m -inst_stnt1b :: inst_stnt1b_z_p_m -emit_stnt1b :: emit_stnt1b_z_p_m -inst_stnt1h :: inst_stnt1h_z_p_m -emit_stnt1h :: emit_stnt1h_z_p_m -inst_stnt1w :: inst_stnt1w_z_p_m -emit_stnt1w :: emit_stnt1w_z_p_m -inst_stnt1d :: inst_stnt1d_z_p_m -emit_stnt1d :: emit_stnt1d_z_p_m -inst_splice :: inst_splice_z_p_z_z -emit_splice :: emit_splice_z_p_z_z -inst_index :: proc{ inst_index_z_i_i, inst_index_z_i_r, inst_index_z_r_i, inst_index_z_r_r } -emit_index :: proc{ emit_index_z_i_i, emit_index_z_i_r, emit_index_z_r_i, emit_index_z_r_r } -inst_bsl1n :: inst_bsl1n_z_z_z_z -emit_bsl1n :: emit_bsl1n_z_z_z_z -inst_bsl2n :: inst_bsl2n_z_z_z_z -emit_bsl2n :: emit_bsl2n_z_z_z_z -inst_nbsl :: inst_nbsl_z_z_z_z -emit_nbsl :: emit_nbsl_z_z_z_z -inst_pmul :: inst_pmul_z_z_z -emit_pmul :: emit_pmul_z_z_z -inst_pmullb :: inst_pmullb_z_z_z -emit_pmullb :: emit_pmullb_z_z_z -inst_pmullt :: inst_pmullt_z_z_z -emit_pmullt :: emit_pmullt_z_z_z -inst_bfcvtnt :: inst_bfcvtnt_z_p_z -emit_bfcvtnt :: emit_bfcvtnt_z_p_z +inst_ldnt1b :: inst_ldnt1b_zb_p_m +emit_ldnt1b :: emit_ldnt1b_zb_p_m +inst_ldnt1h :: inst_ldnt1h_zh_p_m +emit_ldnt1h :: emit_ldnt1h_zh_p_m +inst_ldnt1w :: inst_ldnt1w_zs_p_m +emit_ldnt1w :: emit_ldnt1w_zs_p_m +inst_ldnt1d :: inst_ldnt1d_zd_p_m +emit_ldnt1d :: emit_ldnt1d_zd_p_m +inst_stnt1b :: inst_stnt1b_zb_p_m +emit_stnt1b :: emit_stnt1b_zb_p_m +inst_stnt1h :: inst_stnt1h_zh_p_m +emit_stnt1h :: emit_stnt1h_zh_p_m +inst_stnt1w :: inst_stnt1w_zs_p_m +emit_stnt1w :: emit_stnt1w_zs_p_m +inst_stnt1d :: inst_stnt1d_zd_p_m +emit_stnt1d :: emit_stnt1d_zd_p_m +inst_splice :: inst_splice_zb_p_zb_zb +emit_splice :: emit_splice_zb_p_zb_zb +inst_index :: proc{ inst_index_zb_i_i, inst_index_zb_i_r, inst_index_zb_r_i, inst_index_zb_r_r } +emit_index :: proc{ emit_index_zb_i_i, emit_index_zb_i_r, emit_index_zb_r_i, emit_index_zb_r_r } +inst_bsl1n :: inst_bsl1n_zd_zd_zd_zd +emit_bsl1n :: emit_bsl1n_zd_zd_zd_zd +inst_bsl2n :: inst_bsl2n_zd_zd_zd_zd +emit_bsl2n :: emit_bsl2n_zd_zd_zd_zd +inst_nbsl :: inst_nbsl_zd_zd_zd_zd +emit_nbsl :: emit_nbsl_zd_zd_zd_zd +inst_pmul :: inst_pmul_zb_zb_zb +emit_pmul :: emit_pmul_zb_zb_zb +inst_pmullb :: inst_pmullb_zd_zs_zs +emit_pmullb :: emit_pmullb_zd_zs_zs +inst_pmullt :: inst_pmullt_zd_zs_zs +emit_pmullt :: emit_pmullt_zd_zs_zs +inst_bfcvtnt :: inst_bfcvtnt_zh_p_zs +emit_bfcvtnt :: emit_bfcvtnt_zh_p_zs inst_ldraa :: inst_ldraa_r_m emit_ldraa :: emit_ldraa_r_m inst_ldrab :: inst_ldrab_r_m @@ -5148,16 +5736,16 @@ inst_ldapursh :: inst_ldapursh_r_m emit_ldapursh :: emit_ldapursh_r_m inst_ldapursw :: inst_ldapursw_r_m emit_ldapursw :: emit_ldapursw_r_m -inst_bfadd :: proc{ inst_bfadd_z_p_z_z, inst_bfadd_z_z_z } -emit_bfadd :: proc{ emit_bfadd_z_p_z_z, emit_bfadd_z_z_z } -inst_bfsub :: proc{ inst_bfsub_z_p_z_z, inst_bfsub_z_z_z } -emit_bfsub :: proc{ emit_bfsub_z_p_z_z, emit_bfsub_z_z_z } -inst_bfmul :: proc{ inst_bfmul_z_p_z_z, inst_bfmul_z_z_z } -emit_bfmul :: proc{ emit_bfmul_z_p_z_z, emit_bfmul_z_z_z } -inst_bfmla :: inst_bfmla_z_p_z_z -emit_bfmla :: emit_bfmla_z_p_z_z -inst_bfmls :: inst_bfmls_z_p_z_z -emit_bfmls :: emit_bfmls_z_p_z_z +inst_bfadd :: proc{ inst_bfadd_zh_p_zh_zh, inst_bfadd_zh_zh_zh } +emit_bfadd :: proc{ emit_bfadd_zh_p_zh_zh, emit_bfadd_zh_zh_zh } +inst_bfsub :: proc{ inst_bfsub_zh_p_zh_zh, inst_bfsub_zh_zh_zh } +emit_bfsub :: proc{ emit_bfsub_zh_p_zh_zh, emit_bfsub_zh_zh_zh } +inst_bfmul :: proc{ inst_bfmul_zh_p_zh_zh, inst_bfmul_zh_zh_zh } +emit_bfmul :: proc{ emit_bfmul_zh_p_zh_zh, emit_bfmul_zh_zh_zh } +inst_bfmla :: inst_bfmla_zh_p_zh_zh +emit_bfmla :: emit_bfmla_zh_p_zh_zh +inst_bfmls :: inst_bfmls_zh_p_zh_zh +emit_bfmls :: emit_bfmls_zh_p_zh_zh inst_sb :: inst_sb_none emit_sb :: emit_sb_none inst_csdb :: inst_csdb_none @@ -5174,20 +5762,20 @@ inst_bti_c :: inst_bti_c_none emit_bti_c :: emit_bti_c_none inst_bti_jc :: inst_bti_jc_none emit_bti_jc :: emit_bti_jc_none -inst_bfclamp :: inst_bfclamp_z_z_z -emit_bfclamp :: emit_bfclamp_z_z_z -inst_bfmaxnm :: inst_bfmaxnm_z_p_z_z -emit_bfmaxnm :: emit_bfmaxnm_z_p_z_z -inst_bfminnm :: inst_bfminnm_z_p_z_z -emit_bfminnm :: emit_bfminnm_z_p_z_z -inst_luti2 :: inst_luti2_z_z_z_i -emit_luti2 :: emit_luti2_z_z_z_i -inst_luti4 :: inst_luti4_z_z_z_i -emit_luti4 :: emit_luti4_z_z_z_i -inst_zip :: proc{ inst_zip_z_z_z, inst_zip_z_z } -emit_zip :: proc{ emit_zip_z_z_z, emit_zip_z_z } -inst_uzp :: proc{ inst_uzp_z_z_z, inst_uzp_z_z } -emit_uzp :: proc{ emit_uzp_z_z_z, emit_uzp_z_z } +inst_bfclamp :: inst_bfclamp_zh_zh_zh +emit_bfclamp :: emit_bfclamp_zh_zh_zh +inst_bfmaxnm :: inst_bfmaxnm_zh_p_zh_zh +emit_bfmaxnm :: emit_bfmaxnm_zh_p_zh_zh +inst_bfminnm :: inst_bfminnm_zh_p_zh_zh +emit_bfminnm :: emit_bfminnm_zh_p_zh_zh +inst_luti2 :: inst_luti2_zpb_zpb_zb_i +emit_luti2 :: emit_luti2_zpb_zpb_zb_i +inst_luti4 :: inst_luti4_zpb_zpb_zb_i +emit_luti4 :: emit_luti4_zpb_zpb_zb_i +inst_zip :: proc{ inst_zip_zpb_zb_zb, inst_zip_zqb_zqb } +emit_zip :: proc{ emit_zip_zpb_zb_zb, emit_zip_zqb_zqb } +inst_uzp :: proc{ inst_uzp_zpb_zb_zb, inst_uzp_zqb_zqb } +emit_uzp :: proc{ emit_uzp_zpb_zb_zb, emit_uzp_zqb_zqb } inst_tlbi_rpalos :: inst_tlbi_rpalos_r emit_tlbi_rpalos :: emit_tlbi_rpalos_r inst_tlbi_rpaos :: inst_tlbi_rpaos_r diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index f7538d093..681ec4c4b 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -196,6 +196,47 @@ op_z_d :: #force_inline proc "contextless" (n: u8) -> Operand { return Operand{reg = Register(REG_Z | u16(n & 0x1F)), kind = .REGISTER, size = 8} } +// SVE packs an element size and a shift amount into one field, `tszh:tszl:imm3`, +// as `V = 2*esize - shift`. Because the shift is in [1, esize], V lands in +// [esize, 2*esize), so the four element sizes occupy disjoint ranges and the +// position of the highest set bit names the size: +// +// .b V in [ 8, 15] .s V in [32, 63] +// .h V in [16, 31] .d V in [64, 127] +// +// Encoder and decoder both need this, and it is written once here so the two +// cannot drift apart. + +// The element width, in bits, that a packed tsz value names. +@(require_results) +sve_tsz_esize :: #force_inline proc "contextless" (v: u32) -> u32 { + switch { + case v >= 64: return 64 + case v >= 32: return 32 + case v >= 16: return 16 + } + return 8 +} + +// The shift amount a packed tsz value names. +@(require_results) +sve_tsz_shift :: #force_inline proc "contextless" (v: u32) -> u32 { + return 2 * sve_tsz_esize(v) - v +} + +// The packed tsz value for an element width and shift. +@(require_results) +sve_tsz_pack :: #force_inline proc "contextless" (esize, shift: u32) -> u32 { + return (2 * esize - shift) & 0x7F +} + +// The SVE element-width code (the `size` an operand carries) for a width in +// bits: .b = 1, .h = 2, .s = 4, .d = 8. +@(require_results) +sve_esize_code :: #force_inline proc "contextless" (esize: u32) -> u8 { + return u8(esize / 8) +} + // A predicate register's governing qualifier, carried in Operand.size and read // only when the register's class is REG_P. SVE writes it as a suffix -- `p0/z` // zeroes the inactive lanes, `p0/m` leaves them alone -- and an assembler will @@ -204,6 +245,14 @@ PQUAL_ZERO :: u8(1) PQUAL_MERGE :: u8(2) PQUAL_NONE :: u8(4) +// A predicate that is an instruction's DESTINATION is written with an element +// size instead -- `cmpge p0.b, p1/z, ...` -- so those codes have to live apart +// from the qualifiers above, and apart from the neutral 4 a plain op_reg gives. +PSHAPE_B :: u8(20) +PSHAPE_H :: u8(21) +PSHAPE_S :: u8(22) +PSHAPE_D :: u8(23) + // Arrangement codes carried in Operand.size. Element views are odd and // arrangements are multiples of 8, so the two can never be confused; 4 is the // neutral "no vector shape" value every scalar class uses. @@ -222,6 +271,12 @@ VSHAPE_ELEM_H :: u8(3) VSHAPE_ELEM_S :: u8(5) VSHAPE_ELEM_D :: u8(7) +// SVE element-width codes carried in Operand.size for a Z register. +ZSHAPE_B :: u8(1) +ZSHAPE_H :: u8(2) +ZSHAPE_S :: u8(4) +ZSHAPE_D :: u8(8) + // ----------------------------------------------------------------------------- // NEON V-register arrangement builders. These take the register the caller // actually has, not its number: rebuilding one from `reg_hw` would relabel an diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 26ec37a0d..e207b8b9a 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -426,10 +426,13 @@ write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercas // A predicate's suffix is its governing qualifier, and it hangs off a // slash rather than a dot. case REG_P, REG_PN: - sep = '/' switch size { - case PQUAL_ZERO: shape = "z" - case PQUAL_MERGE: shape = "m" + case PQUAL_ZERO: sep = '/'; shape = "z" + case PQUAL_MERGE: sep = '/'; shape = "m" + case PSHAPE_B: shape = "b" + case PSHAPE_H: shape = "h" + case PSHAPE_S: shape = "s" + case PSHAPE_D: shape = "d" } } if shape == "" { diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index 47457c785..74ea5654e 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -51,6 +51,10 @@ Entry :: struct { feature: lib.Feature, flags: lib.Encoding_Flags, op0: u8, // bits[28:25] + // Table order, so the sort is a total one. Without it, entries that tie on + // every other key come out in whatever order the sort leaves -- and which + // of them decode picks would vary between builds. + seq: u32, } Range :: struct { start: u16, count: u16 } @@ -206,7 +210,7 @@ emit_decode_tables :: proc() -> (total: int) { // Enumerate every 4-bit bucket B such that (B & op0_mask) == op0_static. for b: u8 = 0; b < 16; b += 1 { if (b & op0_mask) != op0_static { continue } - append(&all, Entry{e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags, b}) + append(&all, Entry{e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.flags, b, u32(len(all))}) } } } @@ -214,7 +218,8 @@ emit_decode_tables :: proc() -> (total: int) { if a.op0 != b.op0 { return a.op0 < b.op0 } ac := bits.count_ones(a.mask); bc := bits.count_ones(b.mask) if ac != bc { return ac > bc } - return u16(a.mnemonic) < u16(b.mnemonic) + if a.mnemonic != b.mnemonic { return u16(a.mnemonic) < u16(b.mnemonic) } + return a.seq < b.seq }) op0_idx: [16]Range diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 264329b69..8b67892b4 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2510]lib.Decode_Entry{ +DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -44,12 +44,12 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LUTI4, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, @@ -62,8 +62,8 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, @@ -87,201 +87,201 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, - { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, - { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, - { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, - { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, 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explicit_count=3} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04080000, 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{.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -289,106 +289,106 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -401,11 +401,11 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, @@ -414,136 +414,133 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, @@ -587,15 +584,15 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -604,16 +601,16 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, - { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, @@ -622,12 +619,12 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, @@ -638,88 +635,88 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, - { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -732,15 +729,15 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, @@ -770,142 +767,142 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, @@ -914,192 +911,192 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { 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{.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, @@ -1108,31 +1105,31 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, @@ -1159,46 +1156,46 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, @@ -1219,58 +1216,58 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, @@ -1289,393 +1286,393 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, 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{.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1683,56 +1680,56 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -1753,54 +1750,54 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, @@ -1819,14 +1816,14 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, @@ -1836,18 +1833,18 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -1858,28 +1855,28 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -2039,112 +2036,112 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRL, 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{.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, @@ -2181,12 +2178,12 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2199,8 +2196,8 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, @@ -2212,22 +2209,22 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -2243,22 +2240,22 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, - { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, - { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, @@ -2274,52 +2271,52 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, - { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, - { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, @@ -2327,173 +2324,173 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, - { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, 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{.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, @@ -2504,38 +2501,38 @@ DECODE_ENTRIES := [2510]lib.Decode_Entry{ { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, } @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 77}, - 0x02 = { 77, 508}, - 0x04 = { 585, 76}, - 0x05 = { 661, 50}, - 0x06 = { 711, 56}, - 0x07 = { 767, 1058}, - 0x08 = {1825, 16}, - 0x09 = {1841, 34}, - 0x0A = {1875, 130}, - 0x0B = {2005, 21}, - 0x0C = {2026, 167}, - 0x0D = {2193, 122}, - 0x0E = {2315, 19}, - 0x0F = {2334, 176}, + 0x02 = { 77, 505}, + 0x04 = { 582, 76}, + 0x05 = { 658, 50}, + 0x06 = { 708, 56}, + 0x07 = { 764, 1058}, + 0x08 = {1822, 16}, + 0x09 = {1838, 34}, + 0x0A = {1872, 130}, + 0x0B = {2002, 21}, + 0x0C = {2023, 167}, + 0x0D = {2190, 122}, + 0x0E = {2312, 19}, + 0x0F = {2331, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 91152d575..fd5dbe68b 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2508]lib.Encoding{ +ENCODE_FORMS := [2505]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -87,13 +87,13 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -104,7 +104,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -115,7 +115,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -124,16 +124,16 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -243,7 +243,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -385,7 +385,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -402,7 +402,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -1336,10 +1336,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .XAR { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, // .SM3PARTW1 { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3PARTW2 @@ -2045,45 +2042,45 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGE { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGT { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMLE { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FCMLT { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FACGE { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2426,8 +2423,8 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .MOV, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, @@ -2460,7 +2457,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2473,7 +2470,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2486,7 +2483,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2499,7 +2496,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2512,7 +2509,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2525,11 +2522,11 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -2666,111 +2663,111 @@ ENCODE_FORMS := [2508]lib.Encoding{ { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE - { .PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES - { .PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, // .PFALSE - { .PFALSE, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR - { .RDFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPNE - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGE - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGT - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLE - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLT - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHI - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHS - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLO - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLS - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .FCMNE - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMUO - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .INSR { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -2898,11 +2895,11 @@ ENCODE_FORMS := [2508]lib.Encoding{ // .TBL2 { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .MATCH - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .NMATCH - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .HISTCNT { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, @@ -3340,7 +3337,7 @@ ENCODE_FORMS := [2508]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2508]lib.Clobber{ +CLOBBER_FORMS := [2505]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -4669,9 +4666,6 @@ CLOBBER_FORMS := [2508]lib.Clobber{ // .XAR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}}, // .SM3PARTW1 {written={0}, read={0, 1, 2}}, // .SM3PARTW2 @@ -6992,506 +6986,506 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .EOR3 = { 1002, 2}, .BCAX = { 1004, 2}, .RAX1 = { 1006, 1}, - .XAR = { 1007, 5}, - .SM3PARTW1 = { 1012, 1}, - .SM3PARTW2 = { 1013, 1}, - .SM3SS1 = { 1014, 1}, - .SM3TT1A = { 1015, 1}, - .SM3TT1B = { 1016, 1}, - .SM3TT2A = { 1017, 1}, - .SM3TT2B = { 1018, 1}, - .SM4E = { 1019, 1}, - .SM4EKEY = { 1020, 1}, - .PMULL = { 1021, 2}, - .PMULL2 = { 1023, 2}, - .BFCVT = { 1025, 2}, - .BFDOT = { 1027, 1}, - .BFMMLA = { 1028, 1}, - .BFMLALB = { 1029, 1}, - .BFMLALT = { 1030, 1}, - .BFCVTN = { 1031, 1}, - .BFCVTN2 = { 1032, 1}, - .MUL = { 1033, 7}, - .MLA = { 1040, 6}, - .MLS = { 1046, 6}, - .NEG = { 1052, 13}, - .ABS = { 1065, 11}, - .SHADD = { 1076, 6}, - .UHADD = { 1082, 6}, - .SHSUB = { 1088, 6}, - .UHSUB = { 1094, 6}, - .SRHADD = { 1100, 6}, - .URHADD = { 1106, 6}, - .SQADD = { 1112, 11}, - .UQADD = { 1123, 11}, - .SQSUB = { 1134, 11}, - .UQSUB = { 1145, 11}, - .SMAX = { 1156, 10}, - .UMAX = { 1166, 10}, - .SMIN = { 1176, 10}, - .UMIN = { 1186, 10}, - .SABD = { 1196, 10}, - .UABD = { 1206, 10}, - .SABA = { 1216, 6}, - .UABA = { 1222, 6}, - .ADDP = { 1228, 7}, - .ADDV = { 1235, 5}, - .SADDLP = { 1240, 6}, - .UADDLP = { 1246, 6}, - .SADALP = { 1252, 6}, - .UADALP = { 1258, 6}, - .SADDLV = { 1264, 5}, - .UADDLV = { 1269, 5}, - .SMAXV = { 1274, 5}, - .UMAXV = { 1279, 5}, - .SMINV = { 1284, 5}, - .UMINV = { 1289, 5}, - .SMAXP = { 1294, 6}, - .UMAXP = { 1300, 6}, - .SMINP = { 1306, 6}, - .UMINP = { 1312, 6}, - .SADDL = { 1318, 3}, - .SADDL2 = { 1321, 3}, - .UADDL = { 1324, 3}, - .UADDL2 = { 1327, 3}, - .SSUBL = { 1330, 3}, - .SSUBL2 = { 1333, 3}, - .USUBL = { 1336, 3}, - .USUBL2 = { 1339, 3}, - .SADDW = { 1342, 3}, - .SADDW2 = { 1345, 3}, - .UADDW = { 1348, 3}, - .UADDW2 = { 1351, 3}, - .SSUBW = { 1354, 3}, - .SSUBW2 = { 1357, 3}, - .USUBW = { 1360, 3}, - .USUBW2 = { 1363, 3}, - .RADDHN = { 1366, 3}, - .RADDHN2 = { 1369, 3}, - .RSUBHN = { 1372, 3}, - .RSUBHN2 = { 1375, 3}, - .ADDHN = { 1378, 3}, - .ADDHN2 = { 1381, 3}, - .SUBHN = { 1384, 3}, - .SUBHN2 = { 1387, 3}, - .XTN = { 1390, 3}, - .XTN2 = { 1393, 3}, - .SQXTN = { 1396, 3}, - .SQXTN2 = { 1399, 3}, - .UQXTN = { 1402, 3}, - .UQXTN2 = { 1405, 3}, - .SQXTUN = { 1408, 3}, - .SQXTUN2 = { 1411, 3}, - .SMULL = { 1414, 3}, - .SMULL2 = { 1417, 3}, - .UMULL = { 1420, 3}, - .UMULL2 = { 1423, 3}, - .SMLAL = { 1426, 3}, - .SMLAL2 = { 1429, 3}, - .UMLAL = { 1432, 3}, - .UMLAL2 = { 1435, 3}, - .SMLSL = { 1438, 3}, - .SMLSL2 = { 1441, 3}, - .UMLSL = { 1444, 3}, - .UMLSL2 = { 1447, 3}, - .SQDMULL = { 1450, 2}, - .SQDMULL2 = { 1452, 2}, - .SQDMLAL = { 1454, 2}, - .SQDMLAL2 = { 1456, 2}, - .SQDMLSL = { 1458, 2}, - .SQDMLSL2 = { 1460, 2}, - .SQDMULH = { 1462, 4}, - .SQRDMULH = { 1466, 4}, - .SDOT = { 1470, 2}, - .UDOT = { 1472, 2}, - .USDOT = { 1474, 2}, - .FMLA = { 1476, 8}, - .FMLS = { 1484, 8}, - .FMULX = { 1492, 5}, - .FMAXP = { 1497, 5}, - .FMINP = { 1502, 5}, - .FMAXNMP = { 1507, 5}, - .FMINNMP = { 1512, 5}, - .FMAXV = { 1517, 3}, - .FMINV = { 1520, 3}, - .FMAXNMV = { 1523, 3}, - .FMINNMV = { 1526, 3}, - .FRECPE = { 1529, 5}, - .FRSQRTE = { 1534, 5}, - .FRECPS = { 1539, 8}, - .FRSQRTS = { 1547, 8}, - .FRECPX = { 1555, 6}, - .FADDP = { 1561, 5}, - .FCVTL = { 1566, 2}, - .FCVTL2 = { 1568, 2}, - .FCVTN = { 1570, 2}, - .FCVTN2 = { 1572, 2}, - .FCVTXN = { 1574, 1}, - .FCVTXN2 = { 1575, 1}, - .FCMEQ = { 1576, 8}, - .FCMGE = { 1584, 8}, - .FCMGT = { 1592, 8}, - .FCMLE = { 1600, 8}, - .FCMLT = { 1608, 8}, - .FACGE = { 1616, 5}, - .FACGT = { 1621, 5}, - .CMEQ = { 1626, 4}, - .CMGE = { 1630, 7}, - .CMGT = { 1637, 2}, - .CMHI = { 1639, 2}, - .CMHS = { 1641, 7}, - .CMLE = { 1648, 7}, - .CMLT = { 1655, 7}, - .CMTST = { 1662, 7}, - .MVN = { 1669, 4}, - .BIT = { 1673, 1}, - .BIF = { 1674, 1}, - .BSL = { 1675, 2}, - .SHL = { 1677, 7}, - .SQSHL = { 1684, 7}, - .SQSHLU = { 1691, 7}, - .SRSHL = { 1698, 7}, - .URSHL = { 1705, 7}, - .SSHR = { 1712, 7}, - .USHR = { 1719, 7}, - .SSRA = { 1726, 7}, - .USRA = { 1733, 7}, - .SRSHR = { 1740, 7}, - .URSHR = { 1747, 7}, - .SRSRA = { 1754, 7}, - .URSRA = { 1761, 7}, - .SSHL = { 1768, 7}, - .USHL = { 1775, 7}, - .SLI = { 1782, 7}, - .SRI = { 1789, 7}, - .SSHLL = { 1796, 3}, - .SSHLL2 = { 1799, 3}, - .USHLL = { 1802, 3}, - .USHLL2 = { 1805, 3}, - .SXTL = { 1808, 3}, - .SXTL2 = { 1811, 3}, - .UXTL = { 1814, 3}, - .UXTL2 = { 1817, 3}, - .SHRN = { 1820, 3}, - .SHRN2 = { 1823, 3}, - .RSHRN = { 1826, 3}, - .RSHRN2 = { 1829, 3}, - .SQSHRN = { 1832, 3}, - .SQSHRN2 = { 1835, 3}, - .UQSHRN = { 1838, 3}, - .UQSHRN2 = { 1841, 3}, - .SQRSHRN = { 1844, 3}, - .SQRSHRN2 = { 1847, 3}, - .UQRSHRN = { 1850, 3}, - .UQRSHRN2 = { 1853, 3}, - .SQSHRUN = { 1856, 3}, - .SQSHRUN2 = { 1859, 3}, - .SQRSHRUN = { 1862, 3}, - .SQRSHRUN2 = { 1865, 3}, - .DUP = { 1868, 18}, - .INS = { 1886, 8}, - .MOV = { 1894, 12}, - .EXT = { 1906, 4}, - .TBL = { 1910, 6}, - .TBX = { 1916, 3}, - .ZIP1 = { 1919, 12}, - .ZIP2 = { 1931, 12}, - .UZP1 = { 1943, 12}, - .UZP2 = { 1955, 12}, - .TRN1 = { 1967, 12}, - .TRN2 = { 1979, 12}, - .NOT = { 1991, 3}, - .REV64 = { 1994, 6}, - .CNT = { 2000, 6}, - .URECPE = { 2006, 2}, - .URSQRTE = { 2008, 2}, - .MOVI = { 2010, 7}, - .MVNI = { 2017, 4}, - .LD1 = { 2021, 8}, - .LD2 = { 2029, 5}, - .LD3 = { 2034, 5}, - .LD4 = { 2039, 5}, - .ST1 = { 2044, 8}, - .ST2 = { 2052, 5}, - .ST3 = { 2057, 5}, - .ST4 = { 2062, 5}, - .LD1R = { 2067, 1}, - .LD2R = { 2068, 1}, - .LD3R = { 2069, 1}, - .LD4R = { 2070, 1}, - .SUBR = { 2071, 4}, - .ASRR = { 2075, 4}, - .LSLR = { 2079, 4}, - .LSRR = { 2083, 4}, - .FTSMUL = { 2087, 3}, - .FSUBR = { 2090, 3}, - .FDIVR = { 2093, 3}, - .FNMLA = { 2096, 3}, - .FNMLS = { 2099, 3}, - .NAND = { 2102, 1}, - .NOR = { 2103, 1}, - .SEL = { 2104, 1}, - .ORRS = { 2105, 1}, - .EORS = { 2106, 1}, - .NANDS = { 2107, 1}, - .NORS = { 2108, 1}, - .ORNS = { 2109, 1}, - .MOVS = { 2110, 1}, - .PTRUE = { 2111, 1}, - .PTRUES = { 2112, 1}, - .PFALSE = { 2113, 1}, - .PFIRST = { 2114, 1}, - .PNEXT = { 2115, 1}, - .BRKA = { 2116, 1}, - .BRKB = { 2117, 1}, - .BRKAS = { 2118, 1}, - .BRKBS = { 2119, 1}, - .BRKPA = { 2120, 1}, - .BRKPB = { 2121, 1}, - .BRKN = { 2122, 1}, - .RDFFR = { 2123, 1}, - .WRFFR = { 2124, 1}, - .SETFFR = { 2125, 1}, - .CMPEQ = { 2126, 4}, - .CMPNE = { 2130, 4}, - .CMPGE = { 2134, 4}, - .CMPGT = { 2138, 4}, - .CMPLE = { 2142, 4}, - .CMPLT = { 2146, 4}, - .CMPHI = { 2150, 4}, - .CMPHS = { 2154, 4}, - .CMPLO = { 2158, 4}, - .CMPLS = { 2162, 4}, - .FCMNE = { 2166, 3}, - .FCMUO = { 2169, 3}, - .INSR = { 2172, 4}, - .CPY = { 2176, 4}, - .COMPACT = { 2180, 2}, - .LD1B = { 2182, 6}, - .LD1H = { 2188, 6}, - .LD1W = { 2194, 6}, - .LD1D = { 2200, 5}, - .LD1SB = { 2205, 3}, - .LD1SH = { 2208, 3}, - .LD1SW = { 2211, 2}, - .ST1B = { 2213, 6}, - .ST1H = { 2219, 6}, - .ST1W = { 2225, 6}, - .ST1D = { 2231, 5}, - .LDFF1B = { 2236, 1}, - .LDFF1H = { 2237, 1}, - .LDFF1W = { 2238, 1}, - .LDFF1D = { 2239, 1}, - .WHILEGE = { 2240, 1}, - .WHILEGT = { 2241, 1}, - .WHILELE = { 2242, 1}, - .WHILELT = { 2243, 1}, - .WHILEHI = { 2244, 1}, - .WHILEHS = { 2245, 1}, - .WHILELO = { 2246, 1}, - .WHILELS = { 2247, 1}, - .SQRDMLAH = { 2248, 4}, - .SQRDMLSH = { 2252, 4}, - .ADCLB = { 2256, 2}, - .ADCLT = { 2258, 2}, - .SBCLB = { 2260, 2}, - .SBCLT = { 2262, 2}, - .TBL2 = { 2264, 1}, - .MATCH = { 2265, 2}, - .NMATCH = { 2267, 2}, - .HISTCNT = { 2269, 2}, - .HISTSEG = { 2271, 1}, - .SMSTART = { 2272, 1}, - .SMSTOP = { 2273, 1}, - .RDSVL = { 2274, 1}, - .ADDHA = { 2275, 1}, - .ADDVA = { 2276, 1}, - .ZERO = { 2277, 1}, - .FMOPA = { 2278, 1}, - .FMOPS = { 2279, 1}, - .BFMOPA = { 2280, 1}, - .BFMOPS = { 2281, 1}, - .SMOPA = { 2282, 2}, - .SMOPS = { 2284, 2}, - .UMOPA = { 2286, 2}, - .UMOPS = { 2288, 2}, - .USMOPA = { 2290, 1}, - .SUMOPA = { 2291, 1}, - .LD1Q = { 2292, 1}, - .ST1Q = { 2293, 1}, - .MOVA = { 2294, 2}, - .FCMLA = { 2296, 4}, - .FCADD = { 2300, 4}, - .PRFB = { 2304, 1}, - .PRFH = { 2305, 1}, - .PRFW = { 2306, 1}, - .PRFD = { 2307, 1}, - .LDNT1B = { 2308, 1}, - .LDNT1H = { 2309, 1}, - .LDNT1W = { 2310, 1}, - .LDNT1D = { 2311, 1}, - .STNT1B = { 2312, 1}, - .STNT1H = { 2313, 1}, - .STNT1W = { 2314, 1}, - .STNT1D = { 2315, 1}, - .SPLICE = { 2316, 1}, - .INDEX = { 2317, 4}, - .BSL1N = { 2321, 1}, - .BSL2N = { 2322, 1}, - .NBSL = { 2323, 1}, - .PMUL = { 2324, 1}, - .PMULLB = { 2325, 1}, - .PMULLT = { 2326, 1}, - .BFCVTNT = { 2327, 1}, - .LDRAA = { 2328, 2}, - .LDRAB = { 2330, 2}, - .TSTART = { 2332, 1}, - .TCOMMIT = { 2333, 1}, - .TCANCEL = { 2334, 1}, - .TTEST = { 2335, 1}, - .WFET = { 2336, 1}, - .WFIT = { 2337, 1}, - .BC_EQ = { 2338, 1}, - .BC_NE = { 2339, 1}, - .BC_CS = { 2340, 1}, - .BC_CC = { 2341, 1}, - .BC_MI = { 2342, 1}, - .BC_PL = { 2343, 1}, - .BC_VS = { 2344, 1}, - .BC_VC = { 2345, 1}, - .BC_HI = { 2346, 1}, - .BC_LS = { 2347, 1}, - .BC_GE = { 2348, 1}, - .BC_LT = { 2349, 1}, - .BC_GT = { 2350, 1}, - .BC_LE = { 2351, 1}, - .BC_AL = { 2352, 1}, - .BC_NV = { 2353, 1}, - .UXTB = { 2354, 1}, - .UXTH = { 2355, 1}, - .UXTW = { 2356, 1}, - .SXTB = { 2357, 1}, - .SXTH = { 2358, 1}, - .SXTW = { 2359, 1}, - .ADC = { 2360, 2}, - .ADCS = { 2362, 2}, - .SBC = { 2364, 2}, - .SBCS = { 2366, 2}, - .NGC = { 2368, 2}, - .NGCS = { 2370, 2}, - .LDAPUR = { 2372, 2}, - .STLUR = { 2374, 2}, - .LDAPURB = { 2376, 1}, - .STLURB = { 2377, 1}, - .LDAPURH = { 2378, 1}, - .STLURH = { 2379, 1}, - .LDAPURSB = { 2380, 2}, - .LDAPURSH = { 2382, 2}, - .LDAPURSW = { 2384, 1}, - .BFADD = { 2385, 2}, - .BFSUB = { 2387, 2}, - .BFMUL = { 2389, 2}, - .BFMLA = { 2391, 1}, - .BFMLS = { 2392, 1}, - .SB = { 2393, 1}, - .CSDB = { 2394, 1}, - .DGH = { 2395, 1}, - .PSB_CSYNC = { 2396, 1}, - .TSB_CSYNC = { 2397, 1}, - .BTI_J = { 2398, 1}, - .BTI_C = { 2399, 1}, - .BTI_JC = { 2400, 1}, - .BFCLAMP = { 2401, 1}, - .BFMAXNM = { 2402, 1}, - .BFMINNM = { 2403, 1}, - .LUTI2 = { 2404, 1}, - .LUTI4 = { 2405, 1}, - .ZIP = { 2406, 2}, - .UZP = { 2408, 2}, - .TLBI_RPALOS = { 2410, 1}, - .TLBI_RPAOS = { 2411, 1}, - .AT_S1E1A = { 2412, 1}, - .DC_CIPAPA = { 2413, 1}, - .DC_CIGDPAPA = { 2414, 1}, - .TLBI_PAALL = { 2415, 1}, - .TLBI_PAALLOS = { 2416, 1}, - .AMX_LDX = { 2417, 1}, - .AMX_LDY = { 2418, 1}, - .AMX_STX = { 2419, 1}, - .AMX_STY = { 2420, 1}, - .AMX_LDZ = { 2421, 1}, - .AMX_STZ = { 2422, 1}, - .AMX_LDZI = { 2423, 1}, - .AMX_STZI = { 2424, 1}, - .AMX_EXTRX = { 2425, 1}, - .AMX_EXTRY = { 2426, 1}, - .AMX_FMA64 = { 2427, 1}, - .AMX_FMS64 = { 2428, 1}, - .AMX_FMA32 = { 2429, 1}, - .AMX_FMS32 = { 2430, 1}, - .AMX_MAC16 = { 2431, 1}, - .AMX_FMA16 = { 2432, 1}, - .AMX_FMS16 = { 2433, 1}, - .AMX_SET = { 2434, 1}, - .AMX_CLR = { 2435, 1}, - .AMX_VECINT = { 2436, 1}, - .AMX_VECFP = { 2437, 1}, - .AMX_MATINT = { 2438, 1}, - .AMX_MATFP = { 2439, 1}, - .AMX_GENLUT = { 2440, 1}, - .CPYP = { 2441, 1}, - .CPYM = { 2442, 1}, - .CPYE = { 2443, 1}, - .CPYFP = { 2444, 1}, - .CPYFM = { 2445, 1}, - .CPYFE = { 2446, 1}, - .SETP = { 2447, 1}, - .SETM = { 2448, 1}, - .SETE = { 2449, 1}, - .DC_IVAC = { 2450, 1}, - .DC_ISW = { 2451, 1}, - .DC_CSW = { 2452, 1}, - .DC_CISW = { 2453, 1}, - .DC_ZVA = { 2454, 1}, - .DC_CVAC = { 2455, 1}, - .DC_CVAU = { 2456, 1}, - .DC_CIVAC = { 2457, 1}, - .IC_IALLUIS = { 2458, 1}, - .IC_IALLU = { 2459, 1}, - .IC_IVAU = { 2460, 1}, - .AT_S1E1R = { 2461, 1}, - .AT_S1E1W = { 2462, 1}, - .AT_S1E0R = { 2463, 1}, - .AT_S1E0W = { 2464, 1}, - .AT_S1E2R = { 2465, 1}, - .AT_S1E2W = { 2466, 1}, - .AT_S1E3R = { 2467, 1}, - .AT_S1E3W = { 2468, 1}, - .AT_S12E1R = { 2469, 1}, - .AT_S12E1W = { 2470, 1}, - .AT_S12E0R = { 2471, 1}, - .AT_S12E0W = { 2472, 1}, - .TLBI_VMALLE1 = { 2473, 1}, - .TLBI_VMALLE1IS = { 2474, 1}, - .TLBI_VAE1 = { 2475, 1}, - .TLBI_VAE1IS = { 2476, 1}, - .TLBI_ASIDE1 = { 2477, 1}, - .TLBI_ASIDE1IS = { 2478, 1}, - .TLBI_VAAE1 = { 2479, 1}, - .TLBI_VAAE1IS = { 2480, 1}, - .TLBI_VALE1 = { 2481, 1}, - .TLBI_VALE1IS = { 2482, 1}, - .TLBI_VAALE1 = { 2483, 1}, - .TLBI_VAALE1IS = { 2484, 1}, - .TLBI_ALLE1 = { 2485, 1}, - .TLBI_ALLE1IS = { 2486, 1}, - .TLBI_ALLE2 = { 2487, 1}, - .TLBI_ALLE2IS = { 2488, 1}, - .TLBI_ALLE3 = { 2489, 1}, - .TLBI_ALLE3IS = { 2490, 1}, - .PRFM = { 2491, 2}, - .PRFUM = { 2493, 1}, - .NEGS = { 2494, 2}, - .CMP = { 2496, 6}, - .CMN = { 2502, 6}, + .XAR = { 1007, 2}, + .SM3PARTW1 = { 1009, 1}, + .SM3PARTW2 = { 1010, 1}, + .SM3SS1 = { 1011, 1}, + .SM3TT1A = { 1012, 1}, + .SM3TT1B = { 1013, 1}, + .SM3TT2A = { 1014, 1}, + .SM3TT2B = { 1015, 1}, + .SM4E = { 1016, 1}, + .SM4EKEY = { 1017, 1}, + .PMULL = { 1018, 2}, + .PMULL2 = { 1020, 2}, + .BFCVT = { 1022, 2}, + .BFDOT = { 1024, 1}, + .BFMMLA = { 1025, 1}, + .BFMLALB = { 1026, 1}, + .BFMLALT = { 1027, 1}, + .BFCVTN = { 1028, 1}, + .BFCVTN2 = { 1029, 1}, + .MUL = { 1030, 7}, + .MLA = { 1037, 6}, + .MLS = { 1043, 6}, + .NEG = { 1049, 13}, + .ABS = { 1062, 11}, + .SHADD = { 1073, 6}, + .UHADD = { 1079, 6}, + .SHSUB = { 1085, 6}, + .UHSUB = { 1091, 6}, + .SRHADD = { 1097, 6}, + .URHADD = { 1103, 6}, + .SQADD = { 1109, 11}, + .UQADD = { 1120, 11}, + .SQSUB = { 1131, 11}, + .UQSUB = { 1142, 11}, + .SMAX = { 1153, 10}, + .UMAX = { 1163, 10}, + .SMIN = { 1173, 10}, + .UMIN = { 1183, 10}, + .SABD = { 1193, 10}, + .UABD = { 1203, 10}, + .SABA = { 1213, 6}, + .UABA = { 1219, 6}, + .ADDP = { 1225, 7}, + .ADDV = { 1232, 5}, + .SADDLP = { 1237, 6}, + .UADDLP = { 1243, 6}, + .SADALP = { 1249, 6}, + .UADALP = { 1255, 6}, + .SADDLV = { 1261, 5}, + .UADDLV = { 1266, 5}, + .SMAXV = { 1271, 5}, + .UMAXV = { 1276, 5}, + .SMINV = { 1281, 5}, + .UMINV = { 1286, 5}, + .SMAXP = { 1291, 6}, + .UMAXP = { 1297, 6}, + .SMINP = { 1303, 6}, + .UMINP = { 1309, 6}, + .SADDL = { 1315, 3}, + .SADDL2 = { 1318, 3}, + .UADDL = { 1321, 3}, + .UADDL2 = { 1324, 3}, + .SSUBL = { 1327, 3}, + .SSUBL2 = { 1330, 3}, + .USUBL = { 1333, 3}, + .USUBL2 = { 1336, 3}, + .SADDW = { 1339, 3}, + .SADDW2 = { 1342, 3}, + .UADDW = { 1345, 3}, + .UADDW2 = { 1348, 3}, + .SSUBW = { 1351, 3}, + .SSUBW2 = { 1354, 3}, + .USUBW = { 1357, 3}, + .USUBW2 = { 1360, 3}, + .RADDHN = { 1363, 3}, + .RADDHN2 = { 1366, 3}, + .RSUBHN = { 1369, 3}, + .RSUBHN2 = { 1372, 3}, + .ADDHN = { 1375, 3}, + .ADDHN2 = { 1378, 3}, + .SUBHN = { 1381, 3}, + .SUBHN2 = { 1384, 3}, + .XTN = { 1387, 3}, + .XTN2 = { 1390, 3}, + .SQXTN = { 1393, 3}, + .SQXTN2 = { 1396, 3}, + .UQXTN = { 1399, 3}, + .UQXTN2 = { 1402, 3}, + .SQXTUN = { 1405, 3}, + .SQXTUN2 = { 1408, 3}, + .SMULL = { 1411, 3}, + .SMULL2 = { 1414, 3}, + .UMULL = { 1417, 3}, + .UMULL2 = { 1420, 3}, + .SMLAL = { 1423, 3}, + .SMLAL2 = { 1426, 3}, + .UMLAL = { 1429, 3}, + .UMLAL2 = { 1432, 3}, + .SMLSL = { 1435, 3}, + .SMLSL2 = { 1438, 3}, + .UMLSL = { 1441, 3}, + .UMLSL2 = { 1444, 3}, + .SQDMULL = { 1447, 2}, + .SQDMULL2 = { 1449, 2}, + .SQDMLAL = { 1451, 2}, + .SQDMLAL2 = { 1453, 2}, + .SQDMLSL = { 1455, 2}, + .SQDMLSL2 = { 1457, 2}, + .SQDMULH = { 1459, 4}, + .SQRDMULH = { 1463, 4}, + .SDOT = { 1467, 2}, + .UDOT = { 1469, 2}, + .USDOT = { 1471, 2}, + .FMLA = { 1473, 8}, + .FMLS = { 1481, 8}, + .FMULX = { 1489, 5}, + .FMAXP = { 1494, 5}, + .FMINP = { 1499, 5}, + .FMAXNMP = { 1504, 5}, + .FMINNMP = { 1509, 5}, + .FMAXV = { 1514, 3}, + .FMINV = { 1517, 3}, + .FMAXNMV = { 1520, 3}, + .FMINNMV = { 1523, 3}, + .FRECPE = { 1526, 5}, + .FRSQRTE = { 1531, 5}, + .FRECPS = { 1536, 8}, + .FRSQRTS = { 1544, 8}, + .FRECPX = { 1552, 6}, + .FADDP = { 1558, 5}, + .FCVTL = { 1563, 2}, + .FCVTL2 = { 1565, 2}, + .FCVTN = { 1567, 2}, + .FCVTN2 = { 1569, 2}, + .FCVTXN = { 1571, 1}, + .FCVTXN2 = { 1572, 1}, + .FCMEQ = { 1573, 8}, + .FCMGE = { 1581, 8}, + .FCMGT = { 1589, 8}, + .FCMLE = { 1597, 8}, + .FCMLT = { 1605, 8}, + .FACGE = { 1613, 5}, + .FACGT = { 1618, 5}, + .CMEQ = { 1623, 4}, + .CMGE = { 1627, 7}, + .CMGT = { 1634, 2}, + .CMHI = { 1636, 2}, + .CMHS = { 1638, 7}, + .CMLE = { 1645, 7}, + .CMLT = { 1652, 7}, + .CMTST = { 1659, 7}, + .MVN = { 1666, 4}, + .BIT = { 1670, 1}, + .BIF = { 1671, 1}, + .BSL = { 1672, 2}, + .SHL = { 1674, 7}, + .SQSHL = { 1681, 7}, + .SQSHLU = { 1688, 7}, + .SRSHL = { 1695, 7}, + .URSHL = { 1702, 7}, + .SSHR = { 1709, 7}, + .USHR = { 1716, 7}, + .SSRA = { 1723, 7}, + .USRA = { 1730, 7}, + .SRSHR = { 1737, 7}, + .URSHR = { 1744, 7}, + .SRSRA = { 1751, 7}, + .URSRA = { 1758, 7}, + .SSHL = { 1765, 7}, + .USHL = { 1772, 7}, + .SLI = { 1779, 7}, + .SRI = { 1786, 7}, + .SSHLL = { 1793, 3}, + .SSHLL2 = { 1796, 3}, + .USHLL = { 1799, 3}, + .USHLL2 = { 1802, 3}, + .SXTL = { 1805, 3}, + .SXTL2 = { 1808, 3}, + .UXTL = { 1811, 3}, + .UXTL2 = { 1814, 3}, + .SHRN = { 1817, 3}, + .SHRN2 = { 1820, 3}, + .RSHRN = { 1823, 3}, + .RSHRN2 = { 1826, 3}, + .SQSHRN = { 1829, 3}, + .SQSHRN2 = { 1832, 3}, + .UQSHRN = { 1835, 3}, + .UQSHRN2 = { 1838, 3}, + .SQRSHRN = { 1841, 3}, + .SQRSHRN2 = { 1844, 3}, + .UQRSHRN = { 1847, 3}, + .UQRSHRN2 = { 1850, 3}, + .SQSHRUN = { 1853, 3}, + .SQSHRUN2 = { 1856, 3}, + .SQRSHRUN = { 1859, 3}, + .SQRSHRUN2 = { 1862, 3}, + .DUP = { 1865, 18}, + .INS = { 1883, 8}, + .MOV = { 1891, 12}, + .EXT = { 1903, 4}, + .TBL = { 1907, 6}, + .TBX = { 1913, 3}, + .ZIP1 = { 1916, 12}, + .ZIP2 = { 1928, 12}, + .UZP1 = { 1940, 12}, + .UZP2 = { 1952, 12}, + .TRN1 = { 1964, 12}, + .TRN2 = { 1976, 12}, + .NOT = { 1988, 3}, + .REV64 = { 1991, 6}, + .CNT = { 1997, 6}, + .URECPE = { 2003, 2}, + .URSQRTE = { 2005, 2}, + .MOVI = { 2007, 7}, + .MVNI = { 2014, 4}, + .LD1 = { 2018, 8}, + .LD2 = { 2026, 5}, + .LD3 = { 2031, 5}, + .LD4 = { 2036, 5}, + .ST1 = { 2041, 8}, + .ST2 = { 2049, 5}, + .ST3 = { 2054, 5}, + .ST4 = { 2059, 5}, + .LD1R = { 2064, 1}, + .LD2R = { 2065, 1}, + .LD3R = { 2066, 1}, + .LD4R = { 2067, 1}, + .SUBR = { 2068, 4}, + .ASRR = { 2072, 4}, + .LSLR = { 2076, 4}, + .LSRR = { 2080, 4}, + .FTSMUL = { 2084, 3}, + .FSUBR = { 2087, 3}, + .FDIVR = { 2090, 3}, + .FNMLA = { 2093, 3}, + .FNMLS = { 2096, 3}, + .NAND = { 2099, 1}, + .NOR = { 2100, 1}, + .SEL = { 2101, 1}, + .ORRS = { 2102, 1}, + .EORS = { 2103, 1}, + .NANDS = { 2104, 1}, + .NORS = { 2105, 1}, + .ORNS = { 2106, 1}, + .MOVS = { 2107, 1}, + .PTRUE = { 2108, 1}, + .PTRUES = { 2109, 1}, + .PFALSE = { 2110, 1}, + .PFIRST = { 2111, 1}, + .PNEXT = { 2112, 1}, + .BRKA = { 2113, 1}, + .BRKB = { 2114, 1}, + .BRKAS = { 2115, 1}, + .BRKBS = { 2116, 1}, + .BRKPA = { 2117, 1}, + .BRKPB = { 2118, 1}, + .BRKN = { 2119, 1}, + .RDFFR = { 2120, 1}, + .WRFFR = { 2121, 1}, + .SETFFR = { 2122, 1}, + .CMPEQ = { 2123, 4}, + .CMPNE = { 2127, 4}, + .CMPGE = { 2131, 4}, + .CMPGT = { 2135, 4}, + .CMPLE = { 2139, 4}, + .CMPLT = { 2143, 4}, + .CMPHI = { 2147, 4}, + .CMPHS = { 2151, 4}, + .CMPLO = { 2155, 4}, + .CMPLS = { 2159, 4}, + .FCMNE = { 2163, 3}, + .FCMUO = { 2166, 3}, + .INSR = { 2169, 4}, + .CPY = { 2173, 4}, + .COMPACT = { 2177, 2}, + .LD1B = { 2179, 6}, + .LD1H = { 2185, 6}, + .LD1W = { 2191, 6}, + .LD1D = { 2197, 5}, + .LD1SB = { 2202, 3}, + .LD1SH = { 2205, 3}, + .LD1SW = { 2208, 2}, + .ST1B = { 2210, 6}, + .ST1H = { 2216, 6}, + .ST1W = { 2222, 6}, + .ST1D = { 2228, 5}, + .LDFF1B = { 2233, 1}, + .LDFF1H = { 2234, 1}, + .LDFF1W = { 2235, 1}, + .LDFF1D = { 2236, 1}, + .WHILEGE = { 2237, 1}, + .WHILEGT = { 2238, 1}, + .WHILELE = { 2239, 1}, + .WHILELT = { 2240, 1}, + .WHILEHI = { 2241, 1}, + .WHILEHS = { 2242, 1}, + .WHILELO = { 2243, 1}, + .WHILELS = { 2244, 1}, + .SQRDMLAH = { 2245, 4}, + .SQRDMLSH = { 2249, 4}, + .ADCLB = { 2253, 2}, + .ADCLT = { 2255, 2}, + .SBCLB = { 2257, 2}, + .SBCLT = { 2259, 2}, + .TBL2 = { 2261, 1}, + .MATCH = { 2262, 2}, + .NMATCH = { 2264, 2}, + .HISTCNT = { 2266, 2}, + .HISTSEG = { 2268, 1}, + .SMSTART = { 2269, 1}, + .SMSTOP = { 2270, 1}, + .RDSVL = { 2271, 1}, + .ADDHA = { 2272, 1}, + .ADDVA = { 2273, 1}, + .ZERO = { 2274, 1}, + .FMOPA = { 2275, 1}, + .FMOPS = { 2276, 1}, + .BFMOPA = { 2277, 1}, + .BFMOPS = { 2278, 1}, + .SMOPA = { 2279, 2}, + .SMOPS = { 2281, 2}, + .UMOPA = { 2283, 2}, + .UMOPS = { 2285, 2}, + .USMOPA = { 2287, 1}, + .SUMOPA = { 2288, 1}, + .LD1Q = { 2289, 1}, + .ST1Q = { 2290, 1}, + .MOVA = { 2291, 2}, + .FCMLA = { 2293, 4}, + .FCADD = { 2297, 4}, + .PRFB = { 2301, 1}, + .PRFH = { 2302, 1}, + .PRFW = { 2303, 1}, + .PRFD = { 2304, 1}, + .LDNT1B = { 2305, 1}, + .LDNT1H = { 2306, 1}, + .LDNT1W = { 2307, 1}, + .LDNT1D = { 2308, 1}, + .STNT1B = { 2309, 1}, + .STNT1H = { 2310, 1}, + .STNT1W = { 2311, 1}, + .STNT1D = { 2312, 1}, + .SPLICE = { 2313, 1}, + .INDEX = { 2314, 4}, + .BSL1N = { 2318, 1}, + .BSL2N = { 2319, 1}, + .NBSL = { 2320, 1}, + .PMUL = { 2321, 1}, + .PMULLB = { 2322, 1}, + .PMULLT = { 2323, 1}, + .BFCVTNT = { 2324, 1}, + .LDRAA = { 2325, 2}, + .LDRAB = { 2327, 2}, + .TSTART = { 2329, 1}, + .TCOMMIT = { 2330, 1}, + .TCANCEL = { 2331, 1}, + .TTEST = { 2332, 1}, + .WFET = { 2333, 1}, + .WFIT = { 2334, 1}, + .BC_EQ = { 2335, 1}, + .BC_NE = { 2336, 1}, + .BC_CS = { 2337, 1}, + .BC_CC = { 2338, 1}, + .BC_MI = { 2339, 1}, + .BC_PL = { 2340, 1}, + .BC_VS = { 2341, 1}, + .BC_VC = { 2342, 1}, + .BC_HI = { 2343, 1}, + .BC_LS = { 2344, 1}, + .BC_GE = { 2345, 1}, + .BC_LT = { 2346, 1}, + .BC_GT = { 2347, 1}, + .BC_LE = { 2348, 1}, + .BC_AL = { 2349, 1}, + .BC_NV = { 2350, 1}, + .UXTB = { 2351, 1}, + .UXTH = { 2352, 1}, + .UXTW = { 2353, 1}, + .SXTB = { 2354, 1}, + .SXTH = { 2355, 1}, + .SXTW = { 2356, 1}, + .ADC = { 2357, 2}, + .ADCS = { 2359, 2}, + .SBC = { 2361, 2}, + .SBCS = { 2363, 2}, + .NGC = { 2365, 2}, + .NGCS = { 2367, 2}, + .LDAPUR = { 2369, 2}, + .STLUR = { 2371, 2}, + .LDAPURB = { 2373, 1}, + .STLURB = { 2374, 1}, + .LDAPURH = { 2375, 1}, + .STLURH = { 2376, 1}, + .LDAPURSB = { 2377, 2}, + .LDAPURSH = { 2379, 2}, + .LDAPURSW = { 2381, 1}, + .BFADD = { 2382, 2}, + .BFSUB = { 2384, 2}, + .BFMUL = { 2386, 2}, + .BFMLA = { 2388, 1}, + .BFMLS = { 2389, 1}, + .SB = { 2390, 1}, + .CSDB = { 2391, 1}, + .DGH = { 2392, 1}, + .PSB_CSYNC = { 2393, 1}, + .TSB_CSYNC = { 2394, 1}, + .BTI_J = { 2395, 1}, + .BTI_C = { 2396, 1}, + .BTI_JC = { 2397, 1}, + .BFCLAMP = { 2398, 1}, + .BFMAXNM = { 2399, 1}, + .BFMINNM = { 2400, 1}, + .LUTI2 = { 2401, 1}, + .LUTI4 = { 2402, 1}, + .ZIP = { 2403, 2}, + .UZP = { 2405, 2}, + .TLBI_RPALOS = { 2407, 1}, + .TLBI_RPAOS = { 2408, 1}, + .AT_S1E1A = { 2409, 1}, + .DC_CIPAPA = { 2410, 1}, + .DC_CIGDPAPA = { 2411, 1}, + .TLBI_PAALL = { 2412, 1}, + .TLBI_PAALLOS = { 2413, 1}, + .AMX_LDX = { 2414, 1}, + .AMX_LDY = { 2415, 1}, + .AMX_STX = { 2416, 1}, + .AMX_STY = { 2417, 1}, + .AMX_LDZ = { 2418, 1}, + .AMX_STZ = { 2419, 1}, + .AMX_LDZI = { 2420, 1}, + .AMX_STZI = { 2421, 1}, + .AMX_EXTRX = { 2422, 1}, + .AMX_EXTRY = { 2423, 1}, + .AMX_FMA64 = { 2424, 1}, + .AMX_FMS64 = { 2425, 1}, + .AMX_FMA32 = { 2426, 1}, + .AMX_FMS32 = { 2427, 1}, + .AMX_MAC16 = { 2428, 1}, + .AMX_FMA16 = { 2429, 1}, + .AMX_FMS16 = { 2430, 1}, + .AMX_SET = { 2431, 1}, + .AMX_CLR = { 2432, 1}, + .AMX_VECINT = { 2433, 1}, + .AMX_VECFP = { 2434, 1}, + .AMX_MATINT = { 2435, 1}, + .AMX_MATFP = { 2436, 1}, + .AMX_GENLUT = { 2437, 1}, + .CPYP = { 2438, 1}, + .CPYM = { 2439, 1}, + .CPYE = { 2440, 1}, + .CPYFP = { 2441, 1}, + .CPYFM = { 2442, 1}, + .CPYFE = { 2443, 1}, + .SETP = { 2444, 1}, + .SETM = { 2445, 1}, + .SETE = { 2446, 1}, + .DC_IVAC = { 2447, 1}, + .DC_ISW = { 2448, 1}, + .DC_CSW = { 2449, 1}, + .DC_CISW = { 2450, 1}, + .DC_ZVA = { 2451, 1}, + .DC_CVAC = { 2452, 1}, + .DC_CVAU = { 2453, 1}, + .DC_CIVAC = { 2454, 1}, + .IC_IALLUIS = { 2455, 1}, + .IC_IALLU = { 2456, 1}, + .IC_IVAU = { 2457, 1}, + .AT_S1E1R = { 2458, 1}, + .AT_S1E1W = { 2459, 1}, + .AT_S1E0R = { 2460, 1}, + .AT_S1E0W = { 2461, 1}, + .AT_S1E2R = { 2462, 1}, + .AT_S1E2W = { 2463, 1}, + .AT_S1E3R = { 2464, 1}, + .AT_S1E3W = { 2465, 1}, + .AT_S12E1R = { 2466, 1}, + .AT_S12E1W = { 2467, 1}, + .AT_S12E0R = { 2468, 1}, + .AT_S12E0W = { 2469, 1}, + .TLBI_VMALLE1 = { 2470, 1}, + .TLBI_VMALLE1IS = { 2471, 1}, + .TLBI_VAE1 = { 2472, 1}, + .TLBI_VAE1IS = { 2473, 1}, + .TLBI_ASIDE1 = { 2474, 1}, + .TLBI_ASIDE1IS = { 2475, 1}, + .TLBI_VAAE1 = { 2476, 1}, + .TLBI_VAAE1IS = { 2477, 1}, + .TLBI_VALE1 = { 2478, 1}, + .TLBI_VALE1IS = { 2479, 1}, + .TLBI_VAALE1 = { 2480, 1}, + .TLBI_VAALE1IS = { 2481, 1}, + .TLBI_ALLE1 = { 2482, 1}, + .TLBI_ALLE1IS = { 2483, 1}, + .TLBI_ALLE2 = { 2484, 1}, + .TLBI_ALLE2IS = { 2485, 1}, + .TLBI_ALLE3 = { 2486, 1}, + .TLBI_ALLE3IS = { 2487, 1}, + .PRFM = { 2488, 2}, + .PRFUM = { 2490, 1}, + .NEGS = { 2491, 2}, + .CMP = { 2493, 6}, + .CMN = { 2499, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index f1dc7abde..5ea78dfc8 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -191,14 +191,14 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ANDS = { {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -210,7 +210,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EOR = { {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -222,7 +222,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BIC = { {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -232,18 +232,18 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BICS = { {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EON = { {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -372,7 +372,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, }, .REV16 = { {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, @@ -554,7 +554,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, }, .STR = { @@ -572,7 +572,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, }, .LDRB = { @@ -1749,10 +1749,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .XAR = { {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .SM3PARTW1 = { {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, @@ -2594,9 +2591,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, @@ -2604,9 +2601,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, @@ -2614,9 +2611,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, @@ -2624,9 +2621,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, @@ -2634,9 +2631,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, @@ -3037,8 +3034,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, - {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, + {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.MOV, {.P_REG_S, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, @@ -3075,7 +3072,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .ZIP2 = { {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3089,7 +3086,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP1 = { {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3103,7 +3100,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP2 = { {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3117,7 +3114,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN1 = { {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3131,7 +3128,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN2 = { {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3145,12 +3142,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .NOT = { {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .REV64 = { {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, @@ -3315,70 +3312,70 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_H, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, }, .WRFFR = { {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, @@ -3387,74 +3384,74 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, @@ -3616,12 +3613,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index a987093704ac1c722b7f1734945c899a33ad56d0..ee40c7f39387a62e3fd549bf2688d995d53d8c09 100644 GIT binary patch delta 54 zcmV-60LlNTk^=sb0zkhs1OP?w2Uh?9 diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 0b1f201dca722dddd7d6ac853a05ab10925b2f99..757a48f10d78f8e31f923ab60c7beba473f15f57 100644 GIT binary patch delta 15163 zcmZ9T3wTu3wa53_Ga&&IGD#+ZgoKlYn1zIswd&M?( zj%~c8N-KD1uMcd7TWqyHT8z(DuY+I(?TfbFR*^E{Wwq8vYg@FVxohpc*WUZPejoWh zf9HSx|F!ns=P_r_yuUs2`1VM-!y=Ixj7Ntv_^*huV2Jq+i$-VcFTcYn)m!SsmW>>g zGs5Sb_0Ej2hL<=q1}^2DmTaq(MTP9X$hzdr%NZY00M@}0>7B#4VZRludl+*JE0(%p zw(d@;%e8f1lDb@5_cy7_WBdxn_=Sv(g5((d>u26@fZ>j4LunHf2b&p#q%?Fpf<<{# zcs%-L#}7Mm8l9$aS58TZR!ProBiY*Ushmc$_r-GWe6jcNVPAIEg~?&o_9b$Af!KZ& zw)^42+e2DWZD1IbFqVORN~PnC+Xjw~crFSh+)?;)vXe)1KlT!^_ax)6Z&K}ikJvdenIRNxd;dLRXPdnQ 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z=fu&>P{b=DeG{!W#keAhJh@G@@7!4aeiSa@>ubQDXBGgwA$~ET9m8E@KmB|-L7t(# XbSHV5enM+!??X$ti7#G7F2Mf)1!mwB From 9964798390bb433b75ae2d24687dc2050d18fe64 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:42:57 -0400 Subject: [PATCH 61/89] rexcode/arm32: the fixed-point VCVT matrix, and three fields read as themselves The VFP fixed-point conversions were a handful of forms whose comments named the 32-bit fixed-point variants but whose encodings all had `sx` clear, so they were the 16-bit ones; two of them were duplicates distinguished only by a looser mask. None of them decoded the fraction width at all, because the operand slot had no encoding, so every one of them printed `#0` -- and a `#0` fraction is not what any of these words mean. The block is now the full matrix the architecture defines: three floating-point widths by two fixed-point widths by four directions, twenty-four forms. The fraction is the fixed-point width less the imm4:i field, so the widest fraction is what a zero field encodes. LSR and ASR reach a shift of 32 through a zero field -- a shift of zero would be a MOV, so the encoding spends that value on the one amount five bits cannot otherwise name. Both the standalone mnemonics and the shifted operand of a data-processing instruction printed `#0`, which is not the same instruction; PKHTB dropped its `asr #32` entirely, since a zero amount prints as no shift at all. USAT and USAT16 saturate to an unsigned width of zero to 31 and store it as it stands, unlike SSAT and SSAT16, which store one less than a signed width of one to 32. They had been sharing the signed encoding and so read one too high. The AES and SHA forms carry a bare element size -- `aese.8`, `sha1c.32` -- and had no data type at all. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 21 +- core/rexcode/isa/arm32/encoder.odin | 8 + core/rexcode/isa/arm32/encoding_types.odin | 8 +- .../isa/arm32/tablegen/encoding_table.odin | 86 +- .../tablegen/generated/decode_tables.odin | 1638 +++++++++-------- .../tablegen/generated/encode_tables.odin | 696 +++---- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10670 -> 10726 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 38249 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4688 -> 4688 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 38249 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3298 -> 3326 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 15 +- 16 files changed, 1274 insertions(+), 1198 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 594021caf..4ef390294 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -269,6 +269,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op amt := u8((word >> 7) & 0x1F) if st == .ROR && amt == 0 { return op_reg_shifted(reg, .RRX, 0) } if st == .LSL && amt == 0 { return op_reg(reg) } + // A shift of zero is not a shift, so the field spends that + // spare value on 32 instead -- the one amount five bits cannot + // otherwise reach. LSL has no use for it and ROR spends it on + // RRX, so only these two. + if (st == .LSR || st == .ASR) && amt == 0 { return op_reg_shifted(reg, st, 32) } return op_reg_shifted(reg, st, amt) } return op_reg(reg) @@ -311,6 +316,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op // ---- A32 immediates ---- case .A32_IMM12: return op_imm(i64(word & 0xFFF)) case .A32_IMM_SHIFT: return op_imm(i64((word >> 7) & 0x1F)) + case .A32_IMM_SHIFT_32: + // The LSR and ASR mnemonics reach 32 the same way a shifted operand + // does: a field of zero, since a shift of zero would be a MOV. + amt := (word >> 7) & 0x1F + return op_imm(i64(amt == 0 ? 32 : amt)) case .A32_SHIFT_TYPE: return op_imm(i64((word >> 5) & 0x3)) case .A32_IMM24: // Ambiguous: A32_IMM24 is used both for branch displacements (B/BL, @@ -537,9 +547,18 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op return op_imm(i64((word >> 18) & 0xF)) // ---- Saturate / bit field ---- + case .VFP_FBITS: + // The fixed-point width is 16 or 32 by the sx bit, and the fraction + // is that less imm4:i -- so the widest fraction encodes as zero. + width: u32 = ((word >> 7) & 1) != 0 ? 32 : 16 + return op_imm(i64(width - (((word & 0xF) << 1) | ((word >> 5) & 1)))) case .SAT_IMM5, .SAT_IMM5_T32: - // The field holds one less than the saturate position it names. + // SSAT and SSAT16 saturate to a signed width of one to 32, and the + // field holds one less than that. USAT and USAT16 saturate to an + // unsigned width of zero to 31, which the field holds as it stands. return op_imm(i64(((word >> 16) & 0x1F) + 1)) + case .SAT_IMM5_U, .SAT_IMM5_U_T32: + return op_imm(i64((word >> 16) & 0x1F)) case .BFX_WIDTH: // One less than the width. return op_imm(i64(((word >> 16) & 0x1F) + 1)) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 036d97567..7d4805bb2 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -426,6 +426,7 @@ pack_operand_inline :: #force_inline proc( // ---- A32 immediate field placements ---- case .A32_IMM12: return u32(op.immediate) & 0xFFF case .A32_IMM_SHIFT: return (u32(op.immediate) & 0x1F) << 7 + case .A32_IMM_SHIFT_32: return (u32(op.immediate) & 0x1F) << 7 // 32 wraps to 0, which is what encodes it case .A32_SHIFT_TYPE: return (u32(op.immediate) & 0x3) << 5 case .A32_RS_SHIFT: return (u32(reg_hw(op.reg)) & 0xF) << 8 case .A32_IMM24: @@ -660,8 +661,15 @@ pack_operand_inline :: #force_inline proc( case .IT_MASK: return u32(op.immediate) & 0xFF case .CPS_IFLAGS: return u32(op.immediate) & 0x1FF case .HINT_FIELD: return u32(op.immediate) & 0xFF + case .VFP_FBITS: + // sx is a fixed bit of the form, so the width comes from its pattern. + width: u32 = ((form.bits >> 7) & 1) != 0 ? 32 : 16 + imm := width - (u32(op.immediate) & 0x3F) + return ((imm >> 1) & 0xF) | (imm & 1) << 5 case .SAT_IMM5, .SAT_IMM5_T32, .BFX_WIDTH: return ((u32(op.immediate) - 1) & 0x1F) << 16 + case .SAT_IMM5_U, .SAT_IMM5_U_T32: + return (u32(op.immediate) & 0x1F) << 16 case .BFI_MSB: // msb = lsb + width - 1; the lsb rides in whichever slot carries it. lsb: u32 = 0 diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 4d423bc8d..4d7333849 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -282,6 +282,7 @@ Operand_Encoding :: enum u8 { // ---- Immediate field placements (A32) ---- A32_IMM12, // bits 11-0 (LDR/STR offset) A32_IMM_SHIFT, // bits 11-7 (data-proc shift_imm) + A32_IMM_SHIFT_32, // same field, but a zero means 32 (LSR/ASR) A32_SHIFT_TYPE, // bits 6-5 A32_RS_SHIFT, // bits 11-8 (RSR uses Rs register) A32_IMM24, // bits 23-0 (B/BL/SVC) @@ -410,8 +411,11 @@ Operand_Encoding :: enum u8 { HINT_FIELD, // hint imm // ---- Saturate ---- - SAT_IMM5, // bits 20-16: SSAT/USAT saturate-to width - SAT_IMM5_T32, // Thumb-2 saturate amount + VFP_FBITS, // VCVT fixed-point fraction bits: width - (imm4:i) + SAT_IMM5, // bits 20-16: SSAT/SSAT16 saturate-to width, less one + SAT_IMM5_T32, // Thumb-2 signed saturate amount, less one + SAT_IMM5_U, // bits 20-16: USAT/USAT16 width, which is not biased + SAT_IMM5_U_T32, // Thumb-2 unsigned saturate amount // ---- BFC/BFI/SBFX/UBFX ---- // SBFX/UBFX hold the width less one, where BFI/BFC hold the top bit's diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 5266b6b11..347e0116b 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -614,8 +614,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT = { - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}}, - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5_U, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_U_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSAT16 = { {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, @@ -623,8 +623,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT16 = { - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5_U, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_U_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 USAD8 / USADA8 @@ -1547,24 +1547,34 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCVT.BF16.F32 D, Q // vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600 {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}, {.F16, .F32}}, - // VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}}, - // VCVT.U32.F32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}}, - // VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}}, - // VCVT.F32.U32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}}, - // VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16, .F32}}, - // VCVT.F32.S16 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32, .S16}}, - // F64 variants (sz=1): change cp to 1011 (bit 8 = 1) - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}}, - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}}, - // F16 variants (cp=1001, FEAT_FP16) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}}, - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}}, + // VCVT between floating point and fixed point. The `sx` bit picks the + // fixed-point width -- clear for 16-bit, set for 32-bit -- and the + // number of fraction bits is that width less the imm4:i field, so a + // field of zero is the widest fraction rather than none at all. + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .U16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .U32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32, .F32}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .VFP_FBITS, .NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32, .F32}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .U16}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F64}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S32}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .U32}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32, .F64}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .VFP_FBITS, .NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32, .F64}}, }, .VCVTB = { // VCVTB.F32.F16 / .F16.F32 @@ -2610,21 +2620,21 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON crypto (ARMv8 FEAT_AES / FEAT_SHA1 / FEAT_SHA256) // AESE/AESD/AESMC/AESIMC: 1111 0011 1011 size 00 Vd 0011 op M 0 Vm (op=0 AESE, 1 AESD; bit 7 selects MC) - .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} }, + .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} }, + .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} }, + .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ8, .NONE}} }, // SHA1 family - .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, - .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, + .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {.SZ32, .NONE}} }, // ========================================================================= // ยง11 -- T16 Thumb-1 + T32 Thumb-2 (Thumb-only mnemonics) @@ -2660,7 +2670,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LSR = { - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT_32, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: LSR imm {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, @@ -2672,7 +2682,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ASR = { - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT_32, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: ASR imm {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 986c3ebe8..9d4c275f7 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1649]lib.Decode_Entry{ +DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -151,8 +151,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .STREXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -211,12 +211,12 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -262,11 +262,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -318,7 +318,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -354,7 +354,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, - { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {}, {.I64,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, @@ -367,43 +367,43 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -434,16 +434,16 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -461,12 +461,12 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -485,14 +485,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, @@ -516,7 +516,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, - { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, @@ -558,7 +558,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, @@ -583,8 +583,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -602,7 +602,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, @@ -654,8 +654,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, @@ -675,144 +675,144 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, 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0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, + { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, + { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, + { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -820,30 +820,30 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -945,10 +945,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}, {.NONE,.NONE} }, { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, @@ -1023,8 +1023,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, @@ -1045,8 +1045,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, @@ -1092,8 +1092,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, - { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, + { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1117,20 +1117,20 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, - { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1143,15 +1143,30 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F64} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U16} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S32} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, @@ -1160,26 +1175,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -1242,12 +1256,12 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, - { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1273,8 +1287,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1404,13 +1418,13 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .DCPS1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1525,10 +1539,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1661,7 +1675,7 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1649]u16{ +DECODE_FORM_IDX := [1663]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1673,48 +1687,48 @@ DECODE_FORM_IDX := [1649]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 3, 9, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 23, 24, 25, 22, 21, 0, 0, 0, 19, 20, - 14, 17, 16, 13, 18, 10, 12, 11, 15, 0, 0, 0, 0, 11, 10, 0, - 6, 0, 0, 7, 2, 4, 6, 9, 3, 5, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 25, 23, 22, 24, 21, 0, 0, 0, 10, 20, + 15, 18, 11, 13, 19, 17, 12, 14, 16, 0, 0, 0, 0, 10, 11, 6, + 0, 0, 0, 6, 5, 8, 9, 3, 4, 2, 7, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, - 0, 0, 2, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, - 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, - 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 1, 6, 0, + 2, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, + 2, 19, 13, 12, 8, 2, 2, 7, 2, 7, 1, 3, 1, 3, 1, 3, + 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, 1, + 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, - 20, 14, 13, 9, 4, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, - 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 5, 4, 3, 9, 6, 7, 8, 2, 3, 7, 5, 6, 4, 2, 9, - 8, 10, 1, 0, 2, 0, 5, 1, 2, 3, 4, 2, 1, 0, 2, 0, - 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 1, 3, 5, - 2, 0, 4, 2, 0, 1, 4, 5, 3, 0, 5, 1, 3, 2, 4, 0, - 2, 3, 4, 5, 1, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 12, - 10, 13, 12, 15, 13, 14, 12, 14, 15, 13, 17, 14, 16, 15, 14, 16, - 15, 17, 1, 2, 0, 3, 0, 1, 0, 1, 0, 1, 3, 5, 0, 2, - 1, 3, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, - 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 2, 0, 2, - 0, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, - 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, + 20, 14, 13, 9, 4, 8, 4, 8, 4, 6, 6, 3, 5, 5, 7, 7, + 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 5, 9, 5, 9, 7, 7, + 0, 2, 5, 3, 4, 8, 6, 7, 9, 3, 6, 8, 2, 4, 7, 5, + 9, 10, 0, 1, 2, 5, 3, 1, 0, 4, 2, 2, 1, 0, 4, 0, + 2, 1, 0, 3, 1, 2, 3, 1, 0, 2, 3, 2, 1, 2, 4, 3, + 5, 0, 1, 2, 5, 3, 0, 1, 4, 1, 5, 0, 4, 2, 3, 3, + 1, 5, 4, 2, 0, 2, 3, 4, 3, 2, 4, 0, 0, 0, 11, 13, + 12, 10, 14, 15, 12, 13, 13, 12, 14, 15, 16, 14, 17, 15, 14, 15, + 16, 17, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, 3, 5, 0, 1, + 2, 3, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 2, 3, 0, 1, + 3, 2, 1, 0, 2, 3, 3, 0, 3, 0, 3, 2, 3, 1, 0, 1, + 2, 0, 0, 1, 1, 0, 2, 2, 3, 0, 2, 1, 0, 2, 1, 1, + 0, 1, 0, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1725,51 +1739,51 @@ DECODE_FORM_IDX := [1649]u16{ 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, - 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 1, 0, 1, 0, - 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 4, 32, + 0, 7, 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 4, 32, 31, 3, 2, 1, 0, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, - 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 0, 1, 2, 2, 0, + 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 1, 0, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, - 3, 2, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, - 0, 1, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 19, 18, - 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, - 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, - 0, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, - 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, - 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, - 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, - 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, - 27, 28, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, - 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, - 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, - 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, - 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, - 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, - 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, - 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, - 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, - 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 3, 2, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 34, 31, + 30, 32, 28, 26, 25, 27, 29, 33, 21, 19, 18, 20, 22, 15, 14, 16, + 12, 9, 11, 13, 17, 23, 5, 4, 6, 2, 0, 1, 3, 7, 24, 8, + 0, 1, 0, 1, 0, 1, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, + 0, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, + 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, + 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, + 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, 28, 27, + 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, 4, + 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, 0, + 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, 2, + 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, + 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, 6, + 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, 2, 2, + 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, - 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, - 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, - 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, - 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, - 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, - 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, - 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, - 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, - 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, 1, 1, + 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, + 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, + 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, + 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, 4, + 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, + 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, + 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, 1, + 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2, } @(rodata) -DECODE_BUCKET_LIST := [5335]u16{ +DECODE_BUCKET_LIST := [5363]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1905,205 +1919,207 @@ DECODE_BUCKET_LIST := [5335]u16{ 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, 1008, 995, 996, 1007, 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, - 1007, 1008, 997, 998, 992, 993, 994, 1010, 1011, 1007, 1012, 1008, 995, 1013, 996, 1015, + 1007, 1008, 997, 998, 992, 993, 994, 1011, 1010, 1007, 1012, 1008, 995, 1013, 996, 1015, 1014, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, + 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 1021, 995, 996, 1018, 1019, 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1020, 1021, 995, 996, - 1031, 1030, 1018, 1019, 1023, 1022, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, + 1030, 1031, 1018, 1019, 1022, 1023, 997, 998, 1018, 1019, 1021, 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1362, 1386, 1385, 1387, 1367, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1376, + 1385, 1386, 1387, 1376, 1385, 1386, 1387, 1366, 1417, 1385, 1386, 1387, 1385, 1386, 1387, 1361, + 1385, 1386, 1387, 1362, 1385, 1386, 1387, 1367, 1414, 1376, 1385, 1386, 1387, 1376, 1386, 1385, + 1387, 1408, 1414, 1376, 1385, 1386, 1387, 1376, 1385, 1386, 1387, 1366, 1412, 1386, 1385, 1387, + 1386, 1385, 1387, 1361, 1410, 1411, 1385, 1386, 1387, 1362, 1386, 1385, 1387, 1407, 1367, 1415, + 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1388, 1389, 1390, 1391, 1392, 1394, 1395, 1396, + 1397, 1399, 1400, 1401, 1402, 1409, 1415, 1376, 1386, 1385, 1387, 1393, 1398, 1404, 1405, 1406, + 1376, 1385, 1386, 1387, 1366, 1413, 1386, 1385, 1387, 1386, 1385, 1387, 1403, 1361, 1386, 1385, + 1387, 1362, 1386, 1385, 1387, 1367, 1376, 1377, 1386, 1385, 1387, 1368, 1376, 1378, 1386, 1385, + 1387, 1376, 1384, 1385, 1386, 1387, 1376, 1384, 1385, 1386, 1387, 1366, 1372, 1383, 1386, 1385, + 1387, 1373, 1383, 1385, 1386, 1387, 1361, 1374, 1385, 1386, 1387, 1362, 1374, 1386, 1385, 1387, + 1367, 1376, 1379, 1385, 1386, 1387, 1369, 1376, 1379, 1386, 1385, 1387, 1376, 1385, 1386, 1387, + 1376, 1386, 1385, 1387, 1366, 1385, 1386, 1387, 1385, 1386, 1387, 1361, 1386, 1385, 1387, 1362, + 1386, 1385, 1387, 1367, 1376, 1385, 1386, 1387, 1371, 1376, 1386, 1385, 1387, 1376, 1386, 1385, + 1387, 1376, 1386, 1385, 1387, 1366, 1381, 1386, 1385, 1387, 1381, 1386, 1385, 1387, 1361, 1382, + 1386, 1385, 1387, 1362, 1382, 1386, 1385, 1387, 1367, 1376, 1386, 1385, 1387, 1376, 1385, 1386, + 1387, 1376, 1386, 1385, 1387, 1370, 1376, 1386, 1385, 1387, 1366, 1380, 1385, 1386, 1387, 1380, + 1385, 1386, 1387, 1361, 1385, 1386, 1387, 1362, 1386, 1385, 1387, 1367, 1376, 1385, 1386, 1387, + 1376, 1386, 1385, 1387, 1376, 1385, 1386, 1387, 1376, 1385, 1386, 1387, 1366, 1416, 1386, 1385, + 1387, 1385, 1386, 1387, 1361, 1385, 1386, 1387, 1362, 1385, 1386, 1387, 1367, 1376, 1386, 1385, + 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1366, 1417, 1385, + 1386, 1387, 1385, 1386, 1387, 1361, 1386, 1385, 1387, 1362, 1385, 1386, 1387, 1367, 1376, 1386, + 1385, 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1366, 1385, + 1386, 1387, 1386, 1385, 1387, 1361, 1386, 1385, 1387, 1362, 1385, 1386, 1387, 1418, 1419, 1420, + 1367, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, 1387, 1376, 1386, 1385, + 1387, 1366, 1386, 1385, 1387, 1386, 1385, 1387, 1361, 1386, 1385, 1387, 1362, 1421, 1385, 1386, + 1387, 1425, 1424, 1427, 1426, 1431, 1423, 1422, 1433, 1437, 1430, 1436, 1439, 1438, 1435, 1433, + 1434, 1428, 1429, 1432, 1440, 1441, 1444, 1448, 1503, 1447, 1506, 1443, 1449, 1502, 1446, 1505, + 1442, 1450, 1501, 1445, 1504, 1451, 1457, 1458, 1459, 1460, 1461, 1467, 1473, 1479, 1485, 1491, + 1453, 1454, 1455, 1456, 1462, 1468, 1474, 1480, 1486, 1492, 1463, 1469, 1475, 1481, 1487, 1493, + 1452, 1465, 1471, 1477, 1483, 1489, 1495, 1466, 1472, 1478, 1484, 1490, 1496, 1464, 1470, 1476, + 1482, 1488, 1494, 1497, 1507, 1508, 1500, 1511, 1498, 1509, 1499, 1512, 1510, 1535, 1534, 1525, + 1530, 1532, 1525, 1531, 1533, 1535, 1534, 1530, 1532, 1531, 1533, 1519, 1520, 1521, 1522, 1523, + 1524, 1535, 1513, 1514, 1515, 1516, 1517, 1518, 1526, 1527, 1528, 1529, 1534, 1525, 1530, 1532, + 1525, 1531, 1533, 1519, 1520, 1521, 1522, 1523, 1524, 1535, 1513, 1514, 1515, 1516, 1517, 1518, + 1534, 1530, 1532, 1531, 1533, 1525, 1525, 1526, 1527, 1528, 1529, 1525, 1525, 1552, 1275, 1276, + 1291, 1292, 1293, 1558, 1304, 1305, 1563, 1564, 1565, 1566, 1308, 1568, 1311, 1312, 1315, 1316, + 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1581, 1275, 1276, 1291, 1292, 1293, 1558, 1305, + 1563, 1564, 1565, 1566, 1308, 1568, 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, 1330, + 1331, 1332, 1581, 1275, 1276, 1291, 1292, 1293, 1558, 1305, 1563, 1564, 1565, 1566, 1308, 1568, + 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1581, 1537, 1546, 1547, + 1275, 1276, 1277, 1291, 1292, 1293, 1294, 1558, 1303, 1305, 1563, 1564, 1565, 1566, 1308, 1568, + 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1581, 1552, 1275, 1276, + 1291, 1292, 1293, 1558, 1304, 1305, 1563, 1564, 1565, 1566, 1308, 1568, 1311, 1312, 1315, 1316, + 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1577, 1581, 1275, 1276, 1291, 1292, 1293, 1558, + 1305, 1563, 1564, 1565, 1566, 1308, 1568, 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, + 1330, 1331, 1332, 1577, 1581, 1275, 1276, 1291, 1292, 1293, 1558, 1305, 1563, 1564, 1565, 1566, + 1308, 1568, 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1577, 1581, + 1536, 1546, 1547, 1275, 1276, 1277, 1291, 1292, 1293, 1294, 1558, 1303, 1305, 1563, 1564, 1565, + 1566, 1308, 1568, 1311, 1312, 1315, 1316, 1317, 1318, 1319, 1320, 1329, 1330, 1331, 1332, 1577, + 1581, 1253, 1254, 1286, 1287, 1288, 1289, 1297, 1298, 1299, 1300, 1559, 1560, 1561, 1562, 1568, + 1313, 1314, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1573, 1574, 1575, 1576, 1350, 1579, + 1582, 1559, 1560, 1561, 1562, 1568, 1313, 1314, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, + 1579, 1582, 1559, 1560, 1561, 1562, 1568, 1313, 1314, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1579, 1582, 1544, 1545, 1284, 1285, 1295, 1296, 1301, 1302, 1559, 1560, 1561, 1562, 1568, + 1313, 1314, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1569, 1570, 1571, 1572, 1579, 1582, + 1286, 1287, 1288, 1289, 1297, 1298, 1299, 1300, 1559, 1560, 1561, 1562, 1568, 1313, 1314, 1321, + 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1573, 1574, 1575, 1576, 1350, 1578, 1580, 1582, 1559, + 1560, 1561, 1562, 1568, 1313, 1314, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1578, 1580, + 1582, 1255, 1256, 1257, 1258, 1267, 1268, 1269, 1270, 1559, 1560, 1561, 1562, 1568, 1313, 1314, + 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1578, 1580, 1582, 1544, 1545, 1265, 1266, 1284, + 1285, 1295, 1296, 1301, 1302, 1559, 1560, 1561, 1562, 1568, 1313, 1314, 1321, 1322, 1323, 1324, + 1325, 1326, 1327, 1328, 1569, 1570, 1571, 1572, 1578, 1580, 1582, 1556, 1557, 1558, 1306, 1567, + 1309, 1568, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1557, 1558, + 1306, 1567, 1309, 1568, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, + 1558, 1567, 1307, 1310, 1568, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, + 1344, 1558, 1307, 1567, 1310, 1568, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, + 1343, 1344, 1556, 1557, 1558, 1306, 1567, 1309, 1568, 1333, 1334, 1335, 1336, 1337, 1338, 1339, + 1340, 1341, 1342, 1343, 1344, 1557, 1558, 1306, 1567, 1309, 1568, 1333, 1334, 1335, 1336, 1337, + 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1558, 1567, 1307, 1310, 1568, 1333, 1334, 1335, 1336, + 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1558, 1567, 1307, 1310, 1568, 1333, 1334, 1335, + 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1568, 1347, 1348, 1349, 1568, 1347, 1348, + 1349, 1568, 1347, 1348, 1349, 1538, 1539, 1540, 1541, 1542, 1543, 1548, 1549, 1550, 1551, 1553, + 1554, 1555, 1568, 1347, 1348, 1349, 1568, 1347, 1348, 1349, 1568, 1347, 1348, 1349, 1568, 1347, + 1348, 1349, 1538, 1539, 1540, 1541, 1542, 1543, 1548, 1549, 1550, 1551, 1553, 1554, 1555, 1568, + 1347, 1348, 1349, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2335,419 +2351,419 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0xE8 = { 2442, 14}, 0xE9 = { 2456, 11}, 0xEA = { 2467, 10}, - 0xEB = { 2477, 77}, - 0xEC = { 2554, 15}, - 0xED = { 2569, 11}, - 0xEE = { 2580, 12}, - 0xEF = { 2592, 78}, - 0xF0 = { 2670, 3}, - 0xF1 = { 2673, 3}, - 0xF2 = { 2676, 3}, - 0xF3 = { 2679, 3}, - 0xF4 = { 2682, 3}, - 0xF5 = { 2685, 3}, - 0xF6 = { 2688, 3}, - 0xF7 = { 2691, 3}, - 0xF8 = { 2694, 1}, - 0xF9 = { 2695, 1}, - 0xFA = { 2696, 1}, - 0xFB = { 2697, 1}, - 0xFC = { 2698, 1}, - 0xFD = { 2699, 1}, - 0xFE = { 2700, 1}, - 0xFF = { 2701, 1}, + 0xEB = { 2477, 91}, + 0xEC = { 2568, 15}, + 0xED = { 2583, 11}, + 0xEE = { 2594, 12}, + 0xEF = { 2606, 92}, + 0xF0 = { 2698, 3}, + 0xF1 = { 2701, 3}, + 0xF2 = { 2704, 3}, + 0xF3 = { 2707, 3}, + 0xF4 = { 2710, 3}, + 0xF5 = { 2713, 3}, + 0xF6 = { 2716, 3}, + 0xF7 = { 2719, 3}, + 0xF8 = { 2722, 1}, + 0xF9 = { 2723, 1}, + 0xFA = { 2724, 1}, + 0xFB = { 2725, 1}, + 0xFC = { 2726, 1}, + 0xFD = { 2727, 1}, + 0xFE = { 2728, 1}, + 0xFF = { 2729, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2702, 23}, - 0x75 = { 2725, 19}, - 0x76 = { 2744, 19}, - 0x77 = { 2763, 104}, - 0x78 = { 2867, 31}, - 0x79 = { 2898, 38}, - 0x7A = { 2936, 23}, - 0x7B = { 2959, 14}, - 0x7C = { 2973, 20}, - 0x7D = { 2993, 71}, - 0x7E = { 3064, 23}, - 0x7F = { 3087, 126}, + 0x74 = { 2730, 23}, + 0x75 = { 2753, 19}, + 0x76 = { 2772, 19}, + 0x77 = { 2791, 104}, + 0x78 = { 2895, 31}, + 0x79 = { 2926, 38}, + 0x7A = { 2964, 23}, + 0x7B = { 2987, 14}, + 0x7C = { 3001, 20}, + 0x7D = { 3021, 71}, + 0x7E = { 3092, 23}, + 0x7F = { 3115, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3213, 1}, - 0x01 = { 3214, 1}, - 0x02 = { 3215, 1}, - 0x03 = { 3216, 1}, - 0x04 = { 3217, 1}, - 0x05 = { 3218, 1}, - 0x06 = { 3219, 2}, - 0x07 = { 3221, 2}, - 0x08 = { 3223, 1}, - 0x09 = { 3224, 1}, - 0x0A = { 3225, 1}, - 0x0B = { 3226, 1}, - 0x0C = { 3227, 1}, - 0x0D = { 3228, 1}, - 0x0E = { 3229, 1}, - 0x0F = { 3230, 1}, - 0x10 = { 3231, 16}, - 0x11 = { 3247, 7}, - 0x12 = { 3254, 1}, - 0x13 = { 3255, 1}, - 0x14 = { 3256, 2}, - 0x15 = { 3258, 2}, - 0x16 = { 3260, 2}, - 0x17 = { 3262, 2}, - 0x18 = { 3264, 1}, - 0x19 = { 3265, 1}, - 0x1A = { 3266, 1}, - 0x1B = { 3267, 1}, - 0x1C = { 3268, 1}, - 0x1D = { 3269, 1}, - 0x1E = { 3270, 1}, - 0x1F = { 3271, 1}, - 0x20 = { 3272, 1}, - 0x21 = { 3273, 1}, - 0x22 = { 3274, 1}, - 0x23 = { 3275, 1}, - 0x24 = { 3276, 1}, - 0x25 = { 3277, 1}, - 0x26 = { 3278, 1}, - 0x27 = { 3279, 1}, - 0x28 = { 3280, 1}, - 0x29 = { 3281, 1}, - 0x2A = { 3282, 1}, - 0x2B = { 3283, 1}, - 0x2C = { 3284, 7}, - 0x2D = { 3291, 2}, - 0x2E = { 3293, 4}, - 0x2F = { 3297, 8}, - 0x30 = { 3305, 1}, - 0x31 = { 3306, 1}, - 0x32 = { 3307, 1}, - 0x33 = { 3308, 1}, - 0x34 = { 3309, 1}, - 0x35 = { 3310, 1}, - 0x36 = { 3311, 1}, - 0x37 = { 3312, 3}, - 0x38 = { 3315, 1}, - 0x39 = { 3316, 1}, + 0x00 = { 3241, 1}, + 0x01 = { 3242, 1}, + 0x02 = { 3243, 1}, + 0x03 = { 3244, 1}, + 0x04 = { 3245, 1}, + 0x05 = { 3246, 1}, + 0x06 = { 3247, 2}, + 0x07 = { 3249, 2}, + 0x08 = { 3251, 1}, + 0x09 = { 3252, 1}, + 0x0A = { 3253, 1}, + 0x0B = { 3254, 1}, + 0x0C = { 3255, 1}, + 0x0D = { 3256, 1}, + 0x0E = { 3257, 1}, + 0x0F = { 3258, 1}, + 0x10 = { 3259, 16}, + 0x11 = { 3275, 7}, + 0x12 = { 3282, 1}, + 0x13 = { 3283, 1}, + 0x14 = { 3284, 2}, + 0x15 = { 3286, 2}, + 0x16 = { 3288, 2}, + 0x17 = { 3290, 2}, + 0x18 = { 3292, 1}, + 0x19 = { 3293, 1}, + 0x1A = { 3294, 1}, + 0x1B = { 3295, 1}, + 0x1C = { 3296, 1}, + 0x1D = { 3297, 1}, + 0x1E = { 3298, 1}, + 0x1F = { 3299, 1}, + 0x20 = { 3300, 1}, + 0x21 = { 3301, 1}, + 0x22 = { 3302, 1}, + 0x23 = { 3303, 1}, + 0x24 = { 3304, 1}, + 0x25 = { 3305, 1}, + 0x26 = { 3306, 1}, + 0x27 = { 3307, 1}, + 0x28 = { 3308, 1}, + 0x29 = { 3309, 1}, + 0x2A = { 3310, 1}, + 0x2B = { 3311, 1}, + 0x2C = { 3312, 7}, + 0x2D = { 3319, 2}, + 0x2E = { 3321, 4}, + 0x2F = { 3325, 8}, + 0x30 = { 3333, 1}, + 0x31 = { 3334, 1}, + 0x32 = { 3335, 1}, + 0x33 = { 3336, 1}, + 0x34 = { 3337, 1}, + 0x35 = { 3338, 1}, + 0x36 = { 3339, 1}, + 0x37 = { 3340, 3}, + 0x38 = { 3343, 1}, + 0x39 = { 3344, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3317, 6}, - 0xE85 = { 3323, 2}, - 0xE86 = { 3325, 1}, - 0xE87 = { 3326, 1}, - 0xE88 = { 3327, 1}, - 0xE89 = { 3328, 1}, - 0xE8A = { 3329, 1}, - 0xE8B = { 3330, 2}, - 0xE8C = { 3332, 4}, - 0xE8D = { 3336, 6}, - 0xE8E = { 3342, 1}, - 0xE8F = { 3343, 1}, - 0xE90 = { 3344, 1}, - 0xE91 = { 3345, 1}, - 0xE92 = { 3346, 2}, - 0xE93 = { 3348, 1}, - 0xE94 = { 3349, 1}, - 0xE95 = { 3350, 1}, - 0xE96 = { 3351, 1}, - 0xE97 = { 3352, 2}, - 0xE9C = { 3354, 1}, - 0xE9D = { 3355, 1}, - 0xE9E = { 3356, 1}, - 0xE9F = { 3357, 1}, - 0xEA0 = { 3358, 1}, - 0xEA1 = { 3359, 2}, - 0xEA2 = { 3361, 1}, - 0xEA3 = { 3362, 1}, - 0xEA4 = { 3363, 6}, - 0xEA5 = { 3369, 2}, - 0xEA6 = { 3371, 1}, - 0xEA7 = { 3372, 1}, - 0xEA8 = { 3373, 1}, - 0xEA9 = { 3374, 2}, - 0xEB1 = { 3376, 1}, - 0xEB4 = { 3377, 1}, - 0xEB5 = { 3378, 1}, - 0xEB6 = { 3379, 1}, - 0xEB7 = { 3380, 1}, - 0xEBB = { 3381, 1}, - 0xEBC = { 3382, 1}, - 0xEBD = { 3383, 1}, - 0xEC0 = { 3384, 2}, - 0xEC1 = { 3386, 1}, - 0xEC2 = { 3387, 3}, - 0xEC3 = { 3390, 2}, - 0xEC4 = { 3392, 2}, - 0xEC5 = { 3394, 1}, - 0xEC6 = { 3395, 7}, - 0xEC7 = { 3402, 2}, - 0xEC8 = { 3404, 1}, - 0xEC9 = { 3405, 1}, - 0xECA = { 3406, 2}, - 0xECB = { 3408, 2}, - 0xECC = { 3410, 1}, - 0xECD = { 3411, 1}, - 0xECE = { 3412, 2}, - 0xECF = { 3414, 2}, - 0xED6 = { 3416, 4}, - 0xED8 = { 3420, 4}, - 0xED9 = { 3424, 4}, - 0xEDC = { 3428, 4}, - 0xEDD = { 3432, 4}, - 0xEE0 = { 3436, 24}, - 0xEE1 = { 3460, 23}, - 0xEE2 = { 3483, 22}, - 0xEE3 = { 3505, 29}, - 0xEE4 = { 3534, 23}, - 0xEE5 = { 3557, 22}, - 0xEE6 = { 3579, 22}, - 0xEE7 = { 3601, 29}, - 0xEE8 = { 3630, 28}, - 0xEE9 = { 3658, 12}, - 0xEEA = { 3670, 13}, - 0xEEB = { 3683, 18}, - 0xEEC = { 3701, 27}, - 0xEED = { 3728, 13}, - 0xEEE = { 3741, 22}, - 0xEEF = { 3763, 23}, - 0xEF0 = { 3786, 15}, - 0xEF1 = { 3801, 15}, - 0xEF2 = { 3816, 15}, - 0xEF3 = { 3831, 15}, - 0xEF4 = { 3846, 15}, - 0xEF5 = { 3861, 15}, - 0xEF6 = { 3876, 15}, - 0xEF7 = { 3891, 15}, - 0xEF8 = { 3906, 3}, - 0xEF9 = { 3909, 3}, - 0xEFA = { 3912, 3}, - 0xEFB = { 3915, 3}, - 0xEFC = { 3918, 3}, - 0xEFD = { 3921, 3}, - 0xEFE = { 3924, 3}, - 0xEFF = { 3927, 3}, - 0xF00 = { 3930, 11}, - 0xF01 = { 3941, 10}, - 0xF02 = { 3951, 8}, - 0xF03 = { 3959, 8}, - 0xF04 = { 3967, 8}, - 0xF05 = { 3975, 5}, - 0xF06 = { 3980, 5}, - 0xF07 = { 3985, 5}, - 0xF08 = { 3990, 6}, - 0xF09 = { 3996, 6}, - 0xF0A = { 4002, 4}, - 0xF0B = { 4006, 4}, - 0xF0C = { 4010, 4}, - 0xF0D = { 4014, 3}, - 0xF0E = { 4017, 4}, - 0xF0F = { 4021, 4}, - 0xF10 = { 4025, 7}, - 0xF11 = { 4032, 7}, - 0xF12 = { 4039, 6}, - 0xF13 = { 4045, 6}, - 0xF14 = { 4051, 5}, - 0xF15 = { 4056, 4}, - 0xF16 = { 4060, 5}, - 0xF17 = { 4065, 5}, - 0xF18 = { 4070, 5}, - 0xF19 = { 4075, 4}, - 0xF1A = { 4079, 4}, - 0xF1B = { 4083, 5}, - 0xF1C = { 4088, 5}, - 0xF1D = { 4093, 4}, - 0xF1E = { 4097, 4}, - 0xF1F = { 4101, 4}, - 0xF20 = { 4105, 5}, - 0xF21 = { 4110, 4}, - 0xF22 = { 4114, 4}, - 0xF23 = { 4118, 4}, - 0xF24 = { 4122, 5}, - 0xF25 = { 4127, 3}, - 0xF26 = { 4130, 4}, - 0xF27 = { 4134, 4}, - 0xF28 = { 4138, 5}, - 0xF29 = { 4143, 4}, - 0xF2A = { 4147, 4}, - 0xF2B = { 4151, 4}, - 0xF2C = { 4155, 5}, - 0xF2D = { 4160, 3}, - 0xF2E = { 4163, 4}, - 0xF2F = { 4167, 4}, - 0xF30 = { 4171, 6}, - 0xF31 = { 4177, 4}, - 0xF32 = { 4181, 6}, - 0xF33 = { 4187, 4}, - 0xF34 = { 4191, 5}, - 0xF35 = { 4196, 3}, - 0xF36 = { 4199, 6}, - 0xF37 = { 4205, 4}, - 0xF38 = { 4209, 7}, - 0xF39 = { 4216, 4}, - 0xF3A = { 4220, 19}, - 0xF3B = { 4239, 9}, - 0xF3C = { 4248, 5}, - 0xF3D = { 4253, 3}, - 0xF3E = { 4256, 5}, - 0xF3F = { 4261, 4}, - 0xF40 = { 4265, 6}, - 0xF41 = { 4271, 6}, - 0xF42 = { 4277, 5}, - 0xF43 = { 4282, 5}, - 0xF44 = { 4287, 6}, - 0xF45 = { 4293, 5}, - 0xF46 = { 4298, 5}, - 0xF47 = { 4303, 5}, - 0xF48 = { 4308, 6}, - 0xF49 = { 4314, 6}, - 0xF4A = { 4320, 4}, - 0xF4B = { 4324, 4}, - 0xF4C = { 4328, 4}, - 0xF4D = { 4332, 3}, - 0xF4E = { 4335, 4}, - 0xF4F = { 4339, 4}, - 0xF50 = { 4343, 5}, - 0xF51 = { 4348, 5}, - 0xF52 = { 4353, 4}, - 0xF53 = { 4357, 4}, - 0xF54 = { 4361, 5}, - 0xF55 = { 4366, 4}, - 0xF56 = { 4370, 5}, - 0xF57 = { 4375, 5}, - 0xF58 = { 4380, 5}, - 0xF59 = { 4385, 4}, - 0xF5A = { 4389, 4}, - 0xF5B = { 4393, 5}, - 0xF5C = { 4398, 5}, - 0xF5D = { 4403, 4}, - 0xF5E = { 4407, 4}, - 0xF5F = { 4411, 4}, - 0xF60 = { 4415, 5}, - 0xF61 = { 4420, 4}, - 0xF62 = { 4424, 4}, - 0xF63 = { 4428, 4}, - 0xF64 = { 4432, 5}, - 0xF65 = { 4437, 3}, - 0xF66 = { 4440, 4}, - 0xF67 = { 4444, 4}, - 0xF68 = { 4448, 5}, - 0xF69 = { 4453, 4}, - 0xF6A = { 4457, 4}, - 0xF6B = { 4461, 4}, - 0xF6C = { 4465, 5}, - 0xF6D = { 4470, 3}, - 0xF6E = { 4473, 4}, - 0xF6F = { 4477, 4}, - 0xF70 = { 4481, 5}, - 0xF71 = { 4486, 4}, - 0xF72 = { 4490, 4}, - 0xF73 = { 4494, 4}, - 0xF74 = { 4498, 4}, - 0xF75 = { 4502, 3}, - 0xF76 = { 4505, 4}, - 0xF77 = { 4509, 4}, - 0xF78 = { 4513, 8}, - 0xF79 = { 4521, 4}, - 0xF7A = { 4525, 4}, - 0xF7B = { 4529, 4}, - 0xF7C = { 4533, 4}, - 0xF7D = { 4537, 3}, - 0xF7E = { 4540, 4}, - 0xF7F = { 4544, 5}, - 0xF80 = { 4549, 1}, - 0xF81 = { 4550, 1}, - 0xF82 = { 4551, 1}, - 0xF83 = { 4552, 2}, - 0xF84 = { 4554, 1}, - 0xF85 = { 4555, 2}, - 0xF88 = { 4557, 1}, - 0xF89 = { 4558, 2}, - 0xF8A = { 4560, 1}, - 0xF8B = { 4561, 1}, - 0xF8C = { 4562, 1}, - 0xF8D = { 4563, 2}, - 0xF91 = { 4565, 1}, - 0xF93 = { 4566, 1}, - 0xF99 = { 4567, 2}, - 0xF9B = { 4569, 1}, - 0xFA0 = { 4570, 3}, - 0xFA1 = { 4573, 2}, - 0xFA2 = { 4575, 3}, - 0xFA3 = { 4578, 2}, - 0xFA4 = { 4580, 3}, - 0xFA5 = { 4583, 2}, - 0xFA6 = { 4585, 1}, - 0xFA8 = { 4586, 10}, - 0xFA9 = { 4596, 10}, - 0xFAA = { 4606, 6}, - 0xFAB = { 4612, 1}, - 0xFAC = { 4613, 6}, - 0xFAD = { 4619, 6}, - 0xFAE = { 4625, 6}, - 0xFB0 = { 4631, 3}, - 0xFB5 = { 4634, 1}, - 0xFB8 = { 4635, 1}, - 0xFB9 = { 4636, 1}, - 0xFBA = { 4637, 1}, - 0xFBB = { 4638, 1}, - 0xFBC = { 4639, 1}, - 0xFBE = { 4640, 1}, - 0xFC0 = { 4641, 1}, - 0xFC1 = { 4642, 1}, - 0xFC2 = { 4643, 3}, - 0xFC3 = { 4646, 3}, - 0xFC4 = { 4649, 1}, - 0xFC5 = { 4650, 1}, - 0xFC6 = { 4651, 2}, - 0xFC7 = { 4653, 2}, - 0xFC8 = { 4655, 7}, - 0xFC9 = { 4662, 11}, - 0xFCA = { 4673, 3}, - 0xFCB = { 4676, 3}, - 0xFCC = { 4679, 7}, - 0xFCD = { 4686, 7}, - 0xFCE = { 4693, 2}, - 0xFCF = { 4695, 2}, - 0xFD2 = { 4697, 1}, - 0xFD3 = { 4698, 1}, - 0xFD9 = { 4699, 4}, - 0xFDA = { 4703, 1}, - 0xFDB = { 4704, 1}, - 0xFE0 = { 4705, 28}, - 0xFE1 = { 4733, 26}, - 0xFE2 = { 4759, 26}, - 0xFE3 = { 4785, 32}, - 0xFE4 = { 4817, 29}, - 0xFE5 = { 4846, 27}, - 0xFE6 = { 4873, 27}, - 0xFE7 = { 4900, 33}, - 0xFE8 = { 4933, 32}, - 0xFE9 = { 4965, 17}, - 0xFEA = { 4982, 17}, - 0xFEB = { 4999, 29}, - 0xFEC = { 5028, 31}, - 0xFED = { 5059, 18}, - 0xFEE = { 5077, 26}, - 0xFEF = { 5103, 32}, - 0xFF0 = { 5135, 19}, - 0xFF1 = { 5154, 18}, - 0xFF2 = { 5172, 17}, - 0xFF3 = { 5189, 17}, - 0xFF4 = { 5206, 19}, - 0xFF5 = { 5225, 18}, - 0xFF6 = { 5243, 17}, - 0xFF7 = { 5260, 17}, - 0xFF8 = { 5277, 4}, - 0xFF9 = { 5281, 4}, - 0xFFA = { 5285, 4}, - 0xFFB = { 5289, 17}, - 0xFFC = { 5306, 4}, - 0xFFD = { 5310, 4}, - 0xFFE = { 5314, 4}, - 0xFFF = { 5318, 17}, + 0xE84 = { 3345, 6}, + 0xE85 = { 3351, 2}, + 0xE86 = { 3353, 1}, + 0xE87 = { 3354, 1}, + 0xE88 = { 3355, 1}, + 0xE89 = { 3356, 1}, + 0xE8A = { 3357, 1}, + 0xE8B = { 3358, 2}, + 0xE8C = { 3360, 4}, + 0xE8D = { 3364, 6}, + 0xE8E = { 3370, 1}, + 0xE8F = { 3371, 1}, + 0xE90 = { 3372, 1}, + 0xE91 = { 3373, 1}, + 0xE92 = { 3374, 2}, + 0xE93 = { 3376, 1}, + 0xE94 = { 3377, 1}, + 0xE95 = { 3378, 1}, + 0xE96 = { 3379, 1}, + 0xE97 = { 3380, 2}, + 0xE9C = { 3382, 1}, + 0xE9D = { 3383, 1}, + 0xE9E = { 3384, 1}, + 0xE9F = { 3385, 1}, + 0xEA0 = { 3386, 1}, + 0xEA1 = { 3387, 2}, + 0xEA2 = { 3389, 1}, + 0xEA3 = { 3390, 1}, + 0xEA4 = { 3391, 6}, + 0xEA5 = { 3397, 2}, + 0xEA6 = { 3399, 1}, + 0xEA7 = { 3400, 1}, + 0xEA8 = { 3401, 1}, + 0xEA9 = { 3402, 2}, + 0xEB1 = { 3404, 1}, + 0xEB4 = { 3405, 1}, + 0xEB5 = { 3406, 1}, + 0xEB6 = { 3407, 1}, + 0xEB7 = { 3408, 1}, + 0xEBB = { 3409, 1}, + 0xEBC = { 3410, 1}, + 0xEBD = { 3411, 1}, + 0xEC0 = { 3412, 2}, + 0xEC1 = { 3414, 1}, + 0xEC2 = { 3415, 3}, + 0xEC3 = { 3418, 2}, + 0xEC4 = { 3420, 2}, + 0xEC5 = { 3422, 1}, + 0xEC6 = { 3423, 7}, + 0xEC7 = { 3430, 2}, + 0xEC8 = { 3432, 1}, + 0xEC9 = { 3433, 1}, + 0xECA = { 3434, 2}, + 0xECB = { 3436, 2}, + 0xECC = { 3438, 1}, + 0xECD = { 3439, 1}, + 0xECE = { 3440, 2}, + 0xECF = { 3442, 2}, + 0xED6 = { 3444, 4}, + 0xED8 = { 3448, 4}, + 0xED9 = { 3452, 4}, + 0xEDC = { 3456, 4}, + 0xEDD = { 3460, 4}, + 0xEE0 = { 3464, 24}, + 0xEE1 = { 3488, 23}, + 0xEE2 = { 3511, 22}, + 0xEE3 = { 3533, 29}, + 0xEE4 = { 3562, 23}, + 0xEE5 = { 3585, 22}, + 0xEE6 = { 3607, 22}, + 0xEE7 = { 3629, 29}, + 0xEE8 = { 3658, 28}, + 0xEE9 = { 3686, 12}, + 0xEEA = { 3698, 13}, + 0xEEB = { 3711, 18}, + 0xEEC = { 3729, 27}, + 0xEED = { 3756, 13}, + 0xEEE = { 3769, 22}, + 0xEEF = { 3791, 23}, + 0xEF0 = { 3814, 15}, + 0xEF1 = { 3829, 15}, + 0xEF2 = { 3844, 15}, + 0xEF3 = { 3859, 15}, + 0xEF4 = { 3874, 15}, + 0xEF5 = { 3889, 15}, + 0xEF6 = { 3904, 15}, + 0xEF7 = { 3919, 15}, + 0xEF8 = { 3934, 3}, + 0xEF9 = { 3937, 3}, + 0xEFA = { 3940, 3}, + 0xEFB = { 3943, 3}, + 0xEFC = { 3946, 3}, + 0xEFD = { 3949, 3}, + 0xEFE = { 3952, 3}, + 0xEFF = { 3955, 3}, + 0xF00 = { 3958, 11}, + 0xF01 = { 3969, 10}, + 0xF02 = { 3979, 8}, + 0xF03 = { 3987, 8}, + 0xF04 = { 3995, 8}, + 0xF05 = { 4003, 5}, + 0xF06 = { 4008, 5}, + 0xF07 = { 4013, 5}, + 0xF08 = { 4018, 6}, + 0xF09 = { 4024, 6}, + 0xF0A = { 4030, 4}, + 0xF0B = { 4034, 4}, + 0xF0C = { 4038, 4}, + 0xF0D = { 4042, 3}, + 0xF0E = { 4045, 4}, + 0xF0F = { 4049, 4}, + 0xF10 = { 4053, 7}, + 0xF11 = { 4060, 7}, + 0xF12 = { 4067, 6}, + 0xF13 = { 4073, 6}, + 0xF14 = { 4079, 5}, + 0xF15 = { 4084, 4}, + 0xF16 = { 4088, 5}, + 0xF17 = { 4093, 5}, + 0xF18 = { 4098, 5}, + 0xF19 = { 4103, 4}, + 0xF1A = { 4107, 4}, + 0xF1B = { 4111, 5}, + 0xF1C = { 4116, 5}, + 0xF1D = { 4121, 4}, + 0xF1E = { 4125, 4}, + 0xF1F = { 4129, 4}, + 0xF20 = { 4133, 5}, + 0xF21 = { 4138, 4}, + 0xF22 = { 4142, 4}, + 0xF23 = { 4146, 4}, + 0xF24 = { 4150, 5}, + 0xF25 = { 4155, 3}, + 0xF26 = { 4158, 4}, + 0xF27 = { 4162, 4}, + 0xF28 = { 4166, 5}, + 0xF29 = { 4171, 4}, + 0xF2A = { 4175, 4}, + 0xF2B = { 4179, 4}, + 0xF2C = { 4183, 5}, + 0xF2D = { 4188, 3}, + 0xF2E = { 4191, 4}, + 0xF2F = { 4195, 4}, + 0xF30 = { 4199, 6}, + 0xF31 = { 4205, 4}, + 0xF32 = { 4209, 6}, + 0xF33 = { 4215, 4}, + 0xF34 = { 4219, 5}, + 0xF35 = { 4224, 3}, + 0xF36 = { 4227, 6}, + 0xF37 = { 4233, 4}, + 0xF38 = { 4237, 7}, + 0xF39 = { 4244, 4}, + 0xF3A = { 4248, 19}, + 0xF3B = { 4267, 9}, + 0xF3C = { 4276, 5}, + 0xF3D = { 4281, 3}, + 0xF3E = { 4284, 5}, + 0xF3F = { 4289, 4}, + 0xF40 = { 4293, 6}, + 0xF41 = { 4299, 6}, + 0xF42 = { 4305, 5}, + 0xF43 = { 4310, 5}, + 0xF44 = { 4315, 6}, + 0xF45 = { 4321, 5}, + 0xF46 = { 4326, 5}, + 0xF47 = { 4331, 5}, + 0xF48 = { 4336, 6}, + 0xF49 = { 4342, 6}, + 0xF4A = { 4348, 4}, + 0xF4B = { 4352, 4}, + 0xF4C = { 4356, 4}, + 0xF4D = { 4360, 3}, + 0xF4E = { 4363, 4}, + 0xF4F = { 4367, 4}, + 0xF50 = { 4371, 5}, + 0xF51 = { 4376, 5}, + 0xF52 = { 4381, 4}, + 0xF53 = { 4385, 4}, + 0xF54 = { 4389, 5}, + 0xF55 = { 4394, 4}, + 0xF56 = { 4398, 5}, + 0xF57 = { 4403, 5}, + 0xF58 = { 4408, 5}, + 0xF59 = { 4413, 4}, + 0xF5A = { 4417, 4}, + 0xF5B = { 4421, 5}, + 0xF5C = { 4426, 5}, + 0xF5D = { 4431, 4}, + 0xF5E = { 4435, 4}, + 0xF5F = { 4439, 4}, + 0xF60 = { 4443, 5}, + 0xF61 = { 4448, 4}, + 0xF62 = { 4452, 4}, + 0xF63 = { 4456, 4}, + 0xF64 = { 4460, 5}, + 0xF65 = { 4465, 3}, + 0xF66 = { 4468, 4}, + 0xF67 = { 4472, 4}, + 0xF68 = { 4476, 5}, + 0xF69 = { 4481, 4}, + 0xF6A = { 4485, 4}, + 0xF6B = { 4489, 4}, + 0xF6C = { 4493, 5}, + 0xF6D = { 4498, 3}, + 0xF6E = { 4501, 4}, + 0xF6F = { 4505, 4}, + 0xF70 = { 4509, 5}, + 0xF71 = { 4514, 4}, + 0xF72 = { 4518, 4}, + 0xF73 = { 4522, 4}, + 0xF74 = { 4526, 4}, + 0xF75 = { 4530, 3}, + 0xF76 = { 4533, 4}, + 0xF77 = { 4537, 4}, + 0xF78 = { 4541, 8}, + 0xF79 = { 4549, 4}, + 0xF7A = { 4553, 4}, + 0xF7B = { 4557, 4}, + 0xF7C = { 4561, 4}, + 0xF7D = { 4565, 3}, + 0xF7E = { 4568, 4}, + 0xF7F = { 4572, 5}, + 0xF80 = { 4577, 1}, + 0xF81 = { 4578, 1}, + 0xF82 = { 4579, 1}, + 0xF83 = { 4580, 2}, + 0xF84 = { 4582, 1}, + 0xF85 = { 4583, 2}, + 0xF88 = { 4585, 1}, + 0xF89 = { 4586, 2}, + 0xF8A = { 4588, 1}, + 0xF8B = { 4589, 1}, + 0xF8C = { 4590, 1}, + 0xF8D = { 4591, 2}, + 0xF91 = { 4593, 1}, + 0xF93 = { 4594, 1}, + 0xF99 = { 4595, 2}, + 0xF9B = { 4597, 1}, + 0xFA0 = { 4598, 3}, + 0xFA1 = { 4601, 2}, + 0xFA2 = { 4603, 3}, + 0xFA3 = { 4606, 2}, + 0xFA4 = { 4608, 3}, + 0xFA5 = { 4611, 2}, + 0xFA6 = { 4613, 1}, + 0xFA8 = { 4614, 10}, + 0xFA9 = { 4624, 10}, + 0xFAA = { 4634, 6}, + 0xFAB = { 4640, 1}, + 0xFAC = { 4641, 6}, + 0xFAD = { 4647, 6}, + 0xFAE = { 4653, 6}, + 0xFB0 = { 4659, 3}, + 0xFB5 = { 4662, 1}, + 0xFB8 = { 4663, 1}, + 0xFB9 = { 4664, 1}, + 0xFBA = { 4665, 1}, + 0xFBB = { 4666, 1}, + 0xFBC = { 4667, 1}, + 0xFBE = { 4668, 1}, + 0xFC0 = { 4669, 1}, + 0xFC1 = { 4670, 1}, + 0xFC2 = { 4671, 3}, + 0xFC3 = { 4674, 3}, + 0xFC4 = { 4677, 1}, + 0xFC5 = { 4678, 1}, + 0xFC6 = { 4679, 2}, + 0xFC7 = { 4681, 2}, + 0xFC8 = { 4683, 7}, + 0xFC9 = { 4690, 11}, + 0xFCA = { 4701, 3}, + 0xFCB = { 4704, 3}, + 0xFCC = { 4707, 7}, + 0xFCD = { 4714, 7}, + 0xFCE = { 4721, 2}, + 0xFCF = { 4723, 2}, + 0xFD2 = { 4725, 1}, + 0xFD3 = { 4726, 1}, + 0xFD9 = { 4727, 4}, + 0xFDA = { 4731, 1}, + 0xFDB = { 4732, 1}, + 0xFE0 = { 4733, 28}, + 0xFE1 = { 4761, 26}, + 0xFE2 = { 4787, 26}, + 0xFE3 = { 4813, 32}, + 0xFE4 = { 4845, 29}, + 0xFE5 = { 4874, 27}, + 0xFE6 = { 4901, 27}, + 0xFE7 = { 4928, 33}, + 0xFE8 = { 4961, 32}, + 0xFE9 = { 4993, 17}, + 0xFEA = { 5010, 17}, + 0xFEB = { 5027, 29}, + 0xFEC = { 5056, 31}, + 0xFED = { 5087, 18}, + 0xFEE = { 5105, 26}, + 0xFEF = { 5131, 32}, + 0xFF0 = { 5163, 19}, + 0xFF1 = { 5182, 18}, + 0xFF2 = { 5200, 17}, + 0xFF3 = { 5217, 17}, + 0xFF4 = { 5234, 19}, + 0xFF5 = { 5253, 18}, + 0xFF6 = { 5271, 17}, + 0xFF7 = { 5288, 17}, + 0xFF8 = { 5305, 4}, + 0xFF9 = { 5309, 4}, + 0xFFA = { 5313, 4}, + 0xFFB = { 5317, 17}, + 0xFFC = { 5334, 4}, + 0xFFD = { 5338, 4}, + 0xFFE = { 5342, 4}, + 0xFFF = { 5346, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index b6f98c6fc..f8d26009b 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1649]lib.Encoding{ +ENCODE_FORMS := [1663]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -171,14 +171,14 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSR - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ASR - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT_32,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, @@ -286,14 +286,14 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSAT16 { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT16 - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5_U,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_U_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1065,16 +1065,30 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} }, // .VCVTB { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, @@ -1838,33 +1852,33 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .AESE - { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, // .AESD - { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, // .AESMC - { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, // .AESIMC - { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, // .SHA1H - { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA1SU0 - { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA1SU1 - { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA1C - { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA1M - { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA1P - { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA256H - { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA256H2 - { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA256SU0 - { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .SHA256SU1 - { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, + { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .VJCVT { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, // .VSDOT @@ -2521,314 +2535,314 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .VSQRT = { 754, 3}, .VCMP = { 757, 8}, .VCMPE = { 765, 4}, - .VCVT = { 769, 21}, - .VCVTB = { 790, 2}, - .VCVTT = { 792, 2}, - .VCVTA = { 794, 2}, - .VCVTN = { 796, 2}, - .VCVTP = { 798, 2}, - .VCVTM = { 800, 2}, - .VCVTR = { 802, 4}, - .VMOV = { 806, 33}, - .VMRS = { 839, 1}, - .VMSR = { 840, 1}, - .VLDR = { 841, 2}, - .VSTR = { 843, 2}, - .VLDM = { 845, 2}, - .VSTM = { 847, 2}, - .VPUSH = { 849, 2}, - .VPOP = { 851, 2}, - .VSEL = { 853, 2}, - .VMAXNM = { 855, 2}, - .VMINNM = { 857, 2}, - .VRINTA = { 859, 3}, - .VRINTN = { 862, 3}, - .VRINTP = { 865, 3}, - .VRINTM = { 868, 3}, - .VRINTR = { 871, 2}, - .VRINTZ = { 873, 3}, - .VRINTX = { 876, 3}, - .VADDL = { 879, 6}, - .VADDW = { 885, 6}, - .VSUBL = { 891, 6}, - .VSUBW = { 897, 6}, - .VHADD = { 903, 9}, - .VHSUB = { 912, 9}, - .VRHADD = { 921, 3}, - .VQADD = { 924, 11}, - .VQSUB = { 935, 11}, - .VMULL = { 946, 11}, - .VMLAL = { 957, 10}, - .VMLSL = { 967, 10}, - .VQDMULL = { 977, 4}, - .VQDMLAL = { 981, 4}, - .VQDMLSL = { 985, 4}, - .VQDMULH = { 989, 8}, - .VQRDMULH = { 997, 8}, - .VQRDMLAH = { 1005, 8}, - .VQRDMLSH = { 1013, 8}, - .VABA = { 1021, 8}, - .VABAL = { 1029, 6}, - .VABD = { 1035, 10}, - .VABDL = { 1045, 6}, - .VAND = { 1051, 3}, - .VBIC = { 1054, 3}, - .VORR = { 1057, 3}, - .VORN = { 1060, 3}, - .VEOR = { 1063, 3}, - .VBSL = { 1066, 2}, - .VBIT = { 1068, 2}, - .VBIF = { 1070, 2}, - .VMVN = { 1072, 13}, - .VMOVN = { 1085, 3}, - .VQMOVN = { 1088, 6}, - .VQMOVUN = { 1094, 3}, - .VMOVL = { 1097, 6}, - .VTST = { 1103, 6}, - .VCEQ = { 1109, 14}, - .VCGE = { 1123, 16}, - .VCGT = { 1139, 16}, - .VCLE = { 1155, 18}, - .VCLT = { 1173, 18}, - .VACGE = { 1191, 2}, - .VACGT = { 1193, 2}, - .VACLE = { 1195, 2}, - .VACLT = { 1197, 2}, - .VMAX = { 1199, 13}, - .VMIN = { 1212, 13}, - .VPMAX = { 1225, 5}, - .VPMIN = { 1230, 5}, - .VPADD = { 1235, 5}, - .VPADDL = { 1240, 6}, - .VPADAL = { 1246, 4}, - .VRECPE = { 1250, 4}, - .VRECPS = { 1254, 2}, - .VRSQRTE = { 1256, 4}, - .VRSQRTS = { 1260, 2}, - .VSHL = { 1262, 9}, - .VSHR = { 1271, 3}, - .VSRA = { 1274, 3}, - .VRSHL = { 1277, 5}, - .VRSHR = { 1282, 3}, - .VRSRA = { 1285, 2}, - .VSLI = { 1287, 2}, - .VSRI = { 1289, 2}, - .VQSHL = { 1291, 7}, - .VQSHRN = { 1298, 1}, - .VQSHRUN = { 1299, 1}, - .VQRSHL = { 1300, 16}, - .VQRSHRN = { 1316, 1}, - .VQRSHRUN = { 1317, 1}, - .VSHRN = { 1318, 1}, - .VRSHRN = { 1319, 1}, - .VSHLL = { 1320, 4}, - .VCLS = { 1324, 6}, - .VCLZ = { 1330, 6}, - .VCNT = { 1336, 2}, - .VREV16 = { 1338, 2}, - .VREV32 = { 1340, 4}, - .VREV64 = { 1344, 6}, - .VEXT = { 1350, 2}, - .VTBL = { 1352, 4}, - .VTBX = { 1356, 4}, - .VTRN = { 1360, 6}, - .VUZP = { 1366, 5}, - .VZIP = { 1371, 5}, - .VDUP = { 1376, 5}, - .VSWP = { 1381, 2}, - .VLD1 = { 1383, 8}, - .VLD2 = { 1391, 6}, - .VLD3 = { 1397, 5}, - .VLD4 = { 1402, 5}, - .VST1 = { 1407, 7}, - .VST2 = { 1414, 6}, - .VST3 = { 1420, 5}, - .VST4 = { 1425, 5}, - .AESE = { 1430, 1}, - .AESD = { 1431, 1}, - .AESMC = { 1432, 1}, - .AESIMC = { 1433, 1}, - .SHA1H = { 1434, 1}, - .SHA1SU0 = { 1435, 1}, - .SHA1SU1 = { 1436, 1}, - .SHA1C = { 1437, 1}, - .SHA1M = { 1438, 1}, - .SHA1P = { 1439, 1}, - .SHA256H = { 1440, 1}, - .SHA256H2 = { 1441, 1}, - .SHA256SU0 = { 1442, 1}, - .SHA256SU1 = { 1443, 1}, - .VJCVT = { 1444, 1}, - .VSDOT = { 1445, 4}, - .VUDOT = { 1449, 4}, - .VDOT = { 1453, 2}, - .VMMLA = { 1455, 1}, - .VFMAL = { 1456, 2}, - .VFMSL = { 1458, 2}, - .VCMLA = { 1460, 5}, - .VCADD = { 1465, 2}, - .VSMMLA = { 1467, 1}, - .VUMMLA = { 1468, 1}, - .VUSMMLA = { 1469, 1}, - .VSUDOT = { 1470, 2}, - .VUSDOT = { 1472, 4}, - .VQABS = { 1476, 1}, - .VQNEG = { 1477, 1}, - .VMOVX = { 1478, 1}, - .VINS = { 1479, 1}, - .VLD2R = { 1480, 1}, - .VLD3R = { 1481, 1}, - .VLD4R = { 1482, 1}, - .IT = { 1483, 1}, - .TT = { 1484, 1}, - .TTT = { 1485, 1}, - .TTA = { 1486, 1}, - .TTAT = { 1487, 1}, - .SG = { 1488, 1}, - .BXNS = { 1489, 1}, - .BLXNS = { 1490, 1}, - .PAC = { 1491, 1}, - .PACBTI = { 1492, 1}, - .AUT = { 1493, 1}, - .AUTG = { 1494, 1}, - .BTI = { 1495, 1}, - .WLS = { 1496, 1}, - .WLSTP = { 1497, 1}, - .DLS = { 1498, 1}, - .DLSTP = { 1499, 1}, - .LE = { 1500, 1}, - .LETP = { 1501, 1}, - .LCTP = { 1502, 1}, - .BF = { 1503, 1}, - .BFX = { 1504, 1}, - .BFL = { 1505, 1}, - .BFLX = { 1506, 1}, - .BFCSEL = { 1507, 1}, - .CX1 = { 1508, 1}, - .CX1A = { 1509, 1}, - .CX1D = { 1510, 1}, - .CX1DA = { 1511, 1}, - .CX2 = { 1512, 1}, - .CX2A = { 1513, 1}, - .CX2D = { 1514, 1}, - .CX2DA = { 1515, 1}, - .CX3 = { 1516, 1}, - .CX3A = { 1517, 1}, - .CX3D = { 1518, 1}, - .CX3DA = { 1519, 1}, - .VCX1 = { 1520, 2}, - .VCX1A = { 1522, 2}, - .VCX2 = { 1524, 2}, - .VCX2A = { 1526, 2}, - .VCX3 = { 1528, 2}, - .VCX3A = { 1530, 2}, - .VPT = { 1532, 1}, - .VPST = { 1533, 1}, - .VPSEL = { 1534, 1}, - .VPNOT = { 1535, 1}, - .VCTP = { 1536, 1}, - .VADDV = { 1537, 1}, - .VADDVA = { 1538, 1}, - .VADDLV = { 1539, 1}, - .VADDLVA = { 1540, 1}, - .VMAXV = { 1541, 1}, - .VMAXAV = { 1542, 1}, - .VMINV = { 1543, 1}, - .VMINAV = { 1544, 1}, - .VMAXNMV = { 1545, 1}, - .VMAXNMAV = { 1546, 1}, - .VMINNMV = { 1547, 1}, - .VMINNMAV = { 1548, 1}, - .VABAV = { 1549, 1}, - .VMLADAV = { 1550, 1}, - .VMLADAVA = { 1551, 1}, - .VMLADAVX = { 1552, 1}, - .VMLADAVAX = { 1553, 1}, - .VMLALDAV = { 1554, 1}, - .VMLALDAVA = { 1555, 1}, - .VMLALDAVX = { 1556, 1}, - .VMLALDAVAX = { 1557, 1}, - .VMLSDAV = { 1558, 1}, - .VMLSDAVA = { 1559, 1}, - .VMLSDAVX = { 1560, 1}, - .VMLSDAVAX = { 1561, 1}, - .VMLSLDAV = { 1562, 1}, - .VMLSLDAVA = { 1563, 1}, - .VMLSLDAVX = { 1564, 1}, - .VMLSLDAVAX = { 1565, 1}, - .VRMLALDAVH = { 1566, 1}, - .VRMLALDAVHA = { 1567, 1}, - .VRMLALDAVHX = { 1568, 1}, - .VRMLALDAVHAX = { 1569, 1}, - .VRMLSLDAVH = { 1570, 1}, - .VRMLSLDAVHA = { 1571, 1}, - .VRMLSLDAVHX = { 1572, 1}, - .VRMLSLDAVHAX = { 1573, 1}, - .VMLAV = { 1574, 1}, - .VMLAVA = { 1575, 1}, - .VMLSV = { 1576, 1}, - .VMLSVA = { 1577, 1}, - .VCMUL = { 1578, 1}, - .VHCADD = { 1579, 2}, - .VBRSR = { 1581, 1}, - .VSHLC = { 1582, 1}, - .VDDUP = { 1583, 1}, - .VIDUP = { 1584, 1}, - .VDWDUP = { 1585, 1}, - .VIWDUP = { 1586, 1}, - .VMOVNB = { 1587, 1}, - .VMOVNT = { 1588, 1}, - .VQMOVNB = { 1589, 1}, - .VQMOVNT = { 1590, 1}, - .VQMOVUNB = { 1591, 1}, - .VQMOVUNT = { 1592, 1}, - .VSHLLB = { 1593, 1}, - .VSHLLT = { 1594, 1}, - .VMULLB = { 1595, 1}, - .VMULLT = { 1596, 1}, - .VMLALB = { 1597, 1}, - .VMLALT = { 1598, 1}, - .VMLSLB = { 1599, 1}, - .VMLSLT = { 1600, 1}, - .VSHRNB = { 1601, 1}, - .VSHRNT = { 1602, 1}, - .VRSHRNB = { 1603, 1}, - .VRSHRNT = { 1604, 1}, - .VQSHRNB = { 1605, 1}, - .VQSHRNT = { 1606, 1}, - .VQRSHRNB = { 1607, 1}, - .VQRSHRNT = { 1608, 1}, - .VQSHRUNB = { 1609, 1}, - .VQSHRUNT = { 1610, 1}, - .VQRSHRUNB = { 1611, 1}, - .VQRSHRUNT = { 1612, 1}, - .VQDMLADH = { 1613, 1}, - .VQDMLADHX = { 1614, 1}, - .VQDMLSDH = { 1615, 1}, - .VQDMLSDHX = { 1616, 1}, - .VQRDMLADH = { 1617, 1}, - .VQRDMLADHX = { 1618, 1}, - .VQRDMLSDH = { 1619, 1}, - .VQRDMLSDHX = { 1620, 1}, - .VLDRB = { 1621, 2}, - .VLDRH = { 1623, 2}, - .VLDRW = { 1625, 2}, - .VLDRD = { 1627, 2}, - .VSTRB = { 1629, 2}, - .VSTRH = { 1631, 2}, - .VSTRW = { 1633, 2}, - .VSTRD = { 1635, 2}, - .VLD20 = { 1637, 1}, - .VLD21 = { 1638, 1}, - .VLD40 = { 1639, 1}, - .VLD41 = { 1640, 1}, - .VLD42 = { 1641, 1}, - .VLD43 = { 1642, 1}, - .VST20 = { 1643, 1}, - .VST21 = { 1644, 1}, - .VST40 = { 1645, 1}, - .VST41 = { 1646, 1}, - .VST42 = { 1647, 1}, - .VST43 = { 1648, 1}, - ._COUNT = { 1649, 0}, + .VCVT = { 769, 35}, + .VCVTB = { 804, 2}, + .VCVTT = { 806, 2}, + .VCVTA = { 808, 2}, + .VCVTN = { 810, 2}, + .VCVTP = { 812, 2}, + .VCVTM = { 814, 2}, + .VCVTR = { 816, 4}, + .VMOV = { 820, 33}, + .VMRS = { 853, 1}, + .VMSR = { 854, 1}, + .VLDR = { 855, 2}, + .VSTR = { 857, 2}, + .VLDM = { 859, 2}, + .VSTM = { 861, 2}, + .VPUSH = { 863, 2}, + .VPOP = { 865, 2}, + .VSEL = { 867, 2}, + .VMAXNM = { 869, 2}, + .VMINNM = { 871, 2}, + .VRINTA = { 873, 3}, + .VRINTN = { 876, 3}, + .VRINTP = { 879, 3}, + .VRINTM = { 882, 3}, + .VRINTR = { 885, 2}, + .VRINTZ = { 887, 3}, + .VRINTX = { 890, 3}, + .VADDL = { 893, 6}, + .VADDW = { 899, 6}, + .VSUBL = { 905, 6}, + .VSUBW = { 911, 6}, + .VHADD = { 917, 9}, + .VHSUB = { 926, 9}, + .VRHADD = { 935, 3}, + .VQADD = { 938, 11}, + .VQSUB = { 949, 11}, + .VMULL = { 960, 11}, + .VMLAL = { 971, 10}, + .VMLSL = { 981, 10}, + .VQDMULL = { 991, 4}, + .VQDMLAL = { 995, 4}, + .VQDMLSL = { 999, 4}, + .VQDMULH = { 1003, 8}, + .VQRDMULH = { 1011, 8}, + .VQRDMLAH = { 1019, 8}, + .VQRDMLSH = { 1027, 8}, + .VABA = { 1035, 8}, + .VABAL = { 1043, 6}, + .VABD = { 1049, 10}, + .VABDL = { 1059, 6}, + .VAND = { 1065, 3}, + .VBIC = { 1068, 3}, + .VORR = { 1071, 3}, + .VORN = { 1074, 3}, + .VEOR = { 1077, 3}, + .VBSL = { 1080, 2}, + .VBIT = { 1082, 2}, + .VBIF = { 1084, 2}, + .VMVN = { 1086, 13}, + .VMOVN = { 1099, 3}, + .VQMOVN = { 1102, 6}, + .VQMOVUN = { 1108, 3}, + .VMOVL = { 1111, 6}, + .VTST = { 1117, 6}, + .VCEQ = { 1123, 14}, + .VCGE = { 1137, 16}, + .VCGT = { 1153, 16}, + .VCLE = { 1169, 18}, + .VCLT = { 1187, 18}, + .VACGE = { 1205, 2}, + .VACGT = { 1207, 2}, + .VACLE = { 1209, 2}, + .VACLT = { 1211, 2}, + .VMAX = { 1213, 13}, + .VMIN = { 1226, 13}, + .VPMAX = { 1239, 5}, + .VPMIN = { 1244, 5}, + .VPADD = { 1249, 5}, + .VPADDL = { 1254, 6}, + .VPADAL = { 1260, 4}, + .VRECPE = { 1264, 4}, + .VRECPS = { 1268, 2}, + .VRSQRTE = { 1270, 4}, + .VRSQRTS = { 1274, 2}, + .VSHL = { 1276, 9}, + .VSHR = { 1285, 3}, + .VSRA = { 1288, 3}, + .VRSHL = { 1291, 5}, + .VRSHR = { 1296, 3}, + .VRSRA = { 1299, 2}, + .VSLI = { 1301, 2}, + .VSRI = { 1303, 2}, + .VQSHL = { 1305, 7}, + .VQSHRN = { 1312, 1}, + .VQSHRUN = { 1313, 1}, + .VQRSHL = { 1314, 16}, + .VQRSHRN = { 1330, 1}, + .VQRSHRUN = { 1331, 1}, + .VSHRN = { 1332, 1}, + .VRSHRN = { 1333, 1}, + .VSHLL = { 1334, 4}, + .VCLS = { 1338, 6}, + .VCLZ = { 1344, 6}, + .VCNT = { 1350, 2}, + .VREV16 = { 1352, 2}, + .VREV32 = { 1354, 4}, + .VREV64 = { 1358, 6}, + .VEXT = { 1364, 2}, + .VTBL = { 1366, 4}, + .VTBX = { 1370, 4}, + .VTRN = { 1374, 6}, + .VUZP = { 1380, 5}, + .VZIP = { 1385, 5}, + .VDUP = { 1390, 5}, + .VSWP = { 1395, 2}, + .VLD1 = { 1397, 8}, + .VLD2 = { 1405, 6}, + .VLD3 = { 1411, 5}, + .VLD4 = { 1416, 5}, + .VST1 = { 1421, 7}, + .VST2 = { 1428, 6}, + .VST3 = { 1434, 5}, + .VST4 = { 1439, 5}, + .AESE = { 1444, 1}, + .AESD = { 1445, 1}, + .AESMC = { 1446, 1}, + .AESIMC = { 1447, 1}, + .SHA1H = { 1448, 1}, + .SHA1SU0 = { 1449, 1}, + .SHA1SU1 = { 1450, 1}, + .SHA1C = { 1451, 1}, + .SHA1M = { 1452, 1}, + .SHA1P = { 1453, 1}, + .SHA256H = { 1454, 1}, + .SHA256H2 = { 1455, 1}, + .SHA256SU0 = { 1456, 1}, + .SHA256SU1 = { 1457, 1}, + .VJCVT = { 1458, 1}, + .VSDOT = { 1459, 4}, + .VUDOT = { 1463, 4}, + .VDOT = { 1467, 2}, + .VMMLA = { 1469, 1}, + .VFMAL = { 1470, 2}, + .VFMSL = { 1472, 2}, + .VCMLA = { 1474, 5}, + .VCADD = { 1479, 2}, + .VSMMLA = { 1481, 1}, + .VUMMLA = { 1482, 1}, + .VUSMMLA = { 1483, 1}, + .VSUDOT = { 1484, 2}, + .VUSDOT = { 1486, 4}, + .VQABS = { 1490, 1}, + .VQNEG = { 1491, 1}, + .VMOVX = { 1492, 1}, + .VINS = { 1493, 1}, + .VLD2R = { 1494, 1}, + .VLD3R = { 1495, 1}, + .VLD4R = { 1496, 1}, + .IT = { 1497, 1}, + .TT = { 1498, 1}, + .TTT = { 1499, 1}, + .TTA = { 1500, 1}, + .TTAT = { 1501, 1}, + .SG = { 1502, 1}, + .BXNS = { 1503, 1}, + .BLXNS = { 1504, 1}, + .PAC = { 1505, 1}, + .PACBTI = { 1506, 1}, + .AUT = { 1507, 1}, + .AUTG = { 1508, 1}, + .BTI = { 1509, 1}, + .WLS = { 1510, 1}, + .WLSTP = { 1511, 1}, + .DLS = { 1512, 1}, + .DLSTP = { 1513, 1}, + .LE = { 1514, 1}, + .LETP = { 1515, 1}, + .LCTP = { 1516, 1}, + .BF = { 1517, 1}, + .BFX = { 1518, 1}, + .BFL = { 1519, 1}, + .BFLX = { 1520, 1}, + .BFCSEL = { 1521, 1}, + .CX1 = { 1522, 1}, + .CX1A = { 1523, 1}, + .CX1D = { 1524, 1}, + .CX1DA = { 1525, 1}, + .CX2 = { 1526, 1}, + .CX2A = { 1527, 1}, + .CX2D = { 1528, 1}, + .CX2DA = { 1529, 1}, + .CX3 = { 1530, 1}, + .CX3A = { 1531, 1}, + .CX3D = { 1532, 1}, + .CX3DA = { 1533, 1}, + .VCX1 = { 1534, 2}, + .VCX1A = { 1536, 2}, + .VCX2 = { 1538, 2}, + .VCX2A = { 1540, 2}, + .VCX3 = { 1542, 2}, + .VCX3A = { 1544, 2}, + .VPT = { 1546, 1}, + .VPST = { 1547, 1}, + .VPSEL = { 1548, 1}, + .VPNOT = { 1549, 1}, + .VCTP = { 1550, 1}, + .VADDV = { 1551, 1}, + .VADDVA = { 1552, 1}, + .VADDLV = { 1553, 1}, + .VADDLVA = { 1554, 1}, + .VMAXV = { 1555, 1}, + .VMAXAV = { 1556, 1}, + .VMINV = { 1557, 1}, + .VMINAV = { 1558, 1}, + .VMAXNMV = { 1559, 1}, + .VMAXNMAV = { 1560, 1}, + .VMINNMV = { 1561, 1}, + .VMINNMAV = { 1562, 1}, + .VABAV = { 1563, 1}, + .VMLADAV = { 1564, 1}, + .VMLADAVA = { 1565, 1}, + .VMLADAVX = { 1566, 1}, + .VMLADAVAX = { 1567, 1}, + .VMLALDAV = { 1568, 1}, + .VMLALDAVA = { 1569, 1}, + .VMLALDAVX = { 1570, 1}, + .VMLALDAVAX = { 1571, 1}, + .VMLSDAV = { 1572, 1}, + .VMLSDAVA = { 1573, 1}, + .VMLSDAVX = { 1574, 1}, + .VMLSDAVAX = { 1575, 1}, + .VMLSLDAV = { 1576, 1}, + .VMLSLDAVA = { 1577, 1}, + .VMLSLDAVX = { 1578, 1}, + .VMLSLDAVAX = { 1579, 1}, + .VRMLALDAVH = { 1580, 1}, + .VRMLALDAVHA = { 1581, 1}, + .VRMLALDAVHX = { 1582, 1}, + .VRMLALDAVHAX = { 1583, 1}, + .VRMLSLDAVH = { 1584, 1}, + .VRMLSLDAVHA = { 1585, 1}, + .VRMLSLDAVHX = { 1586, 1}, + .VRMLSLDAVHAX = { 1587, 1}, + .VMLAV = { 1588, 1}, + .VMLAVA = { 1589, 1}, + .VMLSV = { 1590, 1}, + .VMLSVA = { 1591, 1}, + .VCMUL = { 1592, 1}, + .VHCADD = { 1593, 2}, + .VBRSR = { 1595, 1}, + .VSHLC = { 1596, 1}, + .VDDUP = { 1597, 1}, + .VIDUP = { 1598, 1}, + .VDWDUP = { 1599, 1}, + .VIWDUP = { 1600, 1}, + .VMOVNB = { 1601, 1}, + .VMOVNT = { 1602, 1}, + .VQMOVNB = { 1603, 1}, + .VQMOVNT = { 1604, 1}, + .VQMOVUNB = { 1605, 1}, + .VQMOVUNT = { 1606, 1}, + .VSHLLB = { 1607, 1}, + .VSHLLT = { 1608, 1}, + .VMULLB = { 1609, 1}, + .VMULLT = { 1610, 1}, + .VMLALB = { 1611, 1}, + .VMLALT = { 1612, 1}, + .VMLSLB = { 1613, 1}, + .VMLSLT = { 1614, 1}, + .VSHRNB = { 1615, 1}, + .VSHRNT = { 1616, 1}, + .VRSHRNB = { 1617, 1}, + .VRSHRNT = { 1618, 1}, + .VQSHRNB = { 1619, 1}, + .VQSHRNT = { 1620, 1}, + .VQRSHRNB = { 1621, 1}, + .VQRSHRNT = { 1622, 1}, + .VQSHRUNB = { 1623, 1}, + .VQSHRUNT = { 1624, 1}, + .VQRSHRUNB = { 1625, 1}, + .VQRSHRUNT = { 1626, 1}, + .VQDMLADH = { 1627, 1}, + .VQDMLADHX = { 1628, 1}, + .VQDMLSDH = { 1629, 1}, + .VQDMLSDHX = { 1630, 1}, + .VQRDMLADH = { 1631, 1}, + .VQRDMLADHX = { 1632, 1}, + .VQRDMLSDH = { 1633, 1}, + .VQRDMLSDHX = { 1634, 1}, + .VLDRB = { 1635, 2}, + .VLDRH = { 1637, 2}, + .VLDRW = { 1639, 2}, + .VLDRD = { 1641, 2}, + .VSTRB = { 1643, 2}, + .VSTRH = { 1645, 2}, + .VSTRW = { 1647, 2}, + .VSTRD = { 1649, 2}, + .VLD20 = { 1651, 1}, + .VLD21 = { 1652, 1}, + .VLD40 = { 1653, 1}, + .VLD41 = { 1654, 1}, + .VLD42 = { 1655, 1}, + .VLD43 = { 1656, 1}, + .VST20 = { 1657, 1}, + .VST21 = { 1658, 1}, + .VST40 = { 1659, 1}, + .VST41 = { 1660, 1}, + .VST42 = { 1661, 1}, + .VST43 = { 1662, 1}, + ._COUNT = { 1663, 0}, } diff --git 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zuUbo(moeW3-OS73ZswJ+in$m5>#V_3>8vOF%5$l2WPYHcKj=-;(_U7uc?}x!iaN@C zp7|<-eo<|HK}-C4_4=Of^PL{{^Ll}Kz;Dp|epVxXpwn;>E<-8^G!dpkJIoIf>Vn0v z6uMyrtb*0BHmFm7FhLImHF^Y|gzZ6Ti9oP-;^4<_R410rW?T16$ zIRYnm=PRCnO`e4d@H2fBE-_z$Ys|59QdLl!u98nWXn-8OF`ZBg^E8-FpGCGq2XxZs zv0uQv2$rT(T0!=Z>&Ol4H?qHo1Mp^8qd{^H z48bt$W&Z)WpLY+0F&%_Ma5#)>g#45oJ4fh8>7SFw;5eM9*q82|;#ui@QO>_h#Xnz` z@1GuLe}@0dH|)P9zbDU;Kaf9`@BS1{&~I=(OeyJNs&XmSK?tRjb%~0f^v{^%-q^`A z7oZ4}p%F@_shrJZ3ryiV)1Z}kI?Ql!&4gL5T60~U?qs(R7SX$*huvxzJNNL;S{U!F zbNpSh>l%RU73sHELE@)TI6>)K=IY74>%1s81rNQ&CQ% n?1D_BmW Date: Sat, 29 Aug 2026 00:46:58 -0400 Subject: [PATCH 62/89] rexcode/arm32: operands that no field carries, and three forms with the wrong shape VSHLL's widest form shifts by exactly the element size. No field holds that amount -- the size is a fixed bit of the form, so the shift is too -- and the form printed no shift at all, which reads as a different instruction. VCADD and VCMLA name their rotation in degrees, 90 and 270 for one and all four quadrants for the other; both printed the raw field, so every rotation read as `#0`. VSEL is an unconditional word that still names a condition, in bits 21:20 and spelled on the mnemonic; it printed a bare `#0` operand instead and no condition. Only four conditions can be named and not in their usual order, so they get a small table. The shift amount had five bits, which cannot hold 32 -- the amount LSR and ASR reach through a zero field. It silently wrapped back to zero, which is why the previous commit's fix for those did not take. Memory had a spare bit and the register operand had two. Three forms were shaped wrong outright. VDUP from a GPR puts Vd in bits 19:16 with D at bit 7, not where NEON usually puts it, so it named a register sixteen too high. VCVTA, VCVTN, VCVTP and VCVTM to a 32-bit integer land in an S register whatever the source width, and the F64 forms had them landing in a D. VFMAL and VFMSL multiply pairs of half-precision values, so their sources are half the width of the destination -- S registers into a D, D registers into a Q -- and they carried no data type at all. VJCVT likewise: it converts F64 to a signed 32-bit integer. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 14 +++++- core/rexcode/isa/arm32/encoder.odin | 6 +++ core/rexcode/isa/arm32/encoding_types.odin | 10 +++- core/rexcode/isa/arm32/mnemonic_builders.odin | 30 ++++++------ core/rexcode/isa/arm32/operands.odin | 7 ++- .../isa/arm32/tablegen/encoding_table.odin | 44 +++++++++--------- .../tablegen/generated/decode_tables.odin | 44 +++++++++--------- .../tablegen/generated/encode_tables.odin | 44 +++++++++--------- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38249 -> 38249 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38249 -> 38249 bytes 10 files changed, 111 insertions(+), 88 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 4ef390294..3f3d710c8 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -157,7 +157,10 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in inst.dt = e.dt // Cond: A32 entries with bits[31:28] variable in mask take cond from word - if mode == .A32 && (e.mask >> 28) == 0 { + if e.flags.cond_in_21 { + // Four conditions only, and not in their usual order. + inst.cond = VSEL_CONDITIONS[(word >> 20) & 3] + } else if mode == .A32 && (e.mask >> 28) == 0 { inst.cond = u8((word >> 28) & 0xF) } else { inst.cond = 14 // AL / unconditional @@ -547,6 +550,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op return op_imm(i64((word >> 18) & 0xF)) // ---- Saturate / bit field ---- + case .NEON_SHLL_8: return op_imm(8) + case .NEON_SHLL_16: return op_imm(16) + case .NEON_SHLL_32: return op_imm(32) + case .NEON_ROT_2: return op_imm(((word >> 24) & 1) != 0 ? 270 : 90) + case .NEON_ROT_4: return op_imm(i64(((word >> 20) & 3) * 90)) case .VFP_FBITS: // The fixed-point width is 16 or 32 by the sx bit, and the fraction // is that less imm4:i -- so the widest fraction encodes as zero. @@ -678,6 +686,10 @@ table_run_length :: #force_inline proc "contextless" (e: Operand_Encoding) -> u8 return 1 } +// The conditions VSEL can name, in the order bits 21:20 give them. +@(private="file") +VSEL_CONDITIONS := [4]u8{0, 6, 10, 12} // EQ, VS, GE, GT + // Typical-case estimate of the instruction count for `data`. @(require_results) decode_estimate_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int { diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 7d4805bb2..4fc95d9ee 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -661,6 +661,12 @@ pack_operand_inline :: #force_inline proc( case .IT_MASK: return u32(op.immediate) & 0xFF case .CPS_IFLAGS: return u32(op.immediate) & 0x1FF case .HINT_FIELD: return u32(op.immediate) & 0xFF + case .NEON_SHLL_8, .NEON_SHLL_16, .NEON_SHLL_32: + return 0 // the amount is the form's element size; no field carries it + case .NEON_ROT_2: + return (op.immediate == 270 ? u32(1) : 0) << 24 + case .NEON_ROT_4: + return ((u32(op.immediate) / 90) & 3) << 20 case .VFP_FBITS: // sx is a fixed bit of the form, so the width comes from its pattern. width: u32 = ((form.bits >> 7) & 1) != 0 ? 32 : 16 diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 4d7333849..32ca83311 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -156,7 +156,9 @@ Encoding_Flags :: bit_field u8 { writes_pc: bool | 1, thumb32: bool | 1, // T32 32-bit form (vs 16-bit). Ignored for A32. deprecated: bool | 1, - _: u8 | 1, + // VSEL and friends are unconditional words that still name a condition, + // in bits 21:20 rather than 31:28, and spell it on the mnemonic. + cond_in_21: bool | 1, } // ---- Operand types ---------------------------------------------------------- @@ -412,6 +414,12 @@ Operand_Encoding :: enum u8 { // ---- Saturate ---- VFP_FBITS, // VCVT fixed-point fraction bits: width - (imm4:i) + // VSHLL's widest form shifts by exactly the element size, which no field + // carries -- the size is a fixed bit of the form, so the amount is too. + NEON_SHLL_8, NEON_SHLL_16, NEON_SHLL_32, + // Complex-arithmetic rotations, named in degrees. VCADD has two, in bit + // 24; VCMLA has four, in bits 21:20. + NEON_ROT_2, NEON_ROT_4, SAT_IMM5, // bits 20-16: SSAT/SSAT16 saturate-to width, less one SAT_IMM5_T32, // Thumb-2 signed saturate amount, less one SAT_IMM5_U, // bits 20-16: USAT/USAT16 width, which is not biased diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 5e4bdd9a3..87763c9aa 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -758,8 +758,8 @@ inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> In emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) } inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } emit_vpop_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpop_slist(regs)) } -inst_vsel_s_s_s_cond :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vsel_s_s_s_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsel_s_s_s_cond(dst, src, src2, imm)) } +inst_vsel_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsel_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsel_s_s_s(dst, src, src2)) } inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) } inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -959,9 +959,7 @@ emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruc inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) } inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) } -emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) } inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) } inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -1054,10 +1052,10 @@ inst_vdot_d_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_d_d_d(dst, src, src2)) } inst_vmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_q_q_q(dst, src, src2)) } -inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) } -inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } +inst_vfmal_d_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmal_d_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_s_s(dst, src, src2)) } +inst_vfmsl_d_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmsl_d_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_s_s(dst, src, src2)) } inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } inst_vcmla_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } @@ -2001,8 +1999,8 @@ inst_vpush :: inst_vpush_slist emit_vpush :: emit_vpush_slist inst_vpop :: inst_vpop_slist emit_vpop :: emit_vpop_slist -inst_vsel :: inst_vsel_s_s_s_cond -emit_vsel :: emit_vsel_s_s_s_cond +inst_vsel :: inst_vsel_s_s_s +emit_vsel :: emit_vsel_s_s_s inst_vmaxnm :: inst_vmaxnm_s_s_s emit_vmaxnm :: emit_vmaxnm_s_s_s inst_vminnm :: inst_vminnm_s_s_s @@ -2167,8 +2165,8 @@ inst_vshrn :: inst_vshrn_d_q_imm emit_vshrn :: emit_vshrn_d_q_imm inst_vrshrn :: inst_vrshrn_d_q_imm emit_vrshrn :: emit_vrshrn_d_q_imm -inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d } -emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d } +inst_vshll :: inst_vshll_q_d_imm +emit_vshll :: emit_vshll_q_d_imm inst_vcls :: inst_vcls_d_d emit_vcls :: emit_vcls_d_d inst_vclz :: inst_vclz_d_d @@ -2251,10 +2249,10 @@ inst_vdot :: inst_vdot_d_d_d emit_vdot :: emit_vdot_d_d_d inst_vmmla :: inst_vmmla_q_q_q emit_vmmla :: emit_vmmla_q_q_q -inst_vfmal :: inst_vfmal_d_d_d -emit_vfmal :: emit_vfmal_d_d_d -inst_vfmsl :: inst_vfmsl_d_d_d -emit_vfmsl :: emit_vfmsl_d_d_d +inst_vfmal :: inst_vfmal_d_s_s +emit_vfmal :: emit_vfmal_d_s_s +inst_vfmsl :: inst_vfmsl_d_s_s +emit_vfmsl :: emit_vfmsl_d_s_s inst_vcmla :: proc{ inst_vcmla_d_d_d_imm, inst_vcmla_d_d_dlane_imm } emit_vcmla :: proc{ emit_vcmla_d_d_d_imm, emit_vcmla_d_d_dlane_imm } inst_vcadd :: inst_vcadd_d_d_d_imm diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 4914fe0af..2ddab4af4 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -69,11 +69,10 @@ Memory :: bit_field u64 { base: Register | 15, // GPR base register index: Register | 15, // GPR, or Register(0) for imm-only forms shift_type: Shift_Type | 4, - shift_amt: u8 | 5, // 0..31 immediate shift + shift_amt: u8 | 6, // 0..32 -- LSR and ASR reach 32 through a zero field mode: Index_Mode | 2, sign: i8 | 3, // +1 or -1 (U bit) disp: i32 | 19, // immediate displacement (sign-extended) - // 1 bit spare } #assert(size_of(Memory) == 8) @@ -112,12 +111,12 @@ Operand :: struct #packed { using _: bit_field u32 { reg: Register | 15, shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain - shift_amt: u8 | 5, // 0..31, or the Rs index for RSR + shift_amt: u8 | 6, // 0..32, or the Rs index for RSR lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM // Whether `lane` means anything. Lane 0 is a real index -- `d0[0]` // is not `d0` -- so it cannot be spelled by lane == 0. has_lane: bool | 1, - // 2 bits spare + // 1 bit spare }, mem: Memory, immediate: i64, diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 347e0116b..e1b7cb311 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1588,19 +1588,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ARMv8: VCVTA/N/P/M (rounding-mode FP-to-int) - cond=1111 (unconditional class) .VCVTA = { {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, - {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, + {.VCVTA, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTN = { {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, - {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, + {.VCVTN, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTP = { {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, - {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, + {.VCVTP, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTM = { {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, - {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, + {.VCVTM, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, // VMRS / VMSR (access FPSCR + friends as GPR) @@ -1648,8 +1648,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .VSEL = { // VSEL.F32/F64 Sd, Sn, Sm -- cond field at bits 21-20 + 7 - {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, + {.VSEL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false, cond_in_21=true}, {.F32, .NONE}}, + {.VSEL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false, cond_in_21=true}, {.F64, .NONE}}, }, .VRINTA = { {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, @@ -1692,7 +1692,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // VJCVT (ARMv8.3): F64 -> S32 with JS-style rounding - .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {}} }, + .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.S32, .F64}} }, // ---- VFP F16 scalar arithmetic (FEAT_FP16) ---- // Uses coproc 9 (cp_num = 1001) instead of 10/11 used by F32/F64. @@ -2233,8 +2233,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Variant: vector D[lane] form (1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm) // We list the common scalar/Rt form for V_8B/V_16B/V_4H/V_8H/V_2S/V_4S. // (encoder picks based on operand kinds) - {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, + {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, + {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VN_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, // VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, @@ -2548,9 +2548,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHLL_8, .NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHLL_16, .NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHLL_32, .NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm @@ -2753,26 +2753,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCADD: rotation in bit 24 only (2 values: 90, 270 deg) .VCMLA = { // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand - {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VCADD = { // Mask 0xFE800F10 leaves bit 24 variable for rotation operand (90 or 270) - {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NEON_ROT_2}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, // FEAT_FHM (ARMv8.2): FP16 fused multiply-add long .VFMAL = { - {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, - {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMAL, {.DPR, .SPR, .SPR, .NONE}, {.VD_D, .VN_S, .VM_S, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VFMAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, .VFMSL = { - {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, - {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMSL, {.DPR, .SPR, .SPR, .NONE}, {.VD_D, .VN_S, .VM_S, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VFMSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, // FEAT_BF16 (ARMv8.6): BFloat16 arithmetic and conversion diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 9d4c275f7..0e23ed2e7 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -723,9 +723,9 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_32,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_16,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_8,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1010,14 +1010,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .LDC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, - { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VUMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, - { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VFMAL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1027,17 +1027,17 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, - { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_2}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMSL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1050,10 +1050,10 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1115,13 +1115,13 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTA, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, - { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTP, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTM, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, @@ -1193,12 +1193,12 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, + { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.S32,.F64} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, - { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VN_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index f8d26009b..00802981e 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -1097,16 +1097,16 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, // .VCVTA { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTA, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTN { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTP { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTP, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTM { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTM, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTR { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, @@ -1169,8 +1169,8 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSEL - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, // .VMAXNM { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, @@ -1720,9 +1720,9 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_8,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_16,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_32,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCLS { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1788,8 +1788,8 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VDUP - { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VN_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, @@ -1880,7 +1880,7 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .SHA256SU1 { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, // .VJCVT - { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, + { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.S32,.F64} }, // .VSDOT { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, @@ -1897,20 +1897,20 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .VMMLA { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMAL - { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, - { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMAL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, + { .VFMAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, // .VFMSL - { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, - { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMSL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, + { .VFMSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, // .VCMLA - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VCADD - { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_2}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, // .VSMMLA { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VUMMLA diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 3960c23748a4c5fbd4cb7ccdcf30328a53a57293..54ae728c545484b4004272318946daa04ae84cce 100644 GIT binary patch delta 1966 zcmYk7OK%%h7>3_7u@leO$xPaK7^M_DP!nHb)hMMbF(4Jn0+}DsDqAW@qPC$aP2))$ zb4lVfVb~#oMam`{s#tVE1$6|QR$Nlg;)8k?U3io!lD+1tYQv1`}A)Q^X(%OM!3br+~D?6w^Pv%-kZI{gEtRd&N|5kBdM zw)6CWd4eVjdab*uH~q=u6f&BOQA={K+3f84DGw`DRnWJE?c=Cje}BL{7LKSu%DMSM zrt|bq@O0p0ht-QG*FzRkj}HSHS|#0XYd{}TOjT9Xm6tB2PE=^S_5(w=TLuutD@@Z2 zewCe6U;T z(%0fwSve9xn$Cz3N$wl^jrK!8FFvAesmNurwAp3^1RHwA@ zux~rbg@IGm)G&>WiK*WxR*h;pOL$V?->EEObZk*ZSl9yp;o6a^v$|kfRXSh5im3Xt z6W(4hk9I;a`4=0_Y1$%2^3YkUd5yK`CR6b@8>N?9tcMoMq34$|o?tt(i8=R{3)97= z(V@uo64oW$Pna3G-q`XO*^}Hp5Mbx-wGZirDC+jky@YpT0)q;_6z5iIM=RLulfp-N zh|NbN{20ehY1O?eDQr<;n>I)P0)lXM)x9f=32Abehj>QbL|S0k&IGt2+gXmC|GecX P6w8nBu%3AL#jgJWV=39n delta 1966 zcmY+E&2Jk;7{;I3*hzMsWH)WRtWt^{sEK3Os!>WgVn8aC12TU=t6ZrdiQ0yyw28N( zO`LFO!f-)9D@*6;bf&&*CHb8p?a zw{F}@*~a`FAF-3el{o-Yd+^)s9+n0Ufw81(#3(M?$ulCJptKpL56bjP8MU5iY}-9F zju0pMDp!D#vJY$awz5Mk?D}W+iI_JVgM(Ukk=o*-?KqehN8%D69CE$aM7XWO$HVY4 ze{#q@Ns~pp*4?z5;p7Pl8BO+4OM0)_?Cko902@?Qw6~QV;>6|p+e7a0xM>1ee*3wx z&ac0tUk6TgSiN*=J?7;zkB$NsT4mdBTfhJ^%rwn>-FV?r=A=*C_3t~j-*SKiUSgKz zAYbrNCQK6wCner}(e`%_v2+4wsmMV#=kv|;u17OWn>kBW!3^I$zeJ&9XzRQz*WoJ{ zf=Rz}6`JhTCNIhmWgX8li_S2gBiqt!fkBvV zM%TvPmVKv9e;*S%zAdr!Km1V#*T-i+jCt8^z)3U)w&>1L!$DkU7Ng>gxr5yXu$FwC zRp=^Z$8xmW^uA-?YCj+@^?P&(7V<|6wA=K4S>iQ1Pifbby{6eUW#1IGBf1fE`};1? zkDJ1FM0ZJa^S7=IdSsv_R*#GUGM)ziOy6}CA{ENkBL`bPkX**0m7a_)p1ta(@C4W)ml<3JDW?*(R5-cP$z_76H%_KzCY zx_=7snV_Yi^q<*CFMWPSoJ#s1pcw9)FkR7VR^Xz-zv%XUWD^c;o?ae0UCoTr*o2z; zm15JWW^;t675?TWEIx!u?RPGJ0~&!H&~uRwfs>T)>Cgj-}N87R?}Ai diff --git a/core/rexcode/isa/arm32/tables/arm32.entries.bin b/core/rexcode/isa/arm32/tables/arm32.entries.bin index 0d2427859910c06735bf5d93a5d6f5846164fb31..7a831a138112d5f5c132679f734389677977c395 100644 GIT binary patch delta 1863 zcmY+EU1%It6vxk*blv&bbcV!CV`|-r?l$|8*i;h~5!ph0@NFf9Lfc><_MxFQOR-7Q zrrF7tqTOAr7ZH5WJosW%s0{evgI&QFu^(yuXsrc(sZx++X}}l5j_1zo%-rn5vi$z% z{?EPV{_j3ml^(20mzSR^FN2}j57%_NX#lA3CMv1{nSo^}ig+r-hAdQ1hqx%>v#2Tt z{)T^K-oAy|S6+LA+K1w)Q2Zlh?xU5|J`^Vd5e#Y{;!=Q}RJzzn2cns6 zuIaYxP54YOGpF+W$MI+RoX!EXeM1#jc!dVR_+|)y9bh%YXPwc)y$-yvmis0xApwf+#krF z535&8rq54O{be9@g15mZ?dtVbUH?dvz z*USfl6)M8I-oS?I_FxL&d+a0R<79-dAm@n+`~2K}tT>m>|0{LRC8*NcY&05f94&z7 z0J{-1n|(58_AD)sIJrrEe9?cZT4HH|-I(iod1;`Hq<82;U9U3^2A0)5~sUJHq$GY;VIn+iCjS0Ncatzjrje z=)~WpuzRs=QY>9BmZ=~eY=4Dkfua+M{h|0;$@kMLFD>Va@85!VIGO>Ea0stw2g2TLB6(qiim8XKKQnhLZNLikoKXWHA}Hc z^RYWu#AH`Ov0g;*LG$2?QK2&6gAaBEUrM!2>sP-(U#b)&SsL)gu`~EcnF0+a1I~?%*+Z%ls3e{Z#aA-s7>O}SoC-uJ?v!vT!f^?o z#w2YkC$>fX4gbiZeH-(yz4ivR55=>g_(#S(Kr5+zC{6_;7}P$*r2xB`Y_W?DL^Io5 z(^<=#@cCe7?(&PD#GePS^8m2pTdKGsDl`z|3-C7qRwL|=74CQ91^&|LVfs3wD>%ok zBZqO$J$2-&qEr_6(9y>aR?3iudfb6O^*A+vJ%HG4DmyD>gK#Opdjq`SoObH z{ew_USX)K?a%(rO2J&AVP8lt@5m9s4qpo4IdCMv4=$HyKZ zaCY3J??=baMD8n*yLsZZuF!oYba&64cnWFRr7_b6NI+Ax_58EK-xmHftY(o0s{-hd z#Y7@uySK(J#$x0LIeu!Q(EeMU7#F-ssZ;5x!JBDZucY7J*n?IK3`IqHFC8`at8>{M&(_9CECpgG ziD=jzsoJU$Y+$Em0BH z^#(RttzOIk{DA$0e4LK(6%;(R#J`w(fJ^SB`G1w3*%Vb;n~g@J6-Nu;1;8EzZJvKx zF?*ddiBp@@#~1yls->JVzftLa)mfmEliFVDzgSWU*CRYkjxo@@MzCqIHQ#H*$Mf!h zGpai6G;f7zzAdLY!gs?o1B`FO^s?L8j_`ds+uN|nc6J|4gL#<$SJQCOjlV}>_hQ+k zShl=aW`cC^gUccd6rD)iABt}*FX1Bpd--~hh-R3GTjGv`L`3)(>FQa8f0J-M!aqt^ T4}{x^xGrH~!dmX|#gX{`S_0AS From c6f79e8c1b41b5410c7480e560075b5a369c07d8 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:50:19 -0400 Subject: [PATCH 63/89] rexcode/arm32: a flag the table generator dropped, and four more shapes The generator re-emits the encoding table from the typed one, and the routine that writes an entry's flags names them one by one -- so `cond_in_21`, added last commit, survived until the next regeneration and then vanished, taking VSEL's condition with it. Every flag has to be named there; the routine now says so. VCMLA names its rotation twice over. The by-element forms put it in bits 21:20, which is what the previous commit taught it, but the vector forms put it in 24:23 -- so those read every rotation as two quadrants further round than it was. VLDR and VSTR count their offset in words, not bytes, and were sharing the halfword-load encoding, which reads a split imm4H:imm4L field that is not there. They named offsets no VFP load can take. PSB CSYNC and TSB CSYNC are unconditional-only -- the condition field is fixed at AL -- but their entries left bits 31:28 free, so any condition decoded as a conditional PSB. A word with a real condition in it is a plain hint, and that is what it now decodes as. Also gone: the printer's last-resort data type, which guessed `.f32` or `.f64` from the register bank whenever a form gave none. Instructions that take no data type -- VLDR, VSTR, VORN -- got one anyway, and it is not accepted syntax. The table is where a form says what suffix it wants. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 10 +++++ core/rexcode/isa/arm32/encoder.odin | 9 +++- core/rexcode/isa/arm32/encoding_types.odin | 7 ++- core/rexcode/isa/arm32/printer.odin | 25 +++-------- .../isa/arm32/tablegen/encoding_table.odin | 16 +++---- core/rexcode/isa/arm32/tablegen/gen.odin | 3 ++ .../tablegen/generated/decode_tables.odin | 42 +++++++++--------- .../tablegen/generated/encode_tables.odin | 20 ++++----- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38249 -> 38249 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38249 -> 38249 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3326 -> 3326 bytes core/rexcode/isa/arm32/tests/smoke.odin | 4 +- 12 files changed, 72 insertions(+), 64 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 3f3d710c8..9764457bf 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -403,6 +403,15 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op mm := mem_imm(base, disp) if u_bit == 0 { mm.sign = -1 } return op_mem(mm) + case .MEM_IMM8_SCALED4: + // The VFP loads count the offset in words, so the eight bits reach + // +/-1020 rather than +/-255. + base := Register(REG_GPR | u16((word >> 16) & 0xF)) + u_bit := (word >> 23) & 1 + disp := i32(word & 0xFF) * 4 + mm := mem_imm(base, u_bit == 0 ? -disp : disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_IMM8_OFFSET: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 @@ -555,6 +564,7 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op case .NEON_SHLL_32: return op_imm(32) case .NEON_ROT_2: return op_imm(((word >> 24) & 1) != 0 ? 270 : 90) case .NEON_ROT_4: return op_imm(i64(((word >> 20) & 3) * 90)) + case .NEON_ROT_4_HI: return op_imm(i64(((word >> 23) & 3) * 90)) case .VFP_FBITS: // The fixed-point width is 16 or 32 by the sx bit, and the fraction // is that less imm4:i -- so the widest fraction encodes as zero. diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 4fc95d9ee..474dbcea2 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -247,7 +247,7 @@ mem_mode_matches :: #force_inline proc "contextless" (inst: ^Instruction, form: // because R0-as-index is exceedingly rare in real code. has_index := op.mem.index != Register(0) #partial switch form.enc[k] { - case .MEM_IMM12_OFFSET, .MEM_IMM8_OFFSET: + case .MEM_IMM12_OFFSET, .MEM_IMM8_OFFSET, .MEM_IMM8_SCALED4: if m != .OFFSET { return false } if has_index { return false } case .MEM_REG_OFFSET, .MEM_DOUBLEREG: @@ -545,6 +545,11 @@ pack_operand_inline :: #force_inline proc( return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | ((u32(op.list.count) * 2) & 0xFF) // ---- Memory addressing composites -------------------------------------- + case .MEM_IMM8_SCALED4: + m := op.mem + base := (u32(reg_hw(m.base)) & 0xF) << 16 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 + return base | (u_bit << 23) | ((u32(abs_i32(m.disp)) / 4) & 0xFF) case .MEM_IMM12_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 @@ -667,6 +672,8 @@ pack_operand_inline :: #force_inline proc( return (op.immediate == 270 ? u32(1) : 0) << 24 case .NEON_ROT_4: return ((u32(op.immediate) / 90) & 3) << 20 + case .NEON_ROT_4_HI: + return ((u32(op.immediate) / 90) & 3) << 23 case .VFP_FBITS: // sx is a fixed bit of the form, so the width comes from its pattern. width: u32 = ((form.bits >> 7) & 1) != 0 ? 32 : 16 diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 32ca83311..596330d01 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -376,7 +376,8 @@ Operand_Encoding :: enum u8 { RT2_A32_PAIR, MEM_IMM8_PRE_INDEX, MEM_IMM8_POST_INDEX, - MEM_IMM8_OFFSET, // [Rn, #ยฑimm8] (LDRH/STRH/LDRSB/STRD) + MEM_IMM8_OFFSET, + MEM_IMM8_SCALED4, // VFP load/store: imm8 in words, U at bit 23 // [Rn, #ยฑimm8] (LDRH/STRH/LDRSB/STRD) MEM_REG_OFFSET, // [Rn, ยฑRm{, shift}] MEM_PRE_INDEX, // [Rn, #imm]! / [Rn, ยฑRm]! MEM_POST_INDEX, // [Rn], #imm / [Rn], ยฑRm @@ -419,7 +420,9 @@ Operand_Encoding :: enum u8 { NEON_SHLL_8, NEON_SHLL_16, NEON_SHLL_32, // Complex-arithmetic rotations, named in degrees. VCADD has two, in bit // 24; VCMLA has four, in bits 21:20. - NEON_ROT_2, NEON_ROT_4, + // VCMLA names its rotation twice over: the by-element forms put it in + // bits 21:20, the vector forms in 24:23. + NEON_ROT_2, NEON_ROT_4, NEON_ROT_4_HI, SAT_IMM5, // bits 20-16: SSAT/SSAT16 saturate-to width, less one SAT_IMM5_T32, // Thumb-2 signed saturate amount, less one SAT_IMM5_U, // bits 20-16: USAT/USAT16 width, which is not biased diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index e7ac5999d..2100e8e27 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -120,9 +120,11 @@ sbprint :: proc( dt = DECODE_ENTRIES[de_idx].dt } } - if dt[0] == .NONE { - dt_suffix = infer_dt_suffix_from_inst(inst) - } + // No fallback beyond this. Guessing a data type from the register + // bank produced one for every VFP instruction that does not take + // any -- `vldr.f32`, `vorn.f64` -- and those are not accepted + // syntax. If a form needs a suffix, the table is where it says so. + write_mnemonic(sb, inst.mnemonic, inst.cond, inst.sets_flags, opts.uppercase) if dt[0] != .NONE { @@ -208,23 +210,6 @@ infer_dt_suffix :: proc(form: ^Decode_Entry, inst: ^Instruction) -> string { return "" } -@(private="file") -infer_dt_suffix_from_inst :: proc(inst: ^Instruction) -> string { - if inst.operand_count == 0 { return "" } - op0 := &inst.ops[0] - if op0.kind != .REGISTER { return "" } - // A register list leads the load/store-multiple forms -- VPUSH, VPOP and - // friends -- and none of them take a data type. Guessing one from the - // bank produced `vpop.f64 {d0}`, which is not accepted syntax. - if op0.list.count > 0 { return "" } - switch reg_class(op0.reg) { - case REG_SPR: return ".f32" - case REG_DPR: return ".f64" - case REG_QPR: return "" // can't tell integer vs FP from operand alone - } - return "" -} - @(private="file") is_neon_class_op :: proc(form: ^Decode_Entry) -> bool { // NEON A32 unconditional class top byte is F2/F3; T32 is E2/E3 (after bit-28 swap). diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index e1b7cb311..711f2805d 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -916,12 +916,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, // PSB CSYNC (Profiling Synchronization Barrier, FEAT_SPE) -- HINT #17 .PSB_CSYNC = { - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE320F011, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}, {}}, {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // TSB CSYNC (Trace Synchronization Barrier, FEAT_TRF) -- HINT #18 .TSB_CSYNC = { - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE320F012, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}, {}}, {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CSDB (Consumption of Speculative Data Barrier, FEAT_CSV2) -- HINT #20 @@ -1610,12 +1610,12 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VLDR / VSTR (single / double): cond 1101 U D 0 1 Rn Vd 101 sz imm8 .VLDR = { - {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, - {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_SCALED4, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_SCALED4, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, .VSTR = { - {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, - {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_SCALED4, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_SCALED4, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, // VLDM / VSTM (multiple S or D regs): cond 110 P U D W L Rn Vd 101 sz imm8 @@ -2753,8 +2753,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCADD: rotation in bit 24 only (2 values: 90, 270 deg) .VCMLA = { // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand - {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, diff --git a/core/rexcode/isa/arm32/tablegen/gen.odin b/core/rexcode/isa/arm32/tablegen/gen.odin index 617d4a749..7b76018d0 100644 --- a/core/rexcode/isa/arm32/tablegen/gen.odin +++ b/core/rexcode/isa/arm32/tablegen/gen.odin @@ -370,6 +370,9 @@ flags_lit :: proc(f: lib.Encoding_Flags) -> string { if f.writes_pc { append(&parts, "writes_pc=true") } if f.thumb32 { append(&parts, "thumb32=true") } if f.deprecated { append(&parts, "deprecated=true") } + if f.cond_in_21 { append(&parts, "cond_in_21=true") } + // Every flag has to be named here: this is what re-emits the table, so a + // flag left out is a flag silently dropped on the next regeneration. return strings.join(parts[:], ", ", context.temp_allocator) } diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 0e23ed2e7..db52f90ab 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -215,8 +215,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -368,8 +368,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -378,12 +378,12 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -461,8 +461,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -570,6 +570,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE320F011, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE320F012, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, @@ -577,8 +579,6 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, @@ -1016,8 +1016,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VFMAL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1041,10 +1041,10 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1052,8 +1052,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, - { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F64,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1688,9 +1688,9 @@ DECODE_FORM_IDX := [1663]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 3, 9, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, @@ -1698,13 +1698,13 @@ DECODE_FORM_IDX := [1663]u16{ 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 25, 23, 22, 24, 21, 0, 0, 0, 10, 20, - 15, 18, 11, 13, 19, 17, 12, 14, 16, 0, 0, 0, 0, 10, 11, 6, + 3, 3, 0, 3, 0, 3, 25, 22, 23, 24, 21, 0, 0, 0, 10, 20, + 15, 11, 18, 19, 17, 12, 13, 14, 16, 0, 0, 0, 0, 10, 11, 6, 0, 0, 0, 6, 5, 8, 9, 3, 4, 2, 7, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 1, 6, 0, 2, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 8, 2, 2, 7, 2, 7, 1, 3, 1, 3, 1, 3, + 2, 19, 13, 12, 2, 8, 2, 7, 2, 7, 1, 3, 1, 3, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 00802981e..9c4919317 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -616,10 +616,10 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PSB_CSYNC - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE320F011, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TSB_CSYNC - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE320F012, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CSDB { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, @@ -1151,11 +1151,11 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .VMSR { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDR - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSTR - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDM { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1169,8 +1169,8 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSEL - { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, - { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F64,.NONE} }, // .VMAXNM { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, @@ -1903,8 +1903,8 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VFMSL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, { .VFMSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, // .VCMLA - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NEON_ROT_4}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 54ae728c545484b4004272318946daa04ae84cce..d8d4e56583c91a8fc01729f1e935642849e74dea 100644 GIT binary patch delta 3574 zcmY+GTWl0n7{|Y}-EQ~R&Q#lB0z$WirQ5xY7W@*m?QHvpvrR5ch z+RMZ-E-o;|eROe!(u9?b(x69^G_!IciUcczm=c=MG^^|94D79 zuw?@q8o-a2#AXEVLnH>UiNR64G{D&yxEB9=i{UZ6CK;|^?z!l0XE=-AQJ5?tix>_g z*+@@TE2=d@0D(EeVN1MP-Ap#nSj|ghGu=|7;OD`bB@JB)8nsXnXhUenzYm~+0Cc$x zOf>yTOdr-PB|GwqXMadCJDCMbHC>mytaK3XD*(erB4Q8wev-`-w&9i1GWXG~8*TyT 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zuSG7|nJ4jYT`8tZ{CgM9O8kK<#R#~NdDmQ6IMMUQ`ZLSCtdqB%)iPqAlK3Dn96ox7 zmNej;20w@MqXT9y>q94)eFp?_vjd=?g9Q?T01Zz_%c#fp^;f0hw@DH2?qr delta 3491 zcmY+G32aoy8OOibWp}-Y{T`0}ykH`)i48unLueBi7TVn{STqo4NU#@8)a1i>m|d0RL=YfVJ~WfwFizO%t)4l2-hLzjukT1`2Lz=Qje+ zFB%kx)PLna$>$^D=OjU;U^~}?8oHvdYW5WxO*!Hl!LPArjfX>NS_i~{N9=b*N-glPs) z7yGb)*rVBLMbDc%dcfHuWAu@iLhLYaN^0>#2<3;cnX+u04LfLbBu|9nox(LOAWAFd zugliK>oo4HyN@-QYC@_%vQ=T)Eb$c^^GDY=S{_qU{HY`A>owMCytw{7AM4;<8#J^- z8(Pp#Zg`vxoNd+O18|$nW&VRX=gm2PmzDqx@D;6PtixE_I_qa&<)3-71#RZZ36|lB zjV&x=?A%z#kb|c;HKM(`=>@b;Y@R@SbMqSC@uR%?sgeheAEOG&hB9P@eb--cdsw4V~ybk3!J}-8yeR3Q`2&OV5!>^_tYTduIEg_ymAlVQsmI9MogHf;G8)**?LF6QTYmx}fA zc=ZH$tye5wHf&7|PW;k0zuS9_4H@t6Y6-0zs~*P@Nc=9;;qH&L2zP*ECjB2ZOZK|BP9y z>lM22O0?9m;2#cZxM-7#M_lHJl&tXJalCTEDU);3&cm6*SUvl9PWUw+)7Ouu(~UGLe|l~)Ly7${Lq$Qg1Y^jMd>}^z9SA1z zt4BU)+9kq2O*uTw=0a?hh-Fzl(Qbit2d@^DzZzthabfs5wpQF=sc%fpnl~6r5WQsG zV8BT)wl6l|E-yY$O^oPSo*pTSkHnxRW^1hYirG(%~E{F?kOB5B);mw>K%6+>j4Z`d-OK8&G@=EbI)nE&sEC_80@zHUCe zkpA;X|Gb(0RZbT22S-KDAw{Lw;ELNupJ%7|KSr-PnK$od-mgS1IhiN%Z#*fcOZ+4g97bkN2Ik508O@ow7+5CXWc(^G#vslh!63>20bC3s4Ezk-3_=XT41x?i U47`)yGR4g97bkl2F}Uz8O@nl7`P_iWc(^G&LGAh!63>20bC3s4Ezj24BQO748jb8 U3_O$HGR Date: Sat, 29 Aug 2026 01:47:53 -0400 Subject: [PATCH 64/89] rexcode/arm32: modified immediates were decoded and then thrown away The NEON one-register-and-modified-immediate forms -- VMOV, VMVN, VORR and VBIC against a constant -- had no encoding on the value slot at all. The routine that expands an 8-bit field by its cmode was already written and already correct; nothing called it, so twenty-six forms decoded their constant as zero. Printing it back is a second problem. A modified immediate is a bit pattern, and assemblers write it as one: in hex, or as a float when cmode 1111 expanded it into one. Both are operand kinds of their own now, so the VFP `vmov.f32 s0, #2.000000e+00` prints as the float it is rather than as the decimal of its bit pattern. Two more VMOV forms: the one that moves a pair of GPRs to a pair of S registers encodes only the first of the pair, and the second went unprinted rather than being named as the one after it; and the one that moves a 32-bit lane to a GPR names the lane in bit 21, which it did not read, so every lane printed as a bare register. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 15 ++++- core/rexcode/isa/arm32/encoder.odin | 9 ++- core/rexcode/isa/arm32/encoding_types.odin | 4 +- core/rexcode/isa/arm32/operands.odin | 14 +++++ core/rexcode/isa/arm32/printer.odin | 4 ++ .../isa/arm32/tablegen/encoding_table.odin | 58 +++++++++--------- .../tablegen/generated/decode_tables.odin | 58 +++++++++--------- .../tablegen/generated/encode_tables.odin | 58 +++++++++--------- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38249 -> 38249 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38249 -> 38249 bytes 10 files changed, 129 insertions(+), 91 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 9764457bf..893a9d70c 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -451,10 +451,21 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op a := extract_neon_modimm_abcdefgh(word) cmode := (word >> 8) & 0xF op := (word >> 5) & 1 - return op_imm(i64(decode_neon_modimm(a, cmode, op))) + v := decode_neon_modimm(a, cmode, op) + // Only cmode 1111 expands to a float; the rest are bit patterns. + if cmode == 0b1111 { return op_float_imm(v) } + return op_hex_imm(v) + case .VM_S_PLUS1: + // The second of a consecutive pair; only the first is encoded. + return op_reg(Register(REG_SPR | u16(((word & 0xF) << 1 | ((word >> 5) & 1)) + 1))) + case .NEON_LANE_VN_32: + n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF) + return op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> 21) & 1)) case .VFP_IMM8: a := ((word >> 16) & 0xF) << 4 | (word & 0xF) - return op_imm(i64(decode_vfp_imm8_f32(a))) + // Held as the 32-bit pattern whatever the form's width: it is the + // same value either way, and it is what re-encoding needs back. + return op_float_imm(decode_vfp_imm8_f32(a)) case .NEON_D_LIST_1: n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, false) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 474dbcea2..f05dc5e1d 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -314,7 +314,9 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, .IMM_COPROC, .IMM_COPROC_OP, .NEON_IMM, .IMM16_LO_HI: - return op.kind == .IMMEDIATE + // A modified immediate reaches an immediate slot as an expanded bit + // pattern or a float, so all three kinds are the same slot's shape. + return op.kind == .IMMEDIATE || op.kind == .HEX_IMMEDIATE || op.kind == .FLOAT_IMMEDIATE case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .REL_BF: return op.kind == .RELATIVE case .COND: @@ -495,6 +497,11 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0x7) << 17 case .VM_Q_MVE: return (u32(reg_hw(op.reg)) & 0x7) << 1 + case .VM_S_PLUS1: + return 0 // only the first of the pair is encoded + case .NEON_LANE_VN_32: + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 4) & 1) << 7 | (n & 0xF) << 16 | (u32(op.lane) & 1) << 21 case .VFP_IMM8: // Run the VFP 8-bit float encoder; the user supplies the wire-format // 32-bit float bit pattern (for F32). The encoder finds the abcdefgh. diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 596330d01..be4e83b7c 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -324,7 +324,9 @@ Operand_Encoding :: enum u8 { // MVE 3-bit Q registers (Q0..Q7): Qn at bits 19:17, Qm at bits 3:1. VN_Q_MVE, VM_Q_MVE, - VFP_IMM8, // VFP immediate (VMOV.F32/F64 #imm) + VFP_IMM8, + VM_S_PLUS1, // the second S register of a consecutive pair + NEON_LANE_VN_32, // Vn:N with the 32-bit lane index in bit 21 // VFP immediate (VMOV.F32/F64 #imm) NEON_IMM8_ABCDEFGH, // bits 18-16 (abc) + bits 3-0 (defgh) NEON_CMODE, // bits 11-8 (cmode for VMOV/VMVN immediate) NEON_OP_BIT, // bit 5 (op for VMOV immediate variant) diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 2ddab4af4..0a68f1bf1 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -31,6 +31,12 @@ Operand_Kind :: enum u8 { MEMORY, RELATIVE, REG_LIST, // LDM/STM/PUSH/POP bitmask (low 16 bits = R0..R15) + // A modified immediate is a bit pattern an 8-bit field expands into, and + // assemblers write it as one: in hex, or as a float when the expansion + // produced one. The value is stored expanded either way -- for the float + // it is the 32-bit pattern, which is what the encoder needs back. + HEX_IMMEDIATE, + FLOAT_IMMEDIATE, } // ---- Shift / addressing-mode helpers --------------------------------------- @@ -156,6 +162,14 @@ op_imm :: #force_inline proc "contextless" (v: i64, size: u8 = 4) -> Operand { return Operand{immediate = v, kind = .IMMEDIATE, size = size} } @(require_results) +op_hex_imm :: #force_inline proc "contextless" (v: u32) -> Operand { + return Operand{immediate = i64(v), kind = .HEX_IMMEDIATE, size = 4} +} +@(require_results) +op_float_imm :: #force_inline proc "contextless" (bits: u32) -> Operand { + return Operand{immediate = i64(bits), kind = .FLOAT_IMMEDIATE, size = 4} +} +@(require_results) op_mem :: #force_inline proc "contextless" (m: Memory) -> Operand { return Operand{mem = m, kind = .MEMORY, size = 4} } diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 2100e8e27..23d679f89 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -545,6 +545,10 @@ write_operand :: proc( } case .IMMEDIATE: fmt.sbprintf(sb, "#%d", op.immediate) + case .HEX_IMMEDIATE: + fmt.sbprintf(sb, "#0x%x", op.immediate) + case .FLOAT_IMMEDIATE: + fmt.sbprintf(sb, "#%e", f64(transmute(f32)u32(op.immediate))) case .MEMORY: write_memory(sb, op.mem) case .RELATIVE: diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 711f2805d..a5447e1e7 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1426,8 +1426,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // VMOV two GPRs <-> two consecutive S regs - {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, - {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .VM_S_PLUS1}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .VM_S_PLUS1, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // ---- VMOV NEON modified immediate ---- // 1111 0010 1 D 000 imm3 Vd cmode 0 Q op 1 imm4 (op=0 VMOV, op=1 VMVN) // cmode mappings (8 forms when op=0): @@ -1442,29 +1442,29 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1110 .I8 โ†’ 0xF2800E10 // 1111 .F32 (special: high bit = 0) โ†’ 0xF2800F10 (limited to specific imm patterns) // 1110 op=1 + bit 5 set โ†’ .I64 โ†’ 0xF2800E30 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) // Q forms (Q=1, bit 6 = 1) - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q // ---- VMOV scalar to/from GPR (lane access) ---- // VMOV. Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000 // VMOV. Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000 // .8 / .16 / .32 selected by opc1+opc2 split bits in encoding. // 32-bit lane move (.32): - {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, + {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .NEON_LANE_VN_32, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV. Rt, Qd[i] @@ -1481,17 +1481,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, // VMVN immediate: 1111 0010 1 D 000 imm3 Vd cmode 0 Q 1 1 imm4 (op=1) - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Q forms - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // MVE VMVN Qd, Qm {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index db52f90ab..c29cc3c20 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -367,43 +367,43 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -1019,12 +1019,12 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.VM_S_PLUS1}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, @@ -1065,7 +1065,7 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.NEON_LANE_VN_32,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 9c4919317..cbaef5e62 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -1121,25 +1121,25 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.VM_S_PLUS1}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.NEON_LANE_VN_32,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1431,16 +1431,16 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .VMVN { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMOVN { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index d8d4e56583c91a8fc01729f1e935642849e74dea..7e581e308bb3aa767fdadcd3af24c7f6f438eff2 100644 GIT binary patch delta 7280 zcmZvg3vg7`9mfA>v)N=H*}F(`y9Fg1B$6kIT2QH&jjSPx*kDy&2?>a!QiTOkD3R%=@`ola-$w6Z+xpweu=bI!f@940t( zm-zeskMBJ0xp()Y=Y1bN?;EbPe7kn?Dyw2j|4t%Wf0nX^LJ3O{O(n)EY@Z);hgGps z$URW=O1<1wcXZHDNt(v25~P#D;Yj}uqNI+#!iXNz(F%*`+$+``f4t96F&YXqqgt`3 z_9bHRVhVqgPb#} zBybk7qjbK6-6(K1$k+J6Dm(6U2m`1NPdnntsugT4ub+MkThBL4xAECOeSXs>8-e*m z5#@&wj{m+*O^j%hUt*RoT#Wf=(^G6quI0+_v&`2;2vYNff>kO~hp?_h0?UfP0rB@i zF;036S4Tec38D)!+Q55{pOu&;h<@NjC(URBJJEbabvQ1n_Ly-$RO!68I@PocBIQRv zfy;tV{QVp?;8Wp&^8(A=_+y3n>1sQ!#AYd$vINmj9I^5$n=Q-DxoSO&%MnuSbm4!6 zf>=pZ?Rl&{`bYsb40 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z8w=hLJX<3z+)nsa9KggzK!*1!*r<(RUBO0LaXNU6Z(HogGL$H#I8IL;8=1NTh2!}9 vHJ(4o41gbtFOKwi`T*HMLr)Ho2kC21ZY1~7;-{LfxEC$qEdKJe@JReWY4iMA From 8c5ffd7b4c9e226148de13ae4e74f0ed805ea9d2 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 01:54:19 -0400 Subject: [PATCH 65/89] rexcode/arm32: the operands that are tokens, and a register field one bit short The last of the A32 sweep's disagreements, and they were mostly the same shape: an operand the syntax names but no field encodes, left printing as `#0`. MRS names APSR or SPSR by the R bit; VMRS and VMSR name FPSCR and its neighbours out of bits 19:16, which their masks had pinned shut so the register could not vary at all; SETEND names LE or BE by the E bit. Those are bare tokens in the syntax, which is what the special-register classes already model, so the endian pair joins them as a register class of its own. DBG read the whole eight-bit hint field where its option is only the low four, so it printed the fixed bits above it. RFE and SRS name their addressing mode the way LDM and STM do, so they are four mnemonics each rather than one, and the P and U bits that pick the mode are fixed bits of each form -- they had been left out of the mask entirely, so every one of the eight words decoded as the DA form. The writeback bit rides in the base register for RFE and in the implicit SP for SRS. VORR and VBIC against a modified immediate had no forms at all. Those words fell through to the shift-by-immediate family that sits beside them, and decoded as VSRA, VQSHRN and VQRSHRN with a shift of zero -- which is not a shift any of them can take. The register field in an operand was fifteen bits, on the reasoning that a register's raw value never passes 0x401F. Two classes do: the coprocessor registers at 0x8000, and now the endian tokens at 0x9000. Both were truncating silently. The field is sixteen bits, which fills the word exactly. A memory base or index is always a GPR, so those stay as they are. The A32 sweep now round-trips 984 of its 1183 entries byte-exact through llvm-mc, with nothing left that llvm and this disagree on: 159 are words llvm's own disassembly cannot assemble back, 38 are reserved encodings, and the last two are PSB CSYNC and TSB CSYNC, which llvm does not implement for AArch32 at all. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 9 +- core/rexcode/isa/arm32/encoder.odin | 17 +- core/rexcode/isa/arm32/encoding_types.odin | 7 + core/rexcode/isa/arm32/mnemonic_builders.odin | 68 +- core/rexcode/isa/arm32/mnemonics.odin | 5 +- core/rexcode/isa/arm32/operands.odin | 11 +- core/rexcode/isa/arm32/printer.odin | 2 + core/rexcode/isa/arm32/registers.odin | 6 + .../isa/arm32/tablegen/encoding_table.odin | 72 +- .../tablegen/generated/decode_tables.odin | 2340 +++++++++-------- .../tablegen/generated/encode_tables.odin | 770 +++--- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10726 -> 10902 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38249 -> 39123 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4688 -> 4736 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38249 -> 39123 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3326 -> 3402 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 9 +- 21 files changed, 1761 insertions(+), 1555 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 893a9d70c..2adf60b19 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -171,7 +171,7 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in // LDM/STM carry the writeback in bit 21; nothing else in the operand // model records it, and without it the two forms print identically. for k in 0 ..< len(e.enc) { - if e.enc[k] == .A32_REG_LIST { + if e.enc[k] == .A32_REG_LIST || e.enc[k] == .RN_A32_WB || e.enc[k] == .IMPL_SP { inst.writeback = (word >> 21) & 1 != 0 break } @@ -455,6 +455,13 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op // Only cmode 1111 expands to a float; the rest are bit patterns. if cmode == 0b1111 { return op_float_imm(v) } return op_hex_imm(v) + case .DBG_OPTION: return op_imm(i64(word & 0xF)) + case .MRS_SPEC_REG: return op_reg(Register(REG_SREG | u16(((word >> 22) & 1) * 2))) + case .VFP_SPEC_REG: return op_reg(Register(REG_FPSC | u16((word >> 16) & 0xF))) + case .SETEND_ENDIAN: return op_reg(Register(REG_ENDIAN | u16((word >> 9) & 1))) + case .IMPL_SP: return op_reg(SP) + case .MODE_IMM5: return op_imm(i64(word & 0x1F)) + case .RN_A32_WB: return op_reg(Register(REG_GPR | u16((word >> 16) & 0xF))) case .VM_S_PLUS1: // The second of a consecutive pair; only the first is encoded. return op_reg(Register(REG_SPR | u16(((word & 0xF) << 1 | ((word >> 5) & 1)) + 1))) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index f05dc5e1d..bd9083589 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -312,7 +312,7 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op return true case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, - .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, + .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, .IMM_COPROC, .IMM_COPROC_OP, .NEON_IMM, .IMM16_LO_HI: // A modified immediate reaches an immediate slot as an expanded bit // pattern or a float, so all three kinds are the same slot's shape. @@ -328,8 +328,12 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op return op.kind == .MEMORY || op.kind == .RELATIVE case .COPROC_REG, .COPROC_NUM: return op.kind == .REGISTER || op.kind == .IMMEDIATE + case .IMM_ENDIAN: + return op.kind == .REGISTER case .PSR_FIELD: - return op.kind == .IMMEDIATE + // APSR, SPSR and the endian tokens are named registers in the syntax + // even where no field encodes them. + return op.kind == .IMMEDIATE || op.kind == .REGISTER case .VPR, .QPR_MVE: return op.kind == .REGISTER && is_qpr(op.reg) case .QPR_MVE_LIST: @@ -497,6 +501,13 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0x7) << 17 case .VM_Q_MVE: return (u32(reg_hw(op.reg)) & 0x7) << 1 + case .DBG_OPTION: return u32(op.immediate) & 0xF + case .MRS_SPEC_REG: return 0 // the R bit is a fixed bit of the form + case .VFP_SPEC_REG: return (u32(reg_hw(op.reg)) & 0xF) << 16 + case .SETEND_ENDIAN: return (u32(reg_hw(op.reg)) & 1) << 9 + case .IMPL_SP: return 0 + case .MODE_IMM5: return u32(op.immediate) & 0x1F + case .RN_A32_WB: return (u32(reg_hw(op.reg)) & 0xF) << 16 case .VM_S_PLUS1: return 0 // only the first of the pair is encoded case .NEON_LANE_VN_32: @@ -953,7 +964,7 @@ neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (sh @(private="file", require_results) writeback_matches :: #force_inline proc "contextless" (inst: ^Instruction, f: ^Encoding) -> bool { for e in f.enc { - if e == .A32_REG_LIST { + if e == .A32_REG_LIST || e == .RN_A32_WB || e == .IMPL_SP { return ((f.bits >> 21) & 1 != 0) == inst.writeback } } diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index be4e83b7c..e332ac458 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -326,6 +326,13 @@ Operand_Encoding :: enum u8 { VM_Q_MVE, VFP_IMM8, VM_S_PLUS1, // the second S register of a consecutive pair + DBG_OPTION, // DBG's option, bits 3:0 -- not the wider hint field + MRS_SPEC_REG, // APSR or SPSR, by the R bit + VFP_SPEC_REG, // VMRS/VMSR system register, bits 19:16 + SETEND_ENDIAN, // LE or BE, by the E bit + IMPL_SP, // an SP the syntax names but no field encodes + MODE_IMM5, // processor mode, bits 4:0 (SRS) + RN_A32_WB, // base register whose writeback rides in bit 21 NEON_LANE_VN_32, // Vn:N with the 32-bit lane index in bit 21 // VFP immediate (VMOV.F32/F64 #imm) NEON_IMM8_ABCDEFGH, // bits 18-16 (abc) + bits 3-0 (defgh) NEON_CMODE, // bits 11-8 (cmode for VMOV/VMVN immediate) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 87763c9aa..44cb6d7a1 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -620,10 +620,22 @@ inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, s emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } -inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } -inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } +inst_rfeda_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEDA, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeda_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeda_r(dst)) } +inst_rfedb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEDB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfedb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfedb_r(dst)) } +inst_rfeia_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEIA, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeia_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeia_r(dst)) } +inst_rfeib_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEIB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeib_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeib_r(dst)) } +inst_srsda_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsda_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsda_r_imm(dst, imm)) } +inst_srsdb_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsdb_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsdb_r_imm(dst, imm)) } +inst_srsia_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSIA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsia_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsia_r_imm(dst, imm)) } +inst_srsib_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsib_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsib_r_imm(dst, imm)) } inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) } inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } @@ -742,10 +754,10 @@ emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruc emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } emit_vmov_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_qlane_r(dst, lane, src)) } emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } -inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } -inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } +inst_vmrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_vmrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmrs_r_psr(dst, imm)) } +inst_vmsr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} } +emit_vmsr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_vmsr_psr_r(imm, src)) } inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } @@ -846,9 +858,13 @@ inst_vabdl_q_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vabdl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabdl_q_d_d(dst, src, src2)) } inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } +inst_vbic_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbic_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vbic_d_imm(dst, imm)) } emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } +inst_vorr_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorr_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vorr_d_imm(dst, imm)) } emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } @@ -1885,10 +1901,22 @@ inst_swp :: inst_swp_r_r_r emit_swp :: emit_swp_r_r_r inst_swpb :: inst_swpb_r_r_r emit_swpb :: emit_swpb_r_r_r -inst_rfe :: inst_rfe_r -emit_rfe :: emit_rfe_r -inst_srs :: inst_srs_imm -emit_srs :: emit_srs_imm +inst_rfeda :: inst_rfeda_r +emit_rfeda :: emit_rfeda_r +inst_rfedb :: inst_rfedb_r +emit_rfedb :: emit_rfedb_r +inst_rfeia :: inst_rfeia_r +emit_rfeia :: emit_rfeia_r +inst_rfeib :: inst_rfeib_r +emit_rfeib :: emit_rfeib_r +inst_srsda :: inst_srsda_r_imm +emit_srsda :: emit_srsda_r_imm +inst_srsdb :: inst_srsdb_r_imm +emit_srsdb :: emit_srsdb_r_imm +inst_srsia :: inst_srsia_r_imm +emit_srsia :: emit_srsia_r_imm +inst_srsib :: inst_srsib_r_imm +emit_srsib :: emit_srsib_r_imm inst_cdp :: inst_cdp_cpn_cpop_crd_crd emit_cdp :: emit_cdp_cpn_cpop_crd_crd inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd @@ -1983,10 +2011,10 @@ inst_vcvtr :: inst_vcvtr_s_s emit_vcvtr :: emit_vcvtr_s_s inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_qlane_r, inst_vmov_qlane_qlane_r_r } emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_qlane_r, emit_vmov_qlane_qlane_r_r } -inst_vmrs :: inst_vmrs_r -emit_vmrs :: emit_vmrs_r -inst_vmsr :: inst_vmsr_r -emit_vmsr :: emit_vmsr_r +inst_vmrs :: inst_vmrs_r_psr +emit_vmrs :: emit_vmrs_r_psr +inst_vmsr :: inst_vmsr_psr_r +emit_vmsr :: emit_vmsr_psr_r inst_vldr :: inst_vldr_s_mem emit_vldr :: emit_vldr_s_mem inst_vstr :: inst_vstr_s_mem @@ -2067,10 +2095,10 @@ inst_vabdl :: inst_vabdl_q_d_d emit_vabdl :: emit_vabdl_q_d_d inst_vand :: inst_vand_d_d_d emit_vand :: emit_vand_d_d_d -inst_vbic :: inst_vbic_d_d_d -emit_vbic :: emit_vbic_d_d_d -inst_vorr :: inst_vorr_d_d_d -emit_vorr :: emit_vorr_d_d_d +inst_vbic :: proc{ inst_vbic_d_imm, inst_vbic_d_d_d } +emit_vbic :: proc{ emit_vbic_d_imm, emit_vbic_d_d_d } +inst_vorr :: proc{ inst_vorr_d_imm, inst_vorr_d_d_d } +emit_vorr :: proc{ emit_vorr_d_imm, emit_vorr_d_d_d } inst_vorn :: inst_vorn_d_d_d emit_vorn :: emit_vorn_d_d_d inst_veor :: inst_veor_d_d_d diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index 5494705f4..617124fa3 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -207,8 +207,9 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // ARMv6 / Return-from-Exception // ------------------------------------------------------------------------- - RFE, // return from exception - SRS, // store return state + // The addressing mode is part of the name, as it is for LDM and STM. + RFEDA, RFEDB, RFEIA, RFEIB, // return from exception + SRSDA, SRSDB, SRSIA, SRSIB, // store return state // ------------------------------------------------------------------------- // Coprocessor (legacy CP-space; many subsumed by VFP/NEON) diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 0a68f1bf1..3e9f77471 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -67,8 +67,9 @@ Index_Mode :: enum u8 { // multiplied by four in every Instruction. Field syntax and composite // literals are unchanged, so this is invisible to callers. // -// A Register's raw value never exceeds REG_QPR|31 = 0x401F, so 15 bits hold -// one losslessly (index uses Register(0), not a high sentinel, for "absent"). +// A memory base or index is always a GPR, whose raw value never exceeds +// REG_GPR|15 = 0x100F, so 15 bits hold one losslessly (index uses +// Register(0), not a high sentinel, for "absent"). // `disp` gets 19 bits (+/-262,143) against a worst case of 4,095 -- the imm12 // of an A32 load -- so there is ~64x headroom. Memory :: bit_field u64 { @@ -115,14 +116,16 @@ Operand :: struct #packed { // op.shift_type, op.shift_amt and op.lane still read and write // exactly as they did when these were separate fields. using _: bit_field u32 { - reg: Register | 15, + // Sixteen bits, not fifteen: the class nibble reaches 0x9000 for + // the endian tokens and 0x8000 for the coprocessor registers, + // and both were silently truncating. + reg: Register | 16, shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain shift_amt: u8 | 6, // 0..32, or the Rs index for RSR lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM // Whether `lane` means anything. Lane 0 is a real index -- `d0[0]` // is not `d0` -- so it cannot be spelled by lane == 0. has_lane: bool | 1, - // 1 bit spare }, mem: Memory, immediate: i64, diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 23d679f89..ff21c8506 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -501,6 +501,8 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool = fals } case REG_COPROC: fmt.sbprintf(sb, "c%d", hw) + case REG_ENDIAN: + strings.write_string(sb, hw == 0 ? "le" : "be") case: fmt.sbprintf(sb, "?%d", hw) } diff --git a/core/rexcode/isa/arm32/registers.odin b/core/rexcode/isa/arm32/registers.odin index 9bdb102c4..a366e7162 100644 --- a/core/rexcode/isa/arm32/registers.odin +++ b/core/rexcode/isa/arm32/registers.odin @@ -35,6 +35,9 @@ REG_SREG :: u16(0x5000) REG_FPSC :: u16(0x6000) REG_BANKED :: u16(0x7000) REG_COPROC :: u16(0x8000) +// SETEND names its argument `le` or `be`. That is a bare token in the syntax, +// which is what the special-register classes above already model. +REG_ENDIAN :: u16(0x9000) REG_CLASS_MASK :: u16(0xF000) REG_HW_MASK :: u16(0x0FFF) @@ -160,6 +163,9 @@ SPSR :: Register(REG_SREG | 2) // values rather than expanding the Register set. // FPSCR / FPSID and friends +LE :: Register(REG_ENDIAN | 0) +BE :: Register(REG_ENDIAN | 1) + FPSID :: Register(REG_FPSC | 0) FPSCR :: Register(REG_FPSC | 1) MVFR2 :: Register(REG_FPSC | 5) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index a5447e1e7..19efb4f2a 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -832,7 +832,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // MSR / MRS (status reg access) .MRS = { - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .MRS_SPEC_REG, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, // T32 MRS: high=11110011 1110 1111 low=10 0 0 Rd 0000 0000 {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, @@ -849,7 +849,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}, {}} }, // SETEND (deprecated in ARMv8): 1111 0001 0000 0001 0000 000E 0000 0000 - .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, + .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.SETEND_ENDIAN, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, // SETPAN (ARMv8.1): A32 = 1111 0001 0001 0000 0000 0000 imm1 0000 0000 โ†’ bit 9 = imm // T16: 1011 0110 0001 0 imm1 000 โ†’ bit 3 = imm @@ -887,7 +887,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {}} }, - .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, + .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.DBG_OPTION, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {}} }, // Memory barriers (ARMv7): 1111 0101 0111 1111 1111 0000 type imm4 @@ -1154,13 +1154,39 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, // RFE / SRS (return-from-exception / store return state) - .RFE = { - // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 - {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}, {}}, + // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 + .RFEDA = { + {.RFEDA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEDA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, }, - .SRS = { - // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 - {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}, {}}, + .RFEDB = { + {.RFEDB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEDB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + .RFEIA = { + {.RFEIA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEIA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + .RFEIB = { + {.RFEIB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEIB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 + .SRSDA = { + {.SRSDA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSDA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSDB = { + {.SRSDB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSDB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSIA = { + {.SRSIA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSIA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSIB = { + {.SRSIB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSIB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, }, // ========================================================================= @@ -1605,8 +1631,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VMRS / VMSR (access FPSCR + friends as GPR) // VMRS: cond 1110 1111 0001 Rt 1010 0001 0000 (Rt=PC means transfer to APSR.NZCV) - .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, - .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, + .VMRS = { {.VMRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RT_A32, .VFP_SPEC_REG, .NONE, .NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {}} }, + .VMSR = { {.VMSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.VFP_SPEC_REG, .RT_A32, .NONE, .NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {}} }, // VLDR / VSTR (single / double): cond 1101 U D 0 1 Rn Vd 101 sz imm8 .VLDR = { @@ -1803,12 +1829,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBIC = { + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // VBIC D: 1111 0010 0100 Vn Vd 0001 N 0 M 1 Vm {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORR = { + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index c29cc3c20..ad30716ed 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1663]lib.Decode_Entry{ +DECODE_ENTRIES := [1701]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -65,8 +65,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.SETEND_ENDIAN,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.MRS_SPEC_REG,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} }, { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -267,8 +267,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -367,43 +367,67 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -438,8 +462,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -461,18 +485,18 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, @@ -502,11 +526,11 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -518,8 +542,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -580,11 +604,11 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.DBG_OPTION,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -597,8 +621,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -652,12 +676,12 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -675,128 +699,128 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, 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{.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, @@ -805,14 +829,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -821,29 +845,29 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -985,19 +1009,33 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, @@ -1019,8 +1057,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1029,8 +1067,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_2}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, @@ -1039,14 +1077,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VFMSL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, @@ -1056,20 +1094,20 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.NEON_LANE_VN_32,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, @@ -1077,14 +1115,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, @@ -1092,8 +1130,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, - { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1106,100 +1144,100 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVTA, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTP, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S32} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32,.F16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32,.F16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U32,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.U16,.F16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.U16} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S32,.F16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA09C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.S32,.F64} }, - { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.VFP_SPEC_REG,.RT_A32,.NONE,.NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VN_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RT_A32,.VFP_SPEC_REG,.NONE,.NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, @@ -1256,10 +1294,10 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, - { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, @@ -1539,8 +1577,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1675,7 +1713,7 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1663]u16{ +DECODE_FORM_IDX := [1701]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1687,103 +1725,106 @@ DECODE_FORM_IDX := [1663]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, - 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, + 4, 5, 5, 2, 4, 4, 13, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 12, 1, 8, 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, - 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, + 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 13, 5, 5, 5, 4, 4, + 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 1, 2, 2, 12, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 25, 22, 23, 24, 21, 0, 0, 0, 10, 20, - 15, 11, 18, 19, 17, 12, 13, 14, 16, 0, 0, 0, 0, 10, 11, 6, - 0, 0, 0, 6, 5, 8, 9, 3, 4, 2, 7, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 1, 6, 0, - 2, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 2, 7, 2, 7, 1, 3, 1, 3, 1, 3, - 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, 1, - 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, - 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, - 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, - 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, - 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, - 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, - 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, - 20, 14, 13, 9, 4, 8, 4, 8, 4, 6, 6, 3, 5, 5, 7, 7, - 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 5, 9, 5, 9, 7, 7, - 0, 2, 5, 3, 4, 8, 6, 7, 9, 3, 6, 8, 2, 4, 7, 5, - 9, 10, 0, 1, 2, 5, 3, 1, 0, 4, 2, 2, 1, 0, 4, 0, - 2, 1, 0, 3, 1, 2, 3, 1, 0, 2, 3, 2, 1, 2, 4, 3, - 5, 0, 1, 2, 5, 3, 0, 1, 4, 1, 5, 0, 4, 2, 3, 3, - 1, 5, 4, 2, 0, 2, 3, 4, 3, 2, 4, 0, 0, 0, 11, 13, - 12, 10, 14, 15, 12, 13, 13, 12, 14, 15, 16, 14, 17, 15, 14, 15, - 16, 17, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, 3, 5, 0, 1, - 2, 3, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 2, 3, 0, 1, - 3, 2, 1, 0, 2, 3, 3, 0, 3, 0, 3, 2, 3, 1, 0, 1, - 2, 0, 0, 1, 1, 0, 2, 2, 3, 0, 2, 1, 0, 2, 1, 1, - 0, 1, 0, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, - 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, - 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 21, 22, 23, 25, 24, 0, 0, 5, 0, 3, + 6, 8, 1, 11, 9, 2, 10, 7, 4, 9, 0, 11, 3, 8, 1, 10, + 2, 4, 5, 7, 6, 0, 11, 13, 10, 15, 20, 12, 14, 19, 18, 17, + 16, 0, 0, 0, 0, 11, 10, 6, 0, 0, 0, 7, 4, 3, 6, 9, + 2, 8, 5, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, + 0, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, + 11, 7, 1, 6, 1, 6, 1, 0, 2, 2, 0, 0, 2, 4, 4, 4, + 4, 3, 2, 2, 2, 2, 2, 2, 2, 19, 13, 12, 8, 2, 2, 7, + 7, 2, 3, 1, 3, 1, 3, 1, 6, 6, 5, 5, 0, 1, 0, 3, + 0, 3, 0, 3, 7, 13, 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, + 9, 7, 7, 1, 3, 9, 7, 7, 12, 6, 6, 1, 0, 7, 7, 7, + 3, 3, 8, 0, 5, 13, 11, 3, 6, 6, 8, 8, 6, 6, 0, 0, + 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, + 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, + 4, 0, 0, 0, 0, 1, 10, 4, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, + 1, 5, 9, 10, 10, 12, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, + 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, + 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, + 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 4, 9, 4, 8, 4, + 8, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, + 10, 5, 9, 5, 9, 5, 7, 7, 0, 8, 9, 5, 2, 6, 4, 3, + 7, 3, 2, 4, 5, 6, 7, 8, 9, 10, 2, 1, 0, 3, 2, 1, + 5, 4, 0, 0, 1, 2, 4, 0, 1, 2, 2, 0, 1, 3, 2, 3, + 1, 0, 1, 3, 2, 1, 2, 5, 3, 4, 0, 5, 3, 2, 4, 0, + 1, 2, 3, 1, 5, 4, 0, 0, 1, 3, 2, 4, 5, 2, 4, 3, + 2, 4, 3, 0, 0, 0, 12, 10, 11, 13, 14, 13, 12, 15, 14, 15, + 13, 12, 17, 14, 16, 15, 17, 15, 16, 14, 2, 3, 1, 0, 1, 0, + 0, 1, 1, 0, 5, 3, 2, 0, 3, 1, 1, 0, 1, 0, 1, 0, + 0, 0, 0, 0, 1, 0, 3, 2, 0, 2, 3, 1, 2, 3, 3, 0, + 3, 0, 3, 2, 1, 0, 3, 0, 2, 1, 1, 0, 1, 0, 2, 2, + 0, 2, 1, 3, 1, 0, 2, 0, 1, 0, 1, 0, 0, 2, 0, 2, + 0, 0, 6, 5, 4, 4, 5, 4, 3, 3, 4, 3, 2, 2, 7, 5, + 4, 4, 6, 4, 3, 3, 5, 3, 2, 2, 4, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, - 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, - 0, 7, 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, 1, 0, - 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 4, 32, - 31, 3, 2, 1, 0, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, - 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, - 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 1, 0, 2, 2, 0, - 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, - 3, 2, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, - 1, 0, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 34, 31, - 30, 32, 28, 26, 25, 27, 29, 33, 21, 19, 18, 20, 22, 15, 14, 16, - 12, 9, 11, 13, 17, 23, 5, 4, 6, 2, 0, 1, 3, 7, 24, 8, - 0, 1, 0, 1, 0, 1, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, - 0, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, - 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, - 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, - 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, 28, 27, - 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, 4, - 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, 0, - 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, 2, - 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, - 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, 6, - 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, 2, 2, - 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 3, 0, 3, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, + 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, + 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, + 0, 0, 0, 0, 0, 1, 0, 7, 7, 9, 0, 0, 6, 8, 0, 0, + 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, + 0, 1, 1, 0, 4, 32, 31, 3, 2, 1, 0, 2, 2, 1, 0, 1, + 0, 0, 0, 0, 0, 5, 26, 1, 0, 0, 1, 0, 0, 3, 3, 2, + 2, 2, 1, 0, 1, 0, 2, 2, 1, 0, 1, 0, 30, 1, 3, 0, + 1, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, 1, + 0, 0, 1, 3, 2, 5, 2, 3, 1, 0, 1, 0, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 2, 4, + 0, 1, 0, 1, 32, 31, 33, 29, 27, 26, 28, 30, 34, 23, 21, 20, + 22, 24, 17, 16, 18, 14, 12, 11, 13, 15, 19, 25, 7, 5, 4, 6, + 8, 1, 0, 2, 3, 9, 0, 1, 1, 0, 2, 0, 1, 3, 1, 0, + 0, 1, 0, 1, 0, 1, 0, 2, 3, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, + 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, + 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, + 0, 0, 29, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, + 0, 0, 0, 7, 28, 27, 2, 14, 14, 2, 0, 0, 0, 0, 0, 0, + 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, + 10, 10, 12, 12, 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, + 6, 4, 8, 9, 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, + 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, + 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, + 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, + 5, 4, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, 1, 1, - 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, - 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, - 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, - 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, 4, - 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, - 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, - 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, 1, - 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, + 1, 1, 0, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, + 1, 0, 0, 1, 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, + 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, + 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, + 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, + 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, + 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, + 2, 1, 1, 1, 2, } @(rodata) -DECODE_BUCKET_LIST := [5363]u16{ +DECODE_BUCKET_LIST := [5451]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1822,304 +1863,309 @@ DECODE_BUCKET_LIST := [5363]u16{ 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 361, 360, 362, 359, 363, 364, - 365, 370, 375, 376, 369, 374, 371, 368, 372, 367, 373, 366, 377, 378, 379, 380, - 381, 382, 384, 383, 385, 386, 392, 388, 387, 393, 391, 390, 389, 394, 395, 396, - 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 428, 427, - 429, 430, 431, 432, 433, 434, 436, 435, 437, 438, 439, 440, 395, 396, 397, 398, - 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 441, - 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 454, 455, 456, - 457, 458, 459, 461, 460, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 468, 395, - 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, - 412, 413, 469, 470, 471, 468, 362, 360, 361, 359, 358, 363, 364, 365, 376, 375, - 374, 372, 371, 370, 373, 368, 369, 367, 366, 377, 378, 379, 380, 382, 381, 383, - 384, 385, 386, 394, 393, 392, 391, 389, 390, 388, 387, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 472, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, - 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, - 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 473, 472, 442, 443, - 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 457, 456, 458, 459, - 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, - 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 474, 395, 396, 397, 398, - 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 469, - 470, 475, 474, 477, 476, 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, - 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, - 505, 506, 507, 508, 510, 509, 511, 512, 513, 514, 515, 516, 517, 518, 519, 521, - 520, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, - 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, - 553, 554, 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1362, 1363, 1364, 1365, 1366, 1616, 1618, 1620, 1293, 1294, 1295, 1296, 1305, 1306, 1307, + 1308, 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, + 1616, 1618, 1620, 1582, 1583, 1303, 1304, 1322, 1323, 1333, 1334, 1339, 1340, 1597, 1598, 1599, + 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1607, 1608, 1609, 1610, + 1616, 1618, 1620, 1594, 1595, 1596, 1344, 1605, 1347, 1606, 1371, 1372, 1373, 1374, 1375, 1376, + 1377, 1378, 1379, 1380, 1381, 1382, 1595, 1596, 1344, 1605, 1347, 1606, 1371, 1372, 1373, 1374, + 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, 1605, 1345, 1348, 1606, 1371, 1372, 1373, + 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, 1345, 1605, 1348, 1606, 1371, 1372, + 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1594, 1595, 1596, 1344, 1605, 1347, + 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1595, 1596, 1344, + 1605, 1347, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, + 1605, 1345, 1348, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, + 1596, 1605, 1345, 1348, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, + 1382, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1576, 1577, 1578, + 1579, 1580, 1581, 1586, 1587, 1588, 1589, 1591, 1592, 1593, 1606, 1385, 1386, 1387, 1606, 1385, + 1386, 1387, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1576, 1577, 1578, 1579, 1580, 1581, + 1586, 1587, 1588, 1589, 1591, 1592, 1593, 1606, 1385, 1386, 1387, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2163,607 +2209,599 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x25 = { 477, 51}, 0x26 = { 528, 54}, 0x27 = { 582, 19}, - 0x28 = { 601, 57}, - 0x29 = { 658, 47}, - 0x2A = { 705, 46}, - 0x2B = { 751, 23}, - 0x2C = { 774, 57}, - 0x2D = { 831, 47}, - 0x2E = { 878, 46}, - 0x2F = { 924, 23}, - 0x30 = { 947, 58}, - 0x31 = { 1005, 27}, - 0x32 = { 1032, 45}, - 0x33 = { 1077, 9}, - 0x34 = { 1086, 58}, - 0x35 = { 1144, 27}, - 0x36 = { 1171, 33}, - 0x37 = { 1204, 9}, - 0x38 = { 1213, 58}, - 0x39 = { 1271, 43}, - 0x3A = { 1314, 42}, - 0x3B = { 1356, 156}, - 0x3C = { 1512, 58}, - 0x3D = { 1570, 43}, - 0x3E = { 1613, 42}, - 0x3F = { 1655, 156}, - 0x40 = { 1811, 12}, - 0x41 = { 1823, 1}, - 0x42 = { 1824, 12}, - 0x43 = { 1836, 1}, - 0x44 = { 1837, 1}, - 0x45 = { 1838, 2}, - 0x46 = { 1840, 1}, - 0x47 = { 1841, 1}, - 0x48 = { 1842, 13}, - 0x49 = { 1855, 1}, - 0x4A = { 1856, 17}, - 0x4B = { 1873, 1}, - 0x4C = { 1874, 13}, - 0x4D = { 1887, 2}, - 0x4E = { 1889, 17}, - 0x4F = { 1906, 1}, - 0x50 = { 1907, 1}, - 0x51 = { 1908, 1}, - 0x52 = { 1909, 1}, - 0x53 = { 1910, 1}, - 0x54 = { 1911, 1}, - 0x55 = { 1912, 1}, - 0x56 = { 1913, 1}, - 0x57 = { 1914, 6}, - 0x58 = { 1920, 1}, - 0x59 = { 1921, 1}, - 0x5A = { 1922, 1}, - 0x5B = { 1923, 1}, - 0x5C = { 1924, 1}, - 0x5D = { 1925, 3}, - 0x5E = { 1928, 1}, - 0x5F = { 1929, 1}, - 0x61 = { 1930, 6}, - 0x62 = { 1936, 6}, - 0x63 = { 1942, 6}, - 0x65 = { 1948, 6}, - 0x66 = { 1954, 6}, - 0x67 = { 1960, 6}, - 0x68 = { 1966, 5}, - 0x6A = { 1971, 4}, - 0x6B = { 1975, 5}, - 0x6C = { 1980, 2}, - 0x6E = { 1982, 4}, - 0x6F = { 1986, 5}, - 0x70 = { 1991, 9}, - 0x71 = { 2000, 2}, - 0x73 = { 2002, 1}, - 0x74 = { 2003, 5}, - 0x75 = { 2008, 7}, - 0x78 = { 2015, 3}, - 0x79 = { 2018, 1}, - 0x7A = { 2019, 1}, - 0x7B = { 2020, 1}, - 0x7C = { 2021, 3}, - 0x7D = { 2024, 3}, - 0x7E = { 2027, 1}, - 0x7F = { 2028, 2}, - 0x80 = { 2030, 1}, - 0x81 = { 2031, 2}, - 0x82 = { 2033, 1}, - 0x83 = { 2034, 2}, - 0x84 = { 2036, 1}, - 0x85 = { 2037, 1}, - 0x86 = { 2038, 1}, - 0x87 = { 2039, 1}, - 0x88 = { 2040, 1}, - 0x89 = { 2041, 2}, - 0x8A = { 2043, 1}, - 0x8B = { 2044, 3}, - 0x8C = { 2047, 1}, - 0x8D = { 2048, 1}, - 0x8E = { 2049, 1}, - 0x8F = { 2050, 1}, - 0x90 = { 2051, 1}, - 0x91 = { 2052, 2}, - 0x92 = { 2054, 2}, - 0x93 = { 2056, 2}, - 0x94 = { 2058, 1}, - 0x95 = { 2059, 1}, - 0x96 = { 2060, 1}, - 0x97 = { 2061, 1}, - 0x98 = { 2062, 1}, - 0x99 = { 2063, 2}, - 0x9A = { 2065, 1}, - 0x9B = { 2066, 2}, - 0x9C = { 2068, 1}, - 0x9D = { 2069, 1}, - 0x9E = { 2070, 1}, - 0x9F = { 2071, 1}, - 0xA0 = { 2072, 2}, - 0xA1 = { 2074, 2}, - 0xA2 = { 2076, 2}, - 0xA3 = { 2078, 2}, - 0xA4 = { 2080, 2}, - 0xA5 = { 2082, 2}, - 0xA6 = { 2084, 2}, - 0xA7 = { 2086, 2}, - 0xA8 = { 2088, 2}, - 0xA9 = { 2090, 2}, - 0xAA = { 2092, 2}, - 0xAB = { 2094, 2}, - 0xAC = { 2096, 2}, - 0xAD = { 2098, 2}, - 0xAE = { 2100, 2}, - 0xAF = { 2102, 2}, - 0xB0 = { 2104, 2}, - 0xB1 = { 2106, 2}, - 0xB2 = { 2108, 2}, - 0xB3 = { 2110, 2}, - 0xB4 = { 2112, 2}, - 0xB5 = { 2114, 2}, - 0xB6 = { 2116, 2}, - 0xB7 = { 2118, 2}, - 0xB8 = { 2120, 2}, - 0xB9 = { 2122, 2}, - 0xBA = { 2124, 2}, - 0xBB = { 2126, 2}, - 0xBC = { 2128, 2}, - 0xBD = { 2130, 2}, - 0xBE = { 2132, 2}, - 0xBF = { 2134, 2}, - 0xC0 = { 2136, 7}, - 0xC1 = { 2143, 4}, - 0xC2 = { 2147, 12}, - 0xC3 = { 2159, 5}, - 0xC4 = { 2164, 11}, - 0xC5 = { 2175, 8}, - 0xC6 = { 2183, 12}, - 0xC7 = { 2195, 5}, - 0xC8 = { 2200, 6}, - 0xC9 = { 2206, 6}, - 0xCA = { 2212, 12}, - 0xCB = { 2224, 8}, - 0xCC = { 2232, 6}, - 0xCD = { 2238, 6}, - 0xCE = { 2244, 12}, - 0xCF = { 2256, 6}, - 0xD0 = { 2262, 4}, - 0xD1 = { 2266, 4}, - 0xD2 = { 2270, 4}, - 0xD3 = { 2274, 2}, - 0xD4 = { 2276, 4}, - 0xD5 = { 2280, 4}, - 0xD6 = { 2284, 2}, - 0xD7 = { 2286, 2}, - 0xD8 = { 2288, 4}, - 0xD9 = { 2292, 4}, - 0xDA = { 2296, 2}, - 0xDB = { 2298, 2}, - 0xDC = { 2300, 4}, - 0xDD = { 2304, 4}, - 0xDE = { 2308, 2}, - 0xDF = { 2310, 2}, - 0xE0 = { 2312, 19}, - 0xE1 = { 2331, 14}, - 0xE2 = { 2345, 19}, - 0xE3 = { 2364, 15}, - 0xE4 = { 2379, 17}, - 0xE5 = { 2396, 13}, - 0xE6 = { 2409, 18}, - 0xE7 = { 2427, 15}, - 0xE8 = { 2442, 14}, - 0xE9 = { 2456, 11}, - 0xEA = { 2467, 10}, - 0xEB = { 2477, 91}, - 0xEC = { 2568, 15}, - 0xED = { 2583, 11}, - 0xEE = { 2594, 12}, - 0xEF = { 2606, 92}, - 0xF0 = { 2698, 3}, - 0xF1 = { 2701, 3}, - 0xF2 = { 2704, 3}, - 0xF3 = { 2707, 3}, - 0xF4 = { 2710, 3}, - 0xF5 = { 2713, 3}, - 0xF6 = { 2716, 3}, - 0xF7 = { 2719, 3}, - 0xF8 = { 2722, 1}, - 0xF9 = { 2723, 1}, - 0xFA = { 2724, 1}, - 0xFB = { 2725, 1}, - 0xFC = { 2726, 1}, - 0xFD = { 2727, 1}, - 0xFE = { 2728, 1}, - 0xFF = { 2729, 1}, + 0x28 = { 601, 81}, + 0x29 = { 682, 47}, + 0x2A = { 729, 46}, + 0x2B = { 775, 23}, + 0x2C = { 798, 81}, + 0x2D = { 879, 47}, + 0x2E = { 926, 46}, + 0x2F = { 972, 23}, + 0x30 = { 995, 58}, + 0x31 = { 1053, 27}, + 0x32 = { 1080, 45}, + 0x33 = { 1125, 9}, + 0x34 = { 1134, 58}, + 0x35 = { 1192, 27}, + 0x36 = { 1219, 33}, + 0x37 = { 1252, 9}, + 0x38 = { 1261, 82}, + 0x39 = { 1343, 43}, + 0x3A = { 1386, 42}, + 0x3B = { 1428, 156}, + 0x3C = { 1584, 82}, + 0x3D = { 1666, 43}, + 0x3E = { 1709, 42}, + 0x3F = { 1751, 156}, + 0x40 = { 1907, 12}, + 0x41 = { 1919, 1}, + 0x42 = { 1920, 12}, + 0x43 = { 1932, 1}, + 0x44 = { 1933, 1}, + 0x45 = { 1934, 2}, + 0x46 = { 1936, 1}, + 0x47 = { 1937, 1}, + 0x48 = { 1938, 13}, + 0x49 = { 1951, 1}, + 0x4A = { 1952, 17}, + 0x4B = { 1969, 1}, + 0x4C = { 1970, 13}, + 0x4D = { 1983, 2}, + 0x4E = { 1985, 17}, + 0x4F = { 2002, 1}, + 0x50 = { 2003, 1}, + 0x51 = { 2004, 1}, + 0x52 = { 2005, 1}, + 0x53 = { 2006, 1}, + 0x54 = { 2007, 1}, + 0x55 = { 2008, 1}, + 0x56 = { 2009, 1}, + 0x57 = { 2010, 6}, + 0x58 = { 2016, 1}, + 0x59 = { 2017, 1}, + 0x5A = { 2018, 1}, + 0x5B = { 2019, 1}, + 0x5C = { 2020, 1}, + 0x5D = { 2021, 3}, + 0x5E = { 2024, 1}, + 0x5F = { 2025, 1}, + 0x61 = { 2026, 6}, + 0x62 = { 2032, 6}, + 0x63 = { 2038, 6}, + 0x65 = { 2044, 6}, + 0x66 = { 2050, 6}, + 0x67 = { 2056, 6}, + 0x68 = { 2062, 5}, + 0x6A = { 2067, 4}, + 0x6B = { 2071, 5}, + 0x6C = { 2076, 2}, + 0x6E = { 2078, 4}, + 0x6F = { 2082, 5}, + 0x70 = { 2087, 9}, + 0x71 = { 2096, 2}, + 0x73 = { 2098, 1}, + 0x74 = { 2099, 5}, + 0x75 = { 2104, 7}, + 0x78 = { 2111, 3}, + 0x79 = { 2114, 1}, + 0x7A = { 2115, 1}, + 0x7B = { 2116, 1}, + 0x7C = { 2117, 3}, + 0x7D = { 2120, 3}, + 0x7E = { 2123, 1}, + 0x7F = { 2124, 2}, + 0x80 = { 2126, 1}, + 0x81 = { 2127, 2}, + 0x82 = { 2129, 1}, + 0x83 = { 2130, 2}, + 0x84 = { 2132, 1}, + 0x86 = { 2133, 1}, + 0x88 = { 2134, 1}, + 0x89 = { 2135, 2}, + 0x8A = { 2137, 1}, + 0x8B = { 2138, 3}, + 0x8C = { 2141, 1}, + 0x8E = { 2142, 1}, + 0x90 = { 2143, 1}, + 0x91 = { 2144, 2}, + 0x92 = { 2146, 2}, + 0x93 = { 2148, 2}, + 0x94 = { 2150, 1}, + 0x96 = { 2151, 1}, + 0x98 = { 2152, 1}, + 0x99 = { 2153, 2}, + 0x9A = { 2155, 1}, + 0x9B = { 2156, 2}, + 0x9C = { 2158, 1}, + 0x9E = { 2159, 1}, + 0xA0 = { 2160, 2}, + 0xA1 = { 2162, 2}, + 0xA2 = { 2164, 2}, + 0xA3 = { 2166, 2}, + 0xA4 = { 2168, 2}, + 0xA5 = { 2170, 2}, + 0xA6 = { 2172, 2}, + 0xA7 = { 2174, 2}, + 0xA8 = { 2176, 2}, + 0xA9 = { 2178, 2}, + 0xAA = { 2180, 2}, + 0xAB = { 2182, 2}, + 0xAC = { 2184, 2}, + 0xAD = { 2186, 2}, + 0xAE = { 2188, 2}, + 0xAF = { 2190, 2}, + 0xB0 = { 2192, 2}, + 0xB1 = { 2194, 2}, + 0xB2 = { 2196, 2}, + 0xB3 = { 2198, 2}, + 0xB4 = { 2200, 2}, + 0xB5 = { 2202, 2}, + 0xB6 = { 2204, 2}, + 0xB7 = { 2206, 2}, + 0xB8 = { 2208, 2}, + 0xB9 = { 2210, 2}, + 0xBA = { 2212, 2}, + 0xBB = { 2214, 2}, + 0xBC = { 2216, 2}, + 0xBD = { 2218, 2}, + 0xBE = { 2220, 2}, + 0xBF = { 2222, 2}, + 0xC0 = { 2224, 7}, + 0xC1 = { 2231, 4}, + 0xC2 = { 2235, 12}, + 0xC3 = { 2247, 5}, + 0xC4 = { 2252, 11}, + 0xC5 = { 2263, 8}, + 0xC6 = { 2271, 12}, + 0xC7 = { 2283, 5}, + 0xC8 = { 2288, 6}, + 0xC9 = { 2294, 6}, + 0xCA = { 2300, 12}, + 0xCB = { 2312, 8}, + 0xCC = { 2320, 6}, + 0xCD = { 2326, 6}, + 0xCE = { 2332, 12}, + 0xCF = { 2344, 6}, + 0xD0 = { 2350, 4}, + 0xD1 = { 2354, 4}, + 0xD2 = { 2358, 4}, + 0xD3 = { 2362, 2}, + 0xD4 = { 2364, 4}, + 0xD5 = { 2368, 4}, + 0xD6 = { 2372, 2}, + 0xD7 = { 2374, 2}, + 0xD8 = { 2376, 4}, + 0xD9 = { 2380, 4}, + 0xDA = { 2384, 2}, + 0xDB = { 2386, 2}, + 0xDC = { 2388, 4}, + 0xDD = { 2392, 4}, + 0xDE = { 2396, 2}, + 0xDF = { 2398, 2}, + 0xE0 = { 2400, 19}, + 0xE1 = { 2419, 14}, + 0xE2 = { 2433, 19}, + 0xE3 = { 2452, 15}, + 0xE4 = { 2467, 17}, + 0xE5 = { 2484, 13}, + 0xE6 = { 2497, 18}, + 0xE7 = { 2515, 15}, + 0xE8 = { 2530, 14}, + 0xE9 = { 2544, 11}, + 0xEA = { 2555, 10}, + 0xEB = { 2565, 91}, + 0xEC = { 2656, 15}, + 0xED = { 2671, 11}, + 0xEE = { 2682, 12}, + 0xEF = { 2694, 92}, + 0xF0 = { 2786, 3}, + 0xF1 = { 2789, 3}, + 0xF2 = { 2792, 3}, + 0xF3 = { 2795, 3}, + 0xF4 = { 2798, 3}, + 0xF5 = { 2801, 3}, + 0xF6 = { 2804, 3}, + 0xF7 = { 2807, 3}, + 0xF8 = { 2810, 1}, + 0xF9 = { 2811, 1}, + 0xFA = { 2812, 1}, + 0xFB = { 2813, 1}, + 0xFC = { 2814, 1}, + 0xFD = { 2815, 1}, + 0xFE = { 2816, 1}, + 0xFF = { 2817, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2730, 23}, - 0x75 = { 2753, 19}, - 0x76 = { 2772, 19}, - 0x77 = { 2791, 104}, - 0x78 = { 2895, 31}, - 0x79 = { 2926, 38}, - 0x7A = { 2964, 23}, - 0x7B = { 2987, 14}, - 0x7C = { 3001, 20}, - 0x7D = { 3021, 71}, - 0x7E = { 3092, 23}, - 0x7F = { 3115, 126}, + 0x74 = { 2818, 23}, + 0x75 = { 2841, 19}, + 0x76 = { 2860, 19}, + 0x77 = { 2879, 104}, + 0x78 = { 2983, 31}, + 0x79 = { 3014, 38}, + 0x7A = { 3052, 23}, + 0x7B = { 3075, 14}, + 0x7C = { 3089, 20}, + 0x7D = { 3109, 71}, + 0x7E = { 3180, 23}, + 0x7F = { 3203, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3241, 1}, - 0x01 = { 3242, 1}, - 0x02 = { 3243, 1}, - 0x03 = { 3244, 1}, - 0x04 = { 3245, 1}, - 0x05 = { 3246, 1}, - 0x06 = { 3247, 2}, - 0x07 = { 3249, 2}, - 0x08 = { 3251, 1}, - 0x09 = { 3252, 1}, - 0x0A = { 3253, 1}, - 0x0B = { 3254, 1}, - 0x0C = { 3255, 1}, - 0x0D = { 3256, 1}, - 0x0E = { 3257, 1}, - 0x0F = { 3258, 1}, - 0x10 = { 3259, 16}, - 0x11 = { 3275, 7}, - 0x12 = { 3282, 1}, - 0x13 = { 3283, 1}, - 0x14 = { 3284, 2}, - 0x15 = { 3286, 2}, - 0x16 = { 3288, 2}, - 0x17 = { 3290, 2}, - 0x18 = { 3292, 1}, - 0x19 = { 3293, 1}, - 0x1A = { 3294, 1}, - 0x1B = { 3295, 1}, - 0x1C = { 3296, 1}, - 0x1D = { 3297, 1}, - 0x1E = { 3298, 1}, - 0x1F = { 3299, 1}, - 0x20 = { 3300, 1}, - 0x21 = { 3301, 1}, - 0x22 = { 3302, 1}, - 0x23 = { 3303, 1}, - 0x24 = { 3304, 1}, - 0x25 = { 3305, 1}, - 0x26 = { 3306, 1}, - 0x27 = { 3307, 1}, - 0x28 = { 3308, 1}, - 0x29 = { 3309, 1}, - 0x2A = { 3310, 1}, - 0x2B = { 3311, 1}, - 0x2C = { 3312, 7}, - 0x2D = { 3319, 2}, - 0x2E = { 3321, 4}, - 0x2F = { 3325, 8}, - 0x30 = { 3333, 1}, - 0x31 = { 3334, 1}, - 0x32 = { 3335, 1}, - 0x33 = { 3336, 1}, - 0x34 = { 3337, 1}, - 0x35 = { 3338, 1}, - 0x36 = { 3339, 1}, - 0x37 = { 3340, 3}, - 0x38 = { 3343, 1}, - 0x39 = { 3344, 1}, + 0x00 = { 3329, 1}, + 0x01 = { 3330, 1}, + 0x02 = { 3331, 1}, + 0x03 = { 3332, 1}, + 0x04 = { 3333, 1}, + 0x05 = { 3334, 1}, + 0x06 = { 3335, 2}, + 0x07 = { 3337, 2}, + 0x08 = { 3339, 1}, + 0x09 = { 3340, 1}, + 0x0A = { 3341, 1}, + 0x0B = { 3342, 1}, + 0x0C = { 3343, 1}, + 0x0D = { 3344, 1}, + 0x0E = { 3345, 1}, + 0x0F = { 3346, 1}, + 0x10 = { 3347, 16}, + 0x11 = { 3363, 7}, + 0x12 = { 3370, 1}, + 0x13 = { 3371, 1}, + 0x14 = { 3372, 2}, + 0x15 = { 3374, 2}, + 0x16 = { 3376, 2}, + 0x17 = { 3378, 2}, + 0x18 = { 3380, 1}, + 0x19 = { 3381, 1}, + 0x1A = { 3382, 1}, + 0x1B = { 3383, 1}, + 0x1C = { 3384, 1}, + 0x1D = { 3385, 1}, + 0x1E = { 3386, 1}, + 0x1F = { 3387, 1}, + 0x20 = { 3388, 1}, + 0x21 = { 3389, 1}, + 0x22 = { 3390, 1}, + 0x23 = { 3391, 1}, + 0x24 = { 3392, 1}, + 0x25 = { 3393, 1}, + 0x26 = { 3394, 1}, + 0x27 = { 3395, 1}, + 0x28 = { 3396, 1}, + 0x29 = { 3397, 1}, + 0x2A = { 3398, 1}, + 0x2B = { 3399, 1}, + 0x2C = { 3400, 7}, + 0x2D = { 3407, 2}, + 0x2E = { 3409, 4}, + 0x2F = { 3413, 8}, + 0x30 = { 3421, 1}, + 0x31 = { 3422, 1}, + 0x32 = { 3423, 1}, + 0x33 = { 3424, 1}, + 0x34 = { 3425, 1}, + 0x35 = { 3426, 1}, + 0x36 = { 3427, 1}, + 0x37 = { 3428, 3}, + 0x38 = { 3431, 1}, + 0x39 = { 3432, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3345, 6}, - 0xE85 = { 3351, 2}, - 0xE86 = { 3353, 1}, - 0xE87 = { 3354, 1}, - 0xE88 = { 3355, 1}, - 0xE89 = { 3356, 1}, - 0xE8A = { 3357, 1}, - 0xE8B = { 3358, 2}, - 0xE8C = { 3360, 4}, - 0xE8D = { 3364, 6}, - 0xE8E = { 3370, 1}, - 0xE8F = { 3371, 1}, - 0xE90 = { 3372, 1}, - 0xE91 = { 3373, 1}, - 0xE92 = { 3374, 2}, - 0xE93 = { 3376, 1}, - 0xE94 = { 3377, 1}, - 0xE95 = { 3378, 1}, - 0xE96 = { 3379, 1}, - 0xE97 = { 3380, 2}, - 0xE9C = { 3382, 1}, - 0xE9D = { 3383, 1}, - 0xE9E = { 3384, 1}, - 0xE9F = { 3385, 1}, - 0xEA0 = { 3386, 1}, - 0xEA1 = { 3387, 2}, - 0xEA2 = { 3389, 1}, - 0xEA3 = { 3390, 1}, - 0xEA4 = { 3391, 6}, - 0xEA5 = { 3397, 2}, - 0xEA6 = { 3399, 1}, - 0xEA7 = { 3400, 1}, - 0xEA8 = { 3401, 1}, - 0xEA9 = { 3402, 2}, - 0xEB1 = { 3404, 1}, - 0xEB4 = { 3405, 1}, - 0xEB5 = { 3406, 1}, - 0xEB6 = { 3407, 1}, - 0xEB7 = { 3408, 1}, - 0xEBB = { 3409, 1}, - 0xEBC = { 3410, 1}, - 0xEBD = { 3411, 1}, - 0xEC0 = { 3412, 2}, - 0xEC1 = { 3414, 1}, - 0xEC2 = { 3415, 3}, - 0xEC3 = { 3418, 2}, - 0xEC4 = { 3420, 2}, - 0xEC5 = { 3422, 1}, - 0xEC6 = { 3423, 7}, - 0xEC7 = { 3430, 2}, - 0xEC8 = { 3432, 1}, - 0xEC9 = { 3433, 1}, - 0xECA = { 3434, 2}, - 0xECB = { 3436, 2}, - 0xECC = { 3438, 1}, - 0xECD = { 3439, 1}, - 0xECE = { 3440, 2}, - 0xECF = { 3442, 2}, - 0xED6 = { 3444, 4}, - 0xED8 = { 3448, 4}, - 0xED9 = { 3452, 4}, - 0xEDC = { 3456, 4}, - 0xEDD = { 3460, 4}, - 0xEE0 = { 3464, 24}, - 0xEE1 = { 3488, 23}, - 0xEE2 = { 3511, 22}, - 0xEE3 = { 3533, 29}, - 0xEE4 = { 3562, 23}, - 0xEE5 = { 3585, 22}, - 0xEE6 = { 3607, 22}, - 0xEE7 = { 3629, 29}, - 0xEE8 = { 3658, 28}, - 0xEE9 = { 3686, 12}, - 0xEEA = { 3698, 13}, - 0xEEB = { 3711, 18}, - 0xEEC = { 3729, 27}, - 0xEED = { 3756, 13}, - 0xEEE = { 3769, 22}, - 0xEEF = { 3791, 23}, - 0xEF0 = { 3814, 15}, - 0xEF1 = { 3829, 15}, - 0xEF2 = { 3844, 15}, - 0xEF3 = { 3859, 15}, - 0xEF4 = { 3874, 15}, - 0xEF5 = { 3889, 15}, - 0xEF6 = { 3904, 15}, - 0xEF7 = { 3919, 15}, - 0xEF8 = { 3934, 3}, - 0xEF9 = { 3937, 3}, - 0xEFA = { 3940, 3}, - 0xEFB = { 3943, 3}, - 0xEFC = { 3946, 3}, - 0xEFD = { 3949, 3}, - 0xEFE = { 3952, 3}, - 0xEFF = { 3955, 3}, - 0xF00 = { 3958, 11}, - 0xF01 = { 3969, 10}, - 0xF02 = { 3979, 8}, - 0xF03 = { 3987, 8}, - 0xF04 = { 3995, 8}, - 0xF05 = { 4003, 5}, - 0xF06 = { 4008, 5}, - 0xF07 = { 4013, 5}, - 0xF08 = { 4018, 6}, - 0xF09 = { 4024, 6}, - 0xF0A = { 4030, 4}, - 0xF0B = { 4034, 4}, - 0xF0C = { 4038, 4}, - 0xF0D = { 4042, 3}, - 0xF0E = { 4045, 4}, - 0xF0F = { 4049, 4}, - 0xF10 = { 4053, 7}, - 0xF11 = { 4060, 7}, - 0xF12 = { 4067, 6}, - 0xF13 = { 4073, 6}, - 0xF14 = { 4079, 5}, - 0xF15 = { 4084, 4}, - 0xF16 = { 4088, 5}, - 0xF17 = { 4093, 5}, - 0xF18 = { 4098, 5}, - 0xF19 = { 4103, 4}, - 0xF1A = { 4107, 4}, - 0xF1B = { 4111, 5}, - 0xF1C = { 4116, 5}, - 0xF1D = { 4121, 4}, - 0xF1E = { 4125, 4}, - 0xF1F = { 4129, 4}, - 0xF20 = { 4133, 5}, - 0xF21 = { 4138, 4}, - 0xF22 = { 4142, 4}, - 0xF23 = { 4146, 4}, - 0xF24 = { 4150, 5}, - 0xF25 = { 4155, 3}, - 0xF26 = { 4158, 4}, - 0xF27 = { 4162, 4}, - 0xF28 = { 4166, 5}, - 0xF29 = { 4171, 4}, - 0xF2A = { 4175, 4}, - 0xF2B = { 4179, 4}, - 0xF2C = { 4183, 5}, - 0xF2D = { 4188, 3}, - 0xF2E = { 4191, 4}, - 0xF2F = { 4195, 4}, - 0xF30 = { 4199, 6}, - 0xF31 = { 4205, 4}, - 0xF32 = { 4209, 6}, - 0xF33 = { 4215, 4}, - 0xF34 = { 4219, 5}, - 0xF35 = { 4224, 3}, - 0xF36 = { 4227, 6}, - 0xF37 = { 4233, 4}, - 0xF38 = { 4237, 7}, - 0xF39 = { 4244, 4}, - 0xF3A = { 4248, 19}, - 0xF3B = { 4267, 9}, - 0xF3C = { 4276, 5}, - 0xF3D = { 4281, 3}, - 0xF3E = { 4284, 5}, - 0xF3F = { 4289, 4}, - 0xF40 = { 4293, 6}, - 0xF41 = { 4299, 6}, - 0xF42 = { 4305, 5}, - 0xF43 = { 4310, 5}, - 0xF44 = { 4315, 6}, - 0xF45 = { 4321, 5}, - 0xF46 = { 4326, 5}, - 0xF47 = { 4331, 5}, - 0xF48 = { 4336, 6}, - 0xF49 = { 4342, 6}, - 0xF4A = { 4348, 4}, - 0xF4B = { 4352, 4}, - 0xF4C = { 4356, 4}, - 0xF4D = { 4360, 3}, - 0xF4E = { 4363, 4}, - 0xF4F = { 4367, 4}, - 0xF50 = { 4371, 5}, - 0xF51 = { 4376, 5}, - 0xF52 = { 4381, 4}, - 0xF53 = { 4385, 4}, - 0xF54 = { 4389, 5}, - 0xF55 = { 4394, 4}, - 0xF56 = { 4398, 5}, - 0xF57 = { 4403, 5}, - 0xF58 = { 4408, 5}, - 0xF59 = { 4413, 4}, - 0xF5A = { 4417, 4}, - 0xF5B = { 4421, 5}, - 0xF5C = { 4426, 5}, - 0xF5D = { 4431, 4}, - 0xF5E = { 4435, 4}, - 0xF5F = { 4439, 4}, - 0xF60 = { 4443, 5}, - 0xF61 = { 4448, 4}, - 0xF62 = { 4452, 4}, - 0xF63 = { 4456, 4}, - 0xF64 = { 4460, 5}, - 0xF65 = { 4465, 3}, - 0xF66 = { 4468, 4}, - 0xF67 = { 4472, 4}, - 0xF68 = { 4476, 5}, - 0xF69 = { 4481, 4}, - 0xF6A = { 4485, 4}, - 0xF6B = { 4489, 4}, - 0xF6C = { 4493, 5}, - 0xF6D = { 4498, 3}, - 0xF6E = { 4501, 4}, - 0xF6F = { 4505, 4}, - 0xF70 = { 4509, 5}, - 0xF71 = { 4514, 4}, - 0xF72 = { 4518, 4}, - 0xF73 = { 4522, 4}, - 0xF74 = { 4526, 4}, - 0xF75 = { 4530, 3}, - 0xF76 = { 4533, 4}, - 0xF77 = { 4537, 4}, - 0xF78 = { 4541, 8}, - 0xF79 = { 4549, 4}, - 0xF7A = { 4553, 4}, - 0xF7B = { 4557, 4}, - 0xF7C = { 4561, 4}, - 0xF7D = { 4565, 3}, - 0xF7E = { 4568, 4}, - 0xF7F = { 4572, 5}, - 0xF80 = { 4577, 1}, - 0xF81 = { 4578, 1}, - 0xF82 = { 4579, 1}, - 0xF83 = { 4580, 2}, - 0xF84 = { 4582, 1}, - 0xF85 = { 4583, 2}, - 0xF88 = { 4585, 1}, - 0xF89 = { 4586, 2}, - 0xF8A = { 4588, 1}, - 0xF8B = { 4589, 1}, - 0xF8C = { 4590, 1}, - 0xF8D = { 4591, 2}, - 0xF91 = { 4593, 1}, - 0xF93 = { 4594, 1}, - 0xF99 = { 4595, 2}, - 0xF9B = { 4597, 1}, - 0xFA0 = { 4598, 3}, - 0xFA1 = { 4601, 2}, - 0xFA2 = { 4603, 3}, - 0xFA3 = { 4606, 2}, - 0xFA4 = { 4608, 3}, - 0xFA5 = { 4611, 2}, - 0xFA6 = { 4613, 1}, - 0xFA8 = { 4614, 10}, - 0xFA9 = { 4624, 10}, - 0xFAA = { 4634, 6}, - 0xFAB = { 4640, 1}, - 0xFAC = { 4641, 6}, - 0xFAD = { 4647, 6}, - 0xFAE = { 4653, 6}, - 0xFB0 = { 4659, 3}, - 0xFB5 = { 4662, 1}, - 0xFB8 = { 4663, 1}, - 0xFB9 = { 4664, 1}, - 0xFBA = { 4665, 1}, - 0xFBB = { 4666, 1}, - 0xFBC = { 4667, 1}, - 0xFBE = { 4668, 1}, - 0xFC0 = { 4669, 1}, - 0xFC1 = { 4670, 1}, - 0xFC2 = { 4671, 3}, - 0xFC3 = { 4674, 3}, - 0xFC4 = { 4677, 1}, - 0xFC5 = { 4678, 1}, - 0xFC6 = { 4679, 2}, - 0xFC7 = { 4681, 2}, - 0xFC8 = { 4683, 7}, - 0xFC9 = { 4690, 11}, - 0xFCA = { 4701, 3}, - 0xFCB = { 4704, 3}, - 0xFCC = { 4707, 7}, - 0xFCD = { 4714, 7}, - 0xFCE = { 4721, 2}, - 0xFCF = { 4723, 2}, - 0xFD2 = { 4725, 1}, - 0xFD3 = { 4726, 1}, - 0xFD9 = { 4727, 4}, - 0xFDA = { 4731, 1}, - 0xFDB = { 4732, 1}, - 0xFE0 = { 4733, 28}, - 0xFE1 = { 4761, 26}, - 0xFE2 = { 4787, 26}, - 0xFE3 = { 4813, 32}, - 0xFE4 = { 4845, 29}, - 0xFE5 = { 4874, 27}, - 0xFE6 = { 4901, 27}, - 0xFE7 = { 4928, 33}, - 0xFE8 = { 4961, 32}, - 0xFE9 = { 4993, 17}, - 0xFEA = { 5010, 17}, - 0xFEB = { 5027, 29}, - 0xFEC = { 5056, 31}, - 0xFED = { 5087, 18}, - 0xFEE = { 5105, 26}, - 0xFEF = { 5131, 32}, - 0xFF0 = { 5163, 19}, - 0xFF1 = { 5182, 18}, - 0xFF2 = { 5200, 17}, - 0xFF3 = { 5217, 17}, - 0xFF4 = { 5234, 19}, - 0xFF5 = { 5253, 18}, - 0xFF6 = { 5271, 17}, - 0xFF7 = { 5288, 17}, - 0xFF8 = { 5305, 4}, - 0xFF9 = { 5309, 4}, - 0xFFA = { 5313, 4}, - 0xFFB = { 5317, 17}, - 0xFFC = { 5334, 4}, - 0xFFD = { 5338, 4}, - 0xFFE = { 5342, 4}, - 0xFFF = { 5346, 17}, + 0xE84 = { 3433, 6}, + 0xE85 = { 3439, 2}, + 0xE86 = { 3441, 1}, + 0xE87 = { 3442, 1}, + 0xE88 = { 3443, 1}, + 0xE89 = { 3444, 1}, + 0xE8A = { 3445, 1}, + 0xE8B = { 3446, 2}, + 0xE8C = { 3448, 4}, + 0xE8D = { 3452, 6}, + 0xE8E = { 3458, 1}, + 0xE8F = { 3459, 1}, + 0xE90 = { 3460, 1}, + 0xE91 = { 3461, 1}, + 0xE92 = { 3462, 2}, + 0xE93 = { 3464, 1}, + 0xE94 = { 3465, 1}, + 0xE95 = { 3466, 1}, + 0xE96 = { 3467, 1}, + 0xE97 = { 3468, 2}, + 0xE9C = { 3470, 1}, + 0xE9D = { 3471, 1}, + 0xE9E = { 3472, 1}, + 0xE9F = { 3473, 1}, + 0xEA0 = { 3474, 1}, + 0xEA1 = { 3475, 2}, + 0xEA2 = { 3477, 1}, + 0xEA3 = { 3478, 1}, + 0xEA4 = { 3479, 6}, + 0xEA5 = { 3485, 2}, + 0xEA6 = { 3487, 1}, + 0xEA7 = { 3488, 1}, + 0xEA8 = { 3489, 1}, + 0xEA9 = { 3490, 2}, + 0xEB1 = { 3492, 1}, + 0xEB4 = { 3493, 1}, + 0xEB5 = { 3494, 1}, + 0xEB6 = { 3495, 1}, + 0xEB7 = { 3496, 1}, + 0xEBB = { 3497, 1}, + 0xEBC = { 3498, 1}, + 0xEBD = { 3499, 1}, + 0xEC0 = { 3500, 2}, + 0xEC1 = { 3502, 1}, + 0xEC2 = { 3503, 3}, + 0xEC3 = { 3506, 2}, + 0xEC4 = { 3508, 2}, + 0xEC5 = { 3510, 1}, + 0xEC6 = { 3511, 7}, + 0xEC7 = { 3518, 2}, + 0xEC8 = { 3520, 1}, + 0xEC9 = { 3521, 1}, + 0xECA = { 3522, 2}, + 0xECB = { 3524, 2}, + 0xECC = { 3526, 1}, + 0xECD = { 3527, 1}, + 0xECE = { 3528, 2}, + 0xECF = { 3530, 2}, + 0xED6 = { 3532, 4}, + 0xED8 = { 3536, 4}, + 0xED9 = { 3540, 4}, + 0xEDC = { 3544, 4}, + 0xEDD = { 3548, 4}, + 0xEE0 = { 3552, 24}, + 0xEE1 = { 3576, 23}, + 0xEE2 = { 3599, 22}, + 0xEE3 = { 3621, 29}, + 0xEE4 = { 3650, 23}, + 0xEE5 = { 3673, 22}, + 0xEE6 = { 3695, 22}, + 0xEE7 = { 3717, 29}, + 0xEE8 = { 3746, 28}, + 0xEE9 = { 3774, 12}, + 0xEEA = { 3786, 13}, + 0xEEB = { 3799, 18}, + 0xEEC = { 3817, 27}, + 0xEED = { 3844, 13}, + 0xEEE = { 3857, 22}, + 0xEEF = { 3879, 23}, + 0xEF0 = { 3902, 15}, + 0xEF1 = { 3917, 15}, + 0xEF2 = { 3932, 15}, + 0xEF3 = { 3947, 15}, + 0xEF4 = { 3962, 15}, + 0xEF5 = { 3977, 15}, + 0xEF6 = { 3992, 15}, + 0xEF7 = { 4007, 15}, + 0xEF8 = { 4022, 3}, + 0xEF9 = { 4025, 3}, + 0xEFA = { 4028, 3}, + 0xEFB = { 4031, 3}, + 0xEFC = { 4034, 3}, + 0xEFD = { 4037, 3}, + 0xEFE = { 4040, 3}, + 0xEFF = { 4043, 3}, + 0xF00 = { 4046, 11}, + 0xF01 = { 4057, 10}, + 0xF02 = { 4067, 8}, + 0xF03 = { 4075, 8}, + 0xF04 = { 4083, 8}, + 0xF05 = { 4091, 5}, + 0xF06 = { 4096, 5}, + 0xF07 = { 4101, 5}, + 0xF08 = { 4106, 6}, + 0xF09 = { 4112, 6}, + 0xF0A = { 4118, 4}, + 0xF0B = { 4122, 4}, + 0xF0C = { 4126, 4}, + 0xF0D = { 4130, 3}, + 0xF0E = { 4133, 4}, + 0xF0F = { 4137, 4}, + 0xF10 = { 4141, 7}, + 0xF11 = { 4148, 7}, + 0xF12 = { 4155, 6}, + 0xF13 = { 4161, 6}, + 0xF14 = { 4167, 5}, + 0xF15 = { 4172, 4}, + 0xF16 = { 4176, 5}, + 0xF17 = { 4181, 5}, + 0xF18 = { 4186, 5}, + 0xF19 = { 4191, 4}, + 0xF1A = { 4195, 4}, + 0xF1B = { 4199, 5}, + 0xF1C = { 4204, 5}, + 0xF1D = { 4209, 4}, + 0xF1E = { 4213, 4}, + 0xF1F = { 4217, 4}, + 0xF20 = { 4221, 5}, + 0xF21 = { 4226, 4}, + 0xF22 = { 4230, 4}, + 0xF23 = { 4234, 4}, + 0xF24 = { 4238, 5}, + 0xF25 = { 4243, 3}, + 0xF26 = { 4246, 4}, + 0xF27 = { 4250, 4}, + 0xF28 = { 4254, 5}, + 0xF29 = { 4259, 4}, + 0xF2A = { 4263, 4}, + 0xF2B = { 4267, 4}, + 0xF2C = { 4271, 5}, + 0xF2D = { 4276, 3}, + 0xF2E = { 4279, 4}, + 0xF2F = { 4283, 4}, + 0xF30 = { 4287, 6}, + 0xF31 = { 4293, 4}, + 0xF32 = { 4297, 6}, + 0xF33 = { 4303, 4}, + 0xF34 = { 4307, 5}, + 0xF35 = { 4312, 3}, + 0xF36 = { 4315, 6}, + 0xF37 = { 4321, 4}, + 0xF38 = { 4325, 7}, + 0xF39 = { 4332, 4}, + 0xF3A = { 4336, 19}, + 0xF3B = { 4355, 9}, + 0xF3C = { 4364, 5}, + 0xF3D = { 4369, 3}, + 0xF3E = { 4372, 5}, + 0xF3F = { 4377, 4}, + 0xF40 = { 4381, 6}, + 0xF41 = { 4387, 6}, + 0xF42 = { 4393, 5}, + 0xF43 = { 4398, 5}, + 0xF44 = { 4403, 6}, + 0xF45 = { 4409, 5}, + 0xF46 = { 4414, 5}, + 0xF47 = { 4419, 5}, + 0xF48 = { 4424, 6}, + 0xF49 = { 4430, 6}, + 0xF4A = { 4436, 4}, + 0xF4B = { 4440, 4}, + 0xF4C = { 4444, 4}, + 0xF4D = { 4448, 3}, + 0xF4E = { 4451, 4}, + 0xF4F = { 4455, 4}, + 0xF50 = { 4459, 5}, + 0xF51 = { 4464, 5}, + 0xF52 = { 4469, 4}, + 0xF53 = { 4473, 4}, + 0xF54 = { 4477, 5}, + 0xF55 = { 4482, 4}, + 0xF56 = { 4486, 5}, + 0xF57 = { 4491, 5}, + 0xF58 = { 4496, 5}, + 0xF59 = { 4501, 4}, + 0xF5A = { 4505, 4}, + 0xF5B = { 4509, 5}, + 0xF5C = { 4514, 5}, + 0xF5D = { 4519, 4}, + 0xF5E = { 4523, 4}, + 0xF5F = { 4527, 4}, + 0xF60 = { 4531, 5}, + 0xF61 = { 4536, 4}, + 0xF62 = { 4540, 4}, + 0xF63 = { 4544, 4}, + 0xF64 = { 4548, 5}, + 0xF65 = { 4553, 3}, + 0xF66 = { 4556, 4}, + 0xF67 = { 4560, 4}, + 0xF68 = { 4564, 5}, + 0xF69 = { 4569, 4}, + 0xF6A = { 4573, 4}, + 0xF6B = { 4577, 4}, + 0xF6C = { 4581, 5}, + 0xF6D = { 4586, 3}, + 0xF6E = { 4589, 4}, + 0xF6F = { 4593, 4}, + 0xF70 = { 4597, 5}, + 0xF71 = { 4602, 4}, + 0xF72 = { 4606, 4}, + 0xF73 = { 4610, 4}, + 0xF74 = { 4614, 4}, + 0xF75 = { 4618, 3}, + 0xF76 = { 4621, 4}, + 0xF77 = { 4625, 4}, + 0xF78 = { 4629, 8}, + 0xF79 = { 4637, 4}, + 0xF7A = { 4641, 4}, + 0xF7B = { 4645, 4}, + 0xF7C = { 4649, 4}, + 0xF7D = { 4653, 3}, + 0xF7E = { 4656, 4}, + 0xF7F = { 4660, 5}, + 0xF80 = { 4665, 1}, + 0xF81 = { 4666, 1}, + 0xF82 = { 4667, 1}, + 0xF83 = { 4668, 2}, + 0xF84 = { 4670, 1}, + 0xF85 = { 4671, 2}, + 0xF88 = { 4673, 1}, + 0xF89 = { 4674, 2}, + 0xF8A = { 4676, 1}, + 0xF8B = { 4677, 1}, + 0xF8C = { 4678, 1}, + 0xF8D = { 4679, 2}, + 0xF91 = { 4681, 1}, + 0xF93 = { 4682, 1}, + 0xF99 = { 4683, 2}, + 0xF9B = { 4685, 1}, + 0xFA0 = { 4686, 3}, + 0xFA1 = { 4689, 2}, + 0xFA2 = { 4691, 3}, + 0xFA3 = { 4694, 2}, + 0xFA4 = { 4696, 3}, + 0xFA5 = { 4699, 2}, + 0xFA6 = { 4701, 1}, + 0xFA8 = { 4702, 10}, + 0xFA9 = { 4712, 10}, + 0xFAA = { 4722, 6}, + 0xFAB = { 4728, 1}, + 0xFAC = { 4729, 6}, + 0xFAD = { 4735, 6}, + 0xFAE = { 4741, 6}, + 0xFB0 = { 4747, 3}, + 0xFB5 = { 4750, 1}, + 0xFB8 = { 4751, 1}, + 0xFB9 = { 4752, 1}, + 0xFBA = { 4753, 1}, + 0xFBB = { 4754, 1}, + 0xFBC = { 4755, 1}, + 0xFBE = { 4756, 1}, + 0xFC0 = { 4757, 1}, + 0xFC1 = { 4758, 1}, + 0xFC2 = { 4759, 3}, + 0xFC3 = { 4762, 3}, + 0xFC4 = { 4765, 1}, + 0xFC5 = { 4766, 1}, + 0xFC6 = { 4767, 2}, + 0xFC7 = { 4769, 2}, + 0xFC8 = { 4771, 7}, + 0xFC9 = { 4778, 11}, + 0xFCA = { 4789, 3}, + 0xFCB = { 4792, 3}, + 0xFCC = { 4795, 7}, + 0xFCD = { 4802, 7}, + 0xFCE = { 4809, 2}, + 0xFCF = { 4811, 2}, + 0xFD2 = { 4813, 1}, + 0xFD3 = { 4814, 1}, + 0xFD9 = { 4815, 4}, + 0xFDA = { 4819, 1}, + 0xFDB = { 4820, 1}, + 0xFE0 = { 4821, 28}, + 0xFE1 = { 4849, 26}, + 0xFE2 = { 4875, 26}, + 0xFE3 = { 4901, 32}, + 0xFE4 = { 4933, 29}, + 0xFE5 = { 4962, 27}, + 0xFE6 = { 4989, 27}, + 0xFE7 = { 5016, 33}, + 0xFE8 = { 5049, 32}, + 0xFE9 = { 5081, 17}, + 0xFEA = { 5098, 17}, + 0xFEB = { 5115, 29}, + 0xFEC = { 5144, 31}, + 0xFED = { 5175, 18}, + 0xFEE = { 5193, 26}, + 0xFEF = { 5219, 32}, + 0xFF0 = { 5251, 19}, + 0xFF1 = { 5270, 18}, + 0xFF2 = { 5288, 17}, + 0xFF3 = { 5305, 17}, + 0xFF4 = { 5322, 19}, + 0xFF5 = { 5341, 18}, + 0xFF6 = { 5359, 17}, + 0xFF7 = { 5376, 17}, + 0xFF8 = { 5393, 4}, + 0xFF9 = { 5397, 4}, + 0xFFA = { 5401, 4}, + 0xFFB = { 5405, 17}, + 0xFFC = { 5422, 4}, + 0xFFD = { 5426, 4}, + 0xFFE = { 5430, 4}, + 0xFFF = { 5434, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index cbaef5e62..b2bc611f0 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1663]lib.Encoding{ +ENCODE_FORMS := [1701]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -549,12 +549,12 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MRS - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.MRS_SPEC_REG,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CPS { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, // .SETEND - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.SETEND_ENDIAN,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, // .NOP { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, @@ -578,7 +578,7 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .SEVL { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, // .DBG - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.DBG_OPTION,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .HINT { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, // .DMB @@ -834,10 +834,30 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .SWPB { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, - // .RFE - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, - // .SRS - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEDA + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEDB + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEIA + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEIB + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSDA + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSDB + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSIA + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSIB + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, // .CDP { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, // .CDP2 @@ -1147,9 +1167,9 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VMRS - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RT_A32,.VFP_SPEC_REG,.NONE,.NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.VFP_SPEC_REG,.RT_A32,.NONE,.NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDR { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1404,10 +1424,34 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBIC + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORR + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -2495,354 +2539,360 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .POP = { 585, 3}, .SWP = { 588, 1}, .SWPB = { 589, 1}, - .RFE = { 590, 1}, - .SRS = { 591, 1}, - .CDP = { 592, 1}, - .CDP2 = { 593, 1}, - .MCR = { 594, 1}, - .MCR2 = { 595, 1}, - .MRC = { 596, 1}, - .MRC2 = { 597, 1}, - .MCRR = { 598, 1}, - .MCRR2 = { 599, 1}, - .MRRC = { 600, 1}, - .MRRC2 = { 601, 1}, - .LDC = { 602, 1}, - .LDC2 = { 603, 1}, - .STC = { 604, 1}, - .STC2 = { 605, 1}, - .CRC32B = { 606, 1}, - .CRC32H = { 607, 1}, - .CRC32W = { 608, 1}, - .CRC32CB = { 609, 1}, - .CRC32CH = { 610, 1}, - .CRC32CW = { 611, 1}, - .VADD = { 612, 18}, - .VSUB = { 630, 18}, - .VMUL = { 648, 22}, - .VDIV = { 670, 3}, - .VMLA = { 673, 16}, - .VMLS = { 689, 15}, - .VNMUL = { 704, 2}, - .VNMLA = { 706, 2}, - .VNMLS = { 708, 2}, - .VFMA = { 710, 8}, - .VFMS = { 718, 6}, - .VFNMA = { 724, 3}, - .VFNMS = { 727, 3}, - .VABS = { 730, 12}, - .VNEG = { 742, 12}, - .VSQRT = { 754, 3}, - .VCMP = { 757, 8}, - .VCMPE = { 765, 4}, - .VCVT = { 769, 35}, - .VCVTB = { 804, 2}, - .VCVTT = { 806, 2}, - .VCVTA = { 808, 2}, - .VCVTN = { 810, 2}, - .VCVTP = { 812, 2}, - .VCVTM = { 814, 2}, - .VCVTR = { 816, 4}, - .VMOV = { 820, 33}, - .VMRS = { 853, 1}, - .VMSR = { 854, 1}, - .VLDR = { 855, 2}, - .VSTR = { 857, 2}, - .VLDM = { 859, 2}, - .VSTM = { 861, 2}, - .VPUSH = { 863, 2}, - .VPOP = { 865, 2}, - .VSEL = { 867, 2}, - .VMAXNM = { 869, 2}, - .VMINNM = { 871, 2}, - .VRINTA = { 873, 3}, - .VRINTN = { 876, 3}, - .VRINTP = { 879, 3}, - .VRINTM = { 882, 3}, - .VRINTR = { 885, 2}, - .VRINTZ = { 887, 3}, - .VRINTX = { 890, 3}, - .VADDL = { 893, 6}, - .VADDW = { 899, 6}, - .VSUBL = { 905, 6}, - .VSUBW = { 911, 6}, - .VHADD = { 917, 9}, - .VHSUB = { 926, 9}, - .VRHADD = { 935, 3}, - .VQADD = { 938, 11}, - .VQSUB = { 949, 11}, - .VMULL = { 960, 11}, - .VMLAL = { 971, 10}, - .VMLSL = { 981, 10}, - .VQDMULL = { 991, 4}, - .VQDMLAL = { 995, 4}, - .VQDMLSL = { 999, 4}, - .VQDMULH = { 1003, 8}, - .VQRDMULH = { 1011, 8}, - .VQRDMLAH = { 1019, 8}, - .VQRDMLSH = { 1027, 8}, - .VABA = { 1035, 8}, - .VABAL = { 1043, 6}, - .VABD = { 1049, 10}, - .VABDL = { 1059, 6}, - .VAND = { 1065, 3}, - .VBIC = { 1068, 3}, - .VORR = { 1071, 3}, - .VORN = { 1074, 3}, - .VEOR = { 1077, 3}, - .VBSL = { 1080, 2}, - .VBIT = { 1082, 2}, - .VBIF = { 1084, 2}, - .VMVN = { 1086, 13}, - .VMOVN = { 1099, 3}, - .VQMOVN = { 1102, 6}, - .VQMOVUN = { 1108, 3}, - .VMOVL = { 1111, 6}, - .VTST = { 1117, 6}, - .VCEQ = { 1123, 14}, - .VCGE = { 1137, 16}, - .VCGT = { 1153, 16}, - .VCLE = { 1169, 18}, - .VCLT = { 1187, 18}, - .VACGE = { 1205, 2}, - .VACGT = { 1207, 2}, - .VACLE = { 1209, 2}, - .VACLT = { 1211, 2}, - .VMAX = { 1213, 13}, - .VMIN = { 1226, 13}, - .VPMAX = { 1239, 5}, - .VPMIN = { 1244, 5}, - .VPADD = { 1249, 5}, - .VPADDL = { 1254, 6}, - .VPADAL = { 1260, 4}, - .VRECPE = { 1264, 4}, - .VRECPS = { 1268, 2}, - .VRSQRTE = { 1270, 4}, - .VRSQRTS = { 1274, 2}, - .VSHL = { 1276, 9}, - .VSHR = { 1285, 3}, - .VSRA = { 1288, 3}, - .VRSHL = { 1291, 5}, - .VRSHR = { 1296, 3}, - .VRSRA = { 1299, 2}, - .VSLI = { 1301, 2}, - .VSRI = { 1303, 2}, - .VQSHL = { 1305, 7}, - .VQSHRN = { 1312, 1}, - .VQSHRUN = { 1313, 1}, - .VQRSHL = { 1314, 16}, - .VQRSHRN = { 1330, 1}, - .VQRSHRUN = { 1331, 1}, - .VSHRN = { 1332, 1}, - .VRSHRN = { 1333, 1}, - .VSHLL = { 1334, 4}, - .VCLS = { 1338, 6}, - .VCLZ = { 1344, 6}, - .VCNT = { 1350, 2}, - .VREV16 = { 1352, 2}, - .VREV32 = { 1354, 4}, - .VREV64 = { 1358, 6}, - .VEXT = { 1364, 2}, - .VTBL = { 1366, 4}, - .VTBX = { 1370, 4}, - .VTRN = { 1374, 6}, - .VUZP = { 1380, 5}, - .VZIP = { 1385, 5}, - .VDUP = { 1390, 5}, - .VSWP = { 1395, 2}, - .VLD1 = { 1397, 8}, - .VLD2 = { 1405, 6}, - .VLD3 = { 1411, 5}, - .VLD4 = { 1416, 5}, - .VST1 = { 1421, 7}, - .VST2 = { 1428, 6}, - .VST3 = { 1434, 5}, - .VST4 = { 1439, 5}, - .AESE = { 1444, 1}, - .AESD = { 1445, 1}, - .AESMC = { 1446, 1}, - .AESIMC = { 1447, 1}, - .SHA1H = { 1448, 1}, - .SHA1SU0 = { 1449, 1}, - .SHA1SU1 = { 1450, 1}, - .SHA1C = { 1451, 1}, - .SHA1M = { 1452, 1}, - .SHA1P = { 1453, 1}, - .SHA256H = { 1454, 1}, - .SHA256H2 = { 1455, 1}, - .SHA256SU0 = { 1456, 1}, - .SHA256SU1 = { 1457, 1}, - .VJCVT = { 1458, 1}, - .VSDOT = { 1459, 4}, - .VUDOT = { 1463, 4}, - .VDOT = { 1467, 2}, - .VMMLA = { 1469, 1}, - .VFMAL = { 1470, 2}, - .VFMSL = { 1472, 2}, - .VCMLA = { 1474, 5}, - .VCADD = { 1479, 2}, - .VSMMLA = { 1481, 1}, - .VUMMLA = { 1482, 1}, - .VUSMMLA = { 1483, 1}, - .VSUDOT = { 1484, 2}, - .VUSDOT = { 1486, 4}, - .VQABS = { 1490, 1}, - .VQNEG = { 1491, 1}, - .VMOVX = { 1492, 1}, - .VINS = { 1493, 1}, - .VLD2R = { 1494, 1}, - .VLD3R = { 1495, 1}, - .VLD4R = { 1496, 1}, - .IT = { 1497, 1}, - .TT = { 1498, 1}, - .TTT = { 1499, 1}, - .TTA = { 1500, 1}, - .TTAT = { 1501, 1}, - .SG = { 1502, 1}, - .BXNS = { 1503, 1}, - .BLXNS = { 1504, 1}, - .PAC = { 1505, 1}, - .PACBTI = { 1506, 1}, - .AUT = { 1507, 1}, - .AUTG = { 1508, 1}, - .BTI = { 1509, 1}, - .WLS = { 1510, 1}, - .WLSTP = { 1511, 1}, - .DLS = { 1512, 1}, - .DLSTP = { 1513, 1}, - .LE = { 1514, 1}, - .LETP = { 1515, 1}, - .LCTP = { 1516, 1}, - .BF = { 1517, 1}, - .BFX = { 1518, 1}, - .BFL = { 1519, 1}, - .BFLX = { 1520, 1}, - .BFCSEL = { 1521, 1}, - .CX1 = { 1522, 1}, - .CX1A = { 1523, 1}, - .CX1D = { 1524, 1}, - .CX1DA = { 1525, 1}, - .CX2 = { 1526, 1}, - .CX2A = { 1527, 1}, - .CX2D = { 1528, 1}, - .CX2DA = { 1529, 1}, - .CX3 = { 1530, 1}, - .CX3A = { 1531, 1}, - .CX3D = { 1532, 1}, - .CX3DA = { 1533, 1}, - .VCX1 = { 1534, 2}, - .VCX1A = { 1536, 2}, - .VCX2 = { 1538, 2}, - .VCX2A = { 1540, 2}, - .VCX3 = { 1542, 2}, - .VCX3A = { 1544, 2}, - .VPT = { 1546, 1}, - .VPST = { 1547, 1}, - .VPSEL = { 1548, 1}, - .VPNOT = { 1549, 1}, - .VCTP = { 1550, 1}, - .VADDV = { 1551, 1}, - .VADDVA = { 1552, 1}, - .VADDLV = { 1553, 1}, - .VADDLVA = { 1554, 1}, - .VMAXV = { 1555, 1}, - .VMAXAV = { 1556, 1}, - .VMINV = { 1557, 1}, - .VMINAV = { 1558, 1}, - .VMAXNMV = { 1559, 1}, - .VMAXNMAV = { 1560, 1}, - .VMINNMV = { 1561, 1}, - .VMINNMAV = { 1562, 1}, - .VABAV = { 1563, 1}, - .VMLADAV = { 1564, 1}, - .VMLADAVA = { 1565, 1}, - .VMLADAVX = { 1566, 1}, - .VMLADAVAX = { 1567, 1}, - .VMLALDAV = { 1568, 1}, - .VMLALDAVA = { 1569, 1}, - .VMLALDAVX = { 1570, 1}, - .VMLALDAVAX = { 1571, 1}, - .VMLSDAV = { 1572, 1}, - .VMLSDAVA = { 1573, 1}, - .VMLSDAVX = { 1574, 1}, - .VMLSDAVAX = { 1575, 1}, - .VMLSLDAV = { 1576, 1}, - .VMLSLDAVA = { 1577, 1}, - .VMLSLDAVX = { 1578, 1}, - .VMLSLDAVAX = { 1579, 1}, - .VRMLALDAVH = { 1580, 1}, - .VRMLALDAVHA = { 1581, 1}, - .VRMLALDAVHX = { 1582, 1}, - .VRMLALDAVHAX = { 1583, 1}, - .VRMLSLDAVH = { 1584, 1}, - .VRMLSLDAVHA = { 1585, 1}, - .VRMLSLDAVHX = { 1586, 1}, - .VRMLSLDAVHAX = { 1587, 1}, - .VMLAV = { 1588, 1}, - .VMLAVA = { 1589, 1}, - .VMLSV = { 1590, 1}, - .VMLSVA = { 1591, 1}, - .VCMUL = { 1592, 1}, - .VHCADD = { 1593, 2}, - .VBRSR = { 1595, 1}, - .VSHLC = { 1596, 1}, - .VDDUP = { 1597, 1}, - .VIDUP = { 1598, 1}, - .VDWDUP = { 1599, 1}, - .VIWDUP = { 1600, 1}, - .VMOVNB = { 1601, 1}, - .VMOVNT = { 1602, 1}, - .VQMOVNB = { 1603, 1}, - .VQMOVNT = { 1604, 1}, - .VQMOVUNB = { 1605, 1}, - .VQMOVUNT = { 1606, 1}, - .VSHLLB = { 1607, 1}, - .VSHLLT = { 1608, 1}, - .VMULLB = { 1609, 1}, - .VMULLT = { 1610, 1}, - .VMLALB = { 1611, 1}, - .VMLALT = { 1612, 1}, - .VMLSLB = { 1613, 1}, - .VMLSLT = { 1614, 1}, - .VSHRNB = { 1615, 1}, - .VSHRNT = { 1616, 1}, - .VRSHRNB = { 1617, 1}, - .VRSHRNT = { 1618, 1}, - .VQSHRNB = { 1619, 1}, - .VQSHRNT = { 1620, 1}, - .VQRSHRNB = { 1621, 1}, - .VQRSHRNT = { 1622, 1}, - .VQSHRUNB = { 1623, 1}, - .VQSHRUNT = { 1624, 1}, - .VQRSHRUNB = { 1625, 1}, - .VQRSHRUNT = { 1626, 1}, - .VQDMLADH = { 1627, 1}, - .VQDMLADHX = { 1628, 1}, - .VQDMLSDH = { 1629, 1}, - .VQDMLSDHX = { 1630, 1}, - .VQRDMLADH = { 1631, 1}, - .VQRDMLADHX = { 1632, 1}, - .VQRDMLSDH = { 1633, 1}, - .VQRDMLSDHX = { 1634, 1}, - .VLDRB = { 1635, 2}, - .VLDRH = { 1637, 2}, - .VLDRW = { 1639, 2}, - .VLDRD = { 1641, 2}, - .VSTRB = { 1643, 2}, - .VSTRH = { 1645, 2}, - .VSTRW = { 1647, 2}, - .VSTRD = { 1649, 2}, - .VLD20 = { 1651, 1}, - .VLD21 = { 1652, 1}, - .VLD40 = { 1653, 1}, - .VLD41 = { 1654, 1}, - .VLD42 = { 1655, 1}, - .VLD43 = { 1656, 1}, - .VST20 = { 1657, 1}, - .VST21 = { 1658, 1}, - .VST40 = { 1659, 1}, - .VST41 = { 1660, 1}, - .VST42 = { 1661, 1}, - .VST43 = { 1662, 1}, - ._COUNT = { 1663, 0}, + .RFEDA = { 590, 2}, + .RFEDB = { 592, 2}, + .RFEIA = { 594, 2}, + .RFEIB = { 596, 2}, + .SRSDA = { 598, 2}, + .SRSDB = { 600, 2}, + .SRSIA = { 602, 2}, + .SRSIB = { 604, 2}, + .CDP = { 606, 1}, + .CDP2 = { 607, 1}, + .MCR = { 608, 1}, + .MCR2 = { 609, 1}, + .MRC = { 610, 1}, + .MRC2 = { 611, 1}, + .MCRR = { 612, 1}, + .MCRR2 = { 613, 1}, + .MRRC = { 614, 1}, + .MRRC2 = { 615, 1}, + .LDC = { 616, 1}, + .LDC2 = { 617, 1}, + .STC = { 618, 1}, + .STC2 = { 619, 1}, + .CRC32B = { 620, 1}, + .CRC32H = { 621, 1}, + .CRC32W = { 622, 1}, + .CRC32CB = { 623, 1}, + .CRC32CH = { 624, 1}, + .CRC32CW = { 625, 1}, + .VADD = { 626, 18}, + .VSUB = { 644, 18}, + .VMUL = { 662, 22}, + .VDIV = { 684, 3}, + .VMLA = { 687, 16}, + .VMLS = { 703, 15}, + .VNMUL = { 718, 2}, + .VNMLA = { 720, 2}, + .VNMLS = { 722, 2}, + .VFMA = { 724, 8}, + .VFMS = { 732, 6}, + .VFNMA = { 738, 3}, + .VFNMS = { 741, 3}, + .VABS = { 744, 12}, + .VNEG = { 756, 12}, + .VSQRT = { 768, 3}, + .VCMP = { 771, 8}, + .VCMPE = { 779, 4}, + .VCVT = { 783, 35}, + .VCVTB = { 818, 2}, + .VCVTT = { 820, 2}, + .VCVTA = { 822, 2}, + .VCVTN = { 824, 2}, + .VCVTP = { 826, 2}, + .VCVTM = { 828, 2}, + .VCVTR = { 830, 4}, + .VMOV = { 834, 33}, + .VMRS = { 867, 1}, + .VMSR = { 868, 1}, + .VLDR = { 869, 2}, + .VSTR = { 871, 2}, + .VLDM = { 873, 2}, + .VSTM = { 875, 2}, + .VPUSH = { 877, 2}, + .VPOP = { 879, 2}, + .VSEL = { 881, 2}, + .VMAXNM = { 883, 2}, + .VMINNM = { 885, 2}, + .VRINTA = { 887, 3}, + .VRINTN = { 890, 3}, + .VRINTP = { 893, 3}, + .VRINTM = { 896, 3}, + .VRINTR = { 899, 2}, + .VRINTZ = { 901, 3}, + .VRINTX = { 904, 3}, + .VADDL = { 907, 6}, + .VADDW = { 913, 6}, + .VSUBL = { 919, 6}, + .VSUBW = { 925, 6}, + .VHADD = { 931, 9}, + .VHSUB = { 940, 9}, + .VRHADD = { 949, 3}, + .VQADD = { 952, 11}, + .VQSUB = { 963, 11}, + .VMULL = { 974, 11}, + .VMLAL = { 985, 10}, + .VMLSL = { 995, 10}, + .VQDMULL = { 1005, 4}, + .VQDMLAL = { 1009, 4}, + .VQDMLSL = { 1013, 4}, + .VQDMULH = { 1017, 8}, + .VQRDMULH = { 1025, 8}, + .VQRDMLAH = { 1033, 8}, + .VQRDMLSH = { 1041, 8}, + .VABA = { 1049, 8}, + .VABAL = { 1057, 6}, + .VABD = { 1063, 10}, + .VABDL = { 1073, 6}, + .VAND = { 1079, 3}, + .VBIC = { 1082, 15}, + .VORR = { 1097, 15}, + .VORN = { 1112, 3}, + .VEOR = { 1115, 3}, + .VBSL = { 1118, 2}, + .VBIT = { 1120, 2}, + .VBIF = { 1122, 2}, + .VMVN = { 1124, 13}, + .VMOVN = { 1137, 3}, + .VQMOVN = { 1140, 6}, + .VQMOVUN = { 1146, 3}, + .VMOVL = { 1149, 6}, + .VTST = { 1155, 6}, + .VCEQ = { 1161, 14}, + .VCGE = { 1175, 16}, + .VCGT = { 1191, 16}, + .VCLE = { 1207, 18}, + .VCLT = { 1225, 18}, + .VACGE = { 1243, 2}, + .VACGT = { 1245, 2}, + .VACLE = { 1247, 2}, + .VACLT = { 1249, 2}, + .VMAX = { 1251, 13}, + .VMIN = { 1264, 13}, + .VPMAX = { 1277, 5}, + .VPMIN = { 1282, 5}, + .VPADD = { 1287, 5}, + .VPADDL = { 1292, 6}, + .VPADAL = { 1298, 4}, + .VRECPE = { 1302, 4}, + .VRECPS = { 1306, 2}, + .VRSQRTE = { 1308, 4}, + .VRSQRTS = { 1312, 2}, + .VSHL = { 1314, 9}, + .VSHR = { 1323, 3}, + .VSRA = { 1326, 3}, + .VRSHL = { 1329, 5}, + .VRSHR = { 1334, 3}, + .VRSRA = { 1337, 2}, + .VSLI = { 1339, 2}, + .VSRI = { 1341, 2}, + .VQSHL = { 1343, 7}, + .VQSHRN = { 1350, 1}, + .VQSHRUN = { 1351, 1}, + .VQRSHL = { 1352, 16}, + .VQRSHRN = { 1368, 1}, + .VQRSHRUN = { 1369, 1}, + .VSHRN = { 1370, 1}, + .VRSHRN = { 1371, 1}, + .VSHLL = { 1372, 4}, + .VCLS = { 1376, 6}, + .VCLZ = { 1382, 6}, + .VCNT = { 1388, 2}, + .VREV16 = { 1390, 2}, + .VREV32 = { 1392, 4}, + .VREV64 = { 1396, 6}, + .VEXT = { 1402, 2}, + .VTBL = { 1404, 4}, + .VTBX = { 1408, 4}, + .VTRN = { 1412, 6}, + .VUZP = { 1418, 5}, + .VZIP = { 1423, 5}, + .VDUP = { 1428, 5}, + .VSWP = { 1433, 2}, + .VLD1 = { 1435, 8}, + .VLD2 = { 1443, 6}, + .VLD3 = { 1449, 5}, + .VLD4 = { 1454, 5}, + .VST1 = { 1459, 7}, + .VST2 = { 1466, 6}, + .VST3 = { 1472, 5}, + .VST4 = { 1477, 5}, + .AESE = { 1482, 1}, + .AESD = { 1483, 1}, + .AESMC = { 1484, 1}, + .AESIMC = { 1485, 1}, + .SHA1H = { 1486, 1}, + .SHA1SU0 = { 1487, 1}, + .SHA1SU1 = { 1488, 1}, + .SHA1C = { 1489, 1}, + .SHA1M = { 1490, 1}, + .SHA1P = { 1491, 1}, + .SHA256H = { 1492, 1}, + .SHA256H2 = { 1493, 1}, + .SHA256SU0 = { 1494, 1}, + .SHA256SU1 = { 1495, 1}, + .VJCVT = { 1496, 1}, + .VSDOT = { 1497, 4}, + .VUDOT = { 1501, 4}, + .VDOT = { 1505, 2}, + .VMMLA = { 1507, 1}, + .VFMAL = { 1508, 2}, + .VFMSL = { 1510, 2}, + .VCMLA = { 1512, 5}, + .VCADD = { 1517, 2}, + .VSMMLA = { 1519, 1}, + .VUMMLA = { 1520, 1}, + .VUSMMLA = { 1521, 1}, + .VSUDOT = { 1522, 2}, + .VUSDOT = { 1524, 4}, + .VQABS = { 1528, 1}, + .VQNEG = { 1529, 1}, + .VMOVX = { 1530, 1}, + .VINS = { 1531, 1}, + .VLD2R = { 1532, 1}, + .VLD3R = { 1533, 1}, + .VLD4R = { 1534, 1}, + .IT = { 1535, 1}, + .TT = { 1536, 1}, + .TTT = { 1537, 1}, + .TTA = { 1538, 1}, + .TTAT = { 1539, 1}, + .SG = { 1540, 1}, + .BXNS = { 1541, 1}, + .BLXNS = { 1542, 1}, + .PAC = { 1543, 1}, + .PACBTI = { 1544, 1}, + .AUT = { 1545, 1}, + .AUTG = { 1546, 1}, + .BTI = { 1547, 1}, + .WLS = { 1548, 1}, + .WLSTP = { 1549, 1}, + .DLS = { 1550, 1}, + .DLSTP = { 1551, 1}, + .LE = { 1552, 1}, + .LETP = { 1553, 1}, + .LCTP = { 1554, 1}, + .BF = { 1555, 1}, + .BFX = { 1556, 1}, + .BFL = { 1557, 1}, + .BFLX = { 1558, 1}, + .BFCSEL = { 1559, 1}, + .CX1 = { 1560, 1}, + .CX1A = { 1561, 1}, + .CX1D = { 1562, 1}, + .CX1DA = { 1563, 1}, + .CX2 = { 1564, 1}, + .CX2A = { 1565, 1}, + .CX2D = { 1566, 1}, + .CX2DA = { 1567, 1}, + .CX3 = { 1568, 1}, + .CX3A = { 1569, 1}, + .CX3D = { 1570, 1}, + .CX3DA = { 1571, 1}, + .VCX1 = { 1572, 2}, + .VCX1A = { 1574, 2}, + .VCX2 = { 1576, 2}, + .VCX2A = { 1578, 2}, + .VCX3 = { 1580, 2}, + .VCX3A = { 1582, 2}, + .VPT = { 1584, 1}, + .VPST = { 1585, 1}, + .VPSEL = { 1586, 1}, + .VPNOT = { 1587, 1}, + .VCTP = { 1588, 1}, + .VADDV = { 1589, 1}, + .VADDVA = { 1590, 1}, + .VADDLV = { 1591, 1}, + .VADDLVA = { 1592, 1}, + .VMAXV = { 1593, 1}, + .VMAXAV = { 1594, 1}, + .VMINV = { 1595, 1}, + .VMINAV = { 1596, 1}, + .VMAXNMV = { 1597, 1}, + .VMAXNMAV = { 1598, 1}, + .VMINNMV = { 1599, 1}, + .VMINNMAV = { 1600, 1}, + .VABAV = { 1601, 1}, + .VMLADAV = { 1602, 1}, + .VMLADAVA = { 1603, 1}, + .VMLADAVX = { 1604, 1}, + .VMLADAVAX = { 1605, 1}, + .VMLALDAV = { 1606, 1}, + .VMLALDAVA = { 1607, 1}, + .VMLALDAVX = { 1608, 1}, + .VMLALDAVAX = { 1609, 1}, + .VMLSDAV = { 1610, 1}, + .VMLSDAVA = { 1611, 1}, + .VMLSDAVX = { 1612, 1}, + .VMLSDAVAX = { 1613, 1}, + .VMLSLDAV = { 1614, 1}, + .VMLSLDAVA = { 1615, 1}, + .VMLSLDAVX = { 1616, 1}, + .VMLSLDAVAX = { 1617, 1}, + .VRMLALDAVH = { 1618, 1}, + .VRMLALDAVHA = { 1619, 1}, + .VRMLALDAVHX = { 1620, 1}, + .VRMLALDAVHAX = { 1621, 1}, + .VRMLSLDAVH = { 1622, 1}, + .VRMLSLDAVHA = { 1623, 1}, + .VRMLSLDAVHX = { 1624, 1}, + .VRMLSLDAVHAX = { 1625, 1}, + .VMLAV = { 1626, 1}, + .VMLAVA = { 1627, 1}, + .VMLSV = { 1628, 1}, + .VMLSVA = { 1629, 1}, + .VCMUL = { 1630, 1}, + .VHCADD = { 1631, 2}, + .VBRSR = { 1633, 1}, + .VSHLC = { 1634, 1}, + .VDDUP = { 1635, 1}, + .VIDUP = { 1636, 1}, + .VDWDUP = { 1637, 1}, + .VIWDUP = { 1638, 1}, + .VMOVNB = { 1639, 1}, + .VMOVNT = { 1640, 1}, + .VQMOVNB = { 1641, 1}, + .VQMOVNT = { 1642, 1}, + .VQMOVUNB = { 1643, 1}, + .VQMOVUNT = { 1644, 1}, + .VSHLLB = { 1645, 1}, + .VSHLLT = { 1646, 1}, + .VMULLB = { 1647, 1}, + .VMULLT = { 1648, 1}, + .VMLALB = { 1649, 1}, + .VMLALT = { 1650, 1}, + .VMLSLB = { 1651, 1}, + .VMLSLT = { 1652, 1}, + .VSHRNB = { 1653, 1}, + .VSHRNT = { 1654, 1}, + .VRSHRNB = { 1655, 1}, + .VRSHRNT = { 1656, 1}, + .VQSHRNB = { 1657, 1}, + .VQSHRNT = { 1658, 1}, + .VQRSHRNB = { 1659, 1}, + .VQRSHRNT = { 1660, 1}, + .VQSHRUNB = { 1661, 1}, + .VQSHRUNT = { 1662, 1}, + .VQRSHRUNB = { 1663, 1}, + .VQRSHRUNT = { 1664, 1}, + .VQDMLADH = { 1665, 1}, + .VQDMLADHX = { 1666, 1}, + .VQDMLSDH = { 1667, 1}, + .VQDMLSDHX = { 1668, 1}, + .VQRDMLADH = { 1669, 1}, + .VQRDMLADHX = { 1670, 1}, + .VQRDMLSDH = { 1671, 1}, + .VQRDMLSDHX = { 1672, 1}, + .VLDRB = { 1673, 2}, + .VLDRH = { 1675, 2}, + .VLDRW = { 1677, 2}, + .VLDRD = { 1679, 2}, + .VSTRB = { 1681, 2}, + .VSTRH = { 1683, 2}, + .VSTRW = { 1685, 2}, + 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a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin @@ -127,9 +127,12 @@ operand_category :: proc(t: a.Operand_Type) -> Operand_Category { .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: return .REG - case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_PAIR, .Z_QUAD: + case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_REG_ANY, + .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D, + .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: return .ZREG - case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: + case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV, .PN_REG, .PN_REG_ZERO, + .P_REG_B, .P_REG_H, .P_REG_S, .P_REG_D: return .PREG case .REL_26, .REL_19, .REL_14, .REL_PG21: return .REL @@ -172,6 +175,16 @@ list_count :: proc(e: a.Operand_Encoding) -> int { return 0 } +// The ZSHAPE_* constant naming this operand type's SVE element width. +zshape_const :: proc(t: a.Operand_Type) -> string { + #partial switch t { + case .Z_REG_H, .Z_PAIR_H, .Z_QUAD_H: return "ZSHAPE_H" + case .Z_REG_S, .Z_PAIR_S, .Z_QUAD_S: return "ZSHAPE_S" + case .Z_REG_D, .Z_PAIR_D, .Z_QUAD_D: return "ZSHAPE_D" + } + return "ZSHAPE_B" +} + // The VSHAPE_* constant naming this operand type's arrangement. vshape_const :: proc(t: a.Operand_Type) -> string { #partial switch t { @@ -198,7 +211,8 @@ vshape_const :: proc(t: a.Operand_Type) -> string { is_lane_index :: proc(e: a.Operand_Encoding) -> bool { #partial switch e { case .NEON_IDX5, .NEON_IDX4, .NEON_IDX2, - .NEON_LANE_B, .NEON_LANE_H, .NEON_LANE_S, .NEON_LANE_D: + .NEON_LANE_B, .NEON_LANE_H, .NEON_LANE_S, .NEON_LANE_D, + .SVE_FMLA_IDX_H, .SVE_FMLA_IDX_S, .SVE_FMLA_IDX_D: return true } return false @@ -227,7 +241,28 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { // one builder and only the first is reachable. FP16 variants share a token // with their non-FP16 twin because they build an identical operand -- the // encoder tells those two apart by the form, not the operand. + // An SVE element size is not recoverable from the u8 a Z operand is passed + // as, so it has to live in the name -- otherwise every size of a mnemonic + // collapses onto one builder and only the first is reachable. #partial switch t { + case .Z_REG_B: return "zb" + case .Z_REG_H: return "zh" + case .Z_REG_S: return "zs" + case .Z_REG_D: return "zd" + case .Z_PAIR_B: return "zpb" + case .Z_PAIR_H: return "zph" + case .Z_PAIR_S: return "zps" + case .Z_PAIR_D: return "zpd" + case .Z_QUAD_B: return "zqb" + case .Z_QUAD_H: return "zqh" + case .Z_QUAD_S: return "zqs" + case .Z_QUAD_D: return "zqd" + case .P_REG_B: return "pb" + case .P_REG_H: return "ph" + case .P_REG_S: return "ps" + case .P_REG_D: return "pd" + case .PN_REG: return "pn" + case .PN_REG_ZERO: return "pnz" case .V_8B: return "v8b" case .V_16B: return "v16b" case .V_4H, .V_4H_FP16: return "v4h" @@ -410,7 +445,14 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Opera // A register the syntax writes as a list carries how many, which is a // property of the form rather than of the operand type. if n := list_count(enc); n > 0 { - fmt.sbprintf(sb, "op_v_list(%s, %s, %d)", names[0], vshape_const(t), n) + // A Z operand arrives as a bare register number, so it has to be given + // its class before it can head a list. + if operand_category(t) == .ZREG { + fmt.sbprintf(sb, "op_v_list(Register(REG_Z | (u16(%s) & 0x1F)), %s, %d)", + names[0], zshape_const(t), n) + } else { + fmt.sbprintf(sb, "op_v_list(%s, %s, %d)", names[0], vshape_const(t), n) + } return } #partial switch operand_category(t) { @@ -437,10 +479,19 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Opera case .Z_REG_H: fmt.sbprintf(sb, "op_z_h(%s)", names[0]) case .Z_REG_S: fmt.sbprintf(sb, "op_z_s(%s)", names[0]) case .Z_REG_D: fmt.sbprintf(sb, "op_z_d(%s)", names[0]) - case: fmt.sbprintf(sb, "op_reg(Register(REG_Z | (u16(%s) & 0x1F)))", names[0]) // Z_PAIR / Z_QUAD + case .Z_PAIR_B, .Z_QUAD_B: fmt.sbprintf(sb, "op_z_b(%s)", names[0]) + case .Z_PAIR_H, .Z_QUAD_H: fmt.sbprintf(sb, "op_z_h(%s)", names[0]) + case .Z_PAIR_S, .Z_QUAD_S: fmt.sbprintf(sb, "op_z_s(%s)", names[0]) + case .Z_PAIR_D, .Z_QUAD_D: fmt.sbprintf(sb, "op_z_d(%s)", names[0]) + case: fmt.sbprintf(sb, "op_reg(Register(REG_Z | (u16(%s) & 0x1F)))", names[0]) // Z_REG_ANY } case .PREG: - fmt.sbprintf(sb, "op_reg(Register(REG_P | (u16(%s) & 0xF)))", names[0]) + if t == .PN_REG || t == .PN_REG_ZERO { + // SME2 numbers its predicate-as-counter registers from 8. + fmt.sbprintf(sb, "op_reg(Register(REG_PN | (8 + (u16(%s) & 0x7))))", names[0]) + } else { + fmt.sbprintf(sb, "op_reg(Register(REG_P | (u16(%s) & 0xF)))", names[0]) + } case .IMM: if is_lane_index(enc) { fmt.sbprintf(sb, "op_lane_index(%s)", names[0]) From c9b28d2ec1f6387f4d5daf4a63d3b44622a76e4a Mon Sep 17 00:00:00 2001 From: gingerBill Date: Fri, 28 Aug 2026 12:10:16 +0100 Subject: [PATCH 40/89] Add new SVE mnemonics and `IMM_MUL4` operand and encoding type --- core/rexcode/isa/arm64/encoder.odin | 13 +- core/rexcode/isa/arm64/encoding_types.odin | 2 + core/rexcode/isa/arm64/mnemonics.odin | 8 + .../isa/arm64/tablegen/instruction_table.odin | 5206 +++++++++-------- 4 files changed, 2722 insertions(+), 2507 deletions(-) diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index d7b5fecab..20138e78a 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -277,7 +277,8 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .IMMEDIATE case .IMM_12, .IMM_16, .IMM_8, .IMM_6, .IMM_5, .IMM_4, .IMM_3, .IMM_2, - .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX: + .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX, + .IMM_MUL4: return op.kind == .IMMEDIATE case .SYS_REG: return op.kind == .SYSTEM_REGISTER @@ -664,6 +665,16 @@ pack_operand_inline :: #force_inline proc( case .SVE_PATTERN: return (u32(op.immediate) & 0x1F) << 5 + case .IMM_MUL4: + // SVE element-count multiplier "MUL #imm" (INCW/DECW/CNTW/SQINCW/...). + // imm4 field at bits 19:16 encodes (imm - 1); asm range MUL #1..#16 + // maps to 0..15. The operand carries the architectural multiplier + // (1..16), so subtract one here, matching the ENC_LSL_IMM_* / + // NEON_SHR_IMM convention of encoding the adjusted value. + mul := u32(op.immediate) + if mul == 0 { mul = 1 } + return ((mul - 1) & 0xF) << 16 + // SVE memory operands case .SVE_OFFSET_BASE_SS: // [Xn, Xm, LSL #s] scalar+scalar. Base at 9:5, index at 20:16; diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 46d6e8495..d7904f15a 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -156,6 +156,7 @@ Operand_Type :: enum u8 { HW_SHIFT, // 2-bit LSL hw (0/16/32/48) for MOV-immediate BITMASK_IMM, // Logical immediate (bitmask-encoded N:imms:immr) LSE_SIZE, // 2-bit size selector for LSE atomics (00=B 01=H 10=W 11=X) + IMM_MUL4, // ---- PC-relative ---- REL_26, // B / BL (signed 26-bit << 2) @@ -349,6 +350,7 @@ Operand_Encoding :: enum u8 { SVE_IMM5, // 5-bit at bits 20-16 (INDEX imm, etc.) SVE_SHIFT_TSZ_IMM, // tsz:imm3 at bits 22:16, encodes element-size + shift amount SVE_PATTERN, // 5-bit pattern (POW2/VL1.../ALL) at bits 9-5 (PTRUE) + IMM_MUL4, // ---- SVE memory operands --------------------------------------------- SVE_OFFSET_BASE_SS, // [Xn, Xm, LSL #s] -- scalar+scalar contiguous diff --git a/core/rexcode/isa/arm64/mnemonics.odin b/core/rexcode/isa/arm64/mnemonics.odin index 6aae469af..f0b78fc27 100644 --- a/core/rexcode/isa/arm64/mnemonics.odin +++ b/core/rexcode/isa/arm64/mnemonics.odin @@ -392,6 +392,14 @@ Mnemonic :: enum u16 { BFMOPA, BFMOPS, SMOPA, SMOPS, UMOPA, UMOPS, USMOPA, SUMOPA, + CNTB, CNTH, CNTW, CNTD, + INCB, INCH, INCW, INCD, + DECB, DECH, DECW, DECD, + SQINCB, SQINCH, SQINCW, SQINCD, SQDECB, SQDECH, SQDECW, SQDECD, + UQINCB, UQINCH, UQINCW, UQINCD, UQDECB, UQDECH, UQDECW, UQDECD, + CNTP, INCP, DECP, + SQINCP, SQDECP, + UQINCP, UQDECP, // ------------------------------------------------------------------------- // SME tile slice load/store (LD1B/H/W/D/Q to ZA tile slice; ST1 reverse) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index a32b04759..7e069ce08 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -105,4139 +105,4333 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, .ADD = { - {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04000000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04400000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04800000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ADDS = { - {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SUB = { - {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04010000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04410000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04810000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SUBS = { - {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .AND = { - {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041A0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ANDS = { - {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { - {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04180000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EOR = { - {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04190000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BIC = { - {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x041B0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BICS = { - {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { - {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EON = { - {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LSL = { - {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04138000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04538000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04938000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .LSR = { - {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04118000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04518000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04918000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ASR = { - {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04108000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04508000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04908000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ROR = { - {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04950000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04940000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04120000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04520000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04920000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04130000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04530000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04930000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CSET = { - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CSETM = { - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CINC = { - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CINV = { - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - }, - .CNEG = { - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMP = { - {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMN = { - {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSET = { + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CSETM = { + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CINC = { + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CINV = { + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + }, + .CNEG = { + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_EQ = { - {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_NE = { - {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_CS = { - {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_CC = { - {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_MI = { - {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_PL = { - {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_VS = { - {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_VC = { - {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_HI = { - {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_LS = { - {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_GE = { - {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_LT = { - {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_GT = { - {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_LE = { - {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_AL = { - {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .B_NV = { - {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, - {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, - {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, }, .FMOV = { - {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, - {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, - {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65408000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65808000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65418000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65818000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65428000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65828000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x654D8000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x658D8000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65468000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65868000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65478000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65878000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65448000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65848000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65458000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x65858000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .TST = { - {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_2D, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .MUL = { - {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04100000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04500000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04900000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MLA = { - {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .MLS = { - {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .NEG = { - {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, - {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ABS = { - {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04080000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04480000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04880000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04090000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04490000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04890000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040A0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044A0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048A0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040B0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044B0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048B0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040C0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044C0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048C0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x040D0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x044D0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x048D0000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ADDP = { - {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SMULL = { - {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMULL2 = { - {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL = { - {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL2 = { - {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .FMLA = { - {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMLS = { - {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMAXP = { - {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINP = { - {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXV = { - {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINV = { - {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, }, .FADDP = { - {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SHL = { - {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHL = { - {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .DUP = { - {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, }, .MOV = { - {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, - {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, - {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOV, {.P_REG, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .EXT = { - {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .NOT = { - {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .URECPE = { - {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSQRTE = { - {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VM}, 0x04030000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x04430000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VM}, 0x04830000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ASRR = { - {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSLR = { - {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSRR = { - {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .FTSMUL = { - {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUBR = { - {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIVR = { - {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMLA = { - {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .FNMLS = { - {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + {{.PTRUE, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + {{.PFALSE, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, }, .SETFFR = { - {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { - {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .CPY = { - {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .COMPACT = { - {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD, .P_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { - {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQRDMLSH = { - {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .ADCLB = { - {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADCLT = { - {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLB = { - {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLT = { - {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { - {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .HISTSEG = { - {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMSTART = { - {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .SMSTOP = { - {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, }, .ADDHA = { - {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ADDVA = { - {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, }, .FMOPA = { - {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMOPS = { - {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPA = { - {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPS = { - {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SMOPA = { - {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SMOPS = { - {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPA = { - {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPS = { - {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .USMOPA = { - {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SUMOPA = { - {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + }, + .CNTB = { + {{.CNTB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + }, + .CNTH = { + {{.CNTH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + }, + .CNTW = { + {{.CNTW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + }, + .CNTD = { + {{.CNTD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + }, + .INCB = { + {{.INCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + }, + .INCH = { + {{.INCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .INCW = { + {{.INCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .INCD = { + {{.INCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .DECB = { + {{.DECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + }, + .DECH = { + {{.DECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .DECW = { + {{.DECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .DECD = { + {{.DECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + }, + .SQINCB = { + {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQINCH = { + {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQINCW = { + {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQINCD = { + {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQDECB = { + {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQDECH = { + {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQDECW = { + {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .SQDECD = { + {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQINCB = { + {{.UQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQINCH = { + {{.UQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQINCW = { + {{.UQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQINCD = { + {{.UQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQDECB = { + {{.UQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQDECH = { + {{.UQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQDECW = { + {{.UQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .UQDECD = { + {{.UQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + }, + .CNTP = { + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + }, + .INCP = { + {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + }, + .DECP = { + {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + }, + .SQINCP = { + {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + }, + .SQDECP = { + {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + }, + .UQINCP = { + {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + }, + .UQDECP = { + {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, - {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { - {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { - {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BSL1N = { - {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BSL2N = { - {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NBSL = { - {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .PMUL = { - {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVTNT = { - {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .LDRAA = { - {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .LDRAB = { - {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, }, .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, }, .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, }, .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .BC_EQ = { - {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_NE = { - {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_CS = { - {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_CC = { - {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_MI = { - {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_PL = { - {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_VS = { - {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_VC = { - {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_HI = { - {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_LS = { - {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_GE = { - {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_LT = { - {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_GT = { - {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_LE = { - {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_AL = { - {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BC_NV = { - {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, }, .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLUR = { - {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURB = { - {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURH = { - {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65008000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65018000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65028000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { - {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLS = { - {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BFCLAMP = { - {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65048000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VM}, 0x65058000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI2, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, Clobber{written={0}, read={1}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI4, {.Z_PAIR, .Z_PAIR, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, Clobber{written={0}, read={1}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD, .Z_QUAD, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, }, .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .PRFM = { - {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, - {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, }, .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMP = { - {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMN = { - {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, } From 4bd417b63f77efb636035b3018cfd8ea97c1e5ac Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 16:14:56 -0400 Subject: [PATCH 41/89] rexcode/arm64: 48 instructions could not be decoded at all An entry whose `bits` set a bit its `mask` does not cover can never match anything -- `word & mask == bits` is unsatisfiable -- so those instructions were absent from the decoder entirely. There were 48, and LDXR/LDAXR were among them: a plain `ldxr w0, [x1]` disassembled to nothing. They divide cleanly. Most are the SVE predicated *unary* ops (ABS/CLS/CLZ/CNT/FABS/FNEG/FSQRT/NEG), which keep their opcode at bits 20:16 -- the same field that was wrong for the binary ops, except here the stray bits sat in `bits` rather than being left free, so the entry was dead instead of over-matching. The LDXR family has Rs = 11111 in the same place. FCADD, SETE, SETM and UZP each had one fixed bit outside their mask. Every one of them was verified against llvm-mc before widening: the patterns were right, only the masks were too narrow. Four needed more than a wider mask: - BTI was modelled as taking a hint immediate, but its variants are already their own mnemonics (BTI_C/BTI_J/BTI_JC) with exact patterns. The bare row is plain `bti` and never took an operand. - LUTI2/LUTI4 named a Z pair where the architecture has ZT0, SME2's lookup table, and put a register at bits 20:16 where the table index lives. ZT0 is modelled now -- one register, no bits -- and the index is a real lane index at bits 16:15. Both now cover all three element sizes rather than one. - MOVA's mask missed bit 17. Two more the newly-assemblable output exposed: ST1D's scalar+scalar form carried the .q encoding, and LD1SH's was labelled .s while holding the .d pattern, with the .s form missing outright. SVE scalar+scalar addressing scales its index by the access size and an assembler wants that spelled (`[x0, x0, lsl #2]`), which 38 forms did not print. The amount is fixed by the form -- and by the *access* size, not the destination, so LD1SB's is 0 even though it writes halfwords. SVE/SME2 decode entries against llvm-mc: 438 byte-exact and 0 mismatched, from 211 and 78 at the start of the session. Nothing decodes to `invalid` any more. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 16 +- core/rexcode/isa/arm64/encoder.odin | 8 +- core/rexcode/isa/arm64/encoding_types.odin | 7 + core/rexcode/isa/arm64/mnemonic_builders.odin | 32 +- core/rexcode/isa/arm64/printer.odin | 3 + core/rexcode/isa/arm64/registers.odin | 4 + .../tablegen/generated/decode_tables.odin | 207 +++--- .../tablegen/generated/encode_tables.odin | 634 +++++++++--------- .../isa/arm64/tablegen/instruction_table.odin | 177 ++--- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 35070 -> 35140 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 50100 -> 50200 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6568 -> 6568 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 50140 -> 50240 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes core/rexcode/isa/arm64/tests/smoke.odin | 16 +- .../arm64/tools/gen_mnemonic_builders.odin | 13 +- 16 files changed, 595 insertions(+), 522 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index bf406aedb..fbb3ad41f 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -502,6 +502,10 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} case .PM: return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} + case .ENC_ZT0: + return Operand{reg = ZT0, kind = .REGISTER, size = 0} + case .LUTI_IDX: + return Operand{immediate = i64((word >> 15) & 0x3), kind = .IMMEDIATE, size = LANE_INDEX} case .PNG: return Operand{reg = Register(REG_PN | u16(8 + ((word >> 10) & 0x7))), kind = .REGISTER, size = pqual_for_type(ot)} case .PG: @@ -524,13 +528,20 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = 1} // ---- SVE memory operands ---- - case .SVE_OFFSET_BASE_SS: + case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) + shift: u8 = 0 + #partial switch en { + case .SVE_OFFSET_BASE_SS1: shift = 1 + case .SVE_OFFSET_BASE_SS2: shift = 2 + case .SVE_OFFSET_BASE_SS3: shift = 3 + } return Operand{ mem = Memory{ base = Register(REG_X | u16(base_hw)), index = Register(REG_X | u16(idx_hw)), + shift = shift, mode = .REG_OFFSET, }, kind = .MEMORY, size = 4, @@ -712,6 +723,8 @@ reg_from_field :: #force_inline proc "contextless" ( cls = REG_P case .PN_REG, .PN_REG_ZERO: cls = REG_PN + case .ZT_REG: + cls = REG_ZT case .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D, .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: cls = REG_Z @@ -751,6 +764,7 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .Z_REG_H: return 2 case .Z_REG_S: return 4 case .Z_REG_D: return 8 + case .Z_REG_ANY: return 0 // no element size in the syntax case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO case .P_REG_MERGE: return PQUAL_MERGE case .P_REG_B: return PSHAPE_B diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 48b43bec4..3e5edccfa 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -259,6 +259,8 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_P case .PN_REG, .PN_REG_ZERO: return op.kind == .REGISTER && reg_class(op.reg) == REG_PN + case .ZT_REG: + return op.kind == .REGISTER && reg_class(op.reg) == REG_ZT // The first register of a pair must be even, of a quad a multiple of four. case .Z_REG_ANY: return op.kind == .REGISTER && reg_class(op.reg) == REG_Z @@ -655,6 +657,10 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0xF) << 5 case .PM: return (u32(reg_hw(op.reg)) & 0xF) << 16 + case .ENC_ZT0: + return 0 + case .LUTI_IDX: + return (u32(op.immediate) & 0x3) << 15 case .PNG: // The field holds pn - 8. return ((u32(reg_hw(op.reg)) - 8) & 0x7) << 10 @@ -684,7 +690,7 @@ pack_operand_inline :: #force_inline proc( return (u32(op.immediate) & 0x1F) << 5 // SVE memory operands - case .SVE_OFFSET_BASE_SS: + case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3: // [Xn, Xm, LSL #s] scalar+scalar. Base at 9:5, index at 20:16; // shift is implicit in the encoding's static bits (per ESize). base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 88da7d460..0591ef565 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -201,6 +201,7 @@ Operand_Type :: enum u8 { // SME2 predicate-as-counter (PN8..PN15). `_ZERO` prints the `/z` a load // needs; a store writes it bare. PN_REG, PN_REG_ZERO, + ZT_REG, // ZT0 -- SME2's lookup table, and the only one of its kind // A predicate that is written with an element size because it is the // instruction's destination (`cmpge p0.b, p1/z, ...`). P_REG_B, P_REG_H, P_REG_S, P_REG_D, @@ -407,6 +408,12 @@ Operand_Encoding :: enum u8 { // type -- otherwise every count would need its own type per arrangement. VD_LIST1, VD_LIST2, VD_LIST3, VD_LIST4, PNG, // bits 10-12, predicate-as-counter (SME2) + ENC_ZT0, // no bits at all; there is only one ZT register + LUTI_IDX, // bits 15-16, LUTI2/LUTI4 table index + // SVE scalar+scalar addressing scales the index by the access size, and the + // assembler wants that written out (`[x0, x0, lsl #2]`). The amount is a + // property of the form, so it rides on the encoding. + SVE_OFFSET_BASE_SS1, SVE_OFFSET_BASE_SS2, SVE_OFFSET_BASE_SS3, // A Z register whose element size is not in the static pattern but in the // instruction's own tsz field, so decode has to read it out of the word // rather than take it from the form (SVE2 XAR). diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 545d6f969..26c2db5f0 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -1269,8 +1269,8 @@ inst_eretaa_none :: #force_inline proc "contextless" () -> Instruct emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } -inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } +inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI) } +emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } @@ -4109,10 +4109,18 @@ inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: emit_bfmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } emit_bfminnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_luti2_zpb_zpb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti2_zpb_zpb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti2_zpb_zpb_zb_i(rz, rz2, rz3, imm)) } -inst_luti4_zpb_zpb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } -emit_luti4_zpb_zpb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_luti4_zpb_zpb_zb_i(rz, rz2, rz3, imm)) } +inst_luti2_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti2_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti2_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +emit_luti2_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zpb_zt_z_i(rz, rz2, imm)) } +emit_luti2_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zph_zt_z_i(rz, rz2, imm)) } +emit_luti2_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zps_zt_z_i(rz, rz2, imm)) } +inst_luti4_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti4_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti4_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +emit_luti4_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zpb_zt_z_i(rz, rz2, imm)) } +emit_luti4_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zph_zt_z_i(rz, rz2, imm)) } +emit_luti4_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zps_zt_z_i(rz, rz2, imm)) } inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_zip_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_zpb_zb_zb(rz, rz2, rz3)) } @@ -4854,8 +4862,8 @@ inst_eretaa :: inst_eretaa_none emit_eretaa :: emit_eretaa_none inst_eretab :: inst_eretab_none emit_eretab :: emit_eretab_none -inst_bti :: inst_bti_i -emit_bti :: emit_bti_i +inst_bti :: inst_bti_none +emit_bti :: emit_bti_none inst_irg :: inst_irg_r_r_r emit_irg :: emit_irg_r_r_r inst_addg :: inst_addg_r_r_i_i @@ -5768,10 +5776,10 @@ inst_bfmaxnm :: inst_bfmaxnm_zh_p_zh_zh emit_bfmaxnm :: emit_bfmaxnm_zh_p_zh_zh inst_bfminnm :: inst_bfminnm_zh_p_zh_zh emit_bfminnm :: emit_bfminnm_zh_p_zh_zh -inst_luti2 :: inst_luti2_zpb_zpb_zb_i -emit_luti2 :: emit_luti2_zpb_zpb_zb_i -inst_luti4 :: inst_luti4_zpb_zpb_zb_i -emit_luti4 :: emit_luti4_zpb_zpb_zb_i +inst_luti2 :: inst_luti2_zpb_zt_z_i +emit_luti2 :: emit_luti2_zpb_zt_z_i +inst_luti4 :: inst_luti4_zpb_zt_z_i +emit_luti4 :: emit_luti4_zpb_zt_z_i inst_zip :: proc{ inst_zip_zpb_zb_zb, inst_zip_zqb_zqb } emit_zip :: proc{ emit_zip_zpb_zb_zb, emit_zip_zqb_zqb } inst_uzp :: proc{ inst_uzp_zpb_zb_zb, inst_uzp_zqb_zqb } diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index e207b8b9a..8bb94c1e1 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -504,6 +504,9 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { case REG_PN: strings.write_string(sb, uppercase ? "PN" : "pn") write_decimal_u32(sb, u32(hw)) + case REG_ZT: + strings.write_string(sb, uppercase ? "ZT" : "zt") + write_decimal_u32(sb, u32(hw)) } } diff --git a/core/rexcode/isa/arm64/registers.odin b/core/rexcode/isa/arm64/registers.odin index b64fc8f36..b0669b364 100644 --- a/core/rexcode/isa/arm64/registers.odin +++ b/core/rexcode/isa/arm64/registers.odin @@ -35,6 +35,7 @@ REG_Q :: 0x0A00 // Q0..Q31 (quad view) REG_Z :: 0x0B00 // Z0..Z31 SVE scalable vector (low 128 aliased with V) REG_P :: 0x0C00 // P0..P15 SVE predicate REG_PN :: 0x0D00 // PN8..PN15 SME2 predicate-as-counter +REG_ZT :: 0x0E00 // ZT0, the SME2 lookup table NONE :: Register(0xFFFF) @@ -53,6 +54,9 @@ PN10 :: Register(REG_PN | 10); PN11 :: Register(REG_PN | 11) PN12 :: Register(REG_PN | 12); PN13 :: Register(REG_PN | 13) PN14 :: Register(REG_PN | 14); PN15 :: Register(REG_PN | 15) +// SME2's lookup table. There is exactly one, so it takes no bits. +ZT0 :: Register(REG_ZT | 0) + // ----------------------------------------------------------------------------- // 64-bit GPRs (X0..X30, XZR, SP) // ----------------------------------------------------------------------------- diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 8b67892b4..f5b00d293 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2507]lib.Decode_Entry{ +DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -34,30 +34,35 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .LUTI2, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, @@ -72,18 +77,17 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {explicit_count=3} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, @@ -289,6 +293,13 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, @@ -297,6 +308,16 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -308,6 +329,10 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, @@ -364,6 +389,10 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -399,6 +428,10 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, @@ -488,33 +521,8 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, @@ -527,10 +535,6 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, @@ -542,34 +546,35 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, @@ -599,25 +604,25 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, @@ -1812,6 +1817,9 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, @@ -1820,10 +1828,7 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, @@ -1896,6 +1901,7 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, @@ -1919,7 +1925,6 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, - { .BTI, {.IMM_2,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {explicit_count=1} }, { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, @@ -2108,12 +2113,12 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, - { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, - { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, @@ -2520,19 +2525,19 @@ DECODE_ENTRIES := [2507]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ - 0x00 = { 0, 77}, - 0x02 = { 77, 505}, - 0x04 = { 582, 76}, - 0x05 = { 658, 50}, - 0x06 = { 708, 56}, - 0x07 = { 764, 1058}, - 0x08 = {1822, 16}, - 0x09 = {1838, 34}, - 0x0A = {1872, 130}, - 0x0B = {2002, 21}, - 0x0C = {2023, 167}, - 0x0D = {2190, 122}, - 0x0E = {2312, 19}, - 0x0F = {2331, 176}, + 0x00 = { 0, 81}, + 0x02 = { 81, 506}, + 0x04 = { 587, 76}, + 0x05 = { 663, 50}, + 0x06 = { 713, 56}, + 0x07 = { 769, 1058}, + 0x08 = {1827, 16}, + 0x09 = {1843, 34}, + 0x0A = {1877, 130}, + 0x0B = {2007, 21}, + 0x0C = {2028, 167}, + 0x0D = {2195, 122}, + 0x0E = {2317, 19}, + 0x0F = {2336, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index fd5dbe68b..1a31c00d0 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2505]lib.Encoding{ +ENCODE_FORMS := [2510]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -214,10 +214,10 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, // .CLS { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -227,10 +227,10 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, // .RBIT { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -476,14 +476,14 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .STLRH { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDXR - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STXR { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .LDAXR - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLXR { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, @@ -549,9 +549,9 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, // .FNEG { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, @@ -561,9 +561,9 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, // .FSQRT { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, @@ -573,9 +573,9 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, // .FADD { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, @@ -988,19 +988,19 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDXRB - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRB { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRB - { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRB { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDXRH - { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRH { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRH - { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {explicit_count=2} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRH { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAPR @@ -1239,7 +1239,7 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .ERETAB { .ERETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BTI - { .BTI, {.IMM_2,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {explicit_count=1} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, // .IRG { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .ADDG @@ -1406,10 +1406,10 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, // .ABS @@ -1420,10 +1420,10 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, // .SHADD { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2537,10 +2537,10 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .CNT { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, // .URECPE { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -2789,35 +2789,36 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, @@ -2827,33 +2828,33 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LDFF1B { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1H - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1W - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1D - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT @@ -2946,7 +2947,7 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .ST1Q { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {explicit_count=3} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, // .FCMLA { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, @@ -2954,34 +2955,34 @@ ENCODE_FORMS := [2505]lib.Encoding{ { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, // .FCADD - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, // .PRFB { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFH - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFW - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFD - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1B { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1H - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1W - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1D - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .STNT1B { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1H - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1W - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1D - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SPLICE { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX @@ -3141,15 +3142,19 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .BFMINNM { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .LUTI2 - { .LUTI2, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_3}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .LUTI4 - { .LUTI4, {.Z_PAIR_B,.Z_PAIR_B,.Z_REG_B,.IMM_2}, {.ENC_Z_PAIR_VD,.ENC_Z_PAIR_VN,.VM,.IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .ZIP { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, // .UZP - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, // .TLBI_RPALOS { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_RPAOS @@ -3227,9 +3232,9 @@ ENCODE_FORMS := [2505]lib.Encoding{ // .SETP { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETM - { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, // .SETE - { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, // .DC_IVAC { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ISW @@ -3337,7 +3342,7 @@ ENCODE_FORMS := [2505]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2505]lib.Clobber{ +CLOBBER_FORMS := [2510]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -6145,6 +6150,7 @@ CLOBBER_FORMS := [2505]lib.Clobber{ {written={0}, read={1, 2}, reads_mem=true}, {written={0}, read={1, 2}, reads_mem=true}, {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .LD1SW {written={0}, read={1, 2}, reads_mem=true}, {written={0}, read={1, 2}, reads_mem=true}, @@ -6470,9 +6476,13 @@ CLOBBER_FORMS := [2505]lib.Clobber{ // .BFMINNM {written={0}, read={1, 2, 3}}, // .LUTI2 - {written={0}, read={1}}, + {written={0}, read={2}}, + {written={0}, read={2}}, + {written={0}, read={2}}, // .LUTI4 - {written={0}, read={1}}, + {written={0}, read={2}}, + {written={0}, read={2}}, + {written={0}, read={2}}, // .ZIP {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, @@ -7266,226 +7276,226 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .LD1W = { 2191, 6}, .LD1D = { 2197, 5}, .LD1SB = { 2202, 3}, - .LD1SH = { 2205, 3}, - .LD1SW = { 2208, 2}, - .ST1B = { 2210, 6}, - .ST1H = { 2216, 6}, - .ST1W = { 2222, 6}, - .ST1D = { 2228, 5}, - .LDFF1B = { 2233, 1}, - .LDFF1H = { 2234, 1}, - .LDFF1W = { 2235, 1}, - .LDFF1D = { 2236, 1}, - .WHILEGE = { 2237, 1}, - .WHILEGT = { 2238, 1}, - .WHILELE = { 2239, 1}, - .WHILELT = { 2240, 1}, - .WHILEHI = { 2241, 1}, - .WHILEHS = { 2242, 1}, - .WHILELO = { 2243, 1}, - .WHILELS = { 2244, 1}, - .SQRDMLAH = { 2245, 4}, - .SQRDMLSH = { 2249, 4}, - .ADCLB = { 2253, 2}, - .ADCLT = { 2255, 2}, - .SBCLB = { 2257, 2}, - .SBCLT = { 2259, 2}, - .TBL2 = { 2261, 1}, - .MATCH = { 2262, 2}, - .NMATCH = { 2264, 2}, - .HISTCNT = { 2266, 2}, - .HISTSEG = { 2268, 1}, - .SMSTART = { 2269, 1}, - .SMSTOP = { 2270, 1}, - .RDSVL = { 2271, 1}, - .ADDHA = { 2272, 1}, - .ADDVA = { 2273, 1}, - .ZERO = { 2274, 1}, - .FMOPA = { 2275, 1}, - .FMOPS = { 2276, 1}, - .BFMOPA = { 2277, 1}, - .BFMOPS = { 2278, 1}, - .SMOPA = { 2279, 2}, - .SMOPS = { 2281, 2}, - .UMOPA = { 2283, 2}, - .UMOPS = { 2285, 2}, - .USMOPA = { 2287, 1}, - .SUMOPA = { 2288, 1}, - .LD1Q = { 2289, 1}, - .ST1Q = { 2290, 1}, - .MOVA = { 2291, 2}, - .FCMLA = { 2293, 4}, - .FCADD = { 2297, 4}, - .PRFB = { 2301, 1}, - .PRFH = { 2302, 1}, - .PRFW = { 2303, 1}, - .PRFD = { 2304, 1}, - .LDNT1B = { 2305, 1}, - .LDNT1H = { 2306, 1}, - .LDNT1W = { 2307, 1}, - .LDNT1D = { 2308, 1}, - .STNT1B = { 2309, 1}, - .STNT1H = { 2310, 1}, - .STNT1W = { 2311, 1}, - .STNT1D = { 2312, 1}, - .SPLICE = { 2313, 1}, - .INDEX = { 2314, 4}, - .BSL1N = { 2318, 1}, - .BSL2N = { 2319, 1}, - .NBSL = { 2320, 1}, - .PMUL = { 2321, 1}, - .PMULLB = { 2322, 1}, - .PMULLT = { 2323, 1}, - .BFCVTNT = { 2324, 1}, - .LDRAA = { 2325, 2}, - .LDRAB = { 2327, 2}, - .TSTART = { 2329, 1}, - .TCOMMIT = { 2330, 1}, - .TCANCEL = { 2331, 1}, - .TTEST = { 2332, 1}, - .WFET = { 2333, 1}, - .WFIT = { 2334, 1}, - .BC_EQ = { 2335, 1}, - .BC_NE = { 2336, 1}, - .BC_CS = { 2337, 1}, - .BC_CC = { 2338, 1}, - .BC_MI = { 2339, 1}, - .BC_PL = { 2340, 1}, - .BC_VS = { 2341, 1}, - .BC_VC = { 2342, 1}, - .BC_HI = { 2343, 1}, - .BC_LS = { 2344, 1}, - .BC_GE = { 2345, 1}, - .BC_LT = { 2346, 1}, - .BC_GT = { 2347, 1}, - .BC_LE = { 2348, 1}, - .BC_AL = { 2349, 1}, - .BC_NV = { 2350, 1}, - .UXTB = { 2351, 1}, - .UXTH = { 2352, 1}, - .UXTW = { 2353, 1}, - .SXTB = { 2354, 1}, - .SXTH = { 2355, 1}, - .SXTW = { 2356, 1}, - .ADC = { 2357, 2}, - .ADCS = { 2359, 2}, - .SBC = { 2361, 2}, - .SBCS = { 2363, 2}, - .NGC = { 2365, 2}, - .NGCS = { 2367, 2}, - .LDAPUR = { 2369, 2}, - .STLUR = { 2371, 2}, - .LDAPURB = { 2373, 1}, - .STLURB = { 2374, 1}, - .LDAPURH = { 2375, 1}, - .STLURH = { 2376, 1}, - .LDAPURSB = { 2377, 2}, - .LDAPURSH = { 2379, 2}, - .LDAPURSW = { 2381, 1}, - .BFADD = { 2382, 2}, - .BFSUB = { 2384, 2}, - .BFMUL = { 2386, 2}, - .BFMLA = { 2388, 1}, - .BFMLS = { 2389, 1}, - .SB = { 2390, 1}, - .CSDB = { 2391, 1}, - .DGH = { 2392, 1}, - .PSB_CSYNC = { 2393, 1}, - .TSB_CSYNC = { 2394, 1}, - .BTI_J = { 2395, 1}, - .BTI_C = { 2396, 1}, - .BTI_JC = { 2397, 1}, - .BFCLAMP = { 2398, 1}, - .BFMAXNM = { 2399, 1}, - .BFMINNM = { 2400, 1}, - .LUTI2 = { 2401, 1}, - .LUTI4 = { 2402, 1}, - .ZIP = { 2403, 2}, - .UZP = { 2405, 2}, - .TLBI_RPALOS = { 2407, 1}, - .TLBI_RPAOS = { 2408, 1}, - .AT_S1E1A = { 2409, 1}, - .DC_CIPAPA = { 2410, 1}, - .DC_CIGDPAPA = { 2411, 1}, - .TLBI_PAALL = { 2412, 1}, - .TLBI_PAALLOS = { 2413, 1}, - .AMX_LDX = { 2414, 1}, - .AMX_LDY = { 2415, 1}, - .AMX_STX = { 2416, 1}, - .AMX_STY = { 2417, 1}, - .AMX_LDZ = { 2418, 1}, - .AMX_STZ = { 2419, 1}, - .AMX_LDZI = { 2420, 1}, - .AMX_STZI = { 2421, 1}, - .AMX_EXTRX = { 2422, 1}, - .AMX_EXTRY = { 2423, 1}, - .AMX_FMA64 = { 2424, 1}, - .AMX_FMS64 = { 2425, 1}, - .AMX_FMA32 = { 2426, 1}, - .AMX_FMS32 = { 2427, 1}, - .AMX_MAC16 = { 2428, 1}, - .AMX_FMA16 = { 2429, 1}, - .AMX_FMS16 = { 2430, 1}, - .AMX_SET = { 2431, 1}, - .AMX_CLR = { 2432, 1}, - .AMX_VECINT = { 2433, 1}, - .AMX_VECFP = { 2434, 1}, - .AMX_MATINT = { 2435, 1}, - .AMX_MATFP = { 2436, 1}, - .AMX_GENLUT = { 2437, 1}, - .CPYP = { 2438, 1}, - .CPYM = { 2439, 1}, - .CPYE = { 2440, 1}, - .CPYFP = { 2441, 1}, - .CPYFM = { 2442, 1}, - .CPYFE = { 2443, 1}, - .SETP = { 2444, 1}, - .SETM = { 2445, 1}, - .SETE = { 2446, 1}, - .DC_IVAC = { 2447, 1}, - .DC_ISW = { 2448, 1}, - .DC_CSW = { 2449, 1}, - .DC_CISW = { 2450, 1}, - .DC_ZVA = { 2451, 1}, - .DC_CVAC = { 2452, 1}, - .DC_CVAU = { 2453, 1}, - .DC_CIVAC = { 2454, 1}, - .IC_IALLUIS = { 2455, 1}, - .IC_IALLU = { 2456, 1}, - .IC_IVAU = { 2457, 1}, - .AT_S1E1R = { 2458, 1}, - .AT_S1E1W = { 2459, 1}, - .AT_S1E0R = { 2460, 1}, - .AT_S1E0W = { 2461, 1}, - .AT_S1E2R = { 2462, 1}, - .AT_S1E2W = { 2463, 1}, - .AT_S1E3R = { 2464, 1}, - .AT_S1E3W = { 2465, 1}, - .AT_S12E1R = { 2466, 1}, - .AT_S12E1W = { 2467, 1}, - .AT_S12E0R = { 2468, 1}, - .AT_S12E0W = { 2469, 1}, - .TLBI_VMALLE1 = { 2470, 1}, - .TLBI_VMALLE1IS = { 2471, 1}, - .TLBI_VAE1 = { 2472, 1}, - .TLBI_VAE1IS = { 2473, 1}, - .TLBI_ASIDE1 = { 2474, 1}, - .TLBI_ASIDE1IS = { 2475, 1}, - .TLBI_VAAE1 = { 2476, 1}, - .TLBI_VAAE1IS = { 2477, 1}, - .TLBI_VALE1 = { 2478, 1}, - .TLBI_VALE1IS = { 2479, 1}, - .TLBI_VAALE1 = { 2480, 1}, - .TLBI_VAALE1IS = { 2481, 1}, - .TLBI_ALLE1 = { 2482, 1}, - .TLBI_ALLE1IS = { 2483, 1}, - .TLBI_ALLE2 = { 2484, 1}, - .TLBI_ALLE2IS = { 2485, 1}, - .TLBI_ALLE3 = { 2486, 1}, - .TLBI_ALLE3IS = { 2487, 1}, - .PRFM = { 2488, 2}, - .PRFUM = { 2490, 1}, - .NEGS = { 2491, 2}, - .CMP = { 2493, 6}, - .CMN = { 2499, 6}, + .LD1SH = { 2205, 4}, + .LD1SW = { 2209, 2}, + .ST1B = { 2211, 6}, + .ST1H = { 2217, 6}, + .ST1W = { 2223, 6}, + .ST1D = { 2229, 5}, + .LDFF1B = { 2234, 1}, + .LDFF1H = { 2235, 1}, + .LDFF1W = { 2236, 1}, + .LDFF1D = { 2237, 1}, + .WHILEGE = { 2238, 1}, + .WHILEGT = { 2239, 1}, + .WHILELE = { 2240, 1}, + .WHILELT = { 2241, 1}, + .WHILEHI = { 2242, 1}, + .WHILEHS = { 2243, 1}, + .WHILELO = { 2244, 1}, + .WHILELS = { 2245, 1}, + .SQRDMLAH = { 2246, 4}, + .SQRDMLSH = { 2250, 4}, + .ADCLB = { 2254, 2}, + .ADCLT = { 2256, 2}, + .SBCLB = { 2258, 2}, + .SBCLT = { 2260, 2}, + .TBL2 = { 2262, 1}, + .MATCH = { 2263, 2}, + .NMATCH = { 2265, 2}, + .HISTCNT = { 2267, 2}, + .HISTSEG = { 2269, 1}, + .SMSTART = { 2270, 1}, + .SMSTOP = { 2271, 1}, + .RDSVL = { 2272, 1}, + .ADDHA = { 2273, 1}, + .ADDVA = { 2274, 1}, + .ZERO = { 2275, 1}, + .FMOPA = { 2276, 1}, + .FMOPS = { 2277, 1}, + .BFMOPA = { 2278, 1}, + .BFMOPS = { 2279, 1}, + .SMOPA = { 2280, 2}, + .SMOPS = { 2282, 2}, + .UMOPA = { 2284, 2}, + .UMOPS = { 2286, 2}, + .USMOPA = { 2288, 1}, + .SUMOPA = { 2289, 1}, + .LD1Q = { 2290, 1}, + .ST1Q = { 2291, 1}, + .MOVA = { 2292, 2}, + .FCMLA = { 2294, 4}, + .FCADD = { 2298, 4}, + .PRFB = { 2302, 1}, + .PRFH = { 2303, 1}, + .PRFW = { 2304, 1}, + .PRFD = { 2305, 1}, + .LDNT1B = { 2306, 1}, + .LDNT1H = { 2307, 1}, + .LDNT1W = { 2308, 1}, + .LDNT1D = { 2309, 1}, + .STNT1B = { 2310, 1}, + .STNT1H = { 2311, 1}, + .STNT1W = { 2312, 1}, + .STNT1D = { 2313, 1}, + .SPLICE = { 2314, 1}, + .INDEX = { 2315, 4}, + .BSL1N = { 2319, 1}, + .BSL2N = { 2320, 1}, + .NBSL = { 2321, 1}, + .PMUL = { 2322, 1}, + .PMULLB = { 2323, 1}, + .PMULLT = { 2324, 1}, + .BFCVTNT = { 2325, 1}, + .LDRAA = { 2326, 2}, + .LDRAB = { 2328, 2}, + .TSTART = { 2330, 1}, + .TCOMMIT = { 2331, 1}, + .TCANCEL = { 2332, 1}, + .TTEST = { 2333, 1}, + .WFET = { 2334, 1}, + .WFIT = { 2335, 1}, + .BC_EQ = { 2336, 1}, + .BC_NE = { 2337, 1}, + .BC_CS = { 2338, 1}, + .BC_CC = { 2339, 1}, + .BC_MI = { 2340, 1}, + .BC_PL = { 2341, 1}, + .BC_VS = { 2342, 1}, + .BC_VC = { 2343, 1}, + .BC_HI = { 2344, 1}, + .BC_LS = { 2345, 1}, + .BC_GE = { 2346, 1}, + .BC_LT = { 2347, 1}, + .BC_GT = { 2348, 1}, + .BC_LE = { 2349, 1}, + .BC_AL = { 2350, 1}, + .BC_NV = { 2351, 1}, + .UXTB = { 2352, 1}, + .UXTH = { 2353, 1}, + .UXTW = { 2354, 1}, + .SXTB = { 2355, 1}, + .SXTH = { 2356, 1}, + .SXTW = { 2357, 1}, + .ADC = { 2358, 2}, + .ADCS = { 2360, 2}, + .SBC = { 2362, 2}, + .SBCS = { 2364, 2}, + .NGC = { 2366, 2}, + .NGCS = { 2368, 2}, + .LDAPUR = { 2370, 2}, + .STLUR = { 2372, 2}, + .LDAPURB = { 2374, 1}, + .STLURB = { 2375, 1}, + .LDAPURH = { 2376, 1}, + .STLURH = { 2377, 1}, + .LDAPURSB = { 2378, 2}, + .LDAPURSH = { 2380, 2}, + .LDAPURSW = { 2382, 1}, + .BFADD = { 2383, 2}, + .BFSUB = { 2385, 2}, + .BFMUL = { 2387, 2}, + .BFMLA = { 2389, 1}, + .BFMLS = { 2390, 1}, + .SB = { 2391, 1}, + .CSDB = { 2392, 1}, + .DGH = { 2393, 1}, + .PSB_CSYNC = { 2394, 1}, + .TSB_CSYNC = { 2395, 1}, + .BTI_J = { 2396, 1}, + .BTI_C = { 2397, 1}, + .BTI_JC = { 2398, 1}, + .BFCLAMP = { 2399, 1}, + .BFMAXNM = { 2400, 1}, + .BFMINNM = { 2401, 1}, + .LUTI2 = { 2402, 3}, + .LUTI4 = { 2405, 3}, + .ZIP = { 2408, 2}, + .UZP = { 2410, 2}, + .TLBI_RPALOS = { 2412, 1}, + .TLBI_RPAOS = { 2413, 1}, + .AT_S1E1A = { 2414, 1}, + .DC_CIPAPA = { 2415, 1}, + .DC_CIGDPAPA = { 2416, 1}, + .TLBI_PAALL = { 2417, 1}, + .TLBI_PAALLOS = { 2418, 1}, + .AMX_LDX = { 2419, 1}, + .AMX_LDY = { 2420, 1}, + .AMX_STX = { 2421, 1}, + .AMX_STY = { 2422, 1}, + .AMX_LDZ = { 2423, 1}, + .AMX_STZ = { 2424, 1}, + .AMX_LDZI = { 2425, 1}, + .AMX_STZI = { 2426, 1}, + .AMX_EXTRX = { 2427, 1}, + .AMX_EXTRY = { 2428, 1}, + .AMX_FMA64 = { 2429, 1}, + .AMX_FMS64 = { 2430, 1}, + .AMX_FMA32 = { 2431, 1}, + .AMX_FMS32 = { 2432, 1}, + .AMX_MAC16 = { 2433, 1}, + .AMX_FMA16 = { 2434, 1}, + .AMX_FMS16 = { 2435, 1}, + .AMX_SET = { 2436, 1}, + .AMX_CLR = { 2437, 1}, + .AMX_VECINT = { 2438, 1}, + .AMX_VECFP = { 2439, 1}, + .AMX_MATINT = { 2440, 1}, + .AMX_MATFP = { 2441, 1}, + .AMX_GENLUT = { 2442, 1}, + .CPYP = { 2443, 1}, + .CPYM = { 2444, 1}, + .CPYE = { 2445, 1}, + .CPYFP = { 2446, 1}, + .CPYFM = { 2447, 1}, + .CPYFE = { 2448, 1}, + .SETP = { 2449, 1}, + .SETM = { 2450, 1}, + .SETE = { 2451, 1}, + .DC_IVAC = { 2452, 1}, + .DC_ISW = { 2453, 1}, + .DC_CSW = { 2454, 1}, + .DC_CISW = { 2455, 1}, + .DC_ZVA = { 2456, 1}, + .DC_CVAC = { 2457, 1}, + .DC_CVAU = { 2458, 1}, + .DC_CIVAC = { 2459, 1}, + .IC_IALLUIS = { 2460, 1}, + .IC_IALLU = { 2461, 1}, + .IC_IVAU = { 2462, 1}, + .AT_S1E1R = { 2463, 1}, + .AT_S1E1W = { 2464, 1}, + .AT_S1E0R = { 2465, 1}, + .AT_S1E0W = { 2466, 1}, + .AT_S1E2R = { 2467, 1}, + .AT_S1E2W = { 2468, 1}, + .AT_S1E3R = { 2469, 1}, + .AT_S1E3W = { 2470, 1}, + .AT_S12E1R = { 2471, 1}, + .AT_S12E1W = { 2472, 1}, + .AT_S12E0R = { 2473, 1}, + .AT_S12E0W = { 2474, 1}, + .TLBI_VMALLE1 = { 2475, 1}, + .TLBI_VMALLE1IS = { 2476, 1}, + .TLBI_VAE1 = { 2477, 1}, + .TLBI_VAE1IS = { 2478, 1}, + .TLBI_ASIDE1 = { 2479, 1}, + .TLBI_ASIDE1IS = { 2480, 1}, + .TLBI_VAAE1 = { 2481, 1}, + .TLBI_VAAE1IS = { 2482, 1}, + .TLBI_VALE1 = { 2483, 1}, + .TLBI_VALE1IS = { 2484, 1}, + .TLBI_VAALE1 = { 2485, 1}, + .TLBI_VAALE1IS = { 2486, 1}, + .TLBI_ALLE1 = { 2487, 1}, + .TLBI_ALLE1IS = { 2488, 1}, + .TLBI_ALLE2 = { 2489, 1}, + .TLBI_ALLE2IS = { 2490, 1}, + .TLBI_ALLE3 = { 2491, 1}, + .TLBI_ALLE3IS = { 2492, 1}, + .PRFM = { 2493, 2}, + .PRFUM = { 2495, 1}, + .NEGS = { 2496, 2}, + .CMP = { 2498, 6}, + .CMN = { 2504, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 5ea78dfc8..66692ee65 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -340,10 +340,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .CLS = { {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, @@ -354,10 +354,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .RBIT = { {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, @@ -663,16 +663,16 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, @@ -759,9 +759,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FNEG = { {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, @@ -772,9 +772,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .FSQRT = { {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, @@ -785,9 +785,9 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, @@ -1253,25 +1253,25 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, @@ -1607,7 +1607,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.IMM_2, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFF8FF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, }, .IRG = { {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, @@ -1841,10 +1841,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, }, @@ -1856,10 +1856,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .SHADD = { {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3160,10 +3160,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .CNT = { {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, }, .URECPE = { {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, @@ -3478,27 +3478,27 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, @@ -3506,12 +3506,13 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { @@ -3523,39 +3524,39 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5C04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -3686,7 +3687,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, {written={0}, read={1, 2}}}, {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, }, .FCMLA = { @@ -3696,46 +3697,46 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, @@ -3966,18 +3967,22 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR_B, .Z_PAIR_B, .Z_REG_B, .IMM_3}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08C4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR_B, .Z_PAIR_B, .Z_REG_B, .IMM_2}, {.ENC_Z_PAIR_VD, .ENC_Z_PAIR_VN, .VM, .IMM12}, 0xC08A4000, 0xFFE0F000, .SME, {}}, {written={0}, read={1}}}, + {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, }, .ZIP = { {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, {written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, @@ -4094,10 +4099,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin 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a/core/rexcode/isa/arm64/tests/smoke.odin +++ b/core/rexcode/isa/arm64/tests/smoke.odin @@ -190,7 +190,7 @@ main :: proc() { check("MUL S", .MUL, 5, 0x04900000, 0xFFFFE000) check("SVE_SDIV S", .SDIV, 2, 0x04940000, 0xFFFFE000) check("ASR D", .ASR, 5, 0x04D08000, 0xFFFFE000) - check("NEG D", .NEG, 10, 0x04D7A000, 0xFFE0E000) + check("NEG D", .NEG, 10, 0x04D7A000, 0xFFF7E000) // ---- SVE -- bitwise predicated ------------------------------------------ check("AND D", .AND, 5, 0x041A0000, 0xFFFFE000) @@ -261,8 +261,8 @@ main :: proc() { check("CPYFM", .CPYFM, 0, 0x19400400, 0xFFE03C00) check("CPYFE", .CPYFE, 0, 0x19800400, 0xFFE03C00) check("SETP", .SETP, 0, 0x19C00400, 0xFFE03C00) - check("SETM", .SETM, 0, 0x19C04400, 0xFFE03C00) - check("SETE", .SETE, 0, 0x19C08400, 0xFFE03C00) + check("SETM", .SETM, 0, 0x19C04400, 0xFFE07C00) + check("SETE", .SETE, 0, 0x19C08400, 0xFFE0BC00) // ---- Cache management --------------------------------------------------- check("DC IVAC", .DC_IVAC, 0, 0xD5087620, 0xFFFFFFE0) @@ -330,7 +330,7 @@ main :: proc() { check("SME_LD1Q_TILE", .LD1Q, 0, 0xE1C00000, 0xFFE00010) check("SME_ST1B_TILE", .ST1B, 3, 0xE0200000, 0xFFE00010) check("SME_ST1W_TILE", .ST1W, 3, 0xE0A00000, 0xFFE00010) - check("SME_MOVA_Z_FROM_TILE", .MOVA, 0, 0xC0020000, 0xFFE08010) + check("SME_MOVA_Z_FROM_TILE", .MOVA, 0, 0xC0020000, 0xFFE28010) check("SME_MOVA_TILE_FROM_Z", .MOVA, 1, 0xC0000000, 0xFFE08010) // ---- NEON FCMLA / FCADD (v8.3-A FCMA) -- verified vs LLVM golden ----- @@ -338,7 +338,7 @@ main :: proc() { check("FCMLA_8H", .FCMLA, 1, 0x6E40C400, 0xFFE0CC00) check("FCMLA_4S", .FCMLA, 2, 0x6E80C400, 0xFFE0CC00) check("FCMLA_2D", .FCMLA, 3, 0x6EC0C400, 0xFFE0CC00) - check("FCADD_4H", .FCADD, 0, 0x2E40E400, 0xFFA0EC00) + check("FCADD_4H", .FCADD, 0, 0x2E40E400, 0xFFE0EC00) check("FCADD_4S", .FCADD, 2, 0x6E80E400, 0xFFA0EC00) // ---- SVE prefetch ---------------------------------------------------- @@ -457,13 +457,13 @@ main :: proc() { check("BFMINNM", .BFMINNM, 0, 0x65058000, 0xFFFFE000) // ---- SME2 multi-vector ---------------------------------------------- - check("SME2 LUTI2.B", .LUTI2, 0, 0xC08C4000, 0xFFE0F000) - check("SME2 LUTI4.B", .LUTI4, 0, 0xC08A4000, 0xFFE0F000) + check("SME2 LUTI2.B", .LUTI2, 0, 0xC08C4000, 0xFFFE7C00) + check("SME2 LUTI4.B", .LUTI4, 0, 0xC08A4000, 0xFFFE7C00) check("SME2 LD1B x2", .LD1B, 4, 0xA0000000, 0xFFE0E000) check("SME2 LD1W x4", .LD1W, 5, 0xA000C000, 0xFFE0E000) check("SME2 ST1D x2", .ST1D, 3, 0xA0206000, 0xFFE0E000) check("SME2 ZIP_4", .ZIP, 1, 0xC136E000, 0xFFFFFC00) - check("SME2 UZP_3", .UZP, 0, 0xC120D001, 0xFFE0FC00) + check("SME2 UZP_3", .UZP, 0, 0xC120D001, 0xFFE0FC01) // ---- RME (Realm Management Extension) ------------------------------- check("TLBI RPALOS", .TLBI_RPALOS, 0, 0xD5084EE0, 0xFFFFFFE0) diff --git a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin index 13707a956..1baf215a4 100644 --- a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin @@ -71,6 +71,7 @@ Operand_Category :: enum { MEM, // Memory -> op_mem (1 param, suffix m) COND, // Cond -> op_cond (1 param, suffix c) SYSREG, // System_Register -> op_sysreg (1 param, suffix s) + IMPLICIT, // no parameter -- the operand names the only register it can SHIFTED, // Register + Shift_Type + u8 -> op_shifted (3 params, suffix sh) EXTENDED, // Register + Extend + u8 -> op_extended (3 params, suffix ex) } @@ -134,6 +135,9 @@ operand_category :: proc(t: a.Operand_Type) -> Operand_Category { case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV, .PN_REG, .PN_REG_ZERO, .P_REG_B, .P_REG_H, .P_REG_S, .P_REG_D: return .PREG + case .ZT_REG: + // There is only one ZT register, so it takes no parameter at all. + return .IMPLICIT case .REL_26, .REL_19, .REL_14, .REL_PG21: return .REL case .MEM_OFFSET, .MEM_PRE, .MEM_POST, .MEM_REG, .MEM_EXT, @@ -212,7 +216,7 @@ is_lane_index :: proc(e: a.Operand_Encoding) -> bool { #partial switch e { case .NEON_IDX5, .NEON_IDX4, .NEON_IDX2, .NEON_LANE_B, .NEON_LANE_H, .NEON_LANE_S, .NEON_LANE_D, - .SVE_FMLA_IDX_H, .SVE_FMLA_IDX_S, .SVE_FMLA_IDX_D: + .SVE_FMLA_IDX_H, .SVE_FMLA_IDX_S, .SVE_FMLA_IDX_D, .LUTI_IDX: return true } return false @@ -286,6 +290,7 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { case .MEM: return "m" case .COND: return "c" case .SYSREG: return "s" + case .IMPLICIT: return "zt" case .SHIFTED: return "sh" case .EXTENDED: return "ex" } @@ -367,6 +372,8 @@ operand_primary_names :: proc(sig: Operand_Signature) -> [4][3]string { result[i][0] = "cond" case .SYSREG: result[i][0] = "sysreg" + case .IMPLICIT: + result[i][0] = "" case .SHIFTED: rn := reg_name(i, ®_count) result[i][0] = rn @@ -394,6 +401,8 @@ param_list :: proc(sig: Operand_Signature) -> [dynamic]Param { append(¶ms, Param{decl = fmt.tprintf("%s: Register", names[i][0]), name = names[i][0]}) case .ZREG, .PREG: append(¶ms, Param{decl = fmt.tprintf("%s: u8", names[i][0]), name = names[i][0]}) + case .IMPLICIT: + // no parameter case .IMM: append(¶ms, Param{decl = fmt.tprintf("%s: i64", names[i][0]), name = names[i][0]}) case .REL: @@ -506,6 +515,8 @@ write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, enc: a.Opera fmt.sbprintf(sb, "op_cond(%s)", names[0]) case .SYSREG: fmt.sbprintf(sb, "op_sysreg(%s)", names[0]) + case .IMPLICIT: + strings.write_string(sb, "op_reg(ZT0)") case .SHIFTED: fmt.sbprintf(sb, "op_shifted(%s, %s, %s)", names[0], names[1], names[2]) case .EXTENDED: From fe76fb97cb3681f037f36154cd5b8e506d5332ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fl=C4=81vius?= Date: Fri, 28 Aug 2026 16:21:49 -0400 Subject: [PATCH 42/89] x86: a baked enc_hint must name a form of its own mnemonic mnemonic_builders.odin bakes `global_index + 1` into Instruction.enc_hint so the encoder can skip the O(forms) match scan. The index is GLOBAL, so any edit to the encoding table that inserts or removes a form shifts every index after it and leaves the builders naming another instruction's encoding -- and nothing noticed: the encoder took the form, emitted its bytes and returned success. It has happened twice. 6e17e7a2d left 2130 of 3671 builders wrong; 36af73834 regenerated both halves and cleared it; baae2636b (adding `in`/`out`) re-broke 37; 9ae9a9bf9 shifted an early mnemonic and broke 3393 of 3802 -- including CALL, whose r/m64 builder then encoded 0F 8A (JPE) instead of FF /2, turning every indirect call into a conditional jump. The symptom was a segfault in a JIT'd program, arbitrarily far from the cause. Regenerated: 3820 of 3820 builders now correct. Three guards so it cannot return silently: - the encoder checks, under ODIN_DEBUG, that the hinted form lies inside its own mnemonic's ENCODE_RUNS entry. Release keeps the byte-for-byte fast path; this is a regeneration-time mistake and only has to be caught once by anyone running tests. - the generator stamps BUILDER_TABLE_FINGERPRINT, an FNV-1a hash of every ENCODE_RUNS (start, count), into the file it emits. - run_builder_generation_test recomputes it from the loaded tables and fails with the command to regenerate. Known-failing at this commit: four SAL/SHL cases, a separate defect in the alias table, fixed in the commit that follows. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz --- core/rexcode/isa/x86/encoder.odin | 21 + core/rexcode/isa/x86/mnemonic_builders.odin | 6831 +++++++++-------- core/rexcode/isa/x86/tests/test.odin | 37 + .../isa/x86/tools/gen_mnemonic_builders.odin | 25 + 4 files changed, 3521 insertions(+), 3393 deletions(-) diff --git a/core/rexcode/isa/x86/encoder.odin b/core/rexcode/isa/x86/encoder.odin index 1df1fd823..b26df442f 100644 --- a/core/rexcode/isa/x86/encoder.odin +++ b/core/rexcode/isa/x86/encoder.odin @@ -159,6 +159,27 @@ encode :: proc( if mode == ._64 && inst.enc_hint != ENC_HINT_NONE && int(inst.enc_hint) <= len(ENCODE_FORMS) { form_index = int(inst.enc_hint) - 1 matched_enc = &ENCODE_FORMS[form_index] + /* THE HINT MUST NAME A FORM OF THIS MNEMONIC. The bounds check above is not enough: the + index is GLOBAL and baked into `mnemonic_builders.odin` at generation time, so any + later edit to the encoding table that inserts or removes a form shifts every index + after it and leaves the builders naming someone else's instruction. Nothing here + noticed โ€” the encoder took the form, emitted its bytes, and returned success. + + It has happened twice. `6e17e7a2d` left 2130 of 3671 builders pointing at the wrong + form; `36af73834` regenerated both halves and cleared it; `baae2636b` (adding `in` + and `out`) re-broke 37; `9ae9a9bf9` shifted an early mnemonic and broke 3393 of 3802, + including CALL โ€” whose r/m64 builder then encoded `0F 8A` (JPE) instead of `FF /2`, + turning every indirect call into a conditional jump. The symptom was a segfault in a + JIT'd program, arbitrarily far from the cause. + + Debug-only, so the release fast path is byte-for-byte what it was: this is a + REGENERATION-TIME mistake, and it only has to be caught once by anyone running tests. */ + when ODIN_DEBUG { + run := ENCODE_RUNS[inst.mnemonic] + if form_index < int(run.start) || form_index >= int(run.start) + int(run.count) { + panic("rexcode/x86: a baked enc_hint names a form outside its own mnemonic's run โ€” mnemonic_builders.odin is stale relative to tables/x86.encode_*.bin. Regenerate it: odin run core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin -file") + } + } } else { // Resolve the form on the matcher path (memoizing cache + scan) in a // separate, non-inlined proc so this hot loop stays lean for the hint diff --git a/core/rexcode/isa/x86/mnemonic_builders.odin b/core/rexcode/isa/x86/mnemonic_builders.odin index 80e533958..93991e23d 100644 --- a/core/rexcode/isa/x86/mnemonic_builders.odin +++ b/core/rexcode/isa/x86/mnemonic_builders.odin @@ -889,22 +889,54 @@ emit_sar_r64 :: #force_inline proc(instructions: ^[dynami emit_sar_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_sar_m64(dst)) } emit_sar_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_sar_r64_imm8(dst, imm)) } emit_sar_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_sar_m64_imm8(dst, imm)) } -inst_rol_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 323) } -inst_rol_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 323) } -inst_rol_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 325) } -inst_rol_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 325) } -inst_rol_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 326) } -inst_rol_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 326) } -inst_rol_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 328) } -inst_rol_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 328) } -inst_rol_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 329) } -inst_rol_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 329) } -inst_rol_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 331) } -inst_rol_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 331) } -inst_rol_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 332) } -inst_rol_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 332) } -inst_rol_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 334) } -inst_rol_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 334) } +inst_sal_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 323) } +inst_sal_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 323) } +inst_sal_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 325) } +inst_sal_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 325) } +inst_sal_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 326) } +inst_sal_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 326) } +inst_sal_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 328) } +inst_sal_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 328) } +inst_sal_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 329) } +inst_sal_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 329) } +inst_sal_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 331) } +inst_sal_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 331) } +inst_sal_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 332) } +inst_sal_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 332) } +inst_sal_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 334) } +inst_sal_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SAL, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 334) } +emit_sal_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_sal_r8(dst)) } +emit_sal_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_sal_m8(dst)) } +emit_sal_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, imm: i8) { append(instructions, inst_sal_r8_imm8(dst, imm)) } +emit_sal_m8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, imm: i8) { append(instructions, inst_sal_m8_imm8(dst, imm)) } +emit_sal_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_sal_r16(dst)) } +emit_sal_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_sal_m16(dst)) } +emit_sal_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, imm: i8) { append(instructions, inst_sal_r16_imm8(dst, imm)) } +emit_sal_m16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, imm: i8) { append(instructions, inst_sal_m16_imm8(dst, imm)) } +emit_sal_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_sal_r32(dst)) } +emit_sal_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_sal_m32(dst)) } +emit_sal_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, imm: i8) { append(instructions, inst_sal_r32_imm8(dst, imm)) } +emit_sal_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, imm: i8) { append(instructions, inst_sal_m32_imm8(dst, imm)) } +emit_sal_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_sal_r64(dst)) } +emit_sal_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_sal_m64(dst)) } +emit_sal_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_sal_r64_imm8(dst, imm)) } +emit_sal_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_sal_m64_imm8(dst, imm)) } +inst_rol_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 335) } +inst_rol_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 335) } +inst_rol_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 337) } +inst_rol_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 337) } +inst_rol_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 338) } +inst_rol_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 338) } +inst_rol_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 340) } +inst_rol_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 340) } +inst_rol_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 341) } +inst_rol_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 341) } +inst_rol_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 343) } +inst_rol_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 343) } +inst_rol_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 344) } +inst_rol_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 344) } +inst_rol_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 346) } +inst_rol_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROL, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 346) } emit_rol_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_rol_r8(dst)) } emit_rol_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_rol_m8(dst)) } emit_rol_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, imm: i8) { append(instructions, inst_rol_r8_imm8(dst, imm)) } @@ -921,22 +953,22 @@ emit_rol_r64 :: #force_inline proc(instructions: ^[dynami emit_rol_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_rol_m64(dst)) } emit_rol_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_rol_r64_imm8(dst, imm)) } emit_rol_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_rol_m64_imm8(dst, imm)) } -inst_ror_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 335) } -inst_ror_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 335) } -inst_ror_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 337) } -inst_ror_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 337) } -inst_ror_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 338) } -inst_ror_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 338) } -inst_ror_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 340) } -inst_ror_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 340) } -inst_ror_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 341) } -inst_ror_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 341) } -inst_ror_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 343) } -inst_ror_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 343) } -inst_ror_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 344) } -inst_ror_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 344) } -inst_ror_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 346) } -inst_ror_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 346) } +inst_ror_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 347) } +inst_ror_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 347) } +inst_ror_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 349) } +inst_ror_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 349) } +inst_ror_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 350) } +inst_ror_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 350) } +inst_ror_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 352) } +inst_ror_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 352) } +inst_ror_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 353) } +inst_ror_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 353) } +inst_ror_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 355) } +inst_ror_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 355) } +inst_ror_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 356) } +inst_ror_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 356) } +inst_ror_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 358) } +inst_ror_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 358) } emit_ror_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_ror_r8(dst)) } emit_ror_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_ror_m8(dst)) } emit_ror_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, imm: i8) { append(instructions, inst_ror_r8_imm8(dst, imm)) } @@ -953,22 +985,22 @@ emit_ror_r64 :: #force_inline proc(instructions: ^[dynami emit_ror_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_ror_m64(dst)) } emit_ror_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_ror_r64_imm8(dst, imm)) } emit_ror_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_ror_m64_imm8(dst, imm)) } -inst_rcl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 347) } -inst_rcl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 347) } -inst_rcl_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 349) } -inst_rcl_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 349) } -inst_rcl_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 350) } -inst_rcl_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 350) } -inst_rcl_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 352) } -inst_rcl_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 352) } -inst_rcl_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 353) } -inst_rcl_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 353) } -inst_rcl_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 355) } -inst_rcl_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 355) } -inst_rcl_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 356) } -inst_rcl_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 356) } -inst_rcl_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 358) } -inst_rcl_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 358) } +inst_rcl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 359) } +inst_rcl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 359) } +inst_rcl_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 361) } +inst_rcl_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 361) } +inst_rcl_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 362) } +inst_rcl_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 362) } +inst_rcl_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 364) } +inst_rcl_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 364) } +inst_rcl_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 365) } +inst_rcl_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 365) } +inst_rcl_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 367) } +inst_rcl_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 367) } +inst_rcl_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 368) } +inst_rcl_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 368) } +inst_rcl_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 370) } +inst_rcl_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCL, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 370) } emit_rcl_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_rcl_r8(dst)) } emit_rcl_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_rcl_m8(dst)) } emit_rcl_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, imm: i8) { append(instructions, inst_rcl_r8_imm8(dst, imm)) } @@ -985,22 +1017,22 @@ emit_rcl_r64 :: #force_inline proc(instructions: ^[dynami emit_rcl_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_rcl_m64(dst)) } emit_rcl_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_rcl_r64_imm8(dst, imm)) } emit_rcl_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_rcl_m64_imm8(dst, imm)) } -inst_rcr_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 359) } -inst_rcr_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 359) } -inst_rcr_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 361) } -inst_rcr_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 361) } -inst_rcr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 362) } -inst_rcr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 362) } -inst_rcr_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 364) } -inst_rcr_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 364) } -inst_rcr_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 365) } -inst_rcr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 365) } -inst_rcr_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 367) } -inst_rcr_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 367) } -inst_rcr_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 368) } -inst_rcr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 368) } -inst_rcr_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 370) } -inst_rcr_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 370) } +inst_rcr_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 371) } +inst_rcr_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 371) } +inst_rcr_r8_imm8 :: #force_inline proc "contextless" (dst: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr8(dst), op_imm8(imm), {}, {}} }, 373) } +inst_rcr_m8_imm8 :: #force_inline proc "contextless" (dst: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 1), op_imm8(imm), {}, {}} }, 373) } +inst_rcr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 374) } +inst_rcr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 374) } +inst_rcr_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 376) } +inst_rcr_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 376) } +inst_rcr_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 377) } +inst_rcr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 377) } +inst_rcr_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 379) } +inst_rcr_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 379) } +inst_rcr_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 380) } +inst_rcr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 380) } +inst_rcr_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 382) } +inst_rcr_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RCR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 382) } emit_rcr_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_rcr_r8(dst)) } emit_rcr_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_rcr_m8(dst)) } emit_rcr_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, imm: i8) { append(instructions, inst_rcr_r8_imm8(dst, imm)) } @@ -1017,18 +1049,18 @@ emit_rcr_r64 :: #force_inline proc(instructions: ^[dynami emit_rcr_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_rcr_m64(dst)) } emit_rcr_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_rcr_r64_imm8(dst, imm)) } emit_rcr_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_rcr_m64_imm8(dst, imm)) } -inst_shld_r16_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr16(dst), op_gpr16(src), op_imm8(imm), {}} }, 371) } -inst_shld_m16_r16_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 2), op_gpr16(src), op_imm8(imm), {}} }, 371) } -inst_shld_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 372) } -inst_shld_m32_r32_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_gpr32(src), op_imm8(imm), {}} }, 372) } -inst_shld_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 373) } -inst_shld_m64_r64_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 8), op_gpr64(src), op_imm8(imm), {}} }, 373) } -inst_shld_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 374) } -inst_shld_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 374) } -inst_shld_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 375) } -inst_shld_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 375) } -inst_shld_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 376) } -inst_shld_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 376) } +inst_shld_r16_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr16(dst), op_gpr16(src), op_imm8(imm), {}} }, 383) } +inst_shld_m16_r16_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 2), op_gpr16(src), op_imm8(imm), {}} }, 383) } +inst_shld_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 384) } +inst_shld_m32_r32_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_gpr32(src), op_imm8(imm), {}} }, 384) } +inst_shld_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 385) } +inst_shld_m64_r64_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 3, ops = {op_mem(dst.mem, 8), op_gpr64(src), op_imm8(imm), {}} }, 385) } +inst_shld_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 386) } +inst_shld_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 386) } +inst_shld_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 387) } +inst_shld_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 387) } +inst_shld_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 388) } +inst_shld_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 388) } emit_shld_r16_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16, imm: i8) { append(instructions, inst_shld_r16_r16_imm8(dst, src, imm)) } emit_shld_m16_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16, imm: i8) { append(instructions, inst_shld_m16_r16_imm8(dst, src, imm)) } emit_shld_r32_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, imm: i8) { append(instructions, inst_shld_r32_r32_imm8(dst, src, imm)) } @@ -1041,18 +1073,18 @@ emit_shld_r32_r32 :: #force_inline proc(instructions: ^[dynami emit_shld_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_shld_m32_r32(dst, src)) } emit_shld_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_shld_r64_r64(dst, src)) } emit_shld_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_shld_m64_r64(dst, src)) } -inst_shrd_r16_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr16(dst), op_gpr16(src), op_imm8(imm), {}} }, 377) } -inst_shrd_m16_r16_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 2), op_gpr16(src), op_imm8(imm), {}} }, 377) } -inst_shrd_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 378) } -inst_shrd_m32_r32_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_gpr32(src), op_imm8(imm), {}} }, 378) } -inst_shrd_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 379) } -inst_shrd_m64_r64_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 8), op_gpr64(src), op_imm8(imm), {}} }, 379) } -inst_shrd_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 380) } -inst_shrd_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 380) } -inst_shrd_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 381) } -inst_shrd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 381) } -inst_shrd_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 382) } -inst_shrd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 382) } +inst_shrd_r16_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr16(dst), op_gpr16(src), op_imm8(imm), {}} }, 389) } +inst_shrd_m16_r16_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 2), op_gpr16(src), op_imm8(imm), {}} }, 389) } +inst_shrd_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 390) } +inst_shrd_m32_r32_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_gpr32(src), op_imm8(imm), {}} }, 390) } +inst_shrd_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 391) } +inst_shrd_m64_r64_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 3, ops = {op_mem(dst.mem, 8), op_gpr64(src), op_imm8(imm), {}} }, 391) } +inst_shrd_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 392) } +inst_shrd_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 392) } +inst_shrd_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 393) } +inst_shrd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 393) } +inst_shrd_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 394) } +inst_shrd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 394) } emit_shrd_r16_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16, imm: i8) { append(instructions, inst_shrd_r16_r16_imm8(dst, src, imm)) } emit_shrd_m16_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16, imm: i8) { append(instructions, inst_shrd_m16_r16_imm8(dst, src, imm)) } emit_shrd_r32_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, imm: i8) { append(instructions, inst_shrd_r32_r32_imm8(dst, src, imm)) } @@ -1065,18 +1097,18 @@ emit_shrd_r32_r32 :: #force_inline proc(instructions: ^[dynami emit_shrd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_shrd_m32_r32(dst, src)) } emit_shrd_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_shrd_r64_r64(dst, src)) } emit_shrd_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_shrd_m64_r64(dst, src)) } -inst_bt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 383) } -inst_bt_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 383) } -inst_bt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 384) } -inst_bt_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 384) } -inst_bt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 385) } -inst_bt_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 385) } -inst_bt_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 386) } -inst_bt_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 386) } -inst_bt_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 387) } -inst_bt_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 387) } -inst_bt_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 388) } -inst_bt_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 388) } +inst_bt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 395) } +inst_bt_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 395) } +inst_bt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 396) } +inst_bt_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 396) } +inst_bt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 397) } +inst_bt_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 397) } +inst_bt_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 398) } +inst_bt_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 398) } +inst_bt_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 399) } +inst_bt_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 399) } +inst_bt_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 400) } +inst_bt_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BT, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 400) } emit_bt_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_bt_r16_r16(dst, src)) } emit_bt_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_bt_m16_r16(dst, src)) } emit_bt_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_bt_r32_r32(dst, src)) } @@ -1089,18 +1121,18 @@ emit_bt_r32_imm8 :: #force_inline proc(instructions: ^[dynami emit_bt_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, imm: i8) { append(instructions, inst_bt_m32_imm8(dst, imm)) } emit_bt_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_bt_r64_imm8(dst, imm)) } emit_bt_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_bt_m64_imm8(dst, imm)) } -inst_bts_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 389) } -inst_bts_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 389) } -inst_bts_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 390) } -inst_bts_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 390) } -inst_bts_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 391) } -inst_bts_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 391) } -inst_bts_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 392) } -inst_bts_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 392) } -inst_bts_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 393) } -inst_bts_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 393) } -inst_bts_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 394) } -inst_bts_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 394) } +inst_bts_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 401) } +inst_bts_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 401) } +inst_bts_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 402) } +inst_bts_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 402) } +inst_bts_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 403) } +inst_bts_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 403) } +inst_bts_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 404) } +inst_bts_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 404) } +inst_bts_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 405) } +inst_bts_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 405) } +inst_bts_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 406) } +inst_bts_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 406) } emit_bts_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_bts_r16_r16(dst, src)) } emit_bts_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_bts_m16_r16(dst, src)) } emit_bts_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_bts_r32_r32(dst, src)) } @@ -1113,18 +1145,18 @@ emit_bts_r32_imm8 :: #force_inline proc(instructions: ^[dynami emit_bts_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, imm: i8) { append(instructions, inst_bts_m32_imm8(dst, imm)) } emit_bts_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_bts_r64_imm8(dst, imm)) } emit_bts_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_bts_m64_imm8(dst, imm)) } -inst_btr_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 395) } -inst_btr_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 395) } -inst_btr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 396) } -inst_btr_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 396) } -inst_btr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 397) } -inst_btr_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 397) } -inst_btr_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 398) } -inst_btr_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 398) } -inst_btr_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 399) } -inst_btr_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 399) } -inst_btr_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 400) } -inst_btr_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 400) } +inst_btr_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 407) } +inst_btr_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 407) } +inst_btr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 408) } +inst_btr_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 408) } +inst_btr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 409) } +inst_btr_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 409) } +inst_btr_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 410) } +inst_btr_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 410) } +inst_btr_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 411) } +inst_btr_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 411) } +inst_btr_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 412) } +inst_btr_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 412) } emit_btr_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_btr_r16_r16(dst, src)) } emit_btr_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_btr_m16_r16(dst, src)) } emit_btr_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_btr_r32_r32(dst, src)) } @@ -1137,18 +1169,18 @@ emit_btr_r32_imm8 :: #force_inline proc(instructions: ^[dynami emit_btr_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, imm: i8) { append(instructions, inst_btr_m32_imm8(dst, imm)) } emit_btr_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_btr_r64_imm8(dst, imm)) } emit_btr_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_btr_m64_imm8(dst, imm)) } -inst_btc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 401) } -inst_btc_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 401) } -inst_btc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 402) } -inst_btc_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 402) } -inst_btc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 403) } -inst_btc_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 403) } -inst_btc_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 404) } -inst_btc_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 404) } -inst_btc_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 405) } -inst_btc_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 405) } -inst_btc_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 406) } -inst_btc_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 406) } +inst_btc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 413) } +inst_btc_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 413) } +inst_btc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 414) } +inst_btc_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 414) } +inst_btc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 415) } +inst_btc_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 415) } +inst_btc_r16_imm8 :: #force_inline proc "contextless" (dst: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr16(dst), op_imm8(imm), {}, {}} }, 416) } +inst_btc_m16_imm8 :: #force_inline proc "contextless" (dst: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 2), op_imm8(imm), {}, {}} }, 416) } +inst_btc_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr32(dst), op_imm8(imm), {}, {}} }, 417) } +inst_btc_m32_imm8 :: #force_inline proc "contextless" (dst: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 4), op_imm8(imm), {}, {}} }, 417) } +inst_btc_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_gpr64(dst), op_imm8(imm), {}, {}} }, 418) } +inst_btc_m64_imm8 :: #force_inline proc "contextless" (dst: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BTC, operand_count = 2, ops = {op_mem(dst.mem, 8), op_imm8(imm), {}, {}} }, 418) } emit_btc_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_btc_r16_r16(dst, src)) } emit_btc_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_btc_m16_r16(dst, src)) } emit_btc_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_btc_r32_r32(dst, src)) } @@ -1161,60 +1193,60 @@ emit_btc_r32_imm8 :: #force_inline proc(instructions: ^[dynami emit_btc_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, imm: i8) { append(instructions, inst_btc_m32_imm8(dst, imm)) } emit_btc_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, imm: i8) { append(instructions, inst_btc_r64_imm8(dst, imm)) } emit_btc_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, imm: i8) { append(instructions, inst_btc_m64_imm8(dst, imm)) } -inst_bsf_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 407) } -inst_bsf_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 407) } -inst_bsf_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 408) } -inst_bsf_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 408) } -inst_bsf_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 409) } -inst_bsf_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 409) } +inst_bsf_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 419) } +inst_bsf_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 419) } +inst_bsf_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 420) } +inst_bsf_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 420) } +inst_bsf_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 421) } +inst_bsf_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSF, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 421) } emit_bsf_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_bsf_r16_r16(dst, src)) } emit_bsf_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_bsf_r16_m16(dst, src)) } emit_bsf_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_bsf_r32_r32(dst, src)) } emit_bsf_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_bsf_r32_m32(dst, src)) } emit_bsf_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_bsf_r64_r64(dst, src)) } emit_bsf_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_bsf_r64_m64(dst, src)) } -inst_bsr_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 410) } -inst_bsr_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 410) } -inst_bsr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 411) } -inst_bsr_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 411) } -inst_bsr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 412) } -inst_bsr_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 412) } +inst_bsr_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 422) } +inst_bsr_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 422) } +inst_bsr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 423) } +inst_bsr_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 423) } +inst_bsr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 424) } +inst_bsr_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 424) } emit_bsr_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_bsr_r16_r16(dst, src)) } emit_bsr_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_bsr_r16_m16(dst, src)) } emit_bsr_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_bsr_r32_r32(dst, src)) } emit_bsr_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_bsr_r32_m32(dst, src)) } emit_bsr_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_bsr_r64_r64(dst, src)) } emit_bsr_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_bsr_r64_m64(dst, src)) } -inst_popcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 413) } -inst_popcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 413) } -inst_popcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 414) } -inst_popcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 414) } -inst_popcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 415) } -inst_popcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 415) } +inst_popcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 425) } +inst_popcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 425) } +inst_popcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 426) } +inst_popcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 426) } +inst_popcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 427) } +inst_popcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .POPCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 427) } emit_popcnt_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_popcnt_r16_r16(dst, src)) } emit_popcnt_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_popcnt_r16_m16(dst, src)) } emit_popcnt_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_popcnt_r32_r32(dst, src)) } emit_popcnt_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_popcnt_r32_m32(dst, src)) } emit_popcnt_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_popcnt_r64_r64(dst, src)) } emit_popcnt_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_popcnt_r64_m64(dst, src)) } -inst_lzcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 416) } -inst_lzcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 416) } -inst_lzcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 417) } -inst_lzcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 417) } -inst_lzcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 418) } -inst_lzcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 418) } +inst_lzcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 428) } +inst_lzcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 428) } +inst_lzcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 429) } +inst_lzcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 429) } +inst_lzcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 430) } +inst_lzcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LZCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 430) } emit_lzcnt_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_lzcnt_r16_r16(dst, src)) } emit_lzcnt_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_lzcnt_r16_m16(dst, src)) } emit_lzcnt_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_lzcnt_r32_r32(dst, src)) } emit_lzcnt_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_lzcnt_r32_m32(dst, src)) } emit_lzcnt_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_lzcnt_r64_r64(dst, src)) } emit_lzcnt_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_lzcnt_r64_m64(dst, src)) } -inst_tzcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 419) } -inst_tzcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 419) } -inst_tzcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 420) } -inst_tzcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 420) } -inst_tzcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 421) } -inst_tzcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 421) } +inst_tzcnt_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 431) } +inst_tzcnt_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 431) } +inst_tzcnt_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 432) } +inst_tzcnt_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 432) } +inst_tzcnt_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 433) } +inst_tzcnt_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .TZCNT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 433) } emit_tzcnt_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_tzcnt_r16_r16(dst, src)) } emit_tzcnt_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_tzcnt_r16_m16(dst, src)) } emit_tzcnt_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_tzcnt_r32_r32(dst, src)) } @@ -1223,9 +1255,9 @@ emit_tzcnt_r64_r64 :: #force_inline proc(instructions: ^[dynami emit_tzcnt_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_tzcnt_r64_m64(dst, src)) } inst_jmp_rel8 :: #force_inline proc "contextless" (offset: i8) -> Instruction { return Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_rel8(offset), {}, {}, {}} } } inst_jmp_rel32 :: #force_inline proc "contextless" (offset: i32) -> Instruction { return Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_rel32(offset), {}, {}, {}} } } -inst_jmp_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 424) } -inst_jmp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 424) } -inst_jmp_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 425) } +inst_jmp_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 436) } +inst_jmp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 436) } +inst_jmp_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .JMP, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 437) } emit_jmp_rel8 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i8) { append(instructions, inst_jmp_rel8(offset)) } emit_jmp_rel32 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i32) { append(instructions, inst_jmp_rel32(offset)) } emit_jmp_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_jmp_r64(dst)) } @@ -1364,614 +1396,614 @@ emit_loope_rel8 :: #force_inline proc(instructions: ^[dynami inst_loopne_rel8 :: #force_inline proc "contextless" (offset: i8) -> Instruction { return Instruction{ mnemonic = .LOOPNE, operand_count = 1, ops = {op_rel8(offset), {}, {}, {}} } } emit_loopne_rel8 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i8) { append(instructions, inst_loopne_rel8(offset)) } inst_call_rel32 :: #force_inline proc "contextless" (offset: i32) -> Instruction { return Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_rel32(offset), {}, {}, {}} } } -inst_call_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 495) } -inst_call_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 495) } -inst_call_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 496) } +inst_call_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 507) } +inst_call_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 507) } +inst_call_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .CALL, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 508) } emit_call_rel32 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i32) { append(instructions, inst_call_rel32(offset)) } emit_call_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_call_r64(dst)) } emit_call_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_call_m64(dst)) } emit_call_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_call_m(dst)) } -inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RET, operand_count = 0, ops = {{}, {}, {}, {}} }, 499) } -inst_ret_imm16 :: #force_inline proc "contextless" (imm: i16) -> Instruction { return with_hint(Instruction{ mnemonic = .RET, operand_count = 1, ops = {op_imm16(imm), {}, {}, {}} }, 500) } +inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RET, operand_count = 0, ops = {{}, {}, {}, {}} }, 511) } +inst_ret_imm16 :: #force_inline proc "contextless" (imm: i16) -> Instruction { return with_hint(Instruction{ mnemonic = .RET, operand_count = 1, ops = {op_imm16(imm), {}, {}, {}} }, 512) } emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } emit_ret_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i16) { append(instructions, inst_ret_imm16(imm)) } -inst_iret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRET, operand_count = 0, ops = {{}, {}, {}, {}} }, 501) } +inst_iret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRET, operand_count = 0, ops = {{}, {}, {}, {}} }, 513) } emit_iret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_iret_none()) } -inst_iretd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRETD, operand_count = 0, ops = {{}, {}, {}, {}} }, 502) } +inst_iretd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRETD, operand_count = 0, ops = {{}, {}, {}, {}} }, 514) } emit_iretd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_iretd_none()) } -inst_iretq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRETQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 503) } +inst_iretq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .IRETQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 515) } emit_iretq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_iretq_none()) } -inst_int_imm8 :: #force_inline proc "contextless" (imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INT, operand_count = 1, ops = {op_imm8(imm), {}, {}, {}} }, 504) } +inst_int_imm8 :: #force_inline proc "contextless" (imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INT, operand_count = 1, ops = {op_imm8(imm), {}, {}, {}} }, 516) } emit_int_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i8) { append(instructions, inst_int_imm8(imm)) } -inst_int3_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INT3, operand_count = 0, ops = {{}, {}, {}, {}} }, 505) } +inst_int3_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INT3, operand_count = 0, ops = {{}, {}, {}, {}} }, 517) } emit_int3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_int3_none()) } -inst_into_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INTO, operand_count = 0, ops = {{}, {}, {}, {}} }, 506) } +inst_into_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INTO, operand_count = 0, ops = {{}, {}, {}, {}} }, 518) } emit_into_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_into_none()) } -inst_syscall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 507) } +inst_syscall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 519) } emit_syscall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_syscall_none()) } -inst_sysret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSRET, operand_count = 0, ops = {{}, {}, {}, {}} }, 508) } +inst_sysret_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSRET, operand_count = 0, ops = {{}, {}, {}, {}} }, 520) } emit_sysret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sysret_none()) } -inst_sysenter_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSENTER, operand_count = 0, ops = {{}, {}, {}, {}} }, 509) } +inst_sysenter_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSENTER, operand_count = 0, ops = {{}, {}, {}, {}} }, 521) } emit_sysenter_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sysenter_none()) } -inst_sysexit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSEXIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 510) } +inst_sysexit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SYSEXIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 522) } emit_sysexit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sysexit_none()) } -inst_seta_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETA, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 511) } -inst_seta_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 511) } +inst_seta_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETA, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 523) } +inst_seta_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 523) } emit_seta_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_seta_r8(dst)) } emit_seta_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_seta_m8(dst)) } -inst_setae_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETAE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 512) } -inst_setae_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETAE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 512) } +inst_setae_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETAE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 524) } +inst_setae_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETAE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 524) } emit_setae_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setae_r8(dst)) } emit_setae_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setae_m8(dst)) } -inst_setb_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETB, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 513) } -inst_setb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 513) } +inst_setb_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETB, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 525) } +inst_setb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 525) } emit_setb_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setb_r8(dst)) } emit_setb_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setb_m8(dst)) } -inst_setbe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETBE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 514) } -inst_setbe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETBE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 514) } +inst_setbe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETBE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 526) } +inst_setbe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETBE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 526) } emit_setbe_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setbe_r8(dst)) } emit_setbe_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setbe_m8(dst)) } -inst_setc_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETC, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 515) } -inst_setc_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 515) } +inst_setc_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETC, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 527) } +inst_setc_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 527) } emit_setc_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setc_r8(dst)) } emit_setc_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setc_m8(dst)) } -inst_sete_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 516) } -inst_sete_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 516) } +inst_sete_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 528) } +inst_sete_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 528) } emit_sete_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_sete_r8(dst)) } emit_sete_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_sete_m8(dst)) } -inst_setg_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETG, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 517) } -inst_setg_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 517) } +inst_setg_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETG, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 529) } +inst_setg_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 529) } emit_setg_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setg_r8(dst)) } emit_setg_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setg_m8(dst)) } -inst_setge_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETGE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 518) } -inst_setge_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETGE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 518) } +inst_setge_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETGE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 530) } +inst_setge_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETGE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 530) } emit_setge_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setge_r8(dst)) } emit_setge_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setge_m8(dst)) } -inst_setl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 519) } -inst_setl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 519) } +inst_setl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 531) } +inst_setl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 531) } emit_setl_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setl_r8(dst)) } emit_setl_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setl_m8(dst)) } -inst_setle_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETLE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 520) } -inst_setle_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETLE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 520) } +inst_setle_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETLE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 532) } +inst_setle_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETLE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 532) } emit_setle_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setle_r8(dst)) } emit_setle_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setle_m8(dst)) } -inst_setna_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNA, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 521) } -inst_setna_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 521) } +inst_setna_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNA, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 533) } +inst_setna_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 533) } emit_setna_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setna_r8(dst)) } emit_setna_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setna_m8(dst)) } -inst_setnae_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNAE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 522) } -inst_setnae_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNAE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 522) } +inst_setnae_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNAE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 534) } +inst_setnae_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNAE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 534) } emit_setnae_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnae_r8(dst)) } emit_setnae_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnae_m8(dst)) } -inst_setnb_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNB, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 523) } -inst_setnb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 523) } +inst_setnb_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNB, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 535) } +inst_setnb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 535) } emit_setnb_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnb_r8(dst)) } emit_setnb_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnb_m8(dst)) } -inst_setnbe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNBE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 524) } -inst_setnbe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNBE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 524) } +inst_setnbe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNBE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 536) } +inst_setnbe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNBE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 536) } emit_setnbe_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnbe_r8(dst)) } emit_setnbe_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnbe_m8(dst)) } -inst_setnc_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNC, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 525) } -inst_setnc_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 525) } +inst_setnc_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNC, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 537) } +inst_setnc_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 537) } emit_setnc_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnc_r8(dst)) } emit_setnc_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnc_m8(dst)) } -inst_setne_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 526) } -inst_setne_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 526) } +inst_setne_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 538) } +inst_setne_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 538) } emit_setne_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setne_r8(dst)) } emit_setne_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setne_m8(dst)) } -inst_setng_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNG, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 527) } -inst_setng_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 527) } +inst_setng_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNG, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 539) } +inst_setng_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 539) } emit_setng_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setng_r8(dst)) } emit_setng_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setng_m8(dst)) } -inst_setnge_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNGE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 528) } -inst_setnge_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNGE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 528) } +inst_setnge_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNGE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 540) } +inst_setnge_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNGE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 540) } emit_setnge_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnge_r8(dst)) } emit_setnge_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnge_m8(dst)) } -inst_setnl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 529) } -inst_setnl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 529) } +inst_setnl_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNL, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 541) } +inst_setnl_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNL, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 541) } emit_setnl_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnl_r8(dst)) } emit_setnl_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnl_m8(dst)) } -inst_setnle_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNLE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 530) } -inst_setnle_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNLE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 530) } +inst_setnle_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNLE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 542) } +inst_setnle_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNLE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 542) } emit_setnle_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnle_r8(dst)) } emit_setnle_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnle_m8(dst)) } -inst_setno_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 531) } -inst_setno_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 531) } +inst_setno_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 543) } +inst_setno_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 543) } emit_setno_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setno_r8(dst)) } emit_setno_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setno_m8(dst)) } -inst_setnp_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNP, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 532) } -inst_setnp_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNP, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 532) } +inst_setnp_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNP, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 544) } +inst_setnp_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNP, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 544) } emit_setnp_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnp_r8(dst)) } emit_setnp_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnp_m8(dst)) } -inst_setns_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNS, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 533) } -inst_setns_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 533) } +inst_setns_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNS, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 545) } +inst_setns_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 545) } emit_setns_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setns_r8(dst)) } emit_setns_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setns_m8(dst)) } -inst_setnz_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNZ, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 534) } -inst_setnz_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNZ, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 534) } +inst_setnz_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNZ, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 546) } +inst_setnz_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETNZ, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 546) } emit_setnz_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setnz_r8(dst)) } emit_setnz_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setnz_m8(dst)) } -inst_seto_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 535) } -inst_seto_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 535) } +inst_seto_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 547) } +inst_seto_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 547) } emit_seto_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_seto_r8(dst)) } emit_seto_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_seto_m8(dst)) } -inst_setp_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETP, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 536) } -inst_setp_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETP, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 536) } +inst_setp_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETP, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 548) } +inst_setp_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETP, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 548) } emit_setp_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setp_r8(dst)) } emit_setp_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setp_m8(dst)) } -inst_setpe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 537) } -inst_setpe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 537) } +inst_setpe_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPE, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 549) } +inst_setpe_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 549) } emit_setpe_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setpe_r8(dst)) } emit_setpe_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setpe_m8(dst)) } -inst_setpo_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 538) } -inst_setpo_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 538) } +inst_setpo_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPO, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 550) } +inst_setpo_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETPO, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 550) } emit_setpo_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setpo_r8(dst)) } emit_setpo_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setpo_m8(dst)) } -inst_sets_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETS, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 539) } -inst_sets_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 539) } +inst_sets_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETS, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 551) } +inst_sets_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 551) } emit_sets_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_sets_r8(dst)) } emit_sets_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_sets_m8(dst)) } -inst_setz_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETZ, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 540) } -inst_setz_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETZ, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 540) } +inst_setz_r8 :: #force_inline proc "contextless" (dst: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETZ, operand_count = 1, ops = {op_gpr8(dst), {}, {}, {}} }, 552) } +inst_setz_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .SETZ, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 552) } emit_setz_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8) { append(instructions, inst_setz_r8(dst)) } emit_setz_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_setz_m8(dst)) } -inst_cmova_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 541) } -inst_cmova_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 541) } -inst_cmova_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 542) } -inst_cmova_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 542) } -inst_cmova_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 543) } -inst_cmova_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 543) } +inst_cmova_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 553) } +inst_cmova_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 553) } +inst_cmova_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 554) } +inst_cmova_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 554) } +inst_cmova_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 555) } +inst_cmova_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVA, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 555) } emit_cmova_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmova_r16_r16(dst, src)) } emit_cmova_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmova_r16_m16(dst, src)) } emit_cmova_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmova_r32_r32(dst, src)) } emit_cmova_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmova_r32_m32(dst, src)) } emit_cmova_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmova_r64_r64(dst, src)) } emit_cmova_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmova_r64_m64(dst, src)) } -inst_cmovae_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 544) } -inst_cmovae_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 544) } -inst_cmovae_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 545) } -inst_cmovae_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 545) } -inst_cmovae_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 546) } -inst_cmovae_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 546) } +inst_cmovae_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 556) } +inst_cmovae_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 556) } +inst_cmovae_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 557) } +inst_cmovae_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 557) } +inst_cmovae_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 558) } +inst_cmovae_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVAE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 558) } emit_cmovae_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovae_r16_r16(dst, src)) } emit_cmovae_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovae_r16_m16(dst, src)) } emit_cmovae_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovae_r32_r32(dst, src)) } emit_cmovae_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovae_r32_m32(dst, src)) } emit_cmovae_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovae_r64_r64(dst, src)) } emit_cmovae_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovae_r64_m64(dst, src)) } -inst_cmovb_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 547) } -inst_cmovb_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 547) } -inst_cmovb_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 548) } -inst_cmovb_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 548) } -inst_cmovb_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 549) } -inst_cmovb_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 549) } +inst_cmovb_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 559) } +inst_cmovb_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 559) } +inst_cmovb_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 560) } +inst_cmovb_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 560) } +inst_cmovb_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 561) } +inst_cmovb_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVB, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 561) } emit_cmovb_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovb_r16_r16(dst, src)) } emit_cmovb_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovb_r16_m16(dst, src)) } emit_cmovb_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovb_r32_r32(dst, src)) } emit_cmovb_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovb_r32_m32(dst, src)) } emit_cmovb_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovb_r64_r64(dst, src)) } emit_cmovb_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovb_r64_m64(dst, src)) } -inst_cmovbe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 550) } -inst_cmovbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 550) } -inst_cmovbe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 551) } -inst_cmovbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 551) } -inst_cmovbe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 552) } -inst_cmovbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 552) } +inst_cmovbe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 562) } +inst_cmovbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 562) } +inst_cmovbe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 563) } +inst_cmovbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 563) } +inst_cmovbe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 564) } +inst_cmovbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 564) } emit_cmovbe_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovbe_r16_r16(dst, src)) } emit_cmovbe_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovbe_r16_m16(dst, src)) } emit_cmovbe_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovbe_r32_r32(dst, src)) } emit_cmovbe_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovbe_r32_m32(dst, src)) } emit_cmovbe_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovbe_r64_r64(dst, src)) } emit_cmovbe_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovbe_r64_m64(dst, src)) } -inst_cmovc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 553) } -inst_cmovc_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 553) } -inst_cmovc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 554) } -inst_cmovc_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 554) } -inst_cmovc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 555) } -inst_cmovc_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 555) } +inst_cmovc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 565) } +inst_cmovc_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 565) } +inst_cmovc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 566) } +inst_cmovc_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 566) } +inst_cmovc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 567) } +inst_cmovc_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVC, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 567) } emit_cmovc_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovc_r16_r16(dst, src)) } emit_cmovc_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovc_r16_m16(dst, src)) } emit_cmovc_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovc_r32_r32(dst, src)) } emit_cmovc_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovc_r32_m32(dst, src)) } emit_cmovc_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovc_r64_r64(dst, src)) } emit_cmovc_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovc_r64_m64(dst, src)) } -inst_cmove_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 556) } -inst_cmove_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 556) } -inst_cmove_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 557) } -inst_cmove_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 557) } -inst_cmove_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 558) } -inst_cmove_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 558) } +inst_cmove_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 568) } +inst_cmove_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 568) } +inst_cmove_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 569) } +inst_cmove_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 569) } +inst_cmove_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 570) } +inst_cmove_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 570) } emit_cmove_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmove_r16_r16(dst, src)) } emit_cmove_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmove_r16_m16(dst, src)) } emit_cmove_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmove_r32_r32(dst, src)) } emit_cmove_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmove_r32_m32(dst, src)) } emit_cmove_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmove_r64_r64(dst, src)) } emit_cmove_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmove_r64_m64(dst, src)) } -inst_cmovg_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 559) } -inst_cmovg_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 559) } -inst_cmovg_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 560) } -inst_cmovg_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 560) } -inst_cmovg_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 561) } -inst_cmovg_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 561) } +inst_cmovg_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 571) } +inst_cmovg_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 571) } +inst_cmovg_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 572) } +inst_cmovg_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 572) } +inst_cmovg_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 573) } +inst_cmovg_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVG, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 573) } emit_cmovg_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovg_r16_r16(dst, src)) } emit_cmovg_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovg_r16_m16(dst, src)) } emit_cmovg_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovg_r32_r32(dst, src)) } emit_cmovg_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovg_r32_m32(dst, src)) } emit_cmovg_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovg_r64_r64(dst, src)) } emit_cmovg_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovg_r64_m64(dst, src)) } -inst_cmovge_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 562) } -inst_cmovge_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 562) } -inst_cmovge_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 563) } -inst_cmovge_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 563) } -inst_cmovge_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 564) } -inst_cmovge_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 564) } +inst_cmovge_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 574) } +inst_cmovge_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 574) } +inst_cmovge_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 575) } +inst_cmovge_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 575) } +inst_cmovge_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 576) } +inst_cmovge_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVGE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 576) } emit_cmovge_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovge_r16_r16(dst, src)) } emit_cmovge_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovge_r16_m16(dst, src)) } emit_cmovge_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovge_r32_r32(dst, src)) } emit_cmovge_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovge_r32_m32(dst, src)) } emit_cmovge_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovge_r64_r64(dst, src)) } emit_cmovge_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovge_r64_m64(dst, src)) } -inst_cmovl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 565) } -inst_cmovl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 565) } -inst_cmovl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 566) } -inst_cmovl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 566) } -inst_cmovl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 567) } -inst_cmovl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 567) } +inst_cmovl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 577) } +inst_cmovl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 577) } +inst_cmovl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 578) } +inst_cmovl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 578) } +inst_cmovl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 579) } +inst_cmovl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 579) } emit_cmovl_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovl_r16_r16(dst, src)) } emit_cmovl_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovl_r16_m16(dst, src)) } emit_cmovl_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovl_r32_r32(dst, src)) } emit_cmovl_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovl_r32_m32(dst, src)) } emit_cmovl_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovl_r64_r64(dst, src)) } emit_cmovl_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovl_r64_m64(dst, src)) } -inst_cmovle_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 568) } -inst_cmovle_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 568) } -inst_cmovle_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 569) } -inst_cmovle_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 569) } -inst_cmovle_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 570) } -inst_cmovle_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 570) } +inst_cmovle_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 580) } +inst_cmovle_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 580) } +inst_cmovle_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 581) } +inst_cmovle_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 581) } +inst_cmovle_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 582) } +inst_cmovle_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVLE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 582) } emit_cmovle_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovle_r16_r16(dst, src)) } emit_cmovle_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovle_r16_m16(dst, src)) } emit_cmovle_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovle_r32_r32(dst, src)) } emit_cmovle_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovle_r32_m32(dst, src)) } emit_cmovle_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovle_r64_r64(dst, src)) } emit_cmovle_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovle_r64_m64(dst, src)) } -inst_cmovna_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 571) } -inst_cmovna_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 571) } -inst_cmovna_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 572) } -inst_cmovna_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 572) } -inst_cmovna_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 573) } -inst_cmovna_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 573) } +inst_cmovna_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 583) } +inst_cmovna_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 583) } +inst_cmovna_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 584) } +inst_cmovna_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 584) } +inst_cmovna_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 585) } +inst_cmovna_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNA, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 585) } emit_cmovna_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovna_r16_r16(dst, src)) } emit_cmovna_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovna_r16_m16(dst, src)) } emit_cmovna_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovna_r32_r32(dst, src)) } emit_cmovna_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovna_r32_m32(dst, src)) } emit_cmovna_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovna_r64_r64(dst, src)) } emit_cmovna_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovna_r64_m64(dst, src)) } -inst_cmovnae_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 574) } -inst_cmovnae_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 574) } -inst_cmovnae_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 575) } -inst_cmovnae_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 575) } -inst_cmovnae_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 576) } -inst_cmovnae_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 576) } +inst_cmovnae_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 586) } +inst_cmovnae_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 586) } +inst_cmovnae_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 587) } +inst_cmovnae_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 587) } +inst_cmovnae_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 588) } +inst_cmovnae_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNAE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 588) } emit_cmovnae_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnae_r16_r16(dst, src)) } emit_cmovnae_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnae_r16_m16(dst, src)) } emit_cmovnae_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnae_r32_r32(dst, src)) } emit_cmovnae_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnae_r32_m32(dst, src)) } emit_cmovnae_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnae_r64_r64(dst, src)) } emit_cmovnae_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnae_r64_m64(dst, src)) } -inst_cmovnb_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 577) } -inst_cmovnb_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 577) } -inst_cmovnb_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 578) } -inst_cmovnb_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 578) } -inst_cmovnb_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 579) } -inst_cmovnb_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 579) } +inst_cmovnb_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 589) } +inst_cmovnb_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 589) } +inst_cmovnb_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 590) } +inst_cmovnb_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 590) } +inst_cmovnb_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 591) } +inst_cmovnb_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNB, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 591) } emit_cmovnb_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnb_r16_r16(dst, src)) } emit_cmovnb_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnb_r16_m16(dst, src)) } emit_cmovnb_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnb_r32_r32(dst, src)) } emit_cmovnb_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnb_r32_m32(dst, src)) } emit_cmovnb_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnb_r64_r64(dst, src)) } emit_cmovnb_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnb_r64_m64(dst, src)) } -inst_cmovnbe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 580) } -inst_cmovnbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 580) } -inst_cmovnbe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 581) } -inst_cmovnbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 581) } -inst_cmovnbe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 582) } -inst_cmovnbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 582) } +inst_cmovnbe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 592) } +inst_cmovnbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 592) } +inst_cmovnbe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 593) } +inst_cmovnbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 593) } +inst_cmovnbe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 594) } +inst_cmovnbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 594) } emit_cmovnbe_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnbe_r16_r16(dst, src)) } emit_cmovnbe_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnbe_r16_m16(dst, src)) } emit_cmovnbe_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnbe_r32_r32(dst, src)) } emit_cmovnbe_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnbe_r32_m32(dst, src)) } emit_cmovnbe_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnbe_r64_r64(dst, src)) } emit_cmovnbe_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnbe_r64_m64(dst, src)) } -inst_cmovnc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 583) } -inst_cmovnc_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 583) } -inst_cmovnc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 584) } -inst_cmovnc_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 584) } -inst_cmovnc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 585) } -inst_cmovnc_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 585) } +inst_cmovnc_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 595) } +inst_cmovnc_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 595) } +inst_cmovnc_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 596) } +inst_cmovnc_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 596) } +inst_cmovnc_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 597) } +inst_cmovnc_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNC, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 597) } emit_cmovnc_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnc_r16_r16(dst, src)) } emit_cmovnc_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnc_r16_m16(dst, src)) } emit_cmovnc_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnc_r32_r32(dst, src)) } emit_cmovnc_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnc_r32_m32(dst, src)) } emit_cmovnc_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnc_r64_r64(dst, src)) } emit_cmovnc_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnc_r64_m64(dst, src)) } -inst_cmovne_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 586) } -inst_cmovne_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 586) } -inst_cmovne_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 587) } -inst_cmovne_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 587) } -inst_cmovne_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 588) } -inst_cmovne_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 588) } +inst_cmovne_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 598) } +inst_cmovne_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 598) } +inst_cmovne_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 599) } +inst_cmovne_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 599) } +inst_cmovne_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 600) } +inst_cmovne_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 600) } emit_cmovne_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovne_r16_r16(dst, src)) } emit_cmovne_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovne_r16_m16(dst, src)) } emit_cmovne_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovne_r32_r32(dst, src)) } emit_cmovne_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovne_r32_m32(dst, src)) } emit_cmovne_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovne_r64_r64(dst, src)) } emit_cmovne_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovne_r64_m64(dst, src)) } -inst_cmovng_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 589) } -inst_cmovng_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 589) } -inst_cmovng_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 590) } -inst_cmovng_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 590) } -inst_cmovng_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 591) } -inst_cmovng_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 591) } +inst_cmovng_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 601) } +inst_cmovng_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 601) } +inst_cmovng_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 602) } +inst_cmovng_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 602) } +inst_cmovng_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 603) } +inst_cmovng_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNG, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 603) } emit_cmovng_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovng_r16_r16(dst, src)) } emit_cmovng_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovng_r16_m16(dst, src)) } emit_cmovng_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovng_r32_r32(dst, src)) } emit_cmovng_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovng_r32_m32(dst, src)) } emit_cmovng_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovng_r64_r64(dst, src)) } emit_cmovng_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovng_r64_m64(dst, src)) } -inst_cmovnge_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 592) } -inst_cmovnge_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 592) } -inst_cmovnge_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 593) } -inst_cmovnge_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 593) } -inst_cmovnge_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 594) } -inst_cmovnge_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 594) } +inst_cmovnge_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 604) } +inst_cmovnge_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 604) } +inst_cmovnge_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 605) } +inst_cmovnge_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 605) } +inst_cmovnge_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 606) } +inst_cmovnge_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNGE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 606) } emit_cmovnge_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnge_r16_r16(dst, src)) } emit_cmovnge_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnge_r16_m16(dst, src)) } emit_cmovnge_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnge_r32_r32(dst, src)) } emit_cmovnge_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnge_r32_m32(dst, src)) } emit_cmovnge_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnge_r64_r64(dst, src)) } emit_cmovnge_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnge_r64_m64(dst, src)) } -inst_cmovnl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 595) } -inst_cmovnl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 595) } -inst_cmovnl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 596) } -inst_cmovnl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 596) } -inst_cmovnl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 597) } -inst_cmovnl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 597) } +inst_cmovnl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 607) } +inst_cmovnl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 607) } +inst_cmovnl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 608) } +inst_cmovnl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 608) } +inst_cmovnl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 609) } +inst_cmovnl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 609) } emit_cmovnl_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnl_r16_r16(dst, src)) } emit_cmovnl_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnl_r16_m16(dst, src)) } emit_cmovnl_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnl_r32_r32(dst, src)) } emit_cmovnl_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnl_r32_m32(dst, src)) } emit_cmovnl_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnl_r64_r64(dst, src)) } emit_cmovnl_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnl_r64_m64(dst, src)) } -inst_cmovnle_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 598) } -inst_cmovnle_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 598) } -inst_cmovnle_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 599) } -inst_cmovnle_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 599) } -inst_cmovnle_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 600) } -inst_cmovnle_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 600) } +inst_cmovnle_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 610) } +inst_cmovnle_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 610) } +inst_cmovnle_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 611) } +inst_cmovnle_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 611) } +inst_cmovnle_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 612) } +inst_cmovnle_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNLE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 612) } emit_cmovnle_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnle_r16_r16(dst, src)) } emit_cmovnle_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnle_r16_m16(dst, src)) } emit_cmovnle_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnle_r32_r32(dst, src)) } emit_cmovnle_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnle_r32_m32(dst, src)) } emit_cmovnle_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnle_r64_r64(dst, src)) } emit_cmovnle_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnle_r64_m64(dst, src)) } -inst_cmovno_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 601) } -inst_cmovno_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 601) } -inst_cmovno_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 602) } -inst_cmovno_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 602) } -inst_cmovno_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 603) } -inst_cmovno_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 603) } +inst_cmovno_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 613) } +inst_cmovno_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 613) } +inst_cmovno_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 614) } +inst_cmovno_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 614) } +inst_cmovno_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 615) } +inst_cmovno_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 615) } emit_cmovno_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovno_r16_r16(dst, src)) } emit_cmovno_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovno_r16_m16(dst, src)) } emit_cmovno_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovno_r32_r32(dst, src)) } emit_cmovno_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovno_r32_m32(dst, src)) } emit_cmovno_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovno_r64_r64(dst, src)) } emit_cmovno_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovno_r64_m64(dst, src)) } -inst_cmovnp_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 604) } -inst_cmovnp_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 604) } -inst_cmovnp_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 605) } -inst_cmovnp_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 605) } -inst_cmovnp_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 606) } -inst_cmovnp_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 606) } +inst_cmovnp_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 616) } +inst_cmovnp_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 616) } +inst_cmovnp_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 617) } +inst_cmovnp_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 617) } +inst_cmovnp_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 618) } +inst_cmovnp_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNP, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 618) } emit_cmovnp_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnp_r16_r16(dst, src)) } emit_cmovnp_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnp_r16_m16(dst, src)) } emit_cmovnp_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnp_r32_r32(dst, src)) } emit_cmovnp_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnp_r32_m32(dst, src)) } emit_cmovnp_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnp_r64_r64(dst, src)) } emit_cmovnp_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnp_r64_m64(dst, src)) } -inst_cmovns_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 607) } -inst_cmovns_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 607) } -inst_cmovns_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 608) } -inst_cmovns_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 608) } -inst_cmovns_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 609) } -inst_cmovns_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 609) } +inst_cmovns_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 619) } +inst_cmovns_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 619) } +inst_cmovns_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 620) } +inst_cmovns_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 620) } +inst_cmovns_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 621) } +inst_cmovns_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 621) } emit_cmovns_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovns_r16_r16(dst, src)) } emit_cmovns_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovns_r16_m16(dst, src)) } emit_cmovns_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovns_r32_r32(dst, src)) } emit_cmovns_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovns_r32_m32(dst, src)) } emit_cmovns_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovns_r64_r64(dst, src)) } emit_cmovns_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovns_r64_m64(dst, src)) } -inst_cmovnz_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 610) } -inst_cmovnz_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 610) } -inst_cmovnz_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 611) } -inst_cmovnz_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 611) } -inst_cmovnz_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 612) } -inst_cmovnz_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 612) } +inst_cmovnz_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 622) } +inst_cmovnz_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 622) } +inst_cmovnz_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 623) } +inst_cmovnz_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 623) } +inst_cmovnz_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 624) } +inst_cmovnz_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVNZ, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 624) } emit_cmovnz_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovnz_r16_r16(dst, src)) } emit_cmovnz_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovnz_r16_m16(dst, src)) } emit_cmovnz_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovnz_r32_r32(dst, src)) } emit_cmovnz_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovnz_r32_m32(dst, src)) } emit_cmovnz_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovnz_r64_r64(dst, src)) } emit_cmovnz_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovnz_r64_m64(dst, src)) } -inst_cmovo_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 613) } -inst_cmovo_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 613) } -inst_cmovo_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 614) } -inst_cmovo_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 614) } -inst_cmovo_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 615) } -inst_cmovo_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 615) } +inst_cmovo_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 625) } +inst_cmovo_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 625) } +inst_cmovo_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 626) } +inst_cmovo_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 626) } +inst_cmovo_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 627) } +inst_cmovo_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 627) } emit_cmovo_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovo_r16_r16(dst, src)) } emit_cmovo_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovo_r16_m16(dst, src)) } emit_cmovo_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovo_r32_r32(dst, src)) } emit_cmovo_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovo_r32_m32(dst, src)) } emit_cmovo_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovo_r64_r64(dst, src)) } emit_cmovo_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovo_r64_m64(dst, src)) } -inst_cmovp_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 616) } -inst_cmovp_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 616) } -inst_cmovp_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 617) } -inst_cmovp_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 617) } -inst_cmovp_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 618) } -inst_cmovp_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 618) } +inst_cmovp_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 628) } +inst_cmovp_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 628) } +inst_cmovp_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 629) } +inst_cmovp_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 629) } +inst_cmovp_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 630) } +inst_cmovp_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVP, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 630) } emit_cmovp_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovp_r16_r16(dst, src)) } emit_cmovp_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovp_r16_m16(dst, src)) } emit_cmovp_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovp_r32_r32(dst, src)) } emit_cmovp_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovp_r32_m32(dst, src)) } emit_cmovp_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovp_r64_r64(dst, src)) } emit_cmovp_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovp_r64_m64(dst, src)) } -inst_cmovpe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 619) } -inst_cmovpe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 619) } -inst_cmovpe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 620) } -inst_cmovpe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 620) } -inst_cmovpe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 621) } -inst_cmovpe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 621) } +inst_cmovpe_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 631) } +inst_cmovpe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 631) } +inst_cmovpe_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 632) } +inst_cmovpe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 632) } +inst_cmovpe_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 633) } +inst_cmovpe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 633) } emit_cmovpe_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovpe_r16_r16(dst, src)) } emit_cmovpe_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovpe_r16_m16(dst, src)) } emit_cmovpe_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovpe_r32_r32(dst, src)) } emit_cmovpe_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovpe_r32_m32(dst, src)) } emit_cmovpe_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovpe_r64_r64(dst, src)) } emit_cmovpe_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovpe_r64_m64(dst, src)) } -inst_cmovpo_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 622) } -inst_cmovpo_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 622) } -inst_cmovpo_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 623) } -inst_cmovpo_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 623) } -inst_cmovpo_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 624) } -inst_cmovpo_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 624) } +inst_cmovpo_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 634) } +inst_cmovpo_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 634) } +inst_cmovpo_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 635) } +inst_cmovpo_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 635) } +inst_cmovpo_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 636) } +inst_cmovpo_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVPO, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 636) } emit_cmovpo_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovpo_r16_r16(dst, src)) } emit_cmovpo_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovpo_r16_m16(dst, src)) } emit_cmovpo_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovpo_r32_r32(dst, src)) } emit_cmovpo_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovpo_r32_m32(dst, src)) } emit_cmovpo_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovpo_r64_r64(dst, src)) } emit_cmovpo_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovpo_r64_m64(dst, src)) } -inst_cmovs_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 625) } -inst_cmovs_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 625) } -inst_cmovs_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 626) } -inst_cmovs_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 626) } -inst_cmovs_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 627) } -inst_cmovs_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 627) } +inst_cmovs_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 637) } +inst_cmovs_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 637) } +inst_cmovs_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 638) } +inst_cmovs_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 638) } +inst_cmovs_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 639) } +inst_cmovs_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 639) } emit_cmovs_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovs_r16_r16(dst, src)) } emit_cmovs_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovs_r16_m16(dst, src)) } emit_cmovs_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovs_r32_r32(dst, src)) } emit_cmovs_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovs_r32_m32(dst, src)) } emit_cmovs_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovs_r64_r64(dst, src)) } emit_cmovs_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovs_r64_m64(dst, src)) } -inst_cmovz_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 628) } -inst_cmovz_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 628) } -inst_cmovz_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 629) } -inst_cmovz_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 629) } -inst_cmovz_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 630) } -inst_cmovz_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 630) } +inst_cmovz_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 640) } +inst_cmovz_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 640) } +inst_cmovz_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 641) } +inst_cmovz_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 641) } +inst_cmovz_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 642) } +inst_cmovz_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMOVZ, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 642) } emit_cmovz_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmovz_r16_r16(dst, src)) } emit_cmovz_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_cmovz_r16_m16(dst, src)) } emit_cmovz_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_cmovz_r32_r32(dst, src)) } emit_cmovz_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cmovz_r32_m32(dst, src)) } emit_cmovz_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmovz_r64_r64(dst, src)) } emit_cmovz_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cmovz_r64_m64(dst, src)) } -inst_movs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVS, operand_count = 0, ops = {{}, {}, {}, {}} }, 631) } +inst_movs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVS, operand_count = 0, ops = {{}, {}, {}, {}} }, 643) } emit_movs_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_movs_none()) } -inst_movsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 632) } +inst_movsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 644) } emit_movsb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_movsb_none()) } -inst_movsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 633) } +inst_movsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 645) } emit_movsw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_movsw_none()) } -inst_movsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 634) } -inst_movsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 635) } -inst_movsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 635) } -inst_movsd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 636) } +inst_movsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 646) } +inst_movsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 647) } +inst_movsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 647) } +inst_movsd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 648) } emit_movsd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_movsd_none()) } emit_movsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movsd_xmm_xmm(dst, src)) } emit_movsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movsd_xmm_m64(dst, src)) } emit_movsd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movsd_m64_xmm(dst, src)) } -inst_movsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 637) } +inst_movsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 649) } emit_movsq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_movsq_none()) } -inst_cmps_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPS, operand_count = 0, ops = {{}, {}, {}, {}} }, 638) } +inst_cmps_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPS, operand_count = 0, ops = {{}, {}, {}, {}} }, 650) } emit_cmps_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmps_none()) } -inst_cmpsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 639) } +inst_cmpsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 651) } emit_cmpsb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmpsb_none()) } -inst_cmpsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 640) } +inst_cmpsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 652) } emit_cmpsw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmpsw_none()) } -inst_cmpsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 641) } -inst_cmpsd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 642) } -inst_cmpsd_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 642) } +inst_cmpsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 653) } +inst_cmpsd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 654) } +inst_cmpsd_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 654) } emit_cmpsd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmpsd_none()) } emit_cmpsd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpsd_xmm_xmm_imm8(dst, src, imm)) } emit_cmpsd_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64, imm: i8) { append(instructions, inst_cmpsd_xmm_m64_imm8(dst, src, imm)) } -inst_cmpsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 643) } +inst_cmpsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 655) } emit_cmpsq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmpsq_none()) } -inst_scas_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCAS, operand_count = 0, ops = {{}, {}, {}, {}} }, 644) } +inst_scas_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCAS, operand_count = 0, ops = {{}, {}, {}, {}} }, 656) } emit_scas_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_scas_none()) } -inst_scasb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASB, operand_count = 0, ops = {{}, {}, {}, {}} }, 645) } +inst_scasb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASB, operand_count = 0, ops = {{}, {}, {}, {}} }, 657) } emit_scasb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_scasb_none()) } -inst_scasw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASW, operand_count = 0, ops = {{}, {}, {}, {}} }, 646) } +inst_scasw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASW, operand_count = 0, ops = {{}, {}, {}, {}} }, 658) } emit_scasw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_scasw_none()) } -inst_scasd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASD, operand_count = 0, ops = {{}, {}, {}, {}} }, 647) } +inst_scasd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASD, operand_count = 0, ops = {{}, {}, {}, {}} }, 659) } emit_scasd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_scasd_none()) } -inst_scasq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 648) } +inst_scasq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SCASQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 660) } emit_scasq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_scasq_none()) } -inst_lods_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODS, operand_count = 0, ops = {{}, {}, {}, {}} }, 649) } +inst_lods_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODS, operand_count = 0, ops = {{}, {}, {}, {}} }, 661) } emit_lods_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lods_none()) } -inst_lodsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 650) } +inst_lodsb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 662) } emit_lodsb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lodsb_none()) } -inst_lodsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 651) } +inst_lodsw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 663) } emit_lodsw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lodsw_none()) } -inst_lodsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 652) } +inst_lodsd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 664) } emit_lodsd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lodsd_none()) } -inst_lodsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 653) } +inst_lodsq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LODSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 665) } emit_lodsq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lodsq_none()) } -inst_stos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 654) } +inst_stos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 666) } emit_stos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stos_none()) } -inst_stosb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 655) } +inst_stosb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSB, operand_count = 0, ops = {{}, {}, {}, {}} }, 667) } emit_stosb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stosb_none()) } -inst_stosw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 656) } +inst_stosw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSW, operand_count = 0, ops = {{}, {}, {}, {}} }, 668) } emit_stosw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stosw_none()) } -inst_stosd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 657) } +inst_stosd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSD, operand_count = 0, ops = {{}, {}, {}, {}} }, 669) } emit_stosd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stosd_none()) } -inst_stosq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 658) } +inst_stosq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STOSQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 670) } emit_stosq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stosq_none()) } -inst_clc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLC, operand_count = 0, ops = {{}, {}, {}, {}} }, 659) } +inst_clc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLC, operand_count = 0, ops = {{}, {}, {}, {}} }, 671) } emit_clc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clc_none()) } -inst_stc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STC, operand_count = 0, ops = {{}, {}, {}, {}} }, 660) } +inst_stc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STC, operand_count = 0, ops = {{}, {}, {}, {}} }, 672) } emit_stc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stc_none()) } -inst_cmc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMC, operand_count = 0, ops = {{}, {}, {}, {}} }, 661) } +inst_cmc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CMC, operand_count = 0, ops = {{}, {}, {}, {}} }, 673) } emit_cmc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cmc_none()) } -inst_cld_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLD, operand_count = 0, ops = {{}, {}, {}, {}} }, 662) } +inst_cld_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLD, operand_count = 0, ops = {{}, {}, {}, {}} }, 674) } emit_cld_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cld_none()) } -inst_std_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STD, operand_count = 0, ops = {{}, {}, {}, {}} }, 663) } +inst_std_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STD, operand_count = 0, ops = {{}, {}, {}, {}} }, 675) } emit_std_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_std_none()) } -inst_cli_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLI, operand_count = 0, ops = {{}, {}, {}, {}} }, 664) } +inst_cli_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLI, operand_count = 0, ops = {{}, {}, {}, {}} }, 676) } emit_cli_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cli_none()) } -inst_sti_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STI, operand_count = 0, ops = {{}, {}, {}, {}} }, 665) } +inst_sti_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STI, operand_count = 0, ops = {{}, {}, {}, {}} }, 677) } emit_sti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sti_none()) } -inst_lahf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LAHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 666) } +inst_lahf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LAHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 678) } emit_lahf_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lahf_none()) } -inst_sahf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SAHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 667) } +inst_sahf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SAHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 679) } emit_sahf_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sahf_none()) } -inst_pushf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 668) } +inst_pushf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHF, operand_count = 0, ops = {{}, {}, {}, {}} }, 680) } emit_pushf_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pushf_none()) } -inst_pushfd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHFD, operand_count = 0, ops = {{}, {}, {}, {}} }, 669) } +inst_pushfd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHFD, operand_count = 0, ops = {{}, {}, {}, {}} }, 681) } emit_pushfd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pushfd_none()) } -inst_pushfq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHFQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 670) } +inst_pushfq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PUSHFQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 682) } emit_pushfq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pushfq_none()) } -inst_popf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPF, operand_count = 0, ops = {{}, {}, {}, {}} }, 671) } +inst_popf_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPF, operand_count = 0, ops = {{}, {}, {}, {}} }, 683) } emit_popf_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_popf_none()) } -inst_popfd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPFD, operand_count = 0, ops = {{}, {}, {}, {}} }, 672) } +inst_popfd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPFD, operand_count = 0, ops = {{}, {}, {}, {}} }, 684) } emit_popfd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_popfd_none()) } -inst_popfq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPFQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 673) } +inst_popfq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .POPFQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 685) } emit_popfq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_popfq_none()) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 0, ops = {{}, {}, {}, {}} }, 674) } -inst_nop_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 675) } -inst_nop_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 675) } -inst_nop_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 676) } -inst_nop_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 676) } -inst_nop_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 677) } -inst_nop_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 677) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 0, ops = {{}, {}, {}, {}} }, 686) } +inst_nop_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 687) } +inst_nop_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 687) } +inst_nop_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 688) } +inst_nop_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 688) } +inst_nop_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 689) } +inst_nop_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .NOP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 689) } emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } emit_nop_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_nop_r16(dst)) } emit_nop_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_nop_m16(dst)) } @@ -1979,216 +2011,216 @@ emit_nop_r32 :: #force_inline proc(instructions: ^[dynami emit_nop_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_nop_m32(dst)) } emit_nop_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_nop_r64(dst)) } emit_nop_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_nop_m64(dst)) } -inst_hlt_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .HLT, operand_count = 0, ops = {{}, {}, {}, {}} }, 678) } +inst_hlt_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .HLT, operand_count = 0, ops = {{}, {}, {}, {}} }, 690) } emit_hlt_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_hlt_none()) } -inst_wait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 679) } +inst_wait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 691) } emit_wait_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wait_none()) } -inst_lock_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LOCK, operand_count = 0, ops = {{}, {}, {}, {}} }, 680) } +inst_lock_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LOCK, operand_count = 0, ops = {{}, {}, {}, {}} }, 692) } emit_lock_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lock_none()) } -inst_ud0_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD0, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 681) } -inst_ud0_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD0, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 681) } +inst_ud0_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD0, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 693) } +inst_ud0_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD0, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 693) } emit_ud0_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_ud0_r32_r32(dst, src)) } emit_ud0_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_ud0_r32_m32(dst, src)) } -inst_ud1_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD1, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 682) } -inst_ud1_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD1, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 682) } +inst_ud1_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD1, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 694) } +inst_ud1_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UD1, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 694) } emit_ud1_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_ud1_r32_r32(dst, src)) } emit_ud1_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_ud1_r32_m32(dst, src)) } -inst_ud2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .UD2, operand_count = 0, ops = {{}, {}, {}, {}} }, 683) } +inst_ud2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .UD2, operand_count = 0, ops = {{}, {}, {}, {}} }, 695) } emit_ud2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ud2_none()) } -inst_cpuid_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CPUID, operand_count = 0, ops = {{}, {}, {}, {}} }, 684) } +inst_cpuid_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CPUID, operand_count = 0, ops = {{}, {}, {}, {}} }, 696) } emit_cpuid_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cpuid_none()) } -inst_rdtsc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDTSC, operand_count = 0, ops = {{}, {}, {}, {}} }, 685) } +inst_rdtsc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDTSC, operand_count = 0, ops = {{}, {}, {}, {}} }, 697) } emit_rdtsc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdtsc_none()) } -inst_rdtscp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDTSCP, operand_count = 0, ops = {{}, {}, {}, {}} }, 686) } +inst_rdtscp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDTSCP, operand_count = 0, ops = {{}, {}, {}, {}} }, 698) } emit_rdtscp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdtscp_none()) } -inst_rdpmc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPMC, operand_count = 0, ops = {{}, {}, {}, {}} }, 687) } +inst_rdpmc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPMC, operand_count = 0, ops = {{}, {}, {}, {}} }, 699) } emit_rdpmc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdpmc_none()) } -inst_xgetbv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XGETBV, operand_count = 0, ops = {{}, {}, {}, {}} }, 688) } +inst_xgetbv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XGETBV, operand_count = 0, ops = {{}, {}, {}, {}} }, 700) } emit_xgetbv_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xgetbv_none()) } -inst_xsetbv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XSETBV, operand_count = 0, ops = {{}, {}, {}, {}} }, 689) } +inst_xsetbv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XSETBV, operand_count = 0, ops = {{}, {}, {}, {}} }, 701) } emit_xsetbv_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xsetbv_none()) } -inst_cbw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CBW, operand_count = 0, ops = {{}, {}, {}, {}} }, 690) } +inst_cbw_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CBW, operand_count = 0, ops = {{}, {}, {}, {}} }, 702) } emit_cbw_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cbw_none()) } -inst_cwde_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CWDE, operand_count = 0, ops = {{}, {}, {}, {}} }, 691) } +inst_cwde_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CWDE, operand_count = 0, ops = {{}, {}, {}, {}} }, 703) } emit_cwde_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cwde_none()) } -inst_cdqe_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CDQE, operand_count = 0, ops = {{}, {}, {}, {}} }, 692) } +inst_cdqe_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CDQE, operand_count = 0, ops = {{}, {}, {}, {}} }, 704) } emit_cdqe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cdqe_none()) } -inst_cwd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CWD, operand_count = 0, ops = {{}, {}, {}, {}} }, 693) } +inst_cwd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CWD, operand_count = 0, ops = {{}, {}, {}, {}} }, 705) } emit_cwd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cwd_none()) } -inst_cdq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CDQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 694) } +inst_cdq_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CDQ, operand_count = 0, ops = {{}, {}, {}, {}} }, 706) } emit_cdq_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cdq_none()) } -inst_cqo_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CQO, operand_count = 0, ops = {{}, {}, {}, {}} }, 695) } +inst_cqo_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CQO, operand_count = 0, ops = {{}, {}, {}, {}} }, 707) } emit_cqo_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_cqo_none()) } -inst_andn_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 696) } -inst_andn_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 696) } -inst_andn_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 697) } -inst_andn_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 697) } +inst_andn_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 708) } +inst_andn_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 708) } +inst_andn_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 709) } +inst_andn_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDN, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 709) } emit_andn_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_andn_r32_r32_r32(dst, src, src2)) } emit_andn_r32_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: Mem32) { append(instructions, inst_andn_r32_r32_m32(dst, src, src2)) } emit_andn_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_andn_r64_r64_r64(dst, src, src2)) } emit_andn_r64_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: Mem64) { append(instructions, inst_andn_r64_r64_m64(dst, src, src2)) } -inst_bextr_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 698) } -inst_bextr_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 698) } -inst_bextr_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 699) } -inst_bextr_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 699) } +inst_bextr_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 710) } +inst_bextr_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 710) } +inst_bextr_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 711) } +inst_bextr_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BEXTR, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 711) } emit_bextr_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_bextr_r32_r32_r32(dst, src, src2)) } emit_bextr_r32_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, src2: GPR32) { append(instructions, inst_bextr_r32_m32_r32(dst, src, src2)) } emit_bextr_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_bextr_r64_r64_r64(dst, src, src2)) } emit_bextr_r64_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, src2: GPR64) { append(instructions, inst_bextr_r64_m64_r64(dst, src, src2)) } -inst_blsi_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 700) } -inst_blsi_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 700) } -inst_blsi_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 701) } -inst_blsi_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 701) } +inst_blsi_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 712) } +inst_blsi_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 712) } +inst_blsi_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 713) } +inst_blsi_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 713) } emit_blsi_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_blsi_r32_r32(dst, src)) } emit_blsi_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_blsi_r32_m32(dst, src)) } emit_blsi_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_blsi_r64_r64(dst, src)) } emit_blsi_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_blsi_r64_m64(dst, src)) } -inst_blsmsk_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 702) } -inst_blsmsk_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 702) } -inst_blsmsk_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 703) } -inst_blsmsk_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 703) } +inst_blsmsk_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 714) } +inst_blsmsk_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 714) } +inst_blsmsk_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 715) } +inst_blsmsk_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSMSK, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 715) } emit_blsmsk_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_blsmsk_r32_r32(dst, src)) } emit_blsmsk_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_blsmsk_r32_m32(dst, src)) } emit_blsmsk_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_blsmsk_r64_r64(dst, src)) } emit_blsmsk_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_blsmsk_r64_m64(dst, src)) } -inst_blsr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 704) } -inst_blsr_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 704) } -inst_blsr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 705) } -inst_blsr_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 705) } +inst_blsr_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 716) } +inst_blsr_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 716) } +inst_blsr_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 717) } +inst_blsr_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .BLSR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 717) } emit_blsr_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_blsr_r32_r32(dst, src)) } emit_blsr_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_blsr_r32_m32(dst, src)) } emit_blsr_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_blsr_r64_r64(dst, src)) } emit_blsr_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_blsr_r64_m64(dst, src)) } -inst_bzhi_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 706) } -inst_bzhi_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 706) } -inst_bzhi_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 707) } -inst_bzhi_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 707) } +inst_bzhi_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 718) } +inst_bzhi_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 718) } +inst_bzhi_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 719) } +inst_bzhi_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BZHI, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 719) } emit_bzhi_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_bzhi_r32_r32_r32(dst, src, src2)) } emit_bzhi_r32_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, src2: GPR32) { append(instructions, inst_bzhi_r32_m32_r32(dst, src, src2)) } emit_bzhi_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_bzhi_r64_r64_r64(dst, src, src2)) } emit_bzhi_r64_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, src2: GPR64) { append(instructions, inst_bzhi_r64_m64_r64(dst, src, src2)) } -inst_pdep_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 708) } -inst_pdep_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 708) } -inst_pdep_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 709) } -inst_pdep_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 709) } +inst_pdep_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 720) } +inst_pdep_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 720) } +inst_pdep_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 721) } +inst_pdep_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PDEP, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 721) } emit_pdep_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_pdep_r32_r32_r32(dst, src, src2)) } emit_pdep_r32_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: Mem32) { append(instructions, inst_pdep_r32_r32_m32(dst, src, src2)) } emit_pdep_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_pdep_r64_r64_r64(dst, src, src2)) } emit_pdep_r64_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: Mem64) { append(instructions, inst_pdep_r64_r64_m64(dst, src, src2)) } -inst_pext_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 710) } -inst_pext_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 710) } -inst_pext_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 711) } -inst_pext_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 711) } +inst_pext_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 722) } +inst_pext_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 722) } +inst_pext_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 723) } +inst_pext_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXT, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 723) } emit_pext_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_pext_r32_r32_r32(dst, src, src2)) } emit_pext_r32_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: Mem32) { append(instructions, inst_pext_r32_r32_m32(dst, src, src2)) } emit_pext_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_pext_r64_r64_r64(dst, src, src2)) } emit_pext_r64_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: Mem64) { append(instructions, inst_pext_r64_r64_m64(dst, src, src2)) } -inst_rorx_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 712) } -inst_rorx_r32_m32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 712) } -inst_rorx_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 713) } -inst_rorx_r64_m64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 713) } +inst_rorx_r32_r32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_imm8(imm), {}} }, 724) } +inst_rorx_r32_m32_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 724) } +inst_rorx_r64_r64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_imm8(imm), {}} }, 725) } +inst_rorx_r64_m64_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .RORX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 725) } emit_rorx_r32_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, imm: i8) { append(instructions, inst_rorx_r32_r32_imm8(dst, src, imm)) } emit_rorx_r32_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, imm: i8) { append(instructions, inst_rorx_r32_m32_imm8(dst, src, imm)) } emit_rorx_r64_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, imm: i8) { append(instructions, inst_rorx_r64_r64_imm8(dst, src, imm)) } emit_rorx_r64_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, imm: i8) { append(instructions, inst_rorx_r64_m64_imm8(dst, src, imm)) } -inst_sarx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 714) } -inst_sarx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 714) } -inst_sarx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 715) } -inst_sarx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 715) } +inst_sarx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 726) } +inst_sarx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 726) } +inst_sarx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 727) } +inst_sarx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SARX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 727) } emit_sarx_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_sarx_r32_r32_r32(dst, src, src2)) } emit_sarx_r32_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, src2: GPR32) { append(instructions, inst_sarx_r32_m32_r32(dst, src, src2)) } emit_sarx_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_sarx_r64_r64_r64(dst, src, src2)) } emit_sarx_r64_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, src2: GPR64) { append(instructions, inst_sarx_r64_m64_r64(dst, src, src2)) } -inst_shlx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 716) } -inst_shlx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 716) } -inst_shlx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 717) } -inst_shlx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 717) } +inst_shlx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 728) } +inst_shlx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 728) } +inst_shlx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 729) } +inst_shlx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHLX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 729) } emit_shlx_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_shlx_r32_r32_r32(dst, src, src2)) } emit_shlx_r32_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, src2: GPR32) { append(instructions, inst_shlx_r32_m32_r32(dst, src, src2)) } emit_shlx_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_shlx_r64_r64_r64(dst, src, src2)) } emit_shlx_r64_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, src2: GPR64) { append(instructions, inst_shlx_r64_m64_r64(dst, src, src2)) } -inst_shrx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 718) } -inst_shrx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 718) } -inst_shrx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 719) } -inst_shrx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 719) } +inst_shrx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 730) } +inst_shrx_r32_m32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr32(dst), op_mem(src.mem, 4), op_gpr32(src2), {}} }, 730) } +inst_shrx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 731) } +inst_shrx_r64_m64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SHRX, operand_count = 3, ops = {op_gpr64(dst), op_mem(src.mem, 8), op_gpr64(src2), {}} }, 731) } emit_shrx_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_shrx_r32_r32_r32(dst, src, src2)) } emit_shrx_r32_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32, src2: GPR32) { append(instructions, inst_shrx_r32_m32_r32(dst, src, src2)) } emit_shrx_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_shrx_r64_r64_r64(dst, src, src2)) } emit_shrx_r64_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64, src2: GPR64) { append(instructions, inst_shrx_r64_m64_r64(dst, src, src2)) } -inst_mulx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 720) } -inst_mulx_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 720) } -inst_mulx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 721) } -inst_mulx_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 721) } +inst_mulx_r32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_gpr32(src2), {}} }, 732) } +inst_mulx_r32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr32(dst), op_gpr32(src), op_mem(src2.mem, 4), {}} }, 732) } +inst_mulx_r64_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_gpr64(src2), {}} }, 733) } +inst_mulx_r64_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULX, operand_count = 3, ops = {op_gpr64(dst), op_gpr64(src), op_mem(src2.mem, 8), {}} }, 733) } emit_mulx_r32_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: GPR32) { append(instructions, inst_mulx_r32_r32_r32(dst, src, src2)) } emit_mulx_r32_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32, src2: Mem32) { append(instructions, inst_mulx_r32_r32_m32(dst, src, src2)) } emit_mulx_r64_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: GPR64) { append(instructions, inst_mulx_r64_r64_r64(dst, src, src2)) } emit_mulx_r64_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64, src2: Mem64) { append(instructions, inst_mulx_r64_r64_m64(dst, src, src2)) } -inst_adcx_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 722) } -inst_adcx_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 722) } -inst_adcx_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 723) } -inst_adcx_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 723) } +inst_adcx_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 734) } +inst_adcx_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 734) } +inst_adcx_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 735) } +inst_adcx_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADCX, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 735) } emit_adcx_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_adcx_r32_r32(dst, src)) } emit_adcx_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_adcx_r32_m32(dst, src)) } emit_adcx_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_adcx_r64_r64(dst, src)) } emit_adcx_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_adcx_r64_m64(dst, src)) } -inst_adox_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 724) } -inst_adox_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 724) } -inst_adox_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 725) } -inst_adox_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 725) } +inst_adox_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 736) } +inst_adox_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 736) } +inst_adox_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 737) } +inst_adox_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADOX, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 737) } emit_adox_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_adox_r32_r32(dst, src)) } emit_adox_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_adox_r32_m32(dst, src)) } emit_adox_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_adox_r64_r64(dst, src)) } emit_adox_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_adox_r64_m64(dst, src)) } -inst_movaps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 726) } -inst_movaps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 726) } -inst_movaps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 727) } +inst_movaps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 738) } +inst_movaps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 738) } +inst_movaps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 739) } emit_movaps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movaps_xmm_xmm(dst, src)) } emit_movaps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movaps_xmm_m128(dst, src)) } emit_movaps_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movaps_m128_xmm(dst, src)) } -inst_movups_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 728) } -inst_movups_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 728) } -inst_movups_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 729) } +inst_movups_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 740) } +inst_movups_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 740) } +inst_movups_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 741) } emit_movups_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movups_xmm_xmm(dst, src)) } emit_movups_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movups_xmm_m128(dst, src)) } emit_movups_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movups_m128_xmm(dst, src)) } -inst_movapd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 730) } -inst_movapd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 730) } -inst_movapd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 731) } +inst_movapd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 742) } +inst_movapd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 742) } +inst_movapd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 743) } emit_movapd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movapd_xmm_xmm(dst, src)) } emit_movapd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movapd_xmm_m128(dst, src)) } emit_movapd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movapd_m128_xmm(dst, src)) } -inst_movupd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 732) } -inst_movupd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 732) } -inst_movupd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 733) } +inst_movupd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 744) } +inst_movupd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 744) } +inst_movupd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 745) } emit_movupd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movupd_xmm_xmm(dst, src)) } emit_movupd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movupd_xmm_m128(dst, src)) } emit_movupd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movupd_m128_xmm(dst, src)) } -inst_movss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 734) } -inst_movss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 734) } -inst_movss_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 735) } +inst_movss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 746) } +inst_movss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 746) } +inst_movss_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 747) } emit_movss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movss_xmm_xmm(dst, src)) } emit_movss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_movss_xmm_m32(dst, src)) } emit_movss_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_movss_m32_xmm(dst, src)) } -inst_movdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 736) } -inst_movdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 736) } -inst_movdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 737) } +inst_movdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 748) } +inst_movdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 748) } +inst_movdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 749) } emit_movdqa_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movdqa_xmm_xmm(dst, src)) } emit_movdqa_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movdqa_xmm_m128(dst, src)) } emit_movdqa_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movdqa_m128_xmm(dst, src)) } -inst_movdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 738) } -inst_movdqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 738) } -inst_movdqu_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 739) } +inst_movdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 750) } +inst_movdqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 750) } +inst_movdqu_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 751) } emit_movdqu_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movdqu_xmm_xmm(dst, src)) } emit_movdqu_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movdqu_xmm_m128(dst, src)) } emit_movdqu_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movdqu_m128_xmm(dst, src)) } -inst_movq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 740) } -inst_movq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 740) } -inst_movq_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 741) } -inst_movq_mm_mm :: #force_inline proc "contextless" (dst: MM, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mm(dst), op_mm(src), {}, {}} }, 742) } -inst_movq_mm_m64 :: #force_inline proc "contextless" (dst: MM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mm(dst), op_mem(src.mem, 8), {}, {}} }, 742) } -inst_movq_m64_mm :: #force_inline proc "contextless" (dst: Mem64, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_mm(src), {}, {}} }, 743) } -inst_movq_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 744) } -inst_movq_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 745) } +inst_movq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 752) } +inst_movq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 752) } +inst_movq_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 753) } +inst_movq_mm_mm :: #force_inline proc "contextless" (dst: MM, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mm(dst), op_mm(src), {}, {}} }, 754) } +inst_movq_mm_m64 :: #force_inline proc "contextless" (dst: MM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mm(dst), op_mem(src.mem, 8), {}, {}} }, 754) } +inst_movq_m64_mm :: #force_inline proc "contextless" (dst: Mem64, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_mm(src), {}, {}} }, 755) } +inst_movq_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 756) } +inst_movq_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVQ, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 757) } emit_movq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movq_xmm_xmm(dst, src)) } emit_movq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movq_xmm_m64(dst, src)) } emit_movq_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movq_m64_xmm(dst, src)) } @@ -2197,14 +2229,14 @@ emit_movq_mm_m64 :: #force_inline proc(instructions: ^[dynami emit_movq_m64_mm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: MM) { append(instructions, inst_movq_m64_mm(dst, src)) } emit_movq_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_movq_r64_xmm(dst, src)) } emit_movq_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR64) { append(instructions, inst_movq_xmm_r64(dst, src)) } -inst_movd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 746) } -inst_movd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 746) } -inst_movd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 747) } -inst_movd_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 747) } -inst_movd_mm_r32 :: #force_inline proc "contextless" (dst: MM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mm(dst), op_gpr32(src), {}, {}} }, 748) } -inst_movd_mm_m32 :: #force_inline proc "contextless" (dst: MM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mm(dst), op_mem(src.mem, 4), {}, {}} }, 748) } -inst_movd_r32_mm :: #force_inline proc "contextless" (dst: GPR32, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_gpr32(dst), op_mm(src), {}, {}} }, 749) } -inst_movd_m32_mm :: #force_inline proc "contextless" (dst: Mem32, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_mm(src), {}, {}} }, 749) } +inst_movd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 758) } +inst_movd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 758) } +inst_movd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 759) } +inst_movd_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 759) } +inst_movd_mm_r32 :: #force_inline proc "contextless" (dst: MM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mm(dst), op_gpr32(src), {}, {}} }, 760) } +inst_movd_mm_m32 :: #force_inline proc "contextless" (dst: MM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mm(dst), op_mem(src.mem, 4), {}, {}} }, 760) } +inst_movd_r32_mm :: #force_inline proc "contextless" (dst: GPR32, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_gpr32(dst), op_mm(src), {}, {}} }, 761) } +inst_movd_m32_mm :: #force_inline proc "contextless" (dst: Mem32, src: MM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_mm(src), {}, {}} }, 761) } emit_movd_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32) { append(instructions, inst_movd_xmm_r32(dst, src)) } emit_movd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_movd_xmm_m32(dst, src)) } emit_movd_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_movd_r32_xmm(dst, src)) } @@ -2213,926 +2245,926 @@ emit_movd_mm_r32 :: #force_inline proc(instructions: ^[dynami emit_movd_mm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: MM, src: Mem32) { append(instructions, inst_movd_mm_m32(dst, src)) } emit_movd_r32_mm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: MM) { append(instructions, inst_movd_r32_mm(dst, src)) } emit_movd_m32_mm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: MM) { append(instructions, inst_movd_m32_mm(dst, src)) } -inst_movlps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 750) } -inst_movlps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 751) } +inst_movlps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 762) } +inst_movlps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 763) } emit_movlps_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movlps_xmm_m64(dst, src)) } emit_movlps_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movlps_m64_xmm(dst, src)) } -inst_movhps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 752) } -inst_movhps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 753) } +inst_movhps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 764) } +inst_movhps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 765) } emit_movhps_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movhps_xmm_m64(dst, src)) } emit_movhps_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movhps_m64_xmm(dst, src)) } -inst_movlpd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 754) } -inst_movlpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 755) } +inst_movlpd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 766) } +inst_movlpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 767) } emit_movlpd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movlpd_xmm_m64(dst, src)) } emit_movlpd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movlpd_m64_xmm(dst, src)) } -inst_movhpd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 756) } -inst_movhpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 757) } +inst_movhpd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 768) } +inst_movhpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 769) } emit_movhpd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movhpd_xmm_m64(dst, src)) } emit_movhpd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_movhpd_m64_xmm(dst, src)) } -inst_movlhps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLHPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 758) } +inst_movlhps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVLHPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 770) } emit_movlhps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movlhps_xmm_xmm(dst, src)) } -inst_movhlps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHLPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 759) } +inst_movhlps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVHLPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 771) } emit_movhlps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movhlps_xmm_xmm(dst, src)) } -inst_movmskps_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 760) } -inst_movmskps_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPS, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 761) } +inst_movmskps_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 772) } +inst_movmskps_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPS, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 773) } emit_movmskps_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_movmskps_r32_xmm(dst, src)) } emit_movmskps_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_movmskps_r64_xmm(dst, src)) } -inst_movmskpd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 762) } -inst_movmskpd_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPD, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 763) } +inst_movmskpd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 774) } +inst_movmskpd_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVMSKPD, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 775) } emit_movmskpd_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_movmskpd_r32_xmm(dst, src)) } emit_movmskpd_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_movmskpd_r64_xmm(dst, src)) } -inst_movntps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 764) } +inst_movntps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 776) } emit_movntps_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movntps_m128_xmm(dst, src)) } -inst_movntpd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 765) } +inst_movntpd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 777) } emit_movntpd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movntpd_m128_xmm(dst, src)) } -inst_movntdq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 766) } +inst_movntdq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 778) } emit_movntdq_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_movntdq_m128_xmm(dst, src)) } -inst_movntdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 767) } +inst_movntdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVNTDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 779) } emit_movntdqa_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movntdqa_xmm_m128(dst, src)) } -inst_addps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 768) } -inst_addps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 768) } +inst_addps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 780) } +inst_addps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 780) } emit_addps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addps_xmm_xmm(dst, src)) } emit_addps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_addps_xmm_m128(dst, src)) } -inst_addpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 769) } -inst_addpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 769) } +inst_addpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 781) } +inst_addpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 781) } emit_addpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addpd_xmm_xmm(dst, src)) } emit_addpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_addpd_xmm_m128(dst, src)) } -inst_addss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 770) } -inst_addss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 770) } +inst_addss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 782) } +inst_addss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 782) } emit_addss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addss_xmm_xmm(dst, src)) } emit_addss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_addss_xmm_m32(dst, src)) } -inst_addsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 771) } -inst_addsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 771) } +inst_addsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 783) } +inst_addsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 783) } emit_addsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addsd_xmm_xmm(dst, src)) } emit_addsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_addsd_xmm_m64(dst, src)) } -inst_subps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 772) } -inst_subps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 772) } +inst_subps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 784) } +inst_subps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 784) } emit_subps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_subps_xmm_xmm(dst, src)) } emit_subps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_subps_xmm_m128(dst, src)) } -inst_subpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 773) } -inst_subpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 773) } +inst_subpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 785) } +inst_subpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 785) } emit_subpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_subpd_xmm_xmm(dst, src)) } emit_subpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_subpd_xmm_m128(dst, src)) } -inst_subss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 774) } -inst_subss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 774) } +inst_subss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 786) } +inst_subss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 786) } emit_subss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_subss_xmm_xmm(dst, src)) } emit_subss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_subss_xmm_m32(dst, src)) } -inst_subsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 775) } -inst_subsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 775) } +inst_subsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 787) } +inst_subsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .SUBSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 787) } emit_subsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_subsd_xmm_xmm(dst, src)) } emit_subsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_subsd_xmm_m64(dst, src)) } -inst_mulps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 776) } -inst_mulps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 776) } +inst_mulps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 788) } +inst_mulps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 788) } emit_mulps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_mulps_xmm_xmm(dst, src)) } emit_mulps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_mulps_xmm_m128(dst, src)) } -inst_mulpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 777) } -inst_mulpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 777) } +inst_mulpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 789) } +inst_mulpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MULPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 789) } emit_mulpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_mulpd_xmm_xmm(dst, src)) } emit_mulpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_mulpd_xmm_m128(dst, src)) } -inst_mulss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 778) } -inst_mulss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 778) } +inst_mulss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 790) } +inst_mulss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 790) } emit_mulss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_mulss_xmm_xmm(dst, src)) } emit_mulss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_mulss_xmm_m32(dst, src)) } -inst_mulsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 779) } -inst_mulsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 779) } +inst_mulsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 791) } +inst_mulsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MULSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 791) } emit_mulsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_mulsd_xmm_xmm(dst, src)) } emit_mulsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_mulsd_xmm_m64(dst, src)) } -inst_divps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 780) } -inst_divps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 780) } +inst_divps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 792) } +inst_divps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 792) } emit_divps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_divps_xmm_xmm(dst, src)) } emit_divps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_divps_xmm_m128(dst, src)) } -inst_divpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 781) } -inst_divpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 781) } +inst_divpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 793) } +inst_divpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 793) } emit_divpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_divpd_xmm_xmm(dst, src)) } emit_divpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_divpd_xmm_m128(dst, src)) } -inst_divss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 782) } -inst_divss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 782) } +inst_divss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 794) } +inst_divss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 794) } emit_divss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_divss_xmm_xmm(dst, src)) } emit_divss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_divss_xmm_m32(dst, src)) } -inst_divsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 783) } -inst_divsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 783) } +inst_divsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 795) } +inst_divsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .DIVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 795) } emit_divsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_divsd_xmm_xmm(dst, src)) } emit_divsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_divsd_xmm_m64(dst, src)) } -inst_sqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 784) } -inst_sqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 784) } +inst_sqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 796) } +inst_sqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 796) } emit_sqrtps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sqrtps_xmm_xmm(dst, src)) } emit_sqrtps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sqrtps_xmm_m128(dst, src)) } -inst_sqrtpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 785) } -inst_sqrtpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 785) } +inst_sqrtpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 797) } +inst_sqrtpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 797) } emit_sqrtpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sqrtpd_xmm_xmm(dst, src)) } emit_sqrtpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sqrtpd_xmm_m128(dst, src)) } -inst_sqrtss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 786) } -inst_sqrtss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 786) } +inst_sqrtss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 798) } +inst_sqrtss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 798) } emit_sqrtss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sqrtss_xmm_xmm(dst, src)) } emit_sqrtss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_sqrtss_xmm_m32(dst, src)) } -inst_sqrtsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 787) } -inst_sqrtsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 787) } +inst_sqrtsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 799) } +inst_sqrtsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .SQRTSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 799) } emit_sqrtsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sqrtsd_xmm_xmm(dst, src)) } emit_sqrtsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_sqrtsd_xmm_m64(dst, src)) } -inst_rcpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 788) } -inst_rcpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 788) } +inst_rcpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 800) } +inst_rcpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 800) } emit_rcpps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_rcpps_xmm_xmm(dst, src)) } emit_rcpps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_rcpps_xmm_m128(dst, src)) } -inst_rcpss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 789) } -inst_rcpss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 789) } +inst_rcpss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 801) } +inst_rcpss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RCPSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 801) } emit_rcpss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_rcpss_xmm_xmm(dst, src)) } emit_rcpss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_rcpss_xmm_m32(dst, src)) } -inst_rsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 790) } -inst_rsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 790) } +inst_rsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 802) } +inst_rsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 802) } emit_rsqrtps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_rsqrtps_xmm_xmm(dst, src)) } emit_rsqrtps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_rsqrtps_xmm_m128(dst, src)) } -inst_rsqrtss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 791) } -inst_rsqrtss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 791) } +inst_rsqrtss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 803) } +inst_rsqrtss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .RSQRTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 803) } emit_rsqrtss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_rsqrtss_xmm_xmm(dst, src)) } emit_rsqrtss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_rsqrtss_xmm_m32(dst, src)) } -inst_maxps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 792) } -inst_maxps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 792) } +inst_maxps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 804) } +inst_maxps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 804) } emit_maxps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_maxps_xmm_xmm(dst, src)) } emit_maxps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_maxps_xmm_m128(dst, src)) } -inst_maxpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 793) } -inst_maxpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 793) } +inst_maxpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 805) } +inst_maxpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 805) } emit_maxpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_maxpd_xmm_xmm(dst, src)) } emit_maxpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_maxpd_xmm_m128(dst, src)) } -inst_maxss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 794) } -inst_maxss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 794) } +inst_maxss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 806) } +inst_maxss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 806) } emit_maxss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_maxss_xmm_xmm(dst, src)) } emit_maxss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_maxss_xmm_m32(dst, src)) } -inst_maxsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 795) } -inst_maxsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 795) } +inst_maxsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 807) } +inst_maxsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MAXSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 807) } emit_maxsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_maxsd_xmm_xmm(dst, src)) } emit_maxsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_maxsd_xmm_m64(dst, src)) } -inst_minps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 796) } -inst_minps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 796) } +inst_minps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 808) } +inst_minps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 808) } emit_minps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_minps_xmm_xmm(dst, src)) } emit_minps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_minps_xmm_m128(dst, src)) } -inst_minpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 797) } -inst_minpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 797) } +inst_minpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 809) } +inst_minpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MINPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 809) } emit_minpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_minpd_xmm_xmm(dst, src)) } emit_minpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_minpd_xmm_m128(dst, src)) } -inst_minss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 798) } -inst_minss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 798) } +inst_minss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 810) } +inst_minss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 810) } emit_minss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_minss_xmm_xmm(dst, src)) } emit_minss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_minss_xmm_m32(dst, src)) } -inst_minsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 799) } -inst_minsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 799) } +inst_minsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 811) } +inst_minsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MINSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 811) } emit_minsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_minsd_xmm_xmm(dst, src)) } emit_minsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_minsd_xmm_m64(dst, src)) } -inst_andps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 800) } -inst_andps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 800) } +inst_andps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 812) } +inst_andps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 812) } emit_andps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_andps_xmm_xmm(dst, src)) } emit_andps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_andps_xmm_m128(dst, src)) } -inst_andpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 801) } -inst_andpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 801) } +inst_andpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 813) } +inst_andpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 813) } emit_andpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_andpd_xmm_xmm(dst, src)) } emit_andpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_andpd_xmm_m128(dst, src)) } -inst_andnps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 802) } -inst_andnps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 802) } +inst_andnps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 814) } +inst_andnps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 814) } emit_andnps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_andnps_xmm_xmm(dst, src)) } emit_andnps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_andnps_xmm_m128(dst, src)) } -inst_andnpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 803) } -inst_andnpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 803) } +inst_andnpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 815) } +inst_andnpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ANDNPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 815) } emit_andnpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_andnpd_xmm_xmm(dst, src)) } emit_andnpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_andnpd_xmm_m128(dst, src)) } -inst_orps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 804) } -inst_orps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 804) } +inst_orps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 816) } +inst_orps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 816) } emit_orps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_orps_xmm_xmm(dst, src)) } emit_orps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_orps_xmm_m128(dst, src)) } -inst_orpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 805) } -inst_orpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 805) } +inst_orpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 817) } +inst_orpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ORPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 817) } emit_orpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_orpd_xmm_xmm(dst, src)) } emit_orpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_orpd_xmm_m128(dst, src)) } -inst_xorps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 806) } -inst_xorps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 806) } +inst_xorps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 818) } +inst_xorps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 818) } emit_xorps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_xorps_xmm_xmm(dst, src)) } emit_xorps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_xorps_xmm_m128(dst, src)) } -inst_xorpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 807) } -inst_xorpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 807) } +inst_xorpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 819) } +inst_xorpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .XORPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 819) } emit_xorpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_xorpd_xmm_xmm(dst, src)) } emit_xorpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_xorpd_xmm_m128(dst, src)) } -inst_cmpps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 808) } -inst_cmpps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 808) } +inst_cmpps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 820) } +inst_cmpps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 820) } emit_cmpps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpps_xmm_xmm_imm8(dst, src, imm)) } emit_cmpps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_cmpps_xmm_m128_imm8(dst, src, imm)) } -inst_cmppd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 809) } -inst_cmppd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 809) } +inst_cmppd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 821) } +inst_cmppd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 821) } emit_cmppd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmppd_xmm_xmm_imm8(dst, src, imm)) } emit_cmppd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_cmppd_xmm_m128_imm8(dst, src, imm)) } -inst_cmpss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 810) } -inst_cmpss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 810) } +inst_cmpss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 822) } +inst_cmpss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 822) } emit_cmpss_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_cmpss_xmm_xmm_imm8(dst, src, imm)) } emit_cmpss_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_cmpss_xmm_m32_imm8(dst, src, imm)) } -inst_comiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 811) } -inst_comiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 811) } +inst_comiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 823) } +inst_comiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 823) } emit_comiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_comiss_xmm_xmm(dst, src)) } emit_comiss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_comiss_xmm_m32(dst, src)) } -inst_comisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 812) } -inst_comisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 812) } +inst_comisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 824) } +inst_comisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .COMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 824) } emit_comisd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_comisd_xmm_xmm(dst, src)) } emit_comisd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_comisd_xmm_m64(dst, src)) } -inst_ucomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 813) } -inst_ucomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 813) } +inst_ucomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 825) } +inst_ucomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 825) } emit_ucomiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_ucomiss_xmm_xmm(dst, src)) } emit_ucomiss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_ucomiss_xmm_m32(dst, src)) } -inst_ucomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 814) } -inst_ucomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 814) } +inst_ucomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 826) } +inst_ucomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .UCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 826) } emit_ucomisd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_ucomisd_xmm_xmm(dst, src)) } emit_ucomisd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_ucomisd_xmm_m64(dst, src)) } -inst_shufps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 815) } -inst_shufps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 815) } +inst_shufps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 827) } +inst_shufps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 827) } emit_shufps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_shufps_xmm_xmm_imm8(dst, src, imm)) } emit_shufps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_shufps_xmm_m128_imm8(dst, src, imm)) } -inst_shufpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 816) } -inst_shufpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 816) } +inst_shufpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 828) } +inst_shufpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHUFPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 828) } emit_shufpd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_shufpd_xmm_xmm_imm8(dst, src, imm)) } emit_shufpd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_shufpd_xmm_m128_imm8(dst, src, imm)) } -inst_unpcklps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 817) } -inst_unpcklps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 817) } +inst_unpcklps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 829) } +inst_unpcklps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 829) } emit_unpcklps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_unpcklps_xmm_xmm(dst, src)) } emit_unpcklps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_unpcklps_xmm_m128(dst, src)) } -inst_unpckhps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 818) } -inst_unpckhps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 818) } +inst_unpckhps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 830) } +inst_unpckhps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 830) } emit_unpckhps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_unpckhps_xmm_xmm(dst, src)) } emit_unpckhps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_unpckhps_xmm_m128(dst, src)) } -inst_unpcklpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 819) } -inst_unpcklpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 819) } +inst_unpcklpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 831) } +inst_unpcklpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKLPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 831) } emit_unpcklpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_unpcklpd_xmm_xmm(dst, src)) } emit_unpcklpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_unpcklpd_xmm_m128(dst, src)) } -inst_unpckhpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 820) } -inst_unpckhpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 820) } +inst_unpckhpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 832) } +inst_unpckhpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .UNPCKHPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 832) } emit_unpckhpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_unpckhpd_xmm_xmm(dst, src)) } emit_unpckhpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_unpckhpd_xmm_m128(dst, src)) } -inst_cvtps2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 821) } -inst_cvtps2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 821) } +inst_cvtps2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 833) } +inst_cvtps2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 833) } emit_cvtps2pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtps2pd_xmm_xmm(dst, src)) } emit_cvtps2pd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_cvtps2pd_xmm_m64(dst, src)) } -inst_cvtpd2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 822) } -inst_cvtpd2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 822) } +inst_cvtpd2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 834) } +inst_cvtpd2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 834) } emit_cvtpd2ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtpd2ps_xmm_xmm(dst, src)) } emit_cvtpd2ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvtpd2ps_xmm_m128(dst, src)) } -inst_cvtss2sd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 823) } -inst_cvtss2sd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 823) } +inst_cvtss2sd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 835) } +inst_cvtss2sd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 835) } emit_cvtss2sd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtss2sd_xmm_xmm(dst, src)) } emit_cvtss2sd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_cvtss2sd_xmm_m32(dst, src)) } -inst_cvtsd2ss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 824) } -inst_cvtsd2ss_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 824) } +inst_cvtsd2ss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 836) } +inst_cvtsd2ss_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 836) } emit_cvtsd2ss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtsd2ss_xmm_xmm(dst, src)) } emit_cvtsd2ss_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_cvtsd2ss_xmm_m64(dst, src)) } -inst_cvtps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 825) } -inst_cvtps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 825) } +inst_cvtps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 837) } +inst_cvtps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 837) } emit_cvtps2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtps2dq_xmm_xmm(dst, src)) } emit_cvtps2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvtps2dq_xmm_m128(dst, src)) } -inst_cvtpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 826) } -inst_cvtpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 826) } +inst_cvtpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 838) } +inst_cvtpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 838) } emit_cvtpd2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtpd2dq_xmm_xmm(dst, src)) } emit_cvtpd2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvtpd2dq_xmm_m128(dst, src)) } -inst_cvtdq2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 827) } -inst_cvtdq2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 827) } +inst_cvtdq2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 839) } +inst_cvtdq2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 839) } emit_cvtdq2ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtdq2ps_xmm_xmm(dst, src)) } emit_cvtdq2ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvtdq2ps_xmm_m128(dst, src)) } -inst_cvtdq2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 828) } -inst_cvtdq2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 828) } +inst_cvtdq2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 840) } +inst_cvtdq2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 840) } emit_cvtdq2pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvtdq2pd_xmm_xmm(dst, src)) } emit_cvtdq2pd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_cvtdq2pd_xmm_m64(dst, src)) } -inst_cvtss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 829) } -inst_cvtss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 829) } -inst_cvtss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 830) } -inst_cvtss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 830) } +inst_cvtss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 841) } +inst_cvtss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 841) } +inst_cvtss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 842) } +inst_cvtss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 842) } emit_cvtss2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_cvtss2si_r32_xmm(dst, src)) } emit_cvtss2si_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cvtss2si_r32_m32(dst, src)) } emit_cvtss2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_cvtss2si_r64_xmm(dst, src)) } emit_cvtss2si_r64_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem32) { append(instructions, inst_cvtss2si_r64_m32(dst, src)) } -inst_cvtsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 831) } -inst_cvtsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 831) } -inst_cvtsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 832) } -inst_cvtsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 832) } +inst_cvtsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 843) } +inst_cvtsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 843) } +inst_cvtsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 844) } +inst_cvtsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 844) } emit_cvtsd2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_cvtsd2si_r32_xmm(dst, src)) } emit_cvtsd2si_r32_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem64) { append(instructions, inst_cvtsd2si_r32_m64(dst, src)) } emit_cvtsd2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_cvtsd2si_r64_xmm(dst, src)) } emit_cvtsd2si_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cvtsd2si_r64_m64(dst, src)) } -inst_cvtsi2ss_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 833) } -inst_cvtsi2ss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 833) } -inst_cvtsi2ss_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 834) } -inst_cvtsi2ss_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 834) } +inst_cvtsi2ss_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 845) } +inst_cvtsi2ss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 845) } +inst_cvtsi2ss_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 846) } +inst_cvtsi2ss_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 846) } emit_cvtsi2ss_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32) { append(instructions, inst_cvtsi2ss_xmm_r32(dst, src)) } emit_cvtsi2ss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_cvtsi2ss_xmm_m32(dst, src)) } emit_cvtsi2ss_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR64) { append(instructions, inst_cvtsi2ss_xmm_r64(dst, src)) } emit_cvtsi2ss_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_cvtsi2ss_xmm_m64(dst, src)) } -inst_cvtsi2sd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 835) } -inst_cvtsi2sd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 835) } -inst_cvtsi2sd_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 836) } -inst_cvtsi2sd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 836) } +inst_cvtsi2sd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 847) } +inst_cvtsi2sd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 847) } +inst_cvtsi2sd_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 848) } +inst_cvtsi2sd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTSI2SD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 848) } emit_cvtsi2sd_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32) { append(instructions, inst_cvtsi2sd_xmm_r32(dst, src)) } emit_cvtsi2sd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_cvtsi2sd_xmm_m32(dst, src)) } emit_cvtsi2sd_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR64) { append(instructions, inst_cvtsi2sd_xmm_r64(dst, src)) } emit_cvtsi2sd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_cvtsi2sd_xmm_m64(dst, src)) } -inst_cvttps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 837) } -inst_cvttps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 837) } +inst_cvttps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 849) } +inst_cvttps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 849) } emit_cvttps2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvttps2dq_xmm_xmm(dst, src)) } emit_cvttps2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvttps2dq_xmm_m128(dst, src)) } -inst_cvttpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 838) } -inst_cvttpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 838) } +inst_cvttpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 850) } +inst_cvttpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 850) } emit_cvttpd2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_cvttpd2dq_xmm_xmm(dst, src)) } emit_cvttpd2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_cvttpd2dq_xmm_m128(dst, src)) } -inst_cvttss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 839) } -inst_cvttss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 839) } -inst_cvttss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 840) } -inst_cvttss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 840) } +inst_cvttss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 851) } +inst_cvttss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 851) } +inst_cvttss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 852) } +inst_cvttss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 852) } emit_cvttss2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_cvttss2si_r32_xmm(dst, src)) } emit_cvttss2si_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_cvttss2si_r32_m32(dst, src)) } emit_cvttss2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_cvttss2si_r64_xmm(dst, src)) } emit_cvttss2si_r64_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem32) { append(instructions, inst_cvttss2si_r64_m32(dst, src)) } -inst_cvttsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 841) } -inst_cvttsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 841) } -inst_cvttsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 842) } -inst_cvttsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 842) } +inst_cvttsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 853) } +inst_cvttsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 853) } +inst_cvttsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 854) } +inst_cvttsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 854) } emit_cvttsd2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_cvttsd2si_r32_xmm(dst, src)) } emit_cvttsd2si_r32_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem64) { append(instructions, inst_cvttsd2si_r32_m64(dst, src)) } emit_cvttsd2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_cvttsd2si_r64_xmm(dst, src)) } emit_cvttsd2si_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_cvttsd2si_r64_m64(dst, src)) } -inst_paddb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 843) } -inst_paddb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 843) } +inst_paddb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 855) } +inst_paddb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 855) } emit_paddb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddb_xmm_xmm(dst, src)) } emit_paddb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddb_xmm_m128(dst, src)) } -inst_paddw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 844) } -inst_paddw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 844) } +inst_paddw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 856) } +inst_paddw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 856) } emit_paddw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddw_xmm_xmm(dst, src)) } emit_paddw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddw_xmm_m128(dst, src)) } -inst_paddd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 845) } -inst_paddd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 845) } +inst_paddd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 857) } +inst_paddd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 857) } emit_paddd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddd_xmm_xmm(dst, src)) } emit_paddd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddd_xmm_m128(dst, src)) } -inst_paddq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 846) } -inst_paddq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 846) } +inst_paddq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 858) } +inst_paddq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 858) } emit_paddq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddq_xmm_xmm(dst, src)) } emit_paddq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddq_xmm_m128(dst, src)) } -inst_psubb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 847) } -inst_psubb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 847) } +inst_psubb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 859) } +inst_psubb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 859) } emit_psubb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubb_xmm_xmm(dst, src)) } emit_psubb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubb_xmm_m128(dst, src)) } -inst_psubw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 848) } -inst_psubw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 848) } +inst_psubw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 860) } +inst_psubw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 860) } emit_psubw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubw_xmm_xmm(dst, src)) } emit_psubw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubw_xmm_m128(dst, src)) } -inst_psubd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 849) } -inst_psubd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 849) } +inst_psubd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 861) } +inst_psubd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 861) } emit_psubd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubd_xmm_xmm(dst, src)) } emit_psubd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubd_xmm_m128(dst, src)) } -inst_psubq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 850) } -inst_psubq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 850) } +inst_psubq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 862) } +inst_psubq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 862) } emit_psubq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubq_xmm_xmm(dst, src)) } emit_psubq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubq_xmm_m128(dst, src)) } -inst_paddsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 851) } -inst_paddsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 851) } +inst_paddsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 863) } +inst_paddsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 863) } emit_paddsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddsb_xmm_xmm(dst, src)) } emit_paddsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddsb_xmm_m128(dst, src)) } -inst_paddsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 852) } -inst_paddsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 852) } +inst_paddsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 864) } +inst_paddsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 864) } emit_paddsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddsw_xmm_xmm(dst, src)) } emit_paddsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddsw_xmm_m128(dst, src)) } -inst_paddusb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 853) } -inst_paddusb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 853) } +inst_paddusb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 865) } +inst_paddusb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 865) } emit_paddusb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddusb_xmm_xmm(dst, src)) } emit_paddusb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddusb_xmm_m128(dst, src)) } -inst_paddusw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 854) } -inst_paddusw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 854) } +inst_paddusw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 866) } +inst_paddusw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PADDUSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 866) } emit_paddusw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_paddusw_xmm_xmm(dst, src)) } emit_paddusw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_paddusw_xmm_m128(dst, src)) } -inst_psubsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 855) } -inst_psubsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 855) } +inst_psubsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 867) } +inst_psubsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 867) } emit_psubsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubsb_xmm_xmm(dst, src)) } emit_psubsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubsb_xmm_m128(dst, src)) } -inst_psubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 856) } -inst_psubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 856) } +inst_psubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 868) } +inst_psubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 868) } emit_psubsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubsw_xmm_xmm(dst, src)) } emit_psubsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubsw_xmm_m128(dst, src)) } -inst_psubusb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 857) } -inst_psubusb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 857) } +inst_psubusb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 869) } +inst_psubusb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 869) } emit_psubusb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubusb_xmm_xmm(dst, src)) } emit_psubusb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubusb_xmm_m128(dst, src)) } -inst_psubusw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 858) } -inst_psubusw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 858) } +inst_psubusw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 870) } +inst_psubusw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSUBUSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 870) } emit_psubusw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psubusw_xmm_xmm(dst, src)) } emit_psubusw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psubusw_xmm_m128(dst, src)) } -inst_pmullw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 859) } -inst_pmullw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 859) } +inst_pmullw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 871) } +inst_pmullw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 871) } emit_pmullw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmullw_xmm_xmm(dst, src)) } emit_pmullw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmullw_xmm_m128(dst, src)) } -inst_pmulhw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 860) } -inst_pmulhw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 860) } +inst_pmulhw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 872) } +inst_pmulhw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 872) } emit_pmulhw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmulhw_xmm_xmm(dst, src)) } emit_pmulhw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmulhw_xmm_m128(dst, src)) } -inst_pmulhuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 861) } -inst_pmulhuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 861) } +inst_pmulhuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 873) } +inst_pmulhuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 873) } emit_pmulhuw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmulhuw_xmm_xmm(dst, src)) } emit_pmulhuw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmulhuw_xmm_m128(dst, src)) } -inst_pmuludq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULUDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 862) } -inst_pmuludq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULUDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 862) } +inst_pmuludq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULUDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 874) } +inst_pmuludq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULUDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 874) } emit_pmuludq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmuludq_xmm_xmm(dst, src)) } emit_pmuludq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmuludq_xmm_m128(dst, src)) } -inst_pmaddwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 863) } -inst_pmaddwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 863) } +inst_pmaddwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 875) } +inst_pmaddwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 875) } emit_pmaddwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaddwd_xmm_xmm(dst, src)) } emit_pmaddwd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaddwd_xmm_m128(dst, src)) } -inst_pand_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAND, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 864) } -inst_pand_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAND, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 864) } +inst_pand_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAND, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 876) } +inst_pand_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAND, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 876) } emit_pand_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pand_xmm_xmm(dst, src)) } emit_pand_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pand_xmm_m128(dst, src)) } -inst_pandn_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PANDN, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 865) } -inst_pandn_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PANDN, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 865) } +inst_pandn_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PANDN, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 877) } +inst_pandn_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PANDN, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 877) } emit_pandn_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pandn_xmm_xmm(dst, src)) } emit_pandn_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pandn_xmm_m128(dst, src)) } -inst_por_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .POR, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 866) } -inst_por_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .POR, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 866) } +inst_por_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .POR, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 878) } +inst_por_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .POR, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 878) } emit_por_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_por_xmm_xmm(dst, src)) } emit_por_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_por_xmm_m128(dst, src)) } -inst_pxor_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PXOR, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 867) } -inst_pxor_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PXOR, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 867) } +inst_pxor_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PXOR, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 879) } +inst_pxor_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PXOR, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 879) } emit_pxor_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pxor_xmm_xmm(dst, src)) } emit_pxor_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pxor_xmm_m128(dst, src)) } -inst_psllw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 868) } -inst_psllw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 868) } -inst_psllw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 869) } +inst_psllw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 880) } +inst_psllw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 880) } +inst_psllw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 881) } emit_psllw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psllw_xmm_xmm(dst, src)) } emit_psllw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psllw_xmm_m128(dst, src)) } emit_psllw_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psllw_xmm_imm8(dst, imm)) } -inst_pslld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 870) } -inst_pslld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 870) } -inst_pslld_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 871) } +inst_pslld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 882) } +inst_pslld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 882) } +inst_pslld_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 883) } emit_pslld_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pslld_xmm_xmm(dst, src)) } emit_pslld_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pslld_xmm_m128(dst, src)) } emit_pslld_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_pslld_xmm_imm8(dst, imm)) } -inst_psllq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 872) } -inst_psllq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 872) } -inst_psllq_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 873) } +inst_psllq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 884) } +inst_psllq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 884) } +inst_psllq_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSLLQ, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 885) } emit_psllq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psllq_xmm_xmm(dst, src)) } emit_psllq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psllq_xmm_m128(dst, src)) } emit_psllq_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psllq_xmm_imm8(dst, imm)) } -inst_psrlw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 874) } -inst_psrlw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 874) } -inst_psrlw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 875) } +inst_psrlw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 886) } +inst_psrlw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 886) } +inst_psrlw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 887) } emit_psrlw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psrlw_xmm_xmm(dst, src)) } emit_psrlw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psrlw_xmm_m128(dst, src)) } emit_psrlw_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psrlw_xmm_imm8(dst, imm)) } -inst_psrld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 876) } -inst_psrld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 876) } -inst_psrld_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 877) } +inst_psrld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 888) } +inst_psrld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 888) } +inst_psrld_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 889) } emit_psrld_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psrld_xmm_xmm(dst, src)) } emit_psrld_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psrld_xmm_m128(dst, src)) } emit_psrld_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psrld_xmm_imm8(dst, imm)) } -inst_psrlq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 878) } -inst_psrlq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 878) } -inst_psrlq_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 879) } +inst_psrlq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 890) } +inst_psrlq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 890) } +inst_psrlq_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRLQ, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 891) } emit_psrlq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psrlq_xmm_xmm(dst, src)) } emit_psrlq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psrlq_xmm_m128(dst, src)) } emit_psrlq_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psrlq_xmm_imm8(dst, imm)) } -inst_psraw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 880) } -inst_psraw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 880) } -inst_psraw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 881) } +inst_psraw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 892) } +inst_psraw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 892) } +inst_psraw_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAW, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 893) } emit_psraw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psraw_xmm_xmm(dst, src)) } emit_psraw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psraw_xmm_m128(dst, src)) } emit_psraw_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psraw_xmm_imm8(dst, imm)) } -inst_psrad_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 882) } -inst_psrad_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 882) } -inst_psrad_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 883) } +inst_psrad_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 894) } +inst_psrad_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 894) } +inst_psrad_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSRAD, operand_count = 2, ops = {op_xmm(dst), op_imm8(imm), {}, {}} }, 895) } emit_psrad_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psrad_xmm_xmm(dst, src)) } emit_psrad_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psrad_xmm_m128(dst, src)) } emit_psrad_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, imm: i8) { append(instructions, inst_psrad_xmm_imm8(dst, imm)) } -inst_pcmpeqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 884) } -inst_pcmpeqb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 884) } +inst_pcmpeqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 896) } +inst_pcmpeqb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 896) } emit_pcmpeqb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpeqb_xmm_xmm(dst, src)) } emit_pcmpeqb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpeqb_xmm_m128(dst, src)) } -inst_pcmpeqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 885) } -inst_pcmpeqw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 885) } +inst_pcmpeqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 897) } +inst_pcmpeqw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 897) } emit_pcmpeqw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpeqw_xmm_xmm(dst, src)) } emit_pcmpeqw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpeqw_xmm_m128(dst, src)) } -inst_pcmpeqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 886) } -inst_pcmpeqd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 886) } +inst_pcmpeqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 898) } +inst_pcmpeqd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 898) } emit_pcmpeqd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpeqd_xmm_xmm(dst, src)) } emit_pcmpeqd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpeqd_xmm_m128(dst, src)) } -inst_pcmpgtb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 887) } -inst_pcmpgtb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 887) } +inst_pcmpgtb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 899) } +inst_pcmpgtb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 899) } emit_pcmpgtb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpgtb_xmm_xmm(dst, src)) } emit_pcmpgtb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpgtb_xmm_m128(dst, src)) } -inst_pcmpgtw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 888) } -inst_pcmpgtw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 888) } +inst_pcmpgtw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 900) } +inst_pcmpgtw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 900) } emit_pcmpgtw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpgtw_xmm_xmm(dst, src)) } emit_pcmpgtw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpgtw_xmm_m128(dst, src)) } -inst_pcmpgtd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 889) } -inst_pcmpgtd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 889) } +inst_pcmpgtd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 901) } +inst_pcmpgtd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 901) } emit_pcmpgtd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpgtd_xmm_xmm(dst, src)) } emit_pcmpgtd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpgtd_xmm_m128(dst, src)) } -inst_packsswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 890) } -inst_packsswb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSWB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 890) } +inst_packsswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 902) } +inst_packsswb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSWB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 902) } emit_packsswb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_packsswb_xmm_xmm(dst, src)) } emit_packsswb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_packsswb_xmm_m128(dst, src)) } -inst_packssdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 891) } -inst_packssdw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 891) } +inst_packssdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 903) } +inst_packssdw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKSSDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 903) } emit_packssdw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_packssdw_xmm_xmm(dst, src)) } emit_packssdw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_packssdw_xmm_m128(dst, src)) } -inst_packuswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 892) } -inst_packuswb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSWB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 892) } +inst_packuswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 904) } +inst_packuswb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSWB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 904) } emit_packuswb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_packuswb_xmm_xmm(dst, src)) } emit_packuswb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_packuswb_xmm_m128(dst, src)) } -inst_punpcklbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 893) } -inst_punpcklbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 893) } +inst_punpcklbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 905) } +inst_punpcklbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 905) } emit_punpcklbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpcklbw_xmm_xmm(dst, src)) } emit_punpcklbw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpcklbw_xmm_m128(dst, src)) } -inst_punpcklwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 894) } -inst_punpcklwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 894) } +inst_punpcklwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 906) } +inst_punpcklwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 906) } emit_punpcklwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpcklwd_xmm_xmm(dst, src)) } emit_punpcklwd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpcklwd_xmm_m128(dst, src)) } -inst_punpckldq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 895) } -inst_punpckldq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 895) } +inst_punpckldq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 907) } +inst_punpckldq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 907) } emit_punpckldq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpckldq_xmm_xmm(dst, src)) } emit_punpckldq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpckldq_xmm_m128(dst, src)) } -inst_punpcklqdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLQDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 896) } -inst_punpcklqdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLQDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 896) } +inst_punpcklqdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLQDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 908) } +inst_punpcklqdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKLQDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 908) } emit_punpcklqdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpcklqdq_xmm_xmm(dst, src)) } emit_punpcklqdq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpcklqdq_xmm_m128(dst, src)) } -inst_punpckhbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 897) } -inst_punpckhbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 897) } +inst_punpckhbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 909) } +inst_punpckhbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 909) } emit_punpckhbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpckhbw_xmm_xmm(dst, src)) } emit_punpckhbw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpckhbw_xmm_m128(dst, src)) } -inst_punpckhwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 898) } -inst_punpckhwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 898) } +inst_punpckhwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 910) } +inst_punpckhwd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 910) } emit_punpckhwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpckhwd_xmm_xmm(dst, src)) } emit_punpckhwd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpckhwd_xmm_m128(dst, src)) } -inst_punpckhdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 899) } -inst_punpckhdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 899) } +inst_punpckhdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 911) } +inst_punpckhdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 911) } emit_punpckhdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpckhdq_xmm_xmm(dst, src)) } emit_punpckhdq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpckhdq_xmm_m128(dst, src)) } -inst_punpckhqdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHQDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 900) } -inst_punpckhqdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHQDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 900) } +inst_punpckhqdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHQDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 912) } +inst_punpckhqdq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PUNPCKHQDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 912) } emit_punpckhqdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_punpckhqdq_xmm_xmm(dst, src)) } emit_punpckhqdq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_punpckhqdq_xmm_m128(dst, src)) } -inst_pshufd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 901) } -inst_pshufd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 901) } +inst_pshufd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 913) } +inst_pshufd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 913) } emit_pshufd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pshufd_xmm_xmm_imm8(dst, src, imm)) } emit_pshufd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pshufd_xmm_m128_imm8(dst, src, imm)) } -inst_pshufhw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 902) } -inst_pshufhw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 902) } +inst_pshufhw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 914) } +inst_pshufhw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 914) } emit_pshufhw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pshufhw_xmm_xmm_imm8(dst, src, imm)) } emit_pshufhw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pshufhw_xmm_m128_imm8(dst, src, imm)) } -inst_pshuflw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 903) } -inst_pshuflw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 903) } +inst_pshuflw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 915) } +inst_pshuflw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 915) } emit_pshuflw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pshuflw_xmm_xmm_imm8(dst, src, imm)) } emit_pshuflw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pshuflw_xmm_m128_imm8(dst, src, imm)) } -inst_pshufw_mm_mm_imm8 :: #force_inline proc "contextless" (dst: MM, src: MM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFW, operand_count = 3, ops = {op_mm(dst), op_mm(src), op_imm8(imm), {}} }, 904) } -inst_pshufw_mm_m64_imm8 :: #force_inline proc "contextless" (dst: MM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFW, operand_count = 3, ops = {op_mm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 904) } +inst_pshufw_mm_mm_imm8 :: #force_inline proc "contextless" (dst: MM, src: MM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFW, operand_count = 3, ops = {op_mm(dst), op_mm(src), op_imm8(imm), {}} }, 916) } +inst_pshufw_mm_m64_imm8 :: #force_inline proc "contextless" (dst: MM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFW, operand_count = 3, ops = {op_mm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 916) } emit_pshufw_mm_mm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: MM, src: MM, imm: i8) { append(instructions, inst_pshufw_mm_mm_imm8(dst, src, imm)) } emit_pshufw_mm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: MM, src: Mem64, imm: i8) { append(instructions, inst_pshufw_mm_m64_imm8(dst, src, imm)) } -inst_pextrw_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRW, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 905) } -inst_pextrw_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRW, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 906) } +inst_pextrw_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRW, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 917) } +inst_pextrw_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRW, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 918) } emit_pextrw_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_pextrw_r32_xmm_imm8(dst, src, imm)) } emit_pextrw_r64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM, imm: i8) { append(instructions, inst_pextrw_r64_xmm_imm8(dst, src, imm)) } -inst_pinsrw_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRW, operand_count = 3, ops = {op_xmm(dst), op_gpr32(src), op_imm8(imm), {}} }, 907) } -inst_pinsrw_xmm_m16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 2), op_imm8(imm), {}} }, 908) } +inst_pinsrw_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRW, operand_count = 3, ops = {op_xmm(dst), op_gpr32(src), op_imm8(imm), {}} }, 919) } +inst_pinsrw_xmm_m16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 2), op_imm8(imm), {}} }, 920) } emit_pinsrw_xmm_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32, imm: i8) { append(instructions, inst_pinsrw_xmm_r32_imm8(dst, src, imm)) } emit_pinsrw_xmm_m16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem16, imm: i8) { append(instructions, inst_pinsrw_xmm_m16_imm8(dst, src, imm)) } -inst_pmovmskb_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 909) } -inst_pmovmskb_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVMSKB, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 910) } +inst_pmovmskb_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 921) } +inst_pmovmskb_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVMSKB, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 922) } emit_pmovmskb_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_pmovmskb_r32_xmm(dst, src)) } emit_pmovmskb_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_pmovmskb_r64_xmm(dst, src)) } -inst_pavgb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 911) } -inst_pavgb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 911) } +inst_pavgb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 923) } +inst_pavgb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 923) } emit_pavgb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pavgb_xmm_xmm(dst, src)) } emit_pavgb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pavgb_xmm_m128(dst, src)) } -inst_pavgw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 912) } -inst_pavgw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 912) } +inst_pavgw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 924) } +inst_pavgw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PAVGW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 924) } emit_pavgw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pavgw_xmm_xmm(dst, src)) } emit_pavgw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pavgw_xmm_m128(dst, src)) } -inst_pmaxub_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 913) } -inst_pmaxub_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 913) } +inst_pmaxub_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 925) } +inst_pmaxub_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 925) } emit_pmaxub_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxub_xmm_xmm(dst, src)) } emit_pmaxub_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxub_xmm_m128(dst, src)) } -inst_pmaxsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 914) } -inst_pmaxsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 914) } +inst_pmaxsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 926) } +inst_pmaxsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 926) } emit_pmaxsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxsw_xmm_xmm(dst, src)) } emit_pmaxsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxsw_xmm_m128(dst, src)) } -inst_pminub_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 915) } -inst_pminub_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 915) } +inst_pminub_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 927) } +inst_pminub_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 927) } emit_pminub_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminub_xmm_xmm(dst, src)) } emit_pminub_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminub_xmm_m128(dst, src)) } -inst_pminsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 916) } -inst_pminsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 916) } +inst_pminsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 928) } +inst_pminsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 928) } emit_pminsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminsw_xmm_xmm(dst, src)) } emit_pminsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminsw_xmm_m128(dst, src)) } -inst_psadbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSADBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 917) } -inst_psadbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSADBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 917) } +inst_psadbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSADBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 929) } +inst_psadbw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSADBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 929) } emit_psadbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psadbw_xmm_xmm(dst, src)) } emit_psadbw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psadbw_xmm_m128(dst, src)) } -inst_maskmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MASKMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 918) } +inst_maskmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MASKMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 930) } emit_maskmovdqu_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_maskmovdqu_xmm_xmm(dst, src)) } -inst_lfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 919) } +inst_lfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 931) } emit_lfence_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lfence_none()) } -inst_sfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 920) } +inst_sfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 932) } emit_sfence_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sfence_none()) } -inst_mfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 921) } +inst_mfence_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MFENCE, operand_count = 0, ops = {{}, {}, {}, {}} }, 933) } emit_mfence_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_mfence_none()) } -inst_pause_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PAUSE, operand_count = 0, ops = {{}, {}, {}, {}} }, 922) } +inst_pause_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PAUSE, operand_count = 0, ops = {{}, {}, {}, {}} }, 934) } emit_pause_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pause_none()) } -inst_clflush_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLFLUSH, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 923) } +inst_clflush_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLFLUSH, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 935) } emit_clflush_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_clflush_m8(dst)) } -inst_addsubps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 924) } -inst_addsubps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 924) } +inst_addsubps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 936) } +inst_addsubps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 936) } emit_addsubps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addsubps_xmm_xmm(dst, src)) } emit_addsubps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_addsubps_xmm_m128(dst, src)) } -inst_addsubpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 925) } -inst_addsubpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 925) } +inst_addsubpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 937) } +inst_addsubpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .ADDSUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 937) } emit_addsubpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_addsubpd_xmm_xmm(dst, src)) } emit_addsubpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_addsubpd_xmm_m128(dst, src)) } -inst_haddps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 926) } -inst_haddps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 926) } +inst_haddps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 938) } +inst_haddps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 938) } emit_haddps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_haddps_xmm_xmm(dst, src)) } emit_haddps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_haddps_xmm_m128(dst, src)) } -inst_haddpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 927) } -inst_haddpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 927) } +inst_haddpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 939) } +inst_haddpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HADDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 939) } emit_haddpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_haddpd_xmm_xmm(dst, src)) } emit_haddpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_haddpd_xmm_m128(dst, src)) } -inst_hsubps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 928) } -inst_hsubps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 928) } +inst_hsubps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 940) } +inst_hsubps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 940) } emit_hsubps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_hsubps_xmm_xmm(dst, src)) } emit_hsubps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_hsubps_xmm_m128(dst, src)) } -inst_hsubpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 929) } -inst_hsubpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 929) } +inst_hsubpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 941) } +inst_hsubpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .HSUBPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 941) } emit_hsubpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_hsubpd_xmm_xmm(dst, src)) } emit_hsubpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_hsubpd_xmm_m128(dst, src)) } -inst_movddup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 930) } -inst_movddup_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 930) } +inst_movddup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 942) } +inst_movddup_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 942) } emit_movddup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movddup_xmm_xmm(dst, src)) } emit_movddup_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_movddup_xmm_m64(dst, src)) } -inst_movsldup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 931) } -inst_movsldup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 931) } +inst_movsldup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 943) } +inst_movsldup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 943) } emit_movsldup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movsldup_xmm_xmm(dst, src)) } emit_movsldup_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movsldup_xmm_m128(dst, src)) } -inst_movshdup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 932) } -inst_movshdup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 932) } +inst_movshdup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 944) } +inst_movshdup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 944) } emit_movshdup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_movshdup_xmm_xmm(dst, src)) } emit_movshdup_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_movshdup_xmm_m128(dst, src)) } -inst_lddqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .LDDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 933) } +inst_lddqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .LDDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 945) } emit_lddqu_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_lddqu_xmm_m128(dst, src)) } -inst_pshufb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 934) } -inst_pshufb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 934) } +inst_pshufb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 946) } +inst_pshufb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSHUFB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 946) } emit_pshufb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pshufb_xmm_xmm(dst, src)) } emit_pshufb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pshufb_xmm_m128(dst, src)) } -inst_phaddw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 935) } -inst_phaddw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 935) } +inst_phaddw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 947) } +inst_phaddw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 947) } emit_phaddw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phaddw_xmm_xmm(dst, src)) } emit_phaddw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phaddw_xmm_m128(dst, src)) } -inst_phaddd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 936) } -inst_phaddd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 936) } +inst_phaddd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 948) } +inst_phaddd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 948) } emit_phaddd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phaddd_xmm_xmm(dst, src)) } emit_phaddd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phaddd_xmm_m128(dst, src)) } -inst_phaddsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 937) } -inst_phaddsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 937) } +inst_phaddsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 949) } +inst_phaddsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHADDSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 949) } emit_phaddsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phaddsw_xmm_xmm(dst, src)) } emit_phaddsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phaddsw_xmm_m128(dst, src)) } -inst_phsubw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 938) } -inst_phsubw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 938) } +inst_phsubw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 950) } +inst_phsubw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 950) } emit_phsubw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phsubw_xmm_xmm(dst, src)) } emit_phsubw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phsubw_xmm_m128(dst, src)) } -inst_phsubd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 939) } -inst_phsubd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 939) } +inst_phsubd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 951) } +inst_phsubd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 951) } emit_phsubd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phsubd_xmm_xmm(dst, src)) } emit_phsubd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phsubd_xmm_m128(dst, src)) } -inst_phsubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 940) } -inst_phsubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 940) } +inst_phsubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 952) } +inst_phsubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHSUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 952) } emit_phsubsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phsubsw_xmm_xmm(dst, src)) } emit_phsubsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phsubsw_xmm_m128(dst, src)) } -inst_pmaddubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 941) } -inst_pmaddubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 941) } +inst_pmaddubsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDUBSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 953) } +inst_pmaddubsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMADDUBSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 953) } emit_pmaddubsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaddubsw_xmm_xmm(dst, src)) } emit_pmaddubsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaddubsw_xmm_m128(dst, src)) } -inst_pmulhrsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHRSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 942) } -inst_pmulhrsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHRSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 942) } +inst_pmulhrsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHRSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 954) } +inst_pmulhrsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULHRSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 954) } emit_pmulhrsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmulhrsw_xmm_xmm(dst, src)) } emit_pmulhrsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmulhrsw_xmm_m128(dst, src)) } -inst_psignb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 943) } -inst_psignb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 943) } +inst_psignb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 955) } +inst_psignb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 955) } emit_psignb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psignb_xmm_xmm(dst, src)) } emit_psignb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psignb_xmm_m128(dst, src)) } -inst_psignw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 944) } -inst_psignw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 944) } +inst_psignw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 956) } +inst_psignw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGNW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 956) } emit_psignw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psignw_xmm_xmm(dst, src)) } emit_psignw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psignw_xmm_m128(dst, src)) } -inst_psignd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGND, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 945) } -inst_psignd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGND, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 945) } +inst_psignd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGND, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 957) } +inst_psignd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PSIGND, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 957) } emit_psignd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_psignd_xmm_xmm(dst, src)) } emit_psignd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_psignd_xmm_m128(dst, src)) } -inst_pabsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 946) } -inst_pabsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 946) } +inst_pabsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 958) } +inst_pabsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 958) } emit_pabsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pabsb_xmm_xmm(dst, src)) } emit_pabsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pabsb_xmm_m128(dst, src)) } -inst_pabsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 947) } -inst_pabsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 947) } +inst_pabsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 959) } +inst_pabsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 959) } emit_pabsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pabsw_xmm_xmm(dst, src)) } emit_pabsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pabsw_xmm_m128(dst, src)) } -inst_pabsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 948) } -inst_pabsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 948) } +inst_pabsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 960) } +inst_pabsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PABSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 960) } emit_pabsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pabsd_xmm_xmm(dst, src)) } emit_pabsd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pabsd_xmm_m128(dst, src)) } -inst_palignr_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PALIGNR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 949) } -inst_palignr_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PALIGNR, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 949) } +inst_palignr_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PALIGNR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 961) } +inst_palignr_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PALIGNR, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 961) } emit_palignr_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_palignr_xmm_xmm_imm8(dst, src, imm)) } emit_palignr_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_palignr_xmm_m128_imm8(dst, src, imm)) } -inst_blendps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 950) } -inst_blendps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 950) } +inst_blendps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 962) } +inst_blendps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 962) } emit_blendps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_blendps_xmm_xmm_imm8(dst, src, imm)) } emit_blendps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_blendps_xmm_m128_imm8(dst, src, imm)) } -inst_blendpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 951) } -inst_blendpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 951) } +inst_blendpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 963) } +inst_blendpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 963) } emit_blendpd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_blendpd_xmm_xmm_imm8(dst, src, imm)) } emit_blendpd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_blendpd_xmm_m128_imm8(dst, src, imm)) } -inst_blendvps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 952) } -inst_blendvps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 952) } +inst_blendvps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 964) } +inst_blendvps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 964) } emit_blendvps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_blendvps_xmm_xmm(dst, src)) } emit_blendvps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_blendvps_xmm_m128(dst, src)) } -inst_blendvpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 953) } -inst_blendvpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 953) } +inst_blendvpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 965) } +inst_blendvpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .BLENDVPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 965) } emit_blendvpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_blendvpd_xmm_xmm(dst, src)) } emit_blendvpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_blendvpd_xmm_m128(dst, src)) } -inst_pblendw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 954) } -inst_pblendw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 954) } +inst_pblendw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 966) } +inst_pblendw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 966) } emit_pblendw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pblendw_xmm_xmm_imm8(dst, src, imm)) } emit_pblendw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pblendw_xmm_m128_imm8(dst, src, imm)) } -inst_pblendvb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDVB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 955) } -inst_pblendvb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDVB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 955) } +inst_pblendvb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDVB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 967) } +inst_pblendvb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PBLENDVB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 967) } emit_pblendvb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pblendvb_xmm_xmm(dst, src)) } emit_pblendvb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pblendvb_xmm_m128(dst, src)) } -inst_dpps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 956) } -inst_dpps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 956) } +inst_dpps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 968) } +inst_dpps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 968) } emit_dpps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_dpps_xmm_xmm_imm8(dst, src, imm)) } emit_dpps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_dpps_xmm_m128_imm8(dst, src, imm)) } -inst_dppd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 957) } -inst_dppd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 957) } +inst_dppd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 969) } +inst_dppd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .DPPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 969) } emit_dppd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_dppd_xmm_xmm_imm8(dst, src, imm)) } emit_dppd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_dppd_xmm_m128_imm8(dst, src, imm)) } -inst_extractps_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .EXTRACTPS, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 958) } -inst_extractps_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .EXTRACTPS, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 958) } +inst_extractps_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .EXTRACTPS, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 970) } +inst_extractps_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .EXTRACTPS, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 970) } emit_extractps_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_extractps_r32_xmm_imm8(dst, src, imm)) } emit_extractps_m32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM, imm: i8) { append(instructions, inst_extractps_m32_xmm_imm8(dst, src, imm)) } -inst_insertps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INSERTPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 959) } -inst_insertps_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INSERTPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 959) } +inst_insertps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INSERTPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 971) } +inst_insertps_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .INSERTPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 971) } emit_insertps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_insertps_xmm_xmm_imm8(dst, src, imm)) } emit_insertps_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_insertps_xmm_m32_imm8(dst, src, imm)) } -inst_mpsadbw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .MPSADBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 960) } -inst_mpsadbw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .MPSADBW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 960) } +inst_mpsadbw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .MPSADBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 972) } +inst_mpsadbw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .MPSADBW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 972) } emit_mpsadbw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_mpsadbw_xmm_xmm_imm8(dst, src, imm)) } emit_mpsadbw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_mpsadbw_xmm_m128_imm8(dst, src, imm)) } -inst_packusdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 961) } -inst_packusdw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 961) } +inst_packusdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 973) } +inst_packusdw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PACKUSDW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 973) } emit_packusdw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_packusdw_xmm_xmm(dst, src)) } emit_packusdw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_packusdw_xmm_m128(dst, src)) } -inst_pextrb_r8_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRB, operand_count = 3, ops = {op_gpr8(dst), op_xmm(src), op_imm8(imm), {}} }, 962) } -inst_pextrb_m8_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRB, operand_count = 3, ops = {op_mem(dst.mem, 1), op_xmm(src), op_imm8(imm), {}} }, 962) } +inst_pextrb_r8_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRB, operand_count = 3, ops = {op_gpr8(dst), op_xmm(src), op_imm8(imm), {}} }, 974) } +inst_pextrb_m8_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRB, operand_count = 3, ops = {op_mem(dst.mem, 1), op_xmm(src), op_imm8(imm), {}} }, 974) } emit_pextrb_r8_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, src: XMM, imm: i8) { append(instructions, inst_pextrb_r8_xmm_imm8(dst, src, imm)) } emit_pextrb_m8_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, src: XMM, imm: i8) { append(instructions, inst_pextrb_m8_xmm_imm8(dst, src, imm)) } -inst_pextrd_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRD, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 963) } -inst_pextrd_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 963) } +inst_pextrd_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRD, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 975) } +inst_pextrd_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 975) } emit_pextrd_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_pextrd_r32_xmm_imm8(dst, src, imm)) } emit_pextrd_m32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM, imm: i8) { append(instructions, inst_pextrd_m32_xmm_imm8(dst, src, imm)) } -inst_pextrq_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRQ, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 964) } -inst_pextrq_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRQ, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 964) } +inst_pextrq_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRQ, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 976) } +inst_pextrq_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PEXTRQ, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 976) } emit_pextrq_r64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM, imm: i8) { append(instructions, inst_pextrq_r64_xmm_imm8(dst, src, imm)) } emit_pextrq_m64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM, imm: i8) { append(instructions, inst_pextrq_m64_xmm_imm8(dst, src, imm)) } -inst_phminposuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 965) } -inst_phminposuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 965) } +inst_phminposuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 977) } +inst_phminposuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 977) } emit_phminposuw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_phminposuw_xmm_xmm(dst, src)) } emit_phminposuw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_phminposuw_xmm_m128(dst, src)) } -inst_pinsrb_xmm_r8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRB, operand_count = 3, ops = {op_xmm(dst), op_gpr8(src), op_imm8(imm), {}} }, 966) } -inst_pinsrb_xmm_m8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRB, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 1), op_imm8(imm), {}} }, 966) } +inst_pinsrb_xmm_r8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRB, operand_count = 3, ops = {op_xmm(dst), op_gpr8(src), op_imm8(imm), {}} }, 978) } +inst_pinsrb_xmm_m8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRB, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 1), op_imm8(imm), {}} }, 978) } emit_pinsrb_xmm_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR8, imm: i8) { append(instructions, inst_pinsrb_xmm_r8_imm8(dst, src, imm)) } emit_pinsrb_xmm_m8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem8, imm: i8) { append(instructions, inst_pinsrb_xmm_m8_imm8(dst, src, imm)) } -inst_pinsrd_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRD, operand_count = 3, ops = {op_xmm(dst), op_gpr32(src), op_imm8(imm), {}} }, 967) } -inst_pinsrd_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 967) } +inst_pinsrd_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRD, operand_count = 3, ops = {op_xmm(dst), op_gpr32(src), op_imm8(imm), {}} }, 979) } +inst_pinsrd_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 979) } emit_pinsrd_xmm_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32, imm: i8) { append(instructions, inst_pinsrd_xmm_r32_imm8(dst, src, imm)) } emit_pinsrd_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_pinsrd_xmm_m32_imm8(dst, src, imm)) } -inst_pinsrq_xmm_r64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRQ, operand_count = 3, ops = {op_xmm(dst), op_gpr64(src), op_imm8(imm), {}} }, 968) } -inst_pinsrq_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 968) } +inst_pinsrq_xmm_r64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRQ, operand_count = 3, ops = {op_xmm(dst), op_gpr64(src), op_imm8(imm), {}} }, 980) } +inst_pinsrq_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PINSRQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 980) } emit_pinsrq_xmm_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR64, imm: i8) { append(instructions, inst_pinsrq_xmm_r64_imm8(dst, src, imm)) } emit_pinsrq_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64, imm: i8) { append(instructions, inst_pinsrq_xmm_m64_imm8(dst, src, imm)) } -inst_pmaxsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 969) } -inst_pmaxsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 969) } +inst_pmaxsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 981) } +inst_pmaxsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 981) } emit_pmaxsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxsb_xmm_xmm(dst, src)) } emit_pmaxsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxsb_xmm_m128(dst, src)) } -inst_pmaxsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 970) } -inst_pmaxsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 970) } +inst_pmaxsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 982) } +inst_pmaxsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 982) } emit_pmaxsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxsd_xmm_xmm(dst, src)) } emit_pmaxsd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxsd_xmm_m128(dst, src)) } -inst_pmaxuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 971) } -inst_pmaxuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 971) } +inst_pmaxuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 983) } +inst_pmaxuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 983) } emit_pmaxuw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxuw_xmm_xmm(dst, src)) } emit_pmaxuw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxuw_xmm_m128(dst, src)) } -inst_pmaxud_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 972) } -inst_pmaxud_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 972) } +inst_pmaxud_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 984) } +inst_pmaxud_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMAXUD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 984) } emit_pmaxud_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmaxud_xmm_xmm(dst, src)) } emit_pmaxud_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmaxud_xmm_m128(dst, src)) } -inst_pminsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 973) } -inst_pminsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 973) } +inst_pminsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 985) } +inst_pminsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 985) } emit_pminsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminsb_xmm_xmm(dst, src)) } emit_pminsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminsb_xmm_m128(dst, src)) } -inst_pminsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 974) } -inst_pminsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 974) } +inst_pminsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 986) } +inst_pminsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 986) } emit_pminsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminsd_xmm_xmm(dst, src)) } emit_pminsd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminsd_xmm_m128(dst, src)) } -inst_pminuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 975) } -inst_pminuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 975) } +inst_pminuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 987) } +inst_pminuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 987) } emit_pminuw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminuw_xmm_xmm(dst, src)) } emit_pminuw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminuw_xmm_m128(dst, src)) } -inst_pminud_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 976) } -inst_pminud_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 976) } +inst_pminud_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 988) } +inst_pminud_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMINUD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 988) } emit_pminud_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pminud_xmm_xmm(dst, src)) } emit_pminud_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pminud_xmm_m128(dst, src)) } -inst_pmovsxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 977) } -inst_pmovsxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 977) } +inst_pmovsxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 989) } +inst_pmovsxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 989) } emit_pmovsxbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxbw_xmm_xmm(dst, src)) } emit_pmovsxbw_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovsxbw_xmm_m64(dst, src)) } -inst_pmovsxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 978) } -inst_pmovsxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 978) } +inst_pmovsxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 990) } +inst_pmovsxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 990) } emit_pmovsxbd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxbd_xmm_xmm(dst, src)) } emit_pmovsxbd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovsxbd_xmm_m32(dst, src)) } -inst_pmovsxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 979) } -inst_pmovsxbq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 979) } +inst_pmovsxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 991) } +inst_pmovsxbq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 991) } emit_pmovsxbq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxbq_xmm_xmm(dst, src)) } emit_pmovsxbq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovsxbq_xmm_m32(dst, src)) } -inst_pmovsxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 980) } -inst_pmovsxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 980) } +inst_pmovsxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 992) } +inst_pmovsxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 992) } emit_pmovsxwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxwd_xmm_xmm(dst, src)) } emit_pmovsxwd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovsxwd_xmm_m64(dst, src)) } -inst_pmovsxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 981) } -inst_pmovsxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 981) } +inst_pmovsxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 993) } +inst_pmovsxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 993) } emit_pmovsxwq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxwq_xmm_xmm(dst, src)) } emit_pmovsxwq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovsxwq_xmm_m32(dst, src)) } -inst_pmovsxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 982) } -inst_pmovsxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 982) } +inst_pmovsxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 994) } +inst_pmovsxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 994) } emit_pmovsxdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovsxdq_xmm_xmm(dst, src)) } emit_pmovsxdq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovsxdq_xmm_m64(dst, src)) } -inst_pmovzxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 983) } -inst_pmovzxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 983) } +inst_pmovzxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 995) } +inst_pmovzxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 995) } emit_pmovzxbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxbw_xmm_xmm(dst, src)) } emit_pmovzxbw_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovzxbw_xmm_m64(dst, src)) } -inst_pmovzxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 984) } -inst_pmovzxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 984) } +inst_pmovzxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 996) } +inst_pmovzxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 996) } emit_pmovzxbd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxbd_xmm_xmm(dst, src)) } emit_pmovzxbd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovzxbd_xmm_m32(dst, src)) } -inst_pmovzxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 985) } -inst_pmovzxbq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 985) } +inst_pmovzxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 997) } +inst_pmovzxbq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 997) } emit_pmovzxbq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxbq_xmm_xmm(dst, src)) } emit_pmovzxbq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovzxbq_xmm_m32(dst, src)) } -inst_pmovzxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 986) } -inst_pmovzxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 986) } +inst_pmovzxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 998) } +inst_pmovzxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 998) } emit_pmovzxwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxwd_xmm_xmm(dst, src)) } emit_pmovzxwd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovzxwd_xmm_m64(dst, src)) } -inst_pmovzxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 987) } -inst_pmovzxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 987) } +inst_pmovzxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 999) } +inst_pmovzxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 999) } emit_pmovzxwq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxwq_xmm_xmm(dst, src)) } emit_pmovzxwq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_pmovzxwq_xmm_m32(dst, src)) } -inst_pmovzxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 988) } -inst_pmovzxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 988) } +inst_pmovzxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1000) } +inst_pmovzxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1000) } emit_pmovzxdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmovzxdq_xmm_xmm(dst, src)) } emit_pmovzxdq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_pmovzxdq_xmm_m64(dst, src)) } -inst_pmuldq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 989) } -inst_pmuldq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 989) } +inst_pmuldq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1001) } +inst_pmuldq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1001) } emit_pmuldq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmuldq_xmm_xmm(dst, src)) } emit_pmuldq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmuldq_xmm_m128(dst, src)) } -inst_pmulld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 990) } -inst_pmulld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 990) } +inst_pmulld_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1002) } +inst_pmulld_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PMULLD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1002) } emit_pmulld_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pmulld_xmm_xmm(dst, src)) } emit_pmulld_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pmulld_xmm_m128(dst, src)) } -inst_ptest_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PTEST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 991) } -inst_ptest_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PTEST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 991) } +inst_ptest_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PTEST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1003) } +inst_ptest_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PTEST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1003) } emit_ptest_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_ptest_xmm_xmm(dst, src)) } emit_ptest_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_ptest_xmm_m128(dst, src)) } -inst_roundps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 992) } -inst_roundps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 992) } +inst_roundps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1004) } +inst_roundps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1004) } emit_roundps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_roundps_xmm_xmm_imm8(dst, src, imm)) } emit_roundps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_roundps_xmm_m128_imm8(dst, src, imm)) } -inst_roundpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 993) } -inst_roundpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 993) } +inst_roundpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1005) } +inst_roundpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1005) } emit_roundpd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_roundpd_xmm_xmm_imm8(dst, src, imm)) } emit_roundpd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_roundpd_xmm_m128_imm8(dst, src, imm)) } -inst_roundss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 994) } -inst_roundss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 994) } +inst_roundss_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1006) } +inst_roundss_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 1006) } emit_roundss_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_roundss_xmm_xmm_imm8(dst, src, imm)) } emit_roundss_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32, imm: i8) { append(instructions, inst_roundss_xmm_m32_imm8(dst, src, imm)) } -inst_roundsd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 995) } -inst_roundsd_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 995) } +inst_roundsd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1007) } +inst_roundsd_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ROUNDSD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 1007) } emit_roundsd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_roundsd_xmm_xmm_imm8(dst, src, imm)) } emit_roundsd_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64, imm: i8) { append(instructions, inst_roundsd_xmm_m64_imm8(dst, src, imm)) } -inst_pcmpeqq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 996) } -inst_pcmpeqq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 996) } +inst_pcmpeqq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1008) } +inst_pcmpeqq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPEQQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1008) } emit_pcmpeqq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpeqq_xmm_xmm(dst, src)) } emit_pcmpeqq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpeqq_xmm_m128(dst, src)) } -inst_crc32_r32_r8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr8(src), {}, {}} }, 997) } -inst_crc32_r32_m8 :: #force_inline proc "contextless" (dst: GPR32, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 1), {}, {}} }, 997) } -inst_crc32_r32_r16 :: #force_inline proc "contextless" (dst: GPR32, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr16(src), {}, {}} }, 998) } -inst_crc32_r32_m16 :: #force_inline proc "contextless" (dst: GPR32, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 2), {}, {}} }, 998) } -inst_crc32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 999) } -inst_crc32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 999) } -inst_crc32_r64_r8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_gpr8(src), {}, {}} }, 1000) } -inst_crc32_r64_m8 :: #force_inline proc "contextless" (dst: GPR64, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 1), {}, {}} }, 1000) } -inst_crc32_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 1001) } -inst_crc32_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1001) } +inst_crc32_r32_r8 :: #force_inline proc "contextless" (dst: GPR32, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr8(src), {}, {}} }, 1009) } +inst_crc32_r32_m8 :: #force_inline proc "contextless" (dst: GPR32, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 1), {}, {}} }, 1009) } +inst_crc32_r32_r16 :: #force_inline proc "contextless" (dst: GPR32, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr16(src), {}, {}} }, 1010) } +inst_crc32_r32_m16 :: #force_inline proc "contextless" (dst: GPR32, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 2), {}, {}} }, 1010) } +inst_crc32_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 1011) } +inst_crc32_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 1011) } +inst_crc32_r64_r8 :: #force_inline proc "contextless" (dst: GPR64, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_gpr8(src), {}, {}} }, 1012) } +inst_crc32_r64_m8 :: #force_inline proc "contextless" (dst: GPR64, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 1), {}, {}} }, 1012) } +inst_crc32_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 1013) } +inst_crc32_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CRC32, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1013) } emit_crc32_r32_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR8) { append(instructions, inst_crc32_r32_r8(dst, src)) } emit_crc32_r32_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem8) { append(instructions, inst_crc32_r32_m8(dst, src)) } emit_crc32_r32_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR16) { append(instructions, inst_crc32_r32_r16(dst, src)) } @@ -3143,2317 +3175,2317 @@ emit_crc32_r64_r8 :: #force_inline proc(instructions: ^[dynami emit_crc32_r64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem8) { append(instructions, inst_crc32_r64_m8(dst, src)) } emit_crc32_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_crc32_r64_r64(dst, src)) } emit_crc32_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_crc32_r64_m64(dst, src)) } -inst_pcmpestri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1002) } -inst_pcmpestri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1002) } +inst_pcmpestri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1014) } +inst_pcmpestri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1014) } emit_pcmpestri_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pcmpestri_xmm_xmm_imm8(dst, src, imm)) } emit_pcmpestri_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pcmpestri_xmm_m128_imm8(dst, src, imm)) } -inst_pcmpestrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1003) } -inst_pcmpestrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1003) } +inst_pcmpestrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1015) } +inst_pcmpestrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1015) } emit_pcmpestrm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pcmpestrm_xmm_xmm_imm8(dst, src, imm)) } emit_pcmpestrm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pcmpestrm_xmm_m128_imm8(dst, src, imm)) } -inst_pcmpistri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1004) } -inst_pcmpistri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1004) } +inst_pcmpistri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1016) } +inst_pcmpistri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1016) } emit_pcmpistri_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pcmpistri_xmm_xmm_imm8(dst, src, imm)) } emit_pcmpistri_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pcmpistri_xmm_m128_imm8(dst, src, imm)) } -inst_pcmpistrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1005) } -inst_pcmpistrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1005) } +inst_pcmpistrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1017) } +inst_pcmpistrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1017) } emit_pcmpistrm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pcmpistrm_xmm_xmm_imm8(dst, src, imm)) } emit_pcmpistrm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pcmpistrm_xmm_m128_imm8(dst, src, imm)) } -inst_pcmpgtq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1006) } -inst_pcmpgtq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1006) } +inst_pcmpgtq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1018) } +inst_pcmpgtq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .PCMPGTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1018) } emit_pcmpgtq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_pcmpgtq_xmm_xmm(dst, src)) } emit_pcmpgtq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_pcmpgtq_xmm_m128(dst, src)) } -inst_pclmulqdq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCLMULQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1007) } -inst_pclmulqdq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCLMULQDQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1007) } +inst_pclmulqdq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCLMULQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1019) } +inst_pclmulqdq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .PCLMULQDQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1019) } emit_pclmulqdq_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_pclmulqdq_xmm_xmm_imm8(dst, src, imm)) } emit_pclmulqdq_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_pclmulqdq_xmm_m128_imm8(dst, src, imm)) } -inst_aesdec_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDEC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1008) } -inst_aesdec_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDEC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1008) } +inst_aesdec_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDEC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1020) } +inst_aesdec_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDEC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1020) } emit_aesdec_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_aesdec_xmm_xmm(dst, src)) } emit_aesdec_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_aesdec_xmm_m128(dst, src)) } -inst_aesdeclast_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDECLAST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1009) } -inst_aesdeclast_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDECLAST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1009) } +inst_aesdeclast_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDECLAST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1021) } +inst_aesdeclast_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESDECLAST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1021) } emit_aesdeclast_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_aesdeclast_xmm_xmm(dst, src)) } emit_aesdeclast_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_aesdeclast_xmm_m128(dst, src)) } -inst_aesenc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1010) } -inst_aesenc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1010) } +inst_aesenc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1022) } +inst_aesenc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1022) } emit_aesenc_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_aesenc_xmm_xmm(dst, src)) } emit_aesenc_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_aesenc_xmm_m128(dst, src)) } -inst_aesenclast_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENCLAST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1011) } -inst_aesenclast_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENCLAST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1011) } +inst_aesenclast_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENCLAST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1023) } +inst_aesenclast_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESENCLAST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1023) } emit_aesenclast_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_aesenclast_xmm_xmm(dst, src)) } emit_aesenclast_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_aesenclast_xmm_m128(dst, src)) } -inst_aesimc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESIMC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1012) } -inst_aesimc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESIMC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1012) } +inst_aesimc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .AESIMC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1024) } +inst_aesimc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .AESIMC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1024) } emit_aesimc_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_aesimc_xmm_xmm(dst, src)) } emit_aesimc_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_aesimc_xmm_m128(dst, src)) } -inst_aeskeygenassist_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .AESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1013) } -inst_aeskeygenassist_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .AESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1013) } +inst_aeskeygenassist_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .AESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1025) } +inst_aeskeygenassist_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .AESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1025) } emit_aeskeygenassist_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_aeskeygenassist_xmm_xmm_imm8(dst, src, imm)) } emit_aeskeygenassist_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_aeskeygenassist_xmm_m128_imm8(dst, src, imm)) } -inst_sha1msg1_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG1, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1014) } -inst_sha1msg1_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG1, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1014) } +inst_sha1msg1_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG1, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1026) } +inst_sha1msg1_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG1, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1026) } emit_sha1msg1_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha1msg1_xmm_xmm(dst, src)) } emit_sha1msg1_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha1msg1_xmm_m128(dst, src)) } -inst_sha1msg2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1015) } -inst_sha1msg2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1015) } +inst_sha1msg2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1027) } +inst_sha1msg2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1MSG2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1027) } emit_sha1msg2_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha1msg2_xmm_xmm(dst, src)) } emit_sha1msg2_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha1msg2_xmm_m128(dst, src)) } -inst_sha1nexte_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1NEXTE, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1016) } -inst_sha1nexte_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1NEXTE, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1016) } +inst_sha1nexte_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1NEXTE, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1028) } +inst_sha1nexte_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1NEXTE, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1028) } emit_sha1nexte_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha1nexte_xmm_xmm(dst, src)) } emit_sha1nexte_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha1nexte_xmm_m128(dst, src)) } -inst_sha1rnds4_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1RNDS4, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1017) } -inst_sha1rnds4_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1RNDS4, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1017) } +inst_sha1rnds4_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1RNDS4, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1029) } +inst_sha1rnds4_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA1RNDS4, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1029) } emit_sha1rnds4_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_sha1rnds4_xmm_xmm_imm8(dst, src, imm)) } emit_sha1rnds4_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_sha1rnds4_xmm_m128_imm8(dst, src, imm)) } -inst_sha256msg1_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG1, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1018) } -inst_sha256msg1_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG1, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1018) } +inst_sha256msg1_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG1, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1030) } +inst_sha256msg1_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG1, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1030) } emit_sha256msg1_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha256msg1_xmm_xmm(dst, src)) } emit_sha256msg1_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha256msg1_xmm_m128(dst, src)) } -inst_sha256msg2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1019) } -inst_sha256msg2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1019) } +inst_sha256msg2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1031) } +inst_sha256msg2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256MSG2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1031) } emit_sha256msg2_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha256msg2_xmm_xmm(dst, src)) } emit_sha256msg2_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha256msg2_xmm_m128(dst, src)) } -inst_sha256rnds2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256RNDS2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1020) } -inst_sha256rnds2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256RNDS2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1020) } +inst_sha256rnds2_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256RNDS2, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1032) } +inst_sha256rnds2_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .SHA256RNDS2, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1032) } emit_sha256rnds2_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_sha256rnds2_xmm_xmm(dst, src)) } emit_sha256rnds2_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_sha256rnds2_xmm_m128(dst, src)) } -inst_vaddps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1021) } -inst_vaddps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1021) } -inst_vaddps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1022) } -inst_vaddps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1022) } +inst_vaddps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1033) } +inst_vaddps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1033) } +inst_vaddps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1034) } +inst_vaddps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1034) } emit_vaddps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddps_xmm_xmm_xmm(dst, src, src2)) } emit_vaddps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaddps_xmm_xmm_m128(dst, src, src2)) } emit_vaddps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vaddps_ymm_ymm_ymm(dst, src, src2)) } emit_vaddps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vaddps_ymm_ymm_m256(dst, src, src2)) } -inst_vaddpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1023) } -inst_vaddpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1023) } -inst_vaddpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1024) } -inst_vaddpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1024) } +inst_vaddpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1035) } +inst_vaddpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1035) } +inst_vaddpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1036) } +inst_vaddpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1036) } emit_vaddpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddpd_xmm_xmm_xmm(dst, src, src2)) } emit_vaddpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaddpd_xmm_xmm_m128(dst, src, src2)) } emit_vaddpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vaddpd_ymm_ymm_ymm(dst, src, src2)) } emit_vaddpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vaddpd_ymm_ymm_m256(dst, src, src2)) } -inst_vaddss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1025) } -inst_vaddss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1025) } +inst_vaddss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1037) } +inst_vaddss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1037) } emit_vaddss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddss_xmm_xmm_xmm(dst, src, src2)) } emit_vaddss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vaddss_xmm_xmm_m32(dst, src, src2)) } -inst_vaddsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1026) } -inst_vaddsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1026) } +inst_vaddsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1038) } +inst_vaddsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1038) } emit_vaddsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddsd_xmm_xmm_xmm(dst, src, src2)) } emit_vaddsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vaddsd_xmm_xmm_m64(dst, src, src2)) } -inst_vsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1027) } -inst_vsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1027) } -inst_vsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1028) } -inst_vsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1028) } +inst_vsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1039) } +inst_vsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1039) } +inst_vsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1040) } +inst_vsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1040) } emit_vsubps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsubps_xmm_xmm_xmm(dst, src, src2)) } emit_vsubps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vsubps_xmm_xmm_m128(dst, src, src2)) } emit_vsubps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vsubps_ymm_ymm_ymm(dst, src, src2)) } emit_vsubps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vsubps_ymm_ymm_m256(dst, src, src2)) } -inst_vsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1029) } -inst_vsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1029) } -inst_vsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1030) } -inst_vsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1030) } +inst_vsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1041) } +inst_vsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1041) } +inst_vsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1042) } +inst_vsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1042) } emit_vsubpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsubpd_xmm_xmm_xmm(dst, src, src2)) } emit_vsubpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vsubpd_xmm_xmm_m128(dst, src, src2)) } emit_vsubpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vsubpd_ymm_ymm_ymm(dst, src, src2)) } emit_vsubpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vsubpd_ymm_ymm_m256(dst, src, src2)) } -inst_vsubss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1031) } -inst_vsubss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1031) } +inst_vsubss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1043) } +inst_vsubss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1043) } emit_vsubss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsubss_xmm_xmm_xmm(dst, src, src2)) } emit_vsubss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vsubss_xmm_xmm_m32(dst, src, src2)) } -inst_vsubsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1032) } -inst_vsubsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1032) } +inst_vsubsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1044) } +inst_vsubsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSUBSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1044) } emit_vsubsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsubsd_xmm_xmm_xmm(dst, src, src2)) } emit_vsubsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vsubsd_xmm_xmm_m64(dst, src, src2)) } -inst_vmulps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1033) } -inst_vmulps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1033) } -inst_vmulps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1034) } -inst_vmulps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1034) } +inst_vmulps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1045) } +inst_vmulps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1045) } +inst_vmulps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1046) } +inst_vmulps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1046) } emit_vmulps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmulps_xmm_xmm_xmm(dst, src, src2)) } emit_vmulps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmulps_xmm_xmm_m128(dst, src, src2)) } emit_vmulps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vmulps_ymm_ymm_ymm(dst, src, src2)) } emit_vmulps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmulps_ymm_ymm_m256(dst, src, src2)) } -inst_vmulpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1035) } -inst_vmulpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1035) } -inst_vmulpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1036) } -inst_vmulpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1036) } +inst_vmulpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1047) } +inst_vmulpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1047) } +inst_vmulpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1048) } +inst_vmulpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1048) } emit_vmulpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmulpd_xmm_xmm_xmm(dst, src, src2)) } emit_vmulpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmulpd_xmm_xmm_m128(dst, src, src2)) } emit_vmulpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vmulpd_ymm_ymm_ymm(dst, src, src2)) } emit_vmulpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmulpd_ymm_ymm_m256(dst, src, src2)) } -inst_vmulss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1037) } -inst_vmulss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1037) } +inst_vmulss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1049) } +inst_vmulss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1049) } emit_vmulss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmulss_xmm_xmm_xmm(dst, src, src2)) } emit_vmulss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vmulss_xmm_xmm_m32(dst, src, src2)) } -inst_vmulsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1038) } -inst_vmulsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1038) } +inst_vmulsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1050) } +inst_vmulsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMULSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1050) } emit_vmulsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmulsd_xmm_xmm_xmm(dst, src, src2)) } emit_vmulsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmulsd_xmm_xmm_m64(dst, src, src2)) } -inst_vdivps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1039) } -inst_vdivps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1039) } -inst_vdivps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1040) } -inst_vdivps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1040) } +inst_vdivps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1051) } +inst_vdivps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1051) } +inst_vdivps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1052) } +inst_vdivps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1052) } emit_vdivps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vdivps_xmm_xmm_xmm(dst, src, src2)) } emit_vdivps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vdivps_xmm_xmm_m128(dst, src, src2)) } emit_vdivps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vdivps_ymm_ymm_ymm(dst, src, src2)) } emit_vdivps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vdivps_ymm_ymm_m256(dst, src, src2)) } -inst_vdivpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1041) } -inst_vdivpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1041) } -inst_vdivpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1042) } -inst_vdivpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1042) } +inst_vdivpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1053) } +inst_vdivpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1053) } +inst_vdivpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1054) } +inst_vdivpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1054) } emit_vdivpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vdivpd_xmm_xmm_xmm(dst, src, src2)) } emit_vdivpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vdivpd_xmm_xmm_m128(dst, src, src2)) } emit_vdivpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vdivpd_ymm_ymm_ymm(dst, src, src2)) } emit_vdivpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vdivpd_ymm_ymm_m256(dst, src, src2)) } -inst_vdivss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1043) } -inst_vdivss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1043) } +inst_vdivss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1055) } +inst_vdivss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1055) } emit_vdivss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vdivss_xmm_xmm_xmm(dst, src, src2)) } emit_vdivss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vdivss_xmm_xmm_m32(dst, src, src2)) } -inst_vdivsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1044) } -inst_vdivsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1044) } +inst_vdivsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1056) } +inst_vdivsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VDIVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1056) } emit_vdivsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vdivsd_xmm_xmm_xmm(dst, src, src2)) } emit_vdivsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vdivsd_xmm_xmm_m64(dst, src, src2)) } -inst_vsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1045) } -inst_vsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1045) } -inst_vsqrtps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1046) } -inst_vsqrtps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1046) } +inst_vsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1057) } +inst_vsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1057) } +inst_vsqrtps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1058) } +inst_vsqrtps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1058) } emit_vsqrtps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vsqrtps_xmm_xmm(dst, src)) } emit_vsqrtps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vsqrtps_xmm_m128(dst, src)) } emit_vsqrtps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vsqrtps_ymm_ymm(dst, src)) } emit_vsqrtps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vsqrtps_ymm_m256(dst, src)) } -inst_vsqrtpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1047) } -inst_vsqrtpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1047) } -inst_vsqrtpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1048) } -inst_vsqrtpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1048) } +inst_vsqrtpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1059) } +inst_vsqrtpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1059) } +inst_vsqrtpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1060) } +inst_vsqrtpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1060) } emit_vsqrtpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vsqrtpd_xmm_xmm(dst, src)) } emit_vsqrtpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vsqrtpd_xmm_m128(dst, src)) } emit_vsqrtpd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vsqrtpd_ymm_ymm(dst, src)) } emit_vsqrtpd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vsqrtpd_ymm_m256(dst, src)) } -inst_vsqrtss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1049) } -inst_vsqrtss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1049) } +inst_vsqrtss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1061) } +inst_vsqrtss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1061) } emit_vsqrtss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsqrtss_xmm_xmm_xmm(dst, src, src2)) } emit_vsqrtss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vsqrtss_xmm_xmm_m32(dst, src, src2)) } -inst_vsqrtsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1050) } -inst_vsqrtsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1050) } +inst_vsqrtsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1062) } +inst_vsqrtsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSQRTSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1062) } emit_vsqrtsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vsqrtsd_xmm_xmm_xmm(dst, src, src2)) } emit_vsqrtsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vsqrtsd_xmm_xmm_m64(dst, src, src2)) } -inst_vrcpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1051) } -inst_vrcpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1051) } -inst_vrcpps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1052) } -inst_vrcpps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1052) } +inst_vrcpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1063) } +inst_vrcpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1063) } +inst_vrcpps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1064) } +inst_vrcpps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1064) } emit_vrcpps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrcpps_xmm_xmm(dst, src)) } emit_vrcpps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrcpps_xmm_m128(dst, src)) } emit_vrcpps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrcpps_ymm_ymm(dst, src)) } emit_vrcpps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrcpps_ymm_m256(dst, src)) } -inst_vrcpss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1053) } -inst_vrcpss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1053) } +inst_vrcpss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1065) } +inst_vrcpss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1065) } emit_vrcpss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrcpss_xmm_xmm_xmm(dst, src, src2)) } emit_vrcpss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vrcpss_xmm_xmm_m32(dst, src, src2)) } -inst_vrsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1054) } -inst_vrsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1054) } -inst_vrsqrtps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1055) } -inst_vrsqrtps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1055) } +inst_vrsqrtps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1066) } +inst_vrsqrtps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1066) } +inst_vrsqrtps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1067) } +inst_vrsqrtps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1067) } emit_vrsqrtps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrsqrtps_xmm_xmm(dst, src)) } emit_vrsqrtps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrsqrtps_xmm_m128(dst, src)) } emit_vrsqrtps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrsqrtps_ymm_ymm(dst, src)) } emit_vrsqrtps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrsqrtps_ymm_m256(dst, src)) } -inst_vrsqrtss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1056) } -inst_vrsqrtss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1056) } +inst_vrsqrtss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1068) } +inst_vrsqrtss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRTSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1068) } emit_vrsqrtss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrsqrtss_xmm_xmm_xmm(dst, src, src2)) } emit_vrsqrtss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vrsqrtss_xmm_xmm_m32(dst, src, src2)) } -inst_vmaxps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1057) } -inst_vmaxps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1057) } -inst_vmaxps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1058) } -inst_vmaxps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1058) } +inst_vmaxps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1069) } +inst_vmaxps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1069) } +inst_vmaxps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1070) } +inst_vmaxps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1070) } emit_vmaxps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmaxps_xmm_xmm_xmm(dst, src, src2)) } emit_vmaxps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmaxps_xmm_xmm_m128(dst, src, src2)) } emit_vmaxps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vmaxps_ymm_ymm_ymm(dst, src, src2)) } emit_vmaxps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmaxps_ymm_ymm_m256(dst, src, src2)) } -inst_vmaxpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1059) } -inst_vmaxpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1059) } -inst_vmaxpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1060) } -inst_vmaxpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1060) } +inst_vmaxpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1071) } +inst_vmaxpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1071) } +inst_vmaxpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1072) } +inst_vmaxpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1072) } emit_vmaxpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmaxpd_xmm_xmm_xmm(dst, src, src2)) } emit_vmaxpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmaxpd_xmm_xmm_m128(dst, src, src2)) } emit_vmaxpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vmaxpd_ymm_ymm_ymm(dst, src, src2)) } emit_vmaxpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmaxpd_ymm_ymm_m256(dst, src, src2)) } -inst_vmaxss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1061) } -inst_vmaxss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1061) } +inst_vmaxss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1073) } +inst_vmaxss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1073) } emit_vmaxss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmaxss_xmm_xmm_xmm(dst, src, src2)) } emit_vmaxss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vmaxss_xmm_xmm_m32(dst, src, src2)) } -inst_vmaxsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1062) } -inst_vmaxsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1062) } +inst_vmaxsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1074) } +inst_vmaxsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1074) } emit_vmaxsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmaxsd_xmm_xmm_xmm(dst, src, src2)) } emit_vmaxsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmaxsd_xmm_xmm_m64(dst, src, src2)) } -inst_vminps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1063) } -inst_vminps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1063) } -inst_vminps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1064) } -inst_vminps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1064) } +inst_vminps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1075) } +inst_vminps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1075) } +inst_vminps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1076) } +inst_vminps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1076) } emit_vminps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vminps_xmm_xmm_xmm(dst, src, src2)) } emit_vminps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vminps_xmm_xmm_m128(dst, src, src2)) } emit_vminps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vminps_ymm_ymm_ymm(dst, src, src2)) } emit_vminps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vminps_ymm_ymm_m256(dst, src, src2)) } -inst_vminpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1065) } -inst_vminpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1065) } -inst_vminpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1066) } -inst_vminpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1066) } +inst_vminpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1077) } +inst_vminpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1077) } +inst_vminpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1078) } +inst_vminpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1078) } emit_vminpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vminpd_xmm_xmm_xmm(dst, src, src2)) } emit_vminpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vminpd_xmm_xmm_m128(dst, src, src2)) } emit_vminpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vminpd_ymm_ymm_ymm(dst, src, src2)) } emit_vminpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vminpd_ymm_ymm_m256(dst, src, src2)) } -inst_vminss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1067) } -inst_vminss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1067) } +inst_vminss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1079) } +inst_vminss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1079) } emit_vminss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vminss_xmm_xmm_xmm(dst, src, src2)) } emit_vminss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vminss_xmm_xmm_m32(dst, src, src2)) } -inst_vminsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1068) } -inst_vminsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1068) } +inst_vminsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1080) } +inst_vminsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1080) } emit_vminsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vminsd_xmm_xmm_xmm(dst, src, src2)) } emit_vminsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vminsd_xmm_xmm_m64(dst, src, src2)) } -inst_vandps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1069) } -inst_vandps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1069) } -inst_vandps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1070) } -inst_vandps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1070) } +inst_vandps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1081) } +inst_vandps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1081) } +inst_vandps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1082) } +inst_vandps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1082) } emit_vandps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vandps_xmm_xmm_xmm(dst, src, src2)) } emit_vandps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vandps_xmm_xmm_m128(dst, src, src2)) } emit_vandps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vandps_ymm_ymm_ymm(dst, src, src2)) } emit_vandps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vandps_ymm_ymm_m256(dst, src, src2)) } -inst_vandpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1071) } -inst_vandpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1071) } -inst_vandpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1072) } -inst_vandpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1072) } +inst_vandpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1083) } +inst_vandpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1083) } +inst_vandpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1084) } +inst_vandpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1084) } emit_vandpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vandpd_xmm_xmm_xmm(dst, src, src2)) } emit_vandpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vandpd_xmm_xmm_m128(dst, src, src2)) } emit_vandpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vandpd_ymm_ymm_ymm(dst, src, src2)) } emit_vandpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vandpd_ymm_ymm_m256(dst, src, src2)) } -inst_vandnps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1073) } -inst_vandnps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1073) } -inst_vandnps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1074) } -inst_vandnps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1074) } +inst_vandnps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1085) } +inst_vandnps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1085) } +inst_vandnps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1086) } +inst_vandnps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1086) } emit_vandnps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vandnps_xmm_xmm_xmm(dst, src, src2)) } emit_vandnps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vandnps_xmm_xmm_m128(dst, src, src2)) } emit_vandnps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vandnps_ymm_ymm_ymm(dst, src, src2)) } emit_vandnps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vandnps_ymm_ymm_m256(dst, src, src2)) } -inst_vandnpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1075) } -inst_vandnpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1075) } -inst_vandnpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1076) } -inst_vandnpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1076) } +inst_vandnpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1087) } +inst_vandnpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1087) } +inst_vandnpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1088) } +inst_vandnpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VANDNPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1088) } emit_vandnpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vandnpd_xmm_xmm_xmm(dst, src, src2)) } emit_vandnpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vandnpd_xmm_xmm_m128(dst, src, src2)) } emit_vandnpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vandnpd_ymm_ymm_ymm(dst, src, src2)) } emit_vandnpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vandnpd_ymm_ymm_m256(dst, src, src2)) } -inst_vorps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1077) } -inst_vorps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1077) } -inst_vorps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1078) } -inst_vorps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1078) } +inst_vorps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1089) } +inst_vorps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1089) } +inst_vorps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1090) } +inst_vorps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1090) } emit_vorps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vorps_xmm_xmm_xmm(dst, src, src2)) } emit_vorps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vorps_xmm_xmm_m128(dst, src, src2)) } emit_vorps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vorps_ymm_ymm_ymm(dst, src, src2)) } emit_vorps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vorps_ymm_ymm_m256(dst, src, src2)) } -inst_vorpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1079) } -inst_vorpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1079) } -inst_vorpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1080) } -inst_vorpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1080) } +inst_vorpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1091) } +inst_vorpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1091) } +inst_vorpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1092) } +inst_vorpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1092) } emit_vorpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vorpd_xmm_xmm_xmm(dst, src, src2)) } emit_vorpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vorpd_xmm_xmm_m128(dst, src, src2)) } emit_vorpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vorpd_ymm_ymm_ymm(dst, src, src2)) } emit_vorpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vorpd_ymm_ymm_m256(dst, src, src2)) } -inst_vxorps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1081) } -inst_vxorps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1081) } -inst_vxorps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1082) } -inst_vxorps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1082) } +inst_vxorps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1093) } +inst_vxorps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1093) } +inst_vxorps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1094) } +inst_vxorps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1094) } emit_vxorps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vxorps_xmm_xmm_xmm(dst, src, src2)) } emit_vxorps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vxorps_xmm_xmm_m128(dst, src, src2)) } emit_vxorps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vxorps_ymm_ymm_ymm(dst, src, src2)) } emit_vxorps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vxorps_ymm_ymm_m256(dst, src, src2)) } -inst_vxorpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1083) } -inst_vxorpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1083) } -inst_vxorpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1084) } -inst_vxorpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1084) } +inst_vxorpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1095) } +inst_vxorpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1095) } +inst_vxorpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1096) } +inst_vxorpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VXORPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1096) } emit_vxorpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vxorpd_xmm_xmm_xmm(dst, src, src2)) } emit_vxorpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vxorpd_xmm_xmm_m128(dst, src, src2)) } emit_vxorpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vxorpd_ymm_ymm_ymm(dst, src, src2)) } emit_vxorpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vxorpd_ymm_ymm_m256(dst, src, src2)) } -inst_vcmpps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1085) } -inst_vcmpps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1085) } -inst_vcmpps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1086) } -inst_vcmpps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1086) } +inst_vcmpps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1097) } +inst_vcmpps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1097) } +inst_vcmpps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1098) } +inst_vcmpps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1098) } emit_vcmpps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vcmpps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vcmpps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vcmpps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vcmpps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vcmpps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vcmpps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vcmpps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vcmppd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1087) } -inst_vcmppd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1087) } -inst_vcmppd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1088) } -inst_vcmppd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1088) } +inst_vcmppd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1099) } +inst_vcmppd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1099) } +inst_vcmppd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1100) } +inst_vcmppd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1100) } emit_vcmppd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vcmppd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vcmppd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vcmppd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vcmppd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vcmppd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vcmppd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vcmppd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vcmpss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1089) } -inst_vcmpss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1089) } +inst_vcmpss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1101) } +inst_vcmpss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1101) } emit_vcmpss_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vcmpss_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vcmpss_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vcmpss_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vcmpsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1090) } -inst_vcmpsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1090) } +inst_vcmpsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1102) } +inst_vcmpsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCMPSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1102) } emit_vcmpsd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vcmpsd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vcmpsd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vcmpsd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vcomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1091) } -inst_vcomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1091) } +inst_vcomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1103) } +inst_vcomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1103) } emit_vcomiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcomiss_xmm_xmm(dst, src)) } emit_vcomiss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vcomiss_xmm_m32(dst, src)) } -inst_vcomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1092) } -inst_vcomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1092) } +inst_vcomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1104) } +inst_vcomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1104) } emit_vcomisd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcomisd_xmm_xmm(dst, src)) } emit_vcomisd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vcomisd_xmm_m64(dst, src)) } -inst_vucomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1093) } -inst_vucomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1093) } +inst_vucomiss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1105) } +inst_vucomiss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1105) } emit_vucomiss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vucomiss_xmm_xmm(dst, src)) } emit_vucomiss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vucomiss_xmm_m32(dst, src)) } -inst_vucomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1094) } -inst_vucomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1094) } +inst_vucomisd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1106) } +inst_vucomisd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VUCOMISD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1106) } emit_vucomisd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vucomisd_xmm_xmm(dst, src)) } emit_vucomisd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vucomisd_xmm_m64(dst, src)) } -inst_vshufps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1095) } -inst_vshufps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1095) } -inst_vshufps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1096) } -inst_vshufps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1096) } +inst_vshufps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1107) } +inst_vshufps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1107) } +inst_vshufps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1108) } +inst_vshufps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1108) } emit_vshufps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vshufps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vshufps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vshufps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vshufps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vshufps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vshufps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vshufps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vshufpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1097) } -inst_vshufpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1097) } -inst_vshufpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1098) } -inst_vshufpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1098) } +inst_vshufpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1109) } +inst_vshufpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1109) } +inst_vshufpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1110) } +inst_vshufpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VSHUFPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1110) } emit_vshufpd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vshufpd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vshufpd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vshufpd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vshufpd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vshufpd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vshufpd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vshufpd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vunpcklps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1099) } -inst_vunpcklps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1099) } -inst_vunpcklps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1100) } -inst_vunpcklps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1100) } +inst_vunpcklps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1111) } +inst_vunpcklps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1111) } +inst_vunpcklps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1112) } +inst_vunpcklps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1112) } emit_vunpcklps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vunpcklps_xmm_xmm_xmm(dst, src, src2)) } emit_vunpcklps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vunpcklps_xmm_xmm_m128(dst, src, src2)) } emit_vunpcklps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vunpcklps_ymm_ymm_ymm(dst, src, src2)) } emit_vunpcklps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vunpcklps_ymm_ymm_m256(dst, src, src2)) } -inst_vunpckhps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1101) } -inst_vunpckhps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1101) } -inst_vunpckhps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1102) } -inst_vunpckhps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1102) } +inst_vunpckhps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1113) } +inst_vunpckhps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1113) } +inst_vunpckhps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1114) } +inst_vunpckhps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1114) } emit_vunpckhps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vunpckhps_xmm_xmm_xmm(dst, src, src2)) } emit_vunpckhps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vunpckhps_xmm_xmm_m128(dst, src, src2)) } emit_vunpckhps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vunpckhps_ymm_ymm_ymm(dst, src, src2)) } emit_vunpckhps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vunpckhps_ymm_ymm_m256(dst, src, src2)) } -inst_vunpcklpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1103) } -inst_vunpcklpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1103) } -inst_vunpcklpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1104) } -inst_vunpcklpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1104) } +inst_vunpcklpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1115) } +inst_vunpcklpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1115) } +inst_vunpcklpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1116) } +inst_vunpcklpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKLPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1116) } emit_vunpcklpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vunpcklpd_xmm_xmm_xmm(dst, src, src2)) } emit_vunpcklpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vunpcklpd_xmm_xmm_m128(dst, src, src2)) } emit_vunpcklpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vunpcklpd_ymm_ymm_ymm(dst, src, src2)) } emit_vunpcklpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vunpcklpd_ymm_ymm_m256(dst, src, src2)) } -inst_vunpckhpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1105) } -inst_vunpckhpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1105) } -inst_vunpckhpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1106) } -inst_vunpckhpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1106) } +inst_vunpckhpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1117) } +inst_vunpckhpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1117) } +inst_vunpckhpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1118) } +inst_vunpckhpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VUNPCKHPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1118) } emit_vunpckhpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vunpckhpd_xmm_xmm_xmm(dst, src, src2)) } emit_vunpckhpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vunpckhpd_xmm_xmm_m128(dst, src, src2)) } emit_vunpckhpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vunpckhpd_ymm_ymm_ymm(dst, src, src2)) } emit_vunpckhpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vunpckhpd_ymm_ymm_m256(dst, src, src2)) } -inst_vblendps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1107) } -inst_vblendps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1107) } -inst_vblendps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1108) } -inst_vblendps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1108) } +inst_vblendps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1119) } +inst_vblendps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1119) } +inst_vblendps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1120) } +inst_vblendps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1120) } emit_vblendps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vblendps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vblendps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vblendps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vblendps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vblendps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vblendps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vblendps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vblendpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1109) } -inst_vblendpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1109) } -inst_vblendpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1110) } -inst_vblendpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1110) } +inst_vblendpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1121) } +inst_vblendpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1121) } +inst_vblendpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1122) } +inst_vblendpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1122) } emit_vblendpd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vblendpd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vblendpd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vblendpd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vblendpd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vblendpd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vblendpd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vblendpd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vblendvps_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1111) } -inst_vblendvps_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1111) } -inst_vblendvps_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1112) } -inst_vblendvps_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1112) } +inst_vblendvps_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1123) } +inst_vblendvps_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1123) } +inst_vblendvps_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1124) } +inst_vblendvps_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1124) } emit_vblendvps_xmm_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, src3: XMM) { append(instructions, inst_vblendvps_xmm_xmm_xmm_xmm(dst, src, src2, src3)) } emit_vblendvps_xmm_xmm_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, src3: XMM) { append(instructions, inst_vblendvps_xmm_xmm_m128_xmm(dst, src, src2, src3)) } emit_vblendvps_ymm_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, src3: YMM) { append(instructions, inst_vblendvps_ymm_ymm_ymm_ymm(dst, src, src2, src3)) } emit_vblendvps_ymm_ymm_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, src3: YMM) { append(instructions, inst_vblendvps_ymm_ymm_m256_ymm(dst, src, src2, src3)) } -inst_vblendvpd_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1113) } -inst_vblendvpd_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1113) } -inst_vblendvpd_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1114) } -inst_vblendvpd_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1114) } +inst_vblendvpd_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1125) } +inst_vblendvpd_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1125) } +inst_vblendvpd_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1126) } +inst_vblendvpd_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDVPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1126) } emit_vblendvpd_xmm_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, src3: XMM) { append(instructions, inst_vblendvpd_xmm_xmm_xmm_xmm(dst, src, src2, src3)) } emit_vblendvpd_xmm_xmm_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, src3: XMM) { append(instructions, inst_vblendvpd_xmm_xmm_m128_xmm(dst, src, src2, src3)) } emit_vblendvpd_ymm_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, src3: YMM) { append(instructions, inst_vblendvpd_ymm_ymm_ymm_ymm(dst, src, src2, src3)) } emit_vblendvpd_ymm_ymm_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, src3: YMM) { append(instructions, inst_vblendvpd_ymm_ymm_m256_ymm(dst, src, src2, src3)) } -inst_vdpps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1115) } -inst_vdpps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1115) } -inst_vdpps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1116) } -inst_vdpps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1116) } +inst_vdpps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1127) } +inst_vdpps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1127) } +inst_vdpps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1128) } +inst_vdpps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1128) } emit_vdpps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vdpps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vdpps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vdpps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vdpps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vdpps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vdpps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vdpps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vdppd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1117) } -inst_vdppd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1117) } +inst_vdppd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1129) } +inst_vdppd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDPPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1129) } emit_vdppd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vdppd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vdppd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vdppd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } -inst_vroundps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1118) } -inst_vroundps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1118) } -inst_vroundps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1119) } -inst_vroundps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1119) } +inst_vroundps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1130) } +inst_vroundps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1130) } +inst_vroundps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1131) } +inst_vroundps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1131) } emit_vroundps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vroundps_xmm_xmm_imm8(dst, src, imm)) } emit_vroundps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vroundps_xmm_m128_imm8(dst, src, imm)) } emit_vroundps_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vroundps_ymm_ymm_imm8(dst, src, imm)) } emit_vroundps_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vroundps_ymm_m256_imm8(dst, src, imm)) } -inst_vroundpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1120) } -inst_vroundpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1120) } -inst_vroundpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1121) } -inst_vroundpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1121) } +inst_vroundpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1132) } +inst_vroundpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1132) } +inst_vroundpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1133) } +inst_vroundpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1133) } emit_vroundpd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vroundpd_xmm_xmm_imm8(dst, src, imm)) } emit_vroundpd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vroundpd_xmm_m128_imm8(dst, src, imm)) } emit_vroundpd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vroundpd_ymm_ymm_imm8(dst, src, imm)) } emit_vroundpd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vroundpd_ymm_m256_imm8(dst, src, imm)) } -inst_vroundss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1122) } -inst_vroundss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1122) } +inst_vroundss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1134) } +inst_vroundss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1134) } emit_vroundss_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vroundss_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vroundss_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vroundss_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vroundsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1123) } -inst_vroundsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1123) } +inst_vroundsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1135) } +inst_vroundsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VROUNDSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1135) } emit_vroundsd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vroundsd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vroundsd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vroundsd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vextractps_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTPS, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1124) } -inst_vextractps_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTPS, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 1124) } +inst_vextractps_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTPS, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1136) } +inst_vextractps_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTPS, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 1136) } emit_vextractps_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_vextractps_r32_xmm_imm8(dst, src, imm)) } emit_vextractps_m32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM, imm: i8) { append(instructions, inst_vextractps_m32_xmm_imm8(dst, src, imm)) } -inst_vinsertps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1125) } -inst_vinsertps_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1125) } +inst_vinsertps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1137) } +inst_vinsertps_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1137) } emit_vinsertps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vinsertps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vinsertps_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vinsertps_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vmovaps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1126) } -inst_vmovaps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1126) } -inst_vmovaps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1127) } -inst_vmovaps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1128) } -inst_vmovaps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1128) } -inst_vmovaps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1129) } +inst_vmovaps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1138) } +inst_vmovaps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1138) } +inst_vmovaps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1139) } +inst_vmovaps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1140) } +inst_vmovaps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1140) } +inst_vmovaps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1141) } emit_vmovaps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovaps_xmm_xmm(dst, src)) } emit_vmovaps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovaps_xmm_m128(dst, src)) } emit_vmovaps_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovaps_m128_xmm(dst, src)) } emit_vmovaps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovaps_ymm_ymm(dst, src)) } emit_vmovaps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovaps_ymm_m256(dst, src)) } emit_vmovaps_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovaps_m256_ymm(dst, src)) } -inst_vmovups_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1130) } -inst_vmovups_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1130) } -inst_vmovups_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1131) } -inst_vmovups_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1132) } -inst_vmovups_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1132) } -inst_vmovups_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1133) } +inst_vmovups_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1142) } +inst_vmovups_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1142) } +inst_vmovups_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1143) } +inst_vmovups_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1144) } +inst_vmovups_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1144) } +inst_vmovups_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1145) } emit_vmovups_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovups_xmm_xmm(dst, src)) } emit_vmovups_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovups_xmm_m128(dst, src)) } emit_vmovups_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovups_m128_xmm(dst, src)) } emit_vmovups_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovups_ymm_ymm(dst, src)) } emit_vmovups_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovups_ymm_m256(dst, src)) } emit_vmovups_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovups_m256_ymm(dst, src)) } -inst_vmovapd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1134) } -inst_vmovapd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1134) } -inst_vmovapd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1135) } -inst_vmovapd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1136) } -inst_vmovapd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1136) } -inst_vmovapd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1137) } +inst_vmovapd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1146) } +inst_vmovapd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1146) } +inst_vmovapd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1147) } +inst_vmovapd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1148) } +inst_vmovapd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1148) } +inst_vmovapd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVAPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1149) } emit_vmovapd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovapd_xmm_xmm(dst, src)) } emit_vmovapd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovapd_xmm_m128(dst, src)) } emit_vmovapd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovapd_m128_xmm(dst, src)) } emit_vmovapd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovapd_ymm_ymm(dst, src)) } emit_vmovapd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovapd_ymm_m256(dst, src)) } emit_vmovapd_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovapd_m256_ymm(dst, src)) } -inst_vmovupd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1138) } -inst_vmovupd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1138) } -inst_vmovupd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1139) } -inst_vmovupd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1140) } -inst_vmovupd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1140) } -inst_vmovupd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1141) } +inst_vmovupd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1150) } +inst_vmovupd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1150) } +inst_vmovupd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1151) } +inst_vmovupd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1152) } +inst_vmovupd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1152) } +inst_vmovupd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVUPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1153) } emit_vmovupd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovupd_xmm_xmm(dst, src)) } emit_vmovupd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovupd_xmm_m128(dst, src)) } emit_vmovupd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovupd_m128_xmm(dst, src)) } emit_vmovupd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovupd_ymm_ymm(dst, src)) } emit_vmovupd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovupd_ymm_m256(dst, src)) } emit_vmovupd_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovupd_m256_ymm(dst, src)) } -inst_vmovss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1142) } -inst_vmovss_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1143) } -inst_vmovss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1144) } +inst_vmovss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1154) } +inst_vmovss_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1155) } +inst_vmovss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1156) } emit_vmovss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vmovss_xmm_m32(dst, src)) } emit_vmovss_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vmovss_m32_xmm(dst, src)) } emit_vmovss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmovss_xmm_xmm_xmm(dst, src, src2)) } -inst_vmovsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1145) } -inst_vmovsd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1146) } -inst_vmovsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1147) } +inst_vmovsd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1157) } +inst_vmovsd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1158) } +inst_vmovsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1159) } emit_vmovsd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vmovsd_xmm_m64(dst, src)) } emit_vmovsd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovsd_m64_xmm(dst, src)) } emit_vmovsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmovsd_xmm_xmm_xmm(dst, src, src2)) } -inst_vmovdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1148) } -inst_vmovdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1148) } -inst_vmovdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1149) } -inst_vmovdqa_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1150) } -inst_vmovdqa_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1150) } -inst_vmovdqa_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1151) } +inst_vmovdqa_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1160) } +inst_vmovdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1160) } +inst_vmovdqa_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1161) } +inst_vmovdqa_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1162) } +inst_vmovdqa_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1162) } +inst_vmovdqa_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1163) } emit_vmovdqa_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqa_xmm_xmm(dst, src)) } emit_vmovdqa_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqa_xmm_m128(dst, src)) } emit_vmovdqa_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqa_m128_xmm(dst, src)) } emit_vmovdqa_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovdqa_ymm_ymm(dst, src)) } emit_vmovdqa_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovdqa_ymm_m256(dst, src)) } emit_vmovdqa_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovdqa_m256_ymm(dst, src)) } -inst_vmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1152) } -inst_vmovdqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1152) } -inst_vmovdqu_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1153) } -inst_vmovdqu_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1154) } -inst_vmovdqu_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1154) } -inst_vmovdqu_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1155) } +inst_vmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1164) } +inst_vmovdqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1164) } +inst_vmovdqu_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1165) } +inst_vmovdqu_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1166) } +inst_vmovdqu_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1166) } +inst_vmovdqu_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1167) } emit_vmovdqu_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqu_xmm_xmm(dst, src)) } emit_vmovdqu_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqu_xmm_m128(dst, src)) } emit_vmovdqu_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqu_m128_xmm(dst, src)) } emit_vmovdqu_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovdqu_ymm_ymm(dst, src)) } emit_vmovdqu_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovdqu_ymm_m256(dst, src)) } emit_vmovdqu_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovdqu_m256_ymm(dst, src)) } -inst_vmovq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1156) } -inst_vmovq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1156) } -inst_vmovq_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1157) } -inst_vmovq_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 1158) } -inst_vmovq_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1159) } +inst_vmovq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1168) } +inst_vmovq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1168) } +inst_vmovq_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1169) } +inst_vmovq_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_xmm(dst), op_gpr64(src), {}, {}} }, 1170) } +inst_vmovq_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVQ, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1171) } emit_vmovq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovq_xmm_xmm(dst, src)) } emit_vmovq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vmovq_xmm_m64(dst, src)) } emit_vmovq_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovq_m64_xmm(dst, src)) } emit_vmovq_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR64) { append(instructions, inst_vmovq_xmm_r64(dst, src)) } emit_vmovq_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_vmovq_r64_xmm(dst, src)) } -inst_vmovd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 1160) } -inst_vmovd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1160) } -inst_vmovd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1161) } -inst_vmovd_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1161) } +inst_vmovd_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_xmm(dst), op_gpr32(src), {}, {}} }, 1172) } +inst_vmovd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1172) } +inst_vmovd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1173) } +inst_vmovd_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1173) } emit_vmovd_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: GPR32) { append(instructions, inst_vmovd_xmm_r32(dst, src)) } emit_vmovd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vmovd_xmm_m32(dst, src)) } emit_vmovd_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vmovd_r32_xmm(dst, src)) } emit_vmovd_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vmovd_m32_xmm(dst, src)) } -inst_vmovlps_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1162) } -inst_vmovlps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1163) } +inst_vmovlps_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1174) } +inst_vmovlps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1175) } emit_vmovlps_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmovlps_xmm_xmm_m64(dst, src, src2)) } emit_vmovlps_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovlps_m64_xmm(dst, src)) } -inst_vmovhps_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1164) } -inst_vmovhps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1165) } +inst_vmovhps_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1176) } +inst_vmovhps_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPS, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1177) } emit_vmovhps_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmovhps_xmm_xmm_m64(dst, src, src2)) } emit_vmovhps_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovhps_m64_xmm(dst, src)) } -inst_vmovlpd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1166) } -inst_vmovlpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1167) } +inst_vmovlpd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1178) } +inst_vmovlpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1179) } emit_vmovlpd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmovlpd_xmm_xmm_m64(dst, src, src2)) } emit_vmovlpd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovlpd_m64_xmm(dst, src)) } -inst_vmovhpd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1168) } -inst_vmovhpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1169) } +inst_vmovhpd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1180) } +inst_vmovhpd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHPD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1181) } emit_vmovhpd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vmovhpd_xmm_xmm_m64(dst, src, src2)) } emit_vmovhpd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vmovhpd_m64_xmm(dst, src)) } -inst_vmovlhps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1170) } +inst_vmovlhps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVLHPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1182) } emit_vmovlhps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmovlhps_xmm_xmm_xmm(dst, src, src2)) } -inst_vmovhlps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1171) } +inst_vmovhlps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVHLPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1183) } emit_vmovhlps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vmovhlps_xmm_xmm_xmm(dst, src, src2)) } -inst_vmovmskps_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1172) } -inst_vmovmskps_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1173) } +inst_vmovmskps_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1184) } +inst_vmovmskps_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPS, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1185) } emit_vmovmskps_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vmovmskps_r32_xmm(dst, src)) } emit_vmovmskps_r32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: YMM) { append(instructions, inst_vmovmskps_r32_ymm(dst, src)) } -inst_vmovmskpd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1174) } -inst_vmovmskpd_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1175) } +inst_vmovmskpd_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1186) } +inst_vmovmskpd_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVMSKPD, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1187) } emit_vmovmskpd_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vmovmskpd_r32_xmm(dst, src)) } emit_vmovmskpd_r32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: YMM) { append(instructions, inst_vmovmskpd_r32_ymm(dst, src)) } -inst_vmovntps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1176) } -inst_vmovntps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1177) } +inst_vmovntps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1188) } +inst_vmovntps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1189) } emit_vmovntps_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovntps_m128_xmm(dst, src)) } emit_vmovntps_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovntps_m256_ymm(dst, src)) } -inst_vmovntpd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1178) } -inst_vmovntpd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1179) } +inst_vmovntpd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1190) } +inst_vmovntpd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1191) } emit_vmovntpd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovntpd_m128_xmm(dst, src)) } emit_vmovntpd_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovntpd_m256_ymm(dst, src)) } -inst_vmovntdq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1180) } -inst_vmovntdq_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1181) } +inst_vmovntdq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1192) } +inst_vmovntdq_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQ, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1193) } emit_vmovntdq_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovntdq_m128_xmm(dst, src)) } emit_vmovntdq_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vmovntdq_m256_ymm(dst, src)) } -inst_vmovntdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1182) } -inst_vmovntdqa_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQA, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1183) } +inst_vmovntdqa_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQA, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1194) } +inst_vmovntdqa_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVNTDQA, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1195) } emit_vmovntdqa_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovntdqa_xmm_m128(dst, src)) } emit_vmovntdqa_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovntdqa_ymm_m256(dst, src)) } -inst_vaddsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1184) } -inst_vaddsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1184) } -inst_vaddsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1185) } -inst_vaddsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1185) } +inst_vaddsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1196) } +inst_vaddsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1196) } +inst_vaddsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1197) } +inst_vaddsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1197) } emit_vaddsubps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddsubps_xmm_xmm_xmm(dst, src, src2)) } emit_vaddsubps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaddsubps_xmm_xmm_m128(dst, src, src2)) } emit_vaddsubps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vaddsubps_ymm_ymm_ymm(dst, src, src2)) } emit_vaddsubps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vaddsubps_ymm_ymm_m256(dst, src, src2)) } -inst_vaddsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1186) } -inst_vaddsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1186) } -inst_vaddsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1187) } -inst_vaddsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1187) } +inst_vaddsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1198) } +inst_vaddsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1198) } +inst_vaddsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1199) } +inst_vaddsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VADDSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1199) } emit_vaddsubpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaddsubpd_xmm_xmm_xmm(dst, src, src2)) } emit_vaddsubpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaddsubpd_xmm_xmm_m128(dst, src, src2)) } emit_vaddsubpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vaddsubpd_ymm_ymm_ymm(dst, src, src2)) } emit_vaddsubpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vaddsubpd_ymm_ymm_m256(dst, src, src2)) } -inst_vhaddps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1188) } -inst_vhaddps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1188) } -inst_vhaddps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1189) } -inst_vhaddps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1189) } +inst_vhaddps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1200) } +inst_vhaddps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1200) } +inst_vhaddps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1201) } +inst_vhaddps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1201) } emit_vhaddps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vhaddps_xmm_xmm_xmm(dst, src, src2)) } emit_vhaddps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vhaddps_xmm_xmm_m128(dst, src, src2)) } emit_vhaddps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vhaddps_ymm_ymm_ymm(dst, src, src2)) } emit_vhaddps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vhaddps_ymm_ymm_m256(dst, src, src2)) } -inst_vhaddpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1190) } -inst_vhaddpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1190) } -inst_vhaddpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1191) } -inst_vhaddpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1191) } +inst_vhaddpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1202) } +inst_vhaddpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1202) } +inst_vhaddpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1203) } +inst_vhaddpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHADDPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1203) } emit_vhaddpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vhaddpd_xmm_xmm_xmm(dst, src, src2)) } emit_vhaddpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vhaddpd_xmm_xmm_m128(dst, src, src2)) } emit_vhaddpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vhaddpd_ymm_ymm_ymm(dst, src, src2)) } emit_vhaddpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vhaddpd_ymm_ymm_m256(dst, src, src2)) } -inst_vhsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1192) } -inst_vhsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1192) } -inst_vhsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1193) } -inst_vhsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1193) } +inst_vhsubps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1204) } +inst_vhsubps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1204) } +inst_vhsubps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1205) } +inst_vhsubps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1205) } emit_vhsubps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vhsubps_xmm_xmm_xmm(dst, src, src2)) } emit_vhsubps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vhsubps_xmm_xmm_m128(dst, src, src2)) } emit_vhsubps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vhsubps_ymm_ymm_ymm(dst, src, src2)) } emit_vhsubps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vhsubps_ymm_ymm_m256(dst, src, src2)) } -inst_vhsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1194) } -inst_vhsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1194) } -inst_vhsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1195) } -inst_vhsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1195) } +inst_vhsubpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1206) } +inst_vhsubpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1206) } +inst_vhsubpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1207) } +inst_vhsubpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VHSUBPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1207) } emit_vhsubpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vhsubpd_xmm_xmm_xmm(dst, src, src2)) } emit_vhsubpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vhsubpd_xmm_xmm_m128(dst, src, src2)) } emit_vhsubpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vhsubpd_ymm_ymm_ymm(dst, src, src2)) } emit_vhsubpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vhsubpd_ymm_ymm_m256(dst, src, src2)) } -inst_vlddqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VLDDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1196) } -inst_vlddqu_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VLDDQU, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1197) } +inst_vlddqu_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VLDDQU, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1208) } +inst_vlddqu_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VLDDQU, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1209) } emit_vlddqu_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vlddqu_xmm_m128(dst, src)) } emit_vlddqu_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vlddqu_ymm_m256(dst, src)) } -inst_vmovddup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1198) } -inst_vmovddup_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1198) } -inst_vmovddup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1199) } -inst_vmovddup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1199) } +inst_vmovddup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1210) } +inst_vmovddup_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1210) } +inst_vmovddup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1211) } +inst_vmovddup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1211) } emit_vmovddup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovddup_xmm_xmm(dst, src)) } emit_vmovddup_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vmovddup_xmm_m64(dst, src)) } emit_vmovddup_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovddup_ymm_ymm(dst, src)) } emit_vmovddup_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovddup_ymm_m256(dst, src)) } -inst_vmovsldup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1200) } -inst_vmovsldup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1200) } -inst_vmovsldup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1201) } -inst_vmovsldup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1201) } +inst_vmovsldup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1212) } +inst_vmovsldup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1212) } +inst_vmovsldup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1213) } +inst_vmovsldup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSLDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1213) } emit_vmovsldup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovsldup_xmm_xmm(dst, src)) } emit_vmovsldup_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovsldup_xmm_m128(dst, src)) } emit_vmovsldup_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovsldup_ymm_ymm(dst, src)) } emit_vmovsldup_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovsldup_ymm_m256(dst, src)) } -inst_vmovshdup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1202) } -inst_vmovshdup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1202) } -inst_vmovshdup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1203) } -inst_vmovshdup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1203) } +inst_vmovshdup_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1214) } +inst_vmovshdup_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1214) } +inst_vmovshdup_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1215) } +inst_vmovshdup_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVSHDUP, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1215) } emit_vmovshdup_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovshdup_xmm_xmm(dst, src)) } emit_vmovshdup_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovshdup_xmm_m128(dst, src)) } emit_vmovshdup_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vmovshdup_ymm_ymm(dst, src)) } emit_vmovshdup_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vmovshdup_ymm_m256(dst, src)) } -inst_vpcmpestri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1204) } -inst_vpcmpestri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1204) } +inst_vpcmpestri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1216) } +inst_vpcmpestri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1216) } emit_vpcmpestri_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpcmpestri_xmm_xmm_imm8(dst, src, imm)) } emit_vpcmpestri_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpcmpestri_xmm_m128_imm8(dst, src, imm)) } -inst_vpcmpestrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1205) } -inst_vpcmpestrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1205) } +inst_vpcmpestrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1217) } +inst_vpcmpestrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPESTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1217) } emit_vpcmpestrm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpcmpestrm_xmm_xmm_imm8(dst, src, imm)) } emit_vpcmpestrm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpcmpestrm_xmm_m128_imm8(dst, src, imm)) } -inst_vpcmpistri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1206) } -inst_vpcmpistri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1206) } +inst_vpcmpistri_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1218) } +inst_vpcmpistri_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRI, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1218) } emit_vpcmpistri_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpcmpistri_xmm_xmm_imm8(dst, src, imm)) } emit_vpcmpistri_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpcmpistri_xmm_m128_imm8(dst, src, imm)) } -inst_vpcmpistrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1207) } -inst_vpcmpistrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1207) } +inst_vpcmpistrm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1219) } +inst_vpcmpistrm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPISTRM, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1219) } emit_vpcmpistrm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpcmpistrm_xmm_xmm_imm8(dst, src, imm)) } emit_vpcmpistrm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpcmpistrm_xmm_m128_imm8(dst, src, imm)) } -inst_vpbroadcastb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1208) } -inst_vpbroadcastb_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1209) } -inst_vpbroadcastb_xmm_m8 :: #force_inline proc "contextless" (dst: XMM, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 1), {}, {}} }, 1210) } -inst_vpbroadcastb_ymm_m8 :: #force_inline proc "contextless" (dst: YMM, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 1), {}, {}} }, 1211) } +inst_vpbroadcastb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1220) } +inst_vpbroadcastb_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1221) } +inst_vpbroadcastb_xmm_m8 :: #force_inline proc "contextless" (dst: XMM, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 1), {}, {}} }, 1222) } +inst_vpbroadcastb_ymm_m8 :: #force_inline proc "contextless" (dst: YMM, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTB, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 1), {}, {}} }, 1223) } emit_vpbroadcastb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpbroadcastb_xmm_xmm(dst, src)) } emit_vpbroadcastb_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpbroadcastb_ymm_xmm(dst, src)) } emit_vpbroadcastb_xmm_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem8) { append(instructions, inst_vpbroadcastb_xmm_m8(dst, src)) } emit_vpbroadcastb_ymm_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem8) { append(instructions, inst_vpbroadcastb_ymm_m8(dst, src)) } -inst_vpbroadcastw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1212) } -inst_vpbroadcastw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1213) } -inst_vpbroadcastw_xmm_m16 :: #force_inline proc "contextless" (dst: XMM, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 2), {}, {}} }, 1214) } -inst_vpbroadcastw_ymm_m16 :: #force_inline proc "contextless" (dst: YMM, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 2), {}, {}} }, 1215) } +inst_vpbroadcastw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1224) } +inst_vpbroadcastw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1225) } +inst_vpbroadcastw_xmm_m16 :: #force_inline proc "contextless" (dst: XMM, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 2), {}, {}} }, 1226) } +inst_vpbroadcastw_ymm_m16 :: #force_inline proc "contextless" (dst: YMM, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 2), {}, {}} }, 1227) } emit_vpbroadcastw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpbroadcastw_xmm_xmm(dst, src)) } emit_vpbroadcastw_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpbroadcastw_ymm_xmm(dst, src)) } emit_vpbroadcastw_xmm_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem16) { append(instructions, inst_vpbroadcastw_xmm_m16(dst, src)) } emit_vpbroadcastw_ymm_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem16) { append(instructions, inst_vpbroadcastw_ymm_m16(dst, src)) } -inst_vpbroadcastd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1216) } -inst_vpbroadcastd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1217) } -inst_vpbroadcastd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1218) } -inst_vpbroadcastd_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1219) } +inst_vpbroadcastd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1228) } +inst_vpbroadcastd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1229) } +inst_vpbroadcastd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1230) } +inst_vpbroadcastd_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1231) } emit_vpbroadcastd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpbroadcastd_xmm_xmm(dst, src)) } emit_vpbroadcastd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpbroadcastd_ymm_xmm(dst, src)) } emit_vpbroadcastd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vpbroadcastd_xmm_m32(dst, src)) } emit_vpbroadcastd_ymm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem32) { append(instructions, inst_vpbroadcastd_ymm_m32(dst, src)) } -inst_vpbroadcastq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1220) } -inst_vpbroadcastq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1221) } -inst_vpbroadcastq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1222) } -inst_vpbroadcastq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1223) } +inst_vpbroadcastq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1232) } +inst_vpbroadcastq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1233) } +inst_vpbroadcastq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1234) } +inst_vpbroadcastq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBROADCASTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1235) } emit_vpbroadcastq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpbroadcastq_xmm_xmm(dst, src)) } emit_vpbroadcastq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpbroadcastq_ymm_xmm(dst, src)) } emit_vpbroadcastq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpbroadcastq_xmm_m64(dst, src)) } emit_vpbroadcastq_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vpbroadcastq_ymm_m64(dst, src)) } -inst_vcvtps2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1224) } -inst_vcvtps2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1224) } -inst_vcvtps2pd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1225) } -inst_vcvtps2pd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1225) } +inst_vcvtps2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1236) } +inst_vcvtps2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1236) } +inst_vcvtps2pd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1237) } +inst_vcvtps2pd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1237) } emit_vcvtps2pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtps2pd_xmm_xmm(dst, src)) } emit_vcvtps2pd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vcvtps2pd_xmm_m64(dst, src)) } emit_vcvtps2pd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vcvtps2pd_ymm_xmm(dst, src)) } emit_vcvtps2pd_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vcvtps2pd_ymm_m128(dst, src)) } -inst_vcvtpd2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1226) } -inst_vcvtpd2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1226) } -inst_vcvtpd2ps_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1227) } -inst_vcvtpd2ps_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1227) } +inst_vcvtpd2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1238) } +inst_vcvtpd2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1238) } +inst_vcvtpd2ps_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1239) } +inst_vcvtpd2ps_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1239) } emit_vcvtpd2ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtpd2ps_xmm_xmm(dst, src)) } emit_vcvtpd2ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvtpd2ps_xmm_m128(dst, src)) } emit_vcvtpd2ps_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vcvtpd2ps_xmm_ymm(dst, src)) } emit_vcvtpd2ps_xmm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem256) { append(instructions, inst_vcvtpd2ps_xmm_m256(dst, src)) } -inst_vcvtss2sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1228) } -inst_vcvtss2sd_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1228) } +inst_vcvtss2sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1240) } +inst_vcvtss2sd_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1240) } emit_vcvtss2sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vcvtss2sd_xmm_xmm_xmm(dst, src, src2)) } emit_vcvtss2sd_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vcvtss2sd_xmm_xmm_m32(dst, src, src2)) } -inst_vcvtsd2ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1229) } -inst_vcvtsd2ss_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1229) } +inst_vcvtsd2ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1241) } +inst_vcvtsd2ss_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1241) } emit_vcvtsd2ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vcvtsd2ss_xmm_xmm_xmm(dst, src, src2)) } emit_vcvtsd2ss_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vcvtsd2ss_xmm_xmm_m64(dst, src, src2)) } -inst_vcvtps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1230) } -inst_vcvtps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1230) } -inst_vcvtps2dq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1231) } -inst_vcvtps2dq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1231) } +inst_vcvtps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1242) } +inst_vcvtps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1242) } +inst_vcvtps2dq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1243) } +inst_vcvtps2dq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1243) } emit_vcvtps2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtps2dq_xmm_xmm(dst, src)) } emit_vcvtps2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvtps2dq_xmm_m128(dst, src)) } emit_vcvtps2dq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vcvtps2dq_ymm_ymm(dst, src)) } emit_vcvtps2dq_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vcvtps2dq_ymm_m256(dst, src)) } -inst_vcvtpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1232) } -inst_vcvtpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1232) } -inst_vcvtpd2dq_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1233) } -inst_vcvtpd2dq_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1233) } +inst_vcvtpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1244) } +inst_vcvtpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1244) } +inst_vcvtpd2dq_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1245) } +inst_vcvtpd2dq_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1245) } emit_vcvtpd2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtpd2dq_xmm_xmm(dst, src)) } emit_vcvtpd2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvtpd2dq_xmm_m128(dst, src)) } emit_vcvtpd2dq_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vcvtpd2dq_xmm_ymm(dst, src)) } emit_vcvtpd2dq_xmm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem256) { append(instructions, inst_vcvtpd2dq_xmm_m256(dst, src)) } -inst_vcvtdq2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1234) } -inst_vcvtdq2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1234) } -inst_vcvtdq2ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1235) } -inst_vcvtdq2ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1235) } +inst_vcvtdq2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1246) } +inst_vcvtdq2ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1246) } +inst_vcvtdq2ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1247) } +inst_vcvtdq2ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1247) } emit_vcvtdq2ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtdq2ps_xmm_xmm(dst, src)) } emit_vcvtdq2ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvtdq2ps_xmm_m128(dst, src)) } emit_vcvtdq2ps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vcvtdq2ps_ymm_ymm(dst, src)) } emit_vcvtdq2ps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vcvtdq2ps_ymm_m256(dst, src)) } -inst_vcvtdq2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1236) } -inst_vcvtdq2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1236) } -inst_vcvtdq2pd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1237) } -inst_vcvtdq2pd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1237) } +inst_vcvtdq2pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1248) } +inst_vcvtdq2pd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1248) } +inst_vcvtdq2pd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1249) } +inst_vcvtdq2pd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTDQ2PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1249) } emit_vcvtdq2pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtdq2pd_xmm_xmm(dst, src)) } emit_vcvtdq2pd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vcvtdq2pd_xmm_m64(dst, src)) } emit_vcvtdq2pd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vcvtdq2pd_ymm_xmm(dst, src)) } emit_vcvtdq2pd_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vcvtdq2pd_ymm_m128(dst, src)) } -inst_vcvtss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1238) } -inst_vcvtss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 1238) } -inst_vcvtss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1239) } -inst_vcvtss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 1239) } +inst_vcvtss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1250) } +inst_vcvtss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 1250) } +inst_vcvtss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1251) } +inst_vcvtss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 1251) } emit_vcvtss2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vcvtss2si_r32_xmm(dst, src)) } emit_vcvtss2si_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_vcvtss2si_r32_m32(dst, src)) } emit_vcvtss2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_vcvtss2si_r64_xmm(dst, src)) } emit_vcvtss2si_r64_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem32) { append(instructions, inst_vcvtss2si_r64_m32(dst, src)) } -inst_vcvtsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1240) } -inst_vcvtsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 1240) } -inst_vcvtsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1241) } -inst_vcvtsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1241) } +inst_vcvtsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1252) } +inst_vcvtsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 1252) } +inst_vcvtsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1253) } +inst_vcvtsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1253) } emit_vcvtsd2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vcvtsd2si_r32_xmm(dst, src)) } emit_vcvtsd2si_r32_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem64) { append(instructions, inst_vcvtsd2si_r32_m64(dst, src)) } emit_vcvtsd2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_vcvtsd2si_r64_xmm(dst, src)) } emit_vcvtsd2si_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_vcvtsd2si_r64_m64(dst, src)) } -inst_vcvtsi2ss_xmm_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), {}} }, 1242) } -inst_vcvtsi2ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1242) } -inst_vcvtsi2ss_xmm_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), {}} }, 1243) } -inst_vcvtsi2ss_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1243) } +inst_vcvtsi2ss_xmm_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), {}} }, 1254) } +inst_vcvtsi2ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1254) } +inst_vcvtsi2ss_xmm_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), {}} }, 1255) } +inst_vcvtsi2ss_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1255) } emit_vcvtsi2ss_xmm_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR32) { append(instructions, inst_vcvtsi2ss_xmm_xmm_r32(dst, src, src2)) } emit_vcvtsi2ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vcvtsi2ss_xmm_xmm_m32(dst, src, src2)) } emit_vcvtsi2ss_xmm_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR64) { append(instructions, inst_vcvtsi2ss_xmm_xmm_r64(dst, src, src2)) } emit_vcvtsi2ss_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vcvtsi2ss_xmm_xmm_m64(dst, src, src2)) } -inst_vcvtsi2sd_xmm_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), {}} }, 1244) } -inst_vcvtsi2sd_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1244) } -inst_vcvtsi2sd_xmm_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), {}} }, 1245) } -inst_vcvtsi2sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1245) } +inst_vcvtsi2sd_xmm_xmm_r32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), {}} }, 1256) } +inst_vcvtsi2sd_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1256) } +inst_vcvtsi2sd_xmm_xmm_r64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), {}} }, 1257) } +inst_vcvtsi2sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTSI2SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1257) } emit_vcvtsi2sd_xmm_xmm_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR32) { append(instructions, inst_vcvtsi2sd_xmm_xmm_r32(dst, src, src2)) } emit_vcvtsi2sd_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vcvtsi2sd_xmm_xmm_m32(dst, src, src2)) } emit_vcvtsi2sd_xmm_xmm_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR64) { append(instructions, inst_vcvtsi2sd_xmm_xmm_r64(dst, src, src2)) } emit_vcvtsi2sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vcvtsi2sd_xmm_xmm_m64(dst, src, src2)) } -inst_vcvttps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1246) } -inst_vcvttps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1246) } -inst_vcvttps2dq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1247) } -inst_vcvttps2dq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1247) } +inst_vcvttps2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1258) } +inst_vcvttps2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1258) } +inst_vcvttps2dq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1259) } +inst_vcvttps2dq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPS2DQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1259) } emit_vcvttps2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvttps2dq_xmm_xmm(dst, src)) } emit_vcvttps2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvttps2dq_xmm_m128(dst, src)) } emit_vcvttps2dq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vcvttps2dq_ymm_ymm(dst, src)) } emit_vcvttps2dq_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vcvttps2dq_ymm_m256(dst, src)) } -inst_vcvttpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1248) } -inst_vcvttpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1248) } -inst_vcvttpd2dq_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1249) } -inst_vcvttpd2dq_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1249) } +inst_vcvttpd2dq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1260) } +inst_vcvttpd2dq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1260) } +inst_vcvttpd2dq_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1261) } +inst_vcvttpd2dq_xmm_m256 :: #force_inline proc "contextless" (dst: XMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTPD2DQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 32), {}, {}} }, 1261) } emit_vcvttpd2dq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvttpd2dq_xmm_xmm(dst, src)) } emit_vcvttpd2dq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vcvttpd2dq_xmm_m128(dst, src)) } emit_vcvttpd2dq_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vcvttpd2dq_xmm_ymm(dst, src)) } emit_vcvttpd2dq_xmm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem256) { append(instructions, inst_vcvttpd2dq_xmm_m256(dst, src)) } -inst_vcvttss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1250) } -inst_vcvttss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 1250) } -inst_vcvttss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1251) } -inst_vcvttss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 1251) } +inst_vcvttss2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1262) } +inst_vcvttss2si_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 1262) } +inst_vcvttss2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1263) } +inst_vcvttss2si_r64_m32 :: #force_inline proc "contextless" (dst: GPR64, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSS2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 4), {}, {}} }, 1263) } emit_vcvttss2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vcvttss2si_r32_xmm(dst, src)) } emit_vcvttss2si_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_vcvttss2si_r32_m32(dst, src)) } emit_vcvttss2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_vcvttss2si_r64_xmm(dst, src)) } emit_vcvttss2si_r64_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem32) { append(instructions, inst_vcvttss2si_r64_m32(dst, src)) } -inst_vcvttsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1252) } -inst_vcvttsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 1252) } -inst_vcvttsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1253) } -inst_vcvttsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1253) } +inst_vcvttsd2si_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1264) } +inst_vcvttsd2si_r32_m64 :: #force_inline proc "contextless" (dst: GPR32, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 8), {}, {}} }, 1264) } +inst_vcvttsd2si_r64_xmm :: #force_inline proc "contextless" (dst: GPR64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_xmm(src), {}, {}} }, 1265) } +inst_vcvttsd2si_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTTSD2SI, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 1265) } emit_vcvttsd2si_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vcvttsd2si_r32_xmm(dst, src)) } emit_vcvttsd2si_r32_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem64) { append(instructions, inst_vcvttsd2si_r32_m64(dst, src)) } emit_vcvttsd2si_r64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM) { append(instructions, inst_vcvttsd2si_r64_xmm(dst, src)) } emit_vcvttsd2si_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_vcvttsd2si_r64_m64(dst, src)) } -inst_vpaddb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1254) } -inst_vpaddb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1254) } -inst_vpaddb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1255) } -inst_vpaddb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1255) } +inst_vpaddb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1266) } +inst_vpaddb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1266) } +inst_vpaddb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1267) } +inst_vpaddb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1267) } emit_vpaddb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpaddb_xmm_xmm_xmm(dst, src, src2)) } emit_vpaddb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpaddb_xmm_xmm_m128(dst, src, src2)) } emit_vpaddb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpaddb_ymm_ymm_ymm(dst, src, src2)) } emit_vpaddb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpaddb_ymm_ymm_m256(dst, src, src2)) } -inst_vpaddw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1256) } -inst_vpaddw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1256) } -inst_vpaddw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1257) } -inst_vpaddw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1257) } +inst_vpaddw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1268) } +inst_vpaddw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1268) } +inst_vpaddw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1269) } +inst_vpaddw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1269) } emit_vpaddw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpaddw_xmm_xmm_xmm(dst, src, src2)) } emit_vpaddw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpaddw_xmm_xmm_m128(dst, src, src2)) } emit_vpaddw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpaddw_ymm_ymm_ymm(dst, src, src2)) } emit_vpaddw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpaddw_ymm_ymm_m256(dst, src, src2)) } -inst_vpaddd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1258) } -inst_vpaddd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1258) } -inst_vpaddd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1259) } -inst_vpaddd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1259) } +inst_vpaddd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1270) } +inst_vpaddd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1270) } +inst_vpaddd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1271) } +inst_vpaddd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1271) } emit_vpaddd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpaddd_xmm_xmm_xmm(dst, src, src2)) } emit_vpaddd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpaddd_xmm_xmm_m128(dst, src, src2)) } emit_vpaddd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpaddd_ymm_ymm_ymm(dst, src, src2)) } emit_vpaddd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpaddd_ymm_ymm_m256(dst, src, src2)) } -inst_vpaddq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1260) } -inst_vpaddq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1260) } -inst_vpaddq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1261) } -inst_vpaddq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1261) } +inst_vpaddq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1272) } +inst_vpaddq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1272) } +inst_vpaddq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1273) } +inst_vpaddq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPADDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1273) } emit_vpaddq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpaddq_xmm_xmm_xmm(dst, src, src2)) } emit_vpaddq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpaddq_xmm_xmm_m128(dst, src, src2)) } emit_vpaddq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpaddq_ymm_ymm_ymm(dst, src, src2)) } emit_vpaddq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpaddq_ymm_ymm_m256(dst, src, src2)) } -inst_vpsubb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1262) } -inst_vpsubb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1262) } -inst_vpsubb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1263) } -inst_vpsubb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1263) } +inst_vpsubb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1274) } +inst_vpsubb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1274) } +inst_vpsubb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1275) } +inst_vpsubb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1275) } emit_vpsubb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsubb_xmm_xmm_xmm(dst, src, src2)) } emit_vpsubb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsubb_xmm_xmm_m128(dst, src, src2)) } emit_vpsubb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsubb_ymm_ymm_ymm(dst, src, src2)) } emit_vpsubb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsubb_ymm_ymm_m256(dst, src, src2)) } -inst_vpsubw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1264) } -inst_vpsubw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1264) } -inst_vpsubw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1265) } -inst_vpsubw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1265) } +inst_vpsubw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1276) } +inst_vpsubw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1276) } +inst_vpsubw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1277) } +inst_vpsubw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1277) } emit_vpsubw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsubw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsubw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsubw_xmm_xmm_m128(dst, src, src2)) } emit_vpsubw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsubw_ymm_ymm_ymm(dst, src, src2)) } emit_vpsubw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsubw_ymm_ymm_m256(dst, src, src2)) } -inst_vpsubd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1266) } -inst_vpsubd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1266) } -inst_vpsubd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1267) } -inst_vpsubd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1267) } +inst_vpsubd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1278) } +inst_vpsubd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1278) } +inst_vpsubd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1279) } +inst_vpsubd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1279) } emit_vpsubd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsubd_xmm_xmm_xmm(dst, src, src2)) } emit_vpsubd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsubd_xmm_xmm_m128(dst, src, src2)) } emit_vpsubd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsubd_ymm_ymm_ymm(dst, src, src2)) } emit_vpsubd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsubd_ymm_ymm_m256(dst, src, src2)) } -inst_vpsubq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1268) } -inst_vpsubq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1268) } -inst_vpsubq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1269) } -inst_vpsubq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1269) } +inst_vpsubq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1280) } +inst_vpsubq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1280) } +inst_vpsubq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1281) } +inst_vpsubq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSUBQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1281) } emit_vpsubq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsubq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsubq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsubq_xmm_xmm_m128(dst, src, src2)) } emit_vpsubq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsubq_ymm_ymm_ymm(dst, src, src2)) } emit_vpsubq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsubq_ymm_ymm_m256(dst, src, src2)) } -inst_vpmullw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1270) } -inst_vpmullw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1270) } -inst_vpmullw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1271) } -inst_vpmullw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1271) } +inst_vpmullw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1282) } +inst_vpmullw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1282) } +inst_vpmullw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1283) } +inst_vpmullw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1283) } emit_vpmullw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmullw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmullw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmullw_xmm_xmm_m128(dst, src, src2)) } emit_vpmullw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmullw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmullw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmullw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmulhw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1272) } -inst_vpmulhw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1272) } -inst_vpmulhw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1273) } -inst_vpmulhw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1273) } +inst_vpmulhw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1284) } +inst_vpmulhw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1284) } +inst_vpmulhw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1285) } +inst_vpmulhw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1285) } emit_vpmulhw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmulhw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmulhw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmulhw_xmm_xmm_m128(dst, src, src2)) } emit_vpmulhw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmulhw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmulhw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmulhw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmulhuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1274) } -inst_vpmulhuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1274) } -inst_vpmulhuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1275) } -inst_vpmulhuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1275) } +inst_vpmulhuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1286) } +inst_vpmulhuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1286) } +inst_vpmulhuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1287) } +inst_vpmulhuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1287) } emit_vpmulhuw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmulhuw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmulhuw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmulhuw_xmm_xmm_m128(dst, src, src2)) } emit_vpmulhuw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmulhuw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmulhuw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmulhuw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmuludq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1276) } -inst_vpmuludq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1276) } -inst_vpmuludq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1277) } -inst_vpmuludq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1277) } +inst_vpmuludq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1288) } +inst_vpmuludq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1288) } +inst_vpmuludq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1289) } +inst_vpmuludq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULUDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1289) } emit_vpmuludq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmuludq_xmm_xmm_xmm(dst, src, src2)) } emit_vpmuludq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmuludq_xmm_xmm_m128(dst, src, src2)) } emit_vpmuludq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmuludq_ymm_ymm_ymm(dst, src, src2)) } emit_vpmuludq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmuludq_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaddwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1278) } -inst_vpmaddwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1278) } -inst_vpmaddwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1279) } -inst_vpmaddwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1279) } +inst_vpmaddwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1290) } +inst_vpmaddwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1290) } +inst_vpmaddwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1291) } +inst_vpmaddwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1291) } emit_vpmaddwd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaddwd_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaddwd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaddwd_xmm_xmm_m128(dst, src, src2)) } emit_vpmaddwd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaddwd_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaddwd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaddwd_ymm_ymm_m256(dst, src, src2)) } -inst_vpand_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1280) } -inst_vpand_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1280) } -inst_vpand_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1281) } -inst_vpand_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1281) } +inst_vpand_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1292) } +inst_vpand_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1292) } +inst_vpand_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1293) } +inst_vpand_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPAND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1293) } emit_vpand_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpand_xmm_xmm_xmm(dst, src, src2)) } emit_vpand_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpand_xmm_xmm_m128(dst, src, src2)) } emit_vpand_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpand_ymm_ymm_ymm(dst, src, src2)) } emit_vpand_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpand_ymm_ymm_m256(dst, src, src2)) } -inst_vpandn_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1282) } -inst_vpandn_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1282) } -inst_vpandn_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1283) } -inst_vpandn_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1283) } +inst_vpandn_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1294) } +inst_vpandn_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1294) } +inst_vpandn_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1295) } +inst_vpandn_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPANDN, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1295) } emit_vpandn_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpandn_xmm_xmm_xmm(dst, src, src2)) } emit_vpandn_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpandn_xmm_xmm_m128(dst, src, src2)) } emit_vpandn_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpandn_ymm_ymm_ymm(dst, src, src2)) } emit_vpandn_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpandn_ymm_ymm_m256(dst, src, src2)) } -inst_vpor_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1284) } -inst_vpor_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1284) } -inst_vpor_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1285) } -inst_vpor_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1285) } +inst_vpor_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1296) } +inst_vpor_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1296) } +inst_vpor_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1297) } +inst_vpor_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1297) } emit_vpor_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpor_xmm_xmm_xmm(dst, src, src2)) } emit_vpor_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpor_xmm_xmm_m128(dst, src, src2)) } emit_vpor_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpor_ymm_ymm_ymm(dst, src, src2)) } emit_vpor_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpor_ymm_ymm_m256(dst, src, src2)) } -inst_vpxor_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1286) } -inst_vpxor_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1286) } -inst_vpxor_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1287) } -inst_vpxor_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1287) } +inst_vpxor_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1298) } +inst_vpxor_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1298) } +inst_vpxor_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1299) } +inst_vpxor_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPXOR, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1299) } emit_vpxor_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpxor_xmm_xmm_xmm(dst, src, src2)) } emit_vpxor_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpxor_xmm_xmm_m128(dst, src, src2)) } emit_vpxor_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpxor_ymm_ymm_ymm(dst, src, src2)) } emit_vpxor_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpxor_ymm_ymm_m256(dst, src, src2)) } -inst_vpsllw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1288) } -inst_vpsllw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1288) } -inst_vpsllw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1289) } -inst_vpsllw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1290) } -inst_vpsllw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1290) } -inst_vpsllw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1291) } +inst_vpsllw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1300) } +inst_vpsllw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1300) } +inst_vpsllw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1301) } +inst_vpsllw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1302) } +inst_vpsllw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1302) } +inst_vpsllw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1303) } emit_vpsllw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsllw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsllw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsllw_xmm_xmm_m128(dst, src, src2)) } emit_vpsllw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsllw_xmm_xmm_imm8(dst, src, imm)) } emit_vpsllw_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsllw_ymm_ymm_xmm(dst, src, src2)) } emit_vpsllw_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsllw_ymm_ymm_m128(dst, src, src2)) } emit_vpsllw_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsllw_ymm_ymm_imm8(dst, src, imm)) } -inst_vpslld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1292) } -inst_vpslld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1292) } -inst_vpslld_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1293) } -inst_vpslld_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1294) } -inst_vpslld_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1294) } -inst_vpslld_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1295) } +inst_vpslld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1304) } +inst_vpslld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1304) } +inst_vpslld_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1305) } +inst_vpslld_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1306) } +inst_vpslld_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1306) } +inst_vpslld_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1307) } emit_vpslld_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpslld_xmm_xmm_xmm(dst, src, src2)) } emit_vpslld_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpslld_xmm_xmm_m128(dst, src, src2)) } emit_vpslld_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpslld_xmm_xmm_imm8(dst, src, imm)) } emit_vpslld_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpslld_ymm_ymm_xmm(dst, src, src2)) } emit_vpslld_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpslld_ymm_ymm_m128(dst, src, src2)) } emit_vpslld_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpslld_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsllq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1296) } -inst_vpsllq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1296) } -inst_vpsllq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1297) } -inst_vpsllq_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1298) } -inst_vpsllq_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1298) } -inst_vpsllq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1299) } +inst_vpsllq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1308) } +inst_vpsllq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1308) } +inst_vpsllq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1309) } +inst_vpsllq_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1310) } +inst_vpsllq_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1310) } +inst_vpsllq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1311) } emit_vpsllq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsllq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsllq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsllq_xmm_xmm_m128(dst, src, src2)) } emit_vpsllq_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsllq_xmm_xmm_imm8(dst, src, imm)) } emit_vpsllq_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsllq_ymm_ymm_xmm(dst, src, src2)) } emit_vpsllq_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsllq_ymm_ymm_m128(dst, src, src2)) } emit_vpsllq_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsllq_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsrlw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1300) } -inst_vpsrlw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1300) } -inst_vpsrlw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1301) } -inst_vpsrlw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1302) } -inst_vpsrlw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1302) } -inst_vpsrlw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1303) } +inst_vpsrlw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1312) } +inst_vpsrlw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1312) } +inst_vpsrlw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1313) } +inst_vpsrlw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1314) } +inst_vpsrlw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1314) } +inst_vpsrlw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1315) } emit_vpsrlw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrlw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrlw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrlw_xmm_xmm_m128(dst, src, src2)) } emit_vpsrlw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsrlw_xmm_xmm_imm8(dst, src, imm)) } emit_vpsrlw_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsrlw_ymm_ymm_xmm(dst, src, src2)) } emit_vpsrlw_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsrlw_ymm_ymm_m128(dst, src, src2)) } emit_vpsrlw_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsrlw_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsrld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1304) } -inst_vpsrld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1304) } -inst_vpsrld_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1305) } -inst_vpsrld_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1306) } -inst_vpsrld_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1306) } -inst_vpsrld_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1307) } +inst_vpsrld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1316) } +inst_vpsrld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1316) } +inst_vpsrld_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1317) } +inst_vpsrld_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1318) } +inst_vpsrld_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1318) } +inst_vpsrld_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1319) } emit_vpsrld_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrld_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrld_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrld_xmm_xmm_m128(dst, src, src2)) } emit_vpsrld_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsrld_xmm_xmm_imm8(dst, src, imm)) } emit_vpsrld_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsrld_ymm_ymm_xmm(dst, src, src2)) } emit_vpsrld_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsrld_ymm_ymm_m128(dst, src, src2)) } emit_vpsrld_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsrld_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsrlq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1308) } -inst_vpsrlq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1308) } -inst_vpsrlq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1309) } -inst_vpsrlq_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1310) } -inst_vpsrlq_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1310) } -inst_vpsrlq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1311) } +inst_vpsrlq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1320) } +inst_vpsrlq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1320) } +inst_vpsrlq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1321) } +inst_vpsrlq_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1322) } +inst_vpsrlq_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1322) } +inst_vpsrlq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1323) } emit_vpsrlq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrlq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrlq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrlq_xmm_xmm_m128(dst, src, src2)) } emit_vpsrlq_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsrlq_xmm_xmm_imm8(dst, src, imm)) } emit_vpsrlq_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsrlq_ymm_ymm_xmm(dst, src, src2)) } emit_vpsrlq_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsrlq_ymm_ymm_m128(dst, src, src2)) } emit_vpsrlq_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsrlq_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsraw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1312) } -inst_vpsraw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1312) } -inst_vpsraw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1313) } -inst_vpsraw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1314) } -inst_vpsraw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1314) } -inst_vpsraw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1315) } +inst_vpsraw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1324) } +inst_vpsraw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1324) } +inst_vpsraw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1325) } +inst_vpsraw_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1326) } +inst_vpsraw_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1326) } +inst_vpsraw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1327) } emit_vpsraw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsraw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsraw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsraw_xmm_xmm_m128(dst, src, src2)) } emit_vpsraw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsraw_xmm_xmm_imm8(dst, src, imm)) } emit_vpsraw_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsraw_ymm_ymm_xmm(dst, src, src2)) } emit_vpsraw_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsraw_ymm_ymm_m128(dst, src, src2)) } emit_vpsraw_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsraw_ymm_ymm_imm8(dst, src, imm)) } -inst_vpsrad_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1316) } -inst_vpsrad_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1316) } -inst_vpsrad_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1317) } -inst_vpsrad_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1318) } -inst_vpsrad_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1318) } -inst_vpsrad_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1319) } +inst_vpsrad_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1328) } +inst_vpsrad_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1328) } +inst_vpsrad_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1329) } +inst_vpsrad_ymm_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), {}} }, 1330) } +inst_vpsrad_ymm_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), {}} }, 1330) } +inst_vpsrad_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1331) } emit_vpsrad_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrad_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrad_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrad_xmm_xmm_m128(dst, src, src2)) } emit_vpsrad_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpsrad_xmm_xmm_imm8(dst, src, imm)) } emit_vpsrad_ymm_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM) { append(instructions, inst_vpsrad_ymm_ymm_xmm(dst, src, src2)) } emit_vpsrad_ymm_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128) { append(instructions, inst_vpsrad_ymm_ymm_m128(dst, src, src2)) } emit_vpsrad_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpsrad_ymm_ymm_imm8(dst, src, imm)) } -inst_vpcmpeqb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1320) } -inst_vpcmpeqb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1320) } -inst_vpcmpeqb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1321) } -inst_vpcmpeqb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1321) } +inst_vpcmpeqb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1332) } +inst_vpcmpeqb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1332) } +inst_vpcmpeqb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1333) } +inst_vpcmpeqb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1333) } emit_vpcmpeqb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpeqb_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpeqb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpeqb_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpeqb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpeqb_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpeqb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpeqb_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpeqw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1322) } -inst_vpcmpeqw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1322) } -inst_vpcmpeqw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1323) } -inst_vpcmpeqw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1323) } +inst_vpcmpeqw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1334) } +inst_vpcmpeqw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1334) } +inst_vpcmpeqw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1335) } +inst_vpcmpeqw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1335) } emit_vpcmpeqw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpeqw_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpeqw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpeqw_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpeqw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpeqw_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpeqw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpeqw_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpeqd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1324) } -inst_vpcmpeqd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1324) } -inst_vpcmpeqd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1325) } -inst_vpcmpeqd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1325) } +inst_vpcmpeqd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1336) } +inst_vpcmpeqd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1336) } +inst_vpcmpeqd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1337) } +inst_vpcmpeqd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1337) } emit_vpcmpeqd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpeqd_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpeqd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpeqd_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpeqd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpeqd_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpeqd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpeqd_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpeqq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1326) } -inst_vpcmpeqq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1326) } -inst_vpcmpeqq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1327) } -inst_vpcmpeqq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1327) } +inst_vpcmpeqq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1338) } +inst_vpcmpeqq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1338) } +inst_vpcmpeqq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1339) } +inst_vpcmpeqq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPEQQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1339) } emit_vpcmpeqq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpeqq_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpeqq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpeqq_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpeqq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpeqq_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpeqq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpeqq_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpgtb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1328) } -inst_vpcmpgtb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1328) } -inst_vpcmpgtb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1329) } -inst_vpcmpgtb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1329) } +inst_vpcmpgtb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1340) } +inst_vpcmpgtb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1340) } +inst_vpcmpgtb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1341) } +inst_vpcmpgtb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1341) } emit_vpcmpgtb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpgtb_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpgtb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpgtb_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpgtb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpgtb_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpgtb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpgtb_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpgtw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1330) } -inst_vpcmpgtw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1330) } -inst_vpcmpgtw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1331) } -inst_vpcmpgtw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1331) } +inst_vpcmpgtw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1342) } +inst_vpcmpgtw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1342) } +inst_vpcmpgtw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1343) } +inst_vpcmpgtw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1343) } emit_vpcmpgtw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpgtw_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpgtw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpgtw_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpgtw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpgtw_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpgtw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpgtw_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpgtd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1332) } -inst_vpcmpgtd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1332) } -inst_vpcmpgtd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1333) } -inst_vpcmpgtd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1333) } +inst_vpcmpgtd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1344) } +inst_vpcmpgtd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1344) } +inst_vpcmpgtd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1345) } +inst_vpcmpgtd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1345) } emit_vpcmpgtd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpgtd_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpgtd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpgtd_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpgtd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpgtd_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpgtd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpgtd_ymm_ymm_m256(dst, src, src2)) } -inst_vpcmpgtq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1334) } -inst_vpcmpgtq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1334) } -inst_vpcmpgtq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1335) } -inst_vpcmpgtq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1335) } +inst_vpcmpgtq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1346) } +inst_vpcmpgtq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1346) } +inst_vpcmpgtq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1347) } +inst_vpcmpgtq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPGTQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1347) } emit_vpcmpgtq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpcmpgtq_xmm_xmm_xmm(dst, src, src2)) } emit_vpcmpgtq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpcmpgtq_xmm_xmm_m128(dst, src, src2)) } emit_vpcmpgtq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpcmpgtq_ymm_ymm_ymm(dst, src, src2)) } emit_vpcmpgtq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpcmpgtq_ymm_ymm_m256(dst, src, src2)) } -inst_vpacksswb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1336) } -inst_vpacksswb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1336) } -inst_vpacksswb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1337) } -inst_vpacksswb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1337) } +inst_vpacksswb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1348) } +inst_vpacksswb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1348) } +inst_vpacksswb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1349) } +inst_vpacksswb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1349) } emit_vpacksswb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpacksswb_xmm_xmm_xmm(dst, src, src2)) } emit_vpacksswb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpacksswb_xmm_xmm_m128(dst, src, src2)) } emit_vpacksswb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpacksswb_ymm_ymm_ymm(dst, src, src2)) } emit_vpacksswb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpacksswb_ymm_ymm_m256(dst, src, src2)) } -inst_vpackssdw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1338) } -inst_vpackssdw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1338) } -inst_vpackssdw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1339) } -inst_vpackssdw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1339) } +inst_vpackssdw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1350) } +inst_vpackssdw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1350) } +inst_vpackssdw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1351) } +inst_vpackssdw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKSSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1351) } emit_vpackssdw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpackssdw_xmm_xmm_xmm(dst, src, src2)) } emit_vpackssdw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpackssdw_xmm_xmm_m128(dst, src, src2)) } emit_vpackssdw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpackssdw_ymm_ymm_ymm(dst, src, src2)) } emit_vpackssdw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpackssdw_ymm_ymm_m256(dst, src, src2)) } -inst_vpackuswb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1340) } -inst_vpackuswb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1340) } -inst_vpackuswb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1341) } -inst_vpackuswb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1341) } +inst_vpackuswb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1352) } +inst_vpackuswb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1352) } +inst_vpackuswb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1353) } +inst_vpackuswb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSWB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1353) } emit_vpackuswb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpackuswb_xmm_xmm_xmm(dst, src, src2)) } emit_vpackuswb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpackuswb_xmm_xmm_m128(dst, src, src2)) } emit_vpackuswb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpackuswb_ymm_ymm_ymm(dst, src, src2)) } emit_vpackuswb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpackuswb_ymm_ymm_m256(dst, src, src2)) } -inst_vpackusdw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1342) } -inst_vpackusdw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1342) } -inst_vpackusdw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1343) } -inst_vpackusdw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1343) } +inst_vpackusdw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1354) } +inst_vpackusdw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1354) } +inst_vpackusdw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1355) } +inst_vpackusdw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPACKUSDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1355) } emit_vpackusdw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpackusdw_xmm_xmm_xmm(dst, src, src2)) } emit_vpackusdw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpackusdw_xmm_xmm_m128(dst, src, src2)) } emit_vpackusdw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpackusdw_ymm_ymm_ymm(dst, src, src2)) } emit_vpackusdw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpackusdw_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpcklbw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1344) } -inst_vpunpcklbw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1344) } -inst_vpunpcklbw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1345) } -inst_vpunpcklbw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1345) } +inst_vpunpcklbw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1356) } +inst_vpunpcklbw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1356) } +inst_vpunpcklbw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1357) } +inst_vpunpcklbw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1357) } emit_vpunpcklbw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpcklbw_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpcklbw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpcklbw_xmm_xmm_m128(dst, src, src2)) } emit_vpunpcklbw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpcklbw_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpcklbw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpcklbw_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpcklwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1346) } -inst_vpunpcklwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1346) } -inst_vpunpcklwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1347) } -inst_vpunpcklwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1347) } +inst_vpunpcklwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1358) } +inst_vpunpcklwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1358) } +inst_vpunpcklwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1359) } +inst_vpunpcklwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1359) } emit_vpunpcklwd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpcklwd_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpcklwd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpcklwd_xmm_xmm_m128(dst, src, src2)) } emit_vpunpcklwd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpcklwd_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpcklwd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpcklwd_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpckldq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1348) } -inst_vpunpckldq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1348) } -inst_vpunpckldq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1349) } -inst_vpunpckldq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1349) } +inst_vpunpckldq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1360) } +inst_vpunpckldq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1360) } +inst_vpunpckldq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1361) } +inst_vpunpckldq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1361) } emit_vpunpckldq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpckldq_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpckldq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpckldq_xmm_xmm_m128(dst, src, src2)) } emit_vpunpckldq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpckldq_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpckldq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpckldq_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpcklqdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1350) } -inst_vpunpcklqdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1350) } -inst_vpunpcklqdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1351) } -inst_vpunpcklqdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1351) } +inst_vpunpcklqdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1362) } +inst_vpunpcklqdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1362) } +inst_vpunpcklqdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1363) } +inst_vpunpcklqdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKLQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1363) } emit_vpunpcklqdq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpcklqdq_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpcklqdq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpcklqdq_xmm_xmm_m128(dst, src, src2)) } emit_vpunpcklqdq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpcklqdq_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpcklqdq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpcklqdq_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpckhbw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1352) } -inst_vpunpckhbw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1352) } -inst_vpunpckhbw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1353) } -inst_vpunpckhbw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1353) } +inst_vpunpckhbw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1364) } +inst_vpunpckhbw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1364) } +inst_vpunpckhbw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1365) } +inst_vpunpckhbw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1365) } emit_vpunpckhbw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpckhbw_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpckhbw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpckhbw_xmm_xmm_m128(dst, src, src2)) } emit_vpunpckhbw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpckhbw_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpckhbw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpckhbw_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpckhwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1354) } -inst_vpunpckhwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1354) } -inst_vpunpckhwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1355) } -inst_vpunpckhwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1355) } +inst_vpunpckhwd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1366) } +inst_vpunpckhwd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1366) } +inst_vpunpckhwd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1367) } +inst_vpunpckhwd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHWD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1367) } emit_vpunpckhwd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpckhwd_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpckhwd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpckhwd_xmm_xmm_m128(dst, src, src2)) } emit_vpunpckhwd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpckhwd_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpckhwd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpckhwd_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpckhdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1356) } -inst_vpunpckhdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1356) } -inst_vpunpckhdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1357) } -inst_vpunpckhdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1357) } +inst_vpunpckhdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1368) } +inst_vpunpckhdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1368) } +inst_vpunpckhdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1369) } +inst_vpunpckhdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1369) } emit_vpunpckhdq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpckhdq_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpckhdq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpckhdq_xmm_xmm_m128(dst, src, src2)) } emit_vpunpckhdq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpckhdq_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpckhdq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpckhdq_ymm_ymm_m256(dst, src, src2)) } -inst_vpunpckhqdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1358) } -inst_vpunpckhqdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1358) } -inst_vpunpckhqdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1359) } -inst_vpunpckhqdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1359) } +inst_vpunpckhqdq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1370) } +inst_vpunpckhqdq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1370) } +inst_vpunpckhqdq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1371) } +inst_vpunpckhqdq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPUNPCKHQDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1371) } emit_vpunpckhqdq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpunpckhqdq_xmm_xmm_xmm(dst, src, src2)) } emit_vpunpckhqdq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpunpckhqdq_xmm_xmm_m128(dst, src, src2)) } emit_vpunpckhqdq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpunpckhqdq_ymm_ymm_ymm(dst, src, src2)) } emit_vpunpckhqdq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpunpckhqdq_ymm_ymm_m256(dst, src, src2)) } -inst_vpshufd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1360) } -inst_vpshufd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1360) } -inst_vpshufd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1361) } -inst_vpshufd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1361) } +inst_vpshufd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1372) } +inst_vpshufd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1372) } +inst_vpshufd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1373) } +inst_vpshufd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1373) } emit_vpshufd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpshufd_xmm_xmm_imm8(dst, src, imm)) } emit_vpshufd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpshufd_xmm_m128_imm8(dst, src, imm)) } emit_vpshufd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpshufd_ymm_ymm_imm8(dst, src, imm)) } emit_vpshufd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vpshufd_ymm_m256_imm8(dst, src, imm)) } -inst_vpshufhw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1362) } -inst_vpshufhw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1362) } -inst_vpshufhw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1363) } -inst_vpshufhw_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1363) } +inst_vpshufhw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1374) } +inst_vpshufhw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1374) } +inst_vpshufhw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1375) } +inst_vpshufhw_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFHW, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1375) } emit_vpshufhw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpshufhw_xmm_xmm_imm8(dst, src, imm)) } emit_vpshufhw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpshufhw_xmm_m128_imm8(dst, src, imm)) } emit_vpshufhw_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpshufhw_ymm_ymm_imm8(dst, src, imm)) } emit_vpshufhw_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vpshufhw_ymm_m256_imm8(dst, src, imm)) } -inst_vpshuflw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1364) } -inst_vpshuflw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1364) } -inst_vpshuflw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1365) } -inst_vpshuflw_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1365) } +inst_vpshuflw_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1376) } +inst_vpshuflw_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1376) } +inst_vpshuflw_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1377) } +inst_vpshuflw_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFLW, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1377) } emit_vpshuflw_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vpshuflw_xmm_xmm_imm8(dst, src, imm)) } emit_vpshuflw_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vpshuflw_xmm_m128_imm8(dst, src, imm)) } emit_vpshuflw_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpshuflw_ymm_ymm_imm8(dst, src, imm)) } emit_vpshuflw_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vpshuflw_ymm_m256_imm8(dst, src, imm)) } -inst_vpextrb_r8_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRB, operand_count = 3, ops = {op_gpr8(dst), op_xmm(src), op_imm8(imm), {}} }, 1366) } -inst_vpextrb_m8_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRB, operand_count = 3, ops = {op_mem(dst.mem, 1), op_xmm(src), op_imm8(imm), {}} }, 1366) } +inst_vpextrb_r8_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRB, operand_count = 3, ops = {op_gpr8(dst), op_xmm(src), op_imm8(imm), {}} }, 1378) } +inst_vpextrb_m8_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem8, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRB, operand_count = 3, ops = {op_mem(dst.mem, 1), op_xmm(src), op_imm8(imm), {}} }, 1378) } emit_vpextrb_r8_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, src: XMM, imm: i8) { append(instructions, inst_vpextrb_r8_xmm_imm8(dst, src, imm)) } emit_vpextrb_m8_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, src: XMM, imm: i8) { append(instructions, inst_vpextrb_m8_xmm_imm8(dst, src, imm)) } -inst_vpextrw_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1367) } -inst_vpextrw_r16_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_gpr16(dst), op_xmm(src), op_imm8(imm), {}} }, 1368) } -inst_vpextrw_m16_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_mem(dst.mem, 2), op_xmm(src), op_imm8(imm), {}} }, 1368) } +inst_vpextrw_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1379) } +inst_vpextrw_r16_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR16, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_gpr16(dst), op_xmm(src), op_imm8(imm), {}} }, 1380) } +inst_vpextrw_m16_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem16, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRW, operand_count = 3, ops = {op_mem(dst.mem, 2), op_xmm(src), op_imm8(imm), {}} }, 1380) } emit_vpextrw_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_vpextrw_r32_xmm_imm8(dst, src, imm)) } emit_vpextrw_r16_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: XMM, imm: i8) { append(instructions, inst_vpextrw_r16_xmm_imm8(dst, src, imm)) } emit_vpextrw_m16_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: XMM, imm: i8) { append(instructions, inst_vpextrw_m16_xmm_imm8(dst, src, imm)) } -inst_vpextrd_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRD, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1369) } -inst_vpextrd_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 1369) } +inst_vpextrd_r32_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRD, operand_count = 3, ops = {op_gpr32(dst), op_xmm(src), op_imm8(imm), {}} }, 1381) } +inst_vpextrd_m32_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem32, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRD, operand_count = 3, ops = {op_mem(dst.mem, 4), op_xmm(src), op_imm8(imm), {}} }, 1381) } emit_vpextrd_r32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM, imm: i8) { append(instructions, inst_vpextrd_r32_xmm_imm8(dst, src, imm)) } emit_vpextrd_m32_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM, imm: i8) { append(instructions, inst_vpextrd_m32_xmm_imm8(dst, src, imm)) } -inst_vpextrq_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRQ, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 1370) } -inst_vpextrq_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRQ, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 1370) } +inst_vpextrq_r64_xmm_imm8 :: #force_inline proc "contextless" (dst: GPR64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRQ, operand_count = 3, ops = {op_gpr64(dst), op_xmm(src), op_imm8(imm), {}} }, 1382) } +inst_vpextrq_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXTRQ, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 1382) } emit_vpextrq_r64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: XMM, imm: i8) { append(instructions, inst_vpextrq_r64_xmm_imm8(dst, src, imm)) } emit_vpextrq_m64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM, imm: i8) { append(instructions, inst_vpextrq_m64_xmm_imm8(dst, src, imm)) } -inst_vpinsrb_xmm_xmm_r8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr8(src2), op_imm8(imm)} }, 1371) } -inst_vpinsrb_xmm_xmm_m8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 1), op_imm8(imm)} }, 1371) } +inst_vpinsrb_xmm_xmm_r8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr8(src2), op_imm8(imm)} }, 1383) } +inst_vpinsrb_xmm_xmm_m8_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem8, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 1), op_imm8(imm)} }, 1383) } emit_vpinsrb_xmm_xmm_r8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR8, imm: i8) { append(instructions, inst_vpinsrb_xmm_xmm_r8_imm8(dst, src, src2, imm)) } emit_vpinsrb_xmm_xmm_m8_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem8, imm: i8) { append(instructions, inst_vpinsrb_xmm_xmm_m8_imm8(dst, src, src2, imm)) } -inst_vpinsrw_xmm_xmm_r16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr16(src2), op_imm8(imm)} }, 1372) } -inst_vpinsrw_xmm_xmm_m16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 2), op_imm8(imm)} }, 1372) } +inst_vpinsrw_xmm_xmm_r16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr16(src2), op_imm8(imm)} }, 1384) } +inst_vpinsrw_xmm_xmm_m16_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem16, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 2), op_imm8(imm)} }, 1384) } emit_vpinsrw_xmm_xmm_r16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR16, imm: i8) { append(instructions, inst_vpinsrw_xmm_xmm_r16_imm8(dst, src, src2, imm)) } emit_vpinsrw_xmm_xmm_m16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem16, imm: i8) { append(instructions, inst_vpinsrw_xmm_xmm_m16_imm8(dst, src, src2, imm)) } -inst_vpinsrd_xmm_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), op_imm8(imm)} }, 1373) } -inst_vpinsrd_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1373) } +inst_vpinsrd_xmm_xmm_r32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr32(src2), op_imm8(imm)} }, 1385) } +inst_vpinsrd_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1385) } emit_vpinsrd_xmm_xmm_r32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR32, imm: i8) { append(instructions, inst_vpinsrd_xmm_xmm_r32_imm8(dst, src, src2, imm)) } emit_vpinsrd_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vpinsrd_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vpinsrq_xmm_xmm_r64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), op_imm8(imm)} }, 1374) } -inst_vpinsrq_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1374) } +inst_vpinsrq_xmm_xmm_r64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: GPR64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_gpr64(src2), op_imm8(imm)} }, 1386) } +inst_vpinsrq_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPINSRQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1386) } emit_vpinsrq_xmm_xmm_r64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: GPR64, imm: i8) { append(instructions, inst_vpinsrq_xmm_xmm_r64_imm8(dst, src, src2, imm)) } emit_vpinsrq_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vpinsrq_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vpmovmskb_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1375) } -inst_vpmovmskb_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1376) } +inst_vpmovmskb_r32_xmm :: #force_inline proc "contextless" (dst: GPR32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_xmm(src), {}, {}} }, 1387) } +inst_vpmovmskb_r32_ymm :: #force_inline proc "contextless" (dst: GPR32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVMSKB, operand_count = 2, ops = {op_gpr32(dst), op_ymm(src), {}, {}} }, 1388) } emit_vpmovmskb_r32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: XMM) { append(instructions, inst_vpmovmskb_r32_xmm(dst, src)) } emit_vpmovmskb_r32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: YMM) { append(instructions, inst_vpmovmskb_r32_ymm(dst, src)) } -inst_vptest_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1377) } -inst_vptest_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1377) } -inst_vptest_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1378) } -inst_vptest_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1378) } +inst_vptest_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1389) } +inst_vptest_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1389) } +inst_vptest_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1390) } +inst_vptest_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTEST, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1390) } emit_vptest_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vptest_xmm_xmm(dst, src)) } emit_vptest_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vptest_xmm_m128(dst, src)) } emit_vptest_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vptest_ymm_ymm(dst, src)) } emit_vptest_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vptest_ymm_m256(dst, src)) } -inst_vpshufb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1379) } -inst_vpshufb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1379) } -inst_vpshufb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1380) } -inst_vpshufb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1380) } +inst_vpshufb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1391) } +inst_vpshufb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1391) } +inst_vpshufb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1392) } +inst_vpshufb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSHUFB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1392) } emit_vpshufb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpshufb_xmm_xmm_xmm(dst, src, src2)) } emit_vpshufb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpshufb_xmm_xmm_m128(dst, src, src2)) } emit_vpshufb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpshufb_ymm_ymm_ymm(dst, src, src2)) } emit_vpshufb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpshufb_ymm_ymm_m256(dst, src, src2)) } -inst_vphaddw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1381) } -inst_vphaddw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1381) } -inst_vphaddw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1382) } -inst_vphaddw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1382) } +inst_vphaddw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1393) } +inst_vphaddw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1393) } +inst_vphaddw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1394) } +inst_vphaddw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1394) } emit_vphaddw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphaddw_xmm_xmm_xmm(dst, src, src2)) } emit_vphaddw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphaddw_xmm_xmm_m128(dst, src, src2)) } emit_vphaddw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphaddw_ymm_ymm_ymm(dst, src, src2)) } emit_vphaddw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphaddw_ymm_ymm_m256(dst, src, src2)) } -inst_vphaddd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1383) } -inst_vphaddd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1383) } -inst_vphaddd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1384) } -inst_vphaddd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1384) } +inst_vphaddd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1395) } +inst_vphaddd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1395) } +inst_vphaddd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1396) } +inst_vphaddd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1396) } emit_vphaddd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphaddd_xmm_xmm_xmm(dst, src, src2)) } emit_vphaddd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphaddd_xmm_xmm_m128(dst, src, src2)) } emit_vphaddd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphaddd_ymm_ymm_ymm(dst, src, src2)) } emit_vphaddd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphaddd_ymm_ymm_m256(dst, src, src2)) } -inst_vphaddsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1385) } -inst_vphaddsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1385) } -inst_vphaddsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1386) } -inst_vphaddsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1386) } +inst_vphaddsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1397) } +inst_vphaddsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1397) } +inst_vphaddsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1398) } +inst_vphaddsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHADDSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1398) } emit_vphaddsw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphaddsw_xmm_xmm_xmm(dst, src, src2)) } emit_vphaddsw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphaddsw_xmm_xmm_m128(dst, src, src2)) } emit_vphaddsw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphaddsw_ymm_ymm_ymm(dst, src, src2)) } emit_vphaddsw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphaddsw_ymm_ymm_m256(dst, src, src2)) } -inst_vphsubw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1387) } -inst_vphsubw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1387) } -inst_vphsubw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1388) } -inst_vphsubw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1388) } +inst_vphsubw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1399) } +inst_vphsubw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1399) } +inst_vphsubw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1400) } +inst_vphsubw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1400) } emit_vphsubw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphsubw_xmm_xmm_xmm(dst, src, src2)) } emit_vphsubw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphsubw_xmm_xmm_m128(dst, src, src2)) } emit_vphsubw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphsubw_ymm_ymm_ymm(dst, src, src2)) } emit_vphsubw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphsubw_ymm_ymm_m256(dst, src, src2)) } -inst_vphsubd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1389) } -inst_vphsubd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1389) } -inst_vphsubd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1390) } -inst_vphsubd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1390) } +inst_vphsubd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1401) } +inst_vphsubd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1401) } +inst_vphsubd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1402) } +inst_vphsubd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1402) } emit_vphsubd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphsubd_xmm_xmm_xmm(dst, src, src2)) } emit_vphsubd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphsubd_xmm_xmm_m128(dst, src, src2)) } emit_vphsubd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphsubd_ymm_ymm_ymm(dst, src, src2)) } emit_vphsubd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphsubd_ymm_ymm_m256(dst, src, src2)) } -inst_vphsubsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1391) } -inst_vphsubsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1391) } -inst_vphsubsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1392) } -inst_vphsubsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1392) } +inst_vphsubsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1403) } +inst_vphsubsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1403) } +inst_vphsubsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1404) } +inst_vphsubsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHSUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1404) } emit_vphsubsw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vphsubsw_xmm_xmm_xmm(dst, src, src2)) } emit_vphsubsw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vphsubsw_xmm_xmm_m128(dst, src, src2)) } emit_vphsubsw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vphsubsw_ymm_ymm_ymm(dst, src, src2)) } emit_vphsubsw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vphsubsw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaddubsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1393) } -inst_vpmaddubsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1393) } -inst_vpmaddubsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1394) } -inst_vpmaddubsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1394) } +inst_vpmaddubsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1405) } +inst_vpmaddubsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1405) } +inst_vpmaddubsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1406) } +inst_vpmaddubsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMADDUBSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1406) } emit_vpmaddubsw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaddubsw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaddubsw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaddubsw_xmm_xmm_m128(dst, src, src2)) } emit_vpmaddubsw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaddubsw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaddubsw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaddubsw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmulhrsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1395) } -inst_vpmulhrsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1395) } -inst_vpmulhrsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1396) } -inst_vpmulhrsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1396) } +inst_vpmulhrsw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1407) } +inst_vpmulhrsw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1407) } +inst_vpmulhrsw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1408) } +inst_vpmulhrsw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULHRSW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1408) } emit_vpmulhrsw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmulhrsw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmulhrsw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmulhrsw_xmm_xmm_m128(dst, src, src2)) } emit_vpmulhrsw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmulhrsw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmulhrsw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmulhrsw_ymm_ymm_m256(dst, src, src2)) } -inst_vpsignb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1397) } -inst_vpsignb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1397) } -inst_vpsignb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1398) } -inst_vpsignb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1398) } +inst_vpsignb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1409) } +inst_vpsignb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1409) } +inst_vpsignb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1410) } +inst_vpsignb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1410) } emit_vpsignb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsignb_xmm_xmm_xmm(dst, src, src2)) } emit_vpsignb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsignb_xmm_xmm_m128(dst, src, src2)) } emit_vpsignb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsignb_ymm_ymm_ymm(dst, src, src2)) } emit_vpsignb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsignb_ymm_ymm_m256(dst, src, src2)) } -inst_vpsignw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1399) } -inst_vpsignw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1399) } -inst_vpsignw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1400) } -inst_vpsignw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1400) } +inst_vpsignw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1411) } +inst_vpsignw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1411) } +inst_vpsignw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1412) } +inst_vpsignw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGNW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1412) } emit_vpsignw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsignw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsignw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsignw_xmm_xmm_m128(dst, src, src2)) } emit_vpsignw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsignw_ymm_ymm_ymm(dst, src, src2)) } emit_vpsignw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsignw_ymm_ymm_m256(dst, src, src2)) } -inst_vpsignd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1401) } -inst_vpsignd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1401) } -inst_vpsignd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1402) } -inst_vpsignd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1402) } +inst_vpsignd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1413) } +inst_vpsignd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1413) } +inst_vpsignd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1414) } +inst_vpsignd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSIGND, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1414) } emit_vpsignd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsignd_xmm_xmm_xmm(dst, src, src2)) } emit_vpsignd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsignd_xmm_xmm_m128(dst, src, src2)) } emit_vpsignd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsignd_ymm_ymm_ymm(dst, src, src2)) } emit_vpsignd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsignd_ymm_ymm_m256(dst, src, src2)) } -inst_vpabsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1403) } -inst_vpabsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1403) } -inst_vpabsb_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1404) } -inst_vpabsb_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1404) } +inst_vpabsb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1415) } +inst_vpabsb_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1415) } +inst_vpabsb_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1416) } +inst_vpabsb_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSB, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1416) } emit_vpabsb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpabsb_xmm_xmm(dst, src)) } emit_vpabsb_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpabsb_xmm_m128(dst, src)) } emit_vpabsb_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpabsb_ymm_ymm(dst, src)) } emit_vpabsb_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpabsb_ymm_m256(dst, src)) } -inst_vpabsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1405) } -inst_vpabsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1405) } -inst_vpabsw_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1406) } -inst_vpabsw_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1406) } +inst_vpabsw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1417) } +inst_vpabsw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1417) } +inst_vpabsw_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1418) } +inst_vpabsw_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1418) } emit_vpabsw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpabsw_xmm_xmm(dst, src)) } emit_vpabsw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpabsw_xmm_m128(dst, src)) } emit_vpabsw_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpabsw_ymm_ymm(dst, src)) } emit_vpabsw_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpabsw_ymm_m256(dst, src)) } -inst_vpabsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1407) } -inst_vpabsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1407) } -inst_vpabsd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1408) } -inst_vpabsd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1408) } +inst_vpabsd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1419) } +inst_vpabsd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1419) } +inst_vpabsd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1420) } +inst_vpabsd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPABSD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1420) } emit_vpabsd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpabsd_xmm_xmm(dst, src)) } emit_vpabsd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpabsd_xmm_m128(dst, src)) } emit_vpabsd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpabsd_ymm_ymm(dst, src)) } emit_vpabsd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpabsd_ymm_m256(dst, src)) } -inst_vpalignr_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1409) } -inst_vpalignr_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1409) } -inst_vpalignr_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1410) } -inst_vpalignr_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1410) } +inst_vpalignr_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1421) } +inst_vpalignr_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1421) } +inst_vpalignr_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1422) } +inst_vpalignr_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPALIGNR, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1422) } emit_vpalignr_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpalignr_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpalignr_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpalignr_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpalignr_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpalignr_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpalignr_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpalignr_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vpblendw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1411) } -inst_vpblendw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1411) } -inst_vpblendw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1412) } -inst_vpblendw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1412) } +inst_vpblendw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1423) } +inst_vpblendw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1423) } +inst_vpblendw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1424) } +inst_vpblendw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1424) } emit_vpblendw_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpblendw_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpblendw_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpblendw_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpblendw_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpblendw_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpblendw_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpblendw_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vpblendvb_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1413) } -inst_vpblendvb_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1413) } -inst_vpblendvb_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1414) } -inst_vpblendvb_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1414) } +inst_vpblendvb_xmm_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_xmm(src3)} }, 1425) } +inst_vpblendvb_xmm_xmm_m128_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, src3: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_xmm(src3)} }, 1425) } +inst_vpblendvb_ymm_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_ymm(src3)} }, 1426) } +inst_vpblendvb_ymm_ymm_m256_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, src3: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDVB, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_ymm(src3)} }, 1426) } emit_vpblendvb_xmm_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, src3: XMM) { append(instructions, inst_vpblendvb_xmm_xmm_xmm_xmm(dst, src, src2, src3)) } emit_vpblendvb_xmm_xmm_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, src3: XMM) { append(instructions, inst_vpblendvb_xmm_xmm_m128_xmm(dst, src, src2, src3)) } emit_vpblendvb_ymm_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, src3: YMM) { append(instructions, inst_vpblendvb_ymm_ymm_ymm_ymm(dst, src, src2, src3)) } emit_vpblendvb_ymm_ymm_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, src3: YMM) { append(instructions, inst_vpblendvb_ymm_ymm_m256_ymm(dst, src, src2, src3)) } -inst_vmpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1415) } -inst_vmpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1415) } -inst_vmpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1416) } -inst_vmpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1416) } +inst_vmpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1427) } +inst_vmpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1427) } +inst_vmpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1428) } +inst_vmpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1428) } emit_vmpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vmpsadbw_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vmpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vmpsadbw_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vmpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vmpsadbw_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vmpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vmpsadbw_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vphminposuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1417) } -inst_vphminposuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1417) } +inst_vphminposuw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1429) } +inst_vphminposuw_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPHMINPOSUW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1429) } emit_vphminposuw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vphminposuw_xmm_xmm(dst, src)) } emit_vphminposuw_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vphminposuw_xmm_m128(dst, src)) } -inst_vpmaxsb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1418) } -inst_vpmaxsb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1418) } -inst_vpmaxsb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1419) } -inst_vpmaxsb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1419) } +inst_vpmaxsb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1430) } +inst_vpmaxsb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1430) } +inst_vpmaxsb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1431) } +inst_vpmaxsb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1431) } emit_vpmaxsb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaxsb_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaxsb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaxsb_xmm_xmm_m128(dst, src, src2)) } emit_vpmaxsb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaxsb_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaxsb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaxsb_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaxsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1420) } -inst_vpmaxsd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1420) } -inst_vpmaxsd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1421) } -inst_vpmaxsd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1421) } +inst_vpmaxsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1432) } +inst_vpmaxsd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1432) } +inst_vpmaxsd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1433) } +inst_vpmaxsd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1433) } emit_vpmaxsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaxsd_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaxsd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaxsd_xmm_xmm_m128(dst, src, src2)) } emit_vpmaxsd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaxsd_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaxsd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaxsd_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaxuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1422) } -inst_vpmaxuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1422) } -inst_vpmaxuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1423) } -inst_vpmaxuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1423) } +inst_vpmaxuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1434) } +inst_vpmaxuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1434) } +inst_vpmaxuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1435) } +inst_vpmaxuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1435) } emit_vpmaxuw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaxuw_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaxuw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaxuw_xmm_xmm_m128(dst, src, src2)) } emit_vpmaxuw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaxuw_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaxuw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaxuw_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaxud_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1424) } -inst_vpmaxud_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1424) } -inst_vpmaxud_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1425) } -inst_vpmaxud_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1425) } +inst_vpmaxud_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1436) } +inst_vpmaxud_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1436) } +inst_vpmaxud_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1437) } +inst_vpmaxud_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMAXUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1437) } emit_vpmaxud_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmaxud_xmm_xmm_xmm(dst, src, src2)) } emit_vpmaxud_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaxud_xmm_xmm_m128(dst, src, src2)) } emit_vpmaxud_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmaxud_ymm_ymm_ymm(dst, src, src2)) } emit_vpmaxud_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaxud_ymm_ymm_m256(dst, src, src2)) } -inst_vpminsb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1426) } -inst_vpminsb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1426) } -inst_vpminsb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1427) } -inst_vpminsb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1427) } +inst_vpminsb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1438) } +inst_vpminsb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1438) } +inst_vpminsb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1439) } +inst_vpminsb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1439) } emit_vpminsb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpminsb_xmm_xmm_xmm(dst, src, src2)) } emit_vpminsb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpminsb_xmm_xmm_m128(dst, src, src2)) } emit_vpminsb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpminsb_ymm_ymm_ymm(dst, src, src2)) } emit_vpminsb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpminsb_ymm_ymm_m256(dst, src, src2)) } -inst_vpminsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1428) } -inst_vpminsd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1428) } -inst_vpminsd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1429) } -inst_vpminsd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1429) } +inst_vpminsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1440) } +inst_vpminsd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1440) } +inst_vpminsd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1441) } +inst_vpminsd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1441) } emit_vpminsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpminsd_xmm_xmm_xmm(dst, src, src2)) } emit_vpminsd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpminsd_xmm_xmm_m128(dst, src, src2)) } emit_vpminsd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpminsd_ymm_ymm_ymm(dst, src, src2)) } emit_vpminsd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpminsd_ymm_ymm_m256(dst, src, src2)) } -inst_vpminuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1430) } -inst_vpminuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1430) } -inst_vpminuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1431) } -inst_vpminuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1431) } +inst_vpminuw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1442) } +inst_vpminuw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1442) } +inst_vpminuw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1443) } +inst_vpminuw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1443) } emit_vpminuw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpminuw_xmm_xmm_xmm(dst, src, src2)) } emit_vpminuw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpminuw_xmm_xmm_m128(dst, src, src2)) } emit_vpminuw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpminuw_ymm_ymm_ymm(dst, src, src2)) } emit_vpminuw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpminuw_ymm_ymm_m256(dst, src, src2)) } -inst_vpminud_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1432) } -inst_vpminud_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1432) } -inst_vpminud_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1433) } -inst_vpminud_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1433) } +inst_vpminud_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1444) } +inst_vpminud_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1444) } +inst_vpminud_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1445) } +inst_vpminud_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMINUD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1445) } emit_vpminud_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpminud_xmm_xmm_xmm(dst, src, src2)) } emit_vpminud_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpminud_xmm_xmm_m128(dst, src, src2)) } emit_vpminud_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpminud_ymm_ymm_ymm(dst, src, src2)) } emit_vpminud_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpminud_ymm_ymm_m256(dst, src, src2)) } -inst_vpmovsxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1434) } -inst_vpmovsxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1434) } -inst_vpmovsxbw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1435) } -inst_vpmovsxbw_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1435) } +inst_vpmovsxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1446) } +inst_vpmovsxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1446) } +inst_vpmovsxbw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1447) } +inst_vpmovsxbw_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1447) } emit_vpmovsxbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxbw_xmm_xmm(dst, src)) } emit_vpmovsxbw_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovsxbw_xmm_m64(dst, src)) } emit_vpmovsxbw_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxbw_ymm_xmm(dst, src)) } emit_vpmovsxbw_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovsxbw_ymm_m128(dst, src)) } -inst_vpmovsxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1436) } -inst_vpmovsxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1436) } -inst_vpmovsxbd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1437) } -inst_vpmovsxbd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1437) } +inst_vpmovsxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1448) } +inst_vpmovsxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1448) } +inst_vpmovsxbd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1449) } +inst_vpmovsxbd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1449) } emit_vpmovsxbd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxbd_xmm_xmm(dst, src)) } emit_vpmovsxbd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vpmovsxbd_xmm_m32(dst, src)) } emit_vpmovsxbd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxbd_ymm_xmm(dst, src)) } emit_vpmovsxbd_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vpmovsxbd_ymm_m64(dst, src)) } -inst_vpmovsxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1438) } -inst_vpmovsxbq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1439) } -inst_vpmovsxbq_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1439) } +inst_vpmovsxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1450) } +inst_vpmovsxbq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1451) } +inst_vpmovsxbq_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXBQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1451) } emit_vpmovsxbq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxbq_xmm_xmm(dst, src)) } emit_vpmovsxbq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxbq_ymm_xmm(dst, src)) } emit_vpmovsxbq_ymm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem32) { append(instructions, inst_vpmovsxbq_ymm_m32(dst, src)) } -inst_vpmovsxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1440) } -inst_vpmovsxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1440) } -inst_vpmovsxwd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1441) } -inst_vpmovsxwd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1441) } +inst_vpmovsxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1452) } +inst_vpmovsxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1452) } +inst_vpmovsxwd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1453) } +inst_vpmovsxwd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1453) } emit_vpmovsxwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxwd_xmm_xmm(dst, src)) } emit_vpmovsxwd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovsxwd_xmm_m64(dst, src)) } emit_vpmovsxwd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxwd_ymm_xmm(dst, src)) } emit_vpmovsxwd_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovsxwd_ymm_m128(dst, src)) } -inst_vpmovsxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1442) } -inst_vpmovsxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1442) } -inst_vpmovsxwq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1443) } -inst_vpmovsxwq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1443) } +inst_vpmovsxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1454) } +inst_vpmovsxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1454) } +inst_vpmovsxwq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1455) } +inst_vpmovsxwq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXWQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1455) } emit_vpmovsxwq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxwq_xmm_xmm(dst, src)) } emit_vpmovsxwq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vpmovsxwq_xmm_m32(dst, src)) } emit_vpmovsxwq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxwq_ymm_xmm(dst, src)) } emit_vpmovsxwq_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vpmovsxwq_ymm_m64(dst, src)) } -inst_vpmovsxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1444) } -inst_vpmovsxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1444) } -inst_vpmovsxdq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1445) } -inst_vpmovsxdq_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1445) } +inst_vpmovsxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1456) } +inst_vpmovsxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1456) } +inst_vpmovsxdq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1457) } +inst_vpmovsxdq_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSXDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1457) } emit_vpmovsxdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsxdq_xmm_xmm(dst, src)) } emit_vpmovsxdq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovsxdq_xmm_m64(dst, src)) } emit_vpmovsxdq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovsxdq_ymm_xmm(dst, src)) } emit_vpmovsxdq_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovsxdq_ymm_m128(dst, src)) } -inst_vpmovzxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1446) } -inst_vpmovzxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1446) } -inst_vpmovzxbw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1447) } -inst_vpmovzxbw_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1447) } +inst_vpmovzxbw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1458) } +inst_vpmovzxbw_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1458) } +inst_vpmovzxbw_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1459) } +inst_vpmovzxbw_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBW, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1459) } emit_vpmovzxbw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxbw_xmm_xmm(dst, src)) } emit_vpmovzxbw_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovzxbw_xmm_m64(dst, src)) } emit_vpmovzxbw_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxbw_ymm_xmm(dst, src)) } emit_vpmovzxbw_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovzxbw_ymm_m128(dst, src)) } -inst_vpmovzxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1448) } -inst_vpmovzxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1448) } -inst_vpmovzxbd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1449) } -inst_vpmovzxbd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1449) } +inst_vpmovzxbd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1460) } +inst_vpmovzxbd_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1460) } +inst_vpmovzxbd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1461) } +inst_vpmovzxbd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1461) } emit_vpmovzxbd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxbd_xmm_xmm(dst, src)) } emit_vpmovzxbd_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vpmovzxbd_xmm_m32(dst, src)) } emit_vpmovzxbd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxbd_ymm_xmm(dst, src)) } emit_vpmovzxbd_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vpmovzxbd_ymm_m64(dst, src)) } -inst_vpmovzxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1450) } -inst_vpmovzxbq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1451) } -inst_vpmovzxbq_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1451) } +inst_vpmovzxbq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1462) } +inst_vpmovzxbq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1463) } +inst_vpmovzxbq_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXBQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1463) } emit_vpmovzxbq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxbq_xmm_xmm(dst, src)) } emit_vpmovzxbq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxbq_ymm_xmm(dst, src)) } emit_vpmovzxbq_ymm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem32) { append(instructions, inst_vpmovzxbq_ymm_m32(dst, src)) } -inst_vpmovzxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1452) } -inst_vpmovzxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1452) } -inst_vpmovzxwd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1453) } -inst_vpmovzxwd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1453) } +inst_vpmovzxwd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1464) } +inst_vpmovzxwd_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1464) } +inst_vpmovzxwd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1465) } +inst_vpmovzxwd_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1465) } emit_vpmovzxwd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxwd_xmm_xmm(dst, src)) } emit_vpmovzxwd_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovzxwd_xmm_m64(dst, src)) } emit_vpmovzxwd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxwd_ymm_xmm(dst, src)) } emit_vpmovzxwd_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovzxwd_ymm_m128(dst, src)) } -inst_vpmovzxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1454) } -inst_vpmovzxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1454) } -inst_vpmovzxwq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1455) } -inst_vpmovzxwq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1455) } +inst_vpmovzxwq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1466) } +inst_vpmovzxwq_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1466) } +inst_vpmovzxwq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1467) } +inst_vpmovzxwq_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXWQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1467) } emit_vpmovzxwq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxwq_xmm_xmm(dst, src)) } emit_vpmovzxwq_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vpmovzxwq_xmm_m32(dst, src)) } emit_vpmovzxwq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxwq_ymm_xmm(dst, src)) } emit_vpmovzxwq_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vpmovzxwq_ymm_m64(dst, src)) } -inst_vpmovzxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1456) } -inst_vpmovzxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1456) } -inst_vpmovzxdq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1457) } -inst_vpmovzxdq_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1457) } +inst_vpmovzxdq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1468) } +inst_vpmovzxdq_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1468) } +inst_vpmovzxdq_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1469) } +inst_vpmovzxdq_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVZXDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1469) } emit_vpmovzxdq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovzxdq_xmm_xmm(dst, src)) } emit_vpmovzxdq_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vpmovzxdq_xmm_m64(dst, src)) } emit_vpmovzxdq_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vpmovzxdq_ymm_xmm(dst, src)) } emit_vpmovzxdq_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vpmovzxdq_ymm_m128(dst, src)) } -inst_vpmuldq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1458) } -inst_vpmuldq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1458) } -inst_vpmuldq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1459) } -inst_vpmuldq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1459) } +inst_vpmuldq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1470) } +inst_vpmuldq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1470) } +inst_vpmuldq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1471) } +inst_vpmuldq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULDQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1471) } emit_vpmuldq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmuldq_xmm_xmm_xmm(dst, src, src2)) } emit_vpmuldq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmuldq_xmm_xmm_m128(dst, src, src2)) } emit_vpmuldq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmuldq_ymm_ymm_ymm(dst, src, src2)) } emit_vpmuldq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmuldq_ymm_ymm_m256(dst, src, src2)) } -inst_vpmulld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1460) } -inst_vpmulld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1460) } -inst_vpmulld_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1461) } -inst_vpmulld_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1461) } +inst_vpmulld_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1472) } +inst_vpmulld_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1472) } +inst_vpmulld_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1473) } +inst_vpmulld_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1473) } emit_vpmulld_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmulld_xmm_xmm_xmm(dst, src, src2)) } emit_vpmulld_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmulld_xmm_xmm_m128(dst, src, src2)) } emit_vpmulld_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmulld_ymm_ymm_ymm(dst, src, src2)) } emit_vpmulld_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmulld_ymm_ymm_m256(dst, src, src2)) } -inst_vmaskmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1462) } +inst_vmaskmovdqu_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVDQU, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1474) } emit_vmaskmovdqu_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmaskmovdqu_xmm_xmm(dst, src)) } -inst_vpclmulqdq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1463) } -inst_vpclmulqdq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1463) } -inst_vpclmulqdq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1464) } -inst_vpclmulqdq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1464) } +inst_vpclmulqdq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1475) } +inst_vpclmulqdq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1475) } +inst_vpclmulqdq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1476) } +inst_vpclmulqdq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCLMULQDQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1476) } emit_vpclmulqdq_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpclmulqdq_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpclmulqdq_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpclmulqdq_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpclmulqdq_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpclmulqdq_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpclmulqdq_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpclmulqdq_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vaesdec_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDEC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1465) } -inst_vaesdec_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDEC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1465) } +inst_vaesdec_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDEC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1477) } +inst_vaesdec_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDEC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1477) } emit_vaesdec_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaesdec_xmm_xmm_xmm(dst, src, src2)) } emit_vaesdec_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaesdec_xmm_xmm_m128(dst, src, src2)) } -inst_vaesdeclast_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDECLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1466) } -inst_vaesdeclast_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDECLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1466) } +inst_vaesdeclast_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDECLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1478) } +inst_vaesdeclast_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESDECLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1478) } emit_vaesdeclast_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaesdeclast_xmm_xmm_xmm(dst, src, src2)) } emit_vaesdeclast_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaesdeclast_xmm_xmm_m128(dst, src, src2)) } -inst_vaesenc_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1467) } -inst_vaesenc_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1467) } +inst_vaesenc_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1479) } +inst_vaesenc_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENC, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1479) } emit_vaesenc_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaesenc_xmm_xmm_xmm(dst, src, src2)) } emit_vaesenc_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaesenc_xmm_xmm_m128(dst, src, src2)) } -inst_vaesenclast_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENCLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1468) } -inst_vaesenclast_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENCLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1468) } +inst_vaesenclast_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENCLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1480) } +inst_vaesenclast_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESENCLAST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1480) } emit_vaesenclast_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vaesenclast_xmm_xmm_xmm(dst, src, src2)) } emit_vaesenclast_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vaesenclast_xmm_xmm_m128(dst, src, src2)) } -inst_vaesimc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESIMC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1469) } -inst_vaesimc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESIMC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1469) } +inst_vaesimc_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESIMC, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1481) } +inst_vaesimc_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESIMC, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1481) } emit_vaesimc_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vaesimc_xmm_xmm(dst, src)) } emit_vaesimc_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vaesimc_xmm_m128(dst, src)) } -inst_vaeskeygenassist_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1470) } -inst_vaeskeygenassist_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1470) } +inst_vaeskeygenassist_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1482) } +inst_vaeskeygenassist_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VAESKEYGENASSIST, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1482) } emit_vaeskeygenassist_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vaeskeygenassist_xmm_xmm_imm8(dst, src, imm)) } emit_vaeskeygenassist_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vaeskeygenassist_xmm_m128_imm8(dst, src, imm)) } -inst_vbroadcastss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1471) } -inst_vbroadcastss_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1472) } -inst_vbroadcastss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1473) } -inst_vbroadcastss_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1474) } +inst_vbroadcastss_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 4), {}, {}} }, 1483) } +inst_vbroadcastss_ymm_m32 :: #force_inline proc "contextless" (dst: YMM, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 4), {}, {}} }, 1484) } +inst_vbroadcastss_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1485) } +inst_vbroadcastss_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSS, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1486) } emit_vbroadcastss_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem32) { append(instructions, inst_vbroadcastss_xmm_m32(dst, src)) } emit_vbroadcastss_ymm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem32) { append(instructions, inst_vbroadcastss_ymm_m32(dst, src)) } emit_vbroadcastss_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vbroadcastss_xmm_xmm(dst, src)) } emit_vbroadcastss_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vbroadcastss_ymm_xmm(dst, src)) } -inst_vbroadcastsd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1475) } -inst_vbroadcastsd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1476) } +inst_vbroadcastsd_ymm_m64 :: #force_inline proc "contextless" (dst: YMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 8), {}, {}} }, 1487) } +inst_vbroadcastsd_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTSD, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1488) } emit_vbroadcastsd_ymm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem64) { append(instructions, inst_vbroadcastsd_ymm_m64(dst, src)) } emit_vbroadcastsd_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vbroadcastsd_ymm_xmm(dst, src)) } -inst_vbroadcastf128_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTF128, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1477) } +inst_vbroadcastf128_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTF128, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1489) } emit_vbroadcastf128_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vbroadcastf128_ymm_m128(dst, src)) } -inst_vextractf128_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTF128, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1478) } -inst_vextractf128_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTF128, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1478) } +inst_vextractf128_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTF128, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1490) } +inst_vextractf128_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTF128, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1490) } emit_vextractf128_xmm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM, imm: i8) { append(instructions, inst_vextractf128_xmm_ymm_imm8(dst, src, imm)) } emit_vextractf128_m128_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM, imm: i8) { append(instructions, inst_vextractf128_m128_ymm_imm8(dst, src, imm)) } -inst_vinsertf128_ymm_ymm_xmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTF128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), op_imm8(imm)} }, 1479) } -inst_vinsertf128_ymm_ymm_m128_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTF128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1479) } +inst_vinsertf128_ymm_ymm_xmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTF128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), op_imm8(imm)} }, 1491) } +inst_vinsertf128_ymm_ymm_m128_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTF128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1491) } emit_vinsertf128_ymm_ymm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM, imm: i8) { append(instructions, inst_vinsertf128_ymm_ymm_xmm_imm8(dst, src, src2, imm)) } emit_vinsertf128_ymm_ymm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128, imm: i8) { append(instructions, inst_vinsertf128_ymm_ymm_m128_imm8(dst, src, src2, imm)) } -inst_vperm2f128_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2F128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1480) } -inst_vperm2f128_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2F128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1480) } +inst_vperm2f128_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2F128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1492) } +inst_vperm2f128_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2F128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1492) } emit_vperm2f128_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vperm2f128_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vperm2f128_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vperm2f128_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vmaskmovps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1481) } -inst_vmaskmovps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1482) } -inst_vmaskmovps_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1483) } -inst_vmaskmovps_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1484) } +inst_vmaskmovps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1493) } +inst_vmaskmovps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1494) } +inst_vmaskmovps_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1495) } +inst_vmaskmovps_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPS, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1496) } emit_vmaskmovps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmaskmovps_xmm_xmm_m128(dst, src, src2)) } emit_vmaskmovps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmaskmovps_ymm_ymm_m256(dst, src, src2)) } emit_vmaskmovps_m128_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM, src2: XMM) { append(instructions, inst_vmaskmovps_m128_xmm_xmm(dst, src, src2)) } emit_vmaskmovps_m256_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM, src2: YMM) { append(instructions, inst_vmaskmovps_m256_ymm_ymm(dst, src, src2)) } -inst_vmaskmovpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1485) } -inst_vmaskmovpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1486) } -inst_vmaskmovpd_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1487) } -inst_vmaskmovpd_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1488) } +inst_vmaskmovpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1497) } +inst_vmaskmovpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1498) } +inst_vmaskmovpd_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1499) } +inst_vmaskmovpd_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMASKMOVPD, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1500) } emit_vmaskmovpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vmaskmovpd_xmm_xmm_m128(dst, src, src2)) } emit_vmaskmovpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vmaskmovpd_ymm_ymm_m256(dst, src, src2)) } emit_vmaskmovpd_m128_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM, src2: XMM) { append(instructions, inst_vmaskmovpd_m128_xmm_xmm(dst, src, src2)) } emit_vmaskmovpd_m256_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM, src2: YMM) { append(instructions, inst_vmaskmovpd_m256_ymm_ymm(dst, src, src2)) } -inst_vtestps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1489) } -inst_vtestps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1489) } -inst_vtestps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1490) } -inst_vtestps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1490) } +inst_vtestps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1501) } +inst_vtestps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1501) } +inst_vtestps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1502) } +inst_vtestps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1502) } emit_vtestps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vtestps_xmm_xmm(dst, src)) } emit_vtestps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vtestps_xmm_m128(dst, src)) } emit_vtestps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vtestps_ymm_ymm(dst, src)) } emit_vtestps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vtestps_ymm_m256(dst, src)) } -inst_vtestpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1491) } -inst_vtestpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1491) } -inst_vtestpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1492) } -inst_vtestpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1492) } +inst_vtestpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1503) } +inst_vtestpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1503) } +inst_vtestpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1504) } +inst_vtestpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VTESTPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1504) } emit_vtestpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vtestpd_xmm_xmm(dst, src)) } emit_vtestpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vtestpd_xmm_m128(dst, src)) } emit_vtestpd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vtestpd_ymm_ymm(dst, src)) } emit_vtestpd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vtestpd_ymm_m256(dst, src)) } -inst_vzeroall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VZEROALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 1493) } +inst_vzeroall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VZEROALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 1505) } emit_vzeroall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vzeroall_none()) } -inst_vzeroupper_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VZEROUPPER, operand_count = 0, ops = {{}, {}, {}, {}} }, 1494) } +inst_vzeroupper_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VZEROUPPER, operand_count = 0, ops = {{}, {}, {}, {}} }, 1506) } emit_vzeroupper_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vzeroupper_none()) } -inst_vbroadcasti128_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTI128, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1495) } +inst_vbroadcasti128_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBROADCASTI128, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1507) } emit_vbroadcasti128_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vbroadcasti128_ymm_m128(dst, src)) } -inst_vextracti128_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTI128, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1496) } -inst_vextracti128_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTI128, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1496) } +inst_vextracti128_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTI128, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1508) } +inst_vextracti128_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXTRACTI128, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1508) } emit_vextracti128_xmm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM, imm: i8) { append(instructions, inst_vextracti128_xmm_ymm_imm8(dst, src, imm)) } emit_vextracti128_m128_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM, imm: i8) { append(instructions, inst_vextracti128_m128_ymm_imm8(dst, src, imm)) } -inst_vinserti128_ymm_ymm_xmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTI128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), op_imm8(imm)} }, 1497) } -inst_vinserti128_ymm_ymm_m128_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTI128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1497) } +inst_vinserti128_ymm_ymm_xmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTI128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_xmm(src2), op_imm8(imm)} }, 1509) } +inst_vinserti128_ymm_ymm_m128_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VINSERTI128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1509) } emit_vinserti128_ymm_ymm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: XMM, imm: i8) { append(instructions, inst_vinserti128_ymm_ymm_xmm_imm8(dst, src, src2, imm)) } emit_vinserti128_ymm_ymm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem128, imm: i8) { append(instructions, inst_vinserti128_ymm_ymm_m128_imm8(dst, src, src2, imm)) } -inst_vperm2i128_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2I128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1498) } -inst_vperm2i128_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2I128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1498) } +inst_vperm2i128_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2I128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1510) } +inst_vperm2i128_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERM2I128, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1510) } emit_vperm2i128_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vperm2i128_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vperm2i128_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vperm2i128_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vpermd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1499) } -inst_vpermd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1499) } +inst_vpermd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1511) } +inst_vpermd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1511) } emit_vpermd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermd_ymm_ymm_ymm(dst, src, src2)) } emit_vpermd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermd_ymm_ymm_m256(dst, src, src2)) } -inst_vpermps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1500) } -inst_vpermps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1500) } +inst_vpermps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1512) } +inst_vpermps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1512) } emit_vpermps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermps_ymm_ymm_ymm(dst, src, src2)) } emit_vpermps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermps_ymm_ymm_m256(dst, src, src2)) } -inst_vpermq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1501) } -inst_vpermq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1501) } +inst_vpermq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1513) } +inst_vpermq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1513) } emit_vpermq_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpermq_ymm_ymm_imm8(dst, src, imm)) } emit_vpermq_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vpermq_ymm_m256_imm8(dst, src, imm)) } -inst_vpermpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1502) } -inst_vpermpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1502) } +inst_vpermpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1514) } +inst_vpermpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1514) } emit_vpermpd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vpermpd_ymm_ymm_imm8(dst, src, imm)) } emit_vpermpd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vpermpd_ymm_m256_imm8(dst, src, imm)) } -inst_vpblendd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1503) } -inst_vpblendd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1503) } -inst_vpblendd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1504) } -inst_vpblendd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1504) } +inst_vpblendd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1515) } +inst_vpblendd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1515) } +inst_vpblendd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1516) } +inst_vpblendd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1516) } emit_vpblendd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpblendd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpblendd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpblendd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpblendd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpblendd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpblendd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpblendd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } -inst_vpsllvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1505) } -inst_vpsllvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1505) } -inst_vpsllvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1506) } -inst_vpsllvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1506) } +inst_vpsllvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1517) } +inst_vpsllvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1517) } +inst_vpsllvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1518) } +inst_vpsllvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1518) } emit_vpsllvd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsllvd_xmm_xmm_xmm(dst, src, src2)) } emit_vpsllvd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsllvd_xmm_xmm_m128(dst, src, src2)) } emit_vpsllvd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsllvd_ymm_ymm_ymm(dst, src, src2)) } emit_vpsllvd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsllvd_ymm_ymm_m256(dst, src, src2)) } -inst_vpsllvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1507) } -inst_vpsllvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1507) } -inst_vpsllvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1508) } -inst_vpsllvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1508) } +inst_vpsllvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1519) } +inst_vpsllvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1519) } +inst_vpsllvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1520) } +inst_vpsllvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1520) } emit_vpsllvq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsllvq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsllvq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsllvq_xmm_xmm_m128(dst, src, src2)) } emit_vpsllvq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsllvq_ymm_ymm_ymm(dst, src, src2)) } emit_vpsllvq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsllvq_ymm_ymm_m256(dst, src, src2)) } -inst_vpsrlvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1509) } -inst_vpsrlvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1509) } -inst_vpsrlvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1510) } -inst_vpsrlvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1510) } +inst_vpsrlvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1521) } +inst_vpsrlvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1521) } +inst_vpsrlvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1522) } +inst_vpsrlvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1522) } emit_vpsrlvd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrlvd_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrlvd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrlvd_xmm_xmm_m128(dst, src, src2)) } emit_vpsrlvd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsrlvd_ymm_ymm_ymm(dst, src, src2)) } emit_vpsrlvd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsrlvd_ymm_ymm_m256(dst, src, src2)) } -inst_vpsrlvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1511) } -inst_vpsrlvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1511) } -inst_vpsrlvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1512) } -inst_vpsrlvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1512) } +inst_vpsrlvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1523) } +inst_vpsrlvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1523) } +inst_vpsrlvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1524) } +inst_vpsrlvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1524) } emit_vpsrlvq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrlvq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrlvq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrlvq_xmm_xmm_m128(dst, src, src2)) } emit_vpsrlvq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsrlvq_ymm_ymm_ymm(dst, src, src2)) } emit_vpsrlvq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsrlvq_ymm_ymm_m256(dst, src, src2)) } -inst_vpsravd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1513) } -inst_vpsravd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1513) } -inst_vpsravd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1514) } -inst_vpsravd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1514) } +inst_vpsravd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1525) } +inst_vpsravd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1525) } +inst_vpsravd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1526) } +inst_vpsravd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1526) } emit_vpsravd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsravd_xmm_xmm_xmm(dst, src, src2)) } emit_vpsravd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsravd_xmm_xmm_m128(dst, src, src2)) } emit_vpsravd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsravd_ymm_ymm_ymm(dst, src, src2)) } emit_vpsravd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsravd_ymm_ymm_m256(dst, src, src2)) } -inst_vpmaskmovd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1515) } -inst_vpmaskmovd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1516) } -inst_vpmaskmovd_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1517) } -inst_vpmaskmovd_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1518) } +inst_vpmaskmovd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1527) } +inst_vpmaskmovd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1528) } +inst_vpmaskmovd_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1529) } +inst_vpmaskmovd_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVD, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1530) } emit_vpmaskmovd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaskmovd_xmm_xmm_m128(dst, src, src2)) } emit_vpmaskmovd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaskmovd_ymm_ymm_m256(dst, src, src2)) } emit_vpmaskmovd_m128_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM, src2: XMM) { append(instructions, inst_vpmaskmovd_m128_xmm_xmm(dst, src, src2)) } emit_vpmaskmovd_m256_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM, src2: YMM) { append(instructions, inst_vpmaskmovd_m256_ymm_ymm(dst, src, src2)) } -inst_vpmaskmovq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1519) } -inst_vpmaskmovq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1520) } -inst_vpmaskmovq_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1521) } -inst_vpmaskmovq_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1522) } +inst_vpmaskmovq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1531) } +inst_vpmaskmovq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1532) } +inst_vpmaskmovq_m128_xmm_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_mem(dst.mem, 16), op_xmm(src), op_xmm(src2), {}} }, 1533) } +inst_vpmaskmovq_m256_ymm_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMASKMOVQ, operand_count = 3, ops = {op_mem(dst.mem, 32), op_ymm(src), op_ymm(src2), {}} }, 1534) } emit_vpmaskmovq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmaskmovq_xmm_xmm_m128(dst, src, src2)) } emit_vpmaskmovq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmaskmovq_ymm_ymm_m256(dst, src, src2)) } emit_vpmaskmovq_m128_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM, src2: XMM) { append(instructions, inst_vpmaskmovq_m128_xmm_xmm(dst, src, src2)) } emit_vpmaskmovq_m256_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM, src2: YMM) { append(instructions, inst_vpmaskmovq_m256_ymm_ymm(dst, src, src2)) } -inst_vgatherdps_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1523) } -inst_vgatherdps_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1524) } +inst_vgatherdps_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1535) } +inst_vgatherdps_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1536) } emit_vgatherdps_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vgatherdps_xmm_m_xmm(dst, src, src2)) } emit_vgatherdps_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vgatherdps_ymm_m_ymm(dst, src, src2)) } -inst_vgatherdpd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1525) } -inst_vgatherdpd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1526) } +inst_vgatherdpd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1537) } +inst_vgatherdpd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERDPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1538) } emit_vgatherdpd_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vgatherdpd_xmm_m_xmm(dst, src, src2)) } emit_vgatherdpd_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vgatherdpd_ymm_m_ymm(dst, src, src2)) } -inst_vgatherqps_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1527) } +inst_vgatherqps_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1539) } emit_vgatherqps_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vgatherqps_xmm_m_xmm(dst, src, src2)) } -inst_vgatherqpd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1529) } -inst_vgatherqpd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1530) } +inst_vgatherqpd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1541) } +inst_vgatherqpd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGATHERQPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1542) } emit_vgatherqpd_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vgatherqpd_xmm_m_xmm(dst, src, src2)) } emit_vgatherqpd_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vgatherqpd_ymm_m_ymm(dst, src, src2)) } -inst_vpgatherdd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1531) } -inst_vpgatherdd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1532) } +inst_vpgatherdd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1543) } +inst_vpgatherdd_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDD, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1544) } emit_vpgatherdd_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vpgatherdd_xmm_m_xmm(dst, src, src2)) } emit_vpgatherdd_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vpgatherdd_ymm_m_ymm(dst, src, src2)) } -inst_vpgatherdq_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1533) } -inst_vpgatherdq_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1534) } +inst_vpgatherdq_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1545) } +inst_vpgatherdq_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERDQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1546) } emit_vpgatherdq_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vpgatherdq_xmm_m_xmm(dst, src, src2)) } emit_vpgatherdq_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vpgatherdq_ymm_m_ymm(dst, src, src2)) } -inst_vpgatherqd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1535) } +inst_vpgatherqd_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQD, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1547) } emit_vpgatherqd_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vpgatherqd_xmm_m_xmm(dst, src, src2)) } -inst_vpgatherqq_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1537) } -inst_vpgatherqq_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1538) } +inst_vpgatherqq_xmm_m_xmm :: #force_inline proc "contextless" (dst: XMM, src: Memory, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src, 0), op_xmm(src2), {}} }, 1549) } +inst_vpgatherqq_ymm_m_ymm :: #force_inline proc "contextless" (dst: YMM, src: Memory, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPGATHERQQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src, 0), op_ymm(src2), {}} }, 1550) } emit_vpgatherqq_xmm_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Memory, src2: XMM) { append(instructions, inst_vpgatherqq_xmm_m_xmm(dst, src, src2)) } emit_vpgatherqq_ymm_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Memory, src2: YMM) { append(instructions, inst_vpgatherqq_ymm_m_ymm(dst, src, src2)) } -inst_vfmadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1539) } -inst_vfmadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1539) } -inst_vfmadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1540) } -inst_vfmadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1540) } +inst_vfmadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1551) } +inst_vfmadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1551) } +inst_vfmadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1552) } +inst_vfmadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1552) } emit_vfmadd132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1541) } -inst_vfmadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1541) } -inst_vfmadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1542) } -inst_vfmadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1542) } +inst_vfmadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1553) } +inst_vfmadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1553) } +inst_vfmadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1554) } +inst_vfmadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1554) } emit_vfmadd213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1543) } -inst_vfmadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1543) } -inst_vfmadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1544) } -inst_vfmadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1544) } +inst_vfmadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1555) } +inst_vfmadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1555) } +inst_vfmadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1556) } +inst_vfmadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1556) } emit_vfmadd231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1545) } -inst_vfmadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1545) } -inst_vfmadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1546) } -inst_vfmadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1546) } +inst_vfmadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1557) } +inst_vfmadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1557) } +inst_vfmadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1558) } +inst_vfmadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1558) } emit_vfmadd132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1547) } -inst_vfmadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1547) } -inst_vfmadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1548) } -inst_vfmadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1548) } +inst_vfmadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1559) } +inst_vfmadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1559) } +inst_vfmadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1560) } +inst_vfmadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1560) } emit_vfmadd213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1549) } -inst_vfmadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1549) } -inst_vfmadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1550) } -inst_vfmadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1550) } +inst_vfmadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1561) } +inst_vfmadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1561) } +inst_vfmadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1562) } +inst_vfmadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1562) } emit_vfmadd231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmadd231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmadd231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmadd231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmadd231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmadd231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmadd132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1551) } -inst_vfmadd132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1551) } +inst_vfmadd132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1563) } +inst_vfmadd132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1563) } emit_vfmadd132ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd132ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd132ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmadd132ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmadd213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1552) } -inst_vfmadd213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1552) } +inst_vfmadd213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1564) } +inst_vfmadd213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1564) } emit_vfmadd213ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd213ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd213ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmadd213ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmadd231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1553) } -inst_vfmadd231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1553) } +inst_vfmadd231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1565) } +inst_vfmadd231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1565) } emit_vfmadd231ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd231ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd231ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmadd231ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmadd132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1554) } -inst_vfmadd132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1554) } +inst_vfmadd132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1566) } +inst_vfmadd132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1566) } emit_vfmadd132sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd132sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd132sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmadd132sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmadd213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1555) } -inst_vfmadd213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1555) } +inst_vfmadd213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1567) } +inst_vfmadd213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1567) } emit_vfmadd213sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd213sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd213sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmadd213sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmadd231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1556) } -inst_vfmadd231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1556) } +inst_vfmadd231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1568) } +inst_vfmadd231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1568) } emit_vfmadd231sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmadd231sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmadd231sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmadd231sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1557) } -inst_vfmsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1557) } -inst_vfmsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1558) } -inst_vfmsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1558) } +inst_vfmsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1569) } +inst_vfmsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1569) } +inst_vfmsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1570) } +inst_vfmsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1570) } emit_vfmsub132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1559) } -inst_vfmsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1559) } -inst_vfmsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1560) } -inst_vfmsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1560) } +inst_vfmsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1571) } +inst_vfmsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1571) } +inst_vfmsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1572) } +inst_vfmsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1572) } emit_vfmsub213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1561) } -inst_vfmsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1561) } -inst_vfmsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1562) } -inst_vfmsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1562) } +inst_vfmsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1573) } +inst_vfmsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1573) } +inst_vfmsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1574) } +inst_vfmsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1574) } emit_vfmsub231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1563) } -inst_vfmsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1563) } -inst_vfmsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1564) } -inst_vfmsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1564) } +inst_vfmsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1575) } +inst_vfmsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1575) } +inst_vfmsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1576) } +inst_vfmsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1576) } emit_vfmsub132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1565) } -inst_vfmsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1565) } -inst_vfmsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1566) } -inst_vfmsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1566) } +inst_vfmsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1577) } +inst_vfmsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1577) } +inst_vfmsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1578) } +inst_vfmsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1578) } emit_vfmsub213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1567) } -inst_vfmsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1567) } -inst_vfmsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1568) } -inst_vfmsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1568) } +inst_vfmsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1579) } +inst_vfmsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1579) } +inst_vfmsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1580) } +inst_vfmsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1580) } emit_vfmsub231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsub231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsub231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsub231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsub231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsub231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsub132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1569) } -inst_vfmsub132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1569) } +inst_vfmsub132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1581) } +inst_vfmsub132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1581) } emit_vfmsub132ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub132ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub132ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmsub132ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmsub213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1570) } -inst_vfmsub213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1570) } +inst_vfmsub213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1582) } +inst_vfmsub213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1582) } emit_vfmsub213ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub213ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub213ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmsub213ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmsub231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1571) } -inst_vfmsub231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1571) } +inst_vfmsub231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1583) } +inst_vfmsub231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1583) } emit_vfmsub231ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub231ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub231ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfmsub231ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfmsub132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1572) } -inst_vfmsub132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1572) } +inst_vfmsub132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1584) } +inst_vfmsub132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1584) } emit_vfmsub132sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub132sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub132sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmsub132sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmsub213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1573) } -inst_vfmsub213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1573) } +inst_vfmsub213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1585) } +inst_vfmsub213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1585) } emit_vfmsub213sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub213sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub213sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmsub213sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmsub231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1574) } -inst_vfmsub231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1574) } +inst_vfmsub231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1586) } +inst_vfmsub231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1586) } emit_vfmsub231sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsub231sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsub231sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfmsub231sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1575) } -inst_vfnmadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1575) } -inst_vfnmadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1576) } -inst_vfnmadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1576) } +inst_vfnmadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1587) } +inst_vfnmadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1587) } +inst_vfnmadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1588) } +inst_vfnmadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1588) } emit_vfnmadd132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1577) } -inst_vfnmadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1577) } -inst_vfnmadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1578) } -inst_vfnmadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1578) } +inst_vfnmadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1589) } +inst_vfnmadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1589) } +inst_vfnmadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1590) } +inst_vfnmadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1590) } emit_vfnmadd213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1579) } -inst_vfnmadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1579) } -inst_vfnmadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1580) } -inst_vfnmadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1580) } +inst_vfnmadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1591) } +inst_vfnmadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1591) } +inst_vfnmadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1592) } +inst_vfnmadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1592) } emit_vfnmadd231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1581) } -inst_vfnmadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1581) } -inst_vfnmadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1582) } -inst_vfnmadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1582) } +inst_vfnmadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1593) } +inst_vfnmadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1593) } +inst_vfnmadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1594) } +inst_vfnmadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1594) } emit_vfnmadd132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1583) } -inst_vfnmadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1583) } -inst_vfnmadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1584) } -inst_vfnmadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1584) } +inst_vfnmadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1595) } +inst_vfnmadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1595) } +inst_vfnmadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1596) } +inst_vfnmadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1596) } emit_vfnmadd213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1585) } -inst_vfnmadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1585) } -inst_vfnmadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1586) } -inst_vfnmadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1586) } +inst_vfnmadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1597) } +inst_vfnmadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1597) } +inst_vfnmadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1598) } +inst_vfnmadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1598) } emit_vfnmadd231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmadd231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmadd231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmadd231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmadd231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmadd231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmadd132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1587) } -inst_vfnmadd132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1587) } +inst_vfnmadd132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1599) } +inst_vfnmadd132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1599) } emit_vfnmadd132ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd132ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd132ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmadd132ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmadd213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1588) } -inst_vfnmadd213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1588) } +inst_vfnmadd213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1600) } +inst_vfnmadd213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1600) } emit_vfnmadd213ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd213ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd213ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmadd213ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmadd231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1589) } -inst_vfnmadd231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1589) } +inst_vfnmadd231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1601) } +inst_vfnmadd231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1601) } emit_vfnmadd231ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd231ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd231ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmadd231ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmadd132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1590) } -inst_vfnmadd132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1590) } +inst_vfnmadd132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1602) } +inst_vfnmadd132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1602) } emit_vfnmadd132sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd132sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd132sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmadd132sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmadd213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1591) } -inst_vfnmadd213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1591) } +inst_vfnmadd213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1603) } +inst_vfnmadd213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1603) } emit_vfnmadd213sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd213sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd213sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmadd213sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmadd231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1592) } -inst_vfnmadd231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1592) } +inst_vfnmadd231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1604) } +inst_vfnmadd231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMADD231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1604) } emit_vfnmadd231sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmadd231sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmadd231sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmadd231sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1593) } -inst_vfnmsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1593) } -inst_vfnmsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1594) } -inst_vfnmsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1594) } +inst_vfnmsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1605) } +inst_vfnmsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1605) } +inst_vfnmsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1606) } +inst_vfnmsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1606) } emit_vfnmsub132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1595) } -inst_vfnmsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1595) } -inst_vfnmsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1596) } -inst_vfnmsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1596) } +inst_vfnmsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1607) } +inst_vfnmsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1607) } +inst_vfnmsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1608) } +inst_vfnmsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1608) } emit_vfnmsub213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1597) } -inst_vfnmsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1597) } -inst_vfnmsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1598) } -inst_vfnmsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1598) } +inst_vfnmsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1609) } +inst_vfnmsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1609) } +inst_vfnmsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1610) } +inst_vfnmsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1610) } emit_vfnmsub231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1599) } -inst_vfnmsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1599) } -inst_vfnmsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1600) } -inst_vfnmsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1600) } +inst_vfnmsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1611) } +inst_vfnmsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1611) } +inst_vfnmsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1612) } +inst_vfnmsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1612) } emit_vfnmsub132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1601) } -inst_vfnmsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1601) } -inst_vfnmsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1602) } -inst_vfnmsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1602) } +inst_vfnmsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1613) } +inst_vfnmsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1613) } +inst_vfnmsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1614) } +inst_vfnmsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1614) } emit_vfnmsub213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1603) } -inst_vfnmsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1603) } -inst_vfnmsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1604) } -inst_vfnmsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1604) } +inst_vfnmsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1615) } +inst_vfnmsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1615) } +inst_vfnmsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1616) } +inst_vfnmsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1616) } emit_vfnmsub231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfnmsub231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfnmsub231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfnmsub231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfnmsub231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfnmsub231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfnmsub132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1605) } -inst_vfnmsub132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1605) } +inst_vfnmsub132ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1617) } +inst_vfnmsub132ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1617) } emit_vfnmsub132ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub132ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub132ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmsub132ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmsub213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1606) } -inst_vfnmsub213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1606) } +inst_vfnmsub213ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1618) } +inst_vfnmsub213ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1618) } emit_vfnmsub213ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub213ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub213ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmsub213ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmsub231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1607) } -inst_vfnmsub231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1607) } +inst_vfnmsub231ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1619) } +inst_vfnmsub231ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1619) } emit_vfnmsub231ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub231ss_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub231ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vfnmsub231ss_xmm_xmm_m32(dst, src, src2)) } -inst_vfnmsub132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1608) } -inst_vfnmsub132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1608) } +inst_vfnmsub132sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1620) } +inst_vfnmsub132sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB132SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1620) } emit_vfnmsub132sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub132sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub132sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmsub132sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmsub213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1609) } -inst_vfnmsub213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1609) } +inst_vfnmsub213sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1621) } +inst_vfnmsub213sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB213SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1621) } emit_vfnmsub213sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub213sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub213sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmsub213sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfnmsub231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1610) } -inst_vfnmsub231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1610) } +inst_vfnmsub231sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1622) } +inst_vfnmsub231sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VFNMSUB231SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1622) } emit_vfnmsub231sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfnmsub231sd_xmm_xmm_xmm(dst, src, src2)) } emit_vfnmsub231sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vfnmsub231sd_xmm_xmm_m64(dst, src, src2)) } -inst_vfmaddsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1611) } -inst_vfmaddsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1611) } -inst_vfmaddsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1612) } -inst_vfmaddsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1612) } +inst_vfmaddsub132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1623) } +inst_vfmaddsub132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1623) } +inst_vfmaddsub132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1624) } +inst_vfmaddsub132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1624) } emit_vfmaddsub132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmaddsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1613) } -inst_vfmaddsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1613) } -inst_vfmaddsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1614) } -inst_vfmaddsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1614) } +inst_vfmaddsub213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1625) } +inst_vfmaddsub213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1625) } +inst_vfmaddsub213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1626) } +inst_vfmaddsub213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1626) } emit_vfmaddsub213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmaddsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1615) } -inst_vfmaddsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1615) } -inst_vfmaddsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1616) } -inst_vfmaddsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1616) } +inst_vfmaddsub231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1627) } +inst_vfmaddsub231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1627) } +inst_vfmaddsub231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1628) } +inst_vfmaddsub231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1628) } emit_vfmaddsub231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmaddsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1617) } -inst_vfmaddsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1617) } -inst_vfmaddsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1618) } -inst_vfmaddsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1618) } +inst_vfmaddsub132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1629) } +inst_vfmaddsub132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1629) } +inst_vfmaddsub132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1630) } +inst_vfmaddsub132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1630) } emit_vfmaddsub132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmaddsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1619) } -inst_vfmaddsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1619) } -inst_vfmaddsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1620) } -inst_vfmaddsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1620) } +inst_vfmaddsub213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1631) } +inst_vfmaddsub213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1631) } +inst_vfmaddsub213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1632) } +inst_vfmaddsub213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1632) } emit_vfmaddsub213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmaddsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1621) } -inst_vfmaddsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1621) } -inst_vfmaddsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1622) } -inst_vfmaddsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1622) } +inst_vfmaddsub231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1633) } +inst_vfmaddsub231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1633) } +inst_vfmaddsub231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1634) } +inst_vfmaddsub231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMADDSUB231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1634) } emit_vfmaddsub231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmaddsub231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmaddsub231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmaddsub231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmaddsub231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmaddsub231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmaddsub231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmaddsub231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1623) } -inst_vfmsubadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1623) } -inst_vfmsubadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1624) } -inst_vfmsubadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1624) } +inst_vfmsubadd132ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1635) } +inst_vfmsubadd132ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1635) } +inst_vfmsubadd132ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1636) } +inst_vfmsubadd132ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1636) } emit_vfmsubadd132ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd132ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd132ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd132ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd132ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd132ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd132ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd132ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1625) } -inst_vfmsubadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1625) } -inst_vfmsubadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1626) } -inst_vfmsubadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1626) } +inst_vfmsubadd213ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1637) } +inst_vfmsubadd213ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1637) } +inst_vfmsubadd213ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1638) } +inst_vfmsubadd213ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1638) } emit_vfmsubadd213ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd213ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd213ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd213ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd213ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd213ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd213ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd213ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1627) } -inst_vfmsubadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1627) } -inst_vfmsubadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1628) } -inst_vfmsubadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1628) } +inst_vfmsubadd231ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1639) } +inst_vfmsubadd231ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1639) } +inst_vfmsubadd231ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1640) } +inst_vfmsubadd231ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1640) } emit_vfmsubadd231ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd231ps_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd231ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd231ps_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd231ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd231ps_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd231ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd231ps_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1629) } -inst_vfmsubadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1629) } -inst_vfmsubadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1630) } -inst_vfmsubadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1630) } +inst_vfmsubadd132pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1641) } +inst_vfmsubadd132pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1641) } +inst_vfmsubadd132pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1642) } +inst_vfmsubadd132pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD132PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1642) } emit_vfmsubadd132pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd132pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd132pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd132pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd132pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd132pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd132pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd132pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1631) } -inst_vfmsubadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1631) } -inst_vfmsubadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1632) } -inst_vfmsubadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1632) } +inst_vfmsubadd213pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1643) } +inst_vfmsubadd213pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1643) } +inst_vfmsubadd213pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1644) } +inst_vfmsubadd213pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD213PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1644) } emit_vfmsubadd213pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd213pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd213pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd213pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd213pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd213pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd213pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd213pd_ymm_ymm_m256(dst, src, src2)) } -inst_vfmsubadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1633) } -inst_vfmsubadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1633) } -inst_vfmsubadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1634) } -inst_vfmsubadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1634) } +inst_vfmsubadd231pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1645) } +inst_vfmsubadd231pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1645) } +inst_vfmsubadd231pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1646) } +inst_vfmsubadd231pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VFMSUBADD231PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1646) } emit_vfmsubadd231pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vfmsubadd231pd_xmm_xmm_xmm(dst, src, src2)) } emit_vfmsubadd231pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vfmsubadd231pd_xmm_xmm_m128(dst, src, src2)) } emit_vfmsubadd231pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vfmsubadd231pd_ymm_ymm_ymm(dst, src, src2)) } emit_vfmsubadd231pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vfmsubadd231pd_ymm_ymm_m256(dst, src, src2)) } -inst_vcvtph2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1635) } -inst_vcvtph2ps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1635) } -inst_vcvtph2ps_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1636) } -inst_vcvtph2ps_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1636) } -inst_vcvtph2ps_zmm_ymm :: #force_inline proc "contextless" (dst: ZMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_zmm(dst), op_ymm(src), {}, {}} }, 1637) } -inst_vcvtph2ps_zmm_m256 :: #force_inline proc "contextless" (dst: ZMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 32), {}, {}} }, 1637) } +inst_vcvtph2ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1647) } +inst_vcvtph2ps_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 8), {}, {}} }, 1647) } +inst_vcvtph2ps_ymm_xmm :: #force_inline proc "contextless" (dst: YMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_ymm(dst), op_xmm(src), {}, {}} }, 1648) } +inst_vcvtph2ps_ymm_m128 :: #force_inline proc "contextless" (dst: YMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 16), {}, {}} }, 1648) } +inst_vcvtph2ps_zmm_ymm :: #force_inline proc "contextless" (dst: ZMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_zmm(dst), op_ymm(src), {}, {}} }, 1649) } +inst_vcvtph2ps_zmm_m256 :: #force_inline proc "contextless" (dst: ZMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPH2PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 32), {}, {}} }, 1649) } emit_vcvtph2ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcvtph2ps_xmm_xmm(dst, src)) } emit_vcvtph2ps_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem64) { append(instructions, inst_vcvtph2ps_xmm_m64(dst, src)) } emit_vcvtph2ps_ymm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: XMM) { append(instructions, inst_vcvtph2ps_ymm_xmm(dst, src)) } emit_vcvtph2ps_ymm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem128) { append(instructions, inst_vcvtph2ps_ymm_m128(dst, src)) } emit_vcvtph2ps_zmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: YMM) { append(instructions, inst_vcvtph2ps_zmm_ymm(dst, src)) } emit_vcvtph2ps_zmm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem256) { append(instructions, inst_vcvtph2ps_zmm_m256(dst, src)) } -inst_vcvtps2ph_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1638) } -inst_vcvtps2ph_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 1638) } -inst_vcvtps2ph_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1639) } -inst_vcvtps2ph_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1639) } -inst_vcvtps2ph_ymm_zmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_ymm(dst), op_zmm(src), op_imm8(imm), {}} }, 1640) } -inst_vcvtps2ph_m256_zmm_imm8 :: #force_inline proc "contextless" (dst: Mem256, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 32), op_zmm(src), op_imm8(imm), {}} }, 1640) } +inst_vcvtps2ph_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1650) } +inst_vcvtps2ph_m64_xmm_imm8 :: #force_inline proc "contextless" (dst: Mem64, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 8), op_xmm(src), op_imm8(imm), {}} }, 1650) } +inst_vcvtps2ph_xmm_ymm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_xmm(dst), op_ymm(src), op_imm8(imm), {}} }, 1651) } +inst_vcvtps2ph_m128_ymm_imm8 :: #force_inline proc "contextless" (dst: Mem128, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 16), op_ymm(src), op_imm8(imm), {}} }, 1651) } +inst_vcvtps2ph_ymm_zmm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_ymm(dst), op_zmm(src), op_imm8(imm), {}} }, 1652) } +inst_vcvtps2ph_m256_zmm_imm8 :: #force_inline proc "contextless" (dst: Mem256, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VCVTPS2PH, operand_count = 3, ops = {op_mem(dst.mem, 32), op_zmm(src), op_imm8(imm), {}} }, 1652) } emit_vcvtps2ph_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vcvtps2ph_xmm_xmm_imm8(dst, src, imm)) } emit_vcvtps2ph_m64_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM, imm: i8) { append(instructions, inst_vcvtps2ph_m64_xmm_imm8(dst, src, imm)) } emit_vcvtps2ph_xmm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM, imm: i8) { append(instructions, inst_vcvtps2ph_xmm_ymm_imm8(dst, src, imm)) } emit_vcvtps2ph_m128_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM, imm: i8) { append(instructions, inst_vcvtps2ph_m128_ymm_imm8(dst, src, imm)) } emit_vcvtps2ph_ymm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM, imm: i8) { append(instructions, inst_vcvtps2ph_ymm_zmm_imm8(dst, src, imm)) } emit_vcvtps2ph_m256_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM, imm: i8) { append(instructions, inst_vcvtps2ph_m256_zmm_imm8(dst, src, imm)) } -inst_vmovdqa32_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1641) } -inst_vmovdqa32_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1641) } -inst_vmovdqa32_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1642) } -inst_vmovdqa32_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1643) } -inst_vmovdqa32_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1643) } -inst_vmovdqa32_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1644) } -inst_vmovdqa32_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1645) } -inst_vmovdqa32_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1645) } -inst_vmovdqa32_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1646) } +inst_vmovdqa32_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1653) } +inst_vmovdqa32_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1653) } +inst_vmovdqa32_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1654) } +inst_vmovdqa32_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1655) } +inst_vmovdqa32_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1655) } +inst_vmovdqa32_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1656) } +inst_vmovdqa32_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1657) } +inst_vmovdqa32_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1657) } +inst_vmovdqa32_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA32, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1658) } emit_vmovdqa32_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqa32_xmm_xmm(dst, src)) } emit_vmovdqa32_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqa32_xmm_m128(dst, src)) } emit_vmovdqa32_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqa32_m128_xmm(dst, src)) } @@ -5463,15 +5495,15 @@ emit_vmovdqa32_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqa32_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqa32_zmm_zmm(dst, src)) } emit_vmovdqa32_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqa32_zmm_m512(dst, src)) } emit_vmovdqa32_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqa32_m512_zmm(dst, src)) } -inst_vmovdqa64_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1647) } -inst_vmovdqa64_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1647) } -inst_vmovdqa64_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1648) } -inst_vmovdqa64_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1649) } -inst_vmovdqa64_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1649) } -inst_vmovdqa64_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1650) } -inst_vmovdqa64_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1651) } -inst_vmovdqa64_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1651) } -inst_vmovdqa64_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1652) } +inst_vmovdqa64_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1659) } +inst_vmovdqa64_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1659) } +inst_vmovdqa64_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1660) } +inst_vmovdqa64_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1661) } +inst_vmovdqa64_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1661) } +inst_vmovdqa64_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1662) } +inst_vmovdqa64_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1663) } +inst_vmovdqa64_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1663) } +inst_vmovdqa64_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQA64, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1664) } emit_vmovdqa64_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqa64_xmm_xmm(dst, src)) } emit_vmovdqa64_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqa64_xmm_m128(dst, src)) } emit_vmovdqa64_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqa64_m128_xmm(dst, src)) } @@ -5481,15 +5513,15 @@ emit_vmovdqa64_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqa64_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqa64_zmm_zmm(dst, src)) } emit_vmovdqa64_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqa64_zmm_m512(dst, src)) } emit_vmovdqa64_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqa64_m512_zmm(dst, src)) } -inst_vmovdqu8_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1653) } -inst_vmovdqu8_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1653) } -inst_vmovdqu8_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1654) } -inst_vmovdqu8_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1655) } -inst_vmovdqu8_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1655) } -inst_vmovdqu8_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1656) } -inst_vmovdqu8_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1657) } -inst_vmovdqu8_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1657) } -inst_vmovdqu8_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1658) } +inst_vmovdqu8_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1665) } +inst_vmovdqu8_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1665) } +inst_vmovdqu8_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1666) } +inst_vmovdqu8_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1667) } +inst_vmovdqu8_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1667) } +inst_vmovdqu8_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1668) } +inst_vmovdqu8_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1669) } +inst_vmovdqu8_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1669) } +inst_vmovdqu8_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU8, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1670) } emit_vmovdqu8_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqu8_xmm_xmm(dst, src)) } emit_vmovdqu8_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqu8_xmm_m128(dst, src)) } emit_vmovdqu8_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqu8_m128_xmm(dst, src)) } @@ -5499,15 +5531,15 @@ emit_vmovdqu8_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqu8_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqu8_zmm_zmm(dst, src)) } emit_vmovdqu8_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqu8_zmm_m512(dst, src)) } emit_vmovdqu8_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqu8_m512_zmm(dst, src)) } -inst_vmovdqu16_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1659) } -inst_vmovdqu16_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1659) } -inst_vmovdqu16_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1660) } -inst_vmovdqu16_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1661) } -inst_vmovdqu16_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1661) } -inst_vmovdqu16_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1662) } -inst_vmovdqu16_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1663) } -inst_vmovdqu16_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1663) } -inst_vmovdqu16_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1664) } +inst_vmovdqu16_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1671) } +inst_vmovdqu16_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1671) } +inst_vmovdqu16_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1672) } +inst_vmovdqu16_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1673) } +inst_vmovdqu16_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1673) } +inst_vmovdqu16_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1674) } +inst_vmovdqu16_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1675) } +inst_vmovdqu16_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1675) } +inst_vmovdqu16_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU16, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1676) } emit_vmovdqu16_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqu16_xmm_xmm(dst, src)) } emit_vmovdqu16_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqu16_xmm_m128(dst, src)) } emit_vmovdqu16_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqu16_m128_xmm(dst, src)) } @@ -5517,15 +5549,15 @@ emit_vmovdqu16_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqu16_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqu16_zmm_zmm(dst, src)) } emit_vmovdqu16_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqu16_zmm_m512(dst, src)) } emit_vmovdqu16_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqu16_m512_zmm(dst, src)) } -inst_vmovdqu32_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1665) } -inst_vmovdqu32_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1665) } -inst_vmovdqu32_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1666) } -inst_vmovdqu32_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1667) } -inst_vmovdqu32_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1667) } -inst_vmovdqu32_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1668) } -inst_vmovdqu32_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1669) } -inst_vmovdqu32_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1669) } -inst_vmovdqu32_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1670) } +inst_vmovdqu32_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1677) } +inst_vmovdqu32_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1677) } +inst_vmovdqu32_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1678) } +inst_vmovdqu32_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1679) } +inst_vmovdqu32_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1679) } +inst_vmovdqu32_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1680) } +inst_vmovdqu32_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1681) } +inst_vmovdqu32_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1681) } +inst_vmovdqu32_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU32, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1682) } emit_vmovdqu32_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqu32_xmm_xmm(dst, src)) } emit_vmovdqu32_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqu32_xmm_m128(dst, src)) } emit_vmovdqu32_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqu32_m128_xmm(dst, src)) } @@ -5535,15 +5567,15 @@ emit_vmovdqu32_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqu32_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqu32_zmm_zmm(dst, src)) } emit_vmovdqu32_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqu32_zmm_m512(dst, src)) } emit_vmovdqu32_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqu32_m512_zmm(dst, src)) } -inst_vmovdqu64_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1671) } -inst_vmovdqu64_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1671) } -inst_vmovdqu64_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1672) } -inst_vmovdqu64_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1673) } -inst_vmovdqu64_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1673) } -inst_vmovdqu64_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1674) } -inst_vmovdqu64_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1675) } -inst_vmovdqu64_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1675) } -inst_vmovdqu64_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1676) } +inst_vmovdqu64_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1683) } +inst_vmovdqu64_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1683) } +inst_vmovdqu64_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1684) } +inst_vmovdqu64_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1685) } +inst_vmovdqu64_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1685) } +inst_vmovdqu64_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1686) } +inst_vmovdqu64_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1687) } +inst_vmovdqu64_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1687) } +inst_vmovdqu64_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VMOVDQU64, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1688) } emit_vmovdqu64_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vmovdqu64_xmm_xmm(dst, src)) } emit_vmovdqu64_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vmovdqu64_xmm_m128(dst, src)) } emit_vmovdqu64_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vmovdqu64_m128_xmm(dst, src)) } @@ -5553,2086 +5585,2086 @@ emit_vmovdqu64_m256_ymm :: #force_inline proc(instructions: ^[dynami emit_vmovdqu64_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vmovdqu64_zmm_zmm(dst, src)) } emit_vmovdqu64_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vmovdqu64_zmm_m512(dst, src)) } emit_vmovdqu64_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vmovdqu64_m512_zmm(dst, src)) } -inst_vpblendmb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1677) } -inst_vpblendmb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1677) } -inst_vpblendmb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1678) } -inst_vpblendmb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1678) } -inst_vpblendmb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1679) } -inst_vpblendmb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1679) } +inst_vpblendmb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1689) } +inst_vpblendmb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1689) } +inst_vpblendmb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1690) } +inst_vpblendmb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1690) } +inst_vpblendmb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1691) } +inst_vpblendmb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1691) } emit_vpblendmb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpblendmb_xmm_xmm_xmm(dst, src, src2)) } emit_vpblendmb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpblendmb_xmm_xmm_m128(dst, src, src2)) } emit_vpblendmb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpblendmb_ymm_ymm_ymm(dst, src, src2)) } emit_vpblendmb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpblendmb_ymm_ymm_m256(dst, src, src2)) } emit_vpblendmb_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpblendmb_zmm_zmm_zmm(dst, src, src2)) } emit_vpblendmb_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpblendmb_zmm_zmm_m512(dst, src, src2)) } -inst_vpblendmw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1680) } -inst_vpblendmw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1680) } -inst_vpblendmw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1681) } -inst_vpblendmw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1681) } -inst_vpblendmw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1682) } -inst_vpblendmw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1682) } +inst_vpblendmw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1692) } +inst_vpblendmw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1692) } +inst_vpblendmw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1693) } +inst_vpblendmw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1693) } +inst_vpblendmw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1694) } +inst_vpblendmw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1694) } emit_vpblendmw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpblendmw_xmm_xmm_xmm(dst, src, src2)) } emit_vpblendmw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpblendmw_xmm_xmm_m128(dst, src, src2)) } emit_vpblendmw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpblendmw_ymm_ymm_ymm(dst, src, src2)) } emit_vpblendmw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpblendmw_ymm_ymm_m256(dst, src, src2)) } emit_vpblendmw_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpblendmw_zmm_zmm_zmm(dst, src, src2)) } emit_vpblendmw_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpblendmw_zmm_zmm_m512(dst, src, src2)) } -inst_vpblendmd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1683) } -inst_vpblendmd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1683) } -inst_vpblendmd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1684) } -inst_vpblendmd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1684) } -inst_vpblendmd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1685) } -inst_vpblendmd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1685) } +inst_vpblendmd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1695) } +inst_vpblendmd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1695) } +inst_vpblendmd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1696) } +inst_vpblendmd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1696) } +inst_vpblendmd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1697) } +inst_vpblendmd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1697) } emit_vpblendmd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpblendmd_xmm_xmm_xmm(dst, src, src2)) } emit_vpblendmd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpblendmd_xmm_xmm_m128(dst, src, src2)) } emit_vpblendmd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpblendmd_ymm_ymm_ymm(dst, src, src2)) } emit_vpblendmd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpblendmd_ymm_ymm_m256(dst, src, src2)) } emit_vpblendmd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpblendmd_zmm_zmm_zmm(dst, src, src2)) } emit_vpblendmd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpblendmd_zmm_zmm_m512(dst, src, src2)) } -inst_vpblendmq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1686) } -inst_vpblendmq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1686) } -inst_vpblendmq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1687) } -inst_vpblendmq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1687) } -inst_vpblendmq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1688) } -inst_vpblendmq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1688) } +inst_vpblendmq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1698) } +inst_vpblendmq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1698) } +inst_vpblendmq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1699) } +inst_vpblendmq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1699) } +inst_vpblendmq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1700) } +inst_vpblendmq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPBLENDMQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1700) } emit_vpblendmq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpblendmq_xmm_xmm_xmm(dst, src, src2)) } emit_vpblendmq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpblendmq_xmm_xmm_m128(dst, src, src2)) } emit_vpblendmq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpblendmq_ymm_ymm_ymm(dst, src, src2)) } emit_vpblendmq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpblendmq_ymm_ymm_m256(dst, src, src2)) } emit_vpblendmq_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpblendmq_zmm_zmm_zmm(dst, src, src2)) } emit_vpblendmq_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpblendmq_zmm_zmm_m512(dst, src, src2)) } -inst_vblendmps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1689) } -inst_vblendmps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1689) } -inst_vblendmps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1690) } -inst_vblendmps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1690) } -inst_vblendmps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1691) } -inst_vblendmps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1691) } +inst_vblendmps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1701) } +inst_vblendmps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1701) } +inst_vblendmps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1702) } +inst_vblendmps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1702) } +inst_vblendmps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1703) } +inst_vblendmps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1703) } emit_vblendmps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vblendmps_xmm_xmm_xmm(dst, src, src2)) } emit_vblendmps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vblendmps_xmm_xmm_m128(dst, src, src2)) } emit_vblendmps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vblendmps_ymm_ymm_ymm(dst, src, src2)) } emit_vblendmps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vblendmps_ymm_ymm_m256(dst, src, src2)) } emit_vblendmps_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vblendmps_zmm_zmm_zmm(dst, src, src2)) } emit_vblendmps_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vblendmps_zmm_zmm_m512(dst, src, src2)) } -inst_vblendmpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1692) } -inst_vblendmpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1692) } -inst_vblendmpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1693) } -inst_vblendmpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1693) } -inst_vblendmpd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1694) } -inst_vblendmpd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1694) } +inst_vblendmpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1704) } +inst_vblendmpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1704) } +inst_vblendmpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1705) } +inst_vblendmpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1705) } +inst_vblendmpd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1706) } +inst_vblendmpd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VBLENDMPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1706) } emit_vblendmpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vblendmpd_xmm_xmm_xmm(dst, src, src2)) } emit_vblendmpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vblendmpd_xmm_xmm_m128(dst, src, src2)) } emit_vblendmpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vblendmpd_ymm_ymm_ymm(dst, src, src2)) } emit_vblendmpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vblendmpd_ymm_ymm_m256(dst, src, src2)) } emit_vblendmpd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vblendmpd_zmm_zmm_zmm(dst, src, src2)) } emit_vblendmpd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vblendmpd_zmm_zmm_m512(dst, src, src2)) } -inst_vpcmpb_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1695) } -inst_vpcmpb_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1695) } -inst_vpcmpb_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1696) } -inst_vpcmpb_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1696) } -inst_vpcmpb_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1697) } -inst_vpcmpb_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1697) } +inst_vpcmpb_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1707) } +inst_vpcmpb_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1707) } +inst_vpcmpb_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1708) } +inst_vpcmpb_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1708) } +inst_vpcmpb_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1709) } +inst_vpcmpb_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1709) } emit_vpcmpb_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpb_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpb_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpb_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpb_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpb_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpb_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpb_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpb_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpb_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpb_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpb_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpub_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1698) } -inst_vpcmpub_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1698) } -inst_vpcmpub_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1699) } -inst_vpcmpub_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1699) } -inst_vpcmpub_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1700) } -inst_vpcmpub_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1700) } +inst_vpcmpub_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1710) } +inst_vpcmpub_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1710) } +inst_vpcmpub_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1711) } +inst_vpcmpub_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1711) } +inst_vpcmpub_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1712) } +inst_vpcmpub_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUB, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1712) } emit_vpcmpub_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpub_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpub_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpub_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpub_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpub_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpub_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpub_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpub_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpub_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpub_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpub_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpw_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1701) } -inst_vpcmpw_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1701) } -inst_vpcmpw_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1702) } -inst_vpcmpw_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1702) } -inst_vpcmpw_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1703) } -inst_vpcmpw_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1703) } +inst_vpcmpw_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1713) } +inst_vpcmpw_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1713) } +inst_vpcmpw_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1714) } +inst_vpcmpw_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1714) } +inst_vpcmpw_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1715) } +inst_vpcmpw_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1715) } emit_vpcmpw_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpw_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpw_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpw_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpw_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpw_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpw_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpw_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpw_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpw_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpw_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpw_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpuw_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1704) } -inst_vpcmpuw_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1704) } -inst_vpcmpuw_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1705) } -inst_vpcmpuw_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1705) } -inst_vpcmpuw_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1706) } -inst_vpcmpuw_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1706) } +inst_vpcmpuw_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1716) } +inst_vpcmpuw_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1716) } +inst_vpcmpuw_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1717) } +inst_vpcmpuw_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1717) } +inst_vpcmpuw_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1718) } +inst_vpcmpuw_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUW, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1718) } emit_vpcmpuw_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpuw_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpuw_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpuw_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpuw_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpuw_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpuw_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpuw_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpuw_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpuw_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpuw_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpuw_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpd_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1707) } -inst_vpcmpd_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1707) } -inst_vpcmpd_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1708) } -inst_vpcmpd_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1708) } -inst_vpcmpd_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1709) } -inst_vpcmpd_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1709) } +inst_vpcmpd_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1719) } +inst_vpcmpd_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1719) } +inst_vpcmpd_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1720) } +inst_vpcmpd_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1720) } +inst_vpcmpd_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1721) } +inst_vpcmpd_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1721) } emit_vpcmpd_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpd_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpd_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpd_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpd_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpd_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpd_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpd_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpd_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpd_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpd_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpd_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpud_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1710) } -inst_vpcmpud_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1710) } -inst_vpcmpud_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1711) } -inst_vpcmpud_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1711) } -inst_vpcmpud_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1712) } -inst_vpcmpud_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1712) } +inst_vpcmpud_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1722) } +inst_vpcmpud_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1722) } +inst_vpcmpud_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1723) } +inst_vpcmpud_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1723) } +inst_vpcmpud_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1724) } +inst_vpcmpud_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUD, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1724) } emit_vpcmpud_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpud_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpud_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpud_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpud_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpud_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpud_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpud_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpud_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpud_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpud_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpud_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpq_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1713) } -inst_vpcmpq_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1713) } -inst_vpcmpq_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1714) } -inst_vpcmpq_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1714) } -inst_vpcmpq_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1715) } -inst_vpcmpq_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1715) } +inst_vpcmpq_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1725) } +inst_vpcmpq_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1725) } +inst_vpcmpq_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1726) } +inst_vpcmpq_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1726) } +inst_vpcmpq_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1727) } +inst_vpcmpq_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1727) } emit_vpcmpq_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpq_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpq_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpq_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpq_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpq_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpq_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpq_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpq_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpq_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpq_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpq_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpcmpuq_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1716) } -inst_vpcmpuq_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1716) } -inst_vpcmpuq_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1717) } -inst_vpcmpuq_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1717) } -inst_vpcmpuq_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1718) } -inst_vpcmpuq_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1718) } +inst_vpcmpuq_k_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1728) } +inst_vpcmpuq_k_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1728) } +inst_vpcmpuq_k_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1729) } +inst_vpcmpuq_k_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1729) } +inst_vpcmpuq_k_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1730) } +inst_vpcmpuq_k_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCMPUQ, operand_count = 4, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1730) } emit_vpcmpuq_k_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpcmpuq_k_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpcmpuq_k_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpcmpuq_k_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpcmpuq_k_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpcmpuq_k_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpcmpuq_k_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpcmpuq_k_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpcmpuq_k_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpcmpuq_k_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpcmpuq_k_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpcmpuq_k_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vptestmb_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1719) } -inst_vptestmb_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1719) } -inst_vptestmb_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1720) } -inst_vptestmb_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1720) } -inst_vptestmb_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1721) } -inst_vptestmb_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1721) } +inst_vptestmb_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1731) } +inst_vptestmb_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1731) } +inst_vptestmb_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1732) } +inst_vptestmb_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1732) } +inst_vptestmb_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1733) } +inst_vptestmb_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1733) } emit_vptestmb_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestmb_k_xmm_xmm(dst, src, src2)) } emit_vptestmb_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestmb_k_xmm_m128(dst, src, src2)) } emit_vptestmb_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestmb_k_ymm_ymm(dst, src, src2)) } emit_vptestmb_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestmb_k_ymm_m256(dst, src, src2)) } emit_vptestmb_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestmb_k_zmm_zmm(dst, src, src2)) } emit_vptestmb_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestmb_k_zmm_m512(dst, src, src2)) } -inst_vptestmw_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1722) } -inst_vptestmw_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1722) } -inst_vptestmw_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1723) } -inst_vptestmw_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1723) } -inst_vptestmw_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1724) } -inst_vptestmw_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1724) } +inst_vptestmw_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1734) } +inst_vptestmw_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1734) } +inst_vptestmw_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1735) } +inst_vptestmw_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1735) } +inst_vptestmw_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1736) } +inst_vptestmw_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1736) } emit_vptestmw_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestmw_k_xmm_xmm(dst, src, src2)) } emit_vptestmw_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestmw_k_xmm_m128(dst, src, src2)) } emit_vptestmw_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestmw_k_ymm_ymm(dst, src, src2)) } emit_vptestmw_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestmw_k_ymm_m256(dst, src, src2)) } emit_vptestmw_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestmw_k_zmm_zmm(dst, src, src2)) } emit_vptestmw_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestmw_k_zmm_m512(dst, src, src2)) } -inst_vptestmd_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1725) } -inst_vptestmd_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1725) } -inst_vptestmd_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1726) } -inst_vptestmd_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1726) } -inst_vptestmd_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1727) } -inst_vptestmd_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1727) } +inst_vptestmd_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1737) } +inst_vptestmd_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1737) } +inst_vptestmd_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1738) } +inst_vptestmd_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1738) } +inst_vptestmd_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1739) } +inst_vptestmd_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1739) } emit_vptestmd_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestmd_k_xmm_xmm(dst, src, src2)) } emit_vptestmd_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestmd_k_xmm_m128(dst, src, src2)) } emit_vptestmd_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestmd_k_ymm_ymm(dst, src, src2)) } emit_vptestmd_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestmd_k_ymm_m256(dst, src, src2)) } emit_vptestmd_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestmd_k_zmm_zmm(dst, src, src2)) } emit_vptestmd_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestmd_k_zmm_m512(dst, src, src2)) } -inst_vptestmq_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1728) } -inst_vptestmq_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1728) } -inst_vptestmq_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1729) } -inst_vptestmq_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1729) } -inst_vptestmq_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1730) } -inst_vptestmq_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1730) } +inst_vptestmq_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1740) } +inst_vptestmq_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1740) } +inst_vptestmq_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1741) } +inst_vptestmq_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1741) } +inst_vptestmq_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1742) } +inst_vptestmq_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1742) } emit_vptestmq_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestmq_k_xmm_xmm(dst, src, src2)) } emit_vptestmq_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestmq_k_xmm_m128(dst, src, src2)) } emit_vptestmq_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestmq_k_ymm_ymm(dst, src, src2)) } emit_vptestmq_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestmq_k_ymm_m256(dst, src, src2)) } emit_vptestmq_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestmq_k_zmm_zmm(dst, src, src2)) } emit_vptestmq_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestmq_k_zmm_m512(dst, src, src2)) } -inst_vptestnmb_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1731) } -inst_vptestnmb_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1731) } -inst_vptestnmb_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1732) } -inst_vptestnmb_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1732) } -inst_vptestnmb_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1733) } -inst_vptestnmb_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1733) } +inst_vptestnmb_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1743) } +inst_vptestnmb_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1743) } +inst_vptestnmb_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1744) } +inst_vptestnmb_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1744) } +inst_vptestnmb_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1745) } +inst_vptestnmb_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMB, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1745) } emit_vptestnmb_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestnmb_k_xmm_xmm(dst, src, src2)) } emit_vptestnmb_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestnmb_k_xmm_m128(dst, src, src2)) } emit_vptestnmb_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestnmb_k_ymm_ymm(dst, src, src2)) } emit_vptestnmb_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestnmb_k_ymm_m256(dst, src, src2)) } emit_vptestnmb_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestnmb_k_zmm_zmm(dst, src, src2)) } emit_vptestnmb_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestnmb_k_zmm_m512(dst, src, src2)) } -inst_vptestnmw_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1734) } -inst_vptestnmw_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1734) } -inst_vptestnmw_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1735) } -inst_vptestnmw_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1735) } -inst_vptestnmw_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1736) } -inst_vptestnmw_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1736) } +inst_vptestnmw_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1746) } +inst_vptestnmw_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1746) } +inst_vptestnmw_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1747) } +inst_vptestnmw_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1747) } +inst_vptestnmw_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1748) } +inst_vptestnmw_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMW, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1748) } emit_vptestnmw_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestnmw_k_xmm_xmm(dst, src, src2)) } emit_vptestnmw_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestnmw_k_xmm_m128(dst, src, src2)) } emit_vptestnmw_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestnmw_k_ymm_ymm(dst, src, src2)) } emit_vptestnmw_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestnmw_k_ymm_m256(dst, src, src2)) } emit_vptestnmw_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestnmw_k_zmm_zmm(dst, src, src2)) } emit_vptestnmw_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestnmw_k_zmm_m512(dst, src, src2)) } -inst_vptestnmd_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1737) } -inst_vptestnmd_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1737) } -inst_vptestnmd_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1738) } -inst_vptestnmd_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1738) } -inst_vptestnmd_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1739) } -inst_vptestnmd_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1739) } +inst_vptestnmd_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1749) } +inst_vptestnmd_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1749) } +inst_vptestnmd_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1750) } +inst_vptestnmd_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1750) } +inst_vptestnmd_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1751) } +inst_vptestnmd_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1751) } emit_vptestnmd_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestnmd_k_xmm_xmm(dst, src, src2)) } emit_vptestnmd_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestnmd_k_xmm_m128(dst, src, src2)) } emit_vptestnmd_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestnmd_k_ymm_ymm(dst, src, src2)) } emit_vptestnmd_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestnmd_k_ymm_m256(dst, src, src2)) } emit_vptestnmd_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestnmd_k_zmm_zmm(dst, src, src2)) } emit_vptestnmd_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestnmd_k_zmm_m512(dst, src, src2)) } -inst_vptestnmq_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1740) } -inst_vptestnmq_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1740) } -inst_vptestnmq_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1741) } -inst_vptestnmq_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1741) } -inst_vptestnmq_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1742) } -inst_vptestnmq_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1742) } +inst_vptestnmq_k_xmm_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_xmm(src2), {}} }, 1752) } +inst_vptestnmq_k_xmm_m128 :: #force_inline proc "contextless" (dst: KREG, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1752) } +inst_vptestnmq_k_ymm_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_ymm(src2), {}} }, 1753) } +inst_vptestnmq_k_ymm_m256 :: #force_inline proc "contextless" (dst: KREG, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1753) } +inst_vptestnmq_k_zmm_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_zmm(src2), {}} }, 1754) } +inst_vptestnmq_k_zmm_m512 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTESTNMQ, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1754) } emit_vptestnmq_k_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: XMM) { append(instructions, inst_vptestnmq_k_xmm_xmm(dst, src, src2)) } emit_vptestnmq_k_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, src2: Mem128) { append(instructions, inst_vptestnmq_k_xmm_m128(dst, src, src2)) } emit_vptestnmq_k_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: YMM) { append(instructions, inst_vptestnmq_k_ymm_ymm(dst, src, src2)) } emit_vptestnmq_k_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, src2: Mem256) { append(instructions, inst_vptestnmq_k_ymm_m256(dst, src, src2)) } emit_vptestnmq_k_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: ZMM) { append(instructions, inst_vptestnmq_k_zmm_zmm(dst, src, src2)) } emit_vptestnmq_k_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, src2: Mem512) { append(instructions, inst_vptestnmq_k_zmm_m512(dst, src, src2)) } -inst_vpcompressd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1743) } -inst_vpcompressd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1743) } -inst_vpcompressd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1744) } -inst_vpcompressd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1744) } -inst_vpcompressd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1745) } -inst_vpcompressd_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1745) } +inst_vpcompressd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1755) } +inst_vpcompressd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1755) } +inst_vpcompressd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1756) } +inst_vpcompressd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1756) } +inst_vpcompressd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1757) } +inst_vpcompressd_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSD, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1757) } emit_vpcompressd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpcompressd_xmm_xmm(dst, src)) } emit_vpcompressd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vpcompressd_m128_xmm(dst, src)) } emit_vpcompressd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpcompressd_ymm_ymm(dst, src)) } emit_vpcompressd_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vpcompressd_m256_ymm(dst, src)) } emit_vpcompressd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpcompressd_zmm_zmm(dst, src)) } emit_vpcompressd_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vpcompressd_m512_zmm(dst, src)) } -inst_vpcompressq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1746) } -inst_vpcompressq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1746) } -inst_vpcompressq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1747) } -inst_vpcompressq_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1747) } -inst_vpcompressq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1748) } -inst_vpcompressq_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1748) } +inst_vpcompressq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1758) } +inst_vpcompressq_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1758) } +inst_vpcompressq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1759) } +inst_vpcompressq_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1759) } +inst_vpcompressq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1760) } +inst_vpcompressq_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCOMPRESSQ, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1760) } emit_vpcompressq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpcompressq_xmm_xmm(dst, src)) } emit_vpcompressq_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vpcompressq_m128_xmm(dst, src)) } emit_vpcompressq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpcompressq_ymm_ymm(dst, src)) } emit_vpcompressq_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vpcompressq_m256_ymm(dst, src)) } emit_vpcompressq_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpcompressq_zmm_zmm(dst, src)) } emit_vpcompressq_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vpcompressq_m512_zmm(dst, src)) } -inst_vcompressps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1749) } -inst_vcompressps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1749) } -inst_vcompressps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1750) } -inst_vcompressps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1750) } -inst_vcompressps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1751) } -inst_vcompressps_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1751) } +inst_vcompressps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1761) } +inst_vcompressps_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1761) } +inst_vcompressps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1762) } +inst_vcompressps_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1762) } +inst_vcompressps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1763) } +inst_vcompressps_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPS, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1763) } emit_vcompressps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcompressps_xmm_xmm(dst, src)) } emit_vcompressps_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vcompressps_m128_xmm(dst, src)) } emit_vcompressps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vcompressps_ymm_ymm(dst, src)) } emit_vcompressps_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vcompressps_m256_ymm(dst, src)) } emit_vcompressps_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vcompressps_zmm_zmm(dst, src)) } emit_vcompressps_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vcompressps_m512_zmm(dst, src)) } -inst_vcompresspd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1752) } -inst_vcompresspd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1752) } -inst_vcompresspd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1753) } -inst_vcompresspd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1753) } -inst_vcompresspd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1754) } -inst_vcompresspd_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1754) } +inst_vcompresspd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1764) } +inst_vcompresspd_m128_xmm :: #force_inline proc "contextless" (dst: Mem128, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_xmm(src), {}, {}} }, 1764) } +inst_vcompresspd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1765) } +inst_vcompresspd_m256_ymm :: #force_inline proc "contextless" (dst: Mem256, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_ymm(src), {}, {}} }, 1765) } +inst_vcompresspd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1766) } +inst_vcompresspd_m512_zmm :: #force_inline proc "contextless" (dst: Mem512, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VCOMPRESSPD, operand_count = 2, ops = {op_mem(dst.mem, 64), op_zmm(src), {}, {}} }, 1766) } emit_vcompresspd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vcompresspd_xmm_xmm(dst, src)) } emit_vcompresspd_m128_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: XMM) { append(instructions, inst_vcompresspd_m128_xmm(dst, src)) } emit_vcompresspd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vcompresspd_ymm_ymm(dst, src)) } emit_vcompresspd_m256_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: YMM) { append(instructions, inst_vcompresspd_m256_ymm(dst, src)) } emit_vcompresspd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vcompresspd_zmm_zmm(dst, src)) } emit_vcompresspd_m512_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512, src: ZMM) { append(instructions, inst_vcompresspd_m512_zmm(dst, src)) } -inst_vpexpandd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1755) } -inst_vpexpandd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1755) } -inst_vpexpandd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1756) } -inst_vpexpandd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1756) } -inst_vpexpandd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1757) } -inst_vpexpandd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1757) } +inst_vpexpandd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1767) } +inst_vpexpandd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1767) } +inst_vpexpandd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1768) } +inst_vpexpandd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1768) } +inst_vpexpandd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1769) } +inst_vpexpandd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1769) } emit_vpexpandd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpexpandd_xmm_xmm(dst, src)) } emit_vpexpandd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpexpandd_xmm_m128(dst, src)) } emit_vpexpandd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpexpandd_ymm_ymm(dst, src)) } emit_vpexpandd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpexpandd_ymm_m256(dst, src)) } emit_vpexpandd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpexpandd_zmm_zmm(dst, src)) } emit_vpexpandd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vpexpandd_zmm_m512(dst, src)) } -inst_vpexpandq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1758) } -inst_vpexpandq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1758) } -inst_vpexpandq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1759) } -inst_vpexpandq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1759) } -inst_vpexpandq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1760) } -inst_vpexpandq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1760) } +inst_vpexpandq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1770) } +inst_vpexpandq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1770) } +inst_vpexpandq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1771) } +inst_vpexpandq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1771) } +inst_vpexpandq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1772) } +inst_vpexpandq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPEXPANDQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1772) } emit_vpexpandq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpexpandq_xmm_xmm(dst, src)) } emit_vpexpandq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpexpandq_xmm_m128(dst, src)) } emit_vpexpandq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpexpandq_ymm_ymm(dst, src)) } emit_vpexpandq_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpexpandq_ymm_m256(dst, src)) } emit_vpexpandq_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpexpandq_zmm_zmm(dst, src)) } emit_vpexpandq_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vpexpandq_zmm_m512(dst, src)) } -inst_vexpandps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1761) } -inst_vexpandps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1761) } -inst_vexpandps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1762) } -inst_vexpandps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1762) } -inst_vexpandps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1763) } -inst_vexpandps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1763) } +inst_vexpandps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1773) } +inst_vexpandps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1773) } +inst_vexpandps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1774) } +inst_vexpandps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1774) } +inst_vexpandps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1775) } +inst_vexpandps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1775) } emit_vexpandps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vexpandps_xmm_xmm(dst, src)) } emit_vexpandps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vexpandps_xmm_m128(dst, src)) } emit_vexpandps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vexpandps_ymm_ymm(dst, src)) } emit_vexpandps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vexpandps_ymm_m256(dst, src)) } emit_vexpandps_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vexpandps_zmm_zmm(dst, src)) } emit_vexpandps_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vexpandps_zmm_m512(dst, src)) } -inst_vexpandpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1764) } -inst_vexpandpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1764) } -inst_vexpandpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1765) } -inst_vexpandpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1765) } -inst_vexpandpd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1766) } -inst_vexpandpd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1766) } +inst_vexpandpd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1776) } +inst_vexpandpd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1776) } +inst_vexpandpd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1777) } +inst_vexpandpd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1777) } +inst_vexpandpd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1778) } +inst_vexpandpd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VEXPANDPD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1778) } emit_vexpandpd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vexpandpd_xmm_xmm(dst, src)) } emit_vexpandpd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vexpandpd_xmm_m128(dst, src)) } emit_vexpandpd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vexpandpd_ymm_ymm(dst, src)) } emit_vexpandpd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vexpandpd_ymm_m256(dst, src)) } emit_vexpandpd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vexpandpd_zmm_zmm(dst, src)) } emit_vexpandpd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vexpandpd_zmm_m512(dst, src)) } -inst_vpconflictd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1767) } -inst_vpconflictd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1767) } -inst_vpconflictd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1768) } -inst_vpconflictd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1768) } -inst_vpconflictd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1769) } -inst_vpconflictd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1769) } +inst_vpconflictd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1779) } +inst_vpconflictd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1779) } +inst_vpconflictd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1780) } +inst_vpconflictd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1780) } +inst_vpconflictd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1781) } +inst_vpconflictd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1781) } emit_vpconflictd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpconflictd_xmm_xmm(dst, src)) } emit_vpconflictd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpconflictd_xmm_m128(dst, src)) } emit_vpconflictd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpconflictd_ymm_ymm(dst, src)) } emit_vpconflictd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpconflictd_ymm_m256(dst, src)) } emit_vpconflictd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpconflictd_zmm_zmm(dst, src)) } emit_vpconflictd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vpconflictd_zmm_m512(dst, src)) } -inst_vpconflictq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1770) } -inst_vpconflictq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1770) } -inst_vpconflictq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1771) } -inst_vpconflictq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1771) } -inst_vpconflictq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1772) } -inst_vpconflictq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1772) } +inst_vpconflictq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1782) } +inst_vpconflictq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1782) } +inst_vpconflictq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1783) } +inst_vpconflictq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1783) } +inst_vpconflictq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1784) } +inst_vpconflictq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPCONFLICTQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1784) } emit_vpconflictq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpconflictq_xmm_xmm(dst, src)) } emit_vpconflictq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vpconflictq_xmm_m128(dst, src)) } emit_vpconflictq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vpconflictq_ymm_ymm(dst, src)) } emit_vpconflictq_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vpconflictq_ymm_m256(dst, src)) } emit_vpconflictq_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vpconflictq_zmm_zmm(dst, src)) } emit_vpconflictq_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vpconflictq_zmm_m512(dst, src)) } -inst_vplzcntd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1773) } -inst_vplzcntd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1773) } -inst_vplzcntd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1774) } -inst_vplzcntd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1774) } -inst_vplzcntd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1775) } -inst_vplzcntd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1775) } +inst_vplzcntd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1785) } +inst_vplzcntd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1785) } +inst_vplzcntd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1786) } +inst_vplzcntd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1786) } +inst_vplzcntd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1787) } +inst_vplzcntd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1787) } emit_vplzcntd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vplzcntd_xmm_xmm(dst, src)) } emit_vplzcntd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vplzcntd_xmm_m128(dst, src)) } emit_vplzcntd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vplzcntd_ymm_ymm(dst, src)) } emit_vplzcntd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vplzcntd_ymm_m256(dst, src)) } emit_vplzcntd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vplzcntd_zmm_zmm(dst, src)) } emit_vplzcntd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vplzcntd_zmm_m512(dst, src)) } -inst_vplzcntq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1776) } -inst_vplzcntq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1776) } -inst_vplzcntq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1777) } -inst_vplzcntq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1777) } -inst_vplzcntq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1778) } -inst_vplzcntq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1778) } +inst_vplzcntq_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1788) } +inst_vplzcntq_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1788) } +inst_vplzcntq_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1789) } +inst_vplzcntq_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1789) } +inst_vplzcntq_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1790) } +inst_vplzcntq_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPLZCNTQ, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1790) } emit_vplzcntq_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vplzcntq_xmm_xmm(dst, src)) } emit_vplzcntq_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vplzcntq_xmm_m128(dst, src)) } emit_vplzcntq_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vplzcntq_ymm_ymm(dst, src)) } emit_vplzcntq_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vplzcntq_ymm_m256(dst, src)) } emit_vplzcntq_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vplzcntq_zmm_zmm(dst, src)) } emit_vplzcntq_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vplzcntq_zmm_m512(dst, src)) } -inst_vpermi2b_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1779) } -inst_vpermi2b_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1779) } -inst_vpermi2b_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1780) } -inst_vpermi2b_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1780) } -inst_vpermi2b_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1781) } -inst_vpermi2b_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1781) } +inst_vpermi2b_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1791) } +inst_vpermi2b_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1791) } +inst_vpermi2b_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1792) } +inst_vpermi2b_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1792) } +inst_vpermi2b_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1793) } +inst_vpermi2b_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1793) } emit_vpermi2b_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2b_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2b_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2b_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2b_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2b_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2b_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2b_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2b_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2b_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2b_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2b_zmm_zmm_m512(dst, src, src2)) } -inst_vpermi2w_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1782) } -inst_vpermi2w_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1782) } -inst_vpermi2w_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1783) } -inst_vpermi2w_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1783) } -inst_vpermi2w_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1784) } -inst_vpermi2w_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1784) } +inst_vpermi2w_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1794) } +inst_vpermi2w_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1794) } +inst_vpermi2w_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1795) } +inst_vpermi2w_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1795) } +inst_vpermi2w_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1796) } +inst_vpermi2w_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1796) } emit_vpermi2w_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2w_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2w_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2w_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2w_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2w_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2w_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2w_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2w_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2w_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2w_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2w_zmm_zmm_m512(dst, src, src2)) } -inst_vpermi2d_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1785) } -inst_vpermi2d_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1785) } -inst_vpermi2d_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1786) } -inst_vpermi2d_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1786) } -inst_vpermi2d_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1787) } -inst_vpermi2d_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1787) } +inst_vpermi2d_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1797) } +inst_vpermi2d_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1797) } +inst_vpermi2d_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1798) } +inst_vpermi2d_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1798) } +inst_vpermi2d_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1799) } +inst_vpermi2d_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1799) } emit_vpermi2d_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2d_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2d_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2d_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2d_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2d_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2d_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2d_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2d_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2d_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2d_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2d_zmm_zmm_m512(dst, src, src2)) } -inst_vpermi2q_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1788) } -inst_vpermi2q_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1788) } -inst_vpermi2q_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1789) } -inst_vpermi2q_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1789) } -inst_vpermi2q_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1790) } -inst_vpermi2q_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1790) } +inst_vpermi2q_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1800) } +inst_vpermi2q_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1800) } +inst_vpermi2q_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1801) } +inst_vpermi2q_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1801) } +inst_vpermi2q_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1802) } +inst_vpermi2q_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1802) } emit_vpermi2q_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2q_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2q_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2q_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2q_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2q_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2q_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2q_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2q_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2q_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2q_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2q_zmm_zmm_m512(dst, src, src2)) } -inst_vpermi2ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1791) } -inst_vpermi2ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1791) } -inst_vpermi2ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1792) } -inst_vpermi2ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1792) } -inst_vpermi2ps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1793) } -inst_vpermi2ps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1793) } +inst_vpermi2ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1803) } +inst_vpermi2ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1803) } +inst_vpermi2ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1804) } +inst_vpermi2ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1804) } +inst_vpermi2ps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1805) } +inst_vpermi2ps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1805) } emit_vpermi2ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2ps_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2ps_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2ps_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2ps_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2ps_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2ps_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2ps_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2ps_zmm_zmm_m512(dst, src, src2)) } -inst_vpermi2pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1794) } -inst_vpermi2pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1794) } -inst_vpermi2pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1795) } -inst_vpermi2pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1795) } -inst_vpermi2pd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1796) } -inst_vpermi2pd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1796) } +inst_vpermi2pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1806) } +inst_vpermi2pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1806) } +inst_vpermi2pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1807) } +inst_vpermi2pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1807) } +inst_vpermi2pd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1808) } +inst_vpermi2pd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMI2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1808) } emit_vpermi2pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermi2pd_xmm_xmm_xmm(dst, src, src2)) } emit_vpermi2pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermi2pd_xmm_xmm_m128(dst, src, src2)) } emit_vpermi2pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermi2pd_ymm_ymm_ymm(dst, src, src2)) } emit_vpermi2pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermi2pd_ymm_ymm_m256(dst, src, src2)) } emit_vpermi2pd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermi2pd_zmm_zmm_zmm(dst, src, src2)) } emit_vpermi2pd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermi2pd_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2b_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1797) } -inst_vpermt2b_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1797) } -inst_vpermt2b_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1798) } -inst_vpermt2b_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1798) } -inst_vpermt2b_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1799) } -inst_vpermt2b_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1799) } +inst_vpermt2b_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1809) } +inst_vpermt2b_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1809) } +inst_vpermt2b_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1810) } +inst_vpermt2b_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1810) } +inst_vpermt2b_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1811) } +inst_vpermt2b_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2B, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1811) } emit_vpermt2b_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2b_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2b_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2b_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2b_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2b_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2b_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2b_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2b_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2b_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2b_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2b_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2w_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1800) } -inst_vpermt2w_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1800) } -inst_vpermt2w_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1801) } -inst_vpermt2w_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1801) } -inst_vpermt2w_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1802) } -inst_vpermt2w_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1802) } +inst_vpermt2w_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1812) } +inst_vpermt2w_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1812) } +inst_vpermt2w_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1813) } +inst_vpermt2w_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1813) } +inst_vpermt2w_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1814) } +inst_vpermt2w_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2W, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1814) } emit_vpermt2w_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2w_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2w_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2w_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2w_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2w_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2w_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2w_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2w_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2w_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2w_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2w_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2d_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1803) } -inst_vpermt2d_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1803) } -inst_vpermt2d_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1804) } -inst_vpermt2d_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1804) } -inst_vpermt2d_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1805) } -inst_vpermt2d_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1805) } +inst_vpermt2d_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1815) } +inst_vpermt2d_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1815) } +inst_vpermt2d_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1816) } +inst_vpermt2d_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1816) } +inst_vpermt2d_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1817) } +inst_vpermt2d_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2D, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1817) } emit_vpermt2d_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2d_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2d_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2d_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2d_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2d_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2d_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2d_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2d_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2d_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2d_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2d_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2q_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1806) } -inst_vpermt2q_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1806) } -inst_vpermt2q_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1807) } -inst_vpermt2q_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1807) } -inst_vpermt2q_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1808) } -inst_vpermt2q_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1808) } +inst_vpermt2q_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1818) } +inst_vpermt2q_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1818) } +inst_vpermt2q_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1819) } +inst_vpermt2q_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1819) } +inst_vpermt2q_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1820) } +inst_vpermt2q_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2Q, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1820) } emit_vpermt2q_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2q_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2q_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2q_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2q_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2q_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2q_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2q_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2q_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2q_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2q_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2q_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1809) } -inst_vpermt2ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1809) } -inst_vpermt2ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1810) } -inst_vpermt2ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1810) } -inst_vpermt2ps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1811) } -inst_vpermt2ps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1811) } +inst_vpermt2ps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1821) } +inst_vpermt2ps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1821) } +inst_vpermt2ps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1822) } +inst_vpermt2ps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1822) } +inst_vpermt2ps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1823) } +inst_vpermt2ps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1823) } emit_vpermt2ps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2ps_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2ps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2ps_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2ps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2ps_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2ps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2ps_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2ps_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2ps_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2ps_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2ps_zmm_zmm_m512(dst, src, src2)) } -inst_vpermt2pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1812) } -inst_vpermt2pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1812) } -inst_vpermt2pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1813) } -inst_vpermt2pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1813) } -inst_vpermt2pd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1814) } -inst_vpermt2pd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1814) } +inst_vpermt2pd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1824) } +inst_vpermt2pd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1824) } +inst_vpermt2pd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1825) } +inst_vpermt2pd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1825) } +inst_vpermt2pd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1826) } +inst_vpermt2pd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMT2PD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1826) } emit_vpermt2pd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermt2pd_xmm_xmm_xmm(dst, src, src2)) } emit_vpermt2pd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermt2pd_xmm_xmm_m128(dst, src, src2)) } emit_vpermt2pd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermt2pd_ymm_ymm_ymm(dst, src, src2)) } emit_vpermt2pd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermt2pd_ymm_ymm_m256(dst, src, src2)) } emit_vpermt2pd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermt2pd_zmm_zmm_zmm(dst, src, src2)) } emit_vpermt2pd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermt2pd_zmm_zmm_m512(dst, src, src2)) } -inst_vpermb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1815) } -inst_vpermb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1815) } -inst_vpermb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1816) } -inst_vpermb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1816) } -inst_vpermb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1817) } -inst_vpermb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1817) } +inst_vpermb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1827) } +inst_vpermb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1827) } +inst_vpermb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1828) } +inst_vpermb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1828) } +inst_vpermb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1829) } +inst_vpermb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1829) } emit_vpermb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermb_xmm_xmm_xmm(dst, src, src2)) } emit_vpermb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermb_xmm_xmm_m128(dst, src, src2)) } emit_vpermb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermb_ymm_ymm_ymm(dst, src, src2)) } emit_vpermb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermb_ymm_ymm_m256(dst, src, src2)) } emit_vpermb_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermb_zmm_zmm_zmm(dst, src, src2)) } emit_vpermb_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermb_zmm_zmm_m512(dst, src, src2)) } -inst_vpermw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1818) } -inst_vpermw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1818) } -inst_vpermw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1819) } -inst_vpermw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1819) } -inst_vpermw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1820) } -inst_vpermw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1820) } +inst_vpermw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1830) } +inst_vpermw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1830) } +inst_vpermw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1831) } +inst_vpermw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1831) } +inst_vpermw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1832) } +inst_vpermw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPERMW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1832) } emit_vpermw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpermw_xmm_xmm_xmm(dst, src, src2)) } emit_vpermw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpermw_xmm_xmm_m128(dst, src, src2)) } emit_vpermw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpermw_ymm_ymm_ymm(dst, src, src2)) } emit_vpermw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpermw_ymm_ymm_m256(dst, src, src2)) } emit_vpermw_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpermw_zmm_zmm_zmm(dst, src, src2)) } emit_vpermw_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpermw_zmm_zmm_m512(dst, src, src2)) } -inst_vpmovb2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1821) } -inst_vpmovb2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1822) } -inst_vpmovb2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1823) } +inst_vpmovb2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1833) } +inst_vpmovb2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1834) } +inst_vpmovb2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVB2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1835) } emit_vpmovb2m_k_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM) { append(instructions, inst_vpmovb2m_k_xmm(dst, src)) } emit_vpmovb2m_k_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM) { append(instructions, inst_vpmovb2m_k_ymm(dst, src)) } emit_vpmovb2m_k_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM) { append(instructions, inst_vpmovb2m_k_zmm(dst, src)) } -inst_vpmovw2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1824) } -inst_vpmovw2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1825) } -inst_vpmovw2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1826) } +inst_vpmovw2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1836) } +inst_vpmovw2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1837) } +inst_vpmovw2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVW2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1838) } emit_vpmovw2m_k_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM) { append(instructions, inst_vpmovw2m_k_xmm(dst, src)) } emit_vpmovw2m_k_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM) { append(instructions, inst_vpmovw2m_k_ymm(dst, src)) } emit_vpmovw2m_k_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM) { append(instructions, inst_vpmovw2m_k_zmm(dst, src)) } -inst_vpmovd2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1827) } -inst_vpmovd2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1828) } -inst_vpmovd2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1829) } +inst_vpmovd2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1839) } +inst_vpmovd2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1840) } +inst_vpmovd2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVD2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1841) } emit_vpmovd2m_k_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM) { append(instructions, inst_vpmovd2m_k_xmm(dst, src)) } emit_vpmovd2m_k_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM) { append(instructions, inst_vpmovd2m_k_ymm(dst, src)) } emit_vpmovd2m_k_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM) { append(instructions, inst_vpmovd2m_k_zmm(dst, src)) } -inst_vpmovq2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1830) } -inst_vpmovq2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1831) } -inst_vpmovq2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1832) } +inst_vpmovq2m_k_xmm :: #force_inline proc "contextless" (dst: KREG, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_xmm(src), {}, {}} }, 1842) } +inst_vpmovq2m_k_ymm :: #force_inline proc "contextless" (dst: KREG, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_ymm(src), {}, {}} }, 1843) } +inst_vpmovq2m_k_zmm :: #force_inline proc "contextless" (dst: KREG, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQ2M, operand_count = 2, ops = {op_kreg(dst), op_zmm(src), {}, {}} }, 1844) } emit_vpmovq2m_k_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM) { append(instructions, inst_vpmovq2m_k_xmm(dst, src)) } emit_vpmovq2m_k_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM) { append(instructions, inst_vpmovq2m_k_ymm(dst, src)) } emit_vpmovq2m_k_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM) { append(instructions, inst_vpmovq2m_k_zmm(dst, src)) } -inst_vpmovm2b_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1833) } -inst_vpmovm2b_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1834) } -inst_vpmovm2b_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1835) } +inst_vpmovm2b_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1845) } +inst_vpmovm2b_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1846) } +inst_vpmovm2b_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2B, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1847) } emit_vpmovm2b_xmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: KREG) { append(instructions, inst_vpmovm2b_xmm_k(dst, src)) } emit_vpmovm2b_ymm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: KREG) { append(instructions, inst_vpmovm2b_ymm_k(dst, src)) } emit_vpmovm2b_zmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: KREG) { append(instructions, inst_vpmovm2b_zmm_k(dst, src)) } -inst_vpmovm2w_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1836) } -inst_vpmovm2w_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1837) } -inst_vpmovm2w_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1838) } +inst_vpmovm2w_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1848) } +inst_vpmovm2w_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1849) } +inst_vpmovm2w_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2W, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1850) } emit_vpmovm2w_xmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: KREG) { append(instructions, inst_vpmovm2w_xmm_k(dst, src)) } emit_vpmovm2w_ymm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: KREG) { append(instructions, inst_vpmovm2w_ymm_k(dst, src)) } emit_vpmovm2w_zmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: KREG) { append(instructions, inst_vpmovm2w_zmm_k(dst, src)) } -inst_vpmovm2d_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1839) } -inst_vpmovm2d_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1840) } -inst_vpmovm2d_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1841) } +inst_vpmovm2d_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1851) } +inst_vpmovm2d_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1852) } +inst_vpmovm2d_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2D, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1853) } emit_vpmovm2d_xmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: KREG) { append(instructions, inst_vpmovm2d_xmm_k(dst, src)) } emit_vpmovm2d_ymm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: KREG) { append(instructions, inst_vpmovm2d_ymm_k(dst, src)) } emit_vpmovm2d_zmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: KREG) { append(instructions, inst_vpmovm2d_zmm_k(dst, src)) } -inst_vpmovm2q_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1842) } -inst_vpmovm2q_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1843) } -inst_vpmovm2q_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1844) } +inst_vpmovm2q_xmm_k :: #force_inline proc "contextless" (dst: XMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_xmm(dst), op_kreg(src), {}, {}} }, 1854) } +inst_vpmovm2q_ymm_k :: #force_inline proc "contextless" (dst: YMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_ymm(dst), op_kreg(src), {}, {}} }, 1855) } +inst_vpmovm2q_zmm_k :: #force_inline proc "contextless" (dst: ZMM, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVM2Q, operand_count = 2, ops = {op_zmm(dst), op_kreg(src), {}, {}} }, 1856) } emit_vpmovm2q_xmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: KREG) { append(instructions, inst_vpmovm2q_xmm_k(dst, src)) } emit_vpmovm2q_ymm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: KREG) { append(instructions, inst_vpmovm2q_ymm_k(dst, src)) } emit_vpmovm2q_zmm_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: KREG) { append(instructions, inst_vpmovm2q_zmm_k(dst, src)) } -inst_vpmovqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1845) } -inst_vpmovqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1845) } -inst_vpmovqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1846) } -inst_vpmovqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1846) } -inst_vpmovqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1847) } -inst_vpmovqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1847) } +inst_vpmovqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1857) } +inst_vpmovqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1857) } +inst_vpmovqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1858) } +inst_vpmovqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1858) } +inst_vpmovqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1859) } +inst_vpmovqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1859) } emit_vpmovqb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovqb_xmm_xmm(dst, src)) } emit_vpmovqb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovqb_m32_xmm(dst, src)) } emit_vpmovqb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovqb_xmm_ymm(dst, src)) } emit_vpmovqb_m32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: YMM) { append(instructions, inst_vpmovqb_m32_ymm(dst, src)) } emit_vpmovqb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovqb_xmm_zmm(dst, src)) } emit_vpmovqb_m64_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: ZMM) { append(instructions, inst_vpmovqb_m64_zmm(dst, src)) } -inst_vpmovsqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1848) } -inst_vpmovsqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1848) } -inst_vpmovsqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1849) } -inst_vpmovsqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1849) } -inst_vpmovsqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1850) } -inst_vpmovsqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1850) } +inst_vpmovsqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1860) } +inst_vpmovsqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1860) } +inst_vpmovsqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1861) } +inst_vpmovsqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1861) } +inst_vpmovsqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1862) } +inst_vpmovsqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1862) } emit_vpmovsqb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsqb_xmm_xmm(dst, src)) } emit_vpmovsqb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovsqb_m32_xmm(dst, src)) } emit_vpmovsqb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovsqb_xmm_ymm(dst, src)) } emit_vpmovsqb_m32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: YMM) { append(instructions, inst_vpmovsqb_m32_ymm(dst, src)) } emit_vpmovsqb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovsqb_xmm_zmm(dst, src)) } emit_vpmovsqb_m64_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: ZMM) { append(instructions, inst_vpmovsqb_m64_zmm(dst, src)) } -inst_vpmovusqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1851) } -inst_vpmovusqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1851) } -inst_vpmovusqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1852) } -inst_vpmovusqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1852) } -inst_vpmovusqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1853) } -inst_vpmovusqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1853) } +inst_vpmovusqb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1863) } +inst_vpmovusqb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1863) } +inst_vpmovusqb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1864) } +inst_vpmovusqb_m32_ymm :: #force_inline proc "contextless" (dst: Mem32, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_ymm(src), {}, {}} }, 1864) } +inst_vpmovusqb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1865) } +inst_vpmovusqb_m64_zmm :: #force_inline proc "contextless" (dst: Mem64, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_zmm(src), {}, {}} }, 1865) } emit_vpmovusqb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovusqb_xmm_xmm(dst, src)) } emit_vpmovusqb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovusqb_m32_xmm(dst, src)) } emit_vpmovusqb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovusqb_xmm_ymm(dst, src)) } emit_vpmovusqb_m32_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: YMM) { append(instructions, inst_vpmovusqb_m32_ymm(dst, src)) } emit_vpmovusqb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovusqb_xmm_zmm(dst, src)) } emit_vpmovusqb_m64_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: ZMM) { append(instructions, inst_vpmovusqb_m64_zmm(dst, src)) } -inst_vpmovqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1854) } -inst_vpmovqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1854) } -inst_vpmovqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1855) } -inst_vpmovqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1855) } -inst_vpmovqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1856) } -inst_vpmovqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1856) } +inst_vpmovqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1866) } +inst_vpmovqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1866) } +inst_vpmovqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1867) } +inst_vpmovqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1867) } +inst_vpmovqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1868) } +inst_vpmovqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1868) } emit_vpmovqw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovqw_xmm_xmm(dst, src)) } emit_vpmovqw_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovqw_m32_xmm(dst, src)) } emit_vpmovqw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovqw_xmm_ymm(dst, src)) } emit_vpmovqw_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovqw_m64_ymm(dst, src)) } emit_vpmovqw_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovqw_xmm_zmm(dst, src)) } emit_vpmovqw_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovqw_m128_zmm(dst, src)) } -inst_vpmovsqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1857) } -inst_vpmovsqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1857) } -inst_vpmovsqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1858) } -inst_vpmovsqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1858) } -inst_vpmovsqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1859) } -inst_vpmovsqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1859) } +inst_vpmovsqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1869) } +inst_vpmovsqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1869) } +inst_vpmovsqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1870) } +inst_vpmovsqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1870) } +inst_vpmovsqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1871) } +inst_vpmovsqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1871) } emit_vpmovsqw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsqw_xmm_xmm(dst, src)) } emit_vpmovsqw_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovsqw_m32_xmm(dst, src)) } emit_vpmovsqw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovsqw_xmm_ymm(dst, src)) } emit_vpmovsqw_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovsqw_m64_ymm(dst, src)) } emit_vpmovsqw_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovsqw_xmm_zmm(dst, src)) } emit_vpmovsqw_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovsqw_m128_zmm(dst, src)) } -inst_vpmovusqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1860) } -inst_vpmovusqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1860) } -inst_vpmovusqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1861) } -inst_vpmovusqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1861) } -inst_vpmovusqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1862) } -inst_vpmovusqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1862) } +inst_vpmovusqw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1872) } +inst_vpmovusqw_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1872) } +inst_vpmovusqw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1873) } +inst_vpmovusqw_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1873) } +inst_vpmovusqw_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1874) } +inst_vpmovusqw_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1874) } emit_vpmovusqw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovusqw_xmm_xmm(dst, src)) } emit_vpmovusqw_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovusqw_m32_xmm(dst, src)) } emit_vpmovusqw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovusqw_xmm_ymm(dst, src)) } emit_vpmovusqw_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovusqw_m64_ymm(dst, src)) } emit_vpmovusqw_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovusqw_xmm_zmm(dst, src)) } emit_vpmovusqw_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovusqw_m128_zmm(dst, src)) } -inst_vpmovqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1863) } -inst_vpmovqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1863) } -inst_vpmovqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1864) } -inst_vpmovqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1864) } -inst_vpmovqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1865) } -inst_vpmovqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1865) } +inst_vpmovqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1875) } +inst_vpmovqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1875) } +inst_vpmovqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1876) } +inst_vpmovqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1876) } +inst_vpmovqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1877) } +inst_vpmovqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1877) } emit_vpmovqd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovqd_xmm_xmm(dst, src)) } emit_vpmovqd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovqd_m64_xmm(dst, src)) } emit_vpmovqd_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovqd_xmm_ymm(dst, src)) } emit_vpmovqd_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovqd_m128_ymm(dst, src)) } emit_vpmovqd_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovqd_ymm_zmm(dst, src)) } emit_vpmovqd_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovqd_m256_zmm(dst, src)) } -inst_vpmovsqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1866) } -inst_vpmovsqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1866) } -inst_vpmovsqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1867) } -inst_vpmovsqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1867) } -inst_vpmovsqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1868) } -inst_vpmovsqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1868) } +inst_vpmovsqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1878) } +inst_vpmovsqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1878) } +inst_vpmovsqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1879) } +inst_vpmovsqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1879) } +inst_vpmovsqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1880) } +inst_vpmovsqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1880) } emit_vpmovsqd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsqd_xmm_xmm(dst, src)) } emit_vpmovsqd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovsqd_m64_xmm(dst, src)) } emit_vpmovsqd_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovsqd_xmm_ymm(dst, src)) } emit_vpmovsqd_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovsqd_m128_ymm(dst, src)) } emit_vpmovsqd_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovsqd_ymm_zmm(dst, src)) } emit_vpmovsqd_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovsqd_m256_zmm(dst, src)) } -inst_vpmovusqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1869) } -inst_vpmovusqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1869) } -inst_vpmovusqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1870) } -inst_vpmovusqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1870) } -inst_vpmovusqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1871) } -inst_vpmovusqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1871) } +inst_vpmovusqd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1881) } +inst_vpmovusqd_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1881) } +inst_vpmovusqd_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1882) } +inst_vpmovusqd_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1882) } +inst_vpmovusqd_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1883) } +inst_vpmovusqd_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSQD, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1883) } emit_vpmovusqd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovusqd_xmm_xmm(dst, src)) } emit_vpmovusqd_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovusqd_m64_xmm(dst, src)) } emit_vpmovusqd_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovusqd_xmm_ymm(dst, src)) } emit_vpmovusqd_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovusqd_m128_ymm(dst, src)) } emit_vpmovusqd_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovusqd_ymm_zmm(dst, src)) } emit_vpmovusqd_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovusqd_m256_zmm(dst, src)) } -inst_vpmovdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1872) } -inst_vpmovdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1872) } -inst_vpmovdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1873) } -inst_vpmovdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1873) } -inst_vpmovdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1874) } -inst_vpmovdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1874) } +inst_vpmovdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1884) } +inst_vpmovdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1884) } +inst_vpmovdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1885) } +inst_vpmovdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1885) } +inst_vpmovdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1886) } +inst_vpmovdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1886) } emit_vpmovdb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovdb_xmm_xmm(dst, src)) } emit_vpmovdb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovdb_m32_xmm(dst, src)) } emit_vpmovdb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovdb_xmm_ymm(dst, src)) } emit_vpmovdb_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovdb_m64_ymm(dst, src)) } emit_vpmovdb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovdb_xmm_zmm(dst, src)) } emit_vpmovdb_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovdb_m128_zmm(dst, src)) } -inst_vpmovsdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1875) } -inst_vpmovsdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1875) } -inst_vpmovsdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1876) } -inst_vpmovsdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1876) } -inst_vpmovsdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1877) } -inst_vpmovsdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1877) } +inst_vpmovsdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1887) } +inst_vpmovsdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1887) } +inst_vpmovsdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1888) } +inst_vpmovsdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1888) } +inst_vpmovsdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1889) } +inst_vpmovsdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1889) } emit_vpmovsdb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsdb_xmm_xmm(dst, src)) } emit_vpmovsdb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovsdb_m32_xmm(dst, src)) } emit_vpmovsdb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovsdb_xmm_ymm(dst, src)) } emit_vpmovsdb_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovsdb_m64_ymm(dst, src)) } emit_vpmovsdb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovsdb_xmm_zmm(dst, src)) } emit_vpmovsdb_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovsdb_m128_zmm(dst, src)) } -inst_vpmovusdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1878) } -inst_vpmovusdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1878) } -inst_vpmovusdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1879) } -inst_vpmovusdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1879) } -inst_vpmovusdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1880) } -inst_vpmovusdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1880) } +inst_vpmovusdb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1890) } +inst_vpmovusdb_m32_xmm :: #force_inline proc "contextless" (dst: Mem32, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 4), op_xmm(src), {}, {}} }, 1890) } +inst_vpmovusdb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1891) } +inst_vpmovusdb_m64_ymm :: #force_inline proc "contextless" (dst: Mem64, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_ymm(src), {}, {}} }, 1891) } +inst_vpmovusdb_xmm_zmm :: #force_inline proc "contextless" (dst: XMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_xmm(dst), op_zmm(src), {}, {}} }, 1892) } +inst_vpmovusdb_m128_zmm :: #force_inline proc "contextless" (dst: Mem128, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_zmm(src), {}, {}} }, 1892) } emit_vpmovusdb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovusdb_xmm_xmm(dst, src)) } emit_vpmovusdb_m32_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: XMM) { append(instructions, inst_vpmovusdb_m32_xmm(dst, src)) } emit_vpmovusdb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovusdb_xmm_ymm(dst, src)) } emit_vpmovusdb_m64_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: YMM) { append(instructions, inst_vpmovusdb_m64_ymm(dst, src)) } emit_vpmovusdb_xmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: ZMM) { append(instructions, inst_vpmovusdb_xmm_zmm(dst, src)) } emit_vpmovusdb_m128_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: ZMM) { append(instructions, inst_vpmovusdb_m128_zmm(dst, src)) } -inst_vpmovdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1881) } -inst_vpmovdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1881) } -inst_vpmovdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1882) } -inst_vpmovdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1882) } -inst_vpmovdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1883) } -inst_vpmovdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1883) } +inst_vpmovdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1893) } +inst_vpmovdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1893) } +inst_vpmovdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1894) } +inst_vpmovdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1894) } +inst_vpmovdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1895) } +inst_vpmovdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1895) } emit_vpmovdw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovdw_xmm_xmm(dst, src)) } emit_vpmovdw_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovdw_m64_xmm(dst, src)) } emit_vpmovdw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovdw_xmm_ymm(dst, src)) } emit_vpmovdw_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovdw_m128_ymm(dst, src)) } emit_vpmovdw_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovdw_ymm_zmm(dst, src)) } emit_vpmovdw_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovdw_m256_zmm(dst, src)) } -inst_vpmovsdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1884) } -inst_vpmovsdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1884) } -inst_vpmovsdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1885) } -inst_vpmovsdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1885) } -inst_vpmovsdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1886) } -inst_vpmovsdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1886) } +inst_vpmovsdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1896) } +inst_vpmovsdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1896) } +inst_vpmovsdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1897) } +inst_vpmovsdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1897) } +inst_vpmovsdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1898) } +inst_vpmovsdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1898) } emit_vpmovsdw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovsdw_xmm_xmm(dst, src)) } emit_vpmovsdw_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovsdw_m64_xmm(dst, src)) } emit_vpmovsdw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovsdw_xmm_ymm(dst, src)) } emit_vpmovsdw_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovsdw_m128_ymm(dst, src)) } emit_vpmovsdw_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovsdw_ymm_zmm(dst, src)) } emit_vpmovsdw_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovsdw_m256_zmm(dst, src)) } -inst_vpmovusdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1887) } -inst_vpmovusdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1887) } -inst_vpmovusdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1888) } -inst_vpmovusdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1888) } -inst_vpmovusdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1889) } -inst_vpmovusdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1889) } +inst_vpmovusdw_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1899) } +inst_vpmovusdw_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1899) } +inst_vpmovusdw_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1900) } +inst_vpmovusdw_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1900) } +inst_vpmovusdw_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1901) } +inst_vpmovusdw_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSDW, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1901) } emit_vpmovusdw_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovusdw_xmm_xmm(dst, src)) } emit_vpmovusdw_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovusdw_m64_xmm(dst, src)) } emit_vpmovusdw_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovusdw_xmm_ymm(dst, src)) } emit_vpmovusdw_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovusdw_m128_ymm(dst, src)) } emit_vpmovusdw_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovusdw_ymm_zmm(dst, src)) } emit_vpmovusdw_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovusdw_m256_zmm(dst, src)) } -inst_vpmovwb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1890) } -inst_vpmovwb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1890) } -inst_vpmovwb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1891) } -inst_vpmovwb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1891) } -inst_vpmovwb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1892) } -inst_vpmovwb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1892) } +inst_vpmovwb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1902) } +inst_vpmovwb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1902) } +inst_vpmovwb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1903) } +inst_vpmovwb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1903) } +inst_vpmovwb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1904) } +inst_vpmovwb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1904) } emit_vpmovwb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovwb_xmm_xmm(dst, src)) } emit_vpmovwb_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovwb_m64_xmm(dst, src)) } emit_vpmovwb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovwb_xmm_ymm(dst, src)) } emit_vpmovwb_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovwb_m128_ymm(dst, src)) } emit_vpmovwb_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovwb_ymm_zmm(dst, src)) } emit_vpmovwb_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovwb_m256_zmm(dst, src)) } -inst_vpmovswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1893) } -inst_vpmovswb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1893) } -inst_vpmovswb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1894) } -inst_vpmovswb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1894) } -inst_vpmovswb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1895) } -inst_vpmovswb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1895) } +inst_vpmovswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1905) } +inst_vpmovswb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1905) } +inst_vpmovswb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1906) } +inst_vpmovswb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1906) } +inst_vpmovswb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1907) } +inst_vpmovswb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVSWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1907) } emit_vpmovswb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovswb_xmm_xmm(dst, src)) } emit_vpmovswb_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovswb_m64_xmm(dst, src)) } emit_vpmovswb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovswb_xmm_ymm(dst, src)) } emit_vpmovswb_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovswb_m128_ymm(dst, src)) } emit_vpmovswb_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovswb_ymm_zmm(dst, src)) } emit_vpmovswb_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovswb_m256_zmm(dst, src)) } -inst_vpmovuswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1896) } -inst_vpmovuswb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1896) } -inst_vpmovuswb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1897) } -inst_vpmovuswb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1897) } -inst_vpmovuswb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1898) } -inst_vpmovuswb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1898) } +inst_vpmovuswb_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1908) } +inst_vpmovuswb_m64_xmm :: #force_inline proc "contextless" (dst: Mem64, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 8), op_xmm(src), {}, {}} }, 1908) } +inst_vpmovuswb_xmm_ymm :: #force_inline proc "contextless" (dst: XMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_xmm(dst), op_ymm(src), {}, {}} }, 1909) } +inst_vpmovuswb_m128_ymm :: #force_inline proc "contextless" (dst: Mem128, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 16), op_ymm(src), {}, {}} }, 1909) } +inst_vpmovuswb_ymm_zmm :: #force_inline proc "contextless" (dst: YMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_ymm(dst), op_zmm(src), {}, {}} }, 1910) } +inst_vpmovuswb_m256_zmm :: #force_inline proc "contextless" (dst: Mem256, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMOVUSWB, operand_count = 2, ops = {op_mem(dst.mem, 32), op_zmm(src), {}, {}} }, 1910) } emit_vpmovuswb_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vpmovuswb_xmm_xmm(dst, src)) } emit_vpmovuswb_m64_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: XMM) { append(instructions, inst_vpmovuswb_m64_xmm(dst, src)) } emit_vpmovuswb_xmm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: YMM) { append(instructions, inst_vpmovuswb_xmm_ymm(dst, src)) } emit_vpmovuswb_m128_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128, src: YMM) { append(instructions, inst_vpmovuswb_m128_ymm(dst, src)) } emit_vpmovuswb_ymm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: ZMM) { append(instructions, inst_vpmovuswb_ymm_zmm(dst, src)) } emit_vpmovuswb_m256_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem256, src: ZMM) { append(instructions, inst_vpmovuswb_m256_zmm(dst, src)) } -inst_vprold_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1899) } -inst_vprold_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1899) } -inst_vprold_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1900) } -inst_vprold_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1900) } -inst_vprold_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1901) } -inst_vprold_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1901) } +inst_vprold_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1911) } +inst_vprold_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1911) } +inst_vprold_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1912) } +inst_vprold_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1912) } +inst_vprold_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1913) } +inst_vprold_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1913) } emit_vprold_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vprold_xmm_xmm_imm8(dst, src, imm)) } emit_vprold_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vprold_xmm_m128_imm8(dst, src, imm)) } emit_vprold_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vprold_ymm_ymm_imm8(dst, src, imm)) } emit_vprold_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vprold_ymm_m256_imm8(dst, src, imm)) } emit_vprold_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vprold_zmm_zmm_imm8(dst, src, imm)) } emit_vprold_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vprold_zmm_m512_imm8(dst, src, imm)) } -inst_vprolq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1902) } -inst_vprolq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1902) } -inst_vprolq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1903) } -inst_vprolq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1903) } -inst_vprolq_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1904) } -inst_vprolq_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1904) } +inst_vprolq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1914) } +inst_vprolq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1914) } +inst_vprolq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1915) } +inst_vprolq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1915) } +inst_vprolq_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1916) } +inst_vprolq_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLQ, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1916) } emit_vprolq_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vprolq_xmm_xmm_imm8(dst, src, imm)) } emit_vprolq_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vprolq_xmm_m128_imm8(dst, src, imm)) } emit_vprolq_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vprolq_ymm_ymm_imm8(dst, src, imm)) } emit_vprolq_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vprolq_ymm_m256_imm8(dst, src, imm)) } emit_vprolq_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vprolq_zmm_zmm_imm8(dst, src, imm)) } emit_vprolq_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vprolq_zmm_m512_imm8(dst, src, imm)) } -inst_vprolvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1905) } -inst_vprolvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1905) } -inst_vprolvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1906) } -inst_vprolvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1906) } -inst_vprolvd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1907) } -inst_vprolvd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1907) } +inst_vprolvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1917) } +inst_vprolvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1917) } +inst_vprolvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1918) } +inst_vprolvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1918) } +inst_vprolvd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1919) } +inst_vprolvd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1919) } emit_vprolvd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vprolvd_xmm_xmm_xmm(dst, src, src2)) } emit_vprolvd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vprolvd_xmm_xmm_m128(dst, src, src2)) } emit_vprolvd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vprolvd_ymm_ymm_ymm(dst, src, src2)) } emit_vprolvd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vprolvd_ymm_ymm_m256(dst, src, src2)) } emit_vprolvd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vprolvd_zmm_zmm_zmm(dst, src, src2)) } emit_vprolvd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vprolvd_zmm_zmm_m512(dst, src, src2)) } -inst_vprolvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1908) } -inst_vprolvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1908) } -inst_vprolvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1909) } -inst_vprolvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1909) } -inst_vprolvq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1910) } -inst_vprolvq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1910) } +inst_vprolvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1920) } +inst_vprolvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1920) } +inst_vprolvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1921) } +inst_vprolvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1921) } +inst_vprolvq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1922) } +inst_vprolvq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPROLVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1922) } emit_vprolvq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vprolvq_xmm_xmm_xmm(dst, src, src2)) } emit_vprolvq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vprolvq_xmm_xmm_m128(dst, src, src2)) } emit_vprolvq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vprolvq_ymm_ymm_ymm(dst, src, src2)) } emit_vprolvq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vprolvq_ymm_ymm_m256(dst, src, src2)) } emit_vprolvq_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vprolvq_zmm_zmm_zmm(dst, src, src2)) } emit_vprolvq_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vprolvq_zmm_zmm_m512(dst, src, src2)) } -inst_vprord_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1911) } -inst_vprord_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1911) } -inst_vprord_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1912) } -inst_vprord_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1912) } -inst_vprord_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1913) } -inst_vprord_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1913) } +inst_vprord_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1923) } +inst_vprord_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1923) } +inst_vprord_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1924) } +inst_vprord_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1924) } +inst_vprord_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1925) } +inst_vprord_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1925) } emit_vprord_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vprord_xmm_xmm_imm8(dst, src, imm)) } emit_vprord_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vprord_xmm_m128_imm8(dst, src, imm)) } emit_vprord_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vprord_ymm_ymm_imm8(dst, src, imm)) } emit_vprord_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vprord_ymm_m256_imm8(dst, src, imm)) } emit_vprord_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vprord_zmm_zmm_imm8(dst, src, imm)) } emit_vprord_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vprord_zmm_m512_imm8(dst, src, imm)) } -inst_vprorq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1914) } -inst_vprorq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1914) } -inst_vprorq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1915) } -inst_vprorq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1915) } -inst_vprorq_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1916) } -inst_vprorq_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1916) } +inst_vprorq_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1926) } +inst_vprorq_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1926) } +inst_vprorq_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1927) } +inst_vprorq_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1927) } +inst_vprorq_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1928) } +inst_vprorq_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORQ, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1928) } emit_vprorq_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vprorq_xmm_xmm_imm8(dst, src, imm)) } emit_vprorq_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vprorq_xmm_m128_imm8(dst, src, imm)) } emit_vprorq_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vprorq_ymm_ymm_imm8(dst, src, imm)) } emit_vprorq_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vprorq_ymm_m256_imm8(dst, src, imm)) } emit_vprorq_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vprorq_zmm_zmm_imm8(dst, src, imm)) } emit_vprorq_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vprorq_zmm_m512_imm8(dst, src, imm)) } -inst_vprorvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1917) } -inst_vprorvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1917) } -inst_vprorvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1918) } -inst_vprorvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1918) } -inst_vprorvd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1919) } -inst_vprorvd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1919) } +inst_vprorvd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1929) } +inst_vprorvd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1929) } +inst_vprorvd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1930) } +inst_vprorvd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1930) } +inst_vprorvd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1931) } +inst_vprorvd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1931) } emit_vprorvd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vprorvd_xmm_xmm_xmm(dst, src, src2)) } emit_vprorvd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vprorvd_xmm_xmm_m128(dst, src, src2)) } emit_vprorvd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vprorvd_ymm_ymm_ymm(dst, src, src2)) } emit_vprorvd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vprorvd_ymm_ymm_m256(dst, src, src2)) } emit_vprorvd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vprorvd_zmm_zmm_zmm(dst, src, src2)) } emit_vprorvd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vprorvd_zmm_zmm_m512(dst, src, src2)) } -inst_vprorvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1920) } -inst_vprorvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1920) } -inst_vprorvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1921) } -inst_vprorvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1921) } -inst_vprorvq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1922) } -inst_vprorvq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1922) } +inst_vprorvq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1932) } +inst_vprorvq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1932) } +inst_vprorvq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1933) } +inst_vprorvq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1933) } +inst_vprorvq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1934) } +inst_vprorvq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPRORVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1934) } emit_vprorvq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vprorvq_xmm_xmm_xmm(dst, src, src2)) } emit_vprorvq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vprorvq_xmm_xmm_m128(dst, src, src2)) } emit_vprorvq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vprorvq_ymm_ymm_ymm(dst, src, src2)) } emit_vprorvq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vprorvq_ymm_ymm_m256(dst, src, src2)) } emit_vprorvq_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vprorvq_zmm_zmm_zmm(dst, src, src2)) } emit_vprorvq_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vprorvq_zmm_zmm_m512(dst, src, src2)) } -inst_vpscatterdd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1923) } -inst_vpscatterdd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1924) } -inst_vpscatterdd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1925) } +inst_vpscatterdd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1935) } +inst_vpscatterdd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1936) } +inst_vpscatterdd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1937) } emit_vpscatterdd_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vpscatterdd_m_xmm(dst, src)) } emit_vpscatterdd_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vpscatterdd_m_ymm(dst, src)) } emit_vpscatterdd_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vpscatterdd_m_zmm(dst, src)) } -inst_vpscatterdq_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1926) } -inst_vpscatterdq_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1927) } -inst_vpscatterdq_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1928) } +inst_vpscatterdq_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1938) } +inst_vpscatterdq_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1939) } +inst_vpscatterdq_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERDQ, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1940) } emit_vpscatterdq_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vpscatterdq_m_xmm(dst, src)) } emit_vpscatterdq_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vpscatterdq_m_ymm(dst, src)) } emit_vpscatterdq_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vpscatterdq_m_zmm(dst, src)) } -inst_vpscatterqd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1929) } -inst_vpscatterqd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1931) } +inst_vpscatterqd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1941) } +inst_vpscatterqd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1943) } emit_vpscatterqd_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vpscatterqd_m_xmm(dst, src)) } emit_vpscatterqd_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vpscatterqd_m_ymm(dst, src)) } -inst_vpscatterqq_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1932) } -inst_vpscatterqq_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1933) } -inst_vpscatterqq_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1934) } +inst_vpscatterqq_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1944) } +inst_vpscatterqq_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1945) } +inst_vpscatterqq_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSCATTERQQ, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1946) } emit_vpscatterqq_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vpscatterqq_m_xmm(dst, src)) } emit_vpscatterqq_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vpscatterqq_m_ymm(dst, src)) } emit_vpscatterqq_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vpscatterqq_m_zmm(dst, src)) } -inst_vscatterdps_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1935) } -inst_vscatterdps_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1936) } -inst_vscatterdps_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1937) } +inst_vscatterdps_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1947) } +inst_vscatterdps_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1948) } +inst_vscatterdps_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPS, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1949) } emit_vscatterdps_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vscatterdps_m_xmm(dst, src)) } emit_vscatterdps_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vscatterdps_m_ymm(dst, src)) } emit_vscatterdps_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vscatterdps_m_zmm(dst, src)) } -inst_vscatterdpd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1938) } -inst_vscatterdpd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1939) } -inst_vscatterdpd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1940) } +inst_vscatterdpd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1950) } +inst_vscatterdpd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1951) } +inst_vscatterdpd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERDPD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1952) } emit_vscatterdpd_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vscatterdpd_m_xmm(dst, src)) } emit_vscatterdpd_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vscatterdpd_m_ymm(dst, src)) } emit_vscatterdpd_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vscatterdpd_m_zmm(dst, src)) } -inst_vscatterqps_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPS, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1941) } -inst_vscatterqps_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPS, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1943) } +inst_vscatterqps_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPS, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1953) } +inst_vscatterqps_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPS, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1955) } emit_vscatterqps_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vscatterqps_m_xmm(dst, src)) } emit_vscatterqps_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vscatterqps_m_ymm(dst, src)) } -inst_vscatterqpd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1944) } -inst_vscatterqpd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1945) } -inst_vscatterqpd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1946) } +inst_vscatterqpd_m_xmm :: #force_inline proc "contextless" (dst: Memory, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_xmm(src), {}, {}} }, 1956) } +inst_vscatterqpd_m_ymm :: #force_inline proc "contextless" (dst: Memory, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_ymm(src), {}, {}} }, 1957) } +inst_vscatterqpd_m_zmm :: #force_inline proc "contextless" (dst: Memory, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCATTERQPD, operand_count = 2, ops = {op_mem(dst, 0), op_zmm(src), {}, {}} }, 1958) } emit_vscatterqpd_m_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: XMM) { append(instructions, inst_vscatterqpd_m_xmm(dst, src)) } emit_vscatterqpd_m_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: YMM) { append(instructions, inst_vscatterqpd_m_ymm(dst, src)) } emit_vscatterqpd_m_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory, src: ZMM) { append(instructions, inst_vscatterqpd_m_zmm(dst, src)) } -inst_vpsravq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1947) } -inst_vpsravq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1947) } -inst_vpsravq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1948) } -inst_vpsravq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1948) } -inst_vpsravq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1949) } -inst_vpsravq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1949) } +inst_vpsravq_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1959) } +inst_vpsravq_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1959) } +inst_vpsravq_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1960) } +inst_vpsravq_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1960) } +inst_vpsravq_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1961) } +inst_vpsravq_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVQ, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1961) } emit_vpsravq_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsravq_xmm_xmm_xmm(dst, src, src2)) } emit_vpsravq_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsravq_xmm_xmm_m128(dst, src, src2)) } emit_vpsravq_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsravq_ymm_ymm_ymm(dst, src, src2)) } emit_vpsravq_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsravq_ymm_ymm_m256(dst, src, src2)) } emit_vpsravq_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpsravq_zmm_zmm_zmm(dst, src, src2)) } emit_vpsravq_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpsravq_zmm_zmm_m512(dst, src, src2)) } -inst_vpsravw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1950) } -inst_vpsravw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1950) } -inst_vpsravw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1951) } -inst_vpsravw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1951) } -inst_vpsravw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1952) } -inst_vpsravw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1952) } +inst_vpsravw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1962) } +inst_vpsravw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1962) } +inst_vpsravw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1963) } +inst_vpsravw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1963) } +inst_vpsravw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1964) } +inst_vpsravw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRAVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1964) } emit_vpsravw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsravw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsravw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsravw_xmm_xmm_m128(dst, src, src2)) } emit_vpsravw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsravw_ymm_ymm_ymm(dst, src, src2)) } emit_vpsravw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsravw_ymm_ymm_m256(dst, src, src2)) } emit_vpsravw_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpsravw_zmm_zmm_zmm(dst, src, src2)) } emit_vpsravw_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpsravw_zmm_zmm_m512(dst, src, src2)) } -inst_vpsllvw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1953) } -inst_vpsllvw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1953) } -inst_vpsllvw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1954) } -inst_vpsllvw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1954) } -inst_vpsllvw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1955) } -inst_vpsllvw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1955) } +inst_vpsllvw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1965) } +inst_vpsllvw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1965) } +inst_vpsllvw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1966) } +inst_vpsllvw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1966) } +inst_vpsllvw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1967) } +inst_vpsllvw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSLLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1967) } emit_vpsllvw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsllvw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsllvw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsllvw_xmm_xmm_m128(dst, src, src2)) } emit_vpsllvw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsllvw_ymm_ymm_ymm(dst, src, src2)) } emit_vpsllvw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsllvw_ymm_ymm_m256(dst, src, src2)) } emit_vpsllvw_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpsllvw_zmm_zmm_zmm(dst, src, src2)) } emit_vpsllvw_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpsllvw_zmm_zmm_m512(dst, src, src2)) } -inst_vpsrlvw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1956) } -inst_vpsrlvw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1956) } -inst_vpsrlvw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1957) } -inst_vpsrlvw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1957) } -inst_vpsrlvw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1958) } -inst_vpsrlvw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1958) } +inst_vpsrlvw_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1968) } +inst_vpsrlvw_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1968) } +inst_vpsrlvw_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 1969) } +inst_vpsrlvw_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 1969) } +inst_vpsrlvw_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 1970) } +inst_vpsrlvw_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPSRLVW, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 1970) } emit_vpsrlvw_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpsrlvw_xmm_xmm_xmm(dst, src, src2)) } emit_vpsrlvw_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpsrlvw_xmm_xmm_m128(dst, src, src2)) } emit_vpsrlvw_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpsrlvw_ymm_ymm_ymm(dst, src, src2)) } emit_vpsrlvw_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpsrlvw_ymm_ymm_m256(dst, src, src2)) } emit_vpsrlvw_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpsrlvw_zmm_zmm_zmm(dst, src, src2)) } emit_vpsrlvw_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpsrlvw_zmm_zmm_m512(dst, src, src2)) } -inst_vrangeps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1959) } -inst_vrangeps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1959) } -inst_vrangeps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1960) } -inst_vrangeps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1960) } -inst_vrangeps_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1961) } -inst_vrangeps_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1961) } +inst_vrangeps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1971) } +inst_vrangeps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1971) } +inst_vrangeps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1972) } +inst_vrangeps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1972) } +inst_vrangeps_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1973) } +inst_vrangeps_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1973) } emit_vrangeps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrangeps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrangeps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vrangeps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vrangeps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vrangeps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vrangeps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vrangeps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vrangeps_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vrangeps_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vrangeps_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vrangeps_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vrangepd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1962) } -inst_vrangepd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1962) } -inst_vrangepd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1963) } -inst_vrangepd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1963) } -inst_vrangepd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1964) } -inst_vrangepd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1964) } +inst_vrangepd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1974) } +inst_vrangepd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 1974) } +inst_vrangepd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 1975) } +inst_vrangepd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 1975) } +inst_vrangepd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 1976) } +inst_vrangepd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGEPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 1976) } emit_vrangepd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrangepd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrangepd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vrangepd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vrangepd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vrangepd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vrangepd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vrangepd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vrangepd_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vrangepd_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vrangepd_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vrangepd_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vrangess_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1965) } -inst_vrangess_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1965) } +inst_vrangess_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1977) } +inst_vrangess_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1977) } emit_vrangess_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrangess_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrangess_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vrangess_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vrangesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1966) } -inst_vrangesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1966) } +inst_vrangesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1978) } +inst_vrangesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRANGESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1978) } emit_vrangesd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrangesd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrangesd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vrangesd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vreduceps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1967) } -inst_vreduceps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1967) } -inst_vreduceps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1968) } -inst_vreduceps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1968) } -inst_vreduceps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1969) } -inst_vreduceps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1969) } +inst_vreduceps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1979) } +inst_vreduceps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1979) } +inst_vreduceps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1980) } +inst_vreduceps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1980) } +inst_vreduceps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1981) } +inst_vreduceps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1981) } emit_vreduceps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vreduceps_xmm_xmm_imm8(dst, src, imm)) } emit_vreduceps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vreduceps_xmm_m128_imm8(dst, src, imm)) } emit_vreduceps_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vreduceps_ymm_ymm_imm8(dst, src, imm)) } emit_vreduceps_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vreduceps_ymm_m256_imm8(dst, src, imm)) } emit_vreduceps_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vreduceps_zmm_zmm_imm8(dst, src, imm)) } emit_vreduceps_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vreduceps_zmm_m512_imm8(dst, src, imm)) } -inst_vreducepd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1970) } -inst_vreducepd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1970) } -inst_vreducepd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1971) } -inst_vreducepd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1971) } -inst_vreducepd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1972) } -inst_vreducepd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1972) } +inst_vreducepd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1982) } +inst_vreducepd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1982) } +inst_vreducepd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1983) } +inst_vreducepd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1983) } +inst_vreducepd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1984) } +inst_vreducepd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCEPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1984) } emit_vreducepd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vreducepd_xmm_xmm_imm8(dst, src, imm)) } emit_vreducepd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vreducepd_xmm_m128_imm8(dst, src, imm)) } emit_vreducepd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vreducepd_ymm_ymm_imm8(dst, src, imm)) } emit_vreducepd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vreducepd_ymm_m256_imm8(dst, src, imm)) } emit_vreducepd_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vreducepd_zmm_zmm_imm8(dst, src, imm)) } emit_vreducepd_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vreducepd_zmm_m512_imm8(dst, src, imm)) } -inst_vreducess_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1973) } -inst_vreducess_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1973) } +inst_vreducess_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1985) } +inst_vreducess_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1985) } emit_vreducess_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vreducess_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vreducess_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vreducess_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vreducesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1974) } -inst_vreducesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1974) } +inst_vreducesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1986) } +inst_vreducesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VREDUCESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1986) } emit_vreducesd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vreducesd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vreducesd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vreducesd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vrndscaleps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1975) } -inst_vrndscaleps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1975) } -inst_vrndscaleps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1976) } -inst_vrndscaleps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1976) } -inst_vrndscaleps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1977) } -inst_vrndscaleps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1977) } +inst_vrndscaleps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1987) } +inst_vrndscaleps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1987) } +inst_vrndscaleps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1988) } +inst_vrndscaleps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1988) } +inst_vrndscaleps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1989) } +inst_vrndscaleps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1989) } emit_vrndscaleps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vrndscaleps_xmm_xmm_imm8(dst, src, imm)) } emit_vrndscaleps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vrndscaleps_xmm_m128_imm8(dst, src, imm)) } emit_vrndscaleps_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vrndscaleps_ymm_ymm_imm8(dst, src, imm)) } emit_vrndscaleps_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vrndscaleps_ymm_m256_imm8(dst, src, imm)) } emit_vrndscaleps_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vrndscaleps_zmm_zmm_imm8(dst, src, imm)) } emit_vrndscaleps_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vrndscaleps_zmm_m512_imm8(dst, src, imm)) } -inst_vrndscalepd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1978) } -inst_vrndscalepd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1978) } -inst_vrndscalepd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1979) } -inst_vrndscalepd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1979) } -inst_vrndscalepd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1980) } -inst_vrndscalepd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1980) } +inst_vrndscalepd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 1990) } +inst_vrndscalepd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 1990) } +inst_vrndscalepd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 1991) } +inst_vrndscalepd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 1991) } +inst_vrndscalepd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 1992) } +inst_vrndscalepd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALEPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 1992) } emit_vrndscalepd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vrndscalepd_xmm_xmm_imm8(dst, src, imm)) } emit_vrndscalepd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vrndscalepd_xmm_m128_imm8(dst, src, imm)) } emit_vrndscalepd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vrndscalepd_ymm_ymm_imm8(dst, src, imm)) } emit_vrndscalepd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vrndscalepd_ymm_m256_imm8(dst, src, imm)) } emit_vrndscalepd_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vrndscalepd_zmm_zmm_imm8(dst, src, imm)) } emit_vrndscalepd_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vrndscalepd_zmm_m512_imm8(dst, src, imm)) } -inst_vrndscaless_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1981) } -inst_vrndscaless_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1981) } +inst_vrndscaless_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1993) } +inst_vrndscaless_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 1993) } emit_vrndscaless_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrndscaless_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrndscaless_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vrndscaless_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vrndscalesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1982) } -inst_vrndscalesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1982) } +inst_vrndscalesd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 1994) } +inst_vrndscalesd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VRNDSCALESD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 1994) } emit_vrndscalesd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vrndscalesd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vrndscalesd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vrndscalesd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vrsqrt14ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1983) } -inst_vrsqrt14ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1983) } -inst_vrsqrt14ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1984) } -inst_vrsqrt14ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1984) } -inst_vrsqrt14ps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1985) } -inst_vrsqrt14ps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1985) } +inst_vrsqrt14ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1995) } +inst_vrsqrt14ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1995) } +inst_vrsqrt14ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1996) } +inst_vrsqrt14ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1996) } +inst_vrsqrt14ps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1997) } +inst_vrsqrt14ps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1997) } emit_vrsqrt14ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrsqrt14ps_xmm_xmm(dst, src)) } emit_vrsqrt14ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrsqrt14ps_xmm_m128(dst, src)) } emit_vrsqrt14ps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrsqrt14ps_ymm_ymm(dst, src)) } emit_vrsqrt14ps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrsqrt14ps_ymm_m256(dst, src)) } emit_vrsqrt14ps_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vrsqrt14ps_zmm_zmm(dst, src)) } emit_vrsqrt14ps_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vrsqrt14ps_zmm_m512(dst, src)) } -inst_vrsqrt14pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1986) } -inst_vrsqrt14pd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1986) } -inst_vrsqrt14pd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1987) } -inst_vrsqrt14pd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1987) } -inst_vrsqrt14pd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1988) } -inst_vrsqrt14pd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1988) } +inst_vrsqrt14pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1998) } +inst_vrsqrt14pd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1998) } +inst_vrsqrt14pd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1999) } +inst_vrsqrt14pd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1999) } +inst_vrsqrt14pd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2000) } +inst_vrsqrt14pd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14PD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2000) } emit_vrsqrt14pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrsqrt14pd_xmm_xmm(dst, src)) } emit_vrsqrt14pd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrsqrt14pd_xmm_m128(dst, src)) } emit_vrsqrt14pd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrsqrt14pd_ymm_ymm(dst, src)) } emit_vrsqrt14pd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrsqrt14pd_ymm_m256(dst, src)) } emit_vrsqrt14pd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vrsqrt14pd_zmm_zmm(dst, src)) } emit_vrsqrt14pd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vrsqrt14pd_zmm_m512(dst, src)) } -inst_vrsqrt14ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1989) } -inst_vrsqrt14ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1989) } +inst_vrsqrt14ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2001) } +inst_vrsqrt14ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2001) } emit_vrsqrt14ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrsqrt14ss_xmm_xmm_xmm(dst, src, src2)) } emit_vrsqrt14ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vrsqrt14ss_xmm_xmm_m32(dst, src, src2)) } -inst_vrsqrt14sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1990) } -inst_vrsqrt14sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1990) } +inst_vrsqrt14sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2002) } +inst_vrsqrt14sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VRSQRT14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2002) } emit_vrsqrt14sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrsqrt14sd_xmm_xmm_xmm(dst, src, src2)) } emit_vrsqrt14sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vrsqrt14sd_xmm_xmm_m64(dst, src, src2)) } -inst_vrcp14ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1991) } -inst_vrcp14ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1991) } -inst_vrcp14ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1992) } -inst_vrcp14ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1992) } -inst_vrcp14ps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1993) } -inst_vrcp14ps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1993) } +inst_vrcp14ps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2003) } +inst_vrcp14ps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2003) } +inst_vrcp14ps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2004) } +inst_vrcp14ps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2004) } +inst_vrcp14ps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2005) } +inst_vrcp14ps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2005) } emit_vrcp14ps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrcp14ps_xmm_xmm(dst, src)) } emit_vrcp14ps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrcp14ps_xmm_m128(dst, src)) } emit_vrcp14ps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrcp14ps_ymm_ymm(dst, src)) } emit_vrcp14ps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrcp14ps_ymm_m256(dst, src)) } emit_vrcp14ps_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vrcp14ps_zmm_zmm(dst, src)) } emit_vrcp14ps_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vrcp14ps_zmm_m512(dst, src)) } -inst_vrcp14pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 1994) } -inst_vrcp14pd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 1994) } -inst_vrcp14pd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 1995) } -inst_vrcp14pd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 1995) } -inst_vrcp14pd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 1996) } -inst_vrcp14pd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 1996) } +inst_vrcp14pd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2006) } +inst_vrcp14pd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2006) } +inst_vrcp14pd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2007) } +inst_vrcp14pd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2007) } +inst_vrcp14pd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2008) } +inst_vrcp14pd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14PD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2008) } emit_vrcp14pd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vrcp14pd_xmm_xmm(dst, src)) } emit_vrcp14pd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vrcp14pd_xmm_m128(dst, src)) } emit_vrcp14pd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vrcp14pd_ymm_ymm(dst, src)) } emit_vrcp14pd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vrcp14pd_ymm_m256(dst, src)) } emit_vrcp14pd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vrcp14pd_zmm_zmm(dst, src)) } emit_vrcp14pd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vrcp14pd_zmm_m512(dst, src)) } -inst_vrcp14ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1997) } -inst_vrcp14ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 1997) } +inst_vrcp14ss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2009) } +inst_vrcp14ss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2009) } emit_vrcp14ss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrcp14ss_xmm_xmm_xmm(dst, src, src2)) } emit_vrcp14ss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vrcp14ss_xmm_xmm_m32(dst, src, src2)) } -inst_vrcp14sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1998) } -inst_vrcp14sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 1998) } +inst_vrcp14sd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2010) } +inst_vrcp14sd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VRCP14SD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2010) } emit_vrcp14sd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vrcp14sd_xmm_xmm_xmm(dst, src, src2)) } emit_vrcp14sd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vrcp14sd_xmm_xmm_m64(dst, src, src2)) } -inst_vscalefps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 1999) } -inst_vscalefps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 1999) } -inst_vscalefps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2000) } -inst_vscalefps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2000) } -inst_vscalefps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2001) } -inst_vscalefps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2001) } +inst_vscalefps_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2011) } +inst_vscalefps_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2011) } +inst_vscalefps_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2012) } +inst_vscalefps_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2012) } +inst_vscalefps_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2013) } +inst_vscalefps_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2013) } emit_vscalefps_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vscalefps_xmm_xmm_xmm(dst, src, src2)) } emit_vscalefps_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vscalefps_xmm_xmm_m128(dst, src, src2)) } emit_vscalefps_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vscalefps_ymm_ymm_ymm(dst, src, src2)) } emit_vscalefps_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vscalefps_ymm_ymm_m256(dst, src, src2)) } emit_vscalefps_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vscalefps_zmm_zmm_zmm(dst, src, src2)) } emit_vscalefps_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vscalefps_zmm_zmm_m512(dst, src, src2)) } -inst_vscalefpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2002) } -inst_vscalefpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2002) } -inst_vscalefpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2003) } -inst_vscalefpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2003) } -inst_vscalefpd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2004) } -inst_vscalefpd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2004) } +inst_vscalefpd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2014) } +inst_vscalefpd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2014) } +inst_vscalefpd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2015) } +inst_vscalefpd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2015) } +inst_vscalefpd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2016) } +inst_vscalefpd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2016) } emit_vscalefpd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vscalefpd_xmm_xmm_xmm(dst, src, src2)) } emit_vscalefpd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vscalefpd_xmm_xmm_m128(dst, src, src2)) } emit_vscalefpd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vscalefpd_ymm_ymm_ymm(dst, src, src2)) } emit_vscalefpd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vscalefpd_ymm_ymm_m256(dst, src, src2)) } emit_vscalefpd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vscalefpd_zmm_zmm_zmm(dst, src, src2)) } emit_vscalefpd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vscalefpd_zmm_zmm_m512(dst, src, src2)) } -inst_vscalefss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2005) } -inst_vscalefss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2005) } +inst_vscalefss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2017) } +inst_vscalefss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2017) } emit_vscalefss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vscalefss_xmm_xmm_xmm(dst, src, src2)) } emit_vscalefss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vscalefss_xmm_xmm_m32(dst, src, src2)) } -inst_vscalefsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2006) } -inst_vscalefsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2006) } +inst_vscalefsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2018) } +inst_vscalefsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VSCALEFSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2018) } emit_vscalefsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vscalefsd_xmm_xmm_xmm(dst, src, src2)) } emit_vscalefsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vscalefsd_xmm_xmm_m64(dst, src, src2)) } -inst_vgetexpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2007) } -inst_vgetexpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2007) } -inst_vgetexpps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2008) } -inst_vgetexpps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2008) } -inst_vgetexpps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2009) } -inst_vgetexpps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2009) } +inst_vgetexpps_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2019) } +inst_vgetexpps_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2019) } +inst_vgetexpps_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2020) } +inst_vgetexpps_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2020) } +inst_vgetexpps_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2021) } +inst_vgetexpps_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPS, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2021) } emit_vgetexpps_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vgetexpps_xmm_xmm(dst, src)) } emit_vgetexpps_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vgetexpps_xmm_m128(dst, src)) } emit_vgetexpps_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vgetexpps_ymm_ymm(dst, src)) } emit_vgetexpps_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vgetexpps_ymm_m256(dst, src)) } emit_vgetexpps_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vgetexpps_zmm_zmm(dst, src)) } emit_vgetexpps_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vgetexpps_zmm_m512(dst, src)) } -inst_vgetexppd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2010) } -inst_vgetexppd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2010) } -inst_vgetexppd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2011) } -inst_vgetexppd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2011) } -inst_vgetexppd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2012) } -inst_vgetexppd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2012) } +inst_vgetexppd_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_xmm(dst), op_xmm(src), {}, {}} }, 2022) } +inst_vgetexppd_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_xmm(dst), op_mem(src.mem, 16), {}, {}} }, 2022) } +inst_vgetexppd_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_ymm(dst), op_ymm(src), {}, {}} }, 2023) } +inst_vgetexppd_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_ymm(dst), op_mem(src.mem, 32), {}, {}} }, 2023) } +inst_vgetexppd_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_zmm(dst), op_zmm(src), {}, {}} }, 2024) } +inst_vgetexppd_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPPD, operand_count = 2, ops = {op_zmm(dst), op_mem(src.mem, 64), {}, {}} }, 2024) } emit_vgetexppd_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM) { append(instructions, inst_vgetexppd_xmm_xmm(dst, src)) } emit_vgetexppd_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128) { append(instructions, inst_vgetexppd_xmm_m128(dst, src)) } emit_vgetexppd_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM) { append(instructions, inst_vgetexppd_ymm_ymm(dst, src)) } emit_vgetexppd_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256) { append(instructions, inst_vgetexppd_ymm_m256(dst, src)) } emit_vgetexppd_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM) { append(instructions, inst_vgetexppd_zmm_zmm(dst, src)) } emit_vgetexppd_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512) { append(instructions, inst_vgetexppd_zmm_m512(dst, src)) } -inst_vgetexpss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2013) } -inst_vgetexpss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2013) } +inst_vgetexpss_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2025) } +inst_vgetexpss_xmm_xmm_m32 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), {}} }, 2025) } emit_vgetexpss_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vgetexpss_xmm_xmm_xmm(dst, src, src2)) } emit_vgetexpss_xmm_xmm_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32) { append(instructions, inst_vgetexpss_xmm_xmm_m32(dst, src, src2)) } -inst_vgetexpsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2014) } -inst_vgetexpsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2014) } +inst_vgetexpsd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2026) } +inst_vgetexpsd_xmm_xmm_m64 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETEXPSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), {}} }, 2026) } emit_vgetexpsd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vgetexpsd_xmm_xmm_xmm(dst, src, src2)) } emit_vgetexpsd_xmm_xmm_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64) { append(instructions, inst_vgetexpsd_xmm_xmm_m64(dst, src, src2)) } -inst_vgetmantps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 2015) } -inst_vgetmantps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2015) } -inst_vgetmantps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 2016) } -inst_vgetmantps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2016) } -inst_vgetmantps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 2017) } -inst_vgetmantps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2017) } +inst_vgetmantps_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 2027) } +inst_vgetmantps_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2027) } +inst_vgetmantps_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 2028) } +inst_vgetmantps_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2028) } +inst_vgetmantps_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 2029) } +inst_vgetmantps_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPS, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2029) } emit_vgetmantps_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vgetmantps_xmm_xmm_imm8(dst, src, imm)) } emit_vgetmantps_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vgetmantps_xmm_m128_imm8(dst, src, imm)) } emit_vgetmantps_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vgetmantps_ymm_ymm_imm8(dst, src, imm)) } emit_vgetmantps_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vgetmantps_ymm_m256_imm8(dst, src, imm)) } emit_vgetmantps_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vgetmantps_zmm_zmm_imm8(dst, src, imm)) } emit_vgetmantps_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vgetmantps_zmm_m512_imm8(dst, src, imm)) } -inst_vgetmantpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 2018) } -inst_vgetmantpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2018) } -inst_vgetmantpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 2019) } -inst_vgetmantpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2019) } -inst_vgetmantpd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 2020) } -inst_vgetmantpd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2020) } +inst_vgetmantpd_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_imm8(imm), {}} }, 2030) } +inst_vgetmantpd_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_xmm(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2030) } +inst_vgetmantpd_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_imm8(imm), {}} }, 2031) } +inst_vgetmantpd_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_ymm(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2031) } +inst_vgetmantpd_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_imm8(imm), {}} }, 2032) } +inst_vgetmantpd_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTPD, operand_count = 3, ops = {op_zmm(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2032) } emit_vgetmantpd_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, imm: i8) { append(instructions, inst_vgetmantpd_xmm_xmm_imm8(dst, src, imm)) } emit_vgetmantpd_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: Mem128, imm: i8) { append(instructions, inst_vgetmantpd_xmm_m128_imm8(dst, src, imm)) } emit_vgetmantpd_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, imm: i8) { append(instructions, inst_vgetmantpd_ymm_ymm_imm8(dst, src, imm)) } emit_vgetmantpd_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: Mem256, imm: i8) { append(instructions, inst_vgetmantpd_ymm_m256_imm8(dst, src, imm)) } emit_vgetmantpd_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, imm: i8) { append(instructions, inst_vgetmantpd_zmm_zmm_imm8(dst, src, imm)) } emit_vgetmantpd_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: Mem512, imm: i8) { append(instructions, inst_vgetmantpd_zmm_m512_imm8(dst, src, imm)) } -inst_vgetmantss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2021) } -inst_vgetmantss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 2021) } +inst_vgetmantss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2033) } +inst_vgetmantss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 2033) } emit_vgetmantss_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vgetmantss_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vgetmantss_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vgetmantss_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vgetmantsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2022) } -inst_vgetmantsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 2022) } +inst_vgetmantsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2034) } +inst_vgetmantsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VGETMANTSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 2034) } emit_vgetmantsd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vgetmantsd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vgetmantsd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vgetmantsd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vfixupimmps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2023) } -inst_vfixupimmps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2023) } -inst_vfixupimmps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2024) } -inst_vfixupimmps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2024) } -inst_vfixupimmps_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2025) } -inst_vfixupimmps_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2025) } +inst_vfixupimmps_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2035) } +inst_vfixupimmps_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2035) } +inst_vfixupimmps_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2036) } +inst_vfixupimmps_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2036) } +inst_vfixupimmps_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2037) } +inst_vfixupimmps_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPS, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2037) } emit_vfixupimmps_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vfixupimmps_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vfixupimmps_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vfixupimmps_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vfixupimmps_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vfixupimmps_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vfixupimmps_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vfixupimmps_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vfixupimmps_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vfixupimmps_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vfixupimmps_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vfixupimmps_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vfixupimmpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2026) } -inst_vfixupimmpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2026) } -inst_vfixupimmpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2027) } -inst_vfixupimmpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2027) } -inst_vfixupimmpd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2028) } -inst_vfixupimmpd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2028) } +inst_vfixupimmpd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2038) } +inst_vfixupimmpd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2038) } +inst_vfixupimmpd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2039) } +inst_vfixupimmpd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2039) } +inst_vfixupimmpd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2040) } +inst_vfixupimmpd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMPD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2040) } emit_vfixupimmpd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vfixupimmpd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vfixupimmpd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vfixupimmpd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vfixupimmpd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vfixupimmpd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vfixupimmpd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vfixupimmpd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vfixupimmpd_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vfixupimmpd_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vfixupimmpd_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vfixupimmpd_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vfixupimmss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2029) } -inst_vfixupimmss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 2029) } +inst_vfixupimmss_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2041) } +inst_vfixupimmss_xmm_xmm_m32_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSS, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 4), op_imm8(imm)} }, 2041) } emit_vfixupimmss_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vfixupimmss_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vfixupimmss_xmm_xmm_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem32, imm: i8) { append(instructions, inst_vfixupimmss_xmm_xmm_m32_imm8(dst, src, src2, imm)) } -inst_vfixupimmsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2030) } -inst_vfixupimmsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 2030) } +inst_vfixupimmsd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2042) } +inst_vfixupimmsd_xmm_xmm_m64_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFIXUPIMMSD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 8), op_imm8(imm)} }, 2042) } emit_vfixupimmsd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vfixupimmsd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vfixupimmsd_xmm_xmm_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem64, imm: i8) { append(instructions, inst_vfixupimmsd_xmm_xmm_m64_imm8(dst, src, src2, imm)) } -inst_vfpclassps_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2031) } -inst_vfpclassps_k_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2031) } -inst_vfpclassps_k_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_imm8(imm), {}} }, 2032) } -inst_vfpclassps_k_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2032) } -inst_vfpclassps_k_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_imm8(imm), {}} }, 2033) } -inst_vfpclassps_k_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2033) } +inst_vfpclassps_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2043) } +inst_vfpclassps_k_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2043) } +inst_vfpclassps_k_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_imm8(imm), {}} }, 2044) } +inst_vfpclassps_k_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2044) } +inst_vfpclassps_k_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_imm8(imm), {}} }, 2045) } +inst_vfpclassps_k_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2045) } emit_vfpclassps_k_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, imm: i8) { append(instructions, inst_vfpclassps_k_xmm_imm8(dst, src, imm)) } emit_vfpclassps_k_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem128, imm: i8) { append(instructions, inst_vfpclassps_k_m128_imm8(dst, src, imm)) } emit_vfpclassps_k_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, imm: i8) { append(instructions, inst_vfpclassps_k_ymm_imm8(dst, src, imm)) } emit_vfpclassps_k_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem256, imm: i8) { append(instructions, inst_vfpclassps_k_m256_imm8(dst, src, imm)) } emit_vfpclassps_k_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, imm: i8) { append(instructions, inst_vfpclassps_k_zmm_imm8(dst, src, imm)) } emit_vfpclassps_k_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem512, imm: i8) { append(instructions, inst_vfpclassps_k_m512_imm8(dst, src, imm)) } -inst_vfpclasspd_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2034) } -inst_vfpclasspd_k_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2034) } -inst_vfpclasspd_k_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_imm8(imm), {}} }, 2035) } -inst_vfpclasspd_k_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2035) } -inst_vfpclasspd_k_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_imm8(imm), {}} }, 2036) } -inst_vfpclasspd_k_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2036) } +inst_vfpclasspd_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2046) } +inst_vfpclasspd_k_m128_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 16), op_imm8(imm), {}} }, 2046) } +inst_vfpclasspd_k_ymm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_ymm(src), op_imm8(imm), {}} }, 2047) } +inst_vfpclasspd_k_m256_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 32), op_imm8(imm), {}} }, 2047) } +inst_vfpclasspd_k_zmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_zmm(src), op_imm8(imm), {}} }, 2048) } +inst_vfpclasspd_k_m512_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSPD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 64), op_imm8(imm), {}} }, 2048) } emit_vfpclasspd_k_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, imm: i8) { append(instructions, inst_vfpclasspd_k_xmm_imm8(dst, src, imm)) } emit_vfpclasspd_k_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem128, imm: i8) { append(instructions, inst_vfpclasspd_k_m128_imm8(dst, src, imm)) } emit_vfpclasspd_k_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: YMM, imm: i8) { append(instructions, inst_vfpclasspd_k_ymm_imm8(dst, src, imm)) } emit_vfpclasspd_k_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem256, imm: i8) { append(instructions, inst_vfpclasspd_k_m256_imm8(dst, src, imm)) } emit_vfpclasspd_k_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: ZMM, imm: i8) { append(instructions, inst_vfpclasspd_k_zmm_imm8(dst, src, imm)) } emit_vfpclasspd_k_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem512, imm: i8) { append(instructions, inst_vfpclasspd_k_m512_imm8(dst, src, imm)) } -inst_vfpclassss_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSS, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2037) } -inst_vfpclassss_k_m32_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 2037) } +inst_vfpclassss_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSS, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2049) } +inst_vfpclassss_k_m32_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem32, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSS, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 4), op_imm8(imm), {}} }, 2049) } emit_vfpclassss_k_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, imm: i8) { append(instructions, inst_vfpclassss_k_xmm_imm8(dst, src, imm)) } emit_vfpclassss_k_m32_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem32, imm: i8) { append(instructions, inst_vfpclassss_k_m32_imm8(dst, src, imm)) } -inst_vfpclasssd_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2038) } -inst_vfpclasssd_k_m64_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 2038) } +inst_vfpclasssd_k_xmm_imm8 :: #force_inline proc "contextless" (dst: KREG, src: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSD, operand_count = 3, ops = {op_kreg(dst), op_xmm(src), op_imm8(imm), {}} }, 2050) } +inst_vfpclasssd_k_m64_imm8 :: #force_inline proc "contextless" (dst: KREG, src: Mem64, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VFPCLASSSD, operand_count = 3, ops = {op_kreg(dst), op_mem(src.mem, 8), op_imm8(imm), {}} }, 2050) } emit_vfpclasssd_k_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: XMM, imm: i8) { append(instructions, inst_vfpclasssd_k_xmm_imm8(dst, src, imm)) } emit_vfpclasssd_k_m64_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem64, imm: i8) { append(instructions, inst_vfpclasssd_k_m64_imm8(dst, src, imm)) } -inst_valignq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2039) } -inst_valignq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2039) } -inst_valignq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2040) } -inst_valignq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2040) } -inst_valignq_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2041) } -inst_valignq_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2041) } +inst_valignq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2051) } +inst_valignq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2051) } +inst_valignq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2052) } +inst_valignq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2052) } +inst_valignq_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2053) } +inst_valignq_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGNQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2053) } emit_valignq_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_valignq_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_valignq_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_valignq_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_valignq_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_valignq_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_valignq_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_valignq_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_valignq_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_valignq_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_valignq_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_valignq_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_valignd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2042) } -inst_valignd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2042) } -inst_valignd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2043) } -inst_valignd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2043) } -inst_valignd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2044) } -inst_valignd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2044) } +inst_valignd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2054) } +inst_valignd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2054) } +inst_valignd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2055) } +inst_valignd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2055) } +inst_valignd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2056) } +inst_valignd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VALIGND, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2056) } emit_valignd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_valignd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_valignd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_valignd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_valignd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_valignd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_valignd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_valignd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_valignd_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_valignd_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_valignd_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_valignd_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vdbpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2045) } -inst_vdbpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2045) } -inst_vdbpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2046) } -inst_vdbpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2046) } -inst_vdbpsadbw_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2047) } -inst_vdbpsadbw_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2047) } +inst_vdbpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2057) } +inst_vdbpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2057) } +inst_vdbpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2058) } +inst_vdbpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2058) } +inst_vdbpsadbw_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2059) } +inst_vdbpsadbw_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VDBPSADBW, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2059) } emit_vdbpsadbw_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vdbpsadbw_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vdbpsadbw_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vdbpsadbw_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vdbpsadbw_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vdbpsadbw_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vdbpsadbw_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vdbpsadbw_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vdbpsadbw_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vdbpsadbw_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vdbpsadbw_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vdbpsadbw_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpternlogd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2048) } -inst_vpternlogd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2048) } -inst_vpternlogd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2049) } -inst_vpternlogd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2049) } -inst_vpternlogd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2050) } -inst_vpternlogd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2050) } +inst_vpternlogd_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2060) } +inst_vpternlogd_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2060) } +inst_vpternlogd_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2061) } +inst_vpternlogd_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2061) } +inst_vpternlogd_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2062) } +inst_vpternlogd_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGD, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2062) } emit_vpternlogd_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpternlogd_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpternlogd_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpternlogd_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpternlogd_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpternlogd_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpternlogd_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpternlogd_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpternlogd_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpternlogd_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpternlogd_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpternlogd_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpternlogq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2051) } -inst_vpternlogq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2051) } -inst_vpternlogq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2052) } -inst_vpternlogq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2052) } -inst_vpternlogq_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2053) } -inst_vpternlogq_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2053) } +inst_vpternlogq_xmm_xmm_xmm_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), op_imm8(imm)} }, 2063) } +inst_vpternlogq_xmm_xmm_m128_imm8 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), op_imm8(imm)} }, 2063) } +inst_vpternlogq_ymm_ymm_ymm_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), op_imm8(imm)} }, 2064) } +inst_vpternlogq_ymm_ymm_m256_imm8 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), op_imm8(imm)} }, 2064) } +inst_vpternlogq_zmm_zmm_zmm_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), op_imm8(imm)} }, 2065) } +inst_vpternlogq_zmm_zmm_m512_imm8 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .VPTERNLOGQ, operand_count = 4, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), op_imm8(imm)} }, 2065) } emit_vpternlogq_xmm_xmm_xmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM, imm: i8) { append(instructions, inst_vpternlogq_xmm_xmm_xmm_imm8(dst, src, src2, imm)) } emit_vpternlogq_xmm_xmm_m128_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128, imm: i8) { append(instructions, inst_vpternlogq_xmm_xmm_m128_imm8(dst, src, src2, imm)) } emit_vpternlogq_ymm_ymm_ymm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM, imm: i8) { append(instructions, inst_vpternlogq_ymm_ymm_ymm_imm8(dst, src, src2, imm)) } emit_vpternlogq_ymm_ymm_m256_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256, imm: i8) { append(instructions, inst_vpternlogq_ymm_ymm_m256_imm8(dst, src, src2, imm)) } emit_vpternlogq_zmm_zmm_zmm_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM, imm: i8) { append(instructions, inst_vpternlogq_zmm_zmm_zmm_imm8(dst, src, src2, imm)) } emit_vpternlogq_zmm_zmm_m512_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512, imm: i8) { append(instructions, inst_vpternlogq_zmm_zmm_m512_imm8(dst, src, src2, imm)) } -inst_vpdpwssd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2054) } -inst_vpdpwssd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2054) } -inst_vpdpwssd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2055) } -inst_vpdpwssd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2055) } -inst_vpdpwssd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2056) } -inst_vpdpwssd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2056) } +inst_vpdpwssd_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2066) } +inst_vpdpwssd_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2066) } +inst_vpdpwssd_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2067) } +inst_vpdpwssd_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2067) } +inst_vpdpwssd_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2068) } +inst_vpdpwssd_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPDPWSSD, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2068) } emit_vpdpwssd_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpdpwssd_xmm_xmm_xmm(dst, src, src2)) } emit_vpdpwssd_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpdpwssd_xmm_xmm_m128(dst, src, src2)) } emit_vpdpwssd_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpdpwssd_ymm_ymm_ymm(dst, src, src2)) } emit_vpdpwssd_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpdpwssd_ymm_ymm_m256(dst, src, src2)) } emit_vpdpwssd_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpdpwssd_zmm_zmm_zmm(dst, src, src2)) } emit_vpdpwssd_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpdpwssd_zmm_zmm_m512(dst, src, src2)) } -inst_vpmultishiftqb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2057) } -inst_vpmultishiftqb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2057) } -inst_vpmultishiftqb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2058) } -inst_vpmultishiftqb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2058) } -inst_vpmultishiftqb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2059) } -inst_vpmultishiftqb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2059) } +inst_vpmultishiftqb_xmm_xmm_xmm :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: XMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_xmm(src2), {}} }, 2069) } +inst_vpmultishiftqb_xmm_xmm_m128 :: #force_inline proc "contextless" (dst: XMM, src: XMM, src2: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_xmm(dst), op_xmm(src), op_mem(src2.mem, 16), {}} }, 2069) } +inst_vpmultishiftqb_ymm_ymm_ymm :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: YMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_ymm(src2), {}} }, 2070) } +inst_vpmultishiftqb_ymm_ymm_m256 :: #force_inline proc "contextless" (dst: YMM, src: YMM, src2: Mem256) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_ymm(dst), op_ymm(src), op_mem(src2.mem, 32), {}} }, 2070) } +inst_vpmultishiftqb_zmm_zmm_zmm :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: ZMM) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_zmm(src2), {}} }, 2071) } +inst_vpmultishiftqb_zmm_zmm_m512 :: #force_inline proc "contextless" (dst: ZMM, src: ZMM, src2: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .VPMULTISHIFTQB, operand_count = 3, ops = {op_zmm(dst), op_zmm(src), op_mem(src2.mem, 64), {}} }, 2071) } emit_vpmultishiftqb_xmm_xmm_xmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: XMM) { append(instructions, inst_vpmultishiftqb_xmm_xmm_xmm(dst, src, src2)) } emit_vpmultishiftqb_xmm_xmm_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: XMM, src: XMM, src2: Mem128) { append(instructions, inst_vpmultishiftqb_xmm_xmm_m128(dst, src, src2)) } emit_vpmultishiftqb_ymm_ymm_ymm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: YMM) { append(instructions, inst_vpmultishiftqb_ymm_ymm_ymm(dst, src, src2)) } emit_vpmultishiftqb_ymm_ymm_m256 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: YMM, src: YMM, src2: Mem256) { append(instructions, inst_vpmultishiftqb_ymm_ymm_m256(dst, src, src2)) } emit_vpmultishiftqb_zmm_zmm_zmm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: ZMM) { append(instructions, inst_vpmultishiftqb_zmm_zmm_zmm(dst, src, src2)) } emit_vpmultishiftqb_zmm_zmm_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ZMM, src: ZMM, src2: Mem512) { append(instructions, inst_vpmultishiftqb_zmm_zmm_m512(dst, src, src2)) } -inst_kaddw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2060) } +inst_kaddw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2072) } emit_kaddw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kaddw_k_k_k(dst, src, src2)) } -inst_kaddb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2061) } +inst_kaddb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2073) } emit_kaddb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kaddb_k_k_k(dst, src, src2)) } -inst_kaddq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2062) } +inst_kaddq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2074) } emit_kaddq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kaddq_k_k_k(dst, src, src2)) } -inst_kaddd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2063) } +inst_kaddd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KADDD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2075) } emit_kaddd_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kaddd_k_k_k(dst, src, src2)) } -inst_kandw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2064) } +inst_kandw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2076) } emit_kandw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandw_k_k_k(dst, src, src2)) } -inst_kandb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2065) } +inst_kandb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2077) } emit_kandb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandb_k_k_k(dst, src, src2)) } -inst_kandq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2066) } +inst_kandq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2078) } emit_kandq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandq_k_k_k(dst, src, src2)) } -inst_kandd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2067) } +inst_kandd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2079) } emit_kandd_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandd_k_k_k(dst, src, src2)) } -inst_kandnw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2068) } +inst_kandnw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2080) } emit_kandnw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandnw_k_k_k(dst, src, src2)) } -inst_kandnb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2069) } +inst_kandnb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2081) } emit_kandnb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandnb_k_k_k(dst, src, src2)) } -inst_kandnq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2070) } +inst_kandnq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDNQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2082) } emit_kandnq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandnq_k_k_k(dst, src, src2)) } -inst_kandnd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDND, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2071) } +inst_kandnd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KANDND, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2083) } emit_kandnd_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kandnd_k_k_k(dst, src, src2)) } -inst_kmovw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2072) } -inst_kmovw_k_m16 :: #force_inline proc "contextless" (dst: KREG, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 2), {}, {}} }, 2072) } -inst_kmovw_m16_k :: #force_inline proc "contextless" (dst: Mem16, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_mem(dst.mem, 2), op_kreg(src), {}, {}} }, 2073) } -inst_kmovw_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2074) } -inst_kmovw_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2075) } +inst_kmovw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2084) } +inst_kmovw_k_m16 :: #force_inline proc "contextless" (dst: KREG, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 2), {}, {}} }, 2084) } +inst_kmovw_m16_k :: #force_inline proc "contextless" (dst: Mem16, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_mem(dst.mem, 2), op_kreg(src), {}, {}} }, 2085) } +inst_kmovw_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2086) } +inst_kmovw_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVW, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2087) } emit_kmovw_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kmovw_k_k(dst, src)) } emit_kmovw_k_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem16) { append(instructions, inst_kmovw_k_m16(dst, src)) } emit_kmovw_m16_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: KREG) { append(instructions, inst_kmovw_m16_k(dst, src)) } emit_kmovw_k_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: GPR32) { append(instructions, inst_kmovw_k_r32(dst, src)) } emit_kmovw_r32_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: KREG) { append(instructions, inst_kmovw_r32_k(dst, src)) } -inst_kmovb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2076) } -inst_kmovb_k_m8 :: #force_inline proc "contextless" (dst: KREG, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 1), {}, {}} }, 2076) } -inst_kmovb_m8_k :: #force_inline proc "contextless" (dst: Mem8, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_mem(dst.mem, 1), op_kreg(src), {}, {}} }, 2077) } -inst_kmovb_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2078) } -inst_kmovb_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2079) } +inst_kmovb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2088) } +inst_kmovb_k_m8 :: #force_inline proc "contextless" (dst: KREG, src: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 1), {}, {}} }, 2088) } +inst_kmovb_m8_k :: #force_inline proc "contextless" (dst: Mem8, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_mem(dst.mem, 1), op_kreg(src), {}, {}} }, 2089) } +inst_kmovb_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2090) } +inst_kmovb_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVB, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2091) } emit_kmovb_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kmovb_k_k(dst, src)) } emit_kmovb_k_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem8) { append(instructions, inst_kmovb_k_m8(dst, src)) } emit_kmovb_m8_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, src: KREG) { append(instructions, inst_kmovb_m8_k(dst, src)) } emit_kmovb_k_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: GPR32) { append(instructions, inst_kmovb_k_r32(dst, src)) } emit_kmovb_r32_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: KREG) { append(instructions, inst_kmovb_r32_k(dst, src)) } -inst_kmovq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2080) } -inst_kmovq_k_m64 :: #force_inline proc "contextless" (dst: KREG, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 8), {}, {}} }, 2080) } -inst_kmovq_m64_k :: #force_inline proc "contextless" (dst: Mem64, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_kreg(src), {}, {}} }, 2081) } -inst_kmovq_k_r64 :: #force_inline proc "contextless" (dst: KREG, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_gpr64(src), {}, {}} }, 2082) } -inst_kmovq_r64_k :: #force_inline proc "contextless" (dst: GPR64, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_gpr64(dst), op_kreg(src), {}, {}} }, 2083) } +inst_kmovq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2092) } +inst_kmovq_k_m64 :: #force_inline proc "contextless" (dst: KREG, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 8), {}, {}} }, 2092) } +inst_kmovq_m64_k :: #force_inline proc "contextless" (dst: Mem64, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_kreg(src), {}, {}} }, 2093) } +inst_kmovq_k_r64 :: #force_inline proc "contextless" (dst: KREG, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_kreg(dst), op_gpr64(src), {}, {}} }, 2094) } +inst_kmovq_r64_k :: #force_inline proc "contextless" (dst: GPR64, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVQ, operand_count = 2, ops = {op_gpr64(dst), op_kreg(src), {}, {}} }, 2095) } emit_kmovq_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kmovq_k_k(dst, src)) } emit_kmovq_k_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem64) { append(instructions, inst_kmovq_k_m64(dst, src)) } emit_kmovq_m64_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: KREG) { append(instructions, inst_kmovq_m64_k(dst, src)) } emit_kmovq_k_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: GPR64) { append(instructions, inst_kmovq_k_r64(dst, src)) } emit_kmovq_r64_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: KREG) { append(instructions, inst_kmovq_r64_k(dst, src)) } -inst_kmovd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2084) } -inst_kmovd_k_m32 :: #force_inline proc "contextless" (dst: KREG, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 4), {}, {}} }, 2084) } -inst_kmovd_m32_k :: #force_inline proc "contextless" (dst: Mem32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_kreg(src), {}, {}} }, 2085) } -inst_kmovd_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2086) } -inst_kmovd_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2087) } +inst_kmovd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2096) } +inst_kmovd_k_m32 :: #force_inline proc "contextless" (dst: KREG, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_mem(src.mem, 4), {}, {}} }, 2096) } +inst_kmovd_m32_k :: #force_inline proc "contextless" (dst: Mem32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_kreg(src), {}, {}} }, 2097) } +inst_kmovd_k_r32 :: #force_inline proc "contextless" (dst: KREG, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_kreg(dst), op_gpr32(src), {}, {}} }, 2098) } +inst_kmovd_r32_k :: #force_inline proc "contextless" (dst: GPR32, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KMOVD, operand_count = 2, ops = {op_gpr32(dst), op_kreg(src), {}, {}} }, 2099) } emit_kmovd_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kmovd_k_k(dst, src)) } emit_kmovd_k_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: Mem32) { append(instructions, inst_kmovd_k_m32(dst, src)) } emit_kmovd_m32_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: KREG) { append(instructions, inst_kmovd_m32_k(dst, src)) } emit_kmovd_k_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: GPR32) { append(instructions, inst_kmovd_k_r32(dst, src)) } emit_kmovd_r32_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: KREG) { append(instructions, inst_kmovd_r32_k(dst, src)) } -inst_knotw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2088) } +inst_knotw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2100) } emit_knotw_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_knotw_k_k(dst, src)) } -inst_knotb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2089) } +inst_knotb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2101) } emit_knotb_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_knotb_k_k(dst, src)) } -inst_knotq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2090) } +inst_knotq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2102) } emit_knotq_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_knotq_k_k(dst, src)) } -inst_knotd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2091) } +inst_knotd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KNOTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2103) } emit_knotd_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_knotd_k_k(dst, src)) } -inst_korw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2092) } +inst_korw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2104) } emit_korw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_korw_k_k_k(dst, src, src2)) } -inst_korb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2093) } +inst_korb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2105) } emit_korb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_korb_k_k_k(dst, src, src2)) } -inst_korq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2094) } +inst_korq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2106) } emit_korq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_korq_k_k_k(dst, src, src2)) } -inst_kord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2095) } +inst_kord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2107) } emit_kord_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kord_k_k_k(dst, src, src2)) } -inst_kortestw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2096) } +inst_kortestw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2108) } emit_kortestw_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kortestw_k_k(dst, src)) } -inst_kortestb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2097) } +inst_kortestb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2109) } emit_kortestb_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kortestb_k_k(dst, src)) } -inst_kortestq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2098) } +inst_kortestq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2110) } emit_kortestq_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kortestq_k_k(dst, src)) } -inst_kortestd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2099) } +inst_kortestd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KORTESTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2111) } emit_kortestd_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_kortestd_k_k(dst, src)) } -inst_kshiftlw_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2100) } +inst_kshiftlw_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2112) } emit_kshiftlw_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftlw_k_k_imm8(dst, src, imm)) } -inst_kshiftlb_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2101) } +inst_kshiftlb_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2113) } emit_kshiftlb_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftlb_k_k_imm8(dst, src, imm)) } -inst_kshiftlq_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2102) } +inst_kshiftlq_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2114) } emit_kshiftlq_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftlq_k_k_imm8(dst, src, imm)) } -inst_kshiftld_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2103) } +inst_kshiftld_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTLD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2115) } emit_kshiftld_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftld_k_k_imm8(dst, src, imm)) } -inst_kshiftrw_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2104) } +inst_kshiftrw_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2116) } emit_kshiftrw_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftrw_k_k_imm8(dst, src, imm)) } -inst_kshiftrb_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2105) } +inst_kshiftrb_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2117) } emit_kshiftrb_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftrb_k_k_imm8(dst, src, imm)) } -inst_kshiftrq_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2106) } +inst_kshiftrq_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2118) } emit_kshiftrq_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftrq_k_k_imm8(dst, src, imm)) } -inst_kshiftrd_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2107) } +inst_kshiftrd_k_k_imm8 :: #force_inline proc "contextless" (dst: KREG, src: KREG, imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .KSHIFTRD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_imm8(imm), {}} }, 2119) } emit_kshiftrd_k_k_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, imm: i8) { append(instructions, inst_kshiftrd_k_k_imm8(dst, src, imm)) } -inst_ktestw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2108) } +inst_ktestw_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTW, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2120) } emit_ktestw_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_ktestw_k_k(dst, src)) } -inst_ktestb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2109) } +inst_ktestb_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTB, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2121) } emit_ktestb_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_ktestb_k_k(dst, src)) } -inst_ktestq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2110) } +inst_ktestq_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTQ, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2122) } emit_ktestq_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_ktestq_k_k(dst, src)) } -inst_ktestd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2111) } +inst_ktestd_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KTESTD, operand_count = 2, ops = {op_kreg(dst), op_kreg(src), {}, {}} }, 2123) } emit_ktestd_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG) { append(instructions, inst_ktestd_k_k(dst, src)) } -inst_kunpckbw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKBW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2112) } +inst_kunpckbw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKBW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2124) } emit_kunpckbw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kunpckbw_k_k_k(dst, src, src2)) } -inst_kunpckwd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKWD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2113) } +inst_kunpckwd_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKWD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2125) } emit_kunpckwd_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kunpckwd_k_k_k(dst, src, src2)) } -inst_kunpckdq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2114) } +inst_kunpckdq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KUNPCKDQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2126) } emit_kunpckdq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kunpckdq_k_k_k(dst, src, src2)) } -inst_kxnorw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2115) } +inst_kxnorw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2127) } emit_kxnorw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxnorw_k_k_k(dst, src, src2)) } -inst_kxnorb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2116) } +inst_kxnorb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2128) } emit_kxnorb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxnorb_k_k_k(dst, src, src2)) } -inst_kxnorq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2117) } +inst_kxnorq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2129) } emit_kxnorq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxnorq_k_k_k(dst, src, src2)) } -inst_kxnord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2118) } +inst_kxnord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXNORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2130) } emit_kxnord_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxnord_k_k_k(dst, src, src2)) } -inst_kxorw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2119) } +inst_kxorw_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORW, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2131) } emit_kxorw_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxorw_k_k_k(dst, src, src2)) } -inst_kxorb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2120) } +inst_kxorb_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORB, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2132) } emit_kxorb_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxorb_k_k_k(dst, src, src2)) } -inst_kxorq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2121) } +inst_kxorq_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORQ, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2133) } emit_kxorq_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxorq_k_k_k(dst, src, src2)) } -inst_kxord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2122) } +inst_kxord_k_k_k :: #force_inline proc "contextless" (dst: KREG, src: KREG, src2: KREG) -> Instruction { return with_hint(Instruction{ mnemonic = .KXORD, operand_count = 3, ops = {op_kreg(dst), op_kreg(src), op_kreg(src2), {}} }, 2134) } emit_kxord_k_k_k :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: KREG, src: KREG, src2: KREG) { append(instructions, inst_kxord_k_k_k(dst, src, src2)) } -inst_fadd_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2123) } -inst_fadd_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2124) } -inst_fadd_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2125) } +inst_fadd_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2135) } +inst_fadd_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2136) } +inst_fadd_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FADD, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2137) } emit_fadd_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fadd_m32(dst)) } emit_fadd_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fadd_m64(dst)) } emit_fadd_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fadd_st(dst)) } -inst_faddp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FADDP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2127) } -inst_faddp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FADDP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2128) } +inst_faddp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FADDP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2139) } +inst_faddp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FADDP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2140) } emit_faddp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_faddp_st(dst)) } emit_faddp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_faddp_none()) } -inst_fiadd_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIADD, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2129) } -inst_fiadd_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIADD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2130) } +inst_fiadd_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIADD, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2141) } +inst_fiadd_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIADD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2142) } emit_fiadd_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fiadd_m16(dst)) } emit_fiadd_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fiadd_m32(dst)) } -inst_fsub_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2131) } -inst_fsub_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2132) } -inst_fsub_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2133) } +inst_fsub_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2143) } +inst_fsub_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2144) } +inst_fsub_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2145) } emit_fsub_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fsub_m32(dst)) } emit_fsub_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fsub_m64(dst)) } emit_fsub_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fsub_st(dst)) } -inst_fsubp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2135) } -inst_fsubp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2136) } +inst_fsubp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2147) } +inst_fsubp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2148) } emit_fsubp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fsubp_st(dst)) } emit_fsubp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fsubp_none()) } -inst_fisub_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUB, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2137) } -inst_fisub_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUB, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2138) } +inst_fisub_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUB, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2149) } +inst_fisub_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUB, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2150) } emit_fisub_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fisub_m16(dst)) } emit_fisub_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fisub_m32(dst)) } -inst_fsubr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2139) } -inst_fsubr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2140) } -inst_fsubr_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2141) } +inst_fsubr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2151) } +inst_fsubr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2152) } +inst_fsubr_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBR, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2153) } emit_fsubr_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fsubr_m32(dst)) } emit_fsubr_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fsubr_m64(dst)) } emit_fsubr_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fsubr_st(dst)) } -inst_fsubrp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBRP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2143) } -inst_fsubrp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBRP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2144) } +inst_fsubrp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBRP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2155) } +inst_fsubrp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSUBRP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2156) } emit_fsubrp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fsubrp_st(dst)) } emit_fsubrp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fsubrp_none()) } -inst_fisubr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUBR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2145) } -inst_fisubr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUBR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2146) } +inst_fisubr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUBR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2157) } +inst_fisubr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISUBR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2158) } emit_fisubr_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fisubr_m16(dst)) } emit_fisubr_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fisubr_m32(dst)) } -inst_fmul_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2147) } -inst_fmul_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2148) } -inst_fmul_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2149) } +inst_fmul_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2159) } +inst_fmul_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2160) } +inst_fmul_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FMUL, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2161) } emit_fmul_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fmul_m32(dst)) } emit_fmul_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fmul_m64(dst)) } emit_fmul_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fmul_st(dst)) } -inst_fmulp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FMULP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2151) } -inst_fmulp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FMULP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2152) } +inst_fmulp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FMULP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2163) } +inst_fmulp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FMULP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2164) } emit_fmulp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fmulp_st(dst)) } emit_fmulp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fmulp_none()) } -inst_fimul_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIMUL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2153) } -inst_fimul_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIMUL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2154) } +inst_fimul_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIMUL, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2165) } +inst_fimul_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIMUL, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2166) } emit_fimul_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fimul_m16(dst)) } emit_fimul_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fimul_m32(dst)) } -inst_fdiv_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2155) } -inst_fdiv_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2156) } -inst_fdiv_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2157) } +inst_fdiv_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2167) } +inst_fdiv_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2168) } +inst_fdiv_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIV, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2169) } emit_fdiv_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fdiv_m32(dst)) } emit_fdiv_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fdiv_m64(dst)) } emit_fdiv_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fdiv_st(dst)) } -inst_fdivp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2159) } -inst_fdivp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2160) } +inst_fdivp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2171) } +inst_fdivp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2172) } emit_fdivp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fdivp_st(dst)) } emit_fdivp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fdivp_none()) } -inst_fidiv_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIV, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2161) } -inst_fidiv_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIV, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2162) } +inst_fidiv_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIV, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2173) } +inst_fidiv_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIV, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2174) } emit_fidiv_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fidiv_m16(dst)) } emit_fidiv_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fidiv_m32(dst)) } -inst_fdivr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2163) } -inst_fdivr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2164) } -inst_fdivr_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2165) } +inst_fdivr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2175) } +inst_fdivr_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2176) } +inst_fdivr_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVR, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2177) } emit_fdivr_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fdivr_m32(dst)) } emit_fdivr_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fdivr_m64(dst)) } emit_fdivr_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fdivr_st(dst)) } -inst_fdivrp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVRP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2167) } -inst_fdivrp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVRP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2168) } +inst_fdivrp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVRP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2179) } +inst_fdivrp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDIVRP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2180) } emit_fdivrp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fdivrp_st(dst)) } emit_fdivrp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fdivrp_none()) } -inst_fidivr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIVR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2169) } -inst_fidivr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIVR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2170) } +inst_fidivr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIVR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2181) } +inst_fidivr_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIDIVR, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2182) } emit_fidivr_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fidivr_m16(dst)) } emit_fidivr_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fidivr_m32(dst)) } -inst_fsqrt_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSQRT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2171) } +inst_fsqrt_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSQRT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2183) } emit_fsqrt_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fsqrt_none()) } -inst_fabs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FABS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2172) } +inst_fabs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FABS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2184) } emit_fabs_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fabs_none()) } -inst_fchs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCHS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2173) } +inst_fchs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCHS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2185) } emit_fchs_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fchs_none()) } -inst_fprem_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPREM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2174) } +inst_fprem_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPREM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2186) } emit_fprem_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fprem_none()) } -inst_fprem1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPREM1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2175) } +inst_fprem1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPREM1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2187) } emit_fprem1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fprem1_none()) } -inst_frndint_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FRNDINT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2176) } +inst_frndint_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FRNDINT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2188) } emit_frndint_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_frndint_none()) } -inst_fscale_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSCALE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2177) } +inst_fscale_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSCALE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2189) } emit_fscale_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fscale_none()) } -inst_fxtract_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXTRACT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2178) } +inst_fxtract_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXTRACT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2190) } emit_fxtract_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fxtract_none()) } -inst_fxam_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXAM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2179) } +inst_fxam_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXAM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2191) } emit_fxam_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fxam_none()) } -inst_fld_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2180) } -inst_fld_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2181) } -inst_fld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2182) } -inst_fld_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2183) } +inst_fld_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2192) } +inst_fld_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2193) } +inst_fld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2194) } +inst_fld_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FLD, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2195) } emit_fld_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fld_m32(dst)) } emit_fld_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fld_m64(dst)) } emit_fld_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { append(instructions, inst_fld_m80(dst)) } emit_fld_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fld_st(dst)) } -inst_fild_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2184) } -inst_fild_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2185) } -inst_fild_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2186) } +inst_fild_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2196) } +inst_fild_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2197) } +inst_fild_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FILD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2198) } emit_fild_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fild_m16(dst)) } emit_fild_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fild_m32(dst)) } emit_fild_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fild_m64(dst)) } -inst_fbld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FBLD, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2187) } +inst_fbld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FBLD, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2199) } emit_fbld_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { append(instructions, inst_fbld_m80(dst)) } -inst_fst_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2188) } -inst_fst_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2189) } -inst_fst_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2190) } +inst_fst_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2200) } +inst_fst_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2201) } +inst_fst_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FST, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2202) } emit_fst_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fst_m32(dst)) } emit_fst_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fst_m64(dst)) } emit_fst_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fst_st(dst)) } -inst_fstp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2191) } -inst_fstp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2192) } -inst_fstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2193) } -inst_fstp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2194) } +inst_fstp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2203) } +inst_fstp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2204) } +inst_fstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2205) } +inst_fstp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2206) } emit_fstp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fstp_m32(dst)) } emit_fstp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fstp_m64(dst)) } emit_fstp_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { append(instructions, inst_fstp_m80(dst)) } emit_fstp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fstp_st(dst)) } -inst_fist_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIST, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2195) } -inst_fist_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIST, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2196) } +inst_fist_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FIST, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2207) } +inst_fist_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FIST, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2208) } emit_fist_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fist_m16(dst)) } emit_fist_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fist_m32(dst)) } -inst_fistp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2197) } -inst_fistp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2198) } -inst_fistp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2199) } +inst_fistp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2209) } +inst_fistp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2210) } +inst_fistp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2211) } emit_fistp_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fistp_m16(dst)) } emit_fistp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fistp_m32(dst)) } emit_fistp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fistp_m64(dst)) } -inst_fisttp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2200) } -inst_fisttp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2201) } -inst_fisttp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2202) } +inst_fisttp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2212) } +inst_fisttp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2213) } +inst_fisttp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FISTTP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2214) } emit_fisttp_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fisttp_m16(dst)) } emit_fisttp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fisttp_m32(dst)) } emit_fisttp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fisttp_m64(dst)) } -inst_fbstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FBSTP, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2203) } +inst_fbstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return with_hint(Instruction{ mnemonic = .FBSTP, operand_count = 1, ops = {op_mem(dst.mem, 10), {}, {}, {}} }, 2215) } emit_fbstp_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { append(instructions, inst_fbstp_m80(dst)) } -inst_fxch_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FXCH, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2204) } -inst_fxch_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXCH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2205) } +inst_fxch_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FXCH, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2216) } +inst_fxch_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FXCH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2217) } emit_fxch_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fxch_st(dst)) } emit_fxch_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fxch_none()) } -inst_fcmovb_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2206) } +inst_fcmovb_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2218) } emit_fcmovb_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovb_st(dst)) } -inst_fcmove_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2207) } +inst_fcmove_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2219) } emit_fcmove_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmove_st(dst)) } -inst_fcmovbe_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVBE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2208) } +inst_fcmovbe_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVBE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2220) } emit_fcmovbe_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovbe_st(dst)) } -inst_fcmovu_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVU, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2209) } +inst_fcmovu_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVU, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2221) } emit_fcmovu_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovu_st(dst)) } -inst_fcmovnb_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2210) } +inst_fcmovnb_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNB, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2222) } emit_fcmovnb_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovnb_st(dst)) } -inst_fcmovne_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2211) } +inst_fcmovne_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2223) } emit_fcmovne_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovne_st(dst)) } -inst_fcmovnbe_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNBE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2212) } +inst_fcmovnbe_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNBE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2224) } emit_fcmovnbe_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovnbe_st(dst)) } -inst_fcmovnu_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNU, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2213) } +inst_fcmovnu_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCMOVNU, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2225) } emit_fcmovnu_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcmovnu_st(dst)) } -inst_fcom_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2214) } -inst_fcom_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2215) } -inst_fcom_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2216) } -inst_fcom_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2217) } +inst_fcom_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2226) } +inst_fcom_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2227) } +inst_fcom_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2228) } +inst_fcom_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2229) } emit_fcom_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fcom_m32(dst)) } emit_fcom_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fcom_m64(dst)) } emit_fcom_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcom_st(dst)) } emit_fcom_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fcom_none()) } -inst_fcomp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2218) } -inst_fcomp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2219) } -inst_fcomp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2220) } -inst_fcomp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2221) } +inst_fcomp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2230) } +inst_fcomp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2231) } +inst_fcomp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2232) } +inst_fcomp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2233) } emit_fcomp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_fcomp_m32(dst)) } emit_fcomp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_fcomp_m64(dst)) } emit_fcomp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcomp_st(dst)) } emit_fcomp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fcomp_none()) } -inst_fcompp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMPP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2222) } +inst_fcompp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMPP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2234) } emit_fcompp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fcompp_none()) } -inst_ficom_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOM, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2223) } -inst_ficom_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOM, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2224) } +inst_ficom_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOM, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2235) } +inst_ficom_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOM, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2236) } emit_ficom_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_ficom_m16(dst)) } emit_ficom_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_ficom_m32(dst)) } -inst_ficomp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOMP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2225) } -inst_ficomp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOMP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2226) } +inst_ficomp_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOMP, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2237) } +inst_ficomp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .FICOMP, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2238) } emit_ficomp_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_ficomp_m16(dst)) } emit_ficomp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_ficomp_m32(dst)) } -inst_fcomi_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMI, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2227) } +inst_fcomi_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMI, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2239) } emit_fcomi_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcomi_st(dst)) } -inst_fcomip_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMIP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2228) } +inst_fcomip_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FCOMIP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2240) } emit_fcomip_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fcomip_st(dst)) } -inst_fucomi_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMI, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2229) } +inst_fucomi_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMI, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2241) } emit_fucomi_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fucomi_st(dst)) } -inst_fucomip_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMIP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2230) } +inst_fucomip_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMIP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2242) } emit_fucomip_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fucomip_st(dst)) } -inst_fucom_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOM, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2231) } -inst_fucom_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2232) } +inst_fucom_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOM, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2243) } +inst_fucom_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2244) } emit_fucom_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fucom_st(dst)) } emit_fucom_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fucom_none()) } -inst_fucomp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2233) } -inst_fucomp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2234) } +inst_fucomp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2245) } +inst_fucomp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2246) } emit_fucomp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_fucomp_st(dst)) } emit_fucomp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fucomp_none()) } -inst_fucompp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMPP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2235) } +inst_fucompp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FUCOMPP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2247) } emit_fucompp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fucompp_none()) } -inst_ftst_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FTST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2236) } +inst_ftst_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FTST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2248) } emit_ftst_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ftst_none()) } -inst_fldz_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDZ, operand_count = 0, ops = {{}, {}, {}, {}} }, 2237) } +inst_fldz_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDZ, operand_count = 0, ops = {{}, {}, {}, {}} }, 2249) } emit_fldz_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldz_none()) } -inst_fld1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLD1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2238) } +inst_fld1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLD1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2250) } emit_fld1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fld1_none()) } -inst_fldpi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDPI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2239) } +inst_fldpi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDPI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2251) } emit_fldpi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldpi_none()) } -inst_fldl2t_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDL2T, operand_count = 0, ops = {{}, {}, {}, {}} }, 2240) } +inst_fldl2t_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDL2T, operand_count = 0, ops = {{}, {}, {}, {}} }, 2252) } emit_fldl2t_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldl2t_none()) } -inst_fldl2e_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDL2E, operand_count = 0, ops = {{}, {}, {}, {}} }, 2241) } +inst_fldl2e_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDL2E, operand_count = 0, ops = {{}, {}, {}, {}} }, 2253) } emit_fldl2e_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldl2e_none()) } -inst_fldlg2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDLG2, operand_count = 0, ops = {{}, {}, {}, {}} }, 2242) } +inst_fldlg2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDLG2, operand_count = 0, ops = {{}, {}, {}, {}} }, 2254) } emit_fldlg2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldlg2_none()) } -inst_fldln2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDLN2, operand_count = 0, ops = {{}, {}, {}, {}} }, 2243) } +inst_fldln2_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FLDLN2, operand_count = 0, ops = {{}, {}, {}, {}} }, 2255) } emit_fldln2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fldln2_none()) } -inst_fsin_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSIN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2244) } +inst_fsin_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSIN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2256) } emit_fsin_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fsin_none()) } -inst_fcos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2245) } +inst_fcos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2257) } emit_fcos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fcos_none()) } -inst_fsincos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSINCOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2246) } +inst_fsincos_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FSINCOS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2258) } emit_fsincos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fsincos_none()) } -inst_fptan_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPTAN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2247) } +inst_fptan_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPTAN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2259) } emit_fptan_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fptan_none()) } -inst_fpatan_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPATAN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2248) } +inst_fpatan_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FPATAN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2260) } emit_fpatan_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fpatan_none()) } -inst_f2xm1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .F2XM1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2249) } +inst_f2xm1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .F2XM1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2261) } emit_f2xm1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_f2xm1_none()) } -inst_fyl2x_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FYL2X, operand_count = 0, ops = {{}, {}, {}, {}} }, 2250) } +inst_fyl2x_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FYL2X, operand_count = 0, ops = {{}, {}, {}, {}} }, 2262) } emit_fyl2x_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fyl2x_none()) } -inst_fyl2xp1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FYL2XP1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2251) } +inst_fyl2xp1_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FYL2XP1, operand_count = 0, ops = {{}, {}, {}, {}} }, 2263) } emit_fyl2xp1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fyl2xp1_none()) } -inst_finit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2252) } +inst_finit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2264) } emit_finit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_finit_none()) } -inst_fninit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2253) } +inst_fninit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2265) } emit_fninit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fninit_none()) } -inst_fincstp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FINCSTP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2254) } +inst_fincstp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FINCSTP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2266) } emit_fincstp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fincstp_none()) } -inst_fdecstp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDECSTP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2255) } +inst_fdecstp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FDECSTP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2267) } emit_fdecstp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fdecstp_none()) } -inst_ffree_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FFREE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2256) } +inst_ffree_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FFREE, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2268) } emit_ffree_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_ffree_st(dst)) } -inst_ffreep_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FFREEP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2257) } +inst_ffreep_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return with_hint(Instruction{ mnemonic = .FFREEP, operand_count = 1, ops = {op_st(dst), {}, {}, {}} }, 2269) } emit_ffreep_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { append(instructions, inst_ffreep_st(dst)) } -inst_fnop_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNOP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2258) } +inst_fnop_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNOP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2270) } emit_fnop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fnop_none()) } -inst_fwait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FWAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2259) } +inst_fwait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FWAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2271) } emit_fwait_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fwait_none()) } -inst_fclex_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCLEX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2260) } +inst_fclex_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FCLEX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2272) } emit_fclex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fclex_none()) } -inst_fnclex_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNCLEX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2261) } +inst_fnclex_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .FNCLEX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2273) } emit_fnclex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_fnclex_none()) } -inst_fstcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2262) } +inst_fstcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2274) } emit_fstcw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fstcw_m16(dst)) } -inst_fnstcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2263) } +inst_fnstcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2275) } emit_fnstcw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fnstcw_m16(dst)) } -inst_fldcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FLDCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2264) } +inst_fldcw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FLDCW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2276) } emit_fldcw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fldcw_m16(dst)) } -inst_fstenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2265) } +inst_fstenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2277) } emit_fstenv_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_fstenv_m(dst)) } -inst_fnstenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2266) } +inst_fnstenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2278) } emit_fnstenv_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_fnstenv_m(dst)) } -inst_fldenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FLDENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2267) } +inst_fldenv_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FLDENV, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2279) } emit_fldenv_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_fldenv_m(dst)) } -inst_fsave_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FSAVE, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2268) } +inst_fsave_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FSAVE, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2280) } emit_fsave_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_fsave_m(dst)) } -inst_fnsave_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSAVE, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2269) } +inst_fnsave_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSAVE, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2281) } emit_fnsave_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_fnsave_m(dst)) } -inst_frstor_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FRSTOR, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2270) } +inst_frstor_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .FRSTOR, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2282) } emit_frstor_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_frstor_m(dst)) } -inst_fstsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2271) } +inst_fstsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FSTSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2283) } emit_fstsw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fstsw_m16(dst)) } -inst_fnstsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2273) } +inst_fnstsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .FNSTSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2285) } emit_fnstsw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_fnstsw_m16(dst)) } -inst_fxsave_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXSAVE, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2275) } +inst_fxsave_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXSAVE, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2287) } emit_fxsave_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { append(instructions, inst_fxsave_m512(dst)) } -inst_fxsave64_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXSAVE64, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2276) } +inst_fxsave64_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXSAVE64, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2288) } emit_fxsave64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { append(instructions, inst_fxsave64_m512(dst)) } -inst_fxrstor_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXRSTOR, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2277) } +inst_fxrstor_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXRSTOR, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2289) } emit_fxrstor_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { append(instructions, inst_fxrstor_m512(dst)) } -inst_fxrstor64_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXRSTOR64, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2278) } +inst_fxrstor64_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .FXRSTOR64, operand_count = 1, ops = {op_mem(dst.mem, 64), {}, {}, {}} }, 2290) } emit_fxrstor64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { append(instructions, inst_fxrstor64_m512(dst)) } -inst_lgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .LGDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2279) } +inst_lgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .LGDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2291) } emit_lgdt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_lgdt_m(dst)) } -inst_sgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .SGDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2281) } +inst_sgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .SGDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2293) } emit_sgdt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_sgdt_m(dst)) } -inst_lidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .LIDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2283) } +inst_lidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .LIDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2295) } emit_lidt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_lidt_m(dst)) } -inst_sidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .SIDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2285) } +inst_sidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .SIDT, operand_count = 1, ops = {op_mem(dst, 0), {}, {}, {}} }, 2297) } emit_sidt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_sidt_m(dst)) } -inst_lldt_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LLDT, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2287) } -inst_lldt_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LLDT, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2287) } +inst_lldt_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LLDT, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2299) } +inst_lldt_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LLDT, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2299) } emit_lldt_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_lldt_r16(dst)) } emit_lldt_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_lldt_m16(dst)) } -inst_sldt_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2288) } -inst_sldt_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2288) } -inst_sldt_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2289) } -inst_sldt_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2290) } +inst_sldt_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2300) } +inst_sldt_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2300) } +inst_sldt_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2301) } +inst_sldt_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SLDT, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2302) } emit_sldt_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_sldt_r16(dst)) } emit_sldt_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_sldt_m16(dst)) } emit_sldt_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_sldt_r32(dst)) } emit_sldt_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_sldt_r64(dst)) } -inst_ltr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LTR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2291) } -inst_ltr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LTR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2291) } +inst_ltr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LTR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2303) } +inst_ltr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LTR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2303) } emit_ltr_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_ltr_r16(dst)) } emit_ltr_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_ltr_m16(dst)) } -inst_str_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2292) } -inst_str_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2292) } -inst_str_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2293) } -inst_str_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2294) } +inst_str_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2304) } +inst_str_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2304) } +inst_str_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2305) } +inst_str_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .STR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2306) } emit_str_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_str_r16(dst)) } emit_str_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_str_m16(dst)) } emit_str_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_str_r32(dst)) } emit_str_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_str_r64(dst)) } -inst_lmsw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LMSW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2295) } -inst_lmsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LMSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2295) } +inst_lmsw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LMSW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2307) } +inst_lmsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LMSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2307) } emit_lmsw_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_lmsw_r16(dst)) } emit_lmsw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_lmsw_m16(dst)) } -inst_smsw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2296) } -inst_smsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2296) } -inst_smsw_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2297) } -inst_smsw_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2298) } +inst_smsw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2308) } +inst_smsw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2308) } +inst_smsw_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2309) } +inst_smsw_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .SMSW, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2310) } emit_smsw_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_smsw_r16(dst)) } emit_smsw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_smsw_m16(dst)) } emit_smsw_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_smsw_r32(dst)) } emit_smsw_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_smsw_r64(dst)) } -inst_clts_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLTS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2299) } +inst_clts_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLTS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2311) } emit_clts_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clts_none()) } -inst_arpl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ARPL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2300) } -inst_arpl_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ARPL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2300) } +inst_arpl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ARPL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2312) } +inst_arpl_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .ARPL, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2312) } emit_arpl_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_arpl_r16_r16(dst, src)) } emit_arpl_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_arpl_m16_r16(dst, src)) } -inst_lar_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2301) } -inst_lar_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2301) } -inst_lar_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2302) } -inst_lar_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2302) } -inst_lar_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2303) } -inst_lar_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2303) } +inst_lar_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2313) } +inst_lar_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2313) } +inst_lar_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2314) } +inst_lar_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2314) } +inst_lar_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2315) } +inst_lar_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LAR, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2315) } emit_lar_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_lar_r16_r16(dst, src)) } emit_lar_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_lar_r16_m16(dst, src)) } emit_lar_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_lar_r32_r32(dst, src)) } emit_lar_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_lar_r32_m32(dst, src)) } emit_lar_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_lar_r64_r64(dst, src)) } emit_lar_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_lar_r64_m64(dst, src)) } -inst_lsl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2304) } -inst_lsl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2304) } -inst_lsl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2305) } -inst_lsl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2305) } -inst_lsl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2306) } -inst_lsl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2306) } +inst_lsl_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2316) } +inst_lsl_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2316) } +inst_lsl_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2317) } +inst_lsl_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2317) } +inst_lsl_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2318) } +inst_lsl_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .LSL, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2318) } emit_lsl_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_lsl_r16_r16(dst, src)) } emit_lsl_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_lsl_r16_m16(dst, src)) } emit_lsl_r32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: GPR32) { append(instructions, inst_lsl_r32_r32(dst, src)) } emit_lsl_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_lsl_r32_m32(dst, src)) } emit_lsl_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_lsl_r64_r64(dst, src)) } emit_lsl_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_lsl_r64_m64(dst, src)) } -inst_verr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2307) } -inst_verr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2307) } +inst_verr_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERR, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2319) } +inst_verr_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERR, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2319) } emit_verr_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_verr_r16(dst)) } emit_verr_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_verr_m16(dst)) } -inst_verw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2308) } -inst_verw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2308) } +inst_verw_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERW, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2320) } +inst_verw_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .VERW, operand_count = 1, ops = {op_mem(dst.mem, 2), {}, {}, {}} }, 2320) } emit_verw_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_verw_r16(dst)) } emit_verw_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { append(instructions, inst_verw_m16(dst)) } -inst_invd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2309) } +inst_invd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2321) } emit_invd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_invd_none()) } -inst_wbinvd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WBINVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2310) } +inst_wbinvd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WBINVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2322) } emit_wbinvd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wbinvd_none()) } -inst_invlpg_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2311) } +inst_invlpg_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPG, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2323) } emit_invlpg_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_invlpg_m8(dst)) } -inst_invpcid_r32_m128 :: #force_inline proc "contextless" (dst: GPR32, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVPCID, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 16), {}, {}} }, 2312) } -inst_invpcid_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVPCID, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2313) } +inst_invpcid_r32_m128 :: #force_inline proc "contextless" (dst: GPR32, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVPCID, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 16), {}, {}} }, 2324) } +inst_invpcid_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVPCID, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2325) } emit_invpcid_r32_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem128) { append(instructions, inst_invpcid_r32_m128(dst, src)) } emit_invpcid_r64_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem128) { append(instructions, inst_invpcid_r64_m128(dst, src)) } -inst_rsm_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RSM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2314) } +inst_rsm_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RSM, operand_count = 0, ops = {{}, {}, {}, {}} }, 2326) } emit_rsm_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rsm_none()) } -inst_rdmsr_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDMSR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2315) } +inst_rdmsr_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDMSR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2327) } emit_rdmsr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdmsr_none()) } -inst_wrmsr_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WRMSR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2316) } +inst_wrmsr_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WRMSR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2328) } emit_wrmsr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wrmsr_none()) } -inst_vmcall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 2317) } +inst_vmcall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 2329) } emit_vmcall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmcall_none()) } -inst_vmlaunch_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMLAUNCH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2318) } +inst_vmlaunch_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMLAUNCH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2330) } emit_vmlaunch_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmlaunch_none()) } -inst_vmresume_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMRESUME, operand_count = 0, ops = {{}, {}, {}, {}} }, 2319) } +inst_vmresume_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMRESUME, operand_count = 0, ops = {{}, {}, {}, {}} }, 2331) } emit_vmresume_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmresume_none()) } -inst_vmxoff_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMXOFF, operand_count = 0, ops = {{}, {}, {}, {}} }, 2320) } +inst_vmxoff_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMXOFF, operand_count = 0, ops = {{}, {}, {}, {}} }, 2332) } emit_vmxoff_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmxoff_none()) } -inst_vmxon_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMXON, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2321) } +inst_vmxon_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMXON, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2333) } emit_vmxon_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_vmxon_m64(dst)) } -inst_vmclear_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMCLEAR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2322) } +inst_vmclear_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMCLEAR, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2334) } emit_vmclear_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_vmclear_m64(dst)) } -inst_vmptrld_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPTRLD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2323) } +inst_vmptrld_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPTRLD, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2335) } emit_vmptrld_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_vmptrld_m64(dst)) } -inst_vmptrst_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPTRST, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2324) } +inst_vmptrst_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMPTRST, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2336) } emit_vmptrst_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_vmptrst_m64(dst)) } -inst_vmread_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMREAD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2325) } -inst_vmread_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMREAD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2325) } +inst_vmread_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMREAD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2337) } +inst_vmread_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMREAD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2337) } emit_vmread_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_vmread_r64_r64(dst, src)) } emit_vmread_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_vmread_m64_r64(dst, src)) } -inst_vmwrite_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMWRITE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2326) } -inst_vmwrite_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMWRITE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2326) } +inst_vmwrite_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMWRITE, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2338) } +inst_vmwrite_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .VMWRITE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2338) } emit_vmwrite_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_vmwrite_r64_r64(dst, src)) } emit_vmwrite_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_vmwrite_r64_m64(dst, src)) } -inst_vmfunc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMFUNC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2327) } +inst_vmfunc_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMFUNC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2339) } emit_vmfunc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmfunc_none()) } -inst_invept_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVEPT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2328) } +inst_invept_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVEPT, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2340) } emit_invept_r64_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem128) { append(instructions, inst_invept_r64_m128(dst, src)) } -inst_invvpid_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVVPID, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2329) } +inst_invvpid_r64_m128 :: #force_inline proc "contextless" (dst: GPR64, src: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .INVVPID, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 16), {}, {}} }, 2341) } emit_invvpid_r64_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem128) { append(instructions, inst_invvpid_r64_m128(dst, src)) } -inst_encls_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2330) } +inst_encls_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2342) } emit_encls_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_encls_none()) } -inst_enclu_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2331) } +inst_enclu_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2343) } emit_enclu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_enclu_none()) } -inst_enclv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLV, operand_count = 0, ops = {{}, {}, {}, {}} }, 2332) } +inst_enclv_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENCLV, operand_count = 0, ops = {{}, {}, {}, {}} }, 2344) } emit_enclv_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_enclv_none()) } -inst_rdpkru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPKRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2333) } +inst_rdpkru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPKRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2345) } emit_rdpkru_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdpkru_none()) } -inst_wrpkru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WRPKRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2334) } +inst_wrpkru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WRPKRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2346) } emit_wrpkru_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wrpkru_none()) } -inst_incsspd_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .INCSSPD, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2335) } +inst_incsspd_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .INCSSPD, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2347) } emit_incsspd_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_incsspd_r32(dst)) } -inst_incsspq_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .INCSSPQ, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2336) } +inst_incsspq_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .INCSSPQ, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2348) } emit_incsspq_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_incsspq_r64(dst)) } -inst_rdsspd_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSSPD, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2337) } +inst_rdsspd_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSSPD, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2349) } emit_rdsspd_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_rdsspd_r32(dst)) } -inst_rdsspq_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSSPQ, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2338) } +inst_rdsspq_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSSPQ, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2350) } emit_rdsspq_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdsspq_r64(dst)) } -inst_saveprevssp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SAVEPREVSSP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2339) } +inst_saveprevssp_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SAVEPREVSSP, operand_count = 0, ops = {{}, {}, {}, {}} }, 2351) } emit_saveprevssp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_saveprevssp_none()) } -inst_rstorssp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RSTORSSP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2340) } +inst_rstorssp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .RSTORSSP, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2352) } emit_rstorssp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_rstorssp_m64(dst)) } -inst_wrssd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRSSD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2341) } +inst_wrssd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRSSD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2353) } emit_wrssd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_wrssd_m32_r32(dst, src)) } -inst_wrssq_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRSSQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2342) } +inst_wrssq_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRSSQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2354) } emit_wrssq_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_wrssq_m64_r64(dst, src)) } -inst_wrussd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRUSSD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2343) } +inst_wrussd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRUSSD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2355) } emit_wrussd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_wrussd_m32_r32(dst, src)) } -inst_wrussq_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRUSSQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2344) } +inst_wrussq_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRUSSQ, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2356) } emit_wrussq_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_wrussq_m64_r64(dst, src)) } -inst_setssbsy_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SETSSBSY, operand_count = 0, ops = {{}, {}, {}, {}} }, 2345) } +inst_setssbsy_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SETSSBSY, operand_count = 0, ops = {{}, {}, {}, {}} }, 2357) } emit_setssbsy_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setssbsy_none()) } -inst_clrssbsy_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CLRSSBSY, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2346) } +inst_clrssbsy_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CLRSSBSY, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2358) } emit_clrssbsy_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_clrssbsy_m64(dst)) } -inst_endbr64_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENDBR64, operand_count = 0, ops = {{}, {}, {}, {}} }, 2347) } +inst_endbr64_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENDBR64, operand_count = 0, ops = {{}, {}, {}, {}} }, 2359) } emit_endbr64_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_endbr64_none()) } -inst_endbr32_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENDBR32, operand_count = 0, ops = {{}, {}, {}, {}} }, 2348) } +inst_endbr32_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .ENDBR32, operand_count = 0, ops = {{}, {}, {}, {}} }, 2360) } emit_endbr32_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_endbr32_none()) } -inst_xsave_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2349) } +inst_xsave_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2361) } emit_xsave_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsave_m8(dst)) } -inst_xsave64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVE64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2350) } +inst_xsave64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVE64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2362) } emit_xsave64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsave64_m8(dst)) } -inst_xrstor_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTOR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2351) } +inst_xrstor_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTOR, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2363) } emit_xrstor_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xrstor_m8(dst)) } -inst_xrstor64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTOR64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2352) } +inst_xrstor64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTOR64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2364) } emit_xrstor64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xrstor64_m8(dst)) } -inst_xsaveopt_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEOPT, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2353) } +inst_xsaveopt_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEOPT, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2365) } emit_xsaveopt_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsaveopt_m8(dst)) } -inst_xsaveopt64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEOPT64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2354) } +inst_xsaveopt64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEOPT64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2366) } emit_xsaveopt64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsaveopt64_m8(dst)) } -inst_xsavec_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2355) } +inst_xsavec_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEC, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2367) } emit_xsavec_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsavec_m8(dst)) } -inst_xsavec64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEC64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2356) } +inst_xsavec64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVEC64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2368) } emit_xsavec64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsavec64_m8(dst)) } -inst_xsaves_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVES, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2357) } +inst_xsaves_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVES, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2369) } emit_xsaves_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsaves_m8(dst)) } -inst_xsaves64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVES64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2358) } +inst_xsaves64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XSAVES64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2370) } emit_xsaves64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xsaves64_m8(dst)) } -inst_xrstors_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTORS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2359) } +inst_xrstors_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTORS, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2371) } emit_xrstors_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xrstors_m8(dst)) } -inst_xrstors64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTORS64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2360) } +inst_xrstors64_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .XRSTORS64, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2372) } emit_xrstors64_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_xrstors64_m8(dst)) } -inst_prefetcht0_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT0, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2361) } +inst_prefetcht0_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT0, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2373) } emit_prefetcht0_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetcht0_m8(dst)) } -inst_prefetcht1_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT1, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2362) } +inst_prefetcht1_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT1, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2374) } emit_prefetcht1_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetcht1_m8(dst)) } -inst_prefetcht2_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT2, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2363) } +inst_prefetcht2_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHT2, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2375) } emit_prefetcht2_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetcht2_m8(dst)) } -inst_prefetchnta_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHNTA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2364) } +inst_prefetchnta_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHNTA, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2376) } emit_prefetchnta_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetchnta_m8(dst)) } -inst_prefetchw_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHW, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2365) } +inst_prefetchw_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCHW, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2377) } emit_prefetchw_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetchw_m8(dst)) } -inst_clflushopt_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLFLUSHOPT, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2366) } +inst_clflushopt_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLFLUSHOPT, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2378) } emit_clflushopt_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_clflushopt_m8(dst)) } -inst_clwb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLWB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2367) } +inst_clwb_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLWB, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2379) } emit_clwb_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_clwb_m8(dst)) } -inst_cldemote_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLDEMOTE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2368) } +inst_cldemote_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .CLDEMOTE, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2380) } emit_cldemote_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_cldemote_m8(dst)) } -inst_bswap_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSWAP, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2369) } -inst_bswap_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSWAP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2370) } +inst_bswap_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .BSWAP, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2381) } +inst_bswap_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .BSWAP, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2382) } emit_bswap_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_bswap_r32(dst)) } emit_bswap_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_bswap_r64(dst)) } -inst_cmpxchg_r8_r8 :: #force_inline proc "contextless" (dst: GPR8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr8(dst), op_gpr8(src), {}, {}} }, 2371) } -inst_cmpxchg_m8_r8 :: #force_inline proc "contextless" (dst: Mem8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 1), op_gpr8(src), {}, {}} }, 2371) } -inst_cmpxchg_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2372) } -inst_cmpxchg_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2372) } -inst_cmpxchg_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2373) } -inst_cmpxchg_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2373) } -inst_cmpxchg_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2374) } -inst_cmpxchg_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2374) } +inst_cmpxchg_r8_r8 :: #force_inline proc "contextless" (dst: GPR8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr8(dst), op_gpr8(src), {}, {}} }, 2383) } +inst_cmpxchg_m8_r8 :: #force_inline proc "contextless" (dst: Mem8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 1), op_gpr8(src), {}, {}} }, 2383) } +inst_cmpxchg_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2384) } +inst_cmpxchg_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2384) } +inst_cmpxchg_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2385) } +inst_cmpxchg_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2385) } +inst_cmpxchg_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2386) } +inst_cmpxchg_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2386) } emit_cmpxchg_r8_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, src: GPR8) { append(instructions, inst_cmpxchg_r8_r8(dst, src)) } emit_cmpxchg_m8_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, src: GPR8) { append(instructions, inst_cmpxchg_m8_r8(dst, src)) } emit_cmpxchg_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_cmpxchg_r16_r16(dst, src)) } @@ -7641,18 +7673,18 @@ emit_cmpxchg_r32_r32 :: #force_inline proc(instructions: ^[dynami emit_cmpxchg_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_cmpxchg_m32_r32(dst, src)) } emit_cmpxchg_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_cmpxchg_r64_r64(dst, src)) } emit_cmpxchg_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_cmpxchg_m64_r64(dst, src)) } -inst_cmpxchg8b_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG8B, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2375) } +inst_cmpxchg8b_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG8B, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2387) } emit_cmpxchg8b_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_cmpxchg8b_m64(dst)) } -inst_cmpxchg16b_m128 :: #force_inline proc "contextless" (dst: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG16B, operand_count = 1, ops = {op_mem(dst.mem, 16), {}, {}, {}} }, 2376) } +inst_cmpxchg16b_m128 :: #force_inline proc "contextless" (dst: Mem128) -> Instruction { return with_hint(Instruction{ mnemonic = .CMPXCHG16B, operand_count = 1, ops = {op_mem(dst.mem, 16), {}, {}, {}} }, 2388) } emit_cmpxchg16b_m128 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem128) { append(instructions, inst_cmpxchg16b_m128(dst)) } -inst_xadd_r8_r8 :: #force_inline proc "contextless" (dst: GPR8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr8(dst), op_gpr8(src), {}, {}} }, 2377) } -inst_xadd_m8_r8 :: #force_inline proc "contextless" (dst: Mem8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 1), op_gpr8(src), {}, {}} }, 2377) } -inst_xadd_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2378) } -inst_xadd_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2378) } -inst_xadd_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2379) } -inst_xadd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2379) } -inst_xadd_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2380) } -inst_xadd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2380) } +inst_xadd_r8_r8 :: #force_inline proc "contextless" (dst: GPR8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr8(dst), op_gpr8(src), {}, {}} }, 2389) } +inst_xadd_m8_r8 :: #force_inline proc "contextless" (dst: Mem8, src: GPR8) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 1), op_gpr8(src), {}, {}} }, 2389) } +inst_xadd_r16_r16 :: #force_inline proc "contextless" (dst: GPR16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr16(dst), op_gpr16(src), {}, {}} }, 2390) } +inst_xadd_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2390) } +inst_xadd_r32_r32 :: #force_inline proc "contextless" (dst: GPR32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr32(dst), op_gpr32(src), {}, {}} }, 2391) } +inst_xadd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2391) } +inst_xadd_r64_r64 :: #force_inline proc "contextless" (dst: GPR64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_gpr64(dst), op_gpr64(src), {}, {}} }, 2392) } +inst_xadd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .XADD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2392) } emit_xadd_r8_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR8, src: GPR8) { append(instructions, inst_xadd_r8_r8(dst, src)) } emit_xadd_m8_r8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8, src: GPR8) { append(instructions, inst_xadd_m8_r8(dst, src)) } emit_xadd_r16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: GPR16) { append(instructions, inst_xadd_r16_r16(dst, src)) } @@ -7661,157 +7693,161 @@ emit_xadd_r32_r32 :: #force_inline proc(instructions: ^[dynami emit_xadd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_xadd_m32_r32(dst, src)) } emit_xadd_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { append(instructions, inst_xadd_r64_r64(dst, src)) } emit_xadd_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_xadd_m64_r64(dst, src)) } -inst_bound_r16_m :: #force_inline proc "contextless" (dst: GPR16, src: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .BOUND, operand_count = 2, ops = {op_gpr16(dst), op_mem(src, 0), {}, {}} }, 2381) } -inst_bound_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BOUND, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2382) } +inst_bound_r16_m :: #force_inline proc "contextless" (dst: GPR16, src: Memory) -> Instruction { return with_hint(Instruction{ mnemonic = .BOUND, operand_count = 2, ops = {op_gpr16(dst), op_mem(src, 0), {}, {}} }, 2393) } +inst_bound_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .BOUND, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2394) } emit_bound_r16_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Memory) { append(instructions, inst_bound_r16_m(dst, src)) } emit_bound_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_bound_r32_m32(dst, src)) } -inst_enter_imm16_imm8 :: #force_inline proc "contextless" (imm: i16, imm2: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ENTER, operand_count = 2, ops = {op_imm16(imm), op_imm8(imm2), {}, {}} }, 2383) } +inst_enter_imm16_imm8 :: #force_inline proc "contextless" (imm: i16, imm2: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .ENTER, operand_count = 2, ops = {op_imm16(imm), op_imm8(imm2), {}, {}} }, 2395) } emit_enter_imm16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i16, imm2: i8) { append(instructions, inst_enter_imm16_imm8(imm, imm2)) } -inst_leave_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LEAVE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2384) } +inst_leave_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .LEAVE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2396) } emit_leave_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_leave_none()) } -inst_xlat_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XLAT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2385) } +inst_xlat_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XLAT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2397) } emit_xlat_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xlat_none()) } -inst_xlatb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XLATB, operand_count = 0, ops = {{}, {}, {}, {}} }, 2386) } +inst_xlatb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XLATB, operand_count = 0, ops = {{}, {}, {}, {}} }, 2398) } emit_xlatb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xlatb_none()) } -inst_movbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2387) } -inst_movbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2388) } -inst_movbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2389) } -inst_movbe_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2390) } -inst_movbe_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2391) } -inst_movbe_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2392) } +inst_movbe_r16_m16 :: #force_inline proc "contextless" (dst: GPR16, src: Mem16) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr16(dst), op_mem(src.mem, 2), {}, {}} }, 2399) } +inst_movbe_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr32(dst), op_mem(src.mem, 4), {}, {}} }, 2400) } +inst_movbe_r64_m64 :: #force_inline proc "contextless" (dst: GPR64, src: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 8), {}, {}} }, 2401) } +inst_movbe_m16_r16 :: #force_inline proc "contextless" (dst: Mem16, src: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 2), op_gpr16(src), {}, {}} }, 2402) } +inst_movbe_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2403) } +inst_movbe_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVBE, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2404) } emit_movbe_r16_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Mem16) { append(instructions, inst_movbe_r16_m16(dst, src)) } emit_movbe_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { append(instructions, inst_movbe_r32_m32(dst, src)) } emit_movbe_r64_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem64) { append(instructions, inst_movbe_r64_m64(dst, src)) } emit_movbe_m16_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16, src: GPR16) { append(instructions, inst_movbe_m16_r16(dst, src)) } emit_movbe_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_movbe_m32_r32(dst, src)) } emit_movbe_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_movbe_m64_r64(dst, src)) } -inst_rdrand_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2393) } -inst_rdrand_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2394) } -inst_rdrand_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2395) } +inst_rdrand_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2405) } +inst_rdrand_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2406) } +inst_rdrand_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDRAND, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2407) } emit_rdrand_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_rdrand_r16(dst)) } emit_rdrand_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_rdrand_r32(dst)) } emit_rdrand_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdrand_r64(dst)) } -inst_rdseed_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2396) } -inst_rdseed_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2397) } -inst_rdseed_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2398) } +inst_rdseed_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr16(dst), {}, {}, {}} }, 2408) } +inst_rdseed_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2409) } +inst_rdseed_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDSEED, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2410) } emit_rdseed_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { append(instructions, inst_rdseed_r16(dst)) } emit_rdseed_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_rdseed_r32(dst)) } emit_rdseed_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdseed_r64(dst)) } -inst_swapgs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SWAPGS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2399) } +inst_swapgs_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SWAPGS, operand_count = 0, ops = {{}, {}, {}, {}} }, 2411) } emit_swapgs_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_swapgs_none()) } -inst_monitor_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MONITOR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2400) } +inst_monitor_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MONITOR, operand_count = 0, ops = {{}, {}, {}, {}} }, 2412) } emit_monitor_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_monitor_none()) } -inst_mwait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MWAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2401) } +inst_mwait_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MWAIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2413) } emit_mwait_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_mwait_none()) } -inst_clac_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLAC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2402) } +inst_clac_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLAC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2414) } emit_clac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clac_none()) } -inst_stac_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STAC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2403) } +inst_stac_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STAC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2415) } emit_stac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stac_none()) } -inst_rdfsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDFSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2404) } -inst_rdfsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDFSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2405) } +inst_rdfsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDFSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2416) } +inst_rdfsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDFSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2417) } emit_rdfsbase_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_rdfsbase_r32(dst)) } emit_rdfsbase_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdfsbase_r64(dst)) } -inst_rdgsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDGSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2406) } -inst_rdgsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDGSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2407) } +inst_rdgsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .RDGSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2418) } +inst_rdgsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDGSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2419) } emit_rdgsbase_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_rdgsbase_r32(dst)) } emit_rdgsbase_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdgsbase_r64(dst)) } -inst_wrfsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRFSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2408) } -inst_wrfsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRFSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2409) } +inst_wrfsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRFSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2420) } +inst_wrfsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRFSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2421) } emit_wrfsbase_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_wrfsbase_r32(dst)) } emit_wrfsbase_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_wrfsbase_r64(dst)) } -inst_wrgsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRGSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2410) } -inst_wrgsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRGSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2411) } +inst_wrgsbase_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .WRGSBASE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2422) } +inst_wrgsbase_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .WRGSBASE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2423) } emit_wrgsbase_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_wrgsbase_r32(dst)) } emit_wrgsbase_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_wrgsbase_r64(dst)) } -inst_ptwrite_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2412) } -inst_ptwrite_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2412) } -inst_ptwrite_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2413) } -inst_ptwrite_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2413) } +inst_ptwrite_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2424) } +inst_ptwrite_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_mem(dst.mem, 4), {}, {}, {}} }, 2424) } +inst_ptwrite_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2425) } +inst_ptwrite_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return with_hint(Instruction{ mnemonic = .PTWRITE, operand_count = 1, ops = {op_mem(dst.mem, 8), {}, {}, {}} }, 2425) } emit_ptwrite_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_ptwrite_r32(dst)) } emit_ptwrite_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { append(instructions, inst_ptwrite_m32(dst)) } emit_ptwrite_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_ptwrite_r64(dst)) } emit_ptwrite_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { append(instructions, inst_ptwrite_m64(dst)) } -inst_rdpid_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDPID, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2414) } +inst_rdpid_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .RDPID, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2426) } emit_rdpid_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_rdpid_r64(dst)) } -inst_wbnoinvd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WBNOINVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2415) } +inst_wbnoinvd_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .WBNOINVD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2427) } emit_wbnoinvd_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wbnoinvd_none()) } -inst_serialize_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SERIALIZE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2416) } +inst_serialize_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SERIALIZE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2428) } emit_serialize_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_serialize_none()) } -inst_prefetch_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCH, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2417) } +inst_prefetch_m8 :: #force_inline proc "contextless" (dst: Mem8) -> Instruction { return with_hint(Instruction{ mnemonic = .PREFETCH, operand_count = 1, ops = {op_mem(dst.mem, 1), {}, {}, {}} }, 2429) } emit_prefetch_m8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem8) { append(instructions, inst_prefetch_m8(dst)) } -inst_tpause_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .TPAUSE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2418) } +inst_in_imm8 :: #force_inline proc "contextless" (imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .IN, operand_count = 1, ops = {op_imm8(imm), {}, {}, {}} }, 2430) } +emit_in_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i8) { append(instructions, inst_in_imm8(imm)) } +inst_out_imm8 :: #force_inline proc "contextless" (imm: i8) -> Instruction { return with_hint(Instruction{ mnemonic = .OUT, operand_count = 1, ops = {op_imm8(imm), {}, {}, {}} }, 2436) } +emit_out_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i8) { append(instructions, inst_out_imm8(imm)) } +inst_tpause_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .TPAUSE, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2442) } emit_tpause_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_tpause_r32(dst)) } -inst_umonitor_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .UMONITOR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2419) } +inst_umonitor_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .UMONITOR, operand_count = 1, ops = {op_gpr64(dst), {}, {}, {}} }, 2443) } emit_umonitor_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { append(instructions, inst_umonitor_r64(dst)) } -inst_umwait_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UMWAIT, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2420) } +inst_umwait_r32 :: #force_inline proc "contextless" (dst: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .UMWAIT, operand_count = 1, ops = {op_gpr32(dst), {}, {}, {}} }, 2444) } emit_umwait_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32) { append(instructions, inst_umwait_r32(dst)) } -inst_movdiri_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIRI, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2421) } -inst_movdiri_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIRI, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2422) } +inst_movdiri_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIRI, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2445) } +inst_movdiri_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIRI, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2446) } emit_movdiri_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_movdiri_m32_r32(dst, src)) } emit_movdiri_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_movdiri_m64_r64(dst, src)) } -inst_movdir64b_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIR64B, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2423) } +inst_movdir64b_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .MOVDIR64B, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2447) } emit_movdir64b_r64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem512) { append(instructions, inst_movdir64b_r64_m512(dst, src)) } -inst_enqcmd_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .ENQCMD, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2424) } +inst_enqcmd_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .ENQCMD, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2448) } emit_enqcmd_r64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem512) { append(instructions, inst_enqcmd_r64_m512(dst, src)) } -inst_enqcmds_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .ENQCMDS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2425) } +inst_enqcmds_r64_m512 :: #force_inline proc "contextless" (dst: GPR64, src: Mem512) -> Instruction { return with_hint(Instruction{ mnemonic = .ENQCMDS, operand_count = 2, ops = {op_gpr64(dst), op_mem(src.mem, 64), {}, {}} }, 2449) } emit_enqcmds_r64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: Mem512) { append(instructions, inst_enqcmds_r64_m512(dst, src)) } -inst_aadd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AADD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2426) } -inst_aadd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AADD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2427) } +inst_aadd_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AADD, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2450) } +inst_aadd_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AADD, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2451) } emit_aadd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_aadd_m32_r32(dst, src)) } emit_aadd_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_aadd_m64_r64(dst, src)) } -inst_aand_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AAND, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2428) } -inst_aand_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AAND, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2429) } +inst_aand_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AAND, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2452) } +inst_aand_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AAND, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2453) } emit_aand_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_aand_m32_r32(dst, src)) } emit_aand_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_aand_m64_r64(dst, src)) } -inst_aor_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AOR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2430) } -inst_aor_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AOR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2431) } +inst_aor_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AOR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2454) } +inst_aor_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AOR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2455) } emit_aor_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_aor_m32_r32(dst, src)) } emit_aor_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_aor_m64_r64(dst, src)) } -inst_axor_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AXOR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2432) } -inst_axor_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AXOR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2433) } +inst_axor_m32_r32 :: #force_inline proc "contextless" (dst: Mem32, src: GPR32) -> Instruction { return with_hint(Instruction{ mnemonic = .AXOR, operand_count = 2, ops = {op_mem(dst.mem, 4), op_gpr32(src), {}, {}} }, 2456) } +inst_axor_m64_r64 :: #force_inline proc "contextless" (dst: Mem64, src: GPR64) -> Instruction { return with_hint(Instruction{ mnemonic = .AXOR, operand_count = 2, ops = {op_mem(dst.mem, 8), op_gpr64(src), {}, {}} }, 2457) } emit_axor_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { append(instructions, inst_axor_m32_r32(dst, src)) } emit_axor_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { append(instructions, inst_axor_m64_r64(dst, src)) } -inst_xend_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XEND, operand_count = 0, ops = {{}, {}, {}, {}} }, 2434) } +inst_xend_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XEND, operand_count = 0, ops = {{}, {}, {}, {}} }, 2458) } emit_xend_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xend_none()) } -inst_xtest_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XTEST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2435) } +inst_xtest_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .XTEST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2459) } emit_xtest_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xtest_none()) } -inst_vmrun_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMRUN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2436) } +inst_vmrun_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMRUN, operand_count = 0, ops = {{}, {}, {}, {}} }, 2460) } emit_vmrun_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmrun_none()) } -inst_vmmcall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMMCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 2437) } +inst_vmmcall_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMMCALL, operand_count = 0, ops = {{}, {}, {}, {}} }, 2461) } emit_vmmcall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmmcall_none()) } -inst_vmload_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMLOAD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2438) } +inst_vmload_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMLOAD, operand_count = 0, ops = {{}, {}, {}, {}} }, 2462) } emit_vmload_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmload_none()) } -inst_vmsave_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMSAVE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2439) } +inst_vmsave_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .VMSAVE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2463) } emit_vmsave_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vmsave_none()) } -inst_stgi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STGI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2440) } +inst_stgi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .STGI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2464) } emit_stgi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_stgi_none()) } -inst_clgi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLGI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2441) } +inst_clgi_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLGI, operand_count = 0, ops = {{}, {}, {}, {}} }, 2465) } emit_clgi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clgi_none()) } -inst_skinit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SKINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2442) } +inst_skinit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .SKINIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2466) } emit_skinit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_skinit_none()) } -inst_invlpga_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPGA, operand_count = 0, ops = {{}, {}, {}, {}} }, 2443) } +inst_invlpga_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPGA, operand_count = 0, ops = {{}, {}, {}, {}} }, 2467) } emit_invlpga_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_invlpga_none()) } -inst_invlpgb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPGB, operand_count = 0, ops = {{}, {}, {}, {}} }, 2444) } +inst_invlpgb_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .INVLPGB, operand_count = 0, ops = {{}, {}, {}, {}} }, 2468) } emit_invlpgb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_invlpgb_none()) } -inst_tlbsync_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .TLBSYNC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2445) } +inst_tlbsync_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .TLBSYNC, operand_count = 0, ops = {{}, {}, {}, {}} }, 2469) } emit_tlbsync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbsync_none()) } -inst_pvalidate_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PVALIDATE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2446) } +inst_pvalidate_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PVALIDATE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2470) } emit_pvalidate_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pvalidate_none()) } -inst_rmpadjust_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RMPADJUST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2447) } +inst_rmpadjust_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RMPADJUST, operand_count = 0, ops = {{}, {}, {}, {}} }, 2471) } emit_rmpadjust_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rmpadjust_none()) } -inst_rmpupdate_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RMPUPDATE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2448) } +inst_rmpupdate_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RMPUPDATE, operand_count = 0, ops = {{}, {}, {}, {}} }, 2472) } emit_rmpupdate_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rmpupdate_none()) } -inst_psmash_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PSMASH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2449) } +inst_psmash_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .PSMASH, operand_count = 0, ops = {{}, {}, {}, {}} }, 2473) } emit_psmash_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psmash_none()) } -inst_clzero_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLZERO, operand_count = 0, ops = {{}, {}, {}, {}} }, 2450) } +inst_clzero_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .CLZERO, operand_count = 0, ops = {{}, {}, {}, {}} }, 2474) } emit_clzero_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clzero_none()) } -inst_monitorx_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MONITORX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2451) } +inst_monitorx_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MONITORX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2475) } emit_monitorx_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_monitorx_none()) } -inst_mwaitx_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MWAITX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2452) } +inst_mwaitx_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MWAITX, operand_count = 0, ops = {{}, {}, {}, {}} }, 2476) } emit_mwaitx_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_mwaitx_none()) } -inst_rdpru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2453) } +inst_rdpru_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .RDPRU, operand_count = 0, ops = {{}, {}, {}, {}} }, 2477) } emit_rdpru_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_rdpru_none()) } -inst_mcommit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MCOMMIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2454) } +inst_mcommit_none :: #force_inline proc "contextless" () -> Instruction { return with_hint(Instruction{ mnemonic = .MCOMMIT, operand_count = 0, ops = {{}, {}, {}, {}} }, 2478) } emit_mcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_mcommit_none()) } // ============================================================================= @@ -7876,6 +7912,8 @@ inst_shr :: proc{ inst_shr_r8, inst_shr_m8, inst emit_shr :: proc{ emit_shr_r8, emit_shr_m8, emit_shr_r8_imm8, emit_shr_m8_imm8, emit_shr_r16, emit_shr_m16, emit_shr_r16_imm8, emit_shr_m16_imm8, emit_shr_r32, emit_shr_m32, emit_shr_r32_imm8, emit_shr_m32_imm8, emit_shr_r64, emit_shr_m64, emit_shr_r64_imm8, emit_shr_m64_imm8 } inst_sar :: proc{ inst_sar_r8, inst_sar_m8, inst_sar_r8_imm8, inst_sar_m8_imm8, inst_sar_r16, inst_sar_m16, inst_sar_r16_imm8, inst_sar_m16_imm8, inst_sar_r32, inst_sar_m32, inst_sar_r32_imm8, inst_sar_m32_imm8, inst_sar_r64, inst_sar_m64, inst_sar_r64_imm8, inst_sar_m64_imm8 } emit_sar :: proc{ emit_sar_r8, emit_sar_m8, emit_sar_r8_imm8, emit_sar_m8_imm8, emit_sar_r16, emit_sar_m16, emit_sar_r16_imm8, emit_sar_m16_imm8, emit_sar_r32, emit_sar_m32, emit_sar_r32_imm8, emit_sar_m32_imm8, emit_sar_r64, emit_sar_m64, emit_sar_r64_imm8, emit_sar_m64_imm8 } +inst_sal :: proc{ inst_sal_r8, inst_sal_m8, inst_sal_r8_imm8, inst_sal_m8_imm8, inst_sal_r16, inst_sal_m16, inst_sal_r16_imm8, inst_sal_m16_imm8, inst_sal_r32, inst_sal_m32, inst_sal_r32_imm8, inst_sal_m32_imm8, inst_sal_r64, inst_sal_m64, inst_sal_r64_imm8, inst_sal_m64_imm8 } +emit_sal :: proc{ emit_sal_r8, emit_sal_m8, emit_sal_r8_imm8, emit_sal_m8_imm8, emit_sal_r16, emit_sal_m16, emit_sal_r16_imm8, emit_sal_m16_imm8, emit_sal_r32, emit_sal_m32, emit_sal_r32_imm8, emit_sal_m32_imm8, emit_sal_r64, emit_sal_m64, emit_sal_r64_imm8, emit_sal_m64_imm8 } inst_rol :: proc{ inst_rol_r8, inst_rol_m8, inst_rol_r8_imm8, inst_rol_m8_imm8, inst_rol_r16, inst_rol_m16, inst_rol_r16_imm8, inst_rol_m16_imm8, inst_rol_r32, inst_rol_m32, inst_rol_r32_imm8, inst_rol_m32_imm8, inst_rol_r64, inst_rol_m64, inst_rol_r64_imm8, inst_rol_m64_imm8 } emit_rol :: proc{ emit_rol_r8, emit_rol_m8, emit_rol_r8_imm8, emit_rol_m8_imm8, emit_rol_r16, emit_rol_m16, emit_rol_r16_imm8, emit_rol_m16_imm8, emit_rol_r32, emit_rol_m32, emit_rol_r32_imm8, emit_rol_m32_imm8, emit_rol_r64, emit_rol_m64, emit_rol_r64_imm8, emit_rol_m64_imm8 } inst_ror :: proc{ inst_ror_r8, inst_ror_m8, inst_ror_r8_imm8, inst_ror_m8_imm8, inst_ror_r16, inst_ror_m16, inst_ror_r16_imm8, inst_ror_m16_imm8, inst_ror_r32, inst_ror_m32, inst_ror_r32_imm8, inst_ror_m32_imm8, inst_ror_r64, inst_ror_m64, inst_ror_r64_imm8, inst_ror_m64_imm8 } @@ -10230,6 +10268,10 @@ inst_serialize :: inst_serialize_none emit_serialize :: emit_serialize_none inst_prefetch :: inst_prefetch_m8 emit_prefetch :: emit_prefetch_m8 +inst_in :: inst_in_imm8 +emit_in :: emit_in_imm8 +inst_out :: inst_out_imm8 +emit_out :: emit_out_imm8 inst_tpause :: inst_tpause_r32 emit_tpause :: emit_tpause_r32 inst_umonitor :: inst_umonitor_r64 @@ -10294,3 +10336,6 @@ inst_rdpru :: inst_rdpru_none emit_rdpru :: emit_rdpru_none inst_mcommit :: inst_mcommit_none emit_mcommit :: emit_mcommit_none + +// The ENCODE_RUNS layout these hints were generated against โ€” see the note in the generator. +BUILDER_TABLE_FINGERPRINT :: u64(0xecfb0a3d7397cdbe) diff --git a/core/rexcode/isa/x86/tests/test.odin b/core/rexcode/isa/x86/tests/test.odin index 7a2a702ac..5bf116daa 100644 --- a/core/rexcode/isa/x86/tests/test.odin +++ b/core/rexcode/isa/x86/tests/test.odin @@ -3204,7 +3204,44 @@ tb_check :: proc(name: string, typed, generic: x86.Instruction) { } } +/* THE BUILDERS AND THE TABLES MUST BE THE SAME GENERATION. + + `run_typed_builder_tests` below compares a HAND-LISTED sample of typed builders against the matcher + path, which is the right shape of check and covers about forty of 3820 builders. CALL r/m64 is not + among them โ€” so when `9ae9a9bf9` shifted the encode table without regenerating the builders, its + baked hint 495 came to name JPE's `0F 8A` and this suite stayed green while every indirect call in + every JIT compiled to a conditional jump. + + This closes it for ALL of them at once. A baked hint is valid exactly when it lands inside its own + mnemonic's run, so the whole invariant is a function of ENCODE_RUNS; the generator records a + fingerprint of the runs it generated against, and this compares it to the live table. Regenerating + the builders is what makes them agree again โ€” one command, printed here so nobody has to find it. */ +run_builder_generation_test :: proc() { + fingerprint := u64(0xcbf2_9ce4_8422_2325) + for m in x86.Mnemonic { + r := x86.ENCODE_RUNS[m] + for part in ([2]u64{u64(r.start), u64(r.count)}) { + for shift: uint = 0; shift < 64; shift += 8 { + fingerprint = (fingerprint ~ ((part >> shift) & 0xff)) * 0x0000_0100_0000_01b3 + } + } + } + if fingerprint == x86.BUILDER_TABLE_FINGERPRINT { + g_stats.passed += 1 + g_stats.cases_validated += 1 + return + } + g_stats.failed += 1 + fmt.printf(" %sFAIL%s mnemonic_builders.odin is STALE: it bakes form indices for an ENCODE_RUNS\n", RED, RESET) + fmt.printf(" layout of %016x, but the loaded tables are %016x. Every builder past the\n", + x86.BUILDER_TABLE_FINGERPRINT, fingerprint) + fmt.printf(" first inserted form now names another mnemonic's encoding. Regenerate:\n") + fmt.printf(" odin run core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin -file\n") +} + run_typed_builder_tests :: proc() { + run_builder_generation_test() + md8 := x86.mem_base_disp(x86.RBP, -16) md32 := x86.mem_base_disp(x86.RCX, 100000) mbi := x86.mem_base_index_disp(x86.R8, x86.RDX, 4, 32) diff --git a/core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin b/core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin index ea0820a06..bd266bae7 100644 --- a/core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/x86/tools/gen_mnemonic_builders.odin @@ -214,6 +214,31 @@ main :: proc() { } + /* THE TABLE THIS FILE WAS GENERATED AGAINST, as a fingerprint over ENCODE_RUNS. + + Every builder below bakes an ABSOLUTE index into ENCODE_FORMS. Whether that index is still + right depends on exactly one thing โ€” the (start, count) run of its mnemonic โ€” so hashing the + runs captures the whole invariant: if this fingerprint still matches the live table, every + baked hint is still inside its own mnemonic's forms; if it does not, this file is stale and + every builder after the first inserted form names someone else's instruction. + + It has gone stale twice, silently, because nothing compared the two halves: `6e17e7a2d` left + 2130 of 3671 builders pointing at the wrong form, and after `36af73834` regenerated both, + `baae2636b` and `9ae9a9bf9` re-broke 37 and then 3393 of 3802 โ€” the latter including CALL, + whose r/m64 builder encoded `0F 8A` (JPE) instead of `FF /2`, turning every indirect call + into a conditional jump. `tests/test.odin` checks this constant. */ + fingerprint := u64(0xcbf2_9ce4_8422_2325) + for m in x86.Mnemonic { + r := x86.ENCODE_RUNS[m] + for part in ([2]u64{u64(r.start), u64(r.count)}) { + for shift: uint = 0; shift < 64; shift += 8 { + fingerprint = (fingerprint ~ ((part >> shift) & 0xff)) * 0x0000_0100_0000_01b3 + } + } + } + strings.write_string(&sb, "\n// The ENCODE_RUNS layout these hints were generated against โ€” see the note in the generator.\n") + strings.write_string(&sb, fmt.tprintf("BUILDER_TABLE_FINGERPRINT :: u64(0x%016x)\n", fingerprint)) + output := strings.to_string(sb) err := os.write_entire_file(#directory + "/../mnemonic_builders.odin", transmute([]u8)strings.concatenate({GEN_ATTRIB, output})) From 5bc545cd977323455c70a8cb82e41e2231678a51 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fl=C4=81vius?= Date: Fri, 28 Aug 2026 16:23:17 -0400 Subject: [PATCH 43/89] x86: the decoder's choice of mnemonic is declared, not emergent Two defects, one shape: something the decoder must decide was never stated, so it fell out of where an entry landed in an unstably sorted table. CANONICITY. Several mnemonics name one encoding -- SHL and SAL are both /4, JE and JZ are both 0x74. Decoding a representative of each and diffing against llvm-mc: 74 patterns, 22 agreed, 52 did not (0F 84 -> JZ where llvm-mc says JE, A4 -> MOVS vs MOVSB, DB E2 -> FCLEX vs FNCLEX). aliases.odin now declares 57 {alias, canonical} rows, each canonical name MEASURED from llvm-mc rather than picked, and gen.odin drops an aliased entry as it collects decode entries -- so the name never reaches the tables. The drop is conditional on the canonical name covering the byte-identical encoding, which is what lets MOV be the alias at the A0-A3/B8 moffs forms while staying the only name for 88/89. Aliases stay fully encodable; only decoding narrows. 119 of 1350 legacy entries dropped, 74 of 74 now agree. This also fixes the four SAL/SHL failures left by the previous commit, at their root rather than by extending a hand-written list. ADDRESS SIZE. 0xE3's mnemonic is chosen by which counter register it tests -- the 67h axis -- and REX.W does not affect address size at all. Modelling JRCXZ as force_rex_w made its encoding 48 E3 cb where llvm-mc emits a bare E3 cb, gave JECXZ the bare encoding that is really JRCXZ in long mode, and left three indistinguishable entries. Encoding_Flags gains addr_size (2 of 6 spare bits); the matcher refuses a form the mode cannot express, the encoder emits 67h when it differs from the default, the decoder selects on it before the operand-size pass. All ten cases match llvm-mc, refusals included. The tests keep no second copy of the alias table: mnemonics_eq compares canonical_mnemonic, and run_alias_table_test asserts the stronger property the generator guarantees -- zero encodings spelled by two surviving mnemonics. It caught the E3 ambiguity on its own. Also fixed: gen.odin's write_flags enumerates Encoding_Flags by hand and silently dropped addr_size from the generated tables -- the flag read back as its zero value and the instruction was quietly mis-modelled. 271 passed. Bites: dropping {.SAL, .SHL} returns the prime_sieve failure and the guard names every shift-group opcode; restoring force_rex_w decodes E3 00 as JCXZ and encodes JRCXZ to three bytes. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz --- core/rexcode/isa/x86/aliases.odin | 130 ++ core/rexcode/isa/x86/decoder.odin | 15 + core/rexcode/isa/x86/encoder.odin | 31 +- core/rexcode/isa/x86/encoding_types.odin | 49 +- core/rexcode/isa/x86/tablegen/gen.odin | 76 + .../x86/tablegen/generated/decode_tables.odin | 1459 ++++++++--------- .../x86/tablegen/generated/encode_tables.odin | 6 +- .../isa/x86/tablegen/instruction_table.odin | 12 +- .../isa/x86/tables/x86.encode_forms.bin | Bin 39648 -> 39648 bytes .../isa/x86/tables/x86.encode_recipes.bin | Bin 29736 -> 29736 bytes core/rexcode/isa/x86/tables/x86.evex.bin | Bin 8420 -> 8420 bytes core/rexcode/isa/x86/tables/x86.idx_0f.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f38.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.idx_0f3a.bin | Bin 4096 -> 4096 bytes .../rexcode/isa/x86/tables/x86.idx_legacy.bin | Bin 4096 -> 4096 bytes core/rexcode/isa/x86/tables/x86.legacy.bin | Bin 27000 -> 24620 bytes core/rexcode/isa/x86/tables/x86.vex.bin | Bin 14140 -> 14140 bytes core/rexcode/isa/x86/tests/test.odin | 218 ++- 18 files changed, 1171 insertions(+), 825 deletions(-) create mode 100644 core/rexcode/isa/x86/aliases.odin diff --git a/core/rexcode/isa/x86/aliases.odin b/core/rexcode/isa/x86/aliases.odin new file mode 100644 index 000000000..42c8077a4 --- /dev/null +++ b/core/rexcode/isa/x86/aliases.odin @@ -0,0 +1,130 @@ +// rexcode ยท Brendan Punsky (dotbmp@github), original author + +package rexcode_x86 + +// ============================================================================= +// MNEMONIC ALIASES โ€” which of several names for one encoding a disassembler prints +// ============================================================================= +// +// Some x86 instructions have several legal mnemonics for ONE encoding. SHL and +// SAL are both ModRM.reg=4 in the shift group; JE and JZ are both 0x74; there +// are 57 such pairs. A decoder has nothing to tell them apart with โ€” the bytes +// are identical โ€” so it must simply pick a name, and that choice has to be +// DECLARED. Left undeclared it falls out of wherever the entry happened to land +// in the (unstably sorted) decode table: correct, arbitrary, and free to move on +// any table regeneration. It did move once, and four tests that had always +// passed began reporting `SAL != expected SHL`. +// +// The canonical name here is the one **llvm-mc prints**, measured rather than +// chosen: llvm-mc is the ground truth every verifier in this library diffs +// against, so agreeing with it is what makes a disassembly comparable. Before +// this table, 52 of the 74 aliased encodings decoded to a name llvm-mc does not +// use (`0F 84` โ†’ JZ where it says JE, `A4` โ†’ MOVS where it says MOVSB, `DB E2` โ†’ +// FCLEX where it says FNCLEX). +// +// An alias stays fully ENCODABLE โ€” `inst_r_r(.SAL, โ€ฆ)` emits the same bytes it +// always did. Only the decode direction is narrowed, and only where the +// canonical name covers the byte-identical encoding: that condition is what lets +// MOV be the alias at the `A0`-`A3`/`B8` moffs forms while remaining the only +// name for `88`/`89`. `tablegen/gen.odin` applies it when it collects decode +// entries, so an aliased mnemonic never reaches the decode tables at all. +// +// Adding an instruction whose mnemonic aliases another one's encoding requires a +// row here; `run_alias_table_test` in tests/ recomputes the ambiguity from the +// built tables and fails by name if one is missing, so it cannot be forgotten. + +Mnemonic_Alias :: struct { + alias: Mnemonic, // never produced by the decoder + canonical: Mnemonic, // produced instead, at the byte-identical encoding +} + +@(rodata) +MNEMONIC_ALIASES := [?]Mnemonic_Alias{ + // -- Jcc, both the short 0x7x and near 0x0F 8x forms -------------------- + {.JNAE, .JB}, {.JC, .JB}, + {.JNB, .JAE}, {.JNC, .JAE}, + {.JZ, .JE}, + {.JNZ, .JNE}, + {.JNA, .JBE}, + {.JNBE, .JA}, + {.JPE, .JP}, + {.JPO, .JNP}, + {.JNGE, .JL}, + {.JNL, .JGE}, + {.JNG, .JLE}, + {.JNLE, .JG}, + + // -- CMOVcc (0x0F 4x) --------------------------------------------------- + {.CMOVNAE, .CMOVB}, {.CMOVC, .CMOVB}, + {.CMOVNB, .CMOVAE}, {.CMOVNC, .CMOVAE}, + {.CMOVZ, .CMOVE}, + {.CMOVNZ, .CMOVNE}, + {.CMOVNA, .CMOVBE}, + {.CMOVNBE, .CMOVA}, + {.CMOVPE, .CMOVP}, + {.CMOVPO, .CMOVNP}, + {.CMOVNGE, .CMOVL}, + {.CMOVNL, .CMOVGE}, + {.CMOVNG, .CMOVLE}, + {.CMOVNLE, .CMOVG}, + + // -- SETcc (0x0F 9x) ---------------------------------------------------- + {.SETNAE, .SETB}, {.SETC, .SETB}, + {.SETNB, .SETAE}, {.SETNC, .SETAE}, + {.SETZ, .SETE}, + {.SETNZ, .SETNE}, + {.SETNA, .SETBE}, + {.SETNBE, .SETA}, + {.SETPE, .SETP}, + {.SETPO, .SETNP}, + {.SETNGE, .SETL}, + {.SETNL, .SETGE}, + {.SETNG, .SETLE}, + {.SETNLE, .SETG}, + + // -- Shift group: SAL and SHL are both /4, the same encoding ------------ + {.SAL, .SHL}, + + // -- String ops: the bare name against the explicitly byte-sized one ---- + {.CMPS, .CMPSB}, + {.LODS, .LODSB}, + {.MOVS, .MOVSB}, + {.SCAS, .SCASB}, + {.STOS, .STOSB}, + + // -- x87: the assembler's wait-prefixed spelling of a no-wait opcode ---- + // (FSTENV is really `9B D9 /6`; the table gives it the bare `D9 /6`, which + // is FNSTENV. Modelling the 9B prefix is a separate question โ€” until then + // the bare encoding decodes as the no-wait name, which is what it is.) + {.FCLEX, .FNCLEX}, + {.FINIT, .FNINIT}, + {.FSAVE, .FNSAVE}, + {.FSTCW, .FNSTCW}, + {.FSTENV, .FNSTENV}, + {.FSTSW, .FNSTSW}, + + // -- Odds -------------------------------------------------------------- + {.FWAIT, .WAIT}, + {.XLAT, .XLATB}, + // MOV aliases MOVABS only at the moffs (`A0`-`A3`) and imm64 (`B8+r`) + // forms; the coverage rule leaves every other MOV encoding untouched. + {.MOV, .MOVABS}, +} + +// The name a disassembler prints for `m`'s encoding โ€” `m` itself unless it is a +// declared alias. Useful to an assembler front-end that accepts either spelling +// and wants to compare against decoder output. +canonical_mnemonic :: proc "contextless" (m: Mnemonic) -> Mnemonic { + for entry in MNEMONIC_ALIASES { + if entry.alias == m { return entry.canonical } + } + return m +} + +// Is `m` a name the decoder never produces? +is_mnemonic_alias :: proc "contextless" (m: Mnemonic) -> bool { + for entry in MNEMONIC_ALIASES { + if entry.alias == m { return true } + } + return false +} diff --git a/core/rexcode/isa/x86/decoder.odin b/core/rexcode/isa/x86/decoder.odin index e883944ab..69127337f 100644 --- a/core/rexcode/isa/x86/decoder.odin +++ b/core/rexcode/isa/x86/decoder.odin @@ -565,6 +565,21 @@ decode_opcode :: proc(state: ^Decoder_State) -> (entry: ^Decode_Entry, vex_entry } if !has_modrm_byte { + // ADDRESS-size variants first: a form declaring one is picked by which + // address size is in effect (mode default vs 67h), an axis the operand- + // size scan below cannot see -- it reads REX.W and 66h, and neither + // affects address size. 0xE3 is the case: JRCXZ/JECXZ/JCXZ are one + // opcode telling RCX/ECX/CX apart, and nothing else in the bytes says + // which. Checked before the operand-size pass so a REX.W-prefixed E3 + // (legal, and ignored by the CPU for address size) still reads as JRCXZ. + addr_want := effective_addr_size(state.mode, state.prefix_67) + for i in 0.. FS, // 0F A8/A9 -> GS), so a form only matches when the user's segment agrees -- // otherwise `push gs` would take the first {SREG} form (FS) and mis-encode. diff --git a/core/rexcode/isa/x86/encoding_types.odin b/core/rexcode/isa/x86/encoding_types.odin index d4958d284..c756f65c7 100644 --- a/core/rexcode/isa/x86/encoding_types.odin +++ b/core/rexcode/isa/x86/encoding_types.odin @@ -241,6 +241,48 @@ VEX_L :: enum u8 { L2, // L = 2 (512-bit, EVEX only) } +/* + The ADDRESS size a form requires -- a different axis from operand size (66h / + REX.W), selected by 67h against the mode's default: 64-bit in long mode and + 32-bit under 67h; 32-bit in protected mode and 16-bit under 67h. + + Almost every instruction is DEFAULT (it works at whatever address size is in + effect). It matters where address size picks the MNEMONIC: 0xE3 is JRCXZ, + JECXZ or JCXZ purely by which counter register it tests, and nothing else in + the encoding says which. Modelling that as REX.W (which does not affect + address size at all) made `48 E3 cb` the encoding of JRCXZ, where the correct + one is a bare `E3 cb`, and left the decoder unable to tell the three apart. +*/ +Addr_Size :: enum u8 { + DEFAULT, // whatever the mode/prefix selects; the form does not care + A16, // 16-bit addressing (CX) + A32, // 32-bit addressing (ECX) + A64, // 64-bit addressing (RCX); long mode only +} + +// The address size in effect for `mode` with/without a 67h override. +effective_addr_size :: #force_inline proc "contextless" (mode: Mode, prefix_67: bool) -> Addr_Size { + if mode == ._64 { + return prefix_67 ? .A32 : .A64 + } + return prefix_67 ? .A16 : .A32 +} + +// Does reaching `want` in `mode` require a 67h prefix, and is it reachable at all? +addr_size_prefix :: #force_inline proc "contextless" (want: Addr_Size, mode: Mode) -> (prefix_67: bool, ok: bool) { + if want == .DEFAULT { + return false, true + } + if want == effective_addr_size(mode, false) { + return false, true + } + if want == effective_addr_size(mode, true) { + return true, true + } + // e.g. JCXZ (A16) in long mode: 67h there gives 32-bit, never 16-bit. + return false, false +} + // ----------------------------------------------------------------------------- // SECTION: 6.5 Encoding Flags // ----------------------------------------------------------------------------- @@ -259,6 +301,7 @@ Encoding_Flags :: bit_field u32 { rep_ok: bool | 1, // REP prefix valid modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field) mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F) + addr_size: Addr_Size | 2, // required ADDRESS size (67h axis); selects JCXZ/JECXZ/JRCXZ explicit_count: u8 | 3, // 0..<4 non-implicit operands has_implicit: bool | 1, // any implicit operand @@ -302,8 +345,9 @@ encoding_flags :: #force_inline proc "contextless" ( no_rex: bool = false, lock_ok: bool = false, rep_ok: bool = false, - modrm_reg_ext: bool = false, - mode_32_only: bool = false, + modrm_reg_ext: bool = false, + mode_32_only: bool = false, + addr_size: Addr_Size = .DEFAULT, ) -> Encoding_Flags { return Encoding_Flags{ esc = esc, @@ -319,6 +363,7 @@ encoding_flags :: #force_inline proc "contextless" ( rep_ok = rep_ok, modrm_reg_ext = modrm_reg_ext, mode_32_only = mode_32_only, + addr_size = addr_size, } } diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 41346c4ff..7b8b47275 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -267,6 +267,9 @@ emit_decode_tables :: proc() -> (n_legacy, n_vex, n_evex: int) { } } } + drop_aliased(&legacy) + drop_aliased(&vex) + drop_aliased(&evex) slice.sort_by(legacy[:], entry_less) slice.sort_by(vex[:], entry_less) slice.sort_by(evex[:], entry_less) @@ -290,6 +293,73 @@ emit_decode_tables :: proc() -> (n_legacy, n_vex, n_evex: int) { return len(legacy), len(vex), len(evex) } +/* + Several mnemonics can name ONE encoding (SHL and SAL are both /4 in the shift + group; JE and JZ are both 0x74). The decoder reads bytes, so it cannot tell + them apart and must simply print one name -- which means the choice has to be + declared, or it falls out of wherever the entry lands in the sort below. + + lib.MNEMONIC_ALIASES declares it. An alias entry is dropped here, before the + tables are written, so the name never reaches the decoder at all; it stays + fully encodable, since ENCODE_FORMS is built from the same table separately. + + The drop is CONDITIONAL on the canonical name covering the byte-identical + encoding. That is what keeps the rule safe for a mnemonic that is an alias at + one opcode and the only name at another: MOV aliases MOVABS at the `A0`-`A3` + moffs and `B8+r` imm64 forms, and dropping it unconditionally would leave + `88`/`89` -- ordinary register MOV -- with no decode entry at all. +*/ +drop_aliased :: proc(entries: ^[dynamic]Collected_Entry) { + Key :: struct { + esc: lib.Escape, + prefix: u8, + opcode: u8, + ext: u8, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + flags: lib.Encoding_Flags, + vex_w: lib.VEX_W, + vex_l: lib.VEX_L, + } + key_of :: proc(e: Collected_Entry) -> Key { + return Key{e.esc, e.prefix, e.opcode, e.ext, e.ops, e.enc, e.flags, e.vex_w, e.vex_l} + } + /* Which mnemonics each indistinguishable encoding is spelled by. */ + names := make(map[Key][dynamic]lib.Mnemonic) + defer { + for _, list in names { delete(list) } + delete(names) + } + for e in entries { + key := key_of(e) + list, present := &names[key] + if !present { + names[key] = make([dynamic]lib.Mnemonic) + list = &names[key] + } + append(list, e.mnemonic) + } + + kept := 0 + for e in entries { + drop := false + for entry in lib.MNEMONIC_ALIASES { + if entry.alias != e.mnemonic { continue } + for spelling in names[key_of(e)] { + if spelling == entry.canonical { + drop = true + break + } + } + if drop { break } + } + if drop { continue } + entries[kept] = e + kept += 1 + } + resize(entries, kept) +} + entry_less :: proc(a, b: Collected_Entry) -> bool { if a.esc != b.esc { return int(a.esc) < int(b.esc) } if a.prefix != b.prefix { return a.prefix < b.prefix } @@ -470,6 +540,12 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent if flags.rep_ok { append(&parts, "rep_ok=true") } if flags.modrm_reg_ext { append(&parts, "modrm_reg_ext=true") } if flags.mode_32_only { append(&parts, "mode_32_only=true") } + if flags.addr_size != .DEFAULT { append(&parts, fmt.tprintf("addr_size=.%v", flags.addr_size)) } + /* EVERY Encoding_Flags field must be listed above. This enumerates the + struct by hand, so a field added there and forgotten here is silently + dropped from the generated tables -- the flag reads back as its zero value + and the instruction is quietly mis-modelled, with nothing to see in the + diff but its absence. `addr_size` was added and did exactly that. */ switch e in enc { case lib.Encoding: diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 7dec7ce02..9e62a84bb 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -144,27 +144,27 @@ SIB_TABLE := [256]lib.SIB_Info{ } @(rodata) -LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ +LEGACY_DECODE_ENTRIES := [1231]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, @@ -182,115 +182,101 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, - {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, - {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, + {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -301,60 +287,60 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x80, 0x06, .XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x07, .CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x88, 0xFF, .MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x89, 0xFF, .MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -369,71 +355,57 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x8D, 0xFF, .LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8D, 0xFF, .LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8D, 0xFF, .LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, + {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA0, 0xFF, .MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xA2, 0xFF, .MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA2, 0xFF, .MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, @@ -442,119 +414,105 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xB8, 0xFF, .MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xC0, 0x00, .ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x01, .ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC0, 0x04, .SAL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xC3, 0xFF, .RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC7, 0x00, .MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC7, 0x00, .MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC8, 0xFF, .ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xC9, 0xFF, .LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCC, 0xFF, .INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD0, 0x04, .SAL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x05, .SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x05, .SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x07, .SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x00, .ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD2, 0x04, .SAL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x07, .SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x07, .SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD7, 0xFF, .XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD7, 0xFF, .XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD8, 0x01, .FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD8, 0x02, .FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD8, 0x03, .FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -578,8 +536,6 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xC0, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xC8, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -611,8 +567,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFC, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFD, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFE, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -635,10 +591,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDB, 0xC8, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD0, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD8, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xDB, 0xE2, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE2, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE3, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xE3, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE8, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xF0, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, @@ -661,8 +615,6 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0xC0, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD0, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -702,22 +654,21 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDF, 0xC0, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE0, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xDF, 0xE0, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE8, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xF0, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true, op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A64, op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A16, op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A32, op_count=1}}, {.NONE, 0, 0xE4, 0xFF, .IN, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xE5, 0xFF, .IN, {.EAX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xE5, 0xFF, .IN, {.AX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE6, 0xFF, .OUT, {.IMM8, .AL_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .AX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .EAX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .AX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE8, 0xFF, .CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -737,18 +688,18 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xF6, 0x05, .IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF6, 0x06, .DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF6, 0x07, .IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x00, .TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x00, .TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x02, .NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x03, .NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x03, .NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x04, .MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x04, .MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -766,16 +717,16 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xFD, 0xFF, .STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFE, 0x00, .INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFE, 0x01, .DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x00, .INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -784,11 +735,11 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -797,8 +748,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -842,8 +793,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x01, 0xFE, .INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -857,22 +808,22 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -888,96 +839,54 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x33, 0xFF, .RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x34, 0xFF, .SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x35, 0xFF, .SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1004,88 +913,60 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x89, 0xFF, .JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8A, 0xFF, .JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8A, 0xFF, .JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8B, 0xFF, .JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8B, 0xFF, .JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8C, 0xFF, .JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x94, 0xFF, .SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x94, 0xFF, .SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x95, 0xFF, .SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x95, 0xFF, .SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x96, 0xFF, .SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x96, 0xFF, .SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x97, 0xFF, .SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9C, 0xFF, .SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9D, 0xFF, .SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9D, 0xFF, .SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9E, 0xFF, .SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9E, 0xFF, .SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9F, 0xFF, .SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9F, 0xFF, .SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0xA0, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA1, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA2, 0xFF, .CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xA3, 0xFF, .BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xA3, 0xFF, .BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xAA, 0xFF, .RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1094,8 +975,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0xE8, .LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xAE, 0xF0, .MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -1105,65 +986,65 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1209,8 +1090,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -1226,8 +1107,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1235,8 +1116,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC7, 0x06, .VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xD0, 0xFF, .ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1297,16 +1178,16 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0xFA, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x1E, 0xFB, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x52, 0xFF, .RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x53, 0xFF, .RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, @@ -1326,25 +1207,25 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 2, 0xAE, 0x00, .RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xC7, 0x07, .RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1354,8 +1235,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 3, 0x10, 0xFF, .MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x11, 0xFF, .MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1385,9 +1266,9 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, @@ -1442,8 +1323,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 1, 0x41, 0xFF, .PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x80, 0xFF, .INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x81, 0xFF, .INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDB, 0xFF, .AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDC, 0xFF, .AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, @@ -1463,9 +1344,9 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF8, 0xFF, .ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xFC, 0xFF, .AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xFC, 0xFF, .AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, @@ -2696,119 +2577,119 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ 0x6B = { 114, 3}, 0x70 = { 117, 1}, 0x71 = { 118, 1}, - 0x72 = { 119, 3}, - 0x73 = { 122, 3}, - 0x74 = { 125, 2}, - 0x75 = { 127, 2}, - 0x76 = { 129, 2}, - 0x77 = { 131, 2}, - 0x78 = { 133, 1}, - 0x79 = { 134, 1}, - 0x7A = { 135, 2}, - 0x7B = { 137, 2}, - 0x7C = { 139, 2}, - 0x7D = { 141, 2}, - 0x7E = { 143, 2}, - 0x7F = { 145, 2}, - 0x80 = { 147, 8}, - 0x81 = { 155, 24}, - 0x83 = { 179, 24}, - 0x84 = { 203, 1}, - 0x85 = { 204, 3}, - 0x86 = { 207, 1}, - 0x87 = { 208, 3}, - 0x88 = { 211, 1}, - 0x89 = { 212, 3}, - 0x8A = { 215, 1}, - 0x8B = { 216, 3}, - 0x8C = { 219, 2}, - 0x8D = { 221, 3}, - 0x8E = { 224, 2}, - 0x8F = { 226, 2}, - 0x90 = { 228, 4}, - 0x98 = { 232, 3}, - 0x99 = { 235, 3}, - 0x9B = { 238, 2}, - 0x9C = { 240, 3}, - 0x9D = { 243, 3}, - 0x9E = { 246, 1}, - 0x9F = { 247, 1}, - 0xA0 = { 248, 2}, - 0xA1 = { 250, 6}, - 0xA2 = { 256, 2}, - 0xA3 = { 258, 6}, - 0xA4 = { 264, 2}, - 0xA5 = { 266, 3}, - 0xA6 = { 269, 2}, - 0xA7 = { 271, 3}, - 0xA8 = { 274, 1}, - 0xA9 = { 275, 3}, - 0xAA = { 278, 2}, - 0xAB = { 280, 3}, - 0xAC = { 283, 2}, - 0xAD = { 285, 3}, - 0xAE = { 288, 2}, - 0xAF = { 290, 3}, - 0xB0 = { 293, 1}, - 0xB8 = { 294, 4}, - 0xC0 = { 298, 8}, - 0xC1 = { 306, 24}, - 0xC2 = { 330, 1}, - 0xC3 = { 331, 1}, - 0xC6 = { 332, 1}, - 0xC7 = { 333, 3}, - 0xC8 = { 336, 1}, - 0xC9 = { 337, 1}, - 0xCC = { 338, 1}, - 0xCD = { 339, 1}, - 0xCE = { 340, 1}, - 0xCF = { 341, 3}, - 0xD0 = { 344, 8}, - 0xD1 = { 352, 24}, - 0xD2 = { 376, 8}, - 0xD3 = { 384, 24}, - 0xD7 = { 408, 2}, - 0xD8 = { 410, 18}, - 0xD9 = { 428, 40}, - 0xDA = { 468, 13}, - 0xDB = { 481, 16}, - 0xDC = { 497, 14}, - 0xDD = { 511, 16}, - 0xDE = { 527, 21}, - 0xDF = { 548, 13}, - 0xE0 = { 561, 1}, - 0xE1 = { 562, 1}, - 0xE2 = { 563, 1}, - 0xE3 = { 564, 3}, - 0xE4 = { 567, 1}, - 0xE5 = { 568, 2}, - 0xE6 = { 570, 1}, - 0xE7 = { 571, 2}, - 0xE8 = { 573, 1}, - 0xE9 = { 574, 1}, - 0xEB = { 575, 1}, - 0xEC = { 576, 1}, - 0xED = { 577, 2}, - 0xEE = { 579, 1}, - 0xEF = { 580, 2}, - 0xF0 = { 582, 1}, - 0xF4 = { 583, 1}, - 0xF5 = { 584, 1}, - 0xF6 = { 585, 7}, - 0xF7 = { 592, 21}, - 0xF8 = { 613, 1}, - 0xF9 = { 614, 1}, - 0xFA = { 615, 1}, - 0xFB = { 616, 1}, - 0xFC = { 617, 1}, - 0xFD = { 618, 1}, - 0xFE = { 619, 2}, - 0xFF = { 621, 16}, + 0x72 = { 119, 1}, + 0x73 = { 120, 1}, + 0x74 = { 121, 1}, + 0x75 = { 122, 1}, + 0x76 = { 123, 1}, + 0x77 = { 124, 1}, + 0x78 = { 125, 1}, + 0x79 = { 126, 1}, + 0x7A = { 127, 1}, + 0x7B = { 128, 1}, + 0x7C = { 129, 1}, + 0x7D = { 130, 1}, + 0x7E = { 131, 1}, + 0x7F = { 132, 1}, + 0x80 = { 133, 8}, + 0x81 = { 141, 24}, + 0x83 = { 165, 24}, + 0x84 = { 189, 1}, + 0x85 = { 190, 3}, + 0x86 = { 193, 1}, + 0x87 = { 194, 3}, + 0x88 = { 197, 1}, + 0x89 = { 198, 3}, + 0x8A = { 201, 1}, + 0x8B = { 202, 3}, + 0x8C = { 205, 2}, + 0x8D = { 207, 3}, + 0x8E = { 210, 2}, + 0x8F = { 212, 2}, + 0x90 = { 214, 4}, + 0x98 = { 218, 3}, + 0x99 = { 221, 3}, + 0x9B = { 224, 1}, + 0x9C = { 225, 3}, + 0x9D = { 228, 3}, + 0x9E = { 231, 1}, + 0x9F = { 232, 1}, + 0xA0 = { 233, 1}, + 0xA1 = { 234, 3}, + 0xA2 = { 237, 1}, + 0xA3 = { 238, 3}, + 0xA4 = { 241, 1}, + 0xA5 = { 242, 3}, + 0xA6 = { 245, 1}, + 0xA7 = { 246, 3}, + 0xA8 = { 249, 1}, + 0xA9 = { 250, 3}, + 0xAA = { 253, 1}, + 0xAB = { 254, 3}, + 0xAC = { 257, 1}, + 0xAD = { 258, 3}, + 0xAE = { 261, 1}, + 0xAF = { 262, 3}, + 0xB0 = { 265, 1}, + 0xB8 = { 266, 3}, + 0xC0 = { 269, 7}, + 0xC1 = { 276, 21}, + 0xC2 = { 297, 1}, + 0xC3 = { 298, 1}, + 0xC6 = { 299, 1}, + 0xC7 = { 300, 3}, + 0xC8 = { 303, 1}, + 0xC9 = { 304, 1}, + 0xCC = { 305, 1}, + 0xCD = { 306, 1}, + 0xCE = { 307, 1}, + 0xCF = { 308, 3}, + 0xD0 = { 311, 7}, + 0xD1 = { 318, 21}, + 0xD2 = { 339, 7}, + 0xD3 = { 346, 21}, + 0xD7 = { 367, 1}, + 0xD8 = { 368, 18}, + 0xD9 = { 386, 38}, + 0xDA = { 424, 13}, + 0xDB = { 437, 14}, + 0xDC = { 451, 14}, + 0xDD = { 465, 14}, + 0xDE = { 479, 21}, + 0xDF = { 500, 12}, + 0xE0 = { 512, 1}, + 0xE1 = { 513, 1}, + 0xE2 = { 514, 1}, + 0xE3 = { 515, 3}, + 0xE4 = { 518, 1}, + 0xE5 = { 519, 2}, + 0xE6 = { 521, 1}, + 0xE7 = { 522, 2}, + 0xE8 = { 524, 1}, + 0xE9 = { 525, 1}, + 0xEB = { 526, 1}, + 0xEC = { 527, 1}, + 0xED = { 528, 2}, + 0xEE = { 530, 1}, + 0xEF = { 531, 2}, + 0xF0 = { 533, 1}, + 0xF4 = { 534, 1}, + 0xF5 = { 535, 1}, + 0xF6 = { 536, 7}, + 0xF7 = { 543, 21}, + 0xF8 = { 564, 1}, + 0xF9 = { 565, 1}, + 0xFA = { 566, 1}, + 0xFB = { 567, 1}, + 0xFC = { 568, 1}, + 0xFD = { 569, 1}, + 0xFE = { 570, 2}, + 0xFF = { 572, 16}, }, { // prefix = 66 }, { // prefix = F3 - 0x90 = { 637, 1}, + 0x90 = { 588, 1}, }, { // prefix = F2 }, @@ -2817,434 +2698,434 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ @(rodata) DECODE_INDEX_ESC_0F := [4][256]lib.Decode_Index{ { // prefix = none - 0x00 = { 638, 10}, - 0x01 = { 648, 48}, - 0x02 = { 696, 3}, - 0x03 = { 699, 3}, - 0x05 = { 702, 1}, - 0x06 = { 703, 1}, - 0x07 = { 704, 1}, - 0x08 = { 705, 1}, - 0x09 = { 706, 1}, - 0x0B = { 707, 1}, - 0x0D = { 708, 2}, - 0x10 = { 710, 1}, - 0x11 = { 711, 1}, - 0x12 = { 712, 2}, - 0x13 = { 714, 1}, - 0x14 = { 715, 1}, - 0x15 = { 716, 1}, - 0x16 = { 717, 2}, - 0x17 = { 719, 1}, - 0x18 = { 720, 4}, - 0x1C = { 724, 1}, - 0x1F = { 725, 3}, - 0x20 = { 728, 1}, - 0x21 = { 729, 1}, - 0x22 = { 730, 1}, - 0x23 = { 731, 1}, - 0x28 = { 732, 1}, - 0x29 = { 733, 1}, - 0x2B = { 734, 1}, - 0x2E = { 735, 1}, - 0x2F = { 736, 1}, - 0x30 = { 737, 1}, - 0x31 = { 738, 1}, - 0x32 = { 739, 1}, - 0x33 = { 740, 1}, - 0x34 = { 741, 1}, - 0x35 = { 742, 1}, - 0x40 = { 743, 3}, - 0x41 = { 746, 3}, - 0x42 = { 749, 9}, - 0x43 = { 758, 9}, - 0x44 = { 767, 6}, - 0x45 = { 773, 6}, - 0x46 = { 779, 6}, - 0x47 = { 785, 6}, - 0x48 = { 791, 3}, - 0x49 = { 794, 3}, - 0x4A = { 797, 6}, - 0x4B = { 803, 6}, - 0x4C = { 809, 6}, - 0x4D = { 815, 6}, - 0x4E = { 821, 6}, - 0x4F = { 827, 6}, - 0x50 = { 833, 2}, - 0x51 = { 835, 1}, - 0x52 = { 836, 1}, - 0x53 = { 837, 1}, - 0x54 = { 838, 1}, - 0x55 = { 839, 1}, - 0x56 = { 840, 1}, - 0x57 = { 841, 1}, - 0x58 = { 842, 1}, - 0x59 = { 843, 1}, - 0x5A = { 844, 1}, - 0x5B = { 845, 1}, - 0x5C = { 846, 1}, - 0x5D = { 847, 1}, - 0x5E = { 848, 1}, - 0x5F = { 849, 1}, - 0x6E = { 850, 1}, - 0x6F = { 851, 1}, - 0x70 = { 852, 1}, - 0x78 = { 853, 1}, - 0x79 = { 854, 1}, - 0x7E = { 855, 1}, - 0x7F = { 856, 1}, - 0x80 = { 857, 1}, - 0x81 = { 858, 1}, - 0x82 = { 859, 3}, - 0x83 = { 862, 3}, - 0x84 = { 865, 2}, - 0x85 = { 867, 2}, - 0x86 = { 869, 2}, - 0x87 = { 871, 2}, - 0x88 = { 873, 1}, - 0x89 = { 874, 1}, - 0x8A = { 875, 2}, - 0x8B = { 877, 2}, - 0x8C = { 879, 2}, - 0x8D = { 881, 2}, - 0x8E = { 883, 2}, - 0x8F = { 885, 2}, - 0x90 = { 887, 1}, - 0x91 = { 888, 1}, - 0x92 = { 889, 3}, - 0x93 = { 892, 3}, - 0x94 = { 895, 2}, - 0x95 = { 897, 2}, - 0x96 = { 899, 2}, - 0x97 = { 901, 2}, - 0x98 = { 903, 1}, - 0x99 = { 904, 1}, - 0x9A = { 905, 2}, - 0x9B = { 907, 2}, - 0x9C = { 909, 2}, - 0x9D = { 911, 2}, - 0x9E = { 913, 2}, - 0x9F = { 915, 2}, - 0xA0 = { 917, 1}, - 0xA1 = { 918, 1}, - 0xA2 = { 919, 1}, - 0xA3 = { 920, 3}, - 0xA4 = { 923, 3}, - 0xA5 = { 926, 3}, - 0xA8 = { 929, 1}, - 0xA9 = { 930, 1}, - 0xAA = { 931, 1}, - 0xAB = { 932, 3}, - 0xAC = { 935, 3}, - 0xAD = { 938, 3}, - 0xAE = { 941, 14}, - 0xAF = { 955, 3}, - 0xB0 = { 958, 1}, - 0xB1 = { 959, 3}, - 0xB3 = { 962, 3}, - 0xB6 = { 965, 3}, - 0xB7 = { 968, 2}, - 0xB9 = { 970, 1}, - 0xBA = { 971, 12}, - 0xBB = { 983, 3}, - 0xBC = { 986, 3}, - 0xBD = { 989, 3}, - 0xBE = { 992, 3}, - 0xBF = { 995, 2}, - 0xC0 = { 997, 1}, - 0xC1 = { 998, 3}, - 0xC2 = {1001, 1}, - 0xC6 = {1002, 1}, - 0xC7 = {1003, 16}, - 0xC8 = {1019, 2}, - 0xFF = {1021, 1}, + 0x00 = { 589, 10}, + 0x01 = { 599, 48}, + 0x02 = { 647, 3}, + 0x03 = { 650, 3}, + 0x05 = { 653, 1}, + 0x06 = { 654, 1}, + 0x07 = { 655, 1}, + 0x08 = { 656, 1}, + 0x09 = { 657, 1}, + 0x0B = { 658, 1}, + 0x0D = { 659, 2}, + 0x10 = { 661, 1}, + 0x11 = { 662, 1}, + 0x12 = { 663, 2}, + 0x13 = { 665, 1}, + 0x14 = { 666, 1}, + 0x15 = { 667, 1}, + 0x16 = { 668, 2}, + 0x17 = { 670, 1}, + 0x18 = { 671, 4}, + 0x1C = { 675, 1}, + 0x1F = { 676, 3}, + 0x20 = { 679, 1}, + 0x21 = { 680, 1}, + 0x22 = { 681, 1}, + 0x23 = { 682, 1}, + 0x28 = { 683, 1}, + 0x29 = { 684, 1}, + 0x2B = { 685, 1}, + 0x2E = { 686, 1}, + 0x2F = { 687, 1}, + 0x30 = { 688, 1}, + 0x31 = { 689, 1}, + 0x32 = { 690, 1}, + 0x33 = { 691, 1}, + 0x34 = { 692, 1}, + 0x35 = { 693, 1}, + 0x40 = { 694, 3}, + 0x41 = { 697, 3}, + 0x42 = { 700, 3}, + 0x43 = { 703, 3}, + 0x44 = { 706, 3}, + 0x45 = { 709, 3}, + 0x46 = { 712, 3}, + 0x47 = { 715, 3}, + 0x48 = { 718, 3}, + 0x49 = { 721, 3}, + 0x4A = { 724, 3}, + 0x4B = { 727, 3}, + 0x4C = { 730, 3}, + 0x4D = { 733, 3}, + 0x4E = { 736, 3}, + 0x4F = { 739, 3}, + 0x50 = { 742, 2}, + 0x51 = { 744, 1}, + 0x52 = { 745, 1}, + 0x53 = { 746, 1}, + 0x54 = { 747, 1}, + 0x55 = { 748, 1}, + 0x56 = { 749, 1}, + 0x57 = { 750, 1}, + 0x58 = { 751, 1}, + 0x59 = { 752, 1}, + 0x5A = { 753, 1}, + 0x5B = { 754, 1}, + 0x5C = { 755, 1}, + 0x5D = { 756, 1}, + 0x5E = { 757, 1}, + 0x5F = { 758, 1}, + 0x6E = { 759, 1}, + 0x6F = { 760, 1}, + 0x70 = { 761, 1}, + 0x78 = { 762, 1}, + 0x79 = { 763, 1}, + 0x7E = { 764, 1}, + 0x7F = { 765, 1}, + 0x80 = { 766, 1}, + 0x81 = { 767, 1}, + 0x82 = { 768, 1}, + 0x83 = { 769, 1}, + 0x84 = { 770, 1}, + 0x85 = { 771, 1}, + 0x86 = { 772, 1}, + 0x87 = { 773, 1}, + 0x88 = { 774, 1}, + 0x89 = { 775, 1}, + 0x8A = { 776, 1}, + 0x8B = { 777, 1}, + 0x8C = { 778, 1}, + 0x8D = { 779, 1}, + 0x8E = { 780, 1}, + 0x8F = { 781, 1}, + 0x90 = { 782, 1}, + 0x91 = { 783, 1}, + 0x92 = { 784, 1}, + 0x93 = { 785, 1}, + 0x94 = { 786, 1}, + 0x95 = { 787, 1}, + 0x96 = { 788, 1}, + 0x97 = { 789, 1}, + 0x98 = { 790, 1}, + 0x99 = { 791, 1}, + 0x9A = { 792, 1}, + 0x9B = { 793, 1}, + 0x9C = { 794, 1}, + 0x9D = { 795, 1}, + 0x9E = { 796, 1}, + 0x9F = { 797, 1}, + 0xA0 = { 798, 1}, + 0xA1 = { 799, 1}, + 0xA2 = { 800, 1}, + 0xA3 = { 801, 3}, + 0xA4 = { 804, 3}, + 0xA5 = { 807, 3}, + 0xA8 = { 810, 1}, + 0xA9 = { 811, 1}, + 0xAA = { 812, 1}, + 0xAB = { 813, 3}, + 0xAC = { 816, 3}, + 0xAD = { 819, 3}, + 0xAE = { 822, 14}, + 0xAF = { 836, 3}, + 0xB0 = { 839, 1}, + 0xB1 = { 840, 3}, + 0xB3 = { 843, 3}, + 0xB6 = { 846, 3}, + 0xB7 = { 849, 2}, + 0xB9 = { 851, 1}, + 0xBA = { 852, 12}, + 0xBB = { 864, 3}, + 0xBC = { 867, 3}, + 0xBD = { 870, 3}, + 0xBE = { 873, 3}, + 0xBF = { 876, 2}, + 0xC0 = { 878, 1}, + 0xC1 = { 879, 3}, + 0xC2 = { 882, 1}, + 0xC6 = { 883, 1}, + 0xC7 = { 884, 16}, + 0xC8 = { 900, 2}, + 0xFF = { 902, 1}, }, { // prefix = 66 - 0x10 = {1022, 1}, - 0x11 = {1023, 1}, - 0x12 = {1024, 1}, - 0x13 = {1025, 1}, - 0x14 = {1026, 1}, - 0x15 = {1027, 1}, - 0x16 = {1028, 1}, - 0x17 = {1029, 1}, - 0x28 = {1030, 1}, - 0x29 = {1031, 1}, - 0x2B = {1032, 1}, - 0x2E = {1033, 1}, - 0x2F = {1034, 1}, - 0x50 = {1035, 2}, - 0x51 = {1037, 1}, - 0x54 = {1038, 1}, - 0x55 = {1039, 1}, - 0x56 = {1040, 1}, - 0x57 = {1041, 1}, - 0x58 = {1042, 1}, - 0x59 = {1043, 1}, - 0x5A = {1044, 1}, - 0x5B = {1045, 1}, - 0x5C = {1046, 1}, - 0x5D = {1047, 1}, - 0x5E = {1048, 1}, - 0x5F = {1049, 1}, - 0x60 = {1050, 1}, - 0x61 = {1051, 1}, - 0x62 = {1052, 1}, - 0x63 = {1053, 1}, - 0x64 = {1054, 1}, - 0x65 = {1055, 1}, - 0x66 = {1056, 1}, - 0x67 = {1057, 1}, - 0x68 = {1058, 1}, - 0x69 = {1059, 1}, - 0x6A = {1060, 1}, - 0x6B = {1061, 1}, - 0x6C = {1062, 1}, - 0x6D = {1063, 1}, - 0x6E = {1064, 2}, - 0x6F = {1066, 1}, - 0x70 = {1067, 1}, - 0x71 = {1068, 3}, - 0x72 = {1071, 3}, - 0x73 = {1074, 2}, - 0x74 = {1076, 1}, - 0x75 = {1077, 1}, - 0x76 = {1078, 1}, - 0x7C = {1079, 1}, - 0x7D = {1080, 1}, - 0x7E = {1081, 2}, - 0x7F = {1083, 1}, - 0xAE = {1084, 3}, - 0xC2 = {1087, 1}, - 0xC4 = {1088, 2}, - 0xC5 = {1090, 2}, - 0xC6 = {1092, 1}, - 0xC7 = {1093, 1}, - 0xD0 = {1094, 1}, - 0xD1 = {1095, 1}, - 0xD2 = {1096, 1}, - 0xD3 = {1097, 1}, - 0xD4 = {1098, 1}, - 0xD5 = {1099, 1}, - 0xD6 = {1100, 1}, - 0xD7 = {1101, 2}, - 0xD8 = {1103, 1}, - 0xD9 = {1104, 1}, - 0xDA = {1105, 1}, - 0xDB = {1106, 1}, - 0xDC = {1107, 1}, - 0xDD = {1108, 1}, - 0xDE = {1109, 1}, - 0xDF = {1110, 1}, - 0xE0 = {1111, 1}, - 0xE1 = {1112, 1}, - 0xE2 = {1113, 1}, - 0xE3 = {1114, 1}, - 0xE4 = {1115, 1}, - 0xE5 = {1116, 1}, - 0xE6 = {1117, 1}, - 0xE7 = {1118, 1}, - 0xE8 = {1119, 1}, - 0xE9 = {1120, 1}, - 0xEA = {1121, 1}, - 0xEB = {1122, 1}, - 0xEC = {1123, 1}, - 0xED = {1124, 1}, - 0xEE = {1125, 1}, - 0xEF = {1126, 1}, - 0xF1 = {1127, 1}, - 0xF2 = {1128, 1}, - 0xF3 = {1129, 1}, - 0xF4 = {1130, 1}, - 0xF5 = {1131, 1}, - 0xF6 = {1132, 1}, - 0xF7 = {1133, 1}, - 0xF8 = {1134, 1}, - 0xF9 = {1135, 1}, - 0xFA = {1136, 1}, - 0xFB = {1137, 1}, - 0xFC = {1138, 1}, - 0xFD = {1139, 1}, - 0xFE = {1140, 1}, + 0x10 = { 903, 1}, + 0x11 = { 904, 1}, + 0x12 = { 905, 1}, + 0x13 = { 906, 1}, + 0x14 = { 907, 1}, + 0x15 = { 908, 1}, + 0x16 = { 909, 1}, + 0x17 = { 910, 1}, + 0x28 = { 911, 1}, + 0x29 = { 912, 1}, + 0x2B = { 913, 1}, + 0x2E = { 914, 1}, + 0x2F = { 915, 1}, + 0x50 = { 916, 2}, + 0x51 = { 918, 1}, + 0x54 = { 919, 1}, + 0x55 = { 920, 1}, + 0x56 = { 921, 1}, + 0x57 = { 922, 1}, + 0x58 = { 923, 1}, + 0x59 = { 924, 1}, + 0x5A = { 925, 1}, + 0x5B = { 926, 1}, + 0x5C = { 927, 1}, + 0x5D = { 928, 1}, + 0x5E = { 929, 1}, + 0x5F = { 930, 1}, + 0x60 = { 931, 1}, + 0x61 = { 932, 1}, + 0x62 = { 933, 1}, + 0x63 = { 934, 1}, + 0x64 = { 935, 1}, + 0x65 = { 936, 1}, + 0x66 = { 937, 1}, + 0x67 = { 938, 1}, + 0x68 = { 939, 1}, + 0x69 = { 940, 1}, + 0x6A = { 941, 1}, + 0x6B = { 942, 1}, + 0x6C = { 943, 1}, + 0x6D = { 944, 1}, + 0x6E = { 945, 2}, + 0x6F = { 947, 1}, + 0x70 = { 948, 1}, + 0x71 = { 949, 3}, + 0x72 = { 952, 3}, + 0x73 = { 955, 2}, + 0x74 = { 957, 1}, + 0x75 = { 958, 1}, + 0x76 = { 959, 1}, + 0x7C = { 960, 1}, + 0x7D = { 961, 1}, + 0x7E = { 962, 2}, + 0x7F = { 964, 1}, + 0xAE = { 965, 3}, + 0xC2 = { 968, 1}, + 0xC4 = { 969, 2}, + 0xC5 = { 971, 2}, + 0xC6 = { 973, 1}, + 0xC7 = { 974, 1}, + 0xD0 = { 975, 1}, + 0xD1 = { 976, 1}, + 0xD2 = { 977, 1}, + 0xD3 = { 978, 1}, + 0xD4 = { 979, 1}, + 0xD5 = { 980, 1}, + 0xD6 = { 981, 1}, + 0xD7 = { 982, 2}, + 0xD8 = { 984, 1}, + 0xD9 = { 985, 1}, + 0xDA = { 986, 1}, + 0xDB = { 987, 1}, + 0xDC = { 988, 1}, + 0xDD = { 989, 1}, + 0xDE = { 990, 1}, + 0xDF = { 991, 1}, + 0xE0 = { 992, 1}, + 0xE1 = { 993, 1}, + 0xE2 = { 994, 1}, + 0xE3 = { 995, 1}, + 0xE4 = { 996, 1}, + 0xE5 = { 997, 1}, + 0xE6 = { 998, 1}, + 0xE7 = { 999, 1}, + 0xE8 = {1000, 1}, + 0xE9 = {1001, 1}, + 0xEA = {1002, 1}, + 0xEB = {1003, 1}, + 0xEC = {1004, 1}, + 0xED = {1005, 1}, + 0xEE = {1006, 1}, + 0xEF = {1007, 1}, + 0xF1 = {1008, 1}, + 0xF2 = {1009, 1}, + 0xF3 = {1010, 1}, + 0xF4 = {1011, 1}, + 0xF5 = {1012, 1}, + 0xF6 = {1013, 1}, + 0xF7 = {1014, 1}, + 0xF8 = {1015, 1}, + 0xF9 = {1016, 1}, + 0xFA = {1017, 1}, + 0xFB = {1018, 1}, + 0xFC = {1019, 1}, + 0xFD = {1020, 1}, + 0xFE = {1021, 1}, }, { // prefix = F3 - 0x01 = {1141, 6}, - 0x09 = {1147, 1}, - 0x10 = {1148, 1}, - 0x11 = {1149, 1}, - 0x12 = {1150, 1}, - 0x16 = {1151, 1}, - 0x1E = {1152, 4}, - 0x2A = {1156, 2}, - 0x2C = {1158, 2}, - 0x2D = {1160, 2}, - 0x51 = {1162, 1}, - 0x52 = {1163, 1}, - 0x53 = {1164, 1}, - 0x58 = {1165, 1}, - 0x59 = {1166, 1}, - 0x5A = {1167, 1}, - 0x5B = {1168, 1}, - 0x5C = {1169, 1}, - 0x5D = {1170, 1}, - 0x5E = {1171, 1}, - 0x5F = {1172, 1}, - 0x6F = {1173, 1}, - 0x70 = {1174, 1}, - 0x7E = {1175, 1}, - 0x7F = {1176, 1}, - 0xAE = {1177, 14}, - 0xB8 = {1191, 3}, - 0xBC = {1194, 3}, - 0xBD = {1197, 3}, - 0xC2 = {1200, 1}, - 0xC7 = {1201, 2}, - 0xE6 = {1203, 1}, + 0x01 = {1022, 6}, + 0x09 = {1028, 1}, + 0x10 = {1029, 1}, + 0x11 = {1030, 1}, + 0x12 = {1031, 1}, + 0x16 = {1032, 1}, + 0x1E = {1033, 4}, + 0x2A = {1037, 2}, + 0x2C = {1039, 2}, + 0x2D = {1041, 2}, + 0x51 = {1043, 1}, + 0x52 = {1044, 1}, + 0x53 = {1045, 1}, + 0x58 = {1046, 1}, + 0x59 = {1047, 1}, + 0x5A = {1048, 1}, + 0x5B = {1049, 1}, + 0x5C = {1050, 1}, + 0x5D = {1051, 1}, + 0x5E = {1052, 1}, + 0x5F = {1053, 1}, + 0x6F = {1054, 1}, + 0x70 = {1055, 1}, + 0x7E = {1056, 1}, + 0x7F = {1057, 1}, + 0xAE = {1058, 14}, + 0xB8 = {1072, 3}, + 0xBC = {1075, 3}, + 0xBD = {1078, 3}, + 0xC2 = {1081, 1}, + 0xC7 = {1082, 2}, + 0xE6 = {1084, 1}, }, { // prefix = F2 - 0x01 = {1204, 2}, - 0x10 = {1206, 1}, - 0x11 = {1207, 1}, - 0x12 = {1208, 1}, - 0x2A = {1209, 2}, - 0x2C = {1211, 2}, - 0x2D = {1213, 2}, - 0x51 = {1215, 1}, - 0x58 = {1216, 1}, - 0x59 = {1217, 1}, - 0x5A = {1218, 1}, - 0x5C = {1219, 1}, - 0x5D = {1220, 1}, - 0x5E = {1221, 1}, - 0x5F = {1222, 1}, - 0x70 = {1223, 1}, - 0x7C = {1224, 1}, - 0x7D = {1225, 1}, - 0xAE = {1226, 1}, - 0xC2 = {1227, 1}, - 0xD0 = {1228, 1}, - 0xE6 = {1229, 1}, - 0xF0 = {1230, 1}, + 0x01 = {1085, 2}, + 0x10 = {1087, 1}, + 0x11 = {1088, 1}, + 0x12 = {1089, 1}, + 0x2A = {1090, 2}, + 0x2C = {1092, 2}, + 0x2D = {1094, 2}, + 0x51 = {1096, 1}, + 0x58 = {1097, 1}, + 0x59 = {1098, 1}, + 0x5A = {1099, 1}, + 0x5C = {1100, 1}, + 0x5D = {1101, 1}, + 0x5E = {1102, 1}, + 0x5F = {1103, 1}, + 0x70 = {1104, 1}, + 0x7C = {1105, 1}, + 0x7D = {1106, 1}, + 0xAE = {1107, 1}, + 0xC2 = {1108, 1}, + 0xD0 = {1109, 1}, + 0xE6 = {1110, 1}, + 0xF0 = {1111, 1}, }, } @(rodata) DECODE_INDEX_ESC_0F38 := [4][256]lib.Decode_Index{ { // prefix = none - 0xC8 = {1231, 1}, - 0xC9 = {1232, 1}, - 0xCA = {1233, 1}, - 0xCB = {1234, 1}, - 0xCC = {1235, 1}, - 0xCD = {1236, 1}, - 0xF0 = {1237, 3}, - 0xF1 = {1240, 3}, - 0xF6 = {1243, 2}, - 0xF9 = {1245, 2}, - 0xFC = {1247, 2}, + 0xC8 = {1112, 1}, + 0xC9 = {1113, 1}, + 0xCA = {1114, 1}, + 0xCB = {1115, 1}, + 0xCC = {1116, 1}, + 0xCD = {1117, 1}, + 0xF0 = {1118, 3}, + 0xF1 = {1121, 3}, + 0xF6 = {1124, 2}, + 0xF9 = {1126, 2}, + 0xFC = {1128, 2}, }, { // prefix = 66 - 0x00 = {1249, 1}, - 0x01 = {1250, 1}, - 0x02 = {1251, 1}, - 0x03 = {1252, 1}, - 0x04 = {1253, 1}, - 0x05 = {1254, 1}, - 0x06 = {1255, 1}, - 0x07 = {1256, 1}, - 0x08 = {1257, 1}, - 0x09 = {1258, 1}, - 0x0A = {1259, 1}, - 0x0B = {1260, 1}, - 0x10 = {1261, 1}, - 0x14 = {1262, 1}, - 0x15 = {1263, 1}, - 0x17 = {1264, 1}, - 0x1C = {1265, 1}, - 0x1D = {1266, 1}, - 0x1E = {1267, 1}, - 0x20 = {1268, 1}, - 0x21 = {1269, 1}, - 0x22 = {1270, 1}, - 0x23 = {1271, 1}, - 0x24 = {1272, 1}, - 0x25 = {1273, 1}, - 0x28 = {1274, 1}, - 0x29 = {1275, 1}, - 0x2A = {1276, 1}, - 0x2B = {1277, 1}, - 0x30 = {1278, 1}, - 0x31 = {1279, 1}, - 0x32 = {1280, 1}, - 0x33 = {1281, 1}, - 0x34 = {1282, 1}, - 0x35 = {1283, 1}, - 0x37 = {1284, 1}, - 0x38 = {1285, 1}, - 0x39 = {1286, 1}, - 0x3A = {1287, 1}, - 0x3B = {1288, 1}, - 0x3C = {1289, 1}, - 0x3D = {1290, 1}, - 0x3E = {1291, 1}, - 0x3F = {1292, 1}, - 0x40 = {1293, 1}, - 0x41 = {1294, 1}, - 0x80 = {1295, 1}, - 0x81 = {1296, 1}, - 0x82 = {1297, 2}, - 0xDB = {1299, 1}, - 0xDC = {1300, 1}, - 0xDD = {1301, 1}, - 0xDE = {1302, 1}, - 0xDF = {1303, 1}, - 0xF5 = {1304, 2}, - 0xF6 = {1306, 2}, - 0xF8 = {1308, 1}, - 0xFC = {1309, 2}, + 0x00 = {1130, 1}, + 0x01 = {1131, 1}, + 0x02 = {1132, 1}, + 0x03 = {1133, 1}, + 0x04 = {1134, 1}, + 0x05 = {1135, 1}, + 0x06 = {1136, 1}, + 0x07 = {1137, 1}, + 0x08 = {1138, 1}, + 0x09 = {1139, 1}, + 0x0A = {1140, 1}, + 0x0B = {1141, 1}, + 0x10 = {1142, 1}, + 0x14 = {1143, 1}, + 0x15 = {1144, 1}, + 0x17 = {1145, 1}, + 0x1C = {1146, 1}, + 0x1D = {1147, 1}, + 0x1E = {1148, 1}, + 0x20 = {1149, 1}, + 0x21 = {1150, 1}, + 0x22 = {1151, 1}, + 0x23 = {1152, 1}, + 0x24 = {1153, 1}, + 0x25 = {1154, 1}, + 0x28 = {1155, 1}, + 0x29 = {1156, 1}, + 0x2A = {1157, 1}, + 0x2B = {1158, 1}, + 0x30 = {1159, 1}, + 0x31 = {1160, 1}, + 0x32 = {1161, 1}, + 0x33 = {1162, 1}, + 0x34 = {1163, 1}, + 0x35 = {1164, 1}, + 0x37 = {1165, 1}, + 0x38 = {1166, 1}, + 0x39 = {1167, 1}, + 0x3A = {1168, 1}, + 0x3B = {1169, 1}, + 0x3C = {1170, 1}, + 0x3D = {1171, 1}, + 0x3E = {1172, 1}, + 0x3F = {1173, 1}, + 0x40 = {1174, 1}, + 0x41 = {1175, 1}, + 0x80 = {1176, 1}, + 0x81 = {1177, 1}, + 0x82 = {1178, 2}, + 0xDB = {1180, 1}, + 0xDC = {1181, 1}, + 0xDD = {1182, 1}, + 0xDE = {1183, 1}, + 0xDF = {1184, 1}, + 0xF5 = {1185, 2}, + 0xF6 = {1187, 2}, + 0xF8 = {1189, 1}, + 0xFC = {1190, 2}, }, { // prefix = F3 - 0xF6 = {1311, 2}, - 0xF8 = {1313, 1}, - 0xFC = {1314, 2}, + 0xF6 = {1192, 2}, + 0xF8 = {1194, 1}, + 0xFC = {1195, 2}, }, { // prefix = F2 - 0xF0 = {1316, 2}, - 0xF1 = {1318, 3}, - 0xF8 = {1321, 1}, - 0xFC = {1322, 2}, + 0xF0 = {1197, 2}, + 0xF1 = {1199, 3}, + 0xF8 = {1202, 1}, + 0xFC = {1203, 2}, }, } @(rodata) DECODE_INDEX_ESC_0F3A := [4][256]lib.Decode_Index{ { // prefix = none - 0xCC = {1324, 1}, + 0xCC = {1205, 1}, }, { // prefix = 66 - 0x08 = {1325, 1}, - 0x09 = {1326, 1}, - 0x0A = {1327, 1}, - 0x0B = {1328, 1}, - 0x0C = {1329, 1}, - 0x0D = {1330, 1}, - 0x0E = {1331, 1}, - 0x0F = {1332, 1}, - 0x14 = {1333, 1}, - 0x16 = {1334, 2}, - 0x17 = {1336, 1}, - 0x20 = {1337, 1}, - 0x21 = {1338, 1}, - 0x22 = {1339, 2}, - 0x40 = {1341, 1}, - 0x41 = {1342, 1}, - 0x42 = {1343, 1}, - 0x44 = {1344, 1}, - 0x60 = {1345, 1}, - 0x61 = {1346, 1}, - 0x62 = {1347, 1}, - 0x63 = {1348, 1}, - 0xDF = {1349, 1}, + 0x08 = {1206, 1}, + 0x09 = {1207, 1}, + 0x0A = {1208, 1}, + 0x0B = {1209, 1}, + 0x0C = {1210, 1}, + 0x0D = {1211, 1}, + 0x0E = {1212, 1}, + 0x0F = {1213, 1}, + 0x14 = {1214, 1}, + 0x16 = {1215, 2}, + 0x17 = {1217, 1}, + 0x20 = {1218, 1}, + 0x21 = {1219, 1}, + 0x22 = {1220, 2}, + 0x40 = {1222, 1}, + 0x41 = {1223, 1}, + 0x42 = {1224, 1}, + 0x44 = {1225, 1}, + 0x60 = {1226, 1}, + 0x61 = {1227, 1}, + 0x62 = {1228, 1}, + 0x63 = {1229, 1}, + 0xDF = {1230, 1}, }, { // prefix = F3 }, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 3eb58e95a..a459d52cb 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -585,11 +585,11 @@ ENCODE_FORMS := [2478]lib.Encoding{ {.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {explicit_count=1}}, {.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F, explicit_count=1}}, // .JCXZ - {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, + {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A16, explicit_count=1}}, // .JECXZ - {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, + {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A32, explicit_count=1}}, // .JRCXZ - {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true, explicit_count=1}}, + {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A64, explicit_count=1}}, // .LOOP {.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {explicit_count=1}}, // .LOOPE diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 11e897138..e586a3f65 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -733,14 +733,20 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, {{.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, }, + /* 0xE3 is ONE opcode whose mnemonic is chosen by ADDRESS size -- which + counter register it tests -- not by operand size. So the three are told + apart by `addr_size` (67h against the mode default), never by REX.W, which + does not affect address size at all: JRCXZ is a bare `E3 cb` in long mode + and JECXZ is `67 E3 cb`; in protected mode JECXZ is bare and JCXZ takes + the prefix, while JCXZ is unreachable in long mode and JRCXZ outside it. */ .JCXZ = { - {{.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A16}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .JECXZ = { - {{.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A32}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .JRCXZ = { - {{.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A64}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .LOOP = { {{.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {}}, {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}}, diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index a71e55be91b5c96de8a94254ec4bb1d13e17b881..3e03ddfdb190c282e9584d3c5166908d354ce89b 100644 GIT binary patch literal 39648 zcmZ9V1)NpY7RL9DDMDxH_QDKZLn#J0HYx@n5)w9cw^DWs1_&x*0D_A8e0Fy}J80|< z3`$hqx7Ob4+nbs9doq8%Z>_!dI{WN;9SX;oG&H&_y*49k>f#&ZwN+?$1T1Q7&(mdjlswP*7zdC zOAW8W-&X2Jdwf9RnUrifwtQgqTfXOl-|~T> z7wKA*{6}d2i(LyGyE6228jjC2SL|Bid`Y<#w7@vt#XR3Gb*`oWw)5?>z;?bF+xZ3_ zRB$B@!(mp=9f<#zgXQc?zf^#+T#WO=O~7cOI}ZOBKTa2oIVLbp5B#lj z#s&OdhX2n+7V#V3qg={*M#58$(X1XY>M3PC*FmoUTRmXZQ_6gIgnX8Np>mnaVsPpA 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mnemonics name ONE encoding -- SHL and SAL are both /4 in the + shift group, JE and JZ are both 0x74. Which name a decode returns is declared + by x86.MNEMONIC_ALIASES and enforced by the generator, which drops the + aliased spelling before the decode tables are written; so encoding SAL and + decoding it back yields SHL, and a round-trip compares canonical forms. + + This used to be a second alias table maintained BY HAND here, and that is how + SHL/SAL went missing: the shift group was never listed, nothing checked, and + it stayed invisible until a table regeneration moved SAL ahead of SHL and + four long-passing tests began reporting `SAL != expected SHL`. There is now + one table, in the library, and run_alias_table_test below proves it complete + against the built tables rather than against anyone's memory. +*/ mnemonics_eq :: proc(a, b: x86.Mnemonic) -> bool { - if a == b { return true } - aliases := [][2]x86.Mnemonic{ - // MOV/MOVABS - {.MOV, .MOVABS}, - // CMOVcc aliases - {.CMOVE, .CMOVZ}, {.CMOVNE, .CMOVNZ}, - {.CMOVG, .CMOVNLE}, {.CMOVGE, .CMOVNL}, - {.CMOVL, .CMOVNGE}, {.CMOVLE, .CMOVNG}, - {.CMOVA, .CMOVNBE}, {.CMOVAE, .CMOVNB}, {.CMOVAE, .CMOVNC}, - {.CMOVB, .CMOVNAE}, {.CMOVB, .CMOVC}, {.CMOVBE, .CMOVNA}, - // SETcc aliases - {.SETE, .SETZ}, {.SETNE, .SETNZ}, - {.SETG, .SETNLE}, {.SETGE, .SETNL}, - {.SETL, .SETNGE}, {.SETLE, .SETNG}, - {.SETA, .SETNBE}, {.SETAE, .SETNB}, {.SETAE, .SETNC}, - {.SETB, .SETNAE}, {.SETB, .SETC}, {.SETBE, .SETNA}, - // Jcc aliases - {.JE, .JZ}, {.JNE, .JNZ}, - {.JB, .JC}, {.JAE, .JNC}, - {.JG, .JNLE}, {.JGE, .JNL}, - {.JL, .JNGE}, {.JLE, .JNG}, - {.JA, .JNBE}, {.JAE, .JNB}, - {.JB, .JNAE}, {.JBE, .JNA}, + return a == b || x86.canonical_mnemonic(a) == x86.canonical_mnemonic(b) +} + +/* + No encoding may be spelled by two mnemonics that both survive into the decode + tables -- because the decoder would then have to choose between them with + nothing to choose on, which is the defect x86.MNEMONIC_ALIASES exists to + remove. Two entries are indistinguishable exactly when they agree on every + field the decoder can read, so the property is computable from the tables + themselves, and this recomputes it. + + It is what makes the declaration maintainable: an instruction added with a + mnemonic that aliases another's encoding fails here BY NAME, with the row to + write, instead of silently decoding as whichever spelling the sort happened + to put first. +*/ +run_alias_table_test :: proc() { + Group_Key :: struct { + esc: x86.Escape, + prefix: u8, + opcode: u8, + ext: u8, + ops: [4]x86.Operand_Type, + enc: [4]x86.Operand_Encoding, + flags: x86.Encoding_Flags, } - for alias in aliases { - if (a == alias[0] && b == alias[1]) || (a == alias[1] && b == alias[0]) { return true } + groups := make(map[Group_Key][dynamic]x86.Mnemonic) + defer { + for _, list in groups { delete(list) } + delete(groups) + } + for e in x86.LEGACY_DECODE_ENTRIES { + key := Group_Key{e.esc, e.prefix, e.opcode, e.ext, e.ops, e.enc, e.flags} + list, present := &groups[key] + if !present { + groups[key] = make([dynamic]x86.Mnemonic) + list = &groups[key] + } + known := false + for m in list { + if m == e.mnemonic { + known = true + break + } + } + if !known { append(list, e.mnemonic) } + } + + ambiguous := 0 + for key, list in groups { + if len(list) < 2 { continue } + ambiguous += 1 + if ambiguous <= 10 { + fmt.printf(" %sFAIL%s esc=%v prefix=%d opcode=%02X ext=%02X is spelled by", + RED, RESET, key.esc, key.prefix, key.opcode, key.ext) + for m in list { fmt.printf(" %v", m) } + fmt.printf(",\n and the decoder has nothing to choose between them. Declare one in\n") + fmt.printf(" x86.MNEMONIC_ALIASES (isa/x86/aliases.odin), then regenerate:\n") + fmt.printf(" odin run core/rexcode/isa/x86/tablegen && odin run core/rexcode/isa/x86/tablegen/generated\n") + } + } + if ambiguous > 10 { + fmt.printf(" ... and %d further ambiguous encoding(s).\n", ambiguous - 10) + } + if ambiguous > 0 { + g_stats.failed += 1 + return + } + g_stats.passed += 1 + g_stats.cases_validated += 1 +} + +/* + 0xE3 is one opcode whose MNEMONIC is chosen by address size -- which counter + register it tests -- and address size is the 67h axis, not REX.W. Modelling + JRCXZ as `force_rex_w` made its encoding `48 E3 cb` (llvm-mc emits a bare + `E3 cb`, and REX.W does not affect address size at all), gave JECXZ the bare + encoding that is really JRCXZ in long mode, and left the decoder with three + indistinguishable entries to guess between. + + Both directions and both modes are asserted here, refusals included: JCXZ is + unreachable in long mode (67h selects 32-bit there, never 16-bit) and JRCXZ + outside it. Every expectation below was measured against llvm-mc. +*/ +run_addr_size_tests :: proc() { + Decode_Case :: struct { + bytes: []u8, + mode: x86.Mode, + want: x86.Mnemonic, + note: string, + } + decodes := []Decode_Case{ + {{0xE3, 0x00}, ._64, .JRCXZ, "long mode default address size is 64-bit"}, + {{0x67, 0xE3, 0x00}, ._64, .JECXZ, "67h drops long mode to 32-bit"}, + {{0x48, 0xE3, 0x00}, ._64, .JRCXZ, "REX.W is ignored for address size"}, + {{0xE3, 0x00}, ._32, .JECXZ, "protected mode default is 32-bit"}, + {{0x67, 0xE3, 0x00}, ._32, .JCXZ, "67h drops protected mode to 16-bit"}, + } + for c in decodes { + insts := make([dynamic]x86.Instruction) + info := make([dynamic]x86.Instruction_Info) + labels := make([dynamic]x86.Label_Definition) + errors := make([dynamic]x86.Error) + defer { + delete(insts); delete(info); delete(labels); delete(errors) + } + _, ok := x86.decode(c.bytes, nil, &insts, &info, &labels, &errors, c.mode) + if !ok || len(insts) == 0 { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v decode failed in %v (%s)\n", RED, RESET, c.bytes, c.mode, c.note) + continue + } + if insts[0].mnemonic != c.want { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v decoded %v, expected %v -- %s\n", + RED, RESET, c.bytes, c.mode, insts[0].mnemonic, c.want, c.note) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 + } + + Encode_Case :: struct { + mnemonic: x86.Mnemonic, + mode: x86.Mode, + want: []u8, // empty = must be refused; this mode cannot express it + } + encodes := []Encode_Case{ + {.JRCXZ, ._64, {0xE3, 0x00}}, + {.JECXZ, ._64, {0x67, 0xE3, 0x00}}, + {.JCXZ, ._64, {}}, + {.JECXZ, ._32, {0xE3, 0x00}}, + {.JCXZ, ._32, {0x67, 0xE3, 0x00}}, + {.JRCXZ, ._32, {}}, + } + for c in encodes { + insts := []x86.Instruction{x86.inst_rel_offset(c.mnemonic, 0, 1)} + code := make([]u8, 32) + relocs := make([dynamic]x86.Relocation) + errors := make([dynamic]x86.Error) + defer { + delete(code); delete(relocs); delete(errors) + } + count, ok := x86.encode(insts, nil, code, &relocs, &errors, true, 0, c.mode) + if len(c.want) == 0 { + if ok && count > 0 { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v encoded to %02X in %v, but that mode cannot express its address size\n", + RED, RESET, c.mnemonic, code[:count], c.mode) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 + continue + } + if !ok || int(count) != len(c.want) { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v encoded %d byte(s), expected %d\n", + RED, RESET, c.mnemonic, c.mode, count, len(c.want)) + continue + } + same := true + for want, i in c.want { + if code[i] != want { same = false; break } + } + if !same { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v encoded % 02X, expected % 02X\n", + RED, RESET, c.mnemonic, c.mode, code[:count], c.want) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 } - return false } // ============================================================================= @@ -3630,6 +3790,12 @@ main :: proc() { log_header("TYPED BUILDER CONSISTENCY") run_typed_builder_tests() + log_header("MNEMONIC ALIAS TABLE") + run_alias_table_test() + + log_header("ADDRESS-SIZE SELECTED MNEMONICS") + run_addr_size_tests() + log_header("I386 (32-BIT MODE) TESTS") run_i386_tests() From 7664ab61cde89e8a9f513eb89d9437126229e518 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 16:48:22 -0400 Subject: [PATCH 44/89] rexcode/arm64: SVE predicate sizes, gather/scatter addressing, INDEX Predicates are written with an element size wherever they are an operand rather than the governing mask -- `zip1 p0.b, p1.b, p2.b`, and `and p0.b, p1/z, p2.b, p3.b`, where the same instruction has both. 59 source operands printed bare. Two paths were missing it outright: .PN never picked up the size at all, and the WHILE family had one form standing in for all four element sizes, so `whilelt` could only ever print `p0`. SVE gather and scatter name the element size of their vector index and how the base extends it (`[x0, z0.s, uxtw]`); none of that was printed. The two lay their fields out differently and the difference is not cosmetic: a gather has the extend at bit 22 and takes the index width from its opcode, while a scatter has the width at 22 and the extend at 14. Reading them the same way meant the .s scatters carried the .d encoding -- ST1B, ST1H and ST1W all had two forms with identical bits, so one of each pair was dead. Memory had no room left for the index's element size (16 + 16 + 23 + 3 + 3 + 3 is exactly 64; the "1 bit spare" comment was stale), so it travels in the operand's own size field, which memory operands do not otherwise use. INDEX had its two operands in each other's slots: SVE_IMM5 is bits 20:16, which is the *second* operand, so the first was written to the wrong field and the second was not written at all -- `index z0.b, #0,` with a trailing empty operand. It was also .b-only, and its register operands are W below .d rather than X. SVE LDR/STR move a whole register and take no element size; an earlier pass had given their operands one. SVE/SME2 decode entries against llvm-mc: 525 byte-exact and 0 mismatched, from 211 and 78 at the start of the session. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 35 +- core/rexcode/isa/arm64/encoder.odin | 6 +- core/rexcode/isa/arm64/encoding_types.odin | 9 + core/rexcode/isa/arm64/mnemonic_builders.odin | 388 ++++++----- core/rexcode/isa/arm64/operands.odin | 2 +- core/rexcode/isa/arm64/printer.odin | 12 +- .../tablegen/generated/decode_tables.odin | 200 +++--- .../tablegen/generated/encode_tables.odin | 642 ++++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 172 +++-- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 35140 -> 35644 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 50200 -> 50920 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6568 -> 6568 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 50240 -> 50960 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes core/rexcode/isa/arm64/tests/smoke.odin | 8 +- 15 files changed, 864 insertions(+), 610 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index fbb3ad41f..1f84c221f 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -499,7 +499,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .PD: return Operand{reg = Register(REG_P | u16(word & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .PN: - return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = 4} + return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .PM: return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .ENC_ZT0: @@ -520,6 +520,10 @@ extract_operand_inline :: #force_inline proc "contextless" ( v := i32((word >> 5) & 0xFF) if v & 0x80 != 0 { v |= ~i32(0xFF) } return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} + case .SVE_IMM5A: + v := i64((word >> 5) & 0x1F) + if v & 0x10 != 0 { v |= ~i64(0x1F) } + return Operand{immediate = v, kind = .IMMEDIATE, size = 1} case .SVE_IMM5: return Operand{immediate = i64((word >> 16) & 0x1F), kind = .IMMEDIATE, size = 1} case .SVE_SHIFT_TSZ_IMM: @@ -573,17 +577,30 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64((word >> 5) & 0xF), kind = .IMMEDIATE, size = 1} // ---- SVE gather/scatter + vector-base memory ---- - case .SVE_OFFSET_BASE_VEC: + case .SVE_OFFSET_BASE_VEC, .SVE_OFFSET_BASE_VEC_S, .SVE_OFFSET_BASE_VEC_D, + .SVE_OFFSET_BASE_VECST_S, .SVE_OFFSET_BASE_VECST_D: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) - return Operand{ - mem = Memory{ - base = Register(REG_X | u16(base_hw)), - index = Register(REG_Z | u16(idx_hw)), - mode = .REG_OFFSET, - }, - kind = .MEMORY, size = 4, + m := Memory{ + base = Register(REG_X | u16(base_hw)), + index = Register(REG_Z | u16(idx_hw)), + mode = .REG_OFFSET, } + // These forms all extend a 32-bit-wide index, and bit 22 says which way. + // The index's own element size is not derivable from the word, so it + // travels in the operand's size -- Memory has no bits left. + shape := u8(4) + #partial switch en { + case .SVE_OFFSET_BASE_VEC_S, .SVE_OFFSET_BASE_VEC_D: + m.mode = .EXT_REG_OFFSET + m.extend = (word >> 22) & 1 != 0 ? .SXTW : .UXTW + shape = en == .SVE_OFFSET_BASE_VEC_D ? ZSHAPE_D : ZSHAPE_S + case .SVE_OFFSET_BASE_VECST_S, .SVE_OFFSET_BASE_VECST_D: + m.mode = .EXT_REG_OFFSET + m.extend = (word >> 14) & 1 != 0 ? .SXTW : .UXTW + shape = en == .SVE_OFFSET_BASE_VECST_D ? ZSHAPE_D : ZSHAPE_S + } + return Operand{mem = m, kind = .MEMORY, size = shape} case .SVE_OFFSET_VEC_BASE: base_hw := u8((word >> 5) & 0x1F) imm := i32((word >> 16) & 0x1F) diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 3e5edccfa..d3c0ee802 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -679,6 +679,9 @@ pack_operand_inline :: #force_inline proc( case .SVE_IMM8: // Signed 8-bit at bits 12-5 (DUP/CPY/ADD imm). return (u32(op.immediate) & 0xFF) << 5 + case .SVE_IMM5A: + // INDEX's first operand; SVE_IMM5 is the second, at bits 20:16. + return (u32(op.immediate) & 0x1F) << 5 case .SVE_IMM5: // 5-bit at bits 20-16 (INDEX imm, etc.). return (u32(op.immediate) & 0x1F) << 16 @@ -721,7 +724,8 @@ pack_operand_inline :: #force_inline proc( return (u32(op.immediate) & 0xF) << 5 // ---- SVE gather/scatter + vector-base memory -------------------------- - case .SVE_OFFSET_BASE_VEC: + case .SVE_OFFSET_BASE_VEC, .SVE_OFFSET_BASE_VEC_S, .SVE_OFFSET_BASE_VEC_D, + .SVE_OFFSET_BASE_VECST_S, .SVE_OFFSET_BASE_VECST_D: // [Xn, Zm.S/D, extend] -- base GPR at 9:5, Zm at 20:16. base := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 idx := (u32(reg_hw(op.mem.index)) & 0x1F) << 16 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 0591ef565..36a6816f1 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -414,6 +414,15 @@ Operand_Encoding :: enum u8 { // assembler wants that written out (`[x0, x0, lsl #2]`). The amount is a // property of the form, so it rides on the encoding. SVE_OFFSET_BASE_SS1, SVE_OFFSET_BASE_SS2, SVE_OFFSET_BASE_SS3, + // SVE gather/scatter: the index is a vector, and the syntax names its + // element size and how the base extends it. A 32-bit index is written + // `uxtw`/`sxtw` (bit 22 says which); a 64-bit one needs neither. + SVE_OFFSET_BASE_VEC_S, SVE_OFFSET_BASE_VEC_D, + // A scatter lays the same information out differently: bit 22 is the + // index's width and bit 14 is the extend, where a gather has the extend at + // 22 and takes the width from its opcode. + SVE_OFFSET_BASE_VECST_S, SVE_OFFSET_BASE_VECST_D, + SVE_IMM5A, // 5-bit at bits 5-9 (INDEX first operand) // A Z register whose element size is not in the static pattern but in the // instruction's own tsz field, so decode has to read it out of the word // rather than take it from the form (SVE2 XAR). diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 26c2db5f0..321812749 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -116,7 +116,7 @@ inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_and_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_and_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } emit_and_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v16b_v16b_v16b(dst, src, src2)) } @@ -124,13 +124,13 @@ emit_and_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_and_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_and_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_and_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -emit_and_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_p_p(rz, rz2, rz3, rz4)) } +emit_and_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_ands_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } -emit_ands_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_ph_p_p_p(rz, rz2, rz3, rz4)) } +emit_ands_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_ph_p_ph_ph(rz, rz2, rz3, rz4)) } inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -138,7 +138,7 @@ inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orr_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } @@ -146,7 +146,7 @@ emit_orr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_orr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_orr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_orr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -emit_orr_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_ps_p_p_p(rz, rz2, rz3, rz4)) } +emit_orr_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_ps_p_ps_ps(rz, rz2, rz3, rz4)) } inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -154,7 +154,7 @@ inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_eor_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } emit_eor_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v16b_v16b_v16b(dst, src, src2)) } @@ -162,31 +162,31 @@ emit_eor_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_eor_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_eor_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_eor_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -emit_eor_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_pb_p_p_p(rz, rz2, rz3, rz4)) } +emit_eor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_bic_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bic_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bic_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v16b_v16b_v16b(dst, src, src2)) } emit_bic_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_bic_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bic_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_bic_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -emit_bic_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_p_p(rz, rz2, rz3, rz4)) } +emit_bic_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bics_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_bics_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_ph_p_p_p(rz, rz2, rz3, rz4)) } +emit_bics_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_ph_p_ph_ph(rz, rz2, rz3, rz4)) } inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orn_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orn_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } -emit_orn_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_ps_p_p_p(rz, rz2, rz3, rz4)) } +emit_orn_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_ps_p_ps_ps(rz, rz2, rz3, rz4)) } inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } @@ -328,13 +328,13 @@ inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}}} } inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}}} } inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}}} } -inst_rev_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_rev_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } emit_rev_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zb_zb(rz, rz2)) } emit_rev_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zh_zh(rz, rz2)) } emit_rev_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zs_zs(rz, rz2)) } emit_rev_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zd_zd(rz, rz2)) } -emit_rev_pb_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_pb_p(rz, rz2)) } +emit_rev_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_pb_pb(rz, rz2)) } inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } @@ -433,21 +433,21 @@ inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -inst_ldr_zb_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_ldr_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } -emit_ldr_zb_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_zb_m(rz, mem)) } -emit_ldr_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_ps_m(rz, mem)) } +emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } +emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -inst_str_zb_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } -inst_str_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } -emit_str_zb_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_zb_m(rz, mem)) } -emit_str_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_ps_m(rz, mem)) } +emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } +emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } @@ -3186,7 +3186,7 @@ inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_zip1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8b_v8b_v8b(dst, src, src2)) } emit_zip1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v16b_v16b_v16b(dst, src, src2)) } emit_zip1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4h_v4h_v4h(dst, src, src2)) } @@ -3198,7 +3198,7 @@ emit_zip1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zh_zh_zh(rz, rz2, rz3)) } emit_zip1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zs_zs_zs(rz, rz2, rz3)) } emit_zip1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zd_zd_zd(rz, rz2, rz3)) } -emit_zip1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_pb_p_p(rz, rz2, rz3)) } +emit_zip1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_pb_pb_pb(rz, rz2, rz3)) } inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -3210,7 +3210,7 @@ inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_zip2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8b_v8b_v8b(dst, src, src2)) } emit_zip2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v16b_v16b_v16b(dst, src, src2)) } emit_zip2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4h_v4h_v4h(dst, src, src2)) } @@ -3222,7 +3222,7 @@ emit_zip2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zh_zh_zh(rz, rz2, rz3)) } emit_zip2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zs_zs_zs(rz, rz2, rz3)) } emit_zip2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zd_zd_zd(rz, rz2, rz3)) } -emit_zip2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_pb_p_p(rz, rz2, rz3)) } +emit_zip2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_pb_pb_pb(rz, rz2, rz3)) } inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -3234,7 +3234,7 @@ inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_uzp1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8b_v8b_v8b(dst, src, src2)) } emit_uzp1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v16b_v16b_v16b(dst, src, src2)) } emit_uzp1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4h_v4h_v4h(dst, src, src2)) } @@ -3246,7 +3246,7 @@ emit_uzp1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zh_zh_zh(rz, rz2, rz3)) } emit_uzp1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zs_zs_zs(rz, rz2, rz3)) } emit_uzp1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zd_zd_zd(rz, rz2, rz3)) } -emit_uzp1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_pb_p_p(rz, rz2, rz3)) } +emit_uzp1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_pb_pb_pb(rz, rz2, rz3)) } inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -3258,7 +3258,7 @@ inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_uzp2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8b_v8b_v8b(dst, src, src2)) } emit_uzp2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v16b_v16b_v16b(dst, src, src2)) } emit_uzp2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4h_v4h_v4h(dst, src, src2)) } @@ -3270,7 +3270,7 @@ emit_uzp2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zh_zh_zh(rz, rz2, rz3)) } emit_uzp2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zs_zs_zs(rz, rz2, rz3)) } emit_uzp2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zd_zd_zd(rz, rz2, rz3)) } -emit_uzp2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_pb_p_p(rz, rz2, rz3)) } +emit_uzp2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_pb_pb_pb(rz, rz2, rz3)) } inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -3282,7 +3282,7 @@ inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn1_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_trn1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8b_v8b_v8b(dst, src, src2)) } emit_trn1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v16b_v16b_v16b(dst, src, src2)) } emit_trn1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4h_v4h_v4h(dst, src, src2)) } @@ -3294,7 +3294,7 @@ emit_trn1_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zh_zh_zh(rz, rz2, rz3)) } emit_trn1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zs_zs_zs(rz, rz2, rz3)) } emit_trn1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zd_zd_zd(rz, rz2, rz3)) } -emit_trn1_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_pb_p_p(rz, rz2, rz3)) } +emit_trn1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_pb_pb_pb(rz, rz2, rz3)) } inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } @@ -3306,7 +3306,7 @@ inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn2_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_trn2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8b_v8b_v8b(dst, src, src2)) } emit_trn2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v16b_v16b_v16b(dst, src, src2)) } emit_trn2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4h_v4h_v4h(dst, src, src2)) } @@ -3318,13 +3318,13 @@ emit_trn2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zh_zh_zh(rz, rz2, rz3)) } emit_trn2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zs_zs_zs(rz, rz2, rz3)) } emit_trn2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zd_zd_zd(rz, rz2, rz3)) } -emit_trn2_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_pb_p_p(rz, rz2, rz3)) } +emit_trn2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_pb_pb_pb(rz, rz2, rz3)) } inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_not_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_not_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_not_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v8b_v8b(dst, src)) } emit_not_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v16b_v16b(dst, src)) } -emit_not_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_pb_p_p(rz, rz2, rz3)) } +emit_not_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_pb_p_pb(rz, rz2, rz3)) } inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } @@ -3541,22 +3541,22 @@ inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: emit_fnmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_nand_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nand_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_ps_p_p_p(rz, rz2, rz3, rz4)) } -inst_nor_ps_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nor_ps_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_ps_p_p_p(rz, rz2, rz3, rz4)) } -inst_sel_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_sel_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_p_p(rz, rz2, rz3, rz4)) } -inst_orrs_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orrs_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pd_p_p_p(rz, rz2, rz3, rz4)) } -inst_eors_ph_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_eors_ph_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_ph_p_p_p(rz, rz2, rz3, rz4)) } -inst_nands_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nands_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pd_p_p_p(rz, rz2, rz3, rz4)) } -inst_nors_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nors_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pd_p_p_p(rz, rz2, rz3, rz4)) } -inst_orns_pd_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orns_pd_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pd_p_p_p(rz, rz2, rz3, rz4)) } +inst_nand_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nand_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_ps_p_ps_ps(rz, rz2, rz3, rz4)) } +inst_nor_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nor_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_ps_p_ps_ps(rz, rz2, rz3, rz4)) } +inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sel_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_orrs_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orrs_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pd_p_pd_pd(rz, rz2, rz3, rz4)) } +inst_eors_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eors_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_ph_p_ph_ph(rz, rz2, rz3, rz4)) } +inst_nands_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nands_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pd_p_pd_pd(rz, rz2, rz3, rz4)) } +inst_nors_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nors_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pd_p_pd_pd(rz, rz2, rz3, rz4)) } +inst_orns_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orns_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pd_p_pd_pd(rz, rz2, rz3, rz4)) } inst_movs_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_movs_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_ph_p_p(rz, rz2, rz3)) } inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } @@ -3565,28 +3565,28 @@ inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_ph_p_p(rz, rz2, rz3)) } -inst_pnext_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_p(rz, rz2, rz3)) } -inst_brka_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brka_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_p(rz, rz2, rz3)) } -inst_brkb_ps_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkb_ps_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_ps_p_p(rz, rz2, rz3)) } -inst_brkas_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkas_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_ph_p_p(rz, rz2, rz3)) } -inst_brkbs_pd_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkbs_pd_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pd_p_p(rz, rz2, rz3)) } -inst_brkpa_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpa_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkpb_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkpb_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_pb_p_p_p(rz, rz2, rz3, rz4)) } -inst_brkn_pb_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_brkn_pb_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_pb_p_p_p(rz, rz2, rz3, rz4)) } +inst_pfirst_ph_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_ph_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_ph_ph_ph(rz, rz2, rz3)) } +inst_pnext_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_pb_pb(rz, rz2, rz3)) } +inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } +inst_brkb_ps_p_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkb_ps_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_ps_p_ps(rz, rz2, rz3)) } +inst_brkas_ph_p_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkas_ph_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_ph_p_ph(rz, rz2, rz3)) } +inst_brkbs_pd_p_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkbs_pd_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pd_p_pd(rz, rz2, rz3)) } +inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpa_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkpb_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_brkn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_brkn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_rdffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_pb(rz)) } -inst_wrffr_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } -emit_wrffr_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_p(rz)) } +inst_wrffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_wrffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_pb(rz)) } inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } @@ -3749,10 +3749,10 @@ inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: emit_ld1sb_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zh_p_m(rz, rz2, mem)) } emit_ld1sb_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zs_p_m(rz, rz2, mem)) } emit_ld1sb_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zd_p_m(rz, rz2, mem)) } -inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -emit_ld1sh_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zs_p_m(rz, rz2, mem)) } +inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } emit_ld1sh_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zd_p_m(rz, rz2, mem)) } +emit_ld1sh_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zs_p_m(rz, rz2, mem)) } inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } emit_ld1sw_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_zd_p_m(rz, rz2, mem)) } inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } @@ -3805,22 +3805,70 @@ inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: emit_ldff1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_zs_p_m(rz, rz2, mem)) } inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } emit_ldff1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_zd_p_m(rz, rz2, mem)) } -inst_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_p_r_r(rz, src, src2)) } -inst_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_p_r_r(rz, src, src2)) } -inst_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_p_r_r(rz, src, src2)) } -inst_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_p_r_r(rz, src, src2)) } -inst_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_p_r_r(rz, src, src2)) } -inst_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_p_r_r(rz, src, src2)) } -inst_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_p_r_r(rz, src, src2)) } -inst_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -emit_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_p_r_r(rz, src, src2)) } +inst_whilege_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilege_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilege_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilege_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilege_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pb_r_r(rz, src, src2)) } +emit_whilege_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ph_r_r(rz, src, src2)) } +emit_whilege_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ps_r_r(rz, src, src2)) } +emit_whilege_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pd_r_r(rz, src, src2)) } +inst_whilegt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilegt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilegt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilegt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilegt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pb_r_r(rz, src, src2)) } +emit_whilegt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ph_r_r(rz, src, src2)) } +emit_whilegt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ps_r_r(rz, src, src2)) } +emit_whilegt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pd_r_r(rz, src, src2)) } +inst_whilele_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilele_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilele_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilele_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilele_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pb_r_r(rz, src, src2)) } +emit_whilele_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ph_r_r(rz, src, src2)) } +emit_whilele_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ps_r_r(rz, src, src2)) } +emit_whilele_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pd_r_r(rz, src, src2)) } +inst_whilelt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pb_r_r(rz, src, src2)) } +emit_whilelt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ph_r_r(rz, src, src2)) } +emit_whilelt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ps_r_r(rz, src, src2)) } +emit_whilelt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pd_r_r(rz, src, src2)) } +inst_whilehi_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehi_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehi_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehi_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehi_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pb_r_r(rz, src, src2)) } +emit_whilehi_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ph_r_r(rz, src, src2)) } +emit_whilehi_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ps_r_r(rz, src, src2)) } +emit_whilehi_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pd_r_r(rz, src, src2)) } +inst_whilehs_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehs_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehs_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehs_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilehs_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pb_r_r(rz, src, src2)) } +emit_whilehs_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ph_r_r(rz, src, src2)) } +emit_whilehs_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ps_r_r(rz, src, src2)) } +emit_whilehs_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pd_r_r(rz, src, src2)) } +inst_whilelo_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelo_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelo_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelo_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilelo_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pb_r_r(rz, src, src2)) } +emit_whilelo_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ph_r_r(rz, src, src2)) } +emit_whilelo_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ps_r_r(rz, src, src2)) } +emit_whilelo_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pd_r_r(rz, src, src2)) } +inst_whilels_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilels_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilels_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilels_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_whilels_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pb_r_r(rz, src, src2)) } +emit_whilels_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ph_r_r(rz, src, src2)) } +emit_whilels_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ps_r_r(rz, src, src2)) } +emit_whilels_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pd_r_r(rz, src, src2)) } inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } @@ -3963,10 +4011,34 @@ inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } +inst_index_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_zh_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_zh_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_zh_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_reg(src2), {}}} } +inst_index_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_zs_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_zs_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_zs_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_reg(src2), {}}} } +inst_index_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +inst_index_zd_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_reg(src), {}}} } +inst_index_zd_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_imm(imm, 1), {}}} } +inst_index_zd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_reg(src2), {}}} } emit_index_zb_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zb_i_i(rz, imm, imm2)) } emit_index_zb_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zb_i_r(rz, imm, src)) } emit_index_zb_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zb_r_i(rz, src, imm)) } emit_index_zb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zb_r_r(rz, src, src2)) } +emit_index_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zh_i_i(rz, imm, imm2)) } +emit_index_zh_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zh_i_r(rz, imm, src)) } +emit_index_zh_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zh_r_i(rz, src, imm)) } +emit_index_zh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zh_r_r(rz, src, src2)) } +emit_index_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zs_i_i(rz, imm, imm2)) } +emit_index_zs_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zs_i_r(rz, imm, src)) } +emit_index_zs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zs_r_i(rz, src, imm)) } +emit_index_zs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zs_r_r(rz, src, src2)) } +emit_index_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zd_i_i(rz, imm, imm2)) } +emit_index_zd_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zd_i_r(rz, imm, src)) } +emit_index_zd_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zd_r_i(rz, src, imm)) } +emit_index_zd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zd_r_r(rz, src, src2)) } inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } emit_bsl1n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } @@ -4336,18 +4408,18 @@ inst_adrp :: inst_adrp_r_l emit_adrp :: emit_adrp_r_l inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_v16b_v16b_v16b, inst_and_zb_p_zb_zb } emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_v16b_v16b_v16b, emit_and_zb_p_zb_zb } -inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_ph_p_p_p } -emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_ph_p_p_p } +inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_ph_p_ph_ph } +emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_ph_p_ph_ph } inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_v16b_v16b_v16b, inst_orr_zb_p_zb_zb } emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_v16b_v16b_v16b, emit_orr_zb_p_zb_zb } inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_v16b_v16b_v16b, inst_eor_zb_p_zb_zb } emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_v16b_v16b_v16b, emit_eor_zb_p_zb_zb } inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_v16b_v16b_v16b, inst_bic_zb_p_zb_zb } emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_v16b_v16b_v16b, emit_bic_zb_p_zb_zb } -inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_ph_p_p_p } -emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_ph_p_p_p } -inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_ps_p_p_p } -emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_ps_p_p_p } +inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_ph_p_ph_ph } +emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_ph_p_ph_ph } +inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_ps_p_ps_ps } +emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_ps_p_ps_ps } inst_eon :: inst_eon_r_r_sh emit_eon :: emit_eon_r_r_sh inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_zb_p_zb_zb, inst_lsl_r_r_i } @@ -4464,10 +4536,10 @@ inst_tbz :: inst_tbz_r_i_l emit_tbz :: emit_tbz_r_i_l inst_tbnz :: inst_tbnz_r_i_l emit_tbnz :: emit_tbnz_r_i_l -inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_zb_m, inst_ldr_i_m } -emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_zb_m, emit_ldr_i_m } -inst_str :: proc{ inst_str_r_m, inst_str_zb_m, inst_str_i_m } -emit_str :: proc{ emit_str_r_m, emit_str_zb_m, emit_str_i_m } +inst_ldr :: proc{ inst_ldr_r_m, inst_ldr_r_l, inst_ldr_z_m, inst_ldr_i_m } +emit_ldr :: proc{ emit_ldr_r_m, emit_ldr_r_l, emit_ldr_z_m, emit_ldr_i_m } +inst_str :: proc{ inst_str_r_m, inst_str_z_m, inst_str_i_m } +emit_str :: proc{ emit_str_r_m, emit_str_z_m, emit_str_i_m } inst_ldrb :: inst_ldrb_r_m emit_ldrb :: emit_ldrb_r_m inst_strb :: inst_strb_r_m @@ -5368,8 +5440,8 @@ inst_trn1 :: proc{ inst_trn1_v8b_v8b_v8b, inst_trn1_zb_ emit_trn1 :: proc{ emit_trn1_v8b_v8b_v8b, emit_trn1_zb_zb_zb } inst_trn2 :: proc{ inst_trn2_v8b_v8b_v8b, inst_trn2_zb_zb_zb } emit_trn2 :: proc{ emit_trn2_v8b_v8b_v8b, emit_trn2_zb_zb_zb } -inst_not :: proc{ inst_not_v8b_v8b, inst_not_pb_p_p } -emit_not :: proc{ emit_not_v8b_v8b, emit_not_pb_p_p } +inst_not :: proc{ inst_not_v8b_v8b, inst_not_pb_p_pb } +emit_not :: proc{ emit_not_v8b_v8b, emit_not_pb_p_pb } inst_rev64 :: inst_rev64_v8b_v8b emit_rev64 :: emit_rev64_v8b_v8b inst_cnt :: proc{ inst_cnt_v8b_v8b, inst_cnt_zb_p_zb } @@ -5424,22 +5496,22 @@ inst_fnmla :: inst_fnmla_zh_p_zh_zh emit_fnmla :: emit_fnmla_zh_p_zh_zh inst_fnmls :: inst_fnmls_zh_p_zh_zh emit_fnmls :: emit_fnmls_zh_p_zh_zh -inst_nand :: inst_nand_ps_p_p_p -emit_nand :: emit_nand_ps_p_p_p -inst_nor :: inst_nor_ps_p_p_p -emit_nor :: emit_nor_ps_p_p_p -inst_sel :: inst_sel_pb_p_p_p -emit_sel :: emit_sel_pb_p_p_p -inst_orrs :: inst_orrs_pd_p_p_p -emit_orrs :: emit_orrs_pd_p_p_p -inst_eors :: inst_eors_ph_p_p_p -emit_eors :: emit_eors_ph_p_p_p -inst_nands :: inst_nands_pd_p_p_p -emit_nands :: emit_nands_pd_p_p_p -inst_nors :: inst_nors_pd_p_p_p -emit_nors :: emit_nors_pd_p_p_p -inst_orns :: inst_orns_pd_p_p_p -emit_orns :: emit_orns_pd_p_p_p +inst_nand :: inst_nand_ps_p_ps_ps +emit_nand :: emit_nand_ps_p_ps_ps +inst_nor :: inst_nor_ps_p_ps_ps +emit_nor :: emit_nor_ps_p_ps_ps +inst_sel :: inst_sel_pb_p_pb_pb +emit_sel :: emit_sel_pb_p_pb_pb +inst_orrs :: inst_orrs_pd_p_pd_pd +emit_orrs :: emit_orrs_pd_p_pd_pd +inst_eors :: inst_eors_ph_p_ph_ph +emit_eors :: emit_eors_ph_p_ph_ph +inst_nands :: inst_nands_pd_p_pd_pd +emit_nands :: emit_nands_pd_p_pd_pd +inst_nors :: inst_nors_pd_p_pd_pd +emit_nors :: emit_nors_pd_p_pd_pd +inst_orns :: inst_orns_pd_p_pd_pd +emit_orns :: emit_orns_pd_p_pd_pd inst_movs :: inst_movs_ph_p_p emit_movs :: emit_movs_ph_p_p inst_ptrue :: inst_ptrue_pb_i @@ -5448,28 +5520,28 @@ inst_ptrues :: inst_ptrues_pb_i emit_ptrues :: emit_ptrues_pb_i inst_pfalse :: inst_pfalse_pb emit_pfalse :: emit_pfalse_pb -inst_pfirst :: inst_pfirst_ph_p_p -emit_pfirst :: emit_pfirst_ph_p_p -inst_pnext :: inst_pnext_pb_p_p -emit_pnext :: emit_pnext_pb_p_p -inst_brka :: inst_brka_pb_p_p -emit_brka :: emit_brka_pb_p_p -inst_brkb :: inst_brkb_ps_p_p -emit_brkb :: emit_brkb_ps_p_p -inst_brkas :: inst_brkas_ph_p_p -emit_brkas :: emit_brkas_ph_p_p -inst_brkbs :: inst_brkbs_pd_p_p -emit_brkbs :: emit_brkbs_pd_p_p -inst_brkpa :: inst_brkpa_pb_p_p_p -emit_brkpa :: emit_brkpa_pb_p_p_p -inst_brkpb :: inst_brkpb_pb_p_p_p -emit_brkpb :: emit_brkpb_pb_p_p_p -inst_brkn :: inst_brkn_pb_p_p_p -emit_brkn :: emit_brkn_pb_p_p_p +inst_pfirst :: inst_pfirst_ph_ph_ph +emit_pfirst :: emit_pfirst_ph_ph_ph +inst_pnext :: inst_pnext_pb_pb_pb +emit_pnext :: emit_pnext_pb_pb_pb +inst_brka :: inst_brka_pb_p_pb +emit_brka :: emit_brka_pb_p_pb +inst_brkb :: inst_brkb_ps_p_ps +emit_brkb :: emit_brkb_ps_p_ps +inst_brkas :: inst_brkas_ph_p_ph +emit_brkas :: emit_brkas_ph_p_ph +inst_brkbs :: inst_brkbs_pd_p_pd +emit_brkbs :: emit_brkbs_pd_p_pd +inst_brkpa :: inst_brkpa_pb_p_pb_pb +emit_brkpa :: emit_brkpa_pb_p_pb_pb +inst_brkpb :: inst_brkpb_pb_p_pb_pb +emit_brkpb :: emit_brkpb_pb_p_pb_pb +inst_brkn :: inst_brkn_pb_p_pb_pb +emit_brkn :: emit_brkn_pb_p_pb_pb inst_rdffr :: inst_rdffr_pb emit_rdffr :: emit_rdffr_pb -inst_wrffr :: inst_wrffr_p -emit_wrffr :: emit_wrffr_p +inst_wrffr :: inst_wrffr_pb +emit_wrffr :: emit_wrffr_pb inst_setffr :: inst_setffr_none emit_setffr :: emit_setffr_none inst_cmpeq :: inst_cmpeq_pb_p_zb_zb @@ -5512,8 +5584,8 @@ inst_ld1d :: proc{ inst_ld1d_zd_p_m, inst_ld1d_i_p_m } emit_ld1d :: proc{ emit_ld1d_zd_p_m, emit_ld1d_i_p_m } inst_ld1sb :: inst_ld1sb_zh_p_m emit_ld1sb :: emit_ld1sb_zh_p_m -inst_ld1sh :: inst_ld1sh_zs_p_m -emit_ld1sh :: emit_ld1sh_zs_p_m +inst_ld1sh :: inst_ld1sh_zd_p_m +emit_ld1sh :: emit_ld1sh_zd_p_m inst_ld1sw :: inst_ld1sw_zd_p_m emit_ld1sw :: emit_ld1sw_zd_p_m inst_st1b :: proc{ inst_st1b_zb_p_m, inst_st1b_i_p_m } @@ -5532,22 +5604,22 @@ inst_ldff1w :: inst_ldff1w_zs_p_m emit_ldff1w :: emit_ldff1w_zs_p_m inst_ldff1d :: inst_ldff1d_zd_p_m emit_ldff1d :: emit_ldff1d_zd_p_m -inst_whilege :: inst_whilege_p_r_r -emit_whilege :: emit_whilege_p_r_r -inst_whilegt :: inst_whilegt_p_r_r -emit_whilegt :: emit_whilegt_p_r_r -inst_whilele :: inst_whilele_p_r_r -emit_whilele :: emit_whilele_p_r_r -inst_whilelt :: inst_whilelt_p_r_r -emit_whilelt :: emit_whilelt_p_r_r -inst_whilehi :: inst_whilehi_p_r_r -emit_whilehi :: emit_whilehi_p_r_r -inst_whilehs :: inst_whilehs_p_r_r -emit_whilehs :: emit_whilehs_p_r_r -inst_whilelo :: inst_whilelo_p_r_r -emit_whilelo :: emit_whilelo_p_r_r -inst_whilels :: inst_whilels_p_r_r -emit_whilels :: emit_whilels_p_r_r +inst_whilege :: inst_whilege_pb_r_r +emit_whilege :: emit_whilege_pb_r_r +inst_whilegt :: inst_whilegt_pb_r_r +emit_whilegt :: emit_whilegt_pb_r_r +inst_whilele :: inst_whilele_pb_r_r +emit_whilele :: emit_whilele_pb_r_r +inst_whilelt :: inst_whilelt_pb_r_r +emit_whilelt :: emit_whilelt_pb_r_r +inst_whilehi :: inst_whilehi_pb_r_r +emit_whilehi :: emit_whilehi_pb_r_r +inst_whilehs :: inst_whilehs_pb_r_r +emit_whilehs :: emit_whilehs_pb_r_r +inst_whilelo :: inst_whilelo_pb_r_r +emit_whilelo :: emit_whilelo_pb_r_r +inst_whilels :: inst_whilels_pb_r_r +emit_whilels :: emit_whilels_pb_r_r inst_sqrdmlah :: inst_sqrdmlah_zb_zb_zb emit_sqrdmlah :: emit_sqrdmlah_zb_zb_zb inst_sqrdmlsh :: inst_sqrdmlsh_zb_zb_zb diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 681ec4c4b..de07fe5f3 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -77,7 +77,7 @@ Memory :: bit_field u64 { extend: Extend | 3, // for EXT_REG_OFFSET; UXTX otherwise shift: u8 | 3, // 0..4 for register-offset / extended mode: Address_Mode | 3, - // 1 bit spare + // Full: 16 + 16 + 23 + 3 + 3 + 3 = 64. } #assert(size_of(Memory) == 8) diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 8bb94c1e1..1967b8071 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -570,7 +570,7 @@ write_operand :: proc( } case .MEMORY: - write_memory(sb, op.mem, opts) + write_memory(sb, op.mem, op.size, opts) case .RELATIVE: target := u32(op.relative) @@ -583,7 +583,9 @@ write_operand :: proc( } @(private="file") -write_memory :: proc(sb: ^strings.Builder, m: Memory, opts: ^Print_Options) { +// `index_shape` names the element size of a vector index (SVE gather), which +// Memory has no room left to carry; it is 0 for every ordinary addressing mode. +write_memory :: proc(sb: ^strings.Builder, m: Memory, index_shape: u8, opts: ^Print_Options) { strings.write_byte(sb, '[') write_register(sb, m.base, opts.uppercase) @@ -615,6 +617,9 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory, opts: ^Print_Options) { case .REG_OFFSET: strings.write_string(sb, ", ") write_register(sb, m.index, opts.uppercase) + if reg_class(m.index) == REG_Z { + write_vector_shape(sb, m.index, index_shape, opts.uppercase) + } if m.shift != 0 { strings.write_string(sb, ", lsl #") write_decimal_u32(sb, u32(m.shift)) @@ -624,6 +629,9 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory, opts: ^Print_Options) { case .EXT_REG_OFFSET: strings.write_string(sb, ", ") write_register(sb, m.index, opts.uppercase) + if reg_class(m.index) == REG_Z { + write_vector_shape(sb, m.index, index_shape, opts.uppercase) + } strings.write_string(sb, ", ") strings.write_string(sb, EXTEND_NAMES[u8(m.extend) & 0x7]) if m.shift != 0 { diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index f5b00d293..85309d3ac 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2512]lib.Decode_Entry{ +DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -93,12 +93,12 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, - { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, - { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .PFIRST, {.P_REG_H,.P_REG_H,.P_REG_H,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -122,11 +122,11 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG_S,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -252,12 +252,12 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -300,6 +300,38 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, @@ -414,10 +446,22 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -434,28 +478,20 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, @@ -468,12 +504,12 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, @@ -521,8 +557,8 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, @@ -577,25 +613,25 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -2526,18 +2562,18 @@ DECODE_ENTRIES := [2512]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 81}, - 0x02 = { 81, 506}, - 0x04 = { 587, 76}, - 0x05 = { 663, 50}, - 0x06 = { 713, 56}, - 0x07 = { 769, 1058}, - 0x08 = {1827, 16}, - 0x09 = {1843, 34}, - 0x0A = {1877, 130}, - 0x0B = {2007, 21}, - 0x0C = {2028, 167}, - 0x0D = {2195, 122}, - 0x0E = {2317, 19}, - 0x0F = {2336, 176}, + 0x02 = { 81, 542}, + 0x04 = { 623, 76}, + 0x05 = { 699, 50}, + 0x06 = { 749, 56}, + 0x07 = { 805, 1058}, + 0x08 = {1863, 16}, + 0x09 = {1879, 34}, + 0x0A = {1913, 130}, + 0x0B = {2043, 21}, + 0x0C = {2064, 167}, + 0x0D = {2231, 122}, + 0x0E = {2353, 19}, + 0x0F = {2372, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 1a31c00d0..8f87113f4 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2510]lib.Encoding{ +ENCODE_FORMS := [2546]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -87,13 +87,13 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -104,7 +104,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -115,7 +115,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -124,16 +124,16 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -243,7 +243,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -384,8 +384,8 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -401,8 +401,8 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2457,7 +2457,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2470,7 +2470,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2483,7 +2483,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2496,7 +2496,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2509,7 +2509,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2522,11 +2522,11 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -2663,21 +2663,21 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE @@ -2687,27 +2687,27 @@ ENCODE_FORMS := [2510]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_H,.P_REG_H,.P_REG_H,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG_S,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR - { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ @@ -2783,67 +2783,67 @@ ENCODE_FORMS := [2510]lib.Encoding{ { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, @@ -2856,21 +2856,45 @@ ENCODE_FORMS := [2510]lib.Encoding{ // .LDFF1D { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELE - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELO - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELS - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .SQRDMLAH { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, @@ -2986,10 +3010,22 @@ ENCODE_FORMS := [2510]lib.Encoding{ // .SPLICE { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, // .BSL1N { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .BSL2N @@ -3342,7 +3378,7 @@ ENCODE_FORMS := [2510]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2510]lib.Clobber{ +CLOBBER_FORMS := [2546]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -6191,20 +6227,44 @@ CLOBBER_FORMS := [2510]lib.Clobber{ {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, // .WHILEGE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEGT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEHI {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEHS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELO {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .SQRDMLAH {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, @@ -6321,9 +6381,21 @@ CLOBBER_FORMS := [2510]lib.Clobber{ {written={0}, read={1, 2, 3}}, // .INDEX {written={0}}, - {written={0}, read={2}}, - {written={0}, read={1}}, - {written={0}, read={1, 2}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, + {written={0}}, // .BSL1N {written={0}, read={1, 2, 3}}, // .BSL2N @@ -7286,216 +7358,216 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .LDFF1H = { 2235, 1}, .LDFF1W = { 2236, 1}, .LDFF1D = { 2237, 1}, - .WHILEGE = { 2238, 1}, - .WHILEGT = { 2239, 1}, - .WHILELE = { 2240, 1}, - .WHILELT = { 2241, 1}, - .WHILEHI = { 2242, 1}, - .WHILEHS = { 2243, 1}, - .WHILELO = { 2244, 1}, - .WHILELS = { 2245, 1}, - .SQRDMLAH = { 2246, 4}, - .SQRDMLSH = { 2250, 4}, - .ADCLB = { 2254, 2}, - .ADCLT = { 2256, 2}, - .SBCLB = { 2258, 2}, - .SBCLT = { 2260, 2}, - .TBL2 = { 2262, 1}, - .MATCH = { 2263, 2}, - .NMATCH = { 2265, 2}, - .HISTCNT = { 2267, 2}, - .HISTSEG = { 2269, 1}, - .SMSTART = { 2270, 1}, - .SMSTOP = { 2271, 1}, - .RDSVL = { 2272, 1}, - .ADDHA = { 2273, 1}, - .ADDVA = { 2274, 1}, - .ZERO = { 2275, 1}, - .FMOPA = { 2276, 1}, - .FMOPS = { 2277, 1}, - .BFMOPA = { 2278, 1}, - .BFMOPS = { 2279, 1}, - .SMOPA = { 2280, 2}, - .SMOPS = { 2282, 2}, - .UMOPA = { 2284, 2}, - .UMOPS = { 2286, 2}, - .USMOPA = { 2288, 1}, - .SUMOPA = { 2289, 1}, - .LD1Q = { 2290, 1}, - .ST1Q = { 2291, 1}, - .MOVA = { 2292, 2}, - .FCMLA = { 2294, 4}, - .FCADD = { 2298, 4}, - .PRFB = { 2302, 1}, - .PRFH = { 2303, 1}, - .PRFW = { 2304, 1}, - .PRFD = { 2305, 1}, - .LDNT1B = { 2306, 1}, - .LDNT1H = { 2307, 1}, - .LDNT1W = { 2308, 1}, - .LDNT1D = { 2309, 1}, - .STNT1B = { 2310, 1}, - .STNT1H = { 2311, 1}, - .STNT1W = { 2312, 1}, - .STNT1D = { 2313, 1}, - .SPLICE = { 2314, 1}, - .INDEX = { 2315, 4}, - .BSL1N = { 2319, 1}, - .BSL2N = { 2320, 1}, - .NBSL = { 2321, 1}, - .PMUL = { 2322, 1}, - .PMULLB = { 2323, 1}, - .PMULLT = { 2324, 1}, - .BFCVTNT = { 2325, 1}, - .LDRAA = { 2326, 2}, - .LDRAB = { 2328, 2}, - .TSTART = { 2330, 1}, - .TCOMMIT = { 2331, 1}, - .TCANCEL = { 2332, 1}, - .TTEST = { 2333, 1}, - .WFET = { 2334, 1}, - .WFIT = { 2335, 1}, - .BC_EQ = { 2336, 1}, - .BC_NE = { 2337, 1}, - .BC_CS = { 2338, 1}, - .BC_CC = { 2339, 1}, - .BC_MI = { 2340, 1}, - .BC_PL = { 2341, 1}, - .BC_VS = { 2342, 1}, - .BC_VC = { 2343, 1}, - .BC_HI = { 2344, 1}, - .BC_LS = { 2345, 1}, - .BC_GE = { 2346, 1}, - .BC_LT = { 2347, 1}, - .BC_GT = { 2348, 1}, - .BC_LE = { 2349, 1}, - .BC_AL = { 2350, 1}, - .BC_NV = { 2351, 1}, - .UXTB = { 2352, 1}, - .UXTH = { 2353, 1}, - .UXTW = { 2354, 1}, - .SXTB = { 2355, 1}, - .SXTH = { 2356, 1}, - .SXTW = { 2357, 1}, - .ADC = { 2358, 2}, - .ADCS = { 2360, 2}, - .SBC = { 2362, 2}, - .SBCS = { 2364, 2}, - .NGC = { 2366, 2}, - .NGCS = { 2368, 2}, - .LDAPUR = { 2370, 2}, - .STLUR = { 2372, 2}, - .LDAPURB = { 2374, 1}, - .STLURB = { 2375, 1}, - .LDAPURH = { 2376, 1}, - .STLURH = { 2377, 1}, - .LDAPURSB = { 2378, 2}, - .LDAPURSH = { 2380, 2}, - .LDAPURSW = { 2382, 1}, - .BFADD = { 2383, 2}, - .BFSUB = { 2385, 2}, - .BFMUL = { 2387, 2}, - .BFMLA = { 2389, 1}, - .BFMLS = { 2390, 1}, - .SB = { 2391, 1}, - .CSDB = { 2392, 1}, - .DGH = { 2393, 1}, - .PSB_CSYNC = { 2394, 1}, - .TSB_CSYNC = { 2395, 1}, - .BTI_J = { 2396, 1}, - .BTI_C = { 2397, 1}, - .BTI_JC = { 2398, 1}, - .BFCLAMP = { 2399, 1}, - .BFMAXNM = { 2400, 1}, - .BFMINNM = { 2401, 1}, - .LUTI2 = { 2402, 3}, - .LUTI4 = { 2405, 3}, - .ZIP = { 2408, 2}, - .UZP = { 2410, 2}, - .TLBI_RPALOS = { 2412, 1}, - .TLBI_RPAOS = { 2413, 1}, - .AT_S1E1A = { 2414, 1}, - .DC_CIPAPA = { 2415, 1}, - .DC_CIGDPAPA = { 2416, 1}, - .TLBI_PAALL = { 2417, 1}, - .TLBI_PAALLOS = { 2418, 1}, - .AMX_LDX = { 2419, 1}, - .AMX_LDY = { 2420, 1}, - .AMX_STX = { 2421, 1}, - .AMX_STY = { 2422, 1}, - .AMX_LDZ = { 2423, 1}, - .AMX_STZ = { 2424, 1}, - .AMX_LDZI = { 2425, 1}, - .AMX_STZI = { 2426, 1}, - .AMX_EXTRX = { 2427, 1}, - .AMX_EXTRY = { 2428, 1}, - .AMX_FMA64 = { 2429, 1}, - .AMX_FMS64 = { 2430, 1}, - .AMX_FMA32 = { 2431, 1}, - .AMX_FMS32 = { 2432, 1}, - .AMX_MAC16 = { 2433, 1}, - .AMX_FMA16 = { 2434, 1}, - .AMX_FMS16 = { 2435, 1}, - .AMX_SET = { 2436, 1}, - .AMX_CLR = { 2437, 1}, - .AMX_VECINT = { 2438, 1}, - .AMX_VECFP = { 2439, 1}, - .AMX_MATINT = { 2440, 1}, - .AMX_MATFP = { 2441, 1}, - .AMX_GENLUT = { 2442, 1}, - .CPYP = { 2443, 1}, - .CPYM = { 2444, 1}, - .CPYE = { 2445, 1}, - .CPYFP = { 2446, 1}, - .CPYFM = { 2447, 1}, - .CPYFE = { 2448, 1}, - .SETP = { 2449, 1}, - .SETM = { 2450, 1}, - .SETE = { 2451, 1}, - .DC_IVAC = { 2452, 1}, - .DC_ISW = { 2453, 1}, - .DC_CSW = { 2454, 1}, - .DC_CISW = { 2455, 1}, - .DC_ZVA = { 2456, 1}, - .DC_CVAC = { 2457, 1}, - .DC_CVAU = { 2458, 1}, - .DC_CIVAC = { 2459, 1}, - .IC_IALLUIS = { 2460, 1}, - .IC_IALLU = { 2461, 1}, - .IC_IVAU = { 2462, 1}, - .AT_S1E1R = { 2463, 1}, - .AT_S1E1W = { 2464, 1}, - .AT_S1E0R = { 2465, 1}, - .AT_S1E0W = { 2466, 1}, - .AT_S1E2R = { 2467, 1}, - .AT_S1E2W = { 2468, 1}, - .AT_S1E3R = { 2469, 1}, - .AT_S1E3W = { 2470, 1}, - .AT_S12E1R = { 2471, 1}, - .AT_S12E1W = { 2472, 1}, - .AT_S12E0R = { 2473, 1}, - .AT_S12E0W = { 2474, 1}, - .TLBI_VMALLE1 = { 2475, 1}, - .TLBI_VMALLE1IS = { 2476, 1}, - .TLBI_VAE1 = { 2477, 1}, - .TLBI_VAE1IS = { 2478, 1}, - .TLBI_ASIDE1 = { 2479, 1}, - .TLBI_ASIDE1IS = { 2480, 1}, - .TLBI_VAAE1 = { 2481, 1}, - .TLBI_VAAE1IS = { 2482, 1}, - .TLBI_VALE1 = { 2483, 1}, - .TLBI_VALE1IS = { 2484, 1}, - .TLBI_VAALE1 = { 2485, 1}, - .TLBI_VAALE1IS = { 2486, 1}, - .TLBI_ALLE1 = { 2487, 1}, - .TLBI_ALLE1IS = { 2488, 1}, - .TLBI_ALLE2 = { 2489, 1}, - .TLBI_ALLE2IS = { 2490, 1}, - .TLBI_ALLE3 = { 2491, 1}, - .TLBI_ALLE3IS = { 2492, 1}, - .PRFM = { 2493, 2}, - .PRFUM = { 2495, 1}, - .NEGS = { 2496, 2}, - .CMP = { 2498, 6}, - .CMN = { 2504, 6}, + .WHILEGE = { 2238, 4}, + .WHILEGT = { 2242, 4}, + .WHILELE = { 2246, 4}, + .WHILELT = { 2250, 4}, + .WHILEHI = { 2254, 4}, + .WHILEHS = { 2258, 4}, + .WHILELO = { 2262, 4}, + .WHILELS = { 2266, 4}, + .SQRDMLAH = { 2270, 4}, + .SQRDMLSH = { 2274, 4}, + .ADCLB = { 2278, 2}, + .ADCLT = { 2280, 2}, + .SBCLB = { 2282, 2}, + .SBCLT = { 2284, 2}, + .TBL2 = { 2286, 1}, + .MATCH = { 2287, 2}, + .NMATCH = { 2289, 2}, + .HISTCNT = { 2291, 2}, + .HISTSEG = { 2293, 1}, + .SMSTART = { 2294, 1}, + .SMSTOP = { 2295, 1}, + .RDSVL = { 2296, 1}, + .ADDHA = { 2297, 1}, + .ADDVA = { 2298, 1}, + .ZERO = { 2299, 1}, + .FMOPA = { 2300, 1}, + .FMOPS = { 2301, 1}, + .BFMOPA = { 2302, 1}, + .BFMOPS = { 2303, 1}, + .SMOPA = { 2304, 2}, + .SMOPS = { 2306, 2}, + .UMOPA = { 2308, 2}, + .UMOPS = { 2310, 2}, + .USMOPA = { 2312, 1}, + .SUMOPA = { 2313, 1}, + .LD1Q = { 2314, 1}, + .ST1Q = { 2315, 1}, + .MOVA = { 2316, 2}, + .FCMLA = { 2318, 4}, + .FCADD = { 2322, 4}, + .PRFB = { 2326, 1}, + .PRFH = { 2327, 1}, + .PRFW = { 2328, 1}, + .PRFD = { 2329, 1}, + .LDNT1B = { 2330, 1}, + .LDNT1H = { 2331, 1}, + .LDNT1W = { 2332, 1}, + .LDNT1D = { 2333, 1}, + .STNT1B = { 2334, 1}, + .STNT1H = { 2335, 1}, + .STNT1W = { 2336, 1}, + .STNT1D = { 2337, 1}, + .SPLICE = { 2338, 1}, + .INDEX = { 2339, 16}, + .BSL1N = { 2355, 1}, + .BSL2N = { 2356, 1}, + .NBSL = { 2357, 1}, + .PMUL = { 2358, 1}, + .PMULLB = { 2359, 1}, + .PMULLT = { 2360, 1}, + .BFCVTNT = { 2361, 1}, + .LDRAA = { 2362, 2}, + .LDRAB = { 2364, 2}, + .TSTART = { 2366, 1}, + .TCOMMIT = { 2367, 1}, + .TCANCEL = { 2368, 1}, + .TTEST = { 2369, 1}, + .WFET = { 2370, 1}, + .WFIT = { 2371, 1}, + .BC_EQ = { 2372, 1}, + .BC_NE = { 2373, 1}, + .BC_CS = { 2374, 1}, + .BC_CC = { 2375, 1}, + .BC_MI = { 2376, 1}, + .BC_PL = { 2377, 1}, + .BC_VS = { 2378, 1}, + .BC_VC = { 2379, 1}, + .BC_HI = { 2380, 1}, + .BC_LS = { 2381, 1}, + .BC_GE = { 2382, 1}, + .BC_LT = { 2383, 1}, + .BC_GT = { 2384, 1}, + .BC_LE = { 2385, 1}, + .BC_AL = { 2386, 1}, + .BC_NV = { 2387, 1}, + .UXTB = { 2388, 1}, + .UXTH = { 2389, 1}, + .UXTW = { 2390, 1}, + .SXTB = { 2391, 1}, + .SXTH = { 2392, 1}, + .SXTW = { 2393, 1}, + .ADC = { 2394, 2}, + .ADCS = { 2396, 2}, + .SBC = { 2398, 2}, + .SBCS = { 2400, 2}, + .NGC = { 2402, 2}, + .NGCS = { 2404, 2}, + .LDAPUR = { 2406, 2}, + .STLUR = { 2408, 2}, + .LDAPURB = { 2410, 1}, + .STLURB = { 2411, 1}, + .LDAPURH = { 2412, 1}, + .STLURH = { 2413, 1}, + .LDAPURSB = { 2414, 2}, + .LDAPURSH = { 2416, 2}, + .LDAPURSW = { 2418, 1}, + .BFADD = { 2419, 2}, + .BFSUB = { 2421, 2}, + .BFMUL = { 2423, 2}, + .BFMLA = { 2425, 1}, + .BFMLS = { 2426, 1}, + .SB = { 2427, 1}, + .CSDB = { 2428, 1}, + .DGH = { 2429, 1}, + .PSB_CSYNC = { 2430, 1}, + .TSB_CSYNC = { 2431, 1}, + .BTI_J = { 2432, 1}, + .BTI_C = { 2433, 1}, + .BTI_JC = { 2434, 1}, + .BFCLAMP = { 2435, 1}, + .BFMAXNM = { 2436, 1}, + .BFMINNM = { 2437, 1}, + .LUTI2 = { 2438, 3}, + .LUTI4 = { 2441, 3}, + .ZIP = { 2444, 2}, + .UZP = { 2446, 2}, + .TLBI_RPALOS = { 2448, 1}, + .TLBI_RPAOS = { 2449, 1}, + .AT_S1E1A = { 2450, 1}, + .DC_CIPAPA = { 2451, 1}, + .DC_CIGDPAPA = { 2452, 1}, + .TLBI_PAALL = { 2453, 1}, + .TLBI_PAALLOS = { 2454, 1}, + .AMX_LDX = { 2455, 1}, + .AMX_LDY = { 2456, 1}, + .AMX_STX = { 2457, 1}, + .AMX_STY = { 2458, 1}, + .AMX_LDZ = { 2459, 1}, + .AMX_STZ = { 2460, 1}, + .AMX_LDZI = { 2461, 1}, + .AMX_STZI = { 2462, 1}, + .AMX_EXTRX = { 2463, 1}, + .AMX_EXTRY = { 2464, 1}, + .AMX_FMA64 = { 2465, 1}, + .AMX_FMS64 = { 2466, 1}, + .AMX_FMA32 = { 2467, 1}, + .AMX_FMS32 = { 2468, 1}, + .AMX_MAC16 = { 2469, 1}, + .AMX_FMA16 = { 2470, 1}, + .AMX_FMS16 = { 2471, 1}, + .AMX_SET = { 2472, 1}, + .AMX_CLR = { 2473, 1}, + .AMX_VECINT = { 2474, 1}, + .AMX_VECFP = { 2475, 1}, + .AMX_MATINT = { 2476, 1}, + .AMX_MATFP = { 2477, 1}, + .AMX_GENLUT = { 2478, 1}, + .CPYP = { 2479, 1}, + .CPYM = { 2480, 1}, + .CPYE = { 2481, 1}, + .CPYFP = { 2482, 1}, + .CPYFM = { 2483, 1}, + .CPYFE = { 2484, 1}, + .SETP = { 2485, 1}, + .SETM = { 2486, 1}, + .SETE = { 2487, 1}, + .DC_IVAC = { 2488, 1}, + .DC_ISW = { 2489, 1}, + .DC_CSW = { 2490, 1}, + .DC_CISW = { 2491, 1}, + .DC_ZVA = { 2492, 1}, + .DC_CVAC = { 2493, 1}, + .DC_CVAU = { 2494, 1}, + .DC_CIVAC = { 2495, 1}, + .IC_IALLUIS = { 2496, 1}, + .IC_IALLU = { 2497, 1}, + .IC_IVAU = { 2498, 1}, + .AT_S1E1R = { 2499, 1}, + .AT_S1E1W = { 2500, 1}, + .AT_S1E0R = { 2501, 1}, + .AT_S1E0W = { 2502, 1}, + .AT_S1E2R = { 2503, 1}, + .AT_S1E2W = { 2504, 1}, + .AT_S1E3R = { 2505, 1}, + .AT_S1E3W = { 2506, 1}, + .AT_S12E1R = { 2507, 1}, + .AT_S12E1W = { 2508, 1}, + .AT_S12E0R = { 2509, 1}, + .AT_S12E0W = { 2510, 1}, + .TLBI_VMALLE1 = { 2511, 1}, + .TLBI_VMALLE1IS = { 2512, 1}, + .TLBI_VAE1 = { 2513, 1}, + .TLBI_VAE1IS = { 2514, 1}, + .TLBI_ASIDE1 = { 2515, 1}, + .TLBI_ASIDE1IS = { 2516, 1}, + .TLBI_VAAE1 = { 2517, 1}, + .TLBI_VAAE1IS = { 2518, 1}, + .TLBI_VALE1 = { 2519, 1}, + .TLBI_VALE1IS = { 2520, 1}, + .TLBI_VAALE1 = { 2521, 1}, + .TLBI_VAALE1IS = { 2522, 1}, + .TLBI_ALLE1 = { 2523, 1}, + .TLBI_ALLE1IS = { 2524, 1}, + .TLBI_ALLE2 = { 2525, 1}, + .TLBI_ALLE2IS = { 2526, 1}, + .TLBI_ALLE3 = { 2527, 1}, + .TLBI_ALLE3IS = { 2528, 1}, + .PRFM = { 2529, 2}, + .PRFUM = { 2531, 1}, + .NEGS = { 2532, 2}, + .CMP = { 2534, 6}, + .CMN = { 2540, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 66692ee65..6ce97f788 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -191,14 +191,14 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ANDS = { {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -210,7 +210,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EOR = { {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -222,7 +222,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BIC = { {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -232,18 +232,18 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BICS = { {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EON = { {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -372,7 +372,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, }, .REV16 = { {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, @@ -553,8 +553,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, }, .STR = { @@ -571,8 +571,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, }, .LDRB = { @@ -3072,7 +3072,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .ZIP2 = { {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3086,7 +3086,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP1 = { {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3100,7 +3100,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .UZP2 = { {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3114,7 +3114,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN1 = { {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3128,7 +3128,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .TRN2 = { {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, @@ -3142,12 +3142,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .NOT = { {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .REV64 = { {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, @@ -3312,28 +3312,28 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG_B, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { {{.MOVS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -3348,37 +3348,37 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_H, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_H, .P_REG_H, .P_REG_H, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG_S, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .RDFFR = { {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, }, .SETFFR = { {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, @@ -3471,77 +3471,77 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .LD1B = { {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4C08000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, @@ -3559,28 +3559,52 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, @@ -3742,10 +3766,22 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, }, .BSL1N = { {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index 838031ed313c99e96865a2bab13764a9061cc3bf..532dc748c70dc297e33010ce7e14eda6e906cbe0 100644 GIT binary patch delta 74 zcmX>yiD}O?rVUrCCihplp<#>3<^Ca)*ZV6?^sSiOU1GiYU-fFH$qQO$PQH+9IXRY9 SYqGtg!Q}si9Ggw+`MCfw@FA)I delta 53 zcmV-50LuTomIB0*0Xb{!2XT_ zq_dzF0U=F5yk@F(@0*^I`2|)oivcpM7PM>g3#ps;{owUzsa5~)zF_|mfZBc*i(W5 zS%+plF{*3^$Q~wIrKZ_AaB>YKUKNjX29dPQmLDN{m97ic7IE04n4@hx_fNKP`7vbR zNBFpa)_b36M|B!$Z*-sBR>=4loFxK4xG(wq}=NgG|z;M{A z!;>&&fLre0{)X!?s6FsnGeZCgSU6DEopvcrQ z5)-M4^{{PbUlwleL-WWwH^0hvbk=Z70ZX2he$F zqlxbZrZdNJtgLL*Fy~hrH9fDfa^x-~*%w0{B1$En^L56+W>Z6?zOo0@E)gpw_e=hd-GFta#O=(MC9Ju zI+4%_fp)JCfGX9LUCDiO8qtxd$P8pjWN~B}hv`K6DEioo$;nYFeL8V`37}L8bs~k7 zN}=Hj1B$bW;R*v%Xh7x7p30BX}B9{fWO!eg1JnJii!@`*41-%QnElG z;4qW1q{x+&lsGKy67i?%f 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5a3ee059c2ecc434a2a4ee6d5da992763debbf70..afdcfaa3615b847884f3a11e399de09913886541 100644 GIT binary patch delta 991 zcmXZa$uC1u6vy$~YQ&R9gbuopE-fuAurk{is#qc-B4Q2^%dRD2^WuN7l-L`Jq9|&f z$5;^&F^~7WepjEI-#NMG-S^&P-elgCGc)K=N`+ID5+fMJ7{+lQkMSI@@lIa4cI7}y`J2Ve1s-li7nWQZP<<-*oj?Qd8%&g!Cvgs%DDqLNIpb8Y^YRg zU_=75+1u|+(&MAL62}-D7pL7>{Wj~@nbDRakNZL-eq@gHIC BU7G*^ delta 958 zcmXZZw@X7|6vpA3SObbBH;I|D*t=%YK@f2fL{#4l0z z{fPQnzp9D4ebqX&!}UMB6XP%*6EG2zRFi548uYF-+H}moOmw4-9`uSjQ`H z%VsqPb1@I|u>cFP2#c`vbG=(5bF?RV)!Rnj@ltL^h^s?{XcVSQ}1#*A9sY5u7 zBRGm^oASswi()4oWprsz(ribWn59$zrA5cwvHU3-V!zMh>7AM{sD&g BPCftt diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index 550b99cc48a11c245546f5b7e94f57faa25c78e6..48c5d570a934f86c3c25b40a97c604876ebe8abb 100644 GIT binary patch delta 2718 zcmYk8&2JM&7>8fKF^~X`M{#0uh!ZCvRpTU7AXKX6YZajii^v5Ysl>r>|rJYAQ=z?#h&B5nOxcWr0-KO9#mlSO)YFc$CPH% z9$V1N)a-?C?v6Y6g>UXoBSSU0cn=4yt-gK;Jc~aKysp;5<{r++Vjvk11I1=={-X=9 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z0$iLE_Or0Y5+3!wkmfb1)r}RGqkmRod+6R#_28M5EeCxp!OZmoRt|!QO-`)N!K70+Hnq%+> z6>wVE*Vi{~jEr)-EG?7C2y^p0o_5XqdnX&qY~G+{oizQ2biwWi#BspQ8}9JkdjIFV Uqb0f#G}7mf#IJkb-o0|-Kbs$CIsgCw diff --git a/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin b/core/rexcode/isa/arm64/tables/arm64.idx_op0.bin index e17ae68fd0aa72bc4e27ce75047ba8ee1c5aebb9..a0412e35a000c1cb5ebfa8a24a0f9f86962cb028 100644 GIT binary patch literal 64 zcmZQz2xI_(Kn6J`5S`ED!?2slh~X`h1%oQH5{o;#07E#t56T@$IQ3e5yp literal 64 zcmZQz2xI_(K!#t8AljSBhhaLC5yMF)3kF7JB^G6N0S04sC5BM;CWh Date: Fri, 28 Aug 2026 16:52:13 -0400 Subject: [PATCH 45/89] rexcode/arm64: predicate-mask ops, and SVE2's AES take one operand more Seventeen predicate operations were printing an element size they do not have. AND/ORR/NAND/BRKA and the rest of that family treat a predicate as a bit mask rather than as elements, so they are always .b -- bits 23:22 are opcode there, not a size, and deriving the size from them produced `ands p0.h, p0/z, p0.h, p0.h`, which no assembler takes. PNEXT and PTRUE really are sized and keep it. SVE2's AES are destructive: the destination is also the first source and is written twice, so `aese z0.b, z0.b, z1.b` has one operand more than the NEON form. All four were modelled with the NEON operand count, which made them unassemblable regardless of what else was right. PFIRST and PNEXT had their governing predicate sized as well; it is written bare, like every other governing predicate. SVE/SME2 decode entries against llvm-mc: 545 byte-exact and 0 mismatched, from 211 and 78 at the start of the session. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/mnemonic_builders.odin | 172 +++++++++--------- .../tablegen/generated/decode_tables.odin | 44 ++--- .../tablegen/generated/encode_tables.odin | 44 ++--- .../isa/arm64/tablegen/instruction_table.odin | 44 ++--- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 50920 -> 50920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 50960 -> 50960 bytes 6 files changed, 152 insertions(+), 152 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 321812749..7939b2b38 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -127,10 +127,10 @@ emit_and_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst emit_and_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_ands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } -emit_ands_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_ph_p_ph_ph(rz, rz2, rz3, rz4)) } +emit_ands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -138,7 +138,7 @@ inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orr_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } @@ -146,7 +146,7 @@ emit_orr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_orr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_orr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_orr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -emit_orr_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_ps_p_ps_ps(rz, rz2, rz3, rz4)) } +emit_orr_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } @@ -178,15 +178,15 @@ emit_bic_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_bic_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_bic_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bics_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } -emit_bics_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_ph_p_ph_ph(rz, rz2, rz3, rz4)) } +emit_bics_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orn_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } -emit_orn_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_ps_p_ps_ps(rz, rz2, rz3, rz4)) } +emit_orn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } @@ -1318,21 +1318,21 @@ emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Inst inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aese_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aese_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } emit_aese_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_v16b_v16b(dst, src)) } -emit_aese_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aese_zb_zb(rz, rz2)) } +emit_aese_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aese_zb_zb_zb(rz, rz2, rz3)) } inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesd_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } emit_aesd_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_v16b_v16b(dst, src)) } -emit_aesd_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesd_zb_zb(rz, rz2)) } +emit_aesd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aesd_zb_zb_zb(rz, rz2, rz3)) } inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesmc_zb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +inst_aesmc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_aesmc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_v16b_v16b(dst, src)) } -emit_aesmc_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesmc_zb(rz)) } +emit_aesmc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesmc_zb_zb(rz, rz2)) } inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesimc_zb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +inst_aesimc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } emit_aesimc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_v16b_v16b(dst, src)) } -emit_aesimc_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_aesimc_zb(rz)) } +emit_aesimc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesimc_zb_zb(rz, rz2)) } inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } @@ -3138,7 +3138,7 @@ inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_mov_ps_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV, dst, src) } inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } emit_mov_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v8b_v8b(dst, src)) } @@ -3148,7 +3148,7 @@ emit_mov_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_mov_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zs_p_zs(rz, rz2, rz3)) } emit_mov_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_zd_p_zd(rz, rz2, rz3)) } emit_mov_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_mov_pb_p_p(rz, rz2, rz3)) } -emit_mov_ps_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_ps_p(rz, rz2)) } +emit_mov_pb_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_pb_p(rz, rz2)) } emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4)}} } @@ -3541,42 +3541,42 @@ inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: emit_fnmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_nand_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nand_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_ps_p_ps_ps(rz, rz2, rz3, rz4)) } -inst_nor_ps_p_ps_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nor_ps_p_ps_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_ps_p_ps_ps(rz, rz2, rz3, rz4)) } +inst_nand_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nand_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_nor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_sel_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orrs_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orrs_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pd_p_pd_pd(rz, rz2, rz3, rz4)) } -inst_eors_ph_p_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_eors_ph_p_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_ph_p_ph_ph(rz, rz2, rz3, rz4)) } -inst_nands_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nands_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pd_p_pd_pd(rz, rz2, rz3, rz4)) } -inst_nors_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_nors_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pd_p_pd_pd(rz, rz2, rz3, rz4)) } -inst_orns_pd_p_pd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } -emit_orns_pd_p_pd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pd_p_pd_pd(rz, rz2, rz3, rz4)) } -inst_movs_ph_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_movs_ph_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_ph_p_p(rz, rz2, rz3)) } +inst_orrs_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orrs_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_eors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_eors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_nands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_nors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_nors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_orns_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_orns_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pb_p_pb_pb(rz, rz2, rz3, rz4)) } +inst_movs_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_movs_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_pb_p_p(rz, rz2, rz3)) } inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } emit_ptrue_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_pb_i(rz, imm)) } inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_ph_ph_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_ph_ph_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_ph_ph_ph(rz, rz2, rz3)) } -inst_pnext_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_pb_pb(rz, rz2, rz3)) } +inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } +inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } -inst_brkb_ps_p_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkb_ps_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_ps_p_ps(rz, rz2, rz3)) } -inst_brkas_ph_p_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkas_ph_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_ph_p_ph(rz, rz2, rz3)) } -inst_brkbs_pd_p_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_brkbs_pd_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pd_p_pd(rz, rz2, rz3)) } +inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkb_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_pb_p_pb(rz, rz2, rz3)) } +inst_brkas_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkas_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_pb_p_pb(rz, rz2, rz3)) } +inst_brkbs_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_brkbs_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pb_p_pb(rz, rz2, rz3)) } inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } emit_brkpa_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_pb_pb(rz, rz2, rz3, rz4)) } inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } @@ -4408,18 +4408,18 @@ inst_adrp :: inst_adrp_r_l emit_adrp :: emit_adrp_r_l inst_and :: proc{ inst_and_r_r_sh, inst_and_r_r_i, inst_and_v16b_v16b_v16b, inst_and_zb_p_zb_zb } emit_and :: proc{ emit_and_r_r_sh, emit_and_r_r_i, emit_and_v16b_v16b_v16b, emit_and_zb_p_zb_zb } -inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_ph_p_ph_ph } -emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_ph_p_ph_ph } +inst_ands :: proc{ inst_ands_r_r_sh, inst_ands_r_r_i, inst_ands_pb_p_pb_pb } +emit_ands :: proc{ emit_ands_r_r_sh, emit_ands_r_r_i, emit_ands_pb_p_pb_pb } inst_orr :: proc{ inst_orr_r_r_sh, inst_orr_r_r_i, inst_orr_v16b_v16b_v16b, inst_orr_zb_p_zb_zb } emit_orr :: proc{ emit_orr_r_r_sh, emit_orr_r_r_i, emit_orr_v16b_v16b_v16b, emit_orr_zb_p_zb_zb } inst_eor :: proc{ inst_eor_r_r_sh, inst_eor_r_r_i, inst_eor_v16b_v16b_v16b, inst_eor_zb_p_zb_zb } emit_eor :: proc{ emit_eor_r_r_sh, emit_eor_r_r_i, emit_eor_v16b_v16b_v16b, emit_eor_zb_p_zb_zb } inst_bic :: proc{ inst_bic_r_r_sh, inst_bic_v16b_v16b_v16b, inst_bic_zb_p_zb_zb } emit_bic :: proc{ emit_bic_r_r_sh, emit_bic_v16b_v16b_v16b, emit_bic_zb_p_zb_zb } -inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_ph_p_ph_ph } -emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_ph_p_ph_ph } -inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_ps_p_ps_ps } -emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_ps_p_ps_ps } +inst_bics :: proc{ inst_bics_r_r_sh, inst_bics_pb_p_pb_pb } +emit_bics :: proc{ emit_bics_r_r_sh, emit_bics_pb_p_pb_pb } +inst_orn :: proc{ inst_orn_r_r_sh, inst_orn_v16b_v16b_v16b, inst_orn_pb_p_pb_pb } +emit_orn :: proc{ emit_orn_r_r_sh, emit_orn_v16b_v16b_v16b, emit_orn_pb_p_pb_pb } inst_eon :: inst_eon_r_r_sh emit_eon :: emit_eon_r_r_sh inst_lsl :: proc{ inst_lsl_r_r_r, inst_lsl_zb_p_zb_zb, inst_lsl_r_r_i } @@ -4982,14 +4982,14 @@ inst_crc32cw :: inst_crc32cw_r_r_r emit_crc32cw :: emit_crc32cw_r_r_r inst_crc32cx :: inst_crc32cx_r_r_r emit_crc32cx :: emit_crc32cx_r_r_r -inst_aese :: proc{ inst_aese_v16b_v16b, inst_aese_zb_zb } -emit_aese :: proc{ emit_aese_v16b_v16b, emit_aese_zb_zb } -inst_aesd :: proc{ inst_aesd_v16b_v16b, inst_aesd_zb_zb } -emit_aesd :: proc{ emit_aesd_v16b_v16b, emit_aesd_zb_zb } -inst_aesmc :: proc{ inst_aesmc_v16b_v16b, inst_aesmc_zb } -emit_aesmc :: proc{ emit_aesmc_v16b_v16b, emit_aesmc_zb } -inst_aesimc :: proc{ inst_aesimc_v16b_v16b, inst_aesimc_zb } -emit_aesimc :: proc{ emit_aesimc_v16b_v16b, emit_aesimc_zb } +inst_aese :: proc{ inst_aese_v16b_v16b, inst_aese_zb_zb_zb } +emit_aese :: proc{ emit_aese_v16b_v16b, emit_aese_zb_zb_zb } +inst_aesd :: proc{ inst_aesd_v16b_v16b, inst_aesd_zb_zb_zb } +emit_aesd :: proc{ emit_aesd_v16b_v16b, emit_aesd_zb_zb_zb } +inst_aesmc :: proc{ inst_aesmc_v16b_v16b, inst_aesmc_zb_zb } +emit_aesmc :: proc{ emit_aesmc_v16b_v16b, emit_aesmc_zb_zb } +inst_aesimc :: proc{ inst_aesimc_v16b_v16b, inst_aesimc_zb_zb } +emit_aesimc :: proc{ emit_aesimc_v16b_v16b, emit_aesimc_zb_zb } inst_sha1h :: inst_sha1h_r_r emit_sha1h :: emit_sha1h_r_r inst_sha1c :: inst_sha1c_r_r_v4s @@ -5420,8 +5420,8 @@ inst_dup :: proc{ inst_dup_v8b_veb_i, inst_dup_v8b_r, emit_dup :: proc{ emit_dup_v8b_veb_i, emit_dup_v8b_r, emit_dup_zb_r } inst_ins :: proc{ inst_ins_veb_i_veb_i, inst_ins_veb_i_r } emit_ins :: proc{ emit_ins_veb_i_veb_i, emit_ins_veb_i_r } -inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_zb_p_zb, inst_mov_ps_p, inst_mov_r_i } -emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_zb_p_zb, emit_mov_ps_p, emit_mov_r_i } +inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_zb_p_zb, inst_mov_pb_p, inst_mov_r_i } +emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_zb_p_zb, emit_mov_pb_p, emit_mov_r_i } inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_zb_zb_zb_i } emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_zb_zb_zb_i } inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_zb_zb_zb } @@ -5496,42 +5496,42 @@ inst_fnmla :: inst_fnmla_zh_p_zh_zh emit_fnmla :: emit_fnmla_zh_p_zh_zh inst_fnmls :: inst_fnmls_zh_p_zh_zh emit_fnmls :: emit_fnmls_zh_p_zh_zh -inst_nand :: inst_nand_ps_p_ps_ps -emit_nand :: emit_nand_ps_p_ps_ps -inst_nor :: inst_nor_ps_p_ps_ps -emit_nor :: emit_nor_ps_p_ps_ps +inst_nand :: inst_nand_pb_p_pb_pb +emit_nand :: emit_nand_pb_p_pb_pb +inst_nor :: inst_nor_pb_p_pb_pb +emit_nor :: emit_nor_pb_p_pb_pb inst_sel :: inst_sel_pb_p_pb_pb emit_sel :: emit_sel_pb_p_pb_pb -inst_orrs :: inst_orrs_pd_p_pd_pd -emit_orrs :: emit_orrs_pd_p_pd_pd -inst_eors :: inst_eors_ph_p_ph_ph -emit_eors :: emit_eors_ph_p_ph_ph -inst_nands :: inst_nands_pd_p_pd_pd -emit_nands :: emit_nands_pd_p_pd_pd -inst_nors :: inst_nors_pd_p_pd_pd -emit_nors :: emit_nors_pd_p_pd_pd -inst_orns :: inst_orns_pd_p_pd_pd -emit_orns :: emit_orns_pd_p_pd_pd -inst_movs :: inst_movs_ph_p_p -emit_movs :: emit_movs_ph_p_p +inst_orrs :: inst_orrs_pb_p_pb_pb +emit_orrs :: emit_orrs_pb_p_pb_pb +inst_eors :: inst_eors_pb_p_pb_pb +emit_eors :: emit_eors_pb_p_pb_pb +inst_nands :: inst_nands_pb_p_pb_pb +emit_nands :: emit_nands_pb_p_pb_pb +inst_nors :: inst_nors_pb_p_pb_pb +emit_nors :: emit_nors_pb_p_pb_pb +inst_orns :: inst_orns_pb_p_pb_pb +emit_orns :: emit_orns_pb_p_pb_pb +inst_movs :: inst_movs_pb_p_p +emit_movs :: emit_movs_pb_p_p inst_ptrue :: inst_ptrue_pb_i emit_ptrue :: emit_ptrue_pb_i inst_ptrues :: inst_ptrues_pb_i emit_ptrues :: emit_ptrues_pb_i inst_pfalse :: inst_pfalse_pb emit_pfalse :: emit_pfalse_pb -inst_pfirst :: inst_pfirst_ph_ph_ph -emit_pfirst :: emit_pfirst_ph_ph_ph -inst_pnext :: inst_pnext_pb_pb_pb -emit_pnext :: emit_pnext_pb_pb_pb +inst_pfirst :: inst_pfirst_pb_p_pb +emit_pfirst :: emit_pfirst_pb_p_pb +inst_pnext :: inst_pnext_pb_p_pb +emit_pnext :: emit_pnext_pb_p_pb inst_brka :: inst_brka_pb_p_pb emit_brka :: emit_brka_pb_p_pb -inst_brkb :: inst_brkb_ps_p_ps -emit_brkb :: emit_brkb_ps_p_ps -inst_brkas :: inst_brkas_ph_p_ph -emit_brkas :: emit_brkas_ph_p_ph -inst_brkbs :: inst_brkbs_pd_p_pd -emit_brkbs :: emit_brkbs_pd_p_pd +inst_brkb :: inst_brkb_pb_p_pb +emit_brkb :: emit_brkb_pb_p_pb +inst_brkas :: inst_brkas_pb_p_pb +emit_brkas :: emit_brkas_pb_p_pb +inst_brkbs :: inst_brkbs_pb_p_pb +emit_brkbs :: emit_brkbs_pb_p_pb inst_brkpa :: inst_brkpa_pb_p_pb_pb emit_brkpa :: emit_brkpa_pb_p_pb_pb inst_brkpb :: inst_brkpb_pb_p_pb_pb diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 85309d3ac..462bc4e82 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -94,19 +94,19 @@ DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, - { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, - { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_H,.P_REG_H,.P_REG_H,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -123,9 +123,9 @@ DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG_S,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -478,18 +478,18 @@ DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, @@ -503,14 +503,14 @@ DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 8f87113f4..7b7adf71f 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -93,7 +93,7 @@ ENCODE_FORMS := [2546]lib.Encoding{ { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -104,7 +104,7 @@ ENCODE_FORMS := [2546]lib.Encoding{ { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -128,12 +128,12 @@ ENCODE_FORMS := [2546]lib.Encoding{ // .BICS { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -1288,16 +1288,16 @@ ENCODE_FORMS := [2546]lib.Encoding{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .AESE { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESD { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESMC { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .AESIMC { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .SHA1H { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA1C @@ -2424,7 +2424,7 @@ ENCODE_FORMS := [2546]lib.Encoding{ { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, @@ -2663,23 +2663,23 @@ ENCODE_FORMS := [2546]lib.Encoding{ { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG_S,.P_REG_S}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.P_REG_H}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.P_REG_D}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES @@ -2687,17 +2687,17 @@ ENCODE_FORMS := [2546]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_H,.P_REG_H,.P_REG_H,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG_S,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG_H,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG_D,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 6ce97f788..b32dec079 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -198,7 +198,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -210,7 +210,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EOR = { {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -237,13 +237,13 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .BICS = { {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .EON = { {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, @@ -1680,19 +1680,19 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .AESE = { {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESD = { {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, }, .AESMC = { {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .AESIMC = { {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, }, .SHA1H = { {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, @@ -3035,7 +3035,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.MOV, {.P_REG_S, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, + {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, @@ -3312,31 +3312,31 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG_S, .P_REG_S}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .SEL = { {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .P_REG_H}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .P_REG_D}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, @@ -3348,22 +3348,22 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_H, .P_REG_H, .P_REG_H, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKA = { {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG_S, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG_H, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG_D, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 0056a39988def990d20109f9ce7cc7f1c3bf1c0f..550d00c5c473f644802782541428901f932c581e 100644 GIT binary patch delta 389 zcmaFS%lx93dBZkVmPF;m#L2r@kANAQo7fgGLWI;fd>}$)97Zk{vJ6^U+6)X2lw2A9 z{Qu9Fpv@>Cz`y_!Vu;Z21Bo#^Xfw*nLe)Kishj-3N8C~ts8S24@_~Zuga1I?4!Q{4 z6)@epK;2MvPhjdc8~94OGbV2Kp0b%=0_0FHKW`rarv_DlLl6G*Hs~;c9WS;-B^4&g z;BWvU*`W`X1ZiM!a)62%z{LcdK z;N|Vbz;GZ!Rp8(M|GWtnOo@twCns-iVq3rn5mMvufe4jx7`a$5FlcErFfcq& za%K4Q|39CDHlu(5R4hWn4+!Cl!3y2vWD7ZfO57e!oi_l#G z)2+)0)C^Jg1g37Yfv=Q1WAbM2DVzBvK<@MM^Y#&NYETt8^x!{lgANl&Y_ixAmDCjF zloXI8gTn!cWQRTz$Y)?NCkLpQ0TWD}fD=gFhyT1ChHxiNS!fL(&YI| z{Kb-zk{GA20B2`@r~m)} diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index 48c5d570a934f86c3c25b40a97c604876ebe8abb..838f2937b820d8e2bc966055f47d5a45a68ded3f 100644 GIT binary patch delta 376 zcmbQx$2_5rdBbwHKv@O`EiDEHh6f6+5B~rE&*z}aC<_yN0uxhaNK9m4@bU(#b1-2Q z`1k)muY);LqGBRY%!`5HK!hq-EWrXOHu(ozkBThNP;H>0O0EolfQBY$0}X|WJ%NdB zUcv6fsGX<;G{n!FLBL^xs=y(j!3ow(iOLW$28RHMScVNqY_llmL}?u$BN3>TWTtr2-88%0hz9kH9P=n;9*EsPEMX|rfLC~ z6o5+#fF(D#sfsW%CQqKNrY-?e46(5RVnBlq6WD-TYATv=s~tej0hz83azDgICzy@K MOi7#7)nCpB09iwN7XSbN From d40d9e687acf6b86633c43f6d5e2cb05da15f44c Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 16:58:33 -0400 Subject: [PATCH 46/89] rexcode/arm64: model SME's ZA tiles and tile slices A ZA tile printed as the bare number it is encoded as -- `addha #0, p0/m, p0/m, z0.s` -- and a tile slice printed as one too, where the syntax is `za0h.b[w12, 0]`: a tile, taken along its rows or columns, addressed by one of W12..W15 plus an offset. Neither was anything an assembler would take. Tiles are a register class now (ZA0..ZA15, viewed at an element size), so they print through the same path as every other register. A slice is its own operand kind holding the four things it is made of, rather than one packed immediate that only the encoder understood. Getting that right needed the field layout, and the layout is not what the encoding table implied: the tile number and the offset share the low nibble, and how it splits follows the element size -- a byte tile has no tile bits at all and four of offset, while a quadword tile is all tile and none. Reading a fixed four bits as the tile made every byte slice come back as tile 4. LD1Q/ST1Q scale their index by 16, which the mnemonic's last letter does not spell the way B/H/W/D do; they were left unscaled when the other 38 forms were fixed. That also wanted a .q element shape, which nothing had needed before. SVE/SME2 decode entries against llvm-mc: 559 byte-exact and 0 mismatched, from 211 and 78 at the start of the session. What is left is mostly one structural limit: SME's outer products take five operands (`umopa za0.s, p0/m, p1/m, z0.b, z1.b`) and Instruction holds four. Widening it would fit -- five Operands is 55 bytes of the 64 -- but it reaches through Encoding, the table, both codecs and the builders, so it wants its own change. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 80 ++++++++++-------- core/rexcode/isa/arm64/encoder.odin | 48 ++++------- core/rexcode/isa/arm64/encoding_types.odin | 2 +- core/rexcode/isa/arm64/operands.odin | 21 +++++ core/rexcode/isa/arm64/printer.odin | 27 ++++-- core/rexcode/isa/arm64/registers.odin | 1 + .../tablegen/generated/decode_tables.odin | 4 +- .../tablegen/generated/encode_tables.odin | 4 +- .../isa/arm64/tablegen/instruction_table.odin | 4 +- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 50920 -> 50920 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 50960 -> 50960 bytes .../isa/arm64/tests/pipeline_smoke.odin | 12 +-- 12 files changed, 116 insertions(+), 87 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 1f84c221f..bb4b935d8 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -261,7 +261,8 @@ extract_operand_inline :: #force_inline proc "contextless" ( v := ((word >> 16) & 0x1F) << 3 | ((word >> 10) & 0x7) return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 1} case .ZA_TILE_LOW: - return Operand{immediate = i64(word & 0x7), kind = .IMMEDIATE, size = 1} + return Operand{reg = Register(REG_ZA | u16(word & 0x7)), kind = .REGISTER, + size = za_elem_for_type(ot)} case .NEON_LANE_B: i := ((word >> 30) & 0x1) << 3 | ((word >> 12) & 0x1) << 2 | ((word >> 10) & 0x3) return Operand{immediate = i64(i), kind = .IMMEDIATE, size = LANE_INDEX} @@ -532,7 +533,8 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = 1} // ---- SVE memory operands ---- - case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3: + case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3, + .SVE_OFFSET_BASE_SS4: base_hw := u8((word >> 5) & 0x1F) idx_hw := u8((word >> 16) & 0x1F) shift: u8 = 0 @@ -540,6 +542,7 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .SVE_OFFSET_BASE_SS1: shift = 1 case .SVE_OFFSET_BASE_SS2: shift = 2 case .SVE_OFFSET_BASE_SS3: shift = 3 + case .SVE_OFFSET_BASE_SS4: shift = 4 } return Operand{ mem = Memory{ @@ -566,13 +569,17 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- SME ZA tile fields ---- case .ZA_TILE_NUM_B: - return Operand{immediate = 0, kind = .IMMEDIATE, size = 1} + return Operand{reg = Register(REG_ZA | 0), kind = .REGISTER, + size = za_elem_for_type(ot)} case .ZA_TILE_NUM_H: - return Operand{immediate = i64((word >> 22) & 0x1), kind = .IMMEDIATE, size = 1} + return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x1)), kind = .REGISTER, + size = za_elem_for_type(ot)} case .ZA_TILE_NUM_S: - return Operand{immediate = i64((word >> 22) & 0x3), kind = .IMMEDIATE, size = 1} + return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x3)), kind = .REGISTER, + size = za_elem_for_type(ot)} case .ZA_TILE_NUM_D: - return Operand{immediate = i64((word >> 21) & 0x7), kind = .IMMEDIATE, size = 1} + return Operand{reg = Register(REG_ZA | u16((word >> 21) & 0x7)), kind = .REGISTER, + size = za_elem_for_type(ot)} case .SME_PATTERN_FIELD: return Operand{immediate = i64((word >> 5) & 0xF), kind = .IMMEDIATE, size = 1} @@ -630,40 +637,30 @@ extract_operand_inline :: #force_inline proc "contextless" ( // instruction bits 3:0 (packed per element size), Ws at bits 14:13, // V flag at bit 15. case .SME_SLICE_B: - vflag := (word >> 15) & 0x1 - ws := (word >> 13) & 0x3 - imm := word & 0xF - v := imm | (vflag << 4) | (ws << 5) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} + // The tile number and the offset share the low nibble; how it + // splits follows the element size. + return op_za_slice(u8((word >> 4) & 0x0), u8((word >> 13) & 0x3), + u8(word & 0xF), ZSHAPE_B, (word >> 15) & 0x1 != 0) case .SME_SLICE_H: - vflag := (word >> 15) & 0x1 - ws := (word >> 13) & 0x3 - imm := word & 0x7 - tile := (word >> 3) & 0x1 - v := imm | (vflag << 4) | (ws << 5) | (tile << 7) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} + // The tile number and the offset share the low nibble; how it + // splits follows the element size. + return op_za_slice(u8((word >> 3) & 0x1), u8((word >> 13) & 0x3), + u8(word & 0x7), ZSHAPE_H, (word >> 15) & 0x1 != 0) case .SME_SLICE_W: - vflag := (word >> 15) & 0x1 - ws := (word >> 13) & 0x3 - imm := word & 0x3 - tile := (word >> 2) & 0x3 - v := imm | (vflag << 4) | (ws << 5) | (tile << 7) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} + // The tile number and the offset share the low nibble; how it + // splits follows the element size. + return op_za_slice(u8((word >> 2) & 0x3), u8((word >> 13) & 0x3), + u8(word & 0x3), ZSHAPE_S, (word >> 15) & 0x1 != 0) case .SME_SLICE_D: - vflag := (word >> 15) & 0x1 - ws := (word >> 13) & 0x3 - imm := word & 0x1 - tile := (word >> 1) & 0x7 - v := imm | (vflag << 4) | (ws << 5) | (tile << 7) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} + // The tile number and the offset share the low nibble; how it + // splits follows the element size. + return op_za_slice(u8((word >> 1) & 0x7), u8((word >> 13) & 0x3), + u8(word & 0x1), ZSHAPE_D, (word >> 15) & 0x1 != 0) case .SME_SLICE_Q: - vflag := (word >> 15) & 0x1 - ws := (word >> 13) & 0x3 - tile := word & 0xF - v := (vflag << 4) | (ws << 5) | (tile << 7) - return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 2} - - // ---- Batch 3 misc immediates ---- + // The tile number and the offset share the low nibble; how it + // splits follows the element size. + return op_za_slice(u8((word >> 0) & 0xF), u8((word >> 13) & 0x3), + u8(word & 0x0), ZSHAPE_Q, (word >> 15) & 0x1 != 0) case .NEON_IDX2: return Operand{immediate = i64((word >> 12) & 0x3), kind = .IMMEDIATE, size = LANE_INDEX} case .ENC_FCMLA_ROT: @@ -842,3 +839,14 @@ decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic sve_tsz_field :: #force_inline proc "contextless" (word: u32) -> u32 { return ((word >> 22) & 0x3) << 5 | ((word >> 19) & 0x3) << 3 | ((word >> 16) & 0x7) } + +// The element width a ZA tile operand is viewed at. +@(private="file", require_results) +za_elem_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { + #partial switch ot { + case .ZA_TILE_H: return ZSHAPE_H + case .ZA_TILE_S: return ZSHAPE_S + case .ZA_TILE_D: return ZSHAPE_D + } + return ZSHAPE_B +} diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index d3c0ee802..4970e6bfd 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -274,6 +274,7 @@ operand_matches_inline :: #force_inline proc "contextless" ( // SME tile state (immediate-encoded tile number; user supplies the // tile index as an immediate, e.g. 0 for ZA0.S, 3 for ZA3.S). case .ZA_TILE_B, .ZA_TILE_H, .ZA_TILE_S, .ZA_TILE_D, .ZA_TILE_Q: + if op.kind == .REGISTER { return reg_class(op.reg) == REG_ZA } return op.kind == .IMMEDIATE // Misc immediate sub-types added in batch 3 case .FCMLA_ROT, .FCADD_ROT, .SVE_PRFOP, .LDRAA_IMM10: @@ -284,7 +285,7 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .IMMEDIATE // SME tile slice (packed immediate descriptor; see encoding_types.odin) case .SME_SLICE_B, .SME_SLICE_H, .SME_SLICE_W, .SME_SLICE_D, .SME_SLICE_Q: - return op.kind == .IMMEDIATE + return op.kind == .ZA_SLICE case .IMM_12, .IMM_16, .IMM_8, .IMM_6, .IMM_5, .IMM_4, .IMM_3, .IMM_2, .NZCV_IMM, .PSTATE_FIELD, .HW_SHIFT, .LSE_SIZE, .VEC_SHIFT, .VEC_INDEX: @@ -406,7 +407,7 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.extended.reg)) & 0x1F) << 16 | (u32(op.extended.extend) & 0x7) << 13 | (u32(op.extended.amount) & 0x7) << 10 - case .NONE, .IMMEDIATE, .MEMORY, .RELATIVE, .COND, .SYSTEM_REGISTER: + case .NONE, .IMMEDIATE, .MEMORY, .RELATIVE, .COND, .SYSTEM_REGISTER, .ZA_SLICE: return 0 } @@ -693,7 +694,8 @@ pack_operand_inline :: #force_inline proc( return (u32(op.immediate) & 0x1F) << 5 // SVE memory operands - case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3: + case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3, + .SVE_OFFSET_BASE_SS4: // [Xn, Xm, LSL #s] scalar+scalar. Base at 9:5, index at 20:16; // shift is implicit in the encoding's static bits (per ESize). base_bits := (u32(reg_hw(op.mem.base)) & 0x1F) << 5 @@ -769,40 +771,20 @@ pack_operand_inline :: #force_inline proc( // .D : tile[2:0]<<1 | imm[0] (8 tiles, 2 slices each) // .Q : tile[3:0] (16 tiles, no imm) case .SME_SLICE_B: - v := u32(op.immediate) - imm := v & 0xF - vflag := (v >> 4) & 0x1 - ws := (v >> 5) & 0x3 - return (vflag << 15) | (ws << 13) | imm + return (u32(op.za.vertical ? 1 : 0) << 15) | ((u32(op.za.ws) & 0x3) << 13) | + ((u32(op.za.tile) << 4) & 0xF) | (u32(op.za.offset) & 0xF) case .SME_SLICE_H: - v := u32(op.immediate) - imm := v & 0x7 - vflag := (v >> 4) & 0x1 - ws := (v >> 5) & 0x3 - tile := (v >> 7) & 0x1 - return (vflag << 15) | (ws << 13) | imm | (tile << 3) + return (u32(op.za.vertical ? 1 : 0) << 15) | ((u32(op.za.ws) & 0x3) << 13) | + ((u32(op.za.tile) << 3) & 0xF) | (u32(op.za.offset) & 0x7) case .SME_SLICE_W: - v := u32(op.immediate) - imm := v & 0x3 - vflag := (v >> 4) & 0x1 - ws := (v >> 5) & 0x3 - tile := (v >> 7) & 0x3 - return (vflag << 15) | (ws << 13) | imm | (tile << 2) + return (u32(op.za.vertical ? 1 : 0) << 15) | ((u32(op.za.ws) & 0x3) << 13) | + ((u32(op.za.tile) << 2) & 0xF) | (u32(op.za.offset) & 0x3) case .SME_SLICE_D: - v := u32(op.immediate) - imm := v & 0x1 - vflag := (v >> 4) & 0x1 - ws := (v >> 5) & 0x3 - tile := (v >> 7) & 0x7 - return (vflag << 15) | (ws << 13) | imm | (tile << 1) + return (u32(op.za.vertical ? 1 : 0) << 15) | ((u32(op.za.ws) & 0x3) << 13) | + ((u32(op.za.tile) << 1) & 0xF) | (u32(op.za.offset) & 0x1) case .SME_SLICE_Q: - v := u32(op.immediate) - vflag := (v >> 4) & 0x1 - ws := (v >> 5) & 0x3 - tile := (v >> 7) & 0xF - return (vflag << 15) | (ws << 13) | tile - - // ---- Batch 3 misc immediate encodings ---- + return (u32(op.za.vertical ? 1 : 0) << 15) | ((u32(op.za.ws) & 0x3) << 13) | + ((u32(op.za.tile) << 0) & 0xF) | (u32(op.za.offset) & 0x0) case .NEON_IDX2: return (u32(op.immediate) & 0x3) << 12 case .ENC_FCMLA_ROT: diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 36a6816f1..357f27bc2 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -413,7 +413,7 @@ Operand_Encoding :: enum u8 { // SVE scalar+scalar addressing scales the index by the access size, and the // assembler wants that written out (`[x0, x0, lsl #2]`). The amount is a // property of the form, so it rides on the encoding. - SVE_OFFSET_BASE_SS1, SVE_OFFSET_BASE_SS2, SVE_OFFSET_BASE_SS3, + SVE_OFFSET_BASE_SS1, SVE_OFFSET_BASE_SS2, SVE_OFFSET_BASE_SS3, SVE_OFFSET_BASE_SS4, // SVE gather/scatter: the index is a vector, and the syntax names its // element size and how the base extends it. A 32-bit index is written // `uxtw`/`sxtw` (bit 22 says which); a 64-bit one needs neither. diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index de07fe5f3..933ad36ba 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -29,6 +29,17 @@ Operand_Kind :: enum u8 { EXTENDED_REG, // X/W reg + extend + amount COND, // 4-bit condition code (EQ/NE/.../AL/NV) SYSTEM_REGISTER, // MRS/MSR target, as a packed 15-bit field + ZA_SLICE, // `za0h.b[w12, 0]` -- a row or column of an SME tile +} + +// One slice of an SME accumulator tile: which tile, taken along the rows (h) +// or the columns (v), addressed by one of W12..W15 plus a fixed offset. +ZA_Slice :: bit_field u32 { + tile: u8 | 4, + vertical: bool | 1, + ws: u8 | 2, // 0..3, meaning W12..W15 + offset: u8 | 4, + elem: u8 | 5, // the ZSHAPE_* code the tile is viewed at } Shift_Type :: enum u8 { @@ -106,6 +117,7 @@ Operand :: struct #packed { extended: Extended_Reg, // 8 cond: u8, // 1 sysreg: System_Register, // 2 + za: ZA_Slice, // 4 }, // 12 total because of alignment kind: Operand_Kind, // 1 size: u8, // 1 -- carried width info; meaning varies @@ -173,6 +185,14 @@ op_sysreg :: #force_inline proc "contextless" (sr: System_Register) -> Operand { return Operand{sysreg = sr, kind = .SYSTEM_REGISTER, size = 2} } +@(require_results) +op_za_slice :: #force_inline proc "contextless" (tile, ws, offset, elem: u8, vertical := false) -> Operand { + return Operand{ + za = ZA_Slice{tile = tile, vertical = vertical, ws = ws, offset = offset, elem = elem}, + kind = .ZA_SLICE, size = elem, + } +} + // ----------------------------------------------------------------------------- // SVE Z-register builders -- encode the element arrangement in op.size // (B=1, H=2, S=4, D=8). Matcher uses op.size to disambiguate the right @@ -276,6 +296,7 @@ ZSHAPE_B :: u8(1) ZSHAPE_H :: u8(2) ZSHAPE_S :: u8(4) ZSHAPE_D :: u8(8) +ZSHAPE_Q :: u8(16) // ----------------------------------------------------------------------------- // NEON V-register arrangement builders. These take the register the caller diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 1967b8071..9479e461c 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -416,12 +416,13 @@ write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercas case 5: shape = "s" case 7: shape = "d" } - case REG_Z: + case REG_Z, REG_ZA: switch size { - case 1: shape = "b" - case 2: shape = "h" - case 4: shape = "s" - case 8: shape = "d" + case 1: shape = "b" + case 2: shape = "h" + case 4: shape = "s" + case 8: shape = "d" + case 16: shape = "q" } // A predicate's suffix is its governing qualifier, and it hangs off a // slash rather than a dot. @@ -507,6 +508,9 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool) { case REG_ZT: strings.write_string(sb, uppercase ? "ZT" : "zt") write_decimal_u32(sb, u32(hw)) + case REG_ZA: + strings.write_string(sb, uppercase ? "ZA" : "za") + write_decimal_u32(sb, u32(hw)) } } @@ -531,6 +535,19 @@ write_operand :: proc( case .SYSTEM_REGISTER: write_sysreg(sb, op.sysreg, opts.uppercase) + case .ZA_SLICE: + // `za0h.b[w12, 0]` + strings.write_string(sb, opts.uppercase ? "ZA" : "za") + write_decimal_u32(sb, u32(op.za.tile)) + strings.write_byte(sb, op.za.vertical ? (opts.uppercase ? 'V' : 'v') : (opts.uppercase ? 'H' : 'h')) + write_vector_shape(sb, Register(REG_Z), op.za.elem, opts.uppercase) + strings.write_byte(sb, '[') + strings.write_string(sb, opts.uppercase ? "W" : "w") + write_decimal_u32(sb, 12 + u32(op.za.ws)) + strings.write_string(sb, opts.space_after_comma ? ", " : ",") + write_decimal_u32(sb, u32(op.za.offset)) + strings.write_byte(sb, ']') + case .COND: c := op.cond & 0xF s := COND_NAMES[c] diff --git a/core/rexcode/isa/arm64/registers.odin b/core/rexcode/isa/arm64/registers.odin index b0669b364..912c21c5e 100644 --- a/core/rexcode/isa/arm64/registers.odin +++ b/core/rexcode/isa/arm64/registers.odin @@ -36,6 +36,7 @@ REG_Z :: 0x0B00 // Z0..Z31 SVE scalable vector (low 128 aliased with V) REG_P :: 0x0C00 // P0..P15 SVE predicate REG_PN :: 0x0D00 // PN8..PN15 SME2 predicate-as-counter REG_ZT :: 0x0E00 // ZT0, the SME2 lookup table +REG_ZA :: 0x0F00 // ZA0..ZA15, SME's accumulator tiles NONE :: Register(0xFFFF) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 462bc4e82..a8ef0de57 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -88,8 +88,8 @@ DECODE_ENTRIES := [2548]lib.Decode_Entry{ { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 7b7adf71f..2c7b0c043 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -2967,9 +2967,9 @@ ENCODE_FORMS := [2546]lib.Encoding{ // .SUMOPA { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, // .LD1Q - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index b32dec079..3801ee5f6 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -3705,10 +3705,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, {written={0}, read={1, 2}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 550d00c5c473f644802782541428901f932c581e..129ffb42399e0a8a02d24f263e7751869e2ea732 100644 GIT binary patch delta 983 zcmYk5J8aWH9LE2?R4oOSL`fW2LX7|gClM0@K`L;C#8ygZlF~fD5&{Nj34NDWO&in) zsf1(|MzSI0C6GfqHrc|~Y)CYfheqlEBU2IP&OSSM@bLY<|9AJ@+52m@{WaU?U^goP zeue<58i-CnC;3)i2 zH6(T+hrIr;edJ)JmAa)=V;-Fn^4jspmg0X3)fh_?`TDhv+?Cgjol88-7MLh^E; zs+t|M_}xKRl0W5nW?XLMUCe~s(p_T!oaq`u3EkCO;Em)rMsmbTP8CS<6S68zj-aGI z^P#}w%$m;A03zk-C`#%4z{mu1w=pa8QZYnU1Bvz+w#Z7+hcmwvee5L0!XD&Q+;aqR zCrQsK`B%~G$7b(>NBLL zIg>z1edbu1$C>?Ql1X|}o=&0^;mY%Jw3B%%H!3dtZdJ1LFJVtO2S4$xO3TRUbYArb zf>j{Bfdx8J_h{L^7oC9K}3t3Fv!_WN^%zIHOQ<mT1bTgLzZ delta 983 zcmYk5J#5oJ9L4{>R4oOSL`fW2LX7|wClM0@K`L;C#8ygZlG1#DB?Ju6l713FQPKtq zEvbZL6-Kflufqe0*=BT zRYPJAayT5|OH0Ss@9D&0l0%fp@75b`b_zg%m!KB3KJgafPKDs%@U%2hJj3Q5g-Kok zR8_NM7P~tF%hIPJ&rC_pqKlc9+PZ5JfHPgAD6YHuOT3Z%%191d$;lE)enM8I$zhbx zXFim8oLSd-3P7Yh6+uaz9~hZn?lx*=UMdI4YLKNp#w@Z@9>AGj$^+~S#=;&HRNQkM zaVJU7S?O2V?8(vHjHB2c(sQ7~Gc!`C;$mi{`xW9MJxx~(#dX)m3U4I0jpVqM+|p-A zPje=Y68g-sDvvXVsw9*2q&$^CNy6pl)krrJmYOveez$A+%mVBQ=in#4)$AMObULs4 z`~jj(nws0~rdk$j1>NWIc&MgO-wL{NdIVk!<6Bk88IqG&r5f(0kkcdDTdLu`D}e9s z2odv!C>?xluyY~Os*8MQed2rM9b~{aCw<=t8bq|n34@&7q@-YxeuJb376Vv*jlVGU0@gImF6>%HW}B-sx^I{IY0)tnU8qn{KofxxN+3W; z;}F*+@ek0{d?; zieYC1M^-9>L*V%lJ@A}2nttm9bCC!z17aZ9B<3ECL*+$=dO{5v?3+ZB*akCOvoz*~ zZyF%lW<}v6R?{ql1>u_kNWzK=%wS0v3D&hSi-s_k0W8JJS)39+Vhzm<%stcvqbkop zlb9^1nTdJf+xmo&Q4hoyoaEIJsaP%Lid3pvskM|osWi0G zXerTAq%=1%@DaU>i*Mb->qghua*DQ9hYD}7+uFk0*T!KvMfa}Tift<7<#a2p2E9|CZPRMj79Lj{OX3kei zpz}bVm(vO}m6~s-0^fmC^V;Wl5~2fu$~LgCpBujcu#=}y<5w^+D%dz5ATHT`$-2-V@JklZzAoi+ zKX1?bVoPwE9ELv>U~ghD7`zi79AY-DSvVXP%(+{2JxlK2YQ!5}U87^|Uiwp-V1)p2 c1aNiDiS0cJ+1w~it0yHW72gMUe{bgIetLL(M3rI5HLVU z;}F*+@ek0k4v z+HHTLiKYp_42XeX$C$M;Pu8E0y@14S11kU8e)|}6n%(QNyk?eWCq1*LGfJ)sUQ_RXP5Y?GO-SqgK) zw*V0BvV!mtt813VyzngoB%rDS(^wQnf(>oVpdpMU086n_2Iqy3SW7blv-fqusLC_Y zBqj@LW@1kGxS(b^6AQw~4K*xaUKqJymlcJN3u;zGL-@F$Vx=O^v(LTYi(rVKtnniN z{A3##AD)57$+Uat+|P@l@+^n@_=)?ij~JQqz-ZY?T%MGQ)ln`?ZM=D923C@E?}n||j$&d78`8HcnNyf( z#+GOTsIZ?4xF0PKF1Rm9RO6efkVUG_!WSiIE6aDf`L)NUK0b!N~ZQXvy{M! zt(1aRIN_H}DD);sM&E!+br0g-%;~rEHvtUrs?j=+fj|I8CA%wGANm7+$pYHfr+n_G zow6@hfz!kU{H6f=JqClpTccy+%oa2Yhr@z7w`;Da;{K^cyy4X~I@TVfKcx*;2oNU$ bSJ#}_{-aQp8>MLVqy(knv)zOJ#q0k8;b4&b diff --git a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin index f7d0d8ff8..4f44ecf78 100644 --- a/core/rexcode/isa/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/isa/arm64/tests/pipeline_smoke.odin @@ -845,14 +845,12 @@ run_pipeline_tests :: proc() { // ld1b { za0v.b[w14, 5] }, p5/z, [x10, x21] = 0xE015D545 // // Per LLVM MC test for AArch64 SME (file: test/MC/AArch64/SME/ld1b.s). - // Slice descriptor (packed): imm=5, V=1 (vertical), Ws=W14 (idx=2), - // tile=0 (ZA0.B is implicit for byte tile) - // packed = 5 | (1<<4) | (2<<5) | (0<<7) = 0x55 + // Slice: tile 0 (ZA0.B is the only byte tile), taken vertically, indexed + // by W14 with an offset of 5. { clear(&relocs); clear(&errors) for i in 0.. Date: Fri, 28 Aug 2026 17:23:17 -0400 Subject: [PATCH 47/89] rexcode/arm64: adopt the upstream table formatting Upstream c9b28d2ec reformatted the whole instruction table: every row's clobber literal gained an explicit `Clobber` type name, the clobber column stopped being aligned in favour of a per-block target with a one-space minimum, and the mnemonic column was normalised to 17 for the 30 rows that were still at 16. Our six arm64 commits edited that table under the old formatting, so the two collided on nearly every line -- 39 conflict hunks, not one of them a real disagreement: upstream touched 40 mnemonics, we touched 160, and the intersection is empty. This applies their formatting to our rows so the merge has one style to reason about. Purely cosmetic: the file is byte-identical to its previous content once whitespace and the `Clobber` token are normalised away, and the rules were derived from their file rather than guessed -- reformatting the merge base with them reproduces their file exactly but for one `.MSR` row, whose operand sub-column they realigned by hand. arm64 pipeline: 133 passed, 0 failed, unchanged. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz --- .../isa/arm64/tablegen/instruction_table.odin | 5056 ++++++++--------- 1 file changed, 2510 insertions(+), 2546 deletions(-) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 3801ee5f6..3361fbc40 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -105,4189 +105,4153 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, .ADD = { - {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04000000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04400000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04800000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04000000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04400000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04800000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ADDS = { - {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SUB = { - {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, {written={0}, read={1}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04010000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04410000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04810000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04010000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04410000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04810000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SUBS = { - {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, {written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, {written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, {written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .AND = { - {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ANDS = { - {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { - {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04180000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04180000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EOR = { - {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04190000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04190000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BIC = { - {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BICS = { - {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { - {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EON = { - {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LSL = { - {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04138000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04538000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04938000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}}}, - {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04138000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04538000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04938000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .LSR = { - {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04118000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04518000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04918000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04118000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04518000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04918000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ASR = { - {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04108000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04508000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04908000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, {written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04108000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04508000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04908000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ROR = { - {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, {written={0}, read={1}}}, - {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04950000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04950000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04940000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04940000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04120000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04520000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04920000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04120000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04520000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04920000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04130000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04530000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04930000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04130000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04530000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04930000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSET = { - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSETM = { - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, {written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINC = { - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINV = { - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CNEG = { - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMP = { - {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMN = { - {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, {side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, {implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_EQ = { - {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_NE = { - {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_CS = { - {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_CC = { - {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_MI = { - {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_PL = { - {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_VS = { - {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_VC = { - {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_HI = { - {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_LS = { - {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_GE = { - {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_LT = { - {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_GT = { - {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_LE = { - {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_AL = { - {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .B_NV = { - {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, {read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, {written={0}}}, - {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, {written={0}}}, - {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, {read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, {read={1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, {written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, {written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, {written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, {side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, {side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, {written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, {side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, }, .FMOV = { - {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}}, - {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}}, - {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}}, - {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, - {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}}, + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}}, - {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65408000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65808000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65408000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65808000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65418000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65818000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65418000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65818000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65428000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65828000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65428000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65828000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654D8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658D8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, {written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65468000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65868000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65468000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65868000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65478000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65878000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65478000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65878000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65448000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65848000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65448000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65848000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65458000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65858000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65458000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65858000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .TST = { - {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, {written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, {written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, {written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, {written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, {written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, {written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, {written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, {implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, {read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, {read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, {written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, {read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, {written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, {written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, {written={0}, read={0}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, - {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, {written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, {written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, {written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, - {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, {written={0}, read={1, 2}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .MUL = { - {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04100000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04500000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04900000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04100000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04500000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04900000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MLA = { - {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .MLS = { - {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .NEG = { - {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, {written={0}, read={1}}}, - {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ABS = { - {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04080000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04480000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04880000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04080000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04480000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04880000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04090000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04490000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04890000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04090000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04490000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04890000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048A0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048B0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048C0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048D0000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ADDP = { - {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SMULL = { - {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMULL2 = { - {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL = { - {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL2 = { - {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, {written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .FMLA = { - {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMLS = { - {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMAXP = { - {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINP = { - {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXV = { - {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINV = { - {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, }, .FADDP = { - {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SHL = { - {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHL = { - {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, {written={0}, read={0, 1}}}, + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .DUP = { - {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, {written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, }, .MOV = { - {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}}, - {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}}, - {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}}, - {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}}, - {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}}, - {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}}, + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOV, {.P_REG_S, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .EXT = { - {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, {written={0}, read={0, 1, 2}}}, - {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .NOT = { - {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .URECPE = { - {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSQRTE = { - {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, - {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}}, + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, {written={0}}}, + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, {written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, {read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, {read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04030000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04430000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04830000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04030000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04430000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04830000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ASRR = { - {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSLR = { - {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSRR = { - {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .FTSMUL = { - {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUBR = { - {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIVR = { - {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMLA = { - {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .FNMLS = { - {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, {written={0}}}, + {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, {written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, {written={0}}}, + {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_H, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, {written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, {read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, }, .SETFFR = { - {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, {side_effects={.FFR}}}, + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { - {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, {written={0}, read={1}}}, - {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, {written={0}, read={1}}}, + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .CPY = { - {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .COMPACT = { - {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}}}, - {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4C08000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { - {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQRDMLSH = { - {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .ADCLB = { - {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADCLT = { - {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLB = { - {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLT = { - {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, - {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { - {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, - {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .HISTSEG = { - {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMSTART = { - {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .SMSTOP = { - {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, {}}, + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, {written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, }, .ADDHA = { - {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ADDVA = { - {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, {}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, }, .FMOPA = { - {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMOPS = { - {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPA = { - {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPS = { - {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SMOPA = { - {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SMOPS = { - {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPA = { - {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPS = { - {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, - {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, {written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .USMOPA = { - {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SUMOPA = { - {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, {written={0}, read={0, 1, 2, 3}}}, + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, {written={0}, read={1, 2}}}, - {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, {written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, {written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { - {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, {read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { - {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}}}, + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, {written={0}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, {written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BSL1N = { - {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BSL2N = { - {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NBSL = { - {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2, 3}}}, + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .PMUL = { - {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, {written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVTNT = { - {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .LDRAA = { - {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .LDRAB = { - {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, {written={0}, read={1}, reads_mem=true}}, - {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, {written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}, side_effects={.NONDETERMINISTIC}}}, + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, }, .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, {}}, + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, }, .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, {side_effects={.CONTROL}}}, + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, }, .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, {written={0}}}, + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.WAIT}}}, + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .BC_EQ = { - {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_NE = { - {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_CS = { - {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_CC = { - {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_MI = { - {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_PL = { - {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_VS = { - {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_VC = { - {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_HI = { - {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_LS = { - {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_GE = { - {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_LT = { - {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_GT = { - {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_LE = { - {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, {nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_AL = { - {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BC_NV = { - {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, {side_effects={.CONTROL}}}, + {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, {written={0}, read={1}}}, + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, {written={0}, read={1}}}, + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, {written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, }, .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLUR = { - {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURB = { - {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURH = { - {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, {read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, {written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65008000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65008000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65018000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65018000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65028000, 0xFFFFE000, .SVE, {}}, {written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65028000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { - {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLS = { - {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, {written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.FENCE}}}, + {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.HINT}}}, + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, {side_effects={.BTI}}}, + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BFCLAMP = { - {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, {written={0}, read={1, 2}}}, + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65048000, 0xFFFFE000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65048000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, {written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, {written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, {written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, {written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, {written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, {written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, {}}, + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, {read={0}}}, + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, {written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, writes_mem=true, side_effects={.CACHE}}}, + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, }, .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.CACHE}}}, + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, {read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, {side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .PRFM = { - {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, - {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, {side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, }, .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, {read={1}, side_effects={.HINT}}}, + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, {written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMP = { - {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMN = { - {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, {read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, {read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, } From 55da0990e7b80ad38cae2b04f325c6ea58e9b897 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fl=C4=81vius?= Date: Fri, 28 Aug 2026 18:19:26 -0400 Subject: [PATCH 48/89] rexcode/arm64: restore the four SVE encodings the tests already asserted The tests said one thing and the table another: WHILELT and the three SVE scatter stores. The tests were right and had been right for a while -- the table edit that went with them was never committed, and the branch looked green only because the tests read a stale generated blob that still carried the fix. Regenerating the blobs (which merging upstream forced, since its 35 new mnemonics overflowed the old ones) made the disagreement visible. WHILELT mask 0xFF20FC10 -> 0xFFE0FC10 ST1B scatter Zt.S 0xE4008000 -> 0xE4408000, mask 0xFFA0E000 -> 0xFFE0A000 ST1W scatter Zt.S 0xE5008000 -> 0xE5408000, mask 0xFFA0E000 -> 0xFFE0A000 ST1D scatter Zt.D bits unchanged, mask 0xFFA0E000 -> 0xFFE0A000 ST1B and ST1W carried the SAME bits for their Zt.S and Zt.D forms, so the 32-bit scatter was encoding as the 64-bit one; the S rows now differ from the D rows beside them, which is what tells them apart. Values taken from the committed test expectations and independently corroborated by the pre-regeneration blob -- two sources that agree. arm64: 330 passed 0 failed, 133 passed 0 failed. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz --- .../tablegen/generated/decode_tables.odin | 8 ++++---- .../tablegen/generated/encode_tables.odin | 8 ++++---- .../isa/arm64/tablegen/instruction_table.odin | 8 ++++---- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 52680 -> 52680 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 52720 -> 52720 bytes 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 102de694a..c4762cdf8 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -362,6 +362,7 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -566,7 +567,6 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, @@ -713,13 +713,13 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index d6c86d484..37da435b2 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -2822,7 +2822,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, @@ -2836,14 +2836,14 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, @@ -2862,7 +2862,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ // .WHILELE { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 54db87aa6..2bf59540f 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -3517,7 +3517,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1B = { {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3533,7 +3533,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1W = { {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3541,7 +3541,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1D = { {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3568,7 +3568,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 8968cd07057558f6aa0000815e622777ca503ad7..3e16b6aa1bf3e0c3c4758ac33e477f9aca95f6a7 100644 GIT binary patch delta 43 xcmX>xoB70S<_&k&usS?pSny!-!!@s29iD<%7uS|C0V&UQw;3O7R$aeX4gmX67Wx1H delta 43 xcmX>xoB70S<_&k&urfShc(7pd!!@s28J>bz7uS|C0V&UQw;2^StFB)x2LS1j6}kWb diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index 70ed78490bb7136433b12999923c09b514570bd7..9739251df05e4c687fa5d468908e1b5a6e131081 100644 GIT binary patch delta 68 zcmew`oB6|R<_%M%MN*g)nV1;7SlAgDL=;p7{yg~4SFw4D^auXUGqg*%Ssk7*EO;?>> OYD^CnZ0 Date: Fri, 28 Aug 2026 19:15:45 -0400 Subject: [PATCH 49/89] rexcode/arm64: restore the SVE encodings the table reformat dropped Adopting the upstream table formatting in 4683ce0fd took the upstream rows wholesale, which reverted a run of encoding fixes that had been verified against llvm-mc. 78 rows came back with older operand types, encodings or masks, and 37 were dropped outright -- the WHILE family's four element sizes and INDEX's, which had been split from one size-generic form each. Restored as they were: the WHILE and INDEX size splits; the scatter forms, whose .s variants had gone back to carrying the .d encoding so each pair had identical bits again; the gather and scatter index addressing; the predicate element sizes, and the predicate-mask operations that must stay .b; SVE LDR/STR's unsized operands. Against llvm-mc this puts SVE/SME2 back at 559 byte-exact from 450. 18 mismatches remain, all of them in rows the merge brought in -- the SQINCP/UQINCP/INCP family reads its predicate from the wrong field -- and are dealt with separately. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/mnemonic_builders.odin | 216 ++++- .../tablegen/generated/decode_tables.odin | 219 +++--- .../tablegen/generated/encode_tables.odin | 740 ++++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 193 +++-- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 36876 -> 37394 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 52680 -> 53420 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6848 -> 6848 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 52720 -> 53460 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes 9 files changed, 864 insertions(+), 504 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 7939b2b38..4e7e5da6e 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -3768,17 +3768,17 @@ emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_st1b_zpb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zpb_pn_m(rz, rz2, mem)) } emit_st1b_zqb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zqb_pn_m(rz, rz2, mem)) } inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } emit_st1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zh_p_m(rz, rz2, mem)) } -emit_st1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zs_p_m(rz, rz2, mem)) } emit_st1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zd_p_m(rz, rz2, mem)) } emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } emit_st1h_zph_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zph_pn_m(rz, rz2, mem)) } emit_st1h_zqh_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zqh_pn_m(rz, rz2, mem)) } +emit_st1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zs_p_m(rz, rz2, mem)) } inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } @@ -3957,6 +3957,148 @@ inst_usmopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1 emit_usmopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_zb(imm, rz1, rz2, rz3)) } inst_sumopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } emit_sumopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_zb(imm, rz1, rz2, rz3)) } +inst_cntb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_cntb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntb_r_i_i(dst, imm, imm2)) } +inst_cnth_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_cnth_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cnth_r_i_i(dst, imm, imm2)) } +inst_cntw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_cntw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntw_r_i_i(dst, imm, imm2)) } +inst_cntd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_cntd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntd_r_i_i(dst, imm, imm2)) } +inst_incb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_incb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incb_r_i_i(dst, imm, imm2)) } +inst_inch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_inch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_inch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_inch_r_i_i(dst, imm, imm2)) } +emit_inch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_inch_zh_i_i(rz, imm, imm2)) } +inst_incw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_incw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incw_r_i_i(dst, imm, imm2)) } +emit_incw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incw_zs_i_i(rz, imm, imm2)) } +inst_incd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_incd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incd_r_i_i(dst, imm, imm2)) } +emit_incd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incd_zd_i_i(rz, imm, imm2)) } +inst_decb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_decb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decb_r_i_i(dst, imm, imm2)) } +inst_dech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_dech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_dech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_dech_r_i_i(dst, imm, imm2)) } +emit_dech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_dech_zh_i_i(rz, imm, imm2)) } +inst_decw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_decw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decw_r_i_i(dst, imm, imm2)) } +emit_decw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decw_zs_i_i(rz, imm, imm2)) } +inst_decd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_decd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decd_r_i_i(dst, imm, imm2)) } +emit_decd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decd_zd_i_i(rz, imm, imm2)) } +inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_i_i(dst, imm, imm2)) } +inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_i_i(dst, imm, imm2)) } +emit_sqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqinch_zh_i_i(rz, imm, imm2)) } +inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_i_i(dst, imm, imm2)) } +emit_sqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincw_zs_i_i(rz, imm, imm2)) } +inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_i_i(dst, imm, imm2)) } +emit_sqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincd_zd_i_i(rz, imm, imm2)) } +inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_i_i(dst, imm, imm2)) } +inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_i_i(dst, imm, imm2)) } +emit_sqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdech_zh_i_i(rz, imm, imm2)) } +inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_i_i(dst, imm, imm2)) } +emit_sqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_zs_i_i(rz, imm, imm2)) } +inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_sqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_i_i(dst, imm, imm2)) } +emit_sqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_zd_i_i(rz, imm, imm2)) } +inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincb_r_i_i(dst, imm, imm2)) } +inst_uqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqinch_r_i_i(dst, imm, imm2)) } +emit_uqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqinch_zh_i_i(rz, imm, imm2)) } +inst_uqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincw_r_i_i(dst, imm, imm2)) } +emit_uqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincw_zs_i_i(rz, imm, imm2)) } +inst_uqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincd_r_i_i(dst, imm, imm2)) } +emit_uqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincd_zd_i_i(rz, imm, imm2)) } +inst_uqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecb_r_i_i(dst, imm, imm2)) } +inst_uqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdech_r_i_i(dst, imm, imm2)) } +emit_uqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdech_zh_i_i(rz, imm, imm2)) } +inst_uqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_r_i_i(dst, imm, imm2)) } +emit_uqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_zs_i_i(rz, imm, imm2)) } +inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +emit_uqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_r_i_i(dst, imm, imm2)) } +emit_uqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_zd_i_i(rz, imm, imm2)) } +inst_cntp_r_p_p :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +emit_cntp_r_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_p(dst, rz1, rz2)) } +inst_incp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_incp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_p(dst, rz1)) } +emit_incp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_p(rz, rz2)) } +emit_incp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_p(rz, rz2)) } +emit_incp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_p(rz, rz2)) } +inst_decp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_decp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_p(dst, rz1)) } +emit_decp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_p(rz, rz2)) } +emit_decp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_p(rz, rz2)) } +emit_decp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_p(rz, rz2)) } +inst_sqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_p(dst, rz1)) } +emit_sqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_p(rz, rz2)) } +emit_sqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_p(rz, rz2)) } +emit_sqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_p(rz, rz2)) } +inst_sqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_p(dst, rz1)) } +emit_sqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_p(rz, rz2)) } +emit_sqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_p(rz, rz2)) } +emit_sqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_p(rz, rz2)) } +inst_uqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_p(dst, rz1)) } +emit_uqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_p(rz, rz2)) } +emit_uqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_p(rz, rz2)) } +emit_uqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_p(rz, rz2)) } +inst_uqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_p(dst, rz1)) } +emit_uqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_p(rz, rz2)) } +emit_uqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_p(rz, rz2)) } +emit_uqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_p(rz, rz2)) } inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } @@ -5674,6 +5816,76 @@ inst_usmopa :: inst_usmopa_i_p_p_zb emit_usmopa :: emit_usmopa_i_p_p_zb inst_sumopa :: inst_sumopa_i_p_p_zb emit_sumopa :: emit_sumopa_i_p_p_zb +inst_cntb :: inst_cntb_r_i_i +emit_cntb :: emit_cntb_r_i_i +inst_cnth :: inst_cnth_r_i_i +emit_cnth :: emit_cnth_r_i_i +inst_cntw :: inst_cntw_r_i_i +emit_cntw :: emit_cntw_r_i_i +inst_cntd :: inst_cntd_r_i_i +emit_cntd :: emit_cntd_r_i_i +inst_incb :: inst_incb_r_i_i +emit_incb :: emit_incb_r_i_i +inst_inch :: proc{ inst_inch_r_i_i, inst_inch_zh_i_i } +emit_inch :: proc{ emit_inch_r_i_i, emit_inch_zh_i_i } +inst_incw :: proc{ inst_incw_r_i_i, inst_incw_zs_i_i } +emit_incw :: proc{ emit_incw_r_i_i, emit_incw_zs_i_i } +inst_incd :: proc{ inst_incd_r_i_i, inst_incd_zd_i_i } +emit_incd :: proc{ emit_incd_r_i_i, emit_incd_zd_i_i } +inst_decb :: inst_decb_r_i_i +emit_decb :: emit_decb_r_i_i +inst_dech :: proc{ inst_dech_r_i_i, inst_dech_zh_i_i } +emit_dech :: proc{ emit_dech_r_i_i, emit_dech_zh_i_i } +inst_decw :: proc{ inst_decw_r_i_i, inst_decw_zs_i_i } +emit_decw :: proc{ emit_decw_r_i_i, emit_decw_zs_i_i } +inst_decd :: proc{ inst_decd_r_i_i, inst_decd_zd_i_i } +emit_decd :: proc{ emit_decd_r_i_i, emit_decd_zd_i_i } +inst_sqincb :: inst_sqincb_r_i_i +emit_sqincb :: emit_sqincb_r_i_i +inst_sqinch :: proc{ inst_sqinch_r_i_i, inst_sqinch_zh_i_i } +emit_sqinch :: proc{ emit_sqinch_r_i_i, emit_sqinch_zh_i_i } +inst_sqincw :: proc{ inst_sqincw_r_i_i, inst_sqincw_zs_i_i } +emit_sqincw :: proc{ emit_sqincw_r_i_i, emit_sqincw_zs_i_i } +inst_sqincd :: proc{ inst_sqincd_r_i_i, inst_sqincd_zd_i_i } +emit_sqincd :: proc{ emit_sqincd_r_i_i, emit_sqincd_zd_i_i } +inst_sqdecb :: inst_sqdecb_r_i_i +emit_sqdecb :: emit_sqdecb_r_i_i +inst_sqdech :: proc{ inst_sqdech_r_i_i, inst_sqdech_zh_i_i } +emit_sqdech :: proc{ emit_sqdech_r_i_i, emit_sqdech_zh_i_i } +inst_sqdecw :: proc{ inst_sqdecw_r_i_i, inst_sqdecw_zs_i_i } +emit_sqdecw :: proc{ emit_sqdecw_r_i_i, emit_sqdecw_zs_i_i } +inst_sqdecd :: proc{ inst_sqdecd_r_i_i, inst_sqdecd_zd_i_i } +emit_sqdecd :: proc{ emit_sqdecd_r_i_i, emit_sqdecd_zd_i_i } +inst_uqincb :: inst_uqincb_r_i_i +emit_uqincb :: emit_uqincb_r_i_i +inst_uqinch :: proc{ inst_uqinch_r_i_i, inst_uqinch_zh_i_i } +emit_uqinch :: proc{ emit_uqinch_r_i_i, emit_uqinch_zh_i_i } +inst_uqincw :: proc{ inst_uqincw_r_i_i, inst_uqincw_zs_i_i } +emit_uqincw :: proc{ emit_uqincw_r_i_i, emit_uqincw_zs_i_i } +inst_uqincd :: proc{ inst_uqincd_r_i_i, inst_uqincd_zd_i_i } +emit_uqincd :: proc{ emit_uqincd_r_i_i, emit_uqincd_zd_i_i } +inst_uqdecb :: inst_uqdecb_r_i_i +emit_uqdecb :: emit_uqdecb_r_i_i +inst_uqdech :: proc{ inst_uqdech_r_i_i, inst_uqdech_zh_i_i } +emit_uqdech :: proc{ emit_uqdech_r_i_i, emit_uqdech_zh_i_i } +inst_uqdecw :: proc{ inst_uqdecw_r_i_i, inst_uqdecw_zs_i_i } +emit_uqdecw :: proc{ emit_uqdecw_r_i_i, emit_uqdecw_zs_i_i } +inst_uqdecd :: proc{ inst_uqdecd_r_i_i, inst_uqdecd_zd_i_i } +emit_uqdecd :: proc{ emit_uqdecd_r_i_i, emit_uqdecd_zd_i_i } +inst_cntp :: inst_cntp_r_p_p +emit_cntp :: emit_cntp_r_p_p +inst_incp :: proc{ inst_incp_r_p, inst_incp_zh_p } +emit_incp :: proc{ emit_incp_r_p, emit_incp_zh_p } +inst_decp :: proc{ inst_decp_r_p, inst_decp_zh_p } +emit_decp :: proc{ emit_decp_r_p, emit_decp_zh_p } +inst_sqincp :: proc{ inst_sqincp_r_p, inst_sqincp_zh_p } +emit_sqincp :: proc{ emit_sqincp_r_p, emit_sqincp_zh_p } +inst_sqdecp :: proc{ inst_sqdecp_r_p, inst_sqdecp_zh_p } +emit_sqdecp :: proc{ emit_sqdecp_r_p, emit_sqdecp_zh_p } +inst_uqincp :: proc{ inst_uqincp_r_p, inst_uqincp_zh_p } +emit_uqincp :: proc{ emit_uqincp_r_p, emit_uqincp_zh_p } +inst_uqdecp :: proc{ inst_uqdecp_r_p, inst_uqdecp_zh_p } +emit_uqdecp :: proc{ emit_uqdecp_r_p, emit_uqdecp_zh_p } inst_ld1q :: inst_ld1q_i_p_m emit_ld1q :: emit_ld1q_i_p_m inst_st1q :: inst_st1q_i_p_m diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index c4762cdf8..0880cc546 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2636]lib.Decode_Entry{ +DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -88,17 +88,17 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, - { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, - { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, - { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, - { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, @@ -163,8 +163,8 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -184,11 +184,11 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -314,12 +314,12 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -362,7 +362,38 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -539,10 +570,22 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, @@ -559,27 +602,20 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, @@ -591,14 +627,14 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, @@ -645,8 +681,8 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, @@ -658,7 +694,7 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, @@ -701,25 +737,26 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, @@ -2650,18 +2687,18 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 81}, - 0x02 = { 81, 630}, - 0x04 = { 711, 76}, - 0x05 = { 787, 50}, - 0x06 = { 837, 56}, - 0x07 = { 893, 1058}, - 0x08 = {1951, 16}, - 0x09 = {1967, 34}, - 0x0A = {2001, 130}, - 0x0B = {2131, 21}, - 0x0C = {2152, 167}, - 0x0D = {2319, 122}, - 0x0E = {2441, 19}, - 0x0F = {2460, 176}, + 0x02 = { 81, 667}, + 0x04 = { 748, 76}, + 0x05 = { 824, 50}, + 0x06 = { 874, 56}, + 0x07 = { 930, 1058}, + 0x08 = {1988, 16}, + 0x09 = {2004, 34}, + 0x0A = {2038, 130}, + 0x0B = {2168, 21}, + 0x0C = {2189, 167}, + 0x0D = {2356, 122}, + 0x0E = {2478, 19}, + 0x0F = {2497, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 37da435b2..aedfd2e53 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2634]lib.Encoding{ +ENCODE_FORMS := [2671]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -87,13 +87,13 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -104,7 +104,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -115,7 +115,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -124,16 +124,16 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, @@ -243,7 +243,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, @@ -384,8 +384,8 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -401,8 +401,8 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Z_REG_B,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -1288,16 +1288,16 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .AESE { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESD { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESMC { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .AESIMC { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESIMC, {.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=1} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .SHA1H { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA1C @@ -2424,7 +2424,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_S,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, @@ -2433,7 +2433,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.IMM_8}, {.VD,.VD,.VM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2457,7 +2457,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2470,7 +2470,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2483,7 +2483,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2496,7 +2496,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2509,7 +2509,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2522,11 +2522,11 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, @@ -2663,23 +2663,23 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG_S,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG_B,.P_REG,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG_H,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG_D,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES @@ -2687,27 +2687,27 @@ ENCODE_FORMS := [2634]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_H,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG_S,.P_REG_MERGE,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG_H,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG_D,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR - { .WRFFR, {.P_REG,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ @@ -2783,67 +2783,68 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, // .ST1W { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, @@ -2856,21 +2857,45 @@ ENCODE_FORMS := [2634]lib.Encoding{ // .LDFF1D { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE - { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT - { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELE - { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI - { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS - { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELO - { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELS - { .WHILELS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .SQRDMLAH { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, @@ -3102,9 +3127,9 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .UQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .UQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .LD1Q - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, @@ -3145,10 +3170,22 @@ ENCODE_FORMS := [2634]lib.Encoding{ // .SPLICE { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5,.RN,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, // .BSL1N { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .BSL2N @@ -3501,7 +3538,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2634]lib.Clobber{ +CLOBBER_FORMS := [2671]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -6327,6 +6364,7 @@ CLOBBER_FORMS := [2634]lib.Clobber{ {read={0, 1, 2}, writes_mem=true}, {read={0, 1, 2}, writes_mem=true}, {read={0, 1, 2}, writes_mem=true}, + {read={0, 1, 2}, writes_mem=true}, // .ST1W {read={0, 1, 2}, writes_mem=true}, {read={0, 1, 2}, writes_mem=true}, @@ -6350,20 +6388,44 @@ CLOBBER_FORMS := [2634]lib.Clobber{ {written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}, // .WHILEGE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEGT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELE {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELT {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEHI {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILEHS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELO {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .WHILELS {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, + {written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}, // .SQRDMLAH {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, {written={0}, read={0, 1, 2}, fpsr_wr={.QC}}, @@ -6642,6 +6704,18 @@ CLOBBER_FORMS := [2634]lib.Clobber{ {written={0}, read={2}}, {written={0}, read={1}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .BSL1N {written={0}, read={1, 2, 3}}, // .BSL2N @@ -7597,258 +7671,258 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .LD1SH = { 2205, 4}, .LD1SW = { 2209, 2}, .ST1B = { 2211, 6}, - .ST1H = { 2217, 6}, - .ST1W = { 2223, 6}, - .ST1D = { 2229, 5}, - .LDFF1B = { 2234, 1}, - .LDFF1H = { 2235, 1}, - .LDFF1W = { 2236, 1}, - .LDFF1D = { 2237, 1}, - .WHILEGE = { 2238, 1}, - .WHILEGT = { 2239, 1}, - .WHILELE = { 2240, 1}, - .WHILELT = { 2241, 1}, - .WHILEHI = { 2242, 1}, - .WHILEHS = { 2243, 1}, - .WHILELO = { 2244, 1}, - .WHILELS = { 2245, 1}, - .SQRDMLAH = { 2246, 4}, - .SQRDMLSH = { 2250, 4}, - .ADCLB = { 2254, 2}, - .ADCLT = { 2256, 2}, - .SBCLB = { 2258, 2}, - .SBCLT = { 2260, 2}, - .TBL2 = { 2262, 1}, - .MATCH = { 2263, 2}, - .NMATCH = { 2265, 2}, - .HISTCNT = { 2267, 2}, - .HISTSEG = { 2269, 1}, - .SMSTART = { 2270, 1}, - .SMSTOP = { 2271, 1}, - .RDSVL = { 2272, 1}, - .ADDHA = { 2273, 1}, - .ADDVA = { 2274, 1}, - .ZERO = { 2275, 1}, - .FMOPA = { 2276, 1}, - .FMOPS = { 2277, 1}, - .BFMOPA = { 2278, 1}, - .BFMOPS = { 2279, 1}, - .SMOPA = { 2280, 2}, - .SMOPS = { 2282, 2}, - .UMOPA = { 2284, 2}, - .UMOPS = { 2286, 2}, - .USMOPA = { 2288, 1}, - .SUMOPA = { 2289, 1}, - .CNTB = { 2290, 1}, - .CNTH = { 2291, 1}, - .CNTW = { 2292, 1}, - .CNTD = { 2293, 1}, - .INCB = { 2294, 1}, - .INCH = { 2295, 2}, - .INCW = { 2297, 2}, - .INCD = { 2299, 2}, - .DECB = { 2301, 1}, - .DECH = { 2302, 2}, - .DECW = { 2304, 2}, - .DECD = { 2306, 2}, - .SQINCB = { 2308, 2}, - .SQINCH = { 2310, 3}, - .SQINCW = { 2313, 3}, - .SQINCD = { 2316, 3}, - .SQDECB = { 2319, 2}, - .SQDECH = { 2321, 3}, - .SQDECW = { 2324, 3}, - .SQDECD = { 2327, 3}, - .UQINCB = { 2330, 2}, - .UQINCH = { 2332, 3}, - .UQINCW = { 2335, 3}, - .UQINCD = { 2338, 3}, - .UQDECB = { 2341, 2}, - .UQDECH = { 2343, 3}, - .UQDECW = { 2346, 3}, - .UQDECD = { 2349, 3}, - .CNTP = { 2352, 4}, - .INCP = { 2356, 7}, - .DECP = { 2363, 7}, - .SQINCP = { 2370, 11}, - .SQDECP = { 2381, 11}, - .UQINCP = { 2392, 11}, - .UQDECP = { 2403, 11}, - .LD1Q = { 2414, 1}, - .ST1Q = { 2415, 1}, - .MOVA = { 2416, 2}, - .FCMLA = { 2418, 4}, - .FCADD = { 2422, 4}, - .PRFB = { 2426, 1}, - .PRFH = { 2427, 1}, - .PRFW = { 2428, 1}, - .PRFD = { 2429, 1}, - .LDNT1B = { 2430, 1}, - .LDNT1H = { 2431, 1}, - .LDNT1W = { 2432, 1}, - .LDNT1D = { 2433, 1}, - .STNT1B = { 2434, 1}, - .STNT1H = { 2435, 1}, - .STNT1W = { 2436, 1}, - .STNT1D = { 2437, 1}, - .SPLICE = { 2438, 1}, - .INDEX = { 2439, 4}, - .BSL1N = { 2443, 1}, - .BSL2N = { 2444, 1}, - .NBSL = { 2445, 1}, - .PMUL = { 2446, 1}, - .PMULLB = { 2447, 1}, - .PMULLT = { 2448, 1}, - .BFCVTNT = { 2449, 1}, - .LDRAA = { 2450, 2}, - .LDRAB = { 2452, 2}, - .TSTART = { 2454, 1}, - .TCOMMIT = { 2455, 1}, - .TCANCEL = { 2456, 1}, - .TTEST = { 2457, 1}, - .WFET = { 2458, 1}, - .WFIT = { 2459, 1}, - .BC_EQ = { 2460, 1}, - .BC_NE = { 2461, 1}, - .BC_CS = { 2462, 1}, - .BC_CC = { 2463, 1}, - .BC_MI = { 2464, 1}, - .BC_PL = { 2465, 1}, - .BC_VS = { 2466, 1}, - .BC_VC = { 2467, 1}, - .BC_HI = { 2468, 1}, - .BC_LS = { 2469, 1}, - .BC_GE = { 2470, 1}, - .BC_LT = { 2471, 1}, - .BC_GT = { 2472, 1}, - .BC_LE = { 2473, 1}, - .BC_AL = { 2474, 1}, - .BC_NV = { 2475, 1}, - .UXTB = { 2476, 1}, - .UXTH = { 2477, 1}, - .UXTW = { 2478, 1}, - .SXTB = { 2479, 1}, - .SXTH = { 2480, 1}, - .SXTW = { 2481, 1}, - .ADC = { 2482, 2}, - .ADCS = { 2484, 2}, - .SBC = { 2486, 2}, - .SBCS = { 2488, 2}, - .NGC = { 2490, 2}, - .NGCS = { 2492, 2}, - .LDAPUR = { 2494, 2}, - .STLUR = { 2496, 2}, - .LDAPURB = { 2498, 1}, - .STLURB = { 2499, 1}, - .LDAPURH = { 2500, 1}, - .STLURH = { 2501, 1}, - .LDAPURSB = { 2502, 2}, - .LDAPURSH = { 2504, 2}, - .LDAPURSW = { 2506, 1}, - .BFADD = { 2507, 2}, - .BFSUB = { 2509, 2}, - .BFMUL = { 2511, 2}, - .BFMLA = { 2513, 1}, - .BFMLS = { 2514, 1}, - .SB = { 2515, 1}, - .CSDB = { 2516, 1}, - .DGH = { 2517, 1}, - .PSB_CSYNC = { 2518, 1}, - .TSB_CSYNC = { 2519, 1}, - .BTI_J = { 2520, 1}, - .BTI_C = { 2521, 1}, - .BTI_JC = { 2522, 1}, - .BFCLAMP = { 2523, 1}, - .BFMAXNM = { 2524, 1}, - .BFMINNM = { 2525, 1}, - .LUTI2 = { 2526, 3}, - .LUTI4 = { 2529, 3}, - .ZIP = { 2532, 2}, - .UZP = { 2534, 2}, - .TLBI_RPALOS = { 2536, 1}, - .TLBI_RPAOS = { 2537, 1}, - .AT_S1E1A = { 2538, 1}, - .DC_CIPAPA = { 2539, 1}, - .DC_CIGDPAPA = { 2540, 1}, - .TLBI_PAALL = { 2541, 1}, - .TLBI_PAALLOS = { 2542, 1}, - .AMX_LDX = { 2543, 1}, - .AMX_LDY = { 2544, 1}, - .AMX_STX = { 2545, 1}, - .AMX_STY = { 2546, 1}, - .AMX_LDZ = { 2547, 1}, - .AMX_STZ = { 2548, 1}, - .AMX_LDZI = { 2549, 1}, - .AMX_STZI = { 2550, 1}, - .AMX_EXTRX = { 2551, 1}, - .AMX_EXTRY = { 2552, 1}, - .AMX_FMA64 = { 2553, 1}, - .AMX_FMS64 = { 2554, 1}, - .AMX_FMA32 = { 2555, 1}, - .AMX_FMS32 = { 2556, 1}, - .AMX_MAC16 = { 2557, 1}, - .AMX_FMA16 = { 2558, 1}, - .AMX_FMS16 = { 2559, 1}, - .AMX_SET = { 2560, 1}, - .AMX_CLR = { 2561, 1}, - .AMX_VECINT = { 2562, 1}, - .AMX_VECFP = { 2563, 1}, - .AMX_MATINT = { 2564, 1}, - .AMX_MATFP = { 2565, 1}, - .AMX_GENLUT = { 2566, 1}, - .CPYP = { 2567, 1}, - .CPYM = { 2568, 1}, - .CPYE = { 2569, 1}, - .CPYFP = { 2570, 1}, - .CPYFM = { 2571, 1}, - .CPYFE = { 2572, 1}, - .SETP = { 2573, 1}, - .SETM = { 2574, 1}, - .SETE = { 2575, 1}, - .DC_IVAC = { 2576, 1}, - .DC_ISW = { 2577, 1}, - .DC_CSW = { 2578, 1}, - .DC_CISW = { 2579, 1}, - .DC_ZVA = { 2580, 1}, - .DC_CVAC = { 2581, 1}, - .DC_CVAU = { 2582, 1}, - .DC_CIVAC = { 2583, 1}, - .IC_IALLUIS = { 2584, 1}, - .IC_IALLU = { 2585, 1}, - .IC_IVAU = { 2586, 1}, - .AT_S1E1R = { 2587, 1}, - .AT_S1E1W = { 2588, 1}, - .AT_S1E0R = { 2589, 1}, - .AT_S1E0W = { 2590, 1}, - .AT_S1E2R = { 2591, 1}, - .AT_S1E2W = { 2592, 1}, - .AT_S1E3R = { 2593, 1}, - .AT_S1E3W = { 2594, 1}, - .AT_S12E1R = { 2595, 1}, - .AT_S12E1W = { 2596, 1}, - .AT_S12E0R = { 2597, 1}, - .AT_S12E0W = { 2598, 1}, - .TLBI_VMALLE1 = { 2599, 1}, - .TLBI_VMALLE1IS = { 2600, 1}, - .TLBI_VAE1 = { 2601, 1}, - .TLBI_VAE1IS = { 2602, 1}, - .TLBI_ASIDE1 = { 2603, 1}, - .TLBI_ASIDE1IS = { 2604, 1}, - .TLBI_VAAE1 = { 2605, 1}, - .TLBI_VAAE1IS = { 2606, 1}, - .TLBI_VALE1 = { 2607, 1}, - .TLBI_VALE1IS = { 2608, 1}, - .TLBI_VAALE1 = { 2609, 1}, - .TLBI_VAALE1IS = { 2610, 1}, - .TLBI_ALLE1 = { 2611, 1}, - .TLBI_ALLE1IS = { 2612, 1}, - .TLBI_ALLE2 = { 2613, 1}, - .TLBI_ALLE2IS = { 2614, 1}, - .TLBI_ALLE3 = { 2615, 1}, - .TLBI_ALLE3IS = { 2616, 1}, - .PRFM = { 2617, 2}, - .PRFUM = { 2619, 1}, - .NEGS = { 2620, 2}, - .CMP = { 2622, 6}, - .CMN = { 2628, 6}, + .ST1H = { 2217, 7}, + .ST1W = { 2224, 6}, + .ST1D = { 2230, 5}, + .LDFF1B = { 2235, 1}, + .LDFF1H = { 2236, 1}, + .LDFF1W = { 2237, 1}, + .LDFF1D = { 2238, 1}, + .WHILEGE = { 2239, 4}, + .WHILEGT = { 2243, 4}, + .WHILELE = { 2247, 4}, + .WHILELT = { 2251, 4}, + .WHILEHI = { 2255, 4}, + .WHILEHS = { 2259, 4}, + .WHILELO = { 2263, 4}, + .WHILELS = { 2267, 4}, + .SQRDMLAH = { 2271, 4}, + .SQRDMLSH = { 2275, 4}, + .ADCLB = { 2279, 2}, + .ADCLT = { 2281, 2}, + .SBCLB = { 2283, 2}, + .SBCLT = { 2285, 2}, + .TBL2 = { 2287, 1}, + .MATCH = { 2288, 2}, + .NMATCH = { 2290, 2}, + .HISTCNT = { 2292, 2}, + .HISTSEG = { 2294, 1}, + .SMSTART = { 2295, 1}, + .SMSTOP = { 2296, 1}, + .RDSVL = { 2297, 1}, + .ADDHA = { 2298, 1}, + .ADDVA = { 2299, 1}, + .ZERO = { 2300, 1}, + .FMOPA = { 2301, 1}, + .FMOPS = { 2302, 1}, + .BFMOPA = { 2303, 1}, + .BFMOPS = { 2304, 1}, + .SMOPA = { 2305, 2}, + .SMOPS = { 2307, 2}, + .UMOPA = { 2309, 2}, + .UMOPS = { 2311, 2}, + .USMOPA = { 2313, 1}, + .SUMOPA = { 2314, 1}, + .CNTB = { 2315, 1}, + .CNTH = { 2316, 1}, + .CNTW = { 2317, 1}, + .CNTD = { 2318, 1}, + .INCB = { 2319, 1}, + .INCH = { 2320, 2}, + .INCW = { 2322, 2}, + .INCD = { 2324, 2}, + .DECB = { 2326, 1}, + .DECH = { 2327, 2}, + .DECW = { 2329, 2}, + .DECD = { 2331, 2}, + .SQINCB = { 2333, 2}, + .SQINCH = { 2335, 3}, + .SQINCW = { 2338, 3}, + .SQINCD = { 2341, 3}, + .SQDECB = { 2344, 2}, + .SQDECH = { 2346, 3}, + .SQDECW = { 2349, 3}, + .SQDECD = { 2352, 3}, + .UQINCB = { 2355, 2}, + .UQINCH = { 2357, 3}, + .UQINCW = { 2360, 3}, + .UQINCD = { 2363, 3}, + .UQDECB = { 2366, 2}, + .UQDECH = { 2368, 3}, + .UQDECW = { 2371, 3}, + .UQDECD = { 2374, 3}, + .CNTP = { 2377, 4}, + .INCP = { 2381, 7}, + .DECP = { 2388, 7}, + .SQINCP = { 2395, 11}, + .SQDECP = { 2406, 11}, + .UQINCP = { 2417, 11}, + .UQDECP = { 2428, 11}, + .LD1Q = { 2439, 1}, + .ST1Q = { 2440, 1}, + .MOVA = { 2441, 2}, + .FCMLA = { 2443, 4}, + .FCADD = { 2447, 4}, + .PRFB = { 2451, 1}, + .PRFH = { 2452, 1}, + .PRFW = { 2453, 1}, + .PRFD = { 2454, 1}, + .LDNT1B = { 2455, 1}, + .LDNT1H = { 2456, 1}, + .LDNT1W = { 2457, 1}, + .LDNT1D = { 2458, 1}, + .STNT1B = { 2459, 1}, + .STNT1H = { 2460, 1}, + .STNT1W = { 2461, 1}, + .STNT1D = { 2462, 1}, + .SPLICE = { 2463, 1}, + .INDEX = { 2464, 16}, + .BSL1N = { 2480, 1}, + .BSL2N = { 2481, 1}, + .NBSL = { 2482, 1}, + .PMUL = { 2483, 1}, + .PMULLB = { 2484, 1}, + .PMULLT = { 2485, 1}, + .BFCVTNT = { 2486, 1}, + .LDRAA = { 2487, 2}, + .LDRAB = { 2489, 2}, + .TSTART = { 2491, 1}, + .TCOMMIT = { 2492, 1}, + .TCANCEL = { 2493, 1}, + .TTEST = { 2494, 1}, + .WFET = { 2495, 1}, + .WFIT = { 2496, 1}, + .BC_EQ = { 2497, 1}, + .BC_NE = { 2498, 1}, + .BC_CS = { 2499, 1}, + .BC_CC = { 2500, 1}, + .BC_MI = { 2501, 1}, + .BC_PL = { 2502, 1}, + .BC_VS = { 2503, 1}, + .BC_VC = { 2504, 1}, + .BC_HI = { 2505, 1}, + .BC_LS = { 2506, 1}, + .BC_GE = { 2507, 1}, + .BC_LT = { 2508, 1}, + .BC_GT = { 2509, 1}, + .BC_LE = { 2510, 1}, + .BC_AL = { 2511, 1}, + .BC_NV = { 2512, 1}, + .UXTB = { 2513, 1}, + .UXTH = { 2514, 1}, + .UXTW = { 2515, 1}, + .SXTB = { 2516, 1}, + .SXTH = { 2517, 1}, + .SXTW = { 2518, 1}, + .ADC = { 2519, 2}, + .ADCS = { 2521, 2}, + .SBC = { 2523, 2}, + .SBCS = { 2525, 2}, + .NGC = { 2527, 2}, + .NGCS = { 2529, 2}, + .LDAPUR = { 2531, 2}, + .STLUR = { 2533, 2}, + .LDAPURB = { 2535, 1}, + .STLURB = { 2536, 1}, + .LDAPURH = { 2537, 1}, + .STLURH = { 2538, 1}, + .LDAPURSB = { 2539, 2}, + .LDAPURSH = { 2541, 2}, + .LDAPURSW = { 2543, 1}, + .BFADD = { 2544, 2}, + .BFSUB = { 2546, 2}, + .BFMUL = { 2548, 2}, + .BFMLA = { 2550, 1}, + .BFMLS = { 2551, 1}, + .SB = { 2552, 1}, + .CSDB = { 2553, 1}, + .DGH = { 2554, 1}, + .PSB_CSYNC = { 2555, 1}, + .TSB_CSYNC = { 2556, 1}, + .BTI_J = { 2557, 1}, + .BTI_C = { 2558, 1}, + .BTI_JC = { 2559, 1}, + .BFCLAMP = { 2560, 1}, + .BFMAXNM = { 2561, 1}, + .BFMINNM = { 2562, 1}, + .LUTI2 = { 2563, 3}, + .LUTI4 = { 2566, 3}, + .ZIP = { 2569, 2}, + .UZP = { 2571, 2}, + .TLBI_RPALOS = { 2573, 1}, + .TLBI_RPAOS = { 2574, 1}, + .AT_S1E1A = { 2575, 1}, + .DC_CIPAPA = { 2576, 1}, + .DC_CIGDPAPA = { 2577, 1}, + .TLBI_PAALL = { 2578, 1}, + .TLBI_PAALLOS = { 2579, 1}, + .AMX_LDX = { 2580, 1}, + .AMX_LDY = { 2581, 1}, + .AMX_STX = { 2582, 1}, + .AMX_STY = { 2583, 1}, + .AMX_LDZ = { 2584, 1}, + .AMX_STZ = { 2585, 1}, + .AMX_LDZI = { 2586, 1}, + .AMX_STZI = { 2587, 1}, + .AMX_EXTRX = { 2588, 1}, + .AMX_EXTRY = { 2589, 1}, + .AMX_FMA64 = { 2590, 1}, + .AMX_FMS64 = { 2591, 1}, + .AMX_FMA32 = { 2592, 1}, + .AMX_FMS32 = { 2593, 1}, + .AMX_MAC16 = { 2594, 1}, + .AMX_FMA16 = { 2595, 1}, + .AMX_FMS16 = { 2596, 1}, + .AMX_SET = { 2597, 1}, + .AMX_CLR = { 2598, 1}, + .AMX_VECINT = { 2599, 1}, + .AMX_VECFP = { 2600, 1}, + .AMX_MATINT = { 2601, 1}, + .AMX_MATFP = { 2602, 1}, + .AMX_GENLUT = { 2603, 1}, + .CPYP = { 2604, 1}, + .CPYM = { 2605, 1}, + .CPYE = { 2606, 1}, + .CPYFP = { 2607, 1}, + .CPYFM = { 2608, 1}, + .CPYFE = { 2609, 1}, + .SETP = { 2610, 1}, + .SETM = { 2611, 1}, + .SETE = { 2612, 1}, + .DC_IVAC = { 2613, 1}, + .DC_ISW = { 2614, 1}, + .DC_CSW = { 2615, 1}, + .DC_CISW = { 2616, 1}, + .DC_ZVA = { 2617, 1}, + .DC_CVAC = { 2618, 1}, + .DC_CVAU = { 2619, 1}, + .DC_CIVAC = { 2620, 1}, + .IC_IALLUIS = { 2621, 1}, + .IC_IALLU = { 2622, 1}, + .IC_IVAU = { 2623, 1}, + .AT_S1E1R = { 2624, 1}, + .AT_S1E1W = { 2625, 1}, + .AT_S1E0R = { 2626, 1}, + .AT_S1E0W = { 2627, 1}, + .AT_S1E2R = { 2628, 1}, + .AT_S1E2W = { 2629, 1}, + .AT_S1E3R = { 2630, 1}, + .AT_S1E3W = { 2631, 1}, + .AT_S12E1R = { 2632, 1}, + .AT_S12E1W = { 2633, 1}, + .AT_S12E0R = { 2634, 1}, + .AT_S12E0W = { 2635, 1}, + .TLBI_VMALLE1 = { 2636, 1}, + .TLBI_VMALLE1IS = { 2637, 1}, + .TLBI_VAE1 = { 2638, 1}, + .TLBI_VAE1IS = { 2639, 1}, + .TLBI_ASIDE1 = { 2640, 1}, + .TLBI_ASIDE1IS = { 2641, 1}, + .TLBI_VAAE1 = { 2642, 1}, + .TLBI_VAAE1IS = { 2643, 1}, + .TLBI_VALE1 = { 2644, 1}, + .TLBI_VALE1IS = { 2645, 1}, + .TLBI_VAALE1 = { 2646, 1}, + .TLBI_VAALE1IS = { 2647, 1}, + .TLBI_ALLE1 = { 2648, 1}, + .TLBI_ALLE1IS = { 2649, 1}, + .TLBI_ALLE2 = { 2650, 1}, + .TLBI_ALLE2IS = { 2651, 1}, + .TLBI_ALLE3 = { 2652, 1}, + .TLBI_ALLE3IS = { 2653, 1}, + .PRFM = { 2654, 2}, + .PRFUM = { 2656, 1}, + .NEGS = { 2657, 2}, + .CMP = { 2659, 6}, + .CMN = { 2665, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 2bf59540f..1f4df147d 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -191,14 +191,14 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ANDS = { {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -210,7 +210,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EOR = { {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -222,7 +222,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BIC = { {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -232,18 +232,18 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BICS = { {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EON = { {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -372,7 +372,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, }, .REV16 = { {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, @@ -553,8 +553,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { @@ -571,8 +571,8 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_B, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { @@ -704,7 +704,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .MSR = { {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, @@ -1680,19 +1680,19 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .AESE = { {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESD = { {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESMC = { {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .AESIMC = { {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .SHA1H = { {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, @@ -3035,7 +3035,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MOV, {.P_REG_S, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, @@ -3045,7 +3045,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .IMM_8}, {.VD, .VD, .VM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBL = { {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3072,7 +3072,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .ZIP2 = { {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3086,7 +3086,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP1 = { {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3100,7 +3100,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP2 = { {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3114,7 +3114,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN1 = { {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3128,7 +3128,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN2 = { {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3142,12 +3142,12 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .NOT = { {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .REV64 = { {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, @@ -3312,31 +3312,31 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_S, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG_B, .P_REG, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_H, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_D, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, @@ -3348,37 +3348,37 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_H, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_S, .P_REG_MERGE, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_H, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_D, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG, .P_REG}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RDFFR = { {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, }, .SETFFR = { {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, @@ -3471,77 +3471,78 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .LD1B = { {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4C08000, 0xFFE0A000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3559,28 +3560,52 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, @@ -3875,10 +3900,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3936,10 +3961,22 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5, .RN, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BSL1N = { {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, 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literal 64 zcmZQz2xI_(K!!3V5Ph7!0Ktg&F2>ZeRca9gYf_ From 266e436c0c2a24bbb0e703186c6a05ffcc144d91 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 19:19:53 -0400 Subject: [PATCH 50/89] rexcode/arm64: the SVE element-count family, and INCP's predicate field The merge brought in the SQINCP/UQINCP/INCP/DECP family reading its predicate from bits 20:16, where the architecture has it at 8:5, so every one of them encoded a different register than it named. Their predicate also carries an element size -- from the form's Z operand where it has one, and from bits 23:22 for the scalar destinations. SVE writes an element count as a pattern by name and a multiplier as `mul #N`: `cntb x0, pow2, mul #1`. The pattern printed as a bare number and the multiplier did not print at all -- IMM_MUL4 had an encoder but no decoder, so it came back as an empty operand and left a trailing comma. That covers 64 and 62 forms respectively. CNTP's source predicate, and eight more the merge added, wanted the same element sizes as the rest of that family. SVE/SME2 against llvm-mc: 663 byte-exact and 0 mismatched, from 450 and 18 when the merge landed. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 5 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 194 +++++++++++------- core/rexcode/isa/arm64/operands.odin | 15 ++ core/rexcode/isa/arm64/printer.odin | 25 +++ .../tablegen/generated/decode_tables.odin | 132 ++++++------ .../tablegen/generated/encode_tables.odin | 132 ++++++------ .../isa/arm64/tablegen/instruction_table.odin | 132 ++++++------ .../isa/arm64/tables/arm64.encode_forms.bin | Bin 53420 -> 53420 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 53460 -> 53460 bytes 9 files changed, 360 insertions(+), 275 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index bb4b935d8..7eeed8420 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -530,7 +530,10 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .SVE_SHIFT_TSZ_IMM: return Operand{immediate = i64((word >> 16) & 0x7F), kind = .IMMEDIATE, size = 1} case .SVE_PATTERN: - return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = SVE_PATTERN_IMM} + case .IMM_MUL4: + // The field holds the multiplier minus one. + return Operand{immediate = i64(((word >> 16) & 0xF) + 1), kind = .IMMEDIATE, size = SVE_MUL_IMM} // ---- SVE memory operands ---- case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3, diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 4e7e5da6e..8373ea484 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -434,20 +434,20 @@ emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Inst inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } -emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } +emit_ldr_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_ps_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } -emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } +emit_str_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_ps_m(rz, mem)) } emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } @@ -3565,10 +3565,10 @@ inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } -inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } +inst_pfirst_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_pb_pb(rz, rz2, rz3)) } +inst_pnext_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_pb_pb(rz, rz2, rz3)) } inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } @@ -4049,56 +4049,98 @@ inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_uqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_r_i_i(dst, imm, imm2)) } emit_uqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_zd_i_i(rz, imm, imm2)) } -inst_cntp_r_p_p :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -emit_cntp_r_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_p(dst, rz1, rz2)) } -inst_incp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_incp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_p(dst, rz1)) } -emit_incp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_p(rz, rz2)) } -emit_incp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_p(rz, rz2)) } -emit_incp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_p(rz, rz2)) } -inst_decp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_decp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_p(dst, rz1)) } -emit_decp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_p(rz, rz2)) } -emit_decp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_p(rz, rz2)) } -emit_decp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_p(rz, rz2)) } -inst_sqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_p(dst, rz1)) } -emit_sqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_p(rz, rz2)) } -emit_sqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_p(rz, rz2)) } -emit_sqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_p(rz, rz2)) } -inst_sqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_p(dst, rz1)) } -emit_sqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_p(rz, rz2)) } -emit_sqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_p(rz, rz2)) } -emit_sqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_p(rz, rz2)) } -inst_uqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_uqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_p(dst, rz1)) } -emit_uqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_p(rz, rz2)) } -emit_uqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_p(rz, rz2)) } -emit_uqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_p(rz, rz2)) } -inst_uqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_uqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_p(dst, rz1)) } -emit_uqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_p(rz, rz2)) } -emit_uqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_p(rz, rz2)) } -emit_uqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_p(rz, rz2)) } +inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +emit_cntp_r_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pb(dst, rz1, rz2)) } +emit_cntp_r_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ph(dst, rz1, rz2)) } +emit_cntp_r_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ps(dst, rz1, rz2)) } +emit_cntp_r_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pd(dst, rz1, rz2)) } +inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_incp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pb(dst, rz1)) } +emit_incp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ph(dst, rz1)) } +emit_incp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ps(dst, rz1)) } +emit_incp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pd(dst, rz1)) } +emit_incp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_ph(rz, rz2)) } +emit_incp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_ps(rz, rz2)) } +emit_incp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_pd(rz, rz2)) } +inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_decp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pb(dst, rz1)) } +emit_decp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ph(dst, rz1)) } +emit_decp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ps(dst, rz1)) } +emit_decp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pd(dst, rz1)) } +emit_decp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_ph(rz, rz2)) } +emit_decp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_ps(rz, rz2)) } +emit_decp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_pd(rz, rz2)) } +inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pb(dst, rz1)) } +emit_sqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ph(dst, rz1)) } +emit_sqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ps(dst, rz1)) } +emit_sqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pd(dst, rz1)) } +emit_sqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_ph(rz, rz2)) } +emit_sqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_ps(rz, rz2)) } +emit_sqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_pd(rz, rz2)) } +inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pb(dst, rz1)) } +emit_sqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ph(dst, rz1)) } +emit_sqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ps(dst, rz1)) } +emit_sqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pd(dst, rz1)) } +emit_sqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_ph(rz, rz2)) } +emit_sqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_ps(rz, rz2)) } +emit_sqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_pd(rz, rz2)) } +inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pb(dst, rz1)) } +emit_uqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ph(dst, rz1)) } +emit_uqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ps(dst, rz1)) } +emit_uqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pd(dst, rz1)) } +emit_uqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_ph(rz, rz2)) } +emit_uqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_ps(rz, rz2)) } +emit_uqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_pd(rz, rz2)) } +inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pb(dst, rz1)) } +emit_uqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ph(dst, rz1)) } +emit_uqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ps(dst, rz1)) } +emit_uqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pd(dst, rz1)) } +emit_uqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_ph(rz, rz2)) } +emit_uqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_ps(rz, rz2)) } +emit_uqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_pd(rz, rz2)) } inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } @@ -5662,10 +5704,10 @@ inst_ptrues :: inst_ptrues_pb_i emit_ptrues :: emit_ptrues_pb_i inst_pfalse :: inst_pfalse_pb emit_pfalse :: emit_pfalse_pb -inst_pfirst :: inst_pfirst_pb_p_pb -emit_pfirst :: emit_pfirst_pb_p_pb -inst_pnext :: inst_pnext_pb_p_pb -emit_pnext :: emit_pnext_pb_p_pb +inst_pfirst :: inst_pfirst_pb_pb_pb +emit_pfirst :: emit_pfirst_pb_pb_pb +inst_pnext :: inst_pnext_pb_pb_pb +emit_pnext :: emit_pnext_pb_pb_pb inst_brka :: inst_brka_pb_p_pb emit_brka :: emit_brka_pb_p_pb inst_brkb :: inst_brkb_pb_p_pb @@ -5872,20 +5914,20 @@ inst_uqdecw :: proc{ inst_uqdecw_r_i_i, inst_uqdecw_zs_i_ emit_uqdecw :: proc{ emit_uqdecw_r_i_i, emit_uqdecw_zs_i_i } inst_uqdecd :: proc{ inst_uqdecd_r_i_i, inst_uqdecd_zd_i_i } emit_uqdecd :: proc{ emit_uqdecd_r_i_i, emit_uqdecd_zd_i_i } -inst_cntp :: inst_cntp_r_p_p -emit_cntp :: emit_cntp_r_p_p -inst_incp :: proc{ inst_incp_r_p, inst_incp_zh_p } -emit_incp :: proc{ emit_incp_r_p, emit_incp_zh_p } -inst_decp :: proc{ inst_decp_r_p, inst_decp_zh_p } -emit_decp :: proc{ emit_decp_r_p, emit_decp_zh_p } -inst_sqincp :: proc{ inst_sqincp_r_p, inst_sqincp_zh_p } -emit_sqincp :: proc{ emit_sqincp_r_p, emit_sqincp_zh_p } -inst_sqdecp :: proc{ inst_sqdecp_r_p, inst_sqdecp_zh_p } -emit_sqdecp :: proc{ emit_sqdecp_r_p, emit_sqdecp_zh_p } -inst_uqincp :: proc{ inst_uqincp_r_p, inst_uqincp_zh_p } -emit_uqincp :: proc{ emit_uqincp_r_p, emit_uqincp_zh_p } -inst_uqdecp :: proc{ inst_uqdecp_r_p, inst_uqdecp_zh_p } -emit_uqdecp :: proc{ emit_uqdecp_r_p, emit_uqdecp_zh_p } +inst_cntp :: inst_cntp_r_p_pb +emit_cntp :: emit_cntp_r_p_pb +inst_incp :: proc{ inst_incp_r_pb, inst_incp_zh_ph } +emit_incp :: proc{ emit_incp_r_pb, emit_incp_zh_ph } +inst_decp :: proc{ inst_decp_r_pb, inst_decp_zh_ph } +emit_decp :: proc{ emit_decp_r_pb, emit_decp_zh_ph } +inst_sqincp :: proc{ inst_sqincp_r_pb, inst_sqincp_zh_ph } +emit_sqincp :: proc{ emit_sqincp_r_pb, emit_sqincp_zh_ph } +inst_sqdecp :: proc{ inst_sqdecp_r_pb, inst_sqdecp_zh_ph } +emit_sqdecp :: proc{ emit_sqdecp_r_pb, emit_sqdecp_zh_ph } +inst_uqincp :: proc{ inst_uqincp_r_pb, inst_uqincp_zh_ph } +emit_uqincp :: proc{ emit_uqincp_r_pb, emit_uqincp_zh_ph } +inst_uqdecp :: proc{ inst_uqdecp_r_pb, inst_uqdecp_zh_ph } +emit_uqdecp :: proc{ emit_uqdecp_r_pb, emit_uqdecp_zh_ph } inst_ld1q :: inst_ld1q_i_p_m emit_ld1q :: emit_ld1q_i_p_m inst_st1q :: inst_st1q_i_p_m diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 933ad36ba..dc38c0db3 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -176,6 +176,21 @@ op_cond :: #force_inline proc "contextless" (c: Cond) -> Operand { // one -- EXT's byte index, for instance, is written `#3`. LANE_INDEX :: u8(0xFF) +// SVE writes its element-count pattern by name (`vl8`, `mul3`, `all`) and its +// multiplier as `mul #N`, so both need telling apart from a plain immediate. +SVE_PATTERN_IMM :: u8(0xFE) +SVE_MUL_IMM :: u8(0xFD) + +// The 32 SVE element-count patterns; the gaps are reserved and print as a +// bare number. +@(rodata) +SVE_PATTERN_NAMES := [32]string{ + "pow2", "vl1", "vl2", "vl3", "vl4", "vl5", "vl6", "vl7", + "vl8", "vl16", "vl32", "vl64", "vl128", "vl256", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "mul4", "mul3", "all", +} + @(require_results) op_lane_index :: #force_inline proc "contextless" (index: i64) -> Operand { return Operand{immediate = index, kind = .IMMEDIATE, size = LANE_INDEX} diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 9479e461c..cf8f3f21d 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -395,6 +395,18 @@ write_sysreg :: proc(sb: ^strings.Builder, sr: System_Register, uppercase: bool) } } +@(private="file") +write_lowercase :: proc(sb: ^strings.Builder, s: string, uppercase: bool) { + for i in 0 ..< len(s) { + c := s[i] + if uppercase && c >= 'a' && c <= 'z' { + strings.write_byte(sb, c - 'a' + 'A') + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { shape := "" @@ -529,6 +541,19 @@ write_operand :: proc( write_vector_shape(sb, op.reg, op.size, opts.uppercase) case .IMMEDIATE: + // An SVE element-count pattern has a name, and its multiplier is + // written `mul #N` rather than as a bare immediate. + if op.size == SVE_PATTERN_IMM { + name := SVE_PATTERN_NAMES[op.immediate & 0x1F] + if name != "" { + write_lowercase(sb, name, opts.uppercase) + return + } + } else if op.size == SVE_MUL_IMM { + strings.write_string(sb, opts.uppercase ? "MUL #" : "mul #") + write_signed_decimal(sb, op.immediate) + return + } strings.write_byte(sb, '#') write_signed_decimal(sb, op.immediate) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 0880cc546..4e2e00cb2 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -97,68 +97,68 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -174,10 +174,10 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, @@ -614,8 +614,8 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index aedfd2e53..5d5f20924 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -385,7 +385,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -402,7 +402,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2687,9 +2687,9 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB @@ -3058,74 +3058,74 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .CNTP - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, // .INCP - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .DECP - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQINCP - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQDECP - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQINCP - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQDECP - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .LD1Q { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 1f4df147d..5c62a1518 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -554,7 +554,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { @@ -572,7 +572,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { @@ -3348,10 +3348,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3824,80 +3824,80 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .CNTP = { - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .INCP = { - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .DECP = { - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .SQINCP = { - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .SQDECP = { - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQINCP = { - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQDECP = { - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index a507a901bd97f6fd8531eace6cd6dc0bb5e79414..caae9aa829c6c4744ba12e24fa1de3f93acbbe24 100644 GIT binary patch delta 1275 zcmYk6yGjE=7=OaZ(=WG@DX3n?gY(hG%a;H_kKbkBxyT_9&CHZ)nn)4G`W>)K~#yoFSM}GhQ zh8xRCmUV~P599NhN!IG7l2@vgcR4vcO_JG7uttG3Pu?EK>=sU5aneeX%$THZjB$%q z6Wr^HGHZ9p&@a4#+tz<^BeP(ln1y&?HxQK9iRw%Osp|DuyfGn1| zBa3BzB4e3B)(*=T~b~ zrasrR1ED~!W0>n0=DHrTmxXl;C@3s`b$eu5#@~Wjxu|XYSG>q|5T=)fbr1%oLI+`B Z>T~c3<2Yvf<0krl3=9v}b@Qji(SIeWgxdfB delta 1275 zcmZwHy-or_6b0a6uq81n!Af@%NdU38b8FDV(vnd5oA?H^m0HmG0b_+ zp;qG0D~K2N?A$xaR3zVW4)+kkAjuDs{KH8p7Yrg4Zsgydam(`?u zTiT(=1|IvdwnTlkNnea?l<4KmOpGvLkYS8)bSaKmL!q=IkKKFh*BT#_W=(-U#9k94 zOvc9`99{7-oeB!2?RxCmW1rS?p)&ZYQAi&`2t%P`D0B>kWW0{EJdU$G&Sc@PSXaY^ z()K-e>#;9uJOq7FSByiSaS(-$p^%K%Axy^WILqs@Y)_1<;=t6*^q1b*b1=0VkBzMH zIuu4du?~HXq0h0ANec;i9fx@xhk4xy*}hn}iUXw`c38+jcHqrO;&LdQ_( Y82ZR~9A~HFiqk&^4yWse@pFCdA4NBF=>Px# diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index b490723b1f01421f59b1abe6ba1d5e6dbdae2de6..2993fafae59c07ff9c7760c16af067e507f094a7 100644 GIT binary patch delta 1275 zcmYk6yGjE=6oyYmu#p8tY&D7jjf$}HX_)_W(BWcYqi@5Q%vUzxZdyzLSDd! z$O8mzy!KYcGv=K6(|*hU&Hpd6+ba56Mc>nF|45QhtzIK~-lz=zb~@44f=QCopZ>)x zAu@F$va=QPPgV$M@IPrO=KHK$Wk%ua@B4mbj2xDD0?6X*>*(4eNmoyvK+Qhwpz(9xMOlMP{8 nJuE#PiiS(u%}O*rF_Nwk)zA+K+wkD-pV+ey)$d(V<&oEFAu;rXpt=546eYXC0?Vd-x=^;=u4%{#xv zZNULp0|2hqL&!d9ri^JjbJ);f-`W;swwm?Dn2l1lqz$vu0yF_JhND~K!5dg;+PTA? z9QLD)j=`*a1|2iYim5MAT>~+OqdPh#S;a!rjvRLHuy<{qeyi9gpW$(#UOyJjP#G3l zhK15-9c5`9Woewsc4?eQs(7J+$%(@T4*S$b>##5C%5`c8_F0zq3Ex62lt$|)OzZM+ zmZfzn+oN?!1rIds*ff!U`;!L~(LS`%5-f~*#yTvt4Erp@K4~;gP?*+HnAWLq-&nVX z2by;3ut$e| Date: Fri, 28 Aug 2026 19:22:36 -0400 Subject: [PATCH 51/89] rexcode/arm64: the signed saturating forms name their register twice `sqincb x0, w0, pow2, mul #1` writes one register under both names: the 64-bit destination and the 32-bit value it saturates into. Sixteen forms had only the W half, so they printed `sqincb w0, ...`, which no assembler takes. The unsigned ones really do take a single W and were already right. SVE LDR/STR and PFIRST/PNEXT lost their unsized operands again when the predicate sizing was re-run over the merged rows; a predicate that is moved whole, or that governs, carries no element size. SVE/SME2 against llvm-mc: 683 byte-exact and 0 mismatched. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/mnemonic_builders.odin | 96 ++++++++++++------ .../tablegen/generated/decode_tables.odin | 40 ++++---- .../tablegen/generated/encode_tables.odin | 40 ++++---- .../isa/arm64/tablegen/instruction_table.odin | 40 ++++---- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 53420 -> 53420 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 53460 -> 53460 bytes 6 files changed, 124 insertions(+), 92 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 8373ea484..b38fa7d59 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -434,20 +434,20 @@ emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Inst inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_ldr_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } -emit_ldr_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_ps_m(rz, mem)) } +emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_str_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } -emit_str_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_ps_m(rz, mem)) } +emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } @@ -3565,10 +3565,10 @@ inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_pb_pb(rz, rz2, rz3)) } -inst_pnext_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_pb_pb(rz, rz2, rz3)) } +inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } +inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } @@ -3994,32 +3994,48 @@ inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: emit_decd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decd_r_i_i(dst, imm, imm2)) } emit_decd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decd_zd_i_i(rz, imm, imm2)) } inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } emit_sqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_i_i(dst, imm, imm2)) } +emit_sqincb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_r_i_i(dst, src, imm, imm2)) } inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_i_i(dst, imm, imm2)) } +emit_sqinch_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_r_i_i(dst, src, imm, imm2)) } emit_sqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqinch_zh_i_i(rz, imm, imm2)) } inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_i_i(dst, imm, imm2)) } +emit_sqincw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_r_i_i(dst, src, imm, imm2)) } emit_sqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincw_zs_i_i(rz, imm, imm2)) } inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_i_i(dst, imm, imm2)) } +emit_sqincd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_r_i_i(dst, src, imm, imm2)) } emit_sqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincd_zd_i_i(rz, imm, imm2)) } inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } emit_sqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_i_i(dst, imm, imm2)) } +emit_sqdecb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_r_i_i(dst, src, imm, imm2)) } inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_i_i(dst, imm, imm2)) } +emit_sqdech_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_r_i_i(dst, src, imm, imm2)) } emit_sqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdech_zh_i_i(rz, imm, imm2)) } inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_i_i(dst, imm, imm2)) } +emit_sqdecw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_zs_i_i(rz, imm, imm2)) } inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_i_i(dst, imm, imm2)) } +emit_sqdecd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_zd_i_i(rz, imm, imm2)) } inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_uqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincb_r_i_i(dst, imm, imm2)) } @@ -4089,6 +4105,10 @@ inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqincp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqincp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqincp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } @@ -4096,6 +4116,10 @@ emit_sqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ph(dst, rz1)) } emit_sqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ps(dst, rz1)) } emit_sqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pd(dst, rz1)) } +emit_sqincp_r_pb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqincp_r_pb_r(dst, rz1, src)) } +emit_sqincp_r_ph_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqincp_r_ph_r(dst, rz1, src)) } +emit_sqincp_r_ps_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqincp_r_ps_r(dst, rz1, src)) } +emit_sqincp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqincp_r_pd_r(dst, rz1, src)) } emit_sqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_ph(rz, rz2)) } emit_sqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_ps(rz, rz2)) } emit_sqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_pd(rz, rz2)) } @@ -4103,6 +4127,10 @@ inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqdecp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqdecp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } +inst_sqdecp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } @@ -4110,6 +4138,10 @@ emit_sqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ph(dst, rz1)) } emit_sqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ps(dst, rz1)) } emit_sqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pd(dst, rz1)) } +emit_sqdecp_r_pb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqdecp_r_pb_r(dst, rz1, src)) } +emit_sqdecp_r_ph_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqdecp_r_ph_r(dst, rz1, src)) } +emit_sqdecp_r_ps_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqdecp_r_ps_r(dst, rz1, src)) } +emit_sqdecp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, src: Register) { append(instructions, inst_sqdecp_r_pd_r(dst, rz1, src)) } emit_sqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_ph(rz, rz2)) } emit_sqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_ps(rz, rz2)) } emit_sqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_pd(rz, rz2)) } @@ -5704,10 +5736,10 @@ inst_ptrues :: inst_ptrues_pb_i emit_ptrues :: emit_ptrues_pb_i inst_pfalse :: inst_pfalse_pb emit_pfalse :: emit_pfalse_pb -inst_pfirst :: inst_pfirst_pb_pb_pb -emit_pfirst :: emit_pfirst_pb_pb_pb -inst_pnext :: inst_pnext_pb_pb_pb -emit_pnext :: emit_pnext_pb_pb_pb +inst_pfirst :: inst_pfirst_pb_p_pb +emit_pfirst :: emit_pfirst_pb_p_pb +inst_pnext :: inst_pnext_pb_p_pb +emit_pnext :: emit_pnext_pb_p_pb inst_brka :: inst_brka_pb_p_pb emit_brka :: emit_brka_pb_p_pb inst_brkb :: inst_brkb_pb_p_pb @@ -5882,22 +5914,22 @@ inst_decw :: proc{ inst_decw_r_i_i, inst_decw_zs_i_i } emit_decw :: proc{ emit_decw_r_i_i, emit_decw_zs_i_i } inst_decd :: proc{ inst_decd_r_i_i, inst_decd_zd_i_i } emit_decd :: proc{ emit_decd_r_i_i, emit_decd_zd_i_i } -inst_sqincb :: inst_sqincb_r_i_i -emit_sqincb :: emit_sqincb_r_i_i -inst_sqinch :: proc{ inst_sqinch_r_i_i, inst_sqinch_zh_i_i } -emit_sqinch :: proc{ emit_sqinch_r_i_i, emit_sqinch_zh_i_i } -inst_sqincw :: proc{ inst_sqincw_r_i_i, inst_sqincw_zs_i_i } -emit_sqincw :: proc{ emit_sqincw_r_i_i, emit_sqincw_zs_i_i } -inst_sqincd :: proc{ inst_sqincd_r_i_i, inst_sqincd_zd_i_i } -emit_sqincd :: proc{ emit_sqincd_r_i_i, emit_sqincd_zd_i_i } -inst_sqdecb :: inst_sqdecb_r_i_i -emit_sqdecb :: emit_sqdecb_r_i_i -inst_sqdech :: proc{ inst_sqdech_r_i_i, inst_sqdech_zh_i_i } -emit_sqdech :: proc{ emit_sqdech_r_i_i, emit_sqdech_zh_i_i } -inst_sqdecw :: proc{ inst_sqdecw_r_i_i, inst_sqdecw_zs_i_i } -emit_sqdecw :: proc{ emit_sqdecw_r_i_i, emit_sqdecw_zs_i_i } -inst_sqdecd :: proc{ inst_sqdecd_r_i_i, inst_sqdecd_zd_i_i } -emit_sqdecd :: proc{ emit_sqdecd_r_i_i, emit_sqdecd_zd_i_i } +inst_sqincb :: proc{ inst_sqincb_r_i_i, inst_sqincb_r_r_i_i } +emit_sqincb :: proc{ emit_sqincb_r_i_i, emit_sqincb_r_r_i_i } +inst_sqinch :: proc{ inst_sqinch_r_i_i, inst_sqinch_r_r_i_i, inst_sqinch_zh_i_i } +emit_sqinch :: proc{ emit_sqinch_r_i_i, emit_sqinch_r_r_i_i, emit_sqinch_zh_i_i } +inst_sqincw :: proc{ inst_sqincw_r_i_i, inst_sqincw_r_r_i_i, inst_sqincw_zs_i_i } +emit_sqincw :: proc{ emit_sqincw_r_i_i, emit_sqincw_r_r_i_i, emit_sqincw_zs_i_i } +inst_sqincd :: proc{ inst_sqincd_r_i_i, inst_sqincd_r_r_i_i, inst_sqincd_zd_i_i } +emit_sqincd :: proc{ emit_sqincd_r_i_i, emit_sqincd_r_r_i_i, emit_sqincd_zd_i_i } +inst_sqdecb :: proc{ inst_sqdecb_r_i_i, inst_sqdecb_r_r_i_i } +emit_sqdecb :: proc{ emit_sqdecb_r_i_i, emit_sqdecb_r_r_i_i } +inst_sqdech :: proc{ inst_sqdech_r_i_i, inst_sqdech_r_r_i_i, inst_sqdech_zh_i_i } +emit_sqdech :: proc{ emit_sqdech_r_i_i, emit_sqdech_r_r_i_i, emit_sqdech_zh_i_i } +inst_sqdecw :: proc{ inst_sqdecw_r_i_i, inst_sqdecw_r_r_i_i, inst_sqdecw_zs_i_i } +emit_sqdecw :: proc{ emit_sqdecw_r_i_i, emit_sqdecw_r_r_i_i, emit_sqdecw_zs_i_i } +inst_sqdecd :: proc{ inst_sqdecd_r_i_i, inst_sqdecd_r_r_i_i, inst_sqdecd_zd_i_i } +emit_sqdecd :: proc{ emit_sqdecd_r_i_i, emit_sqdecd_r_r_i_i, emit_sqdecd_zd_i_i } inst_uqincb :: inst_uqincb_r_i_i emit_uqincb :: emit_uqincb_r_i_i inst_uqinch :: proc{ inst_uqinch_r_i_i, inst_uqinch_zh_i_i } @@ -5920,10 +5952,10 @@ inst_incp :: proc{ inst_incp_r_pb, inst_incp_zh_ph } emit_incp :: proc{ emit_incp_r_pb, emit_incp_zh_ph } inst_decp :: proc{ inst_decp_r_pb, inst_decp_zh_ph } emit_decp :: proc{ emit_decp_r_pb, emit_decp_zh_ph } -inst_sqincp :: proc{ inst_sqincp_r_pb, inst_sqincp_zh_ph } -emit_sqincp :: proc{ emit_sqincp_r_pb, emit_sqincp_zh_ph } -inst_sqdecp :: proc{ inst_sqdecp_r_pb, inst_sqdecp_zh_ph } -emit_sqdecp :: proc{ emit_sqdecp_r_pb, emit_sqdecp_zh_ph } +inst_sqincp :: proc{ inst_sqincp_r_pb, inst_sqincp_r_pb_r, inst_sqincp_zh_ph } +emit_sqincp :: proc{ emit_sqincp_r_pb, emit_sqincp_r_pb_r, emit_sqincp_zh_ph } +inst_sqdecp :: proc{ inst_sqdecp_r_pb, inst_sqdecp_r_pb_r, inst_sqdecp_zh_ph } +emit_sqdecp :: proc{ emit_sqdecp_r_pb, emit_sqdecp_r_pb_r, emit_sqdecp_zh_ph } inst_uqincp :: proc{ inst_uqincp_r_pb, inst_uqincp_zh_ph } emit_uqincp :: proc{ emit_uqincp_r_pb, emit_uqincp_zh_ph } inst_uqdecp :: proc{ inst_uqdecp_r_pb, inst_uqdecp_zh_ph } diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 4e2e00cb2..cc2ec5558 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -97,8 +97,8 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, @@ -119,10 +119,10 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, @@ -130,10 +130,10 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, @@ -413,26 +413,26 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, @@ -614,8 +614,8 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 5d5f20924..7c4ba00a4 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -385,7 +385,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -402,7 +402,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2687,9 +2687,9 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB @@ -2999,33 +2999,33 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCB { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQINCH { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCW { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCD { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECB { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQDECH { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECW { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECD { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCB { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -3083,10 +3083,10 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, @@ -3095,10 +3095,10 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 5c62a1518..d9ed00761 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -554,7 +554,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { @@ -572,7 +572,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { @@ -3348,10 +3348,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3749,40 +3749,40 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .SQINCB = { {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCH = { {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCW = { {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCD = { {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECB = { {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECH = { {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECW = { {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECD = { {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCB = { @@ -3852,10 +3852,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, @@ -3865,10 +3865,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index caae9aa829c6c4744ba12e24fa1de3f93acbbe24..4f0226e8e2f445ab06cf09af427c82d125c5ad51 100644 GIT binary patch delta 436 zcmZ3pka^8Q<_&G)jEbAv#qAk^)Nu)o9#O?41}|?f28II>ssjK1|L0AxU`kTl%(660 z(29vs+l`4SIE3MY0t>^R5C3@^CNeQ;yD@--7(Nt0#0r37aCHe#b(5!T(-J}mFMtVO zKoNcb6Xw~jg|O@g%(AHn%YMKt1B$^c`vJGCU^|j!Kj4ZXu(ua8F(t#qG7w@ZFtHT~u~eAY3#i!SJ-hpmjMRb(FF`Ug3n2zKauq@h OZsaSd*yb5~L_`3f*N~?G delta 436 zcmZ3pka^8Q<_&G)j47Mj#qAk^)Nu)o9?_&E1}|?f28II>ssjK1|L0AxU`k5b%(660 z(27ypje#jRgn{9M0t>^R4?wwzOiXaG0*F|_L?(o~1gN^nQ?_XdA%qvegfE~7KY$7I zY}Z0q_5)_wRD@+eV3tiqSoQ;MS;2NB%YMKuTZ1ADvuyK=?QP6{j7ba(Ox_F(3>_M( z3?OeiEM{U%hKXe$#8O~lD-dF-FtHa3{2ik3=AC_ zstjPc#Y{}eFtH4TSPD#R1wt$pCiVgj7KT3`{_{3WWMa~GV*m*;d?Jp&pCZCbl5<&~!_9tzA`CNovx1@;pQvIW1A|u>0}wQ{ T3Oso5pVz^ML2+}me&s>{;ed+z delta 432 zcmcbzkon3&<_(Y8M3a&jyu7^_7!E|J3jF*3pEtpRDJg0554J^&evC;B3{2h(3=AC_ zsth1Ghs8{c$uO}DgjfnpYz0Cr6(;rqDmM8AM<0@rT2SF7NJeHM#NbA*LWseQd<7NT ze1!9ys1>8O8v|2t2m`|h1r~-sAAnw%$ixH}D}aa Date: Fri, 28 Aug 2026 19:29:20 -0400 Subject: [PATCH 52/89] rexcode/arm64: an instruction can hold five operands SME's outer products take five -- `smopa za0.s, p0/m, p1/m, z0.b, z1.b` -- and Instruction held four, so the 14 forms in that family could not be represented at all, let alone printed. They named one vector where the instruction multiplies two. Five Operands is 55 bytes, which is odd, so Mnemonic's alignment costs one more; three bytes of padding still land Instruction on exactly one 64-byte cache line, as before. Encoding and Decode_Entry each grow by two. The tile number was wrong as well: it sits in the low bits, as wide as the element size leaves room for -- three for .d down to none for .b -- not at bits 23:22 where the encoding read it. Every MOP form named a tile it was not writing. Note for anyone regenerating: tablegen re-emits tables.odin from a template inside gen.odin, so a struct change there has to go in the template, and the package has to compile before tablegen can run at all. Same for the builders. SVE/SME2 against llvm-mc: 697 byte-exact and 0 mismatched, of 704. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/clobber_types.odin | 2 +- core/rexcode/isa/arm64/decoder.odin | 12 +- core/rexcode/isa/arm64/encoder.odin | 24 +- core/rexcode/isa/arm64/encoding_types.odin | 6 +- core/rexcode/isa/arm64/instructions.odin | 25 +- core/rexcode/isa/arm64/mnemonic_builders.odin | 3832 ++++++------ core/rexcode/isa/arm64/tablegen/gen.odin | 20 +- .../tablegen/generated/decode_tables.odin | 5346 ++++++++--------- .../tablegen/generated/encode_tables.odin | 5342 ++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 5342 ++++++++-------- core/rexcode/isa/arm64/tables.odin | 6 +- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 53420 -> 58762 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 53460 -> 58806 bytes .../isa/arm64/tests/pipeline_smoke.odin | 47 +- .../arm64/tools/gen_mnemonic_builders.odin | 12 +- 15 files changed, 10014 insertions(+), 10002 deletions(-) diff --git a/core/rexcode/isa/arm64/clobber_types.odin b/core/rexcode/isa/arm64/clobber_types.odin index 406094291..e9800c032 100644 --- a/core/rexcode/isa/arm64/clobber_types.odin +++ b/core/rexcode/isa/arm64/clobber_types.odin @@ -1,6 +1,6 @@ package rexcode_arm64 -Operand_Set :: distinct bit_set[0..<4; u8] +Operand_Set :: distinct bit_set[0..<5; u8] NZCV_Flags :: distinct bit_set[NZCV_Flag; u8] NZCV_Flag :: enum u8 { diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 7eeed8420..94c98341b 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -128,6 +128,10 @@ decode_one_inline :: #force_inline proc "contextless" ( if entry.ops[3] != .NONE { inst.ops[3] = extract_operand_inline(word, pc, entry.ops[3], entry.enc[3]) cnt_used = 4 + if entry.ops[4] != .NONE { + inst.ops[4] = extract_operand_inline(word, pc, entry.ops[4], entry.enc[4]) + cnt_used = 5 + } } } } @@ -572,16 +576,16 @@ extract_operand_inline :: #force_inline proc "contextless" ( // ---- SME ZA tile fields ---- case .ZA_TILE_NUM_B: - return Operand{reg = Register(REG_ZA | 0), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x0)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_H: - return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x1)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x1)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_S: - return Operand{reg = Register(REG_ZA | u16((word >> 22) & 0x3)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x3)), kind = .REGISTER, size = za_elem_for_type(ot)} case .ZA_TILE_NUM_D: - return Operand{reg = Register(REG_ZA | u16((word >> 21) & 0x7)), kind = .REGISTER, + return Operand{reg = Register(REG_ZA | u16(word & 0x7)), kind = .REGISTER, size = za_elem_for_type(ot)} case .SME_PATTERN_FIELD: return Operand{immediate = i64((word >> 5) & 0xF), kind = .IMMEDIATE, size = 1} diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 1d445803d..58a5699d3 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -145,6 +145,7 @@ encode_one_inline :: #force_inline proc( if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], form, pc, inst_idx, relocs, inst) } if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], form, pc, inst_idx, relocs, inst) } if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], form, pc, inst_idx, relocs, inst) } + if form.enc[4] != .NONE { word |= pack_operand_inline(&inst.ops[4], form.enc[4], form, pc, inst_idx, relocs, inst) } return word, true } @@ -155,7 +156,8 @@ encoding_matches_inline :: #force_inline proc "contextless" ( return operand_matches_inline(&inst.ops[0], form.ops[0], form) && operand_matches_inline(&inst.ops[1], form.ops[1], form) && operand_matches_inline(&inst.ops[2], form.ops[2], form) && - operand_matches_inline(&inst.ops[3], form.ops[3], form) + operand_matches_inline(&inst.ops[3], form.ops[3], form) && + operand_matches_inline(&inst.ops[4], form.ops[4], form) } @(private="file") @@ -721,17 +723,21 @@ pack_operand_inline :: #force_inline proc( // SME ZA tile number fields (position depends on element size). case .ZA_TILE_NUM_B: - // ZA0.B only -- nothing to encode (single tile of byte form). - return 0 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x0 case .ZA_TILE_NUM_H: - // ZA0.H..ZA1.H -- 1-bit tile number at bit 22. - return (u32(op.immediate) & 0x1) << 22 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x1 case .ZA_TILE_NUM_S: - // ZA0.S..ZA3.S -- 2-bit tile number at bits 23:22. - return (u32(op.immediate) & 0x3) << 22 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x3 case .ZA_TILE_NUM_D: - // ZA0.D..ZA7.D -- 3-bit tile number at bits 23:21. - return (u32(op.immediate) & 0x7) << 21 + // The tile number sits in the low bits, as wide as the element + // size leaves room for. + return u32(reg_hw(op.reg)) & 0x7 case .SME_PATTERN_FIELD: // 4-bit SME pattern/list at bits 8:5 (ZERO instruction list mask). return (u32(op.immediate) & 0xF) << 5 diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index 50f2ec90d..b0f8092e4 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -459,11 +459,11 @@ Operand_Encoding :: enum u8 { Encoding :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 -- static field pattern mask: u32, // 4 -- which bits are static feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Encoding) == 20) +#assert(size_of(Encoding) == 22) diff --git a/core/rexcode/isa/arm64/instructions.odin b/core/rexcode/isa/arm64/instructions.odin index 26ad8bd3f..f40d31a45 100644 --- a/core/rexcode/isa/arm64/instructions.odin +++ b/core/rexcode/isa/arm64/instructions.odin @@ -28,12 +28,13 @@ Instruction_Flags :: bit_field u8 { // The spare bytes are free: they cost nothing over a 48-byte struct that // straddles, and new fields land in them without changing the layout. Instruction :: struct #align(64) { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * size_of(Operand) = 44 + ops: [5]Operand `fmt:"v,operand_count"`, // 5 * size_of(Operand) = 55 mnemonic: Mnemonic, // 2 operand_count: u8, // 1 flags: Instruction_Flags, // 1 length: u8, // 1 -- always 4 - _: [15]u8, + // 55 is odd, so mnemonic's alignment costs a byte here; 3 more reach 64. + _: [3]u8, } #assert(size_of(Instruction) == 64) #assert(align_of(Instruction) == 64) @@ -52,70 +53,70 @@ inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction { @(require_results) inst_r :: #force_inline proc "contextless" (m: Mnemonic, r: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 1, length = 4, - ops = {op_reg(r), {}, {}, {}}} + ops = {op_reg(r), {}, {}, {}, {}}} } // 2-register (e.g. CLZ, RBIT). @(require_results) inst_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rd), op_reg(rn), {}, {}}} + ops = {op_reg(rd), op_reg(rn), {}, {}, {}}} } // 3-register (e.g. ADD shifted, MUL, UDIV, ASRV). @(require_results) inst_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}}} + ops = {op_reg(rd), op_reg(rn), op_reg(rm), {}, {}}} } // 4-register R4-type (MADD, MSUB, SMADDL, ...). @(require_results) inst_r_r_r_r :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm, ra: Register) -> Instruction { return Instruction{mnemonic = m, operand_count = 4, length = 4, - ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra)}} + ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_reg(ra), {}}} } // 2-register + immediate (e.g. ADD imm). @(require_results) inst_r_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd, rn: Register, imm: i64) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_reg(rn), op_imm(imm), {}}} + ops = {op_reg(rd), op_reg(rn), op_imm(imm), {}, {}}} } // 1-register + immediate (e.g. MOVZ). @(require_results) inst_r_i :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rd), op_imm(imm), {}, {}}} + ops = {op_reg(rd), op_imm(imm), {}, {}, {}}} } // MOVZ/MOVN/MOVK with explicit hw shift (0/16/32/48). @(require_results) inst_mov_imm :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64, hw: u8) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rd), op_imm(imm), op_imm(i64(hw), 1), {}}} + ops = {op_reg(rd), op_imm(imm), op_imm(i64(hw), 1), {}, {}}} } // Load/store register: Rt + memory. @(require_results) inst_ldst :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, mm: Memory) -> Instruction { return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rt), op_mem(mm), {}, {}}} + ops = {op_reg(rt), op_mem(mm), {}, {}, {}}} } // Load/store pair: Rt, Rt2, memory. @(require_results) inst_ldp_stp :: #force_inline proc "contextless" (m: Mnemonic, rt, rt2: Register, mm: Memory) -> Instruction { return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rt), op_reg(rt2), op_mem(mm), {}}} + ops = {op_reg(rt), op_reg(rt2), op_mem(mm), {}, {}}} } // PC-relative branch (B, BL). @(require_results) inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> Instruction { return Instruction{mnemonic = m, operand_count = 1, length = 4, - ops = {op_label(label_id, 4), {}, {}, {}}} + ops = {op_label(label_id, 4), {}, {}, {}, {}}} } // NOTE: the conditional branches, inst_cbz (+cbnz), inst_tbz (+tbnz) and diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index b38fa7d59..606deca71 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -22,23 +22,23 @@ package rexcode_arm64 // ============================================================================= inst_add_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD, dst, src, imm) } -inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_add_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_add_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_add_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_add_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_add_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_add_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_add_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_add_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_add_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_add_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_add_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_add_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_add_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } +inst_add_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_add_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_add_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_add_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_add_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_add_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_add_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_add_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_add_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_add_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_add_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_add_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_add_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_add_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_add_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_add_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_i(dst, src, imm)) } emit_add_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_add_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -58,26 +58,26 @@ emit_add_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_add_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_add_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_add_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_adds_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS, dst, src, imm) } -inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_adds_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_adds_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } emit_adds_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_r_r_i(dst, src, imm)) } emit_adds_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_adds_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } inst_sub_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB, dst, src, imm) } -inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } -inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_sub_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_sub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_sub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sub_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_sub_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } +inst_sub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_sub_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_sub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_sub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sub_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_i(dst, src, imm)) } emit_sub_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_sub_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } @@ -94,29 +94,29 @@ emit_sub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_sub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_subs_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS, dst, src, imm) } -inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +inst_subs_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_subs_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}, {}}} } emit_subs_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_r_r_i(dst, src, imm)) } emit_subs_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_subs_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } -inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } -inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } -inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}, {}}} } emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } -inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } -inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } -inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_and_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_and_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND, dst, src, imm) } -inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_and_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_and_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_and_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_and_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_and_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_and_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_and_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_and_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_and_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_i(dst, src, imm)) } emit_and_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v16b_v16b_v16b(dst, src, src2)) } @@ -125,20 +125,20 @@ emit_and_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_and_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_and_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_and_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_and_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_ands_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_ands_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS, dst, src, imm) } -inst_ands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_ands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_ands_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_ands_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_r_r_i(dst, src, imm)) } emit_ands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_ands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_orr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_orr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR, dst, src, imm) } -inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_orr_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orr_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_orr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_orr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_orr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_orr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_orr_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_i(dst, src, imm)) } emit_orr_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v16b_v16b_v16b(dst, src, src2)) } @@ -147,14 +147,14 @@ emit_orr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_orr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_orr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_orr_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orr_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eor_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } inst_eor_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR, dst, src, imm) } -inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_eor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eor_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_eor_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_eor_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_eor_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_eor_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_eor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_eor_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_eor_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_i(dst, src, imm)) } emit_eor_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v16b_v16b_v16b(dst, src, src2)) } @@ -163,13 +163,13 @@ emit_eor_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_eor_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_eor_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_eor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_bic_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bic_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_bic_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_bic_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_bic_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bic_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_bic_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_bic_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_bic_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bic_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v16b_v16b_v16b(dst, src, src2)) } emit_bic_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -177,23 +177,23 @@ emit_bic_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_bic_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_bic_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_bic_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bic_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_bics_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_bics_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_bics_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BICS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_bics_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_bics_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bics_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } -inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_orn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orn_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } +inst_orn_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_orn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orn_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } emit_orn_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v16b_v16b_v16b(dst, src, src2)) } emit_orn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +inst_eon_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}, {}}} } emit_eon_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSL, dst, src, src2) } -inst_lsl_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsl_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsl_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsl_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsl_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsl_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsl_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsl_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_lsl_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL, dst, src, imm) } emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } emit_lsl_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -202,10 +202,10 @@ emit_lsl_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_lsl_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsl_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsl_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_i(dst, src, imm)) } inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSR, dst, src, src2) } -inst_lsr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_lsr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR, dst, src, imm) } emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } emit_lsr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -214,10 +214,10 @@ emit_lsr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_lsr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } emit_lsr_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_i(dst, src, imm)) } inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASR, dst, src, src2) } -inst_asr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_asr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_asr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_asr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_asr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_asr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_asr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_asr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } inst_asr_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR, dst, src, imm) } emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } emit_asr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -230,14 +230,14 @@ inst_ror_r_r_i :: #force_inline proc "contextless" (dst: Register emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } emit_ror_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_i(dst, src, imm)) } inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -inst_udiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_udiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_udiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_udiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } emit_udiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_udiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_udiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -inst_sdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } emit_sdiv_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sdiv_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sdiv_zd_p_zd_zd(rz, rz2, rz3, rz4)) } @@ -254,36 +254,36 @@ emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Inst inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -inst_smulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } emit_smulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_smulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -inst_umulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umulh_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umulh_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umulh_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umulh_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMULH, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } emit_umulh_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_umulh_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umulh_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umulh_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umulh_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } -inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_clz_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_clz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_clz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_clz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_clz_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_clz_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_clz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_clz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_clz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_clz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_clz_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_clz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_clz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_clz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } emit_clz_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v8b_v8b(dst, src)) } emit_clz_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_v16b_v16b(dst, src)) } @@ -296,16 +296,16 @@ emit_clz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_clz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zs_p_zs(rz, rz2, rz3)) } emit_clz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_clz_zd_p_zd(rz, rz2, rz3)) } inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } -inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cls_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_cls_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_cls_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_cls_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_cls_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cls_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cls_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cls_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cls_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cls_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cls_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_cls_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_cls_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_cls_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CLS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } emit_cls_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v8b_v8b(dst, src)) } emit_cls_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_v16b_v16b(dst, src)) } @@ -318,17 +318,17 @@ emit_cls_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_cls_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zs_p_zs(rz, rz2, rz3)) } emit_cls_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cls_zd_p_zd(rz, rz2, rz3)) } inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } -inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rbit_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rbit_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } emit_rbit_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v8b_v8b(dst, src)) } emit_rbit_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_v16b_v16b(dst, src)) } inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } -inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}}} } -inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}}} } -inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}}} } -inst_rev_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_rev_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } +inst_rev_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_h(rz), op_z_h(rz2), {}, {}, {}}} } +inst_rev_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_s(rz), op_z_s(rz2), {}, {}, {}}} } +inst_rev_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_z_d(rz), op_z_d(rz2), {}, {}, {}}} } +inst_rev_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } emit_rev_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zb_zb(rz, rz2)) } emit_rev_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zh_zh(rz, rz2)) } @@ -336,48 +336,48 @@ emit_rev_zs_zs :: #force_inline proc(instructions: ^[dynamic]Inst emit_rev_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_zd_zd(rz, rz2)) } emit_rev_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_rev_pb_pb(rz, rz2)) } inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } -inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_rev16_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev16_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } emit_rev16_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v8b_v8b(dst, src)) } emit_rev16_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_v16b_v16b(dst, src)) } inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } -inst_rev32_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev32_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_rev32_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_rev32_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_rev32_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev32_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_rev32_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_rev32_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV32, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } emit_rev32_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8b_v8b(dst, src)) } emit_rev32_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v16b_v16b(dst, src)) } emit_rev32_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v4h_v4h(dst, src)) } emit_rev32_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_v8h_v8h(dst, src)) } -inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } -inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } -inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } -inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } -inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +inst_ccmp_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond), {}}} } +inst_ccmp_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMP, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond), {}}} } emit_ccmp_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmp_r_r_i_c(dst, src, imm, cond)) } emit_ccmp_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmp_r_i_i_c(dst, imm, imm2, cond)) } -inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond)}} } -inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond)}} } +inst_ccmn_r_r_i_c :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_cond(cond), {}}} } +inst_ccmn_r_i_i_c :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64, cond: Cond) -> Instruction { return Instruction{mnemonic = .CCMN, operand_count = 4, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_imm(imm2, 1), op_cond(cond), {}}} } emit_ccmn_r_r_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, cond: Cond) { append(instructions, inst_ccmn_r_r_i_c(dst, src, imm, cond)) } emit_ccmn_r_i_i_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64, cond: Cond) { append(instructions, inst_ccmn_r_i_i_c(dst, imm, imm2, cond)) } -inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +inst_cset_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSET, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}, {}}} } emit_cset_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_cset_r_c(dst, cond)) } -inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}}} } +inst_csetm_r_c :: #force_inline proc "contextless" (dst: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSETM, operand_count = 2, length = 4, ops = {op_reg(dst), op_cond(cond), {}, {}, {}}} } emit_csetm_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, cond: Cond) { append(instructions, inst_csetm_r_c(dst, cond)) } -inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cinc_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINC, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cinc_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinc_r_r_c(dst, src, cond)) } -inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cinv_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CINV, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cinv_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cinv_r_r_c(dst, src, cond)) } -inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}}} } +inst_cneg_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CNEG, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_cond(cond), {}, {}}} } emit_cneg_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, cond: Cond) { append(instructions, inst_cneg_r_r_c(dst, src, cond)) } -inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } +inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1), {}}} } emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } @@ -423,28 +423,28 @@ inst_b_al_l :: #force_inline proc "contextless" (label: u32) - emit_b_al_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_al_l(label)) } inst_b_nv_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B_NV, label) } emit_b_nv_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_nv_l(label)) } -inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } -inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } -inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}, {}}} } emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } -inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}, {}}} } emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } -inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } -inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } +inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } +inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } +inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } -inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } +inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } +inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } @@ -501,39 +501,39 @@ inst_sev_none :: #force_inline proc "contextless" () -> Instruct emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_hint_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_hint_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_i(imm)) } -inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}}} } +inst_mrs_r_s :: #force_inline proc "contextless" (dst: Register, sysreg: System_Register) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, length = 4, ops = {op_reg(dst), op_sysreg(sysreg), {}, {}, {}}} } emit_mrs_r_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, sysreg: System_Register) { append(instructions, inst_mrs_r_s(dst, sysreg)) } -inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}}} } -inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}}} } +inst_msr_i_i :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_imm(imm2, 1), {}, {}, {}}} } +inst_msr_s_r :: #force_inline proc "contextless" (sysreg: System_Register, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, length = 4, ops = {op_sysreg(sysreg), op_reg(src), {}, {}, {}}} } emit_msr_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_i_i(imm, imm2)) } emit_msr_s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, sysreg: System_Register, src: Register) { append(instructions, inst_msr_s_r(sysreg, src)) } -inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } -inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } -inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}, {}}} } emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } -inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } -inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } -inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } -inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } -inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } inst_fmov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV, dst, src) } inst_fmov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.FMOV, dst, imm) } -inst_fmov_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_fmov_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } +inst_fmov_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_fmov_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FMOV, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } emit_fmov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_r_r(dst, src)) } emit_fmov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_r_i(dst, imm)) } emit_fmov_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v2s_i(dst, imm)) } @@ -542,14 +542,14 @@ emit_fmov_v2d_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmov_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v4h_i(dst, imm)) } emit_fmov_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_fmov_v8h_i(dst, imm)) } inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } -inst_fabs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fabs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fabs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fabs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fabs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fabs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fabs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fabs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fabs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fabs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fabs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fabs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } emit_fabs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v2s_v2s(dst, src)) } emit_fabs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_v4s_v4s(dst, src)) } @@ -560,14 +560,14 @@ emit_fabs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fabs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zs_p_zs(rz, rz2, rz3)) } emit_fabs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fabs_zd_p_zd(rz, rz2, rz3)) } inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } -inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fneg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fneg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fneg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fneg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fneg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fneg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fneg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fneg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fneg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fneg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fneg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FNEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } emit_fneg_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v2s_v2s(dst, src)) } emit_fneg_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_v4s_v4s(dst, src)) } @@ -578,14 +578,14 @@ emit_fneg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fneg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zs_p_zs(rz, rz2, rz3)) } emit_fneg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fneg_zd_p_zd(rz, rz2, rz3)) } inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } -inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fsqrt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fsqrt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fsqrt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fsqrt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fsqrt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fsqrt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fsqrt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fsqrt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fsqrt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fsqrt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fsqrt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSQRT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } emit_fsqrt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v2s_v2s(dst, src)) } emit_fsqrt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_v4s_v4s(dst, src)) } @@ -596,15 +596,15 @@ emit_fsqrt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fsqrt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zs_p_zs(rz, rz2, rz3)) } emit_fsqrt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fsqrt_zd_p_zd(rz, rz2, rz3)) } inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } -inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fadd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fadd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fadd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fadd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FADD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } emit_fadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v2s_v2s_v2s(dst, src, src2)) } emit_fadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v4s_v4s_v4s(dst, src, src2)) } @@ -616,15 +616,15 @@ emit_fadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fadd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fadd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fadd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } -inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fsub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fsub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fsub_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fsub_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUB, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } emit_fsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v2s_v2s_v2s(dst, src, src2)) } emit_fsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v4s_v4s_v4s(dst, src, src2)) } @@ -636,15 +636,15 @@ emit_fsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fsub_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fsub_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsub_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } -inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_fmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_fmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_fmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmul_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmul_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_fmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_fmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_fmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } emit_fmul_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v2s_v2s_v2s(dst, src, src2)) } emit_fmul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v4s_v4s_v4s(dst, src, src2)) } @@ -656,12 +656,12 @@ emit_fmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } -inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fdiv_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fdiv_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fdiv_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fdiv_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fdiv_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fdiv_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fdiv_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIV, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } emit_fdiv_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v2s_v2s_v2s(dst, src, src2)) } emit_fdiv_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v4s_v4s_v4s(dst, src, src2)) } @@ -683,17 +683,17 @@ inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } -inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond), {}}} } emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } -inst_fmax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmax_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } emit_fmax_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v2s_v2s_v2s(dst, src, src2)) } emit_fmax_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_v4s_v4s_v4s(dst, src, src2)) } @@ -704,14 +704,14 @@ emit_fmax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } -inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmin_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } emit_fmin_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v2s_v2s_v2s(dst, src, src2)) } emit_fmin_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_v4s_v4s_v4s(dst, src, src2)) } @@ -722,14 +722,14 @@ emit_fmin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } -inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmaxnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmaxnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fmaxnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmaxnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmaxnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMAXNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } emit_fmaxnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_v4s_v4s_v4s(dst, src, src2)) } @@ -740,14 +740,14 @@ emit_fmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmaxnm_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fmaxnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmaxnm_zd_p_zd_zd(rz, rz2, rz3, rz4)) } inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } -inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fminnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fminnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fminnm_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminnm_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminnm_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminnm_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminnm_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fminnm_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fminnm_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMINNM, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } emit_fminnm_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v2s_v2s_v2s(dst, src, src2)) } emit_fminnm_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_v4s_v4s_v4s(dst, src, src2)) } @@ -760,11 +760,11 @@ emit_fminnm_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } -inst_scvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_scvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_scvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_scvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_scvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_scvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_scvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_scvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_scvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_scvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } emit_scvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v2s_v2s(dst, src)) } emit_scvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4s_v4s(dst, src)) } @@ -772,11 +772,11 @@ emit_scvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_scvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v4h_v4h(dst, src)) } emit_scvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_v8h_v8h(dst, src)) } inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } -inst_ucvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_ucvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_ucvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_ucvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_ucvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_ucvtf_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_ucvtf_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_ucvtf_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_ucvtf_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_ucvtf_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UCVTF, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } emit_ucvtf_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v2s_v2s(dst, src)) } emit_ucvtf_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4s_v4s(dst, src)) } @@ -784,11 +784,11 @@ emit_ucvtf_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_ucvtf_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v4h_v4h(dst, src)) } emit_ucvtf_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_v8h_v8h(dst, src)) } inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } -inst_fcvtzs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtzs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtzs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtzs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtzs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtzs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtzs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtzs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtzs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtzs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } emit_fcvtzs_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v2s_v2s(dst, src)) } emit_fcvtzs_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4s_v4s(dst, src)) } @@ -796,11 +796,11 @@ emit_fcvtzs_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtzs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v4h_v4h(dst, src)) } emit_fcvtzs_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_v8h_v8h(dst, src)) } inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } -inst_fcvtzu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtzu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtzu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtzu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtzu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtzu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtzu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtzu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtzu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtzu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTZU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } emit_fcvtzu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v2s_v2s(dst, src)) } emit_fcvtzu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4s_v4s(dst, src)) } @@ -808,11 +808,11 @@ emit_fcvtzu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtzu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v4h_v4h(dst, src)) } emit_fcvtzu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_v8h_v8h(dst, src)) } inst_fcvtas_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAS, dst, src) } -inst_fcvtas_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtas_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtas_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtas_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtas_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtas_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtas_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtas_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtas_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtas_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtas_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_r_r(dst, src)) } emit_fcvtas_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v2s_v2s(dst, src)) } emit_fcvtas_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4s_v4s(dst, src)) } @@ -820,11 +820,11 @@ emit_fcvtas_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtas_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v4h_v4h(dst, src)) } emit_fcvtas_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtas_v8h_v8h(dst, src)) } inst_fcvtau_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTAU, dst, src) } -inst_fcvtau_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtau_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtau_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtau_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtau_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtau_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtau_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtau_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtau_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtau_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTAU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtau_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_r_r(dst, src)) } emit_fcvtau_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v2s_v2s(dst, src)) } emit_fcvtau_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4s_v4s(dst, src)) } @@ -832,11 +832,11 @@ emit_fcvtau_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtau_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v4h_v4h(dst, src)) } emit_fcvtau_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtau_v8h_v8h(dst, src)) } inst_fcvtns_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNS, dst, src) } -inst_fcvtns_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtns_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtns_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtns_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtns_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtns_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtns_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtns_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtns_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtns_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtns_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_r_r(dst, src)) } emit_fcvtns_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v2s_v2s(dst, src)) } emit_fcvtns_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4s_v4s(dst, src)) } @@ -844,11 +844,11 @@ emit_fcvtns_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtns_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v4h_v4h(dst, src)) } emit_fcvtns_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtns_v8h_v8h(dst, src)) } inst_fcvtnu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTNU, dst, src) } -inst_fcvtnu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtnu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtnu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtnu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtnu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtnu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtnu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtnu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtnu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtnu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTNU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtnu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_r_r(dst, src)) } emit_fcvtnu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v2s_v2s(dst, src)) } emit_fcvtnu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4s_v4s(dst, src)) } @@ -856,11 +856,11 @@ emit_fcvtnu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtnu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v4h_v4h(dst, src)) } emit_fcvtnu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtnu_v8h_v8h(dst, src)) } inst_fcvtps_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPS, dst, src) } -inst_fcvtps_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtps_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtps_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtps_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtps_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtps_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtps_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtps_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtps_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtps_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_r_r(dst, src)) } emit_fcvtps_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v2s_v2s(dst, src)) } emit_fcvtps_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4s_v4s(dst, src)) } @@ -868,11 +868,11 @@ emit_fcvtps_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtps_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v4h_v4h(dst, src)) } emit_fcvtps_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtps_v8h_v8h(dst, src)) } inst_fcvtpu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTPU, dst, src) } -inst_fcvtpu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtpu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtpu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtpu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtpu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtpu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtpu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtpu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtpu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtpu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTPU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtpu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_r_r(dst, src)) } emit_fcvtpu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v2s_v2s(dst, src)) } emit_fcvtpu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4s_v4s(dst, src)) } @@ -880,11 +880,11 @@ emit_fcvtpu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtpu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v4h_v4h(dst, src)) } emit_fcvtpu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtpu_v8h_v8h(dst, src)) } inst_fcvtms_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMS, dst, src) } -inst_fcvtms_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtms_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtms_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtms_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtms_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtms_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtms_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtms_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtms_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtms_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtms_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_r_r(dst, src)) } emit_fcvtms_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v2s_v2s(dst, src)) } emit_fcvtms_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4s_v4s(dst, src)) } @@ -892,11 +892,11 @@ emit_fcvtms_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtms_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v4h_v4h(dst, src)) } emit_fcvtms_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtms_v8h_v8h(dst, src)) } inst_fcvtmu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTMU, dst, src) } -inst_fcvtmu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcvtmu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcvtmu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcvtmu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcvtmu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_fcvtmu_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcvtmu_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtmu_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcvtmu_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtmu_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTMU, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_fcvtmu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_r_r(dst, src)) } emit_fcvtmu_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v2s_v2s(dst, src)) } emit_fcvtmu_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4s_v4s(dst, src)) } @@ -904,14 +904,14 @@ emit_fcvtmu_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcvtmu_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v4h_v4h(dst, src)) } emit_fcvtmu_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtmu_v8h_v8h(dst, src)) } inst_frinta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTA, dst, src) } -inst_frinta_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinta_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frinta_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frinta_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frinta_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frinta_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frinta_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frinta_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frinta_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frinta_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frinta_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frinta_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTA, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frinta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_r_r(dst, src)) } emit_frinta_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v2s_v2s(dst, src)) } emit_frinta_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinta_v4s_v4s(dst, src)) } @@ -922,14 +922,14 @@ emit_frinta_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frinta_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zs_p_zs(rz, rz2, rz3)) } emit_frinta_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinta_zd_p_zd(rz, rz2, rz3)) } inst_frinti_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTI, dst, src) } -inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frinti_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frinti_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frinti_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frinti_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frinti_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frinti_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frinti_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frinti_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frinti_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frinti_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frinti_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTI, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frinti_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_r_r(dst, src)) } emit_frinti_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v2s_v2s(dst, src)) } emit_frinti_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frinti_v4s_v4s(dst, src)) } @@ -940,14 +940,14 @@ emit_frinti_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frinti_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zs_p_zs(rz, rz2, rz3)) } emit_frinti_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frinti_zd_p_zd(rz, rz2, rz3)) } inst_frintm_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTM, dst, src) } -inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintm_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintm_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintm_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintm_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintm_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintm_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintm_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintm_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintm_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintm_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintm_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTM, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintm_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_r_r(dst, src)) } emit_frintm_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v2s_v2s(dst, src)) } emit_frintm_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintm_v4s_v4s(dst, src)) } @@ -958,14 +958,14 @@ emit_frintm_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintm_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zs_p_zs(rz, rz2, rz3)) } emit_frintm_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintm_zd_p_zd(rz, rz2, rz3)) } inst_frintn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTN, dst, src) } -inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintn_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintn_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintn_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintn_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintn_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintn_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintn_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintn_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintn_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintn_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintn_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTN, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_r_r(dst, src)) } emit_frintn_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v2s_v2s(dst, src)) } emit_frintn_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintn_v4s_v4s(dst, src)) } @@ -976,14 +976,14 @@ emit_frintn_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintn_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zs_p_zs(rz, rz2, rz3)) } emit_frintn_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintn_zd_p_zd(rz, rz2, rz3)) } inst_frintp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTP, dst, src) } -inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintp_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintp_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintp_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintp_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintp_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintp_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintp_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintp_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintp_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintp_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintp_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTP, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_r_r(dst, src)) } emit_frintp_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v2s_v2s(dst, src)) } emit_frintp_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintp_v4s_v4s(dst, src)) } @@ -994,14 +994,14 @@ emit_frintp_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintp_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zs_p_zs(rz, rz2, rz3)) } emit_frintp_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintp_zd_p_zd(rz, rz2, rz3)) } inst_frintx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTX, dst, src) } -inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintx_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintx_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintx_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintx_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintx_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_r_r(dst, src)) } emit_frintx_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v2s_v2s(dst, src)) } emit_frintx_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintx_v4s_v4s(dst, src)) } @@ -1012,14 +1012,14 @@ emit_frintx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zs_p_zs(rz, rz2, rz3)) } emit_frintx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintx_zd_p_zd(rz, rz2, rz3)) } inst_frintz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRINTZ, dst, src) } -inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_frintz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frintz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frintz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frintz_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frintz_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frintz_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frintz_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frintz_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_frintz_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frintz_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frintz_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRINTZ, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frintz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_r_r(dst, src)) } emit_frintz_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v2s_v2s(dst, src)) } emit_frintz_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frintz_v4s_v4s(dst, src)) } @@ -1030,7 +1030,7 @@ emit_frintz_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frintz_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zs_p_zs(rz, rz2, rz3)) } emit_frintz_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frintz_zd_p_zd(rz, rz2, rz3)) } inst_tst_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST, dst, imm) } -inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_tst_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_tst_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_i(dst, imm)) } emit_tst_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_r_sh(dst, src, src_shift, src_amount)) } inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } @@ -1057,11 +1057,11 @@ inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } -inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem), {}}} } emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } -inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem), {}}} } emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } @@ -1273,9 +1273,9 @@ inst_bti_none :: #force_inline proc "contextless" () -> Instruct emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } -inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1), {}}} } emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } -inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1), {}}} } emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } @@ -1317,113 +1317,113 @@ inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } -inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aese_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_aese_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aese_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_aese_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_v16b_v16b(dst, src)) } emit_aese_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aese_zb_zb_zb(rz, rz2, rz3)) } -inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_aesd_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_aesd_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_v16b_v16b(dst, src)) } emit_aesd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_aesd_zb_zb_zb(rz, rz2, rz3)) } -inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesmc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesmc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesmc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_aesmc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_v16b_v16b(dst, src)) } emit_aesmc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesmc_zb_zb(rz, rz2)) } -inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_aesimc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_aesimc_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_aesimc_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_aesimc_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_v16b_v16b(dst, src)) } emit_aesimc_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_aesimc_zb_zb(rz, rz2)) } inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } -inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1c_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1c_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_v4s(dst, src, src2)) } -inst_sha1p_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1p_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1p_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_v4s(dst, src, src2)) } -inst_sha1m_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha1m_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha1m_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_v4s(dst, src, src2)) } -inst_sha1su0_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sha1su0_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sha1su0_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_v4s_v4s_v4s(dst, src, src2)) } -inst_sha1su1_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sha1su1_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sha1su1_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_v4s_v4s(dst, src)) } -inst_sha256h_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha256h_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha256h_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_v4s(dst, src, src2)) } -inst_sha256h2_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}}} } +inst_sha256h2_r_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(src2), {}, {}}} } emit_sha256h2_r_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_v4s(dst, src, src2)) } -inst_sha256su0_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sha256su0_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sha256su0_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_v4s_v4s(dst, src)) } -inst_sha256su1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sha256su1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sha256su1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_v4s_v4s_v4s(dst, src, src2)) } -inst_sha512h_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +inst_sha512h_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}, {}}} } emit_sha512h_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_v2d(dst, src, src2)) } -inst_sha512h2_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}}} } +inst_sha512h2_r_r_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(src2), {}, {}}} } emit_sha512h2_r_r_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_v2d(dst, src, src2)) } -inst_sha512su0_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_sha512su0_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_sha512su0_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_v2d_v2d(dst, src)) } -inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sha512su1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_sha512su1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_v2d_v2d_v2d(dst, src, src2)) } -inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_eor3_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_eor3_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3), {}}} } +inst_eor3_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_eor3_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } emit_eor3_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eor3_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3)}} } -inst_bcax_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bcax_v16b_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_v_16b(src3), {}}} } +inst_bcax_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bcax_v16b_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_v16b_v16b_v16b_v16b(dst, src, src2, src3)) } emit_bcax_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bcax_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rax1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_v2d_v2d_v2d(dst, src, src2)) } -inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } -inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4)}} } +inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } +inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4), {}}} } emit_xar_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_v2d_v2d_v2d_i(dst, src, src2, imm)) } emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } -inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm3partw1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_v4s_v4s_v4s(dst, src, src2)) } -inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm3partw2_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_v4s_v4s_v4s(dst, src, src2)) } -inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3)}} } +inst_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_v_4s(src3), {}}} } emit_sm3ss1_v4s_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_v4s_v4s_v4s_v4s(dst, src, src2, src3)) } -inst_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt1a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1a_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt1b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt1b_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt2a_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2a_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm)}} } +inst_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_elem_s(src2), op_lane_index(imm), {}}} } emit_sm3tt2b_v4s_v4s_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_sm3tt2b_v4s_v4s_ves_i(dst, src, src2, imm)) } -inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_sm4e_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_sm4e_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_v4s_v4s(dst, src)) } -inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sm4ekey_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm4ekey_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_v4s_v4s_v4s(dst, src, src2)) } -inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_pmull_v1q_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_1d(src), op_v_1d(src2), {}}} } +inst_pmull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_pmull_v1q_v1d_v1d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_1d(src), op_v_1d(src2), {}, {}}} } emit_pmull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v8h_v8b_v8b(dst, src, src2)) } emit_pmull_v1q_v1d_v1d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_v1q_v1d_v1d(dst, src, src2)) } -inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_pmull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_pmull2_v1q_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_1q(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_pmull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v8h_v16b_v16b(dst, src, src2)) } emit_pmull2_v1q_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_v1q_v2d_v2d(dst, src, src2)) } inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -inst_bfcvt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_bfcvt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } emit_bfcvt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvt_zh_p_zs(rz, rz2, rz3)) } -inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfdot_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfdot_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmmla_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmmla_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmlalb_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmlalb_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmlalb_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_v4s_v8h_v8h(dst, src, src2)) } -inst_bfmlalt_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_bfmlalt_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_bfmlalt_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_v4s_v8h_v8h(dst, src, src2)) } -inst_bfcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } +inst_bfcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } emit_bfcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_v4h_v4s(dst, src)) } -inst_bfcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } +inst_bfcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } emit_bfcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_v8h_v4s(dst, src)) } -inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_mul_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_mul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_mul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_mul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_mul_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mul_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mul_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_mul_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_mul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_mul_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_mul_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_mul_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v16b_v16b_v16b(dst, src, src2)) } emit_mul_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v8h_v8h_v8h(dst, src, src2)) } emit_mul_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v4s_v4s_v4s(dst, src, src2)) } @@ -1431,42 +1431,42 @@ emit_mul_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_mul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_mul_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_mul_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_mul_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_mla_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mla_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_mla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_mla_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_mla_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mla_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_mla_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mla_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_mla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_mla_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8b_v8b_v8b(dst, src, src2)) } emit_mla_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v16b_v16b_v16b(dst, src, src2)) } emit_mla_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4h_v4h_v4h(dst, src, src2)) } emit_mla_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v8h_v8h_v8h(dst, src, src2)) } emit_mla_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v2s_v2s_v2s(dst, src, src2)) } emit_mla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mla_v4s_v4s_v4s(dst, src, src2)) } -inst_mls_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_mls_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_mls_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_mls_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_mls_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_mls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_mls_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_mls_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_mls_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_mls_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_mls_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_mls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_mls_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8b_v8b_v8b(dst, src, src2)) } emit_mls_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v16b_v16b_v16b(dst, src, src2)) } emit_mls_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4h_v4h_v4h(dst, src, src2)) } emit_mls_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v8h_v8h_v8h(dst, src, src2)) } emit_mls_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v2s_v2s_v2s(dst, src, src2)) } emit_mls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mls_v4s_v4s_v4s(dst, src, src2)) } -inst_neg_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_neg_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_neg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_neg_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_neg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_neg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_neg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } -inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_neg_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_neg_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_neg_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_neg_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_neg_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_neg_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_neg_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_neg_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_neg_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_neg_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_neg_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } +inst_neg_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_neg_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v8b_v8b(dst, src)) } emit_neg_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v16b_v16b(dst, src)) } emit_neg_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_v4h_v4h(dst, src)) } @@ -1479,17 +1479,17 @@ emit_neg_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_neg_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zs_p_zs(rz, rz2, rz3)) } emit_neg_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_neg_zd_p_zd(rz, rz2, rz3)) } emit_neg_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_r_sh(dst, src, src_shift, src_amount)) } -inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_abs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_abs_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_abs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_abs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_abs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_abs_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_abs_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_abs_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_abs_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_abs_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_abs_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_abs_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_abs_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_abs_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_abs_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_abs_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ABS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_abs_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v8b_v8b(dst, src)) } emit_abs_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v16b_v16b(dst, src)) } emit_abs_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_abs_v4h_v4h(dst, src)) } @@ -1501,89 +1501,89 @@ emit_abs_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_abs_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zh_p_zh(rz, rz2, rz3)) } emit_abs_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zs_p_zs(rz, rz2, rz3)) } emit_abs_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_abs_zd_p_zd(rz, rz2, rz3)) } -inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_shadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_shadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_shadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_shadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_shadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_shadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_shadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_shadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_shadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_shadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8b_v8b_v8b(dst, src, src2)) } emit_shadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v16b_v16b_v16b(dst, src, src2)) } emit_shadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4h_v4h_v4h(dst, src, src2)) } emit_shadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v8h_v8h_v8h(dst, src, src2)) } emit_shadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v2s_v2s_v2s(dst, src, src2)) } emit_shadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd_v4s_v4s_v4s(dst, src, src2)) } -inst_uhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8b_v8b_v8b(dst, src, src2)) } emit_uhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v16b_v16b_v16b(dst, src, src2)) } emit_uhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4h_v4h_v4h(dst, src, src2)) } emit_uhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v8h_v8h_v8h(dst, src, src2)) } emit_uhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v2s_v2s_v2s(dst, src, src2)) } emit_uhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_shsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_shsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_shsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_shsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_shsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_shsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_shsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_shsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_shsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_shsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_shsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_shsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_shsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8b_v8b_v8b(dst, src, src2)) } emit_shsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v16b_v16b_v16b(dst, src, src2)) } emit_shsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4h_v4h_v4h(dst, src, src2)) } emit_shsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v8h_v8h_v8h(dst, src, src2)) } emit_shsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v2s_v2s_v2s(dst, src, src2)) } emit_shsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub_v4s_v4s_v4s(dst, src, src2)) } -inst_uhsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uhsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uhsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uhsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uhsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uhsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uhsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uhsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uhsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uhsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uhsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uhsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uhsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8b_v8b_v8b(dst, src, src2)) } emit_uhsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v16b_v16b_v16b(dst, src, src2)) } emit_uhsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4h_v4h_v4h(dst, src, src2)) } emit_uhsub_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v8h_v8h_v8h(dst, src, src2)) } emit_uhsub_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v2s_v2s_v2s(dst, src, src2)) } emit_uhsub_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub_v4s_v4s_v4s(dst, src, src2)) } -inst_srhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_srhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_srhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_srhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_srhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_srhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_srhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_srhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_srhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_srhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_srhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_srhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_srhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8b_v8b_v8b(dst, src, src2)) } emit_srhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v16b_v16b_v16b(dst, src, src2)) } emit_srhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4h_v4h_v4h(dst, src, src2)) } emit_srhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v8h_v8h_v8h(dst, src, src2)) } emit_srhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v2s_v2s_v2s(dst, src, src2)) } emit_srhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_urhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_urhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_urhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_urhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_urhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_urhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_urhadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_urhadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_urhadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_urhadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_urhadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_urhadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URHADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_urhadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8b_v8b_v8b(dst, src, src2)) } emit_urhadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v16b_v16b_v16b(dst, src, src2)) } emit_urhadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4h_v4h_v4h(dst, src, src2)) } emit_urhadd_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v8h_v8h_v8h(dst, src, src2)) } emit_urhadd_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v2s_v2s_v2s(dst, src, src2)) } emit_urhadd_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urhadd_v4s_v4s_v4s(dst, src, src2)) } -inst_sqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v8b_v8b_v8b(dst, src, src2)) } emit_sqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v16b_v16b_v16b(dst, src, src2)) } emit_sqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1595,17 +1595,17 @@ emit_sqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zh_zh_zh(rz, rz2, rz3)) } emit_sqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zs_zs_zs(rz, rz2, rz3)) } emit_sqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqadd_zd_zd_zd(rz, rz2, rz3)) } -inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uqadd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uqadd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uqadd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uqadd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uqadd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uqadd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uqadd_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uqadd_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uqadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uqadd_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uqadd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQADD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_uqadd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v8b_v8b_v8b(dst, src, src2)) } emit_uqadd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v16b_v16b_v16b(dst, src, src2)) } emit_uqadd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd_v4h_v4h_v4h(dst, src, src2)) } @@ -1617,17 +1617,17 @@ emit_uqadd_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zh_zh_zh(rz, rz2, rz3)) } emit_uqadd_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zs_zs_zs(rz, rz2, rz3)) } emit_uqadd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqadd_zd_zd_zd(rz, rz2, rz3)) } -inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_sqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_sqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v8b_v8b_v8b(dst, src, src2)) } emit_sqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v16b_v16b_v16b(dst, src, src2)) } emit_sqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1639,17 +1639,17 @@ emit_sqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zh_zh_zh(rz, rz2, rz3)) } emit_sqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zs_zs_zs(rz, rz2, rz3)) } emit_sqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqsub_zd_zd_zd(rz, rz2, rz3)) } -inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_uqsub_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uqsub_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uqsub_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uqsub_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uqsub_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uqsub_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uqsub_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uqsub_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uqsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uqsub_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uqsub_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UQSUB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_uqsub_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v8b_v8b_v8b(dst, src, src2)) } emit_uqsub_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v16b_v16b_v16b(dst, src, src2)) } emit_uqsub_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub_v4h_v4h_v4h(dst, src, src2)) } @@ -1661,16 +1661,16 @@ emit_uqsub_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zh_zh_zh(rz, rz2, rz3)) } emit_uqsub_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zs_zs_zs(rz, rz2, rz3)) } emit_uqsub_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uqsub_zd_zd_zd(rz, rz2, rz3)) } -inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_smax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v8b_v8b_v8b(dst, src, src2)) } emit_smax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v16b_v16b_v16b(dst, src, src2)) } emit_smax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smax_v4h_v4h_v4h(dst, src, src2)) } @@ -1681,16 +1681,16 @@ emit_smax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_smax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umax_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umax_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umax_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umax_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umax_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umax_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_umax_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umax_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umax_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umax_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMAX, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umax_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v8b_v8b_v8b(dst, src, src2)) } emit_umax_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v16b_v16b_v16b(dst, src, src2)) } emit_umax_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umax_v4h_v4h_v4h(dst, src, src2)) } @@ -1701,16 +1701,16 @@ emit_umax_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_umax_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umax_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umax_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umax_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_smin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_smin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_smin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_smin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_smin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_smin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_smin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_smin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_smin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_smin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v8b_v8b_v8b(dst, src, src2)) } emit_smin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v16b_v16b_v16b(dst, src, src2)) } emit_smin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smin_v4h_v4h_v4h(dst, src, src2)) } @@ -1721,16 +1721,16 @@ emit_smin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_smin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_smin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_smin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_umin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_umin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_umin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_umin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_umin_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umin_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umin_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umin_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umin_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umin_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_umin_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_umin_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_umin_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_umin_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMIN, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_umin_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v8b_v8b_v8b(dst, src, src2)) } emit_umin_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v16b_v16b_v16b(dst, src, src2)) } emit_umin_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umin_v4h_v4h_v4h(dst, src, src2)) } @@ -1741,16 +1741,16 @@ emit_umin_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_umin_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_umin_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_umin_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umin_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_sabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_sabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_sabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_sabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_sabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_sabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_sabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_sabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v8b_v8b_v8b(dst, src, src2)) } emit_sabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v16b_v16b_v16b(dst, src, src2)) } emit_sabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sabd_v4h_v4h_v4h(dst, src, src2)) } @@ -1761,16 +1761,16 @@ emit_sabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_sabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_sabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_sabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_uabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_uabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_uabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_uabd_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uabd_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uabd_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uabd_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uabd_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uabd_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uabd_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_uabd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_uabd_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_uabd_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UABD, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_uabd_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v8b_v8b_v8b(dst, src, src2)) } emit_uabd_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v16b_v16b_v16b(dst, src, src2)) } emit_uabd_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uabd_v4h_v4h_v4h(dst, src, src2)) } @@ -1781,37 +1781,37 @@ emit_uabd_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Inst emit_uabd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_uabd_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_uabd_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_uabd_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_saba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_saba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_saba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_saba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_saba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_saba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_saba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_saba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_saba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_saba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8b_v8b_v8b(dst, src, src2)) } emit_saba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v16b_v16b_v16b(dst, src, src2)) } emit_saba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4h_v4h_v4h(dst, src, src2)) } emit_saba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v8h_v8h_v8h(dst, src, src2)) } emit_saba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v2s_v2s_v2s(dst, src, src2)) } emit_saba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saba_v4s_v4s_v4s(dst, src, src2)) } -inst_uaba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uaba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uaba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uaba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uaba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uaba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uaba_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uaba_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uaba_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uaba_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uaba_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uaba_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UABA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uaba_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8b_v8b_v8b(dst, src, src2)) } emit_uaba_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v16b_v16b_v16b(dst, src, src2)) } emit_uaba_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4h_v4h_v4h(dst, src, src2)) } emit_uaba_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v8h_v8h_v8h(dst, src, src2)) } emit_uaba_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v2s_v2s_v2s(dst, src, src2)) } emit_uaba_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaba_v4s_v4s_v4s(dst, src, src2)) } -inst_addp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_addp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_addp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_addp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_addp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_addp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_addp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_addp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_addp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v8b_v8b_v8b(dst, src, src2)) } emit_addp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v16b_v16b_v16b(dst, src, src2)) } emit_addp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4h_v4h_v4h(dst, src, src2)) } @@ -1819,496 +1819,496 @@ emit_addp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_addp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2s_v2s_v2s(dst, src, src2)) } emit_addp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v4s_v4s_v4s(dst, src, src2)) } emit_addp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addp_v2d_v2d_v2d(dst, src, src2)) } -inst_addv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_addv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_addv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_addv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_addv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_addv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_addv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_addv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_addv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_addv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADDV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_addv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8b(dst, src)) } emit_addv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v16b(dst, src)) } emit_addv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4h(dst, src)) } emit_addv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v8h(dst, src)) } emit_addv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_addv_r_v4s(dst, src)) } -inst_saddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_saddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_saddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_saddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_saddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_saddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_saddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_saddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_saddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_saddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_saddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_saddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_saddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4h_v8b(dst, src)) } emit_saddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v8h_v16b(dst, src)) } emit_saddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2s_v4h(dst, src)) } emit_saddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v4s_v8h(dst, src)) } emit_saddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v1d_v2s(dst, src)) } emit_saddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlp_v2d_v4s(dst, src)) } -inst_uaddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_uaddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uaddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_uaddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uaddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_uaddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uaddlp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uaddlp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uaddlp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uaddlp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uaddlp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_uaddlp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uaddlp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4h_v8b(dst, src)) } emit_uaddlp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v8h_v16b(dst, src)) } emit_uaddlp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2s_v4h(dst, src)) } emit_uaddlp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v4s_v8h(dst, src)) } emit_uaddlp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v1d_v2s(dst, src)) } emit_uaddlp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlp_v2d_v4s(dst, src)) } -inst_sadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_sadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_sadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_sadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_sadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_sadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_sadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_sadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_sadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_sadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_sadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_sadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_sadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4h_v8b(dst, src)) } emit_sadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v8h_v16b(dst, src)) } emit_sadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2s_v4h(dst, src)) } emit_sadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v4s_v8h(dst, src)) } emit_sadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v1d_v2s(dst, src)) } emit_sadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sadalp_v2d_v4s(dst, src)) } -inst_uadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}}} } -inst_uadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}}} } -inst_uadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}}} } -inst_uadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uadalp_v4h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uadalp_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uadalp_v2s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uadalp_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uadalp_v1d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_1d(dst), op_v_2s(src), {}, {}, {}}} } +inst_uadalp_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADALP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uadalp_v4h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4h_v8b(dst, src)) } emit_uadalp_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v8h_v16b(dst, src)) } emit_uadalp_v2s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2s_v4h(dst, src)) } emit_uadalp_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v4s_v8h(dst, src)) } emit_uadalp_v1d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v1d_v2s(dst, src)) } emit_uadalp_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uadalp_v2d_v4s(dst, src)) } -inst_saddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_saddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_saddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_saddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_saddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_saddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_saddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_saddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_saddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_saddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_saddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8b(dst, src)) } emit_saddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v16b(dst, src)) } emit_saddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4h(dst, src)) } emit_saddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v8h(dst, src)) } emit_saddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_saddlv_r_v4s(dst, src)) } -inst_uaddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_uaddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_uaddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_uaddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_uaddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_uaddlv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_uaddlv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_uaddlv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_uaddlv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_uaddlv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UADDLV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_uaddlv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8b(dst, src)) } emit_uaddlv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v16b(dst, src)) } emit_uaddlv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4h(dst, src)) } emit_uaddlv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v8h(dst, src)) } emit_uaddlv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uaddlv_r_v4s(dst, src)) } -inst_smaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_smaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_smaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_smaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_smaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_smaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_smaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_smaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_smaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_smaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_smaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8b(dst, src)) } emit_smaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v16b(dst, src)) } emit_smaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4h(dst, src)) } emit_smaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v8h(dst, src)) } emit_smaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_smaxv_r_v4s(dst, src)) } -inst_umaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_umaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_umaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_umaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_umaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_umaxv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_umaxv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_umaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_umaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_umaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_umaxv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8b(dst, src)) } emit_umaxv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v16b(dst, src)) } emit_umaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4h(dst, src)) } emit_umaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v8h(dst, src)) } emit_umaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_umaxv_r_v4s(dst, src)) } -inst_sminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_sminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_sminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_sminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_sminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_sminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_sminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_sminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_sminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_sminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_sminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8b(dst, src)) } emit_sminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v16b(dst, src)) } emit_sminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4h(dst, src)) } emit_sminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v8h(dst, src)) } emit_sminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sminv_r_v4s(dst, src)) } -inst_uminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}}} } -inst_uminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}}} } -inst_uminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_uminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } -inst_uminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } +inst_uminv_r_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8b(src), {}, {}, {}}} } +inst_uminv_r_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_16b(src), {}, {}, {}}} } +inst_uminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_uminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } +inst_uminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } emit_uminv_r_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8b(dst, src)) } emit_uminv_r_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v16b(dst, src)) } emit_uminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4h(dst, src)) } emit_uminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v8h(dst, src)) } emit_uminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uminv_r_v4s(dst, src)) } -inst_smaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_smaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_smaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8b_v8b_v8b(dst, src, src2)) } emit_smaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v16b_v16b_v16b(dst, src, src2)) } emit_smaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4h_v4h_v4h(dst, src, src2)) } emit_smaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v8h_v8h_v8h(dst, src, src2)) } emit_smaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v2s_v2s_v2s(dst, src, src2)) } emit_smaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smaxp_v4s_v4s_v4s(dst, src, src2)) } -inst_umaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_umaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umaxp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umaxp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_umaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umaxp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8b_v8b_v8b(dst, src, src2)) } emit_umaxp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v16b_v16b_v16b(dst, src, src2)) } emit_umaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4h_v4h_v4h(dst, src, src2)) } emit_umaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v8h_v8h_v8h(dst, src, src2)) } emit_umaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v2s_v2s_v2s(dst, src, src2)) } emit_umaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umaxp_v4s_v4s_v4s(dst, src, src2)) } -inst_sminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8b_v8b_v8b(dst, src, src2)) } emit_sminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v16b_v16b_v16b(dst, src, src2)) } emit_sminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4h_v4h_v4h(dst, src, src2)) } emit_sminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v8h_v8h_v8h(dst, src, src2)) } emit_sminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v2s_v2s_v2s(dst, src, src2)) } emit_sminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sminp_v4s_v4s_v4s(dst, src, src2)) } -inst_uminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uminp_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uminp_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uminp_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8b_v8b_v8b(dst, src, src2)) } emit_uminp_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v16b_v16b_v16b(dst, src, src2)) } emit_uminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4h_v4h_v4h(dst, src, src2)) } emit_uminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v8h_v8h_v8h(dst, src, src2)) } emit_uminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v2s_v2s_v2s(dst, src, src2)) } emit_uminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uminp_v4s_v4s_v4s(dst, src, src2)) } -inst_saddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_saddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_saddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_saddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_saddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_saddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_saddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v8h_v8b_v8b(dst, src, src2)) } emit_saddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v4s_v4h_v4h(dst, src, src2)) } emit_saddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl_v2d_v2s_v2s(dst, src, src2)) } -inst_saddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_saddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_saddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_saddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_saddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_saddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_saddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v8h_v16b_v16b(dst, src, src2)) } emit_saddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v4s_v8h_v8h(dst, src, src2)) } emit_saddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddl2_v2d_v4s_v4s(dst, src, src2)) } -inst_uaddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uaddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uaddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_uaddl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uaddl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uaddl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_uaddl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v8h_v8b_v8b(dst, src, src2)) } emit_uaddl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v4s_v4h_v4h(dst, src, src2)) } emit_uaddl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl_v2d_v2s_v2s(dst, src, src2)) } -inst_uaddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uaddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uaddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_uaddl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uaddl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uaddl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_uaddl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v8h_v16b_v16b(dst, src, src2)) } emit_uaddl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v4s_v8h_v8h(dst, src, src2)) } emit_uaddl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddl2_v2d_v4s_v4s(dst, src, src2)) } -inst_ssubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_ssubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_ssubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_ssubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_ssubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_ssubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_ssubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v8h_v8b_v8b(dst, src, src2)) } emit_ssubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v4s_v4h_v4h(dst, src, src2)) } emit_ssubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl_v2d_v2s_v2s(dst, src, src2)) } -inst_ssubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_ssubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_ssubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_ssubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_ssubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_ssubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_ssubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v8h_v16b_v16b(dst, src, src2)) } emit_ssubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v4s_v8h_v8h(dst, src, src2)) } emit_ssubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubl2_v2d_v4s_v4s(dst, src, src2)) } -inst_usubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_usubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_usubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_usubl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_usubl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_usubl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_usubl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v8h_v8b_v8b(dst, src, src2)) } emit_usubl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v4s_v4h_v4h(dst, src, src2)) } emit_usubl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_v2d_v2s_v2s(dst, src, src2)) } -inst_usubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_usubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_usubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_usubl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_usubl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_usubl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_usubl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v8h_v16b_v16b(dst, src, src2)) } emit_usubl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v4s_v8h_v8h(dst, src, src2)) } emit_usubl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_v2d_v4s_v4s(dst, src, src2)) } -inst_saddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_saddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_saddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_saddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_saddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_saddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_saddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v8h_v8h_v8b(dst, src, src2)) } emit_saddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v4s_v4s_v4h(dst, src, src2)) } emit_saddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_v2d_v2d_v2s(dst, src, src2)) } -inst_saddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_saddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_saddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_saddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_saddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_saddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_saddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v8h_v8h_v16b(dst, src, src2)) } emit_saddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v4s_v4s_v8h(dst, src, src2)) } emit_saddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_v2d_v2d_v4s(dst, src, src2)) } -inst_uaddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_uaddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_uaddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_uaddw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_uaddw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_uaddw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_uaddw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v8h_v8h_v8b(dst, src, src2)) } emit_uaddw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v4s_v4s_v4h(dst, src, src2)) } emit_uaddw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_v2d_v2d_v2s(dst, src, src2)) } -inst_uaddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_uaddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_uaddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_uaddw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_uaddw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_uaddw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_uaddw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v8h_v8h_v16b(dst, src, src2)) } emit_uaddw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v4s_v4s_v8h(dst, src, src2)) } emit_uaddw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_v2d_v2d_v4s(dst, src, src2)) } -inst_ssubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_ssubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_ssubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_ssubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_ssubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_ssubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_ssubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v8h_v8h_v8b(dst, src, src2)) } emit_ssubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v4s_v4s_v4h(dst, src, src2)) } emit_ssubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_v2d_v2d_v2s(dst, src, src2)) } -inst_ssubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_ssubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_ssubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_ssubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_ssubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_ssubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_ssubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v8h_v8h_v16b(dst, src, src2)) } emit_ssubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v4s_v4s_v8h(dst, src, src2)) } emit_ssubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_v2d_v2d_v4s(dst, src, src2)) } -inst_usubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}}} } -inst_usubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}}} } -inst_usubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}}} } +inst_usubw_v8h_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8b(src2), {}, {}}} } +inst_usubw_v4s_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4h(src2), {}, {}}} } +inst_usubw_v2d_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2s(src2), {}, {}}} } emit_usubw_v8h_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v8h_v8h_v8b(dst, src, src2)) } emit_usubw_v4s_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v4s_v4s_v4h(dst, src, src2)) } emit_usubw_v2d_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_v2d_v2d_v2s(dst, src, src2)) } -inst_usubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}}} } -inst_usubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}}} } -inst_usubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}}} } +inst_usubw2_v8h_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_16b(src2), {}, {}}} } +inst_usubw2_v4s_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_8h(src2), {}, {}}} } +inst_usubw2_v2d_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_4s(src2), {}, {}}} } emit_usubw2_v8h_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v8h_v8h_v16b(dst, src, src2)) } emit_usubw2_v4s_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v4s_v4s_v8h(dst, src, src2)) } emit_usubw2_v2d_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_v2d_v2d_v4s(dst, src, src2)) } -inst_raddhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_raddhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_raddhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_raddhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_raddhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_raddhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_raddhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v8b_v8h_v8h(dst, src, src2)) } emit_raddhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v4h_v4s_v4s(dst, src, src2)) } emit_raddhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_v2s_v2d_v2d(dst, src, src2)) } -inst_raddhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_raddhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_raddhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_raddhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_raddhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_raddhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_raddhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v16b_v8h_v8h(dst, src, src2)) } emit_raddhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v8h_v4s_v4s(dst, src, src2)) } emit_raddhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_rsubhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_rsubhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_rsubhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rsubhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_rsubhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_rsubhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rsubhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v8b_v8h_v8h(dst, src, src2)) } emit_rsubhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v4h_v4s_v4s(dst, src, src2)) } emit_rsubhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_v2s_v2d_v2d(dst, src, src2)) } -inst_rsubhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_rsubhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_rsubhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_rsubhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_rsubhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_rsubhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rsubhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v16b_v8h_v8h(dst, src, src2)) } emit_rsubhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v8h_v4s_v4s(dst, src, src2)) } emit_rsubhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_addhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v8b_v8h_v8h(dst, src, src2)) } emit_addhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v4h_v4s_v4s(dst, src, src2)) } emit_addhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_v2s_v2d_v2d(dst, src, src2)) } -inst_addhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_addhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_addhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_addhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_addhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_addhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_addhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v16b_v8h_v8h(dst, src, src2)) } emit_addhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v8h_v4s_v4s(dst, src, src2)) } emit_addhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_subhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_subhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_subhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_subhn_v8b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_subhn_v4h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_subhn_v2s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_subhn_v8b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v8b_v8h_v8h(dst, src, src2)) } emit_subhn_v4h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v4h_v4s_v4s(dst, src, src2)) } emit_subhn_v2s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_v2s_v2d_v2d(dst, src, src2)) } -inst_subhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_subhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_subhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_subhn2_v16b_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_subhn2_v8h_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_subhn2_v4s_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_subhn2_v16b_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v16b_v8h_v8h(dst, src, src2)) } emit_subhn2_v8h_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v8h_v4s_v4s(dst, src, src2)) } emit_subhn2_v4s_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_v4s_v2d_v2d(dst, src, src2)) } -inst_xtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_xtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_xtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_xtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_xtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_xtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_xtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v8b_v8h(dst, src)) } emit_xtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v4h_v4s(dst, src)) } emit_xtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_v2s_v2d(dst, src)) } -inst_xtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_xtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_xtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_xtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_xtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_xtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_xtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v16b_v8h(dst, src)) } emit_xtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v8h_v4s(dst, src)) } emit_xtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_v4s_v2d(dst, src)) } -inst_sqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v8b_v8h(dst, src)) } emit_sqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v4h_v4s(dst, src)) } emit_sqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_v2s_v2d(dst, src)) } -inst_sqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v16b_v8h(dst, src)) } emit_sqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v8h_v4s(dst, src)) } emit_sqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_v4s_v2d(dst, src)) } -inst_uqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_uqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_uqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_uqxtn_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_uqxtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_uqxtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_uqxtn_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v8b_v8h(dst, src)) } emit_uqxtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v4h_v4s(dst, src)) } emit_uqxtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_v2s_v2d(dst, src)) } -inst_uqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_uqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_uqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_uqxtn2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_uqxtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_uqxtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_uqxtn2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v16b_v8h(dst, src)) } emit_uqxtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v8h_v4s(dst, src)) } emit_uqxtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_v4s_v2d(dst, src)) } -inst_sqxtun_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtun_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtun_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtun_v8b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtun_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtun_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtun_v8b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v8b_v8h(dst, src)) } emit_sqxtun_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v4h_v4s(dst, src)) } emit_sqxtun_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_v2s_v2d(dst, src)) } -inst_sqxtun2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}}} } -inst_sqxtun2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_sqxtun2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_sqxtun2_v16b_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_8h(src), {}, {}, {}}} } +inst_sqxtun2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_sqxtun2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_sqxtun2_v16b_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v16b_v8h(dst, src)) } emit_sqxtun2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v8h_v4s(dst, src)) } emit_sqxtun2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_v4s_v2d(dst, src)) } -inst_smull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v8h_v8b_v8b(dst, src, src2)) } emit_smull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v4s_v4h_v4h(dst, src, src2)) } emit_smull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v2d_v2s_v2s(dst, src, src2)) } -inst_smull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v8h_v16b_v16b(dst, src, src2)) } emit_smull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v4s_v8h_v8h(dst, src, src2)) } emit_smull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull2_v2d_v4s_v4s(dst, src, src2)) } -inst_umull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umull_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umull_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v8h_v8b_v8b(dst, src, src2)) } emit_umull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v4s_v4h_v4h(dst, src, src2)) } emit_umull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull_v2d_v2s_v2s(dst, src, src2)) } -inst_umull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umull2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umull2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v8h_v16b_v16b(dst, src, src2)) } emit_umull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v4s_v8h_v8h(dst, src, src2)) } emit_umull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umull2_v2d_v4s_v4s(dst, src, src2)) } -inst_smlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v8h_v8b_v8b(dst, src, src2)) } emit_smlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v4s_v4h_v4h(dst, src, src2)) } emit_smlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal_v2d_v2s_v2s(dst, src, src2)) } -inst_smlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v8h_v16b_v16b(dst, src, src2)) } emit_smlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v4s_v8h_v8h(dst, src, src2)) } emit_smlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_umlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umlal_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umlal_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v8h_v8b_v8b(dst, src, src2)) } emit_umlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v4s_v4h_v4h(dst, src, src2)) } emit_umlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal_v2d_v2s_v2s(dst, src, src2)) } -inst_umlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umlal2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umlal2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v8h_v16b_v16b(dst, src, src2)) } emit_umlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v4s_v8h_v8h(dst, src, src2)) } emit_umlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_smlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_smlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_smlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_smlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_smlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_smlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_smlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v8h_v8b_v8b(dst, src, src2)) } emit_smlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v4s_v4h_v4h(dst, src, src2)) } emit_smlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_smlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_smlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_smlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_smlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_smlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_smlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_smlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v8h_v16b_v16b(dst, src, src2)) } emit_smlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_smlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_umlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_umlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_umlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_umlsl_v8h_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_umlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_umlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_umlsl_v8h_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v8h_v8b_v8b(dst, src, src2)) } emit_umlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v4s_v4h_v4h(dst, src, src2)) } emit_umlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_umlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_umlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_umlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_umlsl2_v8h_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_umlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_umlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_umlsl2_v8h_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v8h_v16b_v16b(dst, src, src2)) } emit_umlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_umlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmull_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmull_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmull_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmull_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmull2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmull2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmull2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmull2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmull2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmlal_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmlal_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmlal_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmlal_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmlal2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmlal2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLAL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmlal2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmlal2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlal2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}}} } +inst_sqdmlsl_v4s_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmlsl_v2d_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } emit_sqdmlsl_v4s_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v4s_v4h_v4h(dst, src, src2)) } emit_sqdmlsl_v2d_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl_v2d_v2s_v2s(dst, src, src2)) } -inst_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMLSL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmlsl2_v4s_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v4s_v8h_v8h(dst, src, src2)) } emit_sqdmlsl2_v2d_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmlsl2_v2d_v4s_v4s(dst, src, src2)) } -inst_sqdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4h_v4h_v4h(dst, src, src2)) } emit_sqdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v8h_v8h_v8h(dst, src, src2)) } emit_sqdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v2s_v2s_v2s(dst, src, src2)) } emit_sqdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqdmulh_v4s_v4s_v4s(dst, src, src2)) } -inst_sqrdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sqrdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sqrdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sqrdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } +inst_sqrdmulh_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sqrdmulh_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sqrdmulh_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sqrdmulh_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SQRDMULH, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sqrdmulh_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4h_v4h_v4h(dst, src, src2)) } emit_sqrdmulh_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v8h_v8h_v8h(dst, src, src2)) } emit_sqrdmulh_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v2s_v2s_v2s(dst, src, src2)) } emit_sqrdmulh_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sqrdmulh_v4s_v4s_v4s(dst, src, src2)) } -inst_sdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_sdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_sdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v2s_v8b_v8b(dst, src, src2)) } emit_sdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_v4s_v16b_v16b(dst, src, src2)) } -inst_udot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_udot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_udot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_udot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_udot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v2s_v8b_v8b(dst, src, src2)) } emit_udot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_v4s_v16b_v16b(dst, src, src2)) } -inst_usdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_usdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_usdot_v2s_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_usdot_v4s_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USDOT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_usdot_v2s_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v2s_v8b_v8b(dst, src, src2)) } emit_usdot_v4s_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usdot_v4s_v16b_v16b(dst, src, src2)) } -inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_fmla_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } -inst_fmla_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } -inst_fmla_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } +inst_fmla_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmla_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_fmla_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm), {}}} } +inst_fmla_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm), {}}} } +inst_fmla_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm), {}}} } emit_fmla_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v4s_v4s_v4s(dst, src, src2)) } emit_fmla_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v2d_v2d_v2d(dst, src, src2)) } emit_fmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } @@ -2317,14 +2317,14 @@ emit_fmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmla_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zh_zh_zh_i(rz, rz2, rz3, imm)) } emit_fmla_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zs_zs_zs_i(rz, rz2, rz3, imm)) } emit_fmla_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmla_zd_zd_zd_i(rz, rz2, rz3, imm)) } -inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } -inst_fmls_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm)}} } -inst_fmls_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm)}} } -inst_fmls_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm)}} } +inst_fmls_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmls_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } +inst_fmls_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_lane_index(imm), {}}} } +inst_fmls_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_lane_index(imm), {}}} } +inst_fmls_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .FMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_lane_index(imm), {}}} } emit_fmls_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v4s_v4s_v4s(dst, src, src2)) } emit_fmls_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v2d_v2d_v2d(dst, src, src2)) } emit_fmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } @@ -2333,108 +2333,108 @@ emit_fmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst emit_fmls_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zh_zh_zh_i(rz, rz2, rz3, imm)) } emit_fmls_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zs_zs_zs_i(rz, rz2, rz3, imm)) } emit_fmls_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_fmls_zd_zd_zd_i(rz, rz2, rz3, imm)) } -inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmulx_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmulx_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmulx_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmulx_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmulx_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmulx_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmulx_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMULX, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmulx_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2s_v2s_v2s(dst, src, src2)) } emit_fmulx_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4s_v4s_v4s(dst, src, src2)) } emit_fmulx_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v2d_v2d_v2d(dst, src, src2)) } emit_fmulx_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v4h_v4h_v4h(dst, src, src2)) } emit_fmulx_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmulx_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmaxp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmaxp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4s_v4s_v4s(dst, src, src2)) } emit_fmaxp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v2d_v2d_v2d(dst, src, src2)) } emit_fmaxp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v4h_v4h_v4h(dst, src, src2)) } emit_fmaxp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxp_v8h_v8h_v8h(dst, src, src2)) } -inst_fminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fminp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fminp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2s_v2s_v2s(dst, src, src2)) } emit_fminp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4s_v4s_v4s(dst, src, src2)) } emit_fminp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v2d_v2d_v2d(dst, src, src2)) } emit_fminp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v4h_v4h_v4h(dst, src, src2)) } emit_fminp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminp_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fmaxnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fmaxnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fmaxnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fmaxnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fmaxnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fmaxnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fmaxnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fmaxnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fmaxnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fmaxnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2s_v2s_v2s(dst, src, src2)) } emit_fmaxnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4s_v4s_v4s(dst, src, src2)) } emit_fmaxnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v2d_v2d_v2d(dst, src, src2)) } emit_fmaxnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v4h_v4h_v4h(dst, src, src2)) } emit_fmaxnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnmp_v8h_v8h_v8h(dst, src, src2)) } -inst_fminnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fminnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fminnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fminnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fminnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_fminnmp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fminnmp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fminnmp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fminnmp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fminnmp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMINNMP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_fminnmp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2s_v2s_v2s(dst, src, src2)) } emit_fminnmp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4s_v4s_v4s(dst, src, src2)) } emit_fminnmp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v2d_v2d_v2d(dst, src, src2)) } emit_fminnmp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v4h_v4h_v4h(dst, src, src2)) } emit_fminnmp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnmp_v8h_v8h_v8h(dst, src, src2)) } -inst_fmaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fmaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fmaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fmaxv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fmaxv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fmaxv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fmaxv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4s(dst, src)) } emit_fmaxv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v4h(dst, src)) } emit_fmaxv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxv_r_v8h(dst, src)) } -inst_fminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fminv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fminv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fminv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fminv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4s(dst, src)) } emit_fminv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v4h(dst, src)) } emit_fminv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminv_r_v8h(dst, src)) } -inst_fmaxnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fmaxnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fmaxnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fmaxnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fmaxnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fmaxnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMAXNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fmaxnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4s(dst, src)) } emit_fmaxnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v4h(dst, src)) } emit_fmaxnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmaxnmv_r_v8h(dst, src)) } -inst_fminnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}}} } -inst_fminnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}}} } -inst_fminnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}}} } +inst_fminnmv_r_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4s(src), {}, {}, {}}} } +inst_fminnmv_r_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_4h(src), {}, {}, {}}} } +inst_fminnmv_r_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FMINNMV, operand_count = 2, length = 4, ops = {op_reg(dst), op_v_8h(src), {}, {}, {}}} } emit_fminnmv_r_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4s(dst, src)) } emit_fminnmv_r_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v4h(dst, src)) } emit_fminnmv_r_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fminnmv_r_v8h(dst, src)) } -inst_frecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frecpe_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frecpe_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frecpe_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frecpe_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frecpe_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frecpe_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRECPE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_frecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2s_v2s(dst, src)) } emit_frecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4s_v4s(dst, src)) } emit_frecpe_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v2d_v2d(dst, src)) } emit_frecpe_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v4h_v4h(dst, src)) } emit_frecpe_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpe_v8h_v8h(dst, src)) } -inst_frsqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_frsqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_frsqrte_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_frsqrte_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_frsqrte_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } +inst_frsqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_frsqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_frsqrte_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_frsqrte_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_frsqrte_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } emit_frsqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2s_v2s(dst, src)) } emit_frsqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4s_v4s(dst, src)) } emit_frsqrte_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v2d_v2d(dst, src)) } emit_frsqrte_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v4h_v4h(dst, src)) } emit_frsqrte_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrte_v8h_v8h(dst, src)) } -inst_frecps_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frecps_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_frecps_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_frecps_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_frecps_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_frecps_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_frecps_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_frecps_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_frecps_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_frecps_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_frecps_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_frecps_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_frecps_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2s_v2s_v2s(dst, src, src2)) } emit_frecps_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v4s_v4s_v4s(dst, src, src2)) } emit_frecps_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frecps_v2d_v2d_v2d(dst, src, src2)) } @@ -2443,14 +2443,14 @@ emit_frecps_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_frecps_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zh_zh_zh(rz, rz2, rz3)) } emit_frecps_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zs_zs_zs(rz, rz2, rz3)) } emit_frecps_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecps_zd_zd_zd(rz, rz2, rz3)) } -inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_frsqrts_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_frsqrts_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_frsqrts_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_frsqrts_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_frsqrts_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_frsqrts_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_frsqrts_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_frsqrts_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_frsqrts_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_frsqrts_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_frsqrts_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRSQRTS, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_frsqrts_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2s_v2s_v2s(dst, src, src2)) } emit_frsqrts_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v4s_v4s_v4s(dst, src, src2)) } emit_frsqrts_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_frsqrts_v2d_v2d_v2d(dst, src, src2)) } @@ -2460,51 +2460,51 @@ emit_frsqrts_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_frsqrts_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zs_zs_zs(rz, rz2, rz3)) } emit_frsqrts_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frsqrts_zd_zd_zd(rz, rz2, rz3)) } inst_frecpx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FRECPX, dst, src) } -inst_frecpx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_frecpx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_frecpx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_frecpx_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_frecpx_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_frecpx_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FRECPX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_frecpx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frecpx_r_r(dst, src)) } emit_frecpx_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zh_p_zh(rz, rz2, rz3)) } emit_frecpx_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zs_p_zs(rz, rz2, rz3)) } emit_frecpx_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_frecpx_zd_p_zd(rz, rz2, rz3)) } -inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_faddp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_faddp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_faddp_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_faddp_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_faddp_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_faddp_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_faddp_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADDP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_faddp_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2s_v2s_v2s(dst, src, src2)) } emit_faddp_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4s_v4s_v4s(dst, src, src2)) } emit_faddp_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v2d_v2d_v2d(dst, src, src2)) } emit_faddp_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v4h_v4h_v4h(dst, src, src2)) } emit_faddp_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_faddp_v8h_v8h_v8h(dst, src, src2)) } -inst_fcvtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_fcvtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_fcvtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcvtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_fcvtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v4s_v4h(dst, src)) } emit_fcvtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl_v2d_v2s(dst, src)) } -inst_fcvtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_fcvtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_fcvtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcvtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_fcvtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v4s_v8h(dst, src)) } emit_fcvtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtl2_v2d_v4s(dst, src)) } -inst_fcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}}} } -inst_fcvtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtn_v4h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtn_v4h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v4h_v4s(dst, src)) } emit_fcvtn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn_v2s_v2d(dst, src)) } -inst_fcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}}} } -inst_fcvtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtn2_v8h_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcvtn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtn2_v8h_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v8h_v4s(dst, src)) } emit_fcvtn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtn2_v4s_v2d(dst, src)) } -inst_fcvtxn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtxn_v2s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtxn_v2s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn_v2s_v2d(dst, src)) } -inst_fcvtxn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}}} } +inst_fcvtxn2_v4s_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCVTXN2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_2d(src), {}, {}, {}}} } emit_fcvtxn2_v4s_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtxn2_v4s_v2d(dst, src)) } -inst_fcmeq_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmeq_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmeq_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmeq_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2s_v2s_v2s(dst, src, src2)) } emit_fcmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v4s_v4s_v4s(dst, src, src2)) } emit_fcmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmeq_v2d_v2d_v2d(dst, src, src2)) } @@ -2513,14 +2513,14 @@ emit_fcmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2s_v2s_v2s(dst, src, src2)) } emit_fcmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v4s_v4s_v4s(dst, src, src2)) } emit_fcmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmge_v2d_v2d_v2d(dst, src, src2)) } @@ -2529,14 +2529,14 @@ emit_fcmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_fcmgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_fcmgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_fcmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_fcmgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_fcmgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_fcmgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2s_v2s_v2s(dst, src, src2)) } emit_fcmgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v4s_v4s_v4s(dst, src, src2)) } emit_fcmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcmgt_v2d_v2d_v2d(dst, src, src2)) } @@ -2545,14 +2545,14 @@ emit_fcmgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmle_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fcmle_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fcmle_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fcmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcmle_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fcmle_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fcmle_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fcmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2s_v2s(dst, src)) } emit_fcmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v4s_v4s(dst, src)) } emit_fcmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmle_v2d_v2d(dst, src)) } @@ -2561,14 +2561,14 @@ emit_fcmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmle_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ph_p_zh(rz, rz2, rz3)) } emit_fcmle_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_ps_p_zs(rz, rz2, rz3)) } emit_fcmle_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmle_pd_p_zd(rz, rz2, rz3)) } -inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } -inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_fcmlt_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_fcmlt_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_fcmlt_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_fcmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_fcmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_fcmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } +inst_fcmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_fcmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_fcmlt_ph_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_fcmlt_ps_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_fcmlt_pd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FCMLT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_fcmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2s_v2s(dst, src)) } emit_fcmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v4s_v4s(dst, src)) } emit_fcmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmlt_v2d_v2d(dst, src)) } @@ -2577,41 +2577,41 @@ emit_fcmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_fcmlt_ph_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ph_p_zh(rz, rz2, rz3)) } emit_fcmlt_ps_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_ps_p_zs(rz, rz2, rz3)) } emit_fcmlt_pd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_fcmlt_pd_p_zd(rz, rz2, rz3)) } -inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_facge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_facge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_facge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_facge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_facge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_facge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_facge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_facge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2s_v2s_v2s(dst, src, src2)) } emit_facge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4s_v4s_v4s(dst, src, src2)) } emit_facge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v2d_v2d_v2d(dst, src, src2)) } emit_facge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v4h_v4h_v4h(dst, src, src2)) } emit_facge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facge_v8h_v8h_v8h(dst, src, src2)) } -inst_facgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_facgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_facgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_facgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_facgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } +inst_facgt_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_facgt_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_facgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_facgt_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_facgt_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FACGT, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } emit_facgt_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2s_v2s_v2s(dst, src, src2)) } emit_facgt_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4s_v4s_v4s(dst, src, src2)) } emit_facgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v2d_v2d_v2d(dst, src, src2)) } emit_facgt_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v4h_v4h_v4h(dst, src, src2)) } emit_facgt_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_facgt_v8h_v8h_v8h(dst, src, src2)) } -inst_cmeq_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmeq_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmeq_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmeq_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmeq_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmeq_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v16b_v16b_v16b(dst, src, src2)) } emit_cmeq_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v8h_v8h_v8h(dst, src, src2)) } emit_cmeq_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v4s_v4s_v4s(dst, src, src2)) } emit_cmeq_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_v2d_v2d_v2d(dst, src, src2)) } -inst_cmge_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmge_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmge_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmge_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmge_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmge_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmge_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmge_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmge_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGE, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmge_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v8b_v8b_v8b(dst, src, src2)) } emit_cmge_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v16b_v16b_v16b(dst, src, src2)) } emit_cmge_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4h_v4h_v4h(dst, src, src2)) } @@ -2619,21 +2619,21 @@ emit_cmge_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmge_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2s_v2s_v2s(dst, src, src2)) } emit_cmge_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v4s_v4s_v4s(dst, src, src2)) } emit_cmge_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmge_v2d_v2d_v2d(dst, src, src2)) } -inst_cmgt_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmgt_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmgt_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmgt_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v16b_v16b_v16b(dst, src, src2)) } emit_cmgt_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_v2d_v2d_v2d(dst, src, src2)) } -inst_cmhi_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmhi_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmhi_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmhi_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmhi_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v16b_v16b_v16b(dst, src, src2)) } emit_cmhi_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_v2d_v2d_v2d(dst, src, src2)) } -inst_cmhs_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmhs_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmhs_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmhs_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmhs_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmhs_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmhs_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmhs_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmhs_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmhs_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmhs_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmhs_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmhs_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmhs_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHS, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmhs_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v8b_v8b_v8b(dst, src, src2)) } emit_cmhs_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v16b_v16b_v16b(dst, src, src2)) } emit_cmhs_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4h_v4h_v4h(dst, src, src2)) } @@ -2641,13 +2641,13 @@ emit_cmhs_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmhs_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2s_v2s_v2s(dst, src, src2)) } emit_cmhs_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v4s_v4s_v4s(dst, src, src2)) } emit_cmhs_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhs_v2d_v2d_v2d(dst, src, src2)) } -inst_cmle_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cmle_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_cmle_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cmle_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cmle_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cmle_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cmle_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cmle_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cmle_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLE, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_cmle_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v8b_v8b(dst, src)) } emit_cmle_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v16b_v16b(dst, src)) } emit_cmle_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4h_v4h(dst, src)) } @@ -2655,13 +2655,13 @@ emit_cmle_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmle_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2s_v2s(dst, src)) } emit_cmle_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v4s_v4s(dst, src)) } emit_cmle_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmle_v2d_v2d(dst, src)) } -inst_cmlt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cmlt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_cmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_cmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_cmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } -inst_cmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}}} } +inst_cmlt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cmlt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cmlt_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_cmlt_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_cmlt_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_cmlt_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } +inst_cmlt_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMLT, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2d(src), {}, {}, {}}} } emit_cmlt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v8b_v8b(dst, src)) } emit_cmlt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v16b_v16b(dst, src)) } emit_cmlt_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4h_v4h(dst, src)) } @@ -2669,13 +2669,13 @@ emit_cmlt_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmlt_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2s_v2s(dst, src)) } emit_cmlt_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v4s_v4s(dst, src)) } emit_cmlt_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmlt_v2d_v2d(dst, src)) } -inst_cmtst_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_cmtst_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_cmtst_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_cmtst_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_cmtst_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_cmtst_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_cmtst_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_cmtst_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_cmtst_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_cmtst_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_cmtst_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_cmtst_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_cmtst_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_cmtst_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMTST, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_cmtst_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v8b_v8b_v8b(dst, src, src2)) } emit_cmtst_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v16b_v16b_v16b(dst, src, src2)) } emit_cmtst_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4h_v4h_v4h(dst, src, src2)) } @@ -2683,27 +2683,27 @@ emit_cmtst_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_cmtst_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2s_v2s_v2s(dst, src, src2)) } emit_cmtst_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v4s_v4s_v4s(dst, src, src2)) } emit_cmtst_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmtst_v2d_v2d_v2d(dst, src, src2)) } -inst_mvn_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_mvn_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } +inst_mvn_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_mvn_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } emit_mvn_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v8b_v8b(dst, src)) } emit_mvn_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_v16b_v16b(dst, src)) } emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } -inst_bit_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bit_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_bit_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_v16b_v16b_v16b(dst, src, src2)) } -inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } +inst_bif_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } emit_bif_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_v16b_v16b_v16b(dst, src, src2)) } -inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_bsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_bsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_v16b_v16b_v16b(dst, src, src2)) } emit_bsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_shl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_shl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v8b_v8b_i(dst, src, imm)) } emit_shl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v16b_v16b_i(dst, src, imm)) } emit_shl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4h_v4h_i(dst, src, imm)) } @@ -2711,13 +2711,13 @@ emit_shl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_shl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2s_v2s_i(dst, src, imm)) } emit_shl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v4s_v4s_i(dst, src, imm)) } emit_shl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shl_v2d_v2d_i(dst, src, imm)) } -inst_sqshl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sqshl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sqshl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sqshl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sqshl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshl_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshl_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshl_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v8b_v8b_i(dst, src, imm)) } emit_sqshl_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v16b_v16b_i(dst, src, imm)) } emit_sqshl_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4h_v4h_i(dst, src, imm)) } @@ -2725,13 +2725,13 @@ emit_sqshl_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqshl_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2s_v2s_i(dst, src, imm)) } emit_sqshl_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v4s_v4s_i(dst, src, imm)) } emit_sqshl_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshl_v2d_v2d_i(dst, src, imm)) } -inst_sqshlu_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshlu_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshlu_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshlu_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHLU, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshlu_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v8b_v8b_i(dst, src, imm)) } emit_sqshlu_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v16b_v16b_i(dst, src, imm)) } emit_sqshlu_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4h_v4h_i(dst, src, imm)) } @@ -2739,13 +2739,13 @@ emit_sqshlu_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqshlu_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2s_v2s_i(dst, src, imm)) } emit_sqshlu_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v4s_v4s_i(dst, src, imm)) } emit_sqshlu_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshlu_v2d_v2d_i(dst, src, imm)) } -inst_srshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_srshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_srshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_srshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_srshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_srshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_srshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_srshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_srshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_srshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_srshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_srshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_srshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_srshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_srshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v8b_v8b_v8b(dst, src, src2)) } emit_srshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v16b_v16b_v16b(dst, src, src2)) } emit_srshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2753,13 +2753,13 @@ emit_srshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_srshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2s_v2s_v2s(dst, src, src2)) } emit_srshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v4s_v4s_v4s(dst, src, src2)) } emit_srshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_srshl_v2d_v2d_v2d(dst, src, src2)) } -inst_urshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_urshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_urshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_urshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_urshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_urshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_urshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_urshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_urshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_urshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_urshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_urshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_urshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_urshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .URSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_urshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v8b_v8b_v8b(dst, src, src2)) } emit_urshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v16b_v16b_v16b(dst, src, src2)) } emit_urshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2767,13 +2767,13 @@ emit_urshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_urshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2s_v2s_v2s(dst, src, src2)) } emit_urshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v4s_v4s_v4s(dst, src, src2)) } emit_urshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_urshl_v2d_v2d_v2d(dst, src, src2)) } -inst_sshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v8b_v8b_i(dst, src, imm)) } emit_sshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v16b_v16b_i(dst, src, imm)) } emit_sshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4h_v4h_i(dst, src, imm)) } @@ -2781,13 +2781,13 @@ emit_sshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2s_v2s_i(dst, src, imm)) } emit_sshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v4s_v4s_i(dst, src, imm)) } emit_sshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshr_v2d_v2d_i(dst, src, imm)) } -inst_ushr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ushr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ushr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ushr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ushr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ushr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ushr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ushr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ushr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ushr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v8b_v8b_i(dst, src, imm)) } emit_ushr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v16b_v16b_i(dst, src, imm)) } emit_ushr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4h_v4h_i(dst, src, imm)) } @@ -2795,13 +2795,13 @@ emit_ushr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ushr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2s_v2s_i(dst, src, imm)) } emit_ushr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v4s_v4s_i(dst, src, imm)) } emit_ushr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushr_v2d_v2d_i(dst, src, imm)) } -inst_ssra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ssra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ssra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ssra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ssra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ssra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ssra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ssra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ssra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ssra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v8b_v8b_i(dst, src, imm)) } emit_ssra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v16b_v16b_i(dst, src, imm)) } emit_ssra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4h_v4h_i(dst, src, imm)) } @@ -2809,13 +2809,13 @@ emit_ssra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ssra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2s_v2s_i(dst, src, imm)) } emit_ssra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v4s_v4s_i(dst, src, imm)) } emit_ssra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ssra_v2d_v2d_i(dst, src, imm)) } -inst_usra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_usra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_usra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_usra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_usra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_usra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_usra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_usra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_usra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_usra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v8b_v8b_i(dst, src, imm)) } emit_usra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v16b_v16b_i(dst, src, imm)) } emit_usra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4h_v4h_i(dst, src, imm)) } @@ -2823,13 +2823,13 @@ emit_usra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_usra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2s_v2s_i(dst, src, imm)) } emit_usra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v4s_v4s_i(dst, src, imm)) } emit_usra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_usra_v2d_v2d_i(dst, src, imm)) } -inst_srshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_srshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_srshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_srshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_srshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_srshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_srshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_srshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_srshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_srshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v8b_v8b_i(dst, src, imm)) } emit_srshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v16b_v16b_i(dst, src, imm)) } emit_srshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4h_v4h_i(dst, src, imm)) } @@ -2837,13 +2837,13 @@ emit_srshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_srshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2s_v2s_i(dst, src, imm)) } emit_srshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v4s_v4s_i(dst, src, imm)) } emit_srshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srshr_v2d_v2d_i(dst, src, imm)) } -inst_urshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_urshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_urshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_urshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_urshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_urshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_urshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_urshr_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_urshr_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSHR, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_urshr_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v8b_v8b_i(dst, src, imm)) } emit_urshr_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v16b_v16b_i(dst, src, imm)) } emit_urshr_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4h_v4h_i(dst, src, imm)) } @@ -2851,13 +2851,13 @@ emit_urshr_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_urshr_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2s_v2s_i(dst, src, imm)) } emit_urshr_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v4s_v4s_i(dst, src, imm)) } emit_urshr_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_urshr_v2d_v2d_i(dst, src, imm)) } -inst_srsra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_srsra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_srsra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_srsra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_srsra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_srsra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_srsra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_srsra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_srsra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_srsra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v8b_v8b_i(dst, src, imm)) } emit_srsra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v16b_v16b_i(dst, src, imm)) } emit_srsra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4h_v4h_i(dst, src, imm)) } @@ -2865,13 +2865,13 @@ emit_srsra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_srsra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2s_v2s_i(dst, src, imm)) } emit_srsra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v4s_v4s_i(dst, src, imm)) } emit_srsra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_srsra_v2d_v2d_i(dst, src, imm)) } -inst_ursra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ursra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ursra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ursra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ursra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_ursra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_ursra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_ursra_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_ursra_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .URSRA, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_ursra_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v8b_v8b_i(dst, src, imm)) } emit_ursra_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v16b_v16b_i(dst, src, imm)) } emit_ursra_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4h_v4h_i(dst, src, imm)) } @@ -2879,13 +2879,13 @@ emit_ursra_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ursra_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2s_v2s_i(dst, src, imm)) } emit_ursra_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v4s_v4s_i(dst, src, imm)) } emit_ursra_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ursra_v2d_v2d_i(dst, src, imm)) } -inst_sshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_sshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_sshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_sshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_sshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_sshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_sshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_sshl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_sshl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_sshl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_sshl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_sshl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_sshl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_sshl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_sshl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v8b_v8b_v8b(dst, src, src2)) } emit_sshl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v16b_v16b_v16b(dst, src, src2)) } emit_sshl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4h_v4h_v4h(dst, src, src2)) } @@ -2893,13 +2893,13 @@ emit_sshl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_sshl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2s_v2s_v2s(dst, src, src2)) } emit_sshl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v4s_v4s_v4s(dst, src, src2)) } emit_sshl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sshl_v2d_v2d_v2d(dst, src, src2)) } -inst_ushl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_ushl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_ushl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_ushl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_ushl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_ushl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_ushl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } +inst_ushl_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_ushl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_ushl_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_ushl_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_ushl_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_ushl_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_ushl_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USHL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_ushl_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v8b_v8b_v8b(dst, src, src2)) } emit_ushl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v16b_v16b_v16b(dst, src, src2)) } emit_ushl_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4h_v4h_v4h(dst, src, src2)) } @@ -2907,13 +2907,13 @@ emit_ushl_v8h_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Inst emit_ushl_v2s_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2s_v2s_v2s(dst, src, src2)) } emit_ushl_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v4s_v4s_v4s(dst, src, src2)) } emit_ushl_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ushl_v2d_v2d_v2d(dst, src, src2)) } -inst_sli_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sli_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sli_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sli_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sli_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sli_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sli_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sli_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sli_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SLI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sli_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v8b_v8b_i(dst, src, imm)) } emit_sli_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v16b_v16b_i(dst, src, imm)) } emit_sli_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4h_v4h_i(dst, src, imm)) } @@ -2921,13 +2921,13 @@ emit_sli_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sli_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2s_v2s_i(dst, src, imm)) } emit_sli_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v4s_v4s_i(dst, src, imm)) } emit_sli_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sli_v2d_v2d_i(dst, src, imm)) } -inst_sri_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sri_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sri_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sri_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sri_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}}} } -inst_sri_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sri_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sri_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v2s_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sri_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRI, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sri_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v8b_v8b_i(dst, src, imm)) } emit_sri_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v16b_v16b_i(dst, src, imm)) } emit_sri_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4h_v4h_i(dst, src, imm)) } @@ -2935,168 +2935,168 @@ emit_sri_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_sri_v2s_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2s_v2s_i(dst, src, imm)) } emit_sri_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v4s_v4s_i(dst, src, imm)) } emit_sri_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sri_v2d_v2d_i(dst, src, imm)) } -inst_sshll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_sshll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_sshll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_sshll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_sshll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_sshll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } emit_sshll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v8h_v8b_i(dst, src, imm)) } emit_sshll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v4s_v4h_i(dst, src, imm)) } emit_sshll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll_v2d_v2s_i(dst, src, imm)) } -inst_sshll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_sshll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sshll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_sshll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_sshll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sshll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SSHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } emit_sshll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v8h_v16b_i(dst, src, imm)) } emit_sshll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v4s_v8h_i(dst, src, imm)) } emit_sshll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sshll2_v2d_v4s_i(dst, src, imm)) } -inst_ushll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}}} } -inst_ushll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}}} } -inst_ushll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}}} } +inst_ushll_v8h_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8b(src), op_imm(imm, 4), {}, {}}} } +inst_ushll_v4s_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4h(src), op_imm(imm, 4), {}, {}}} } +inst_ushll_v2d_v2s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2s(src), op_imm(imm, 4), {}, {}}} } emit_ushll_v8h_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v8h_v8b_i(dst, src, imm)) } emit_ushll_v4s_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v4s_v4h_i(dst, src, imm)) } emit_ushll_v2d_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll_v2d_v2s_i(dst, src, imm)) } -inst_ushll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}}} } -inst_ushll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_ushll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}}} } +inst_ushll2_v8h_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_16b(src), op_imm(imm, 4), {}, {}}} } +inst_ushll2_v4s_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_ushll2_v2d_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .USHLL2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } emit_ushll2_v8h_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v8h_v16b_i(dst, src, imm)) } emit_ushll2_v4s_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v4s_v8h_i(dst, src, imm)) } emit_ushll2_v2d_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ushll2_v2d_v4s_i(dst, src, imm)) } -inst_sxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } -inst_sxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_sxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_sxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}, {}}} } +inst_sxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_sxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_sxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v8h_v8b(dst, src)) } emit_sxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v4s_v4h(dst, src)) } emit_sxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl_v2d_v2s(dst, src)) } -inst_sxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_sxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_sxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_sxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_sxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_sxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_sxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v8h_v16b(dst, src)) } emit_sxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v4s_v8h(dst, src)) } emit_sxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtl2_v2d_v4s(dst, src)) } -inst_uxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}}} } -inst_uxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}}} } -inst_uxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}}} } +inst_uxtl_v8h_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8b(src), {}, {}, {}}} } +inst_uxtl_v4s_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4h(src), {}, {}, {}}} } +inst_uxtl_v2d_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_2s(src), {}, {}, {}}} } emit_uxtl_v8h_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v8h_v8b(dst, src)) } emit_uxtl_v4s_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v4s_v4h(dst, src)) } emit_uxtl_v2d_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl_v2d_v2s(dst, src)) } -inst_uxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}}} } -inst_uxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}}} } -inst_uxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}}} } +inst_uxtl2_v8h_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_16b(src), {}, {}, {}}} } +inst_uxtl2_v4s_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_8h(src), {}, {}, {}}} } +inst_uxtl2_v2d_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTL2, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_v_4s(src), {}, {}, {}}} } emit_uxtl2_v8h_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v8h_v16b(dst, src)) } emit_uxtl2_v4s_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v4s_v8h(dst, src)) } emit_uxtl2_v2d_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtl2_v2d_v4s(dst, src)) } -inst_shrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v8b_v8h_i(dst, src, imm)) } emit_shrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v4h_v4s_i(dst, src, imm)) } emit_shrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn_v2s_v2d_i(dst, src, imm)) } -inst_shrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_shrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_shrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_shrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_shrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_shrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_shrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v16b_v8h_i(dst, src, imm)) } emit_shrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v8h_v4s_i(dst, src, imm)) } emit_shrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_shrn2_v4s_v2d_i(dst, src, imm)) } -inst_rshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_rshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_rshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_rshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_rshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v8b_v8h_i(dst, src, imm)) } emit_rshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v4h_v4s_i(dst, src, imm)) } emit_rshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn_v2s_v2d_i(dst, src, imm)) } -inst_rshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_rshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_rshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_rshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_rshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_rshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v16b_v8h_i(dst, src, imm)) } emit_rshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v8h_v4s_i(dst, src, imm)) } emit_rshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v8b_v8h_i(dst, src, imm)) } emit_sqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v4h_v4s_i(dst, src, imm)) } emit_sqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn_v2s_v2d_i(dst, src, imm)) } -inst_sqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v16b_v8h_i(dst, src, imm)) } emit_sqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v8h_v4s_i(dst, src, imm)) } emit_sqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrn2_v4s_v2d_i(dst, src, imm)) } -inst_uqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v8b_v8h_i(dst, src, imm)) } emit_uqshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v4h_v4s_i(dst, src, imm)) } emit_uqshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn_v2s_v2d_i(dst, src, imm)) } -inst_uqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v16b_v8h_i(dst, src, imm)) } emit_uqshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v8h_v4s_i(dst, src, imm)) } emit_uqshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v8b_v8h_i(dst, src, imm)) } emit_sqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v4h_v4s_i(dst, src, imm)) } emit_sqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn_v2s_v2d_i(dst, src, imm)) } -inst_sqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v16b_v8h_i(dst, src, imm)) } emit_sqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v8h_v4s_i(dst, src, imm)) } emit_sqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrn2_v4s_v2d_i(dst, src, imm)) } -inst_uqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqrshrn_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqrshrn_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v8b_v8h_i(dst, src, imm)) } emit_uqrshrn_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v4h_v4s_i(dst, src, imm)) } emit_uqrshrn_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn_v2s_v2d_i(dst, src, imm)) } -inst_uqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_uqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_uqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_uqrshrn2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_uqrshrn2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .UQRSHRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_uqrshrn2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v16b_v8h_i(dst, src, imm)) } emit_uqrshrn2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v8h_v4s_i(dst, src, imm)) } emit_uqrshrn2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_uqrshrn2_v4s_v2d_i(dst, src, imm)) } -inst_sqshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v8b_v8h_i(dst, src, imm)) } emit_sqshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v4h_v4s_i(dst, src, imm)) } emit_sqshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun_v2s_v2d_i(dst, src, imm)) } -inst_sqshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v16b_v8h_i(dst, src, imm)) } emit_sqshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v8h_v4s_i(dst, src, imm)) } emit_sqshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqshrun2_v4s_v2d_i(dst, src, imm)) } -inst_sqrshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrun_v8b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun_v4h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun_v2s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrun_v8b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v8b_v8h_i(dst, src, imm)) } emit_sqrshrun_v4h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v4h_v4s_i(dst, src, imm)) } emit_sqrshrun_v2s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun_v2s_v2d_i(dst, src, imm)) } -inst_sqrshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}}} } -inst_sqrshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}}} } -inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}}} } +inst_sqrshrun2_v16b_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_8h(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun2_v8h_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_4s(src), op_imm(imm, 4), {}, {}}} } +inst_sqrshrun2_v4s_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SQRSHRUN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_2d(src), op_imm(imm, 4), {}, {}}} } emit_sqrshrun2_v16b_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v16b_v8h_i(dst, src, imm)) } emit_sqrshrun2_v8h_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v8h_v4s_i(dst, src, imm)) } emit_sqrshrun2_v4s_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sqrshrun2_v4s_v2d_i(dst, src, imm)) } -inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } -inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_lane_index(imm), {}}} } -inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } -inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_lane_index(imm), {}}} } -inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } -inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_lane_index(imm), {}}} } -inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_lane_index(imm), {}}} } -inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}}} } -inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}}} } -inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}}} } -inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_reg(src), {}, {}}} } -inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}}} } -inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}}} } -inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}}} } -inst_dup_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -inst_dup_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } -inst_dup_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } -inst_dup_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } +inst_dup_v8b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_elem_b(src), op_lane_index(imm), {}, {}}} } +inst_dup_v16b_veb_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_elem_b(src), op_lane_index(imm), {}, {}}} } +inst_dup_v4h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_elem_h(src), op_lane_index(imm), {}, {}}} } +inst_dup_v8h_veh_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_elem_h(src), op_lane_index(imm), {}, {}}} } +inst_dup_v2s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_elem_s(src), op_lane_index(imm), {}, {}}} } +inst_dup_v4s_ves_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_elem_s(src), op_lane_index(imm), {}, {}}} } +inst_dup_v2d_ved_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_elem_d(src), op_lane_index(imm), {}, {}}} } +inst_dup_v8b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v16b_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v4h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v8h_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v2s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v4s_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_reg(src), {}, {}, {}}} } +inst_dup_v2d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_reg(src), {}, {}, {}}} } +inst_dup_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}, {}}} } +inst_dup_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .DUP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}, {}}} } emit_dup_v8b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v8b_veb_i(dst, src, imm)) } emit_dup_v16b_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v16b_veb_i(dst, src, imm)) } emit_dup_v4h_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_dup_v4h_veh_i(dst, src, imm)) } @@ -3115,14 +3115,14 @@ emit_dup_zb_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_dup_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zh_r(rz, src)) } emit_dup_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zs_r(rz, src)) } emit_dup_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_dup_zd_r(rz, src)) } -inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2)}} } -inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2)}} } -inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2)}} } -inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_v_elem_d(src), op_lane_index(imm2)}} } -inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_reg(src), {}}} } -inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_reg(src), {}}} } +inst_ins_veb_i_veb_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_v_elem_b(src), op_lane_index(imm2), {}}} } +inst_ins_veh_i_veh_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_v_elem_h(src), op_lane_index(imm2), {}}} } +inst_ins_ves_i_ves_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_v_elem_s(src), op_lane_index(imm2), {}}} } +inst_ins_ved_i_ved_i :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 4, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_v_elem_d(src), op_lane_index(imm2), {}}} } +inst_ins_veb_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_b(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_veh_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_h(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_ves_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_s(dst), op_lane_index(imm), op_reg(src), {}, {}}} } +inst_ins_ved_i_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INS, operand_count = 3, length = 4, ops = {op_v_elem_d(dst), op_lane_index(imm), op_reg(src), {}, {}}} } emit_ins_veb_i_veb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veb_i_veb_i(dst, imm, src, imm2)) } emit_ins_veh_i_veh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_veh_i_veh_i(dst, imm, src, imm2)) } emit_ins_ves_i_ves_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, imm2: i64) { append(instructions, inst_ins_ves_i_ves_i(dst, imm, src, imm2)) } @@ -3131,14 +3131,14 @@ emit_ins_veb_i_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_ins_veh_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_veh_i_r(dst, imm, src)) } emit_ins_ves_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ves_i_r(dst, imm, src)) } emit_ins_ved_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ins_ved_i_r(dst, imm, src)) } -inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_mov_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } -inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -inst_mov_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_mov_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_mov_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_mov_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_mov_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_mov_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_mov_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } +inst_mov_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } +inst_mov_pb_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV, dst, src) } inst_mov_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV, dst, imm) } emit_mov_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v8b_v8b(dst, src)) } @@ -3151,42 +3151,42 @@ emit_mov_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Inst emit_mov_pb_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_mov_pb_p(rz, rz2)) } emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } emit_mov_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_i(dst, imm)) } -inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4)}} } -inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4)}} } -inst_ext_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4)}} } +inst_ext_v8b_v8b_v8b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), op_imm(imm, 4), {}}} } +inst_ext_v16b_v16b_v16b_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), op_imm(imm, 4), {}}} } +inst_ext_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4), {}}} } emit_ext_v8b_v8b_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v8b_v8b_v8b_i(dst, src, src2, imm)) } emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_ext_v16b_v16b_v16b_i(dst, src, src2, imm)) } emit_ext_zb_zb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_zb_zb_zb_i(rz, rz2, rz3, imm)) } -inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } -inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } +inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } +inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } emit_tbl_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zb_zb(rz, rz2, rz3)) } emit_tbl_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zh_zh_zh(rz, rz2, rz3)) } emit_tbl_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zs_zs_zs(rz, rz2, rz3)) } emit_tbl_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zd_zd_zd(rz, rz2, rz3)) } -inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}}} } -inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}}} } -inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } +inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } +inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_tbx_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v8b_v16b_v8b(dst, src, src2)) } emit_tbx_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbx_v16b_v16b_v16b(dst, src, src2)) } emit_tbx_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbx_zb_zb_zb(rz, rz2, rz3)) } -inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_zip1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_zip1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_zip1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_zip1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_zip1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_zip1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_zip1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_zip1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_zip1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_zip1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_zip1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v8b_v8b_v8b(dst, src, src2)) } emit_zip1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v16b_v16b_v16b(dst, src, src2)) } emit_zip1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip1_v4h_v4h_v4h(dst, src, src2)) } @@ -3199,18 +3199,18 @@ emit_zip1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zs_zs_zs(rz, rz2, rz3)) } emit_zip1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_zd_zd_zd(rz, rz2, rz3)) } emit_zip1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip1_pb_pb_pb(rz, rz2, rz3)) } -inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_zip2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_zip2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_zip2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_zip2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_zip2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_zip2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_zip2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_zip2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_zip2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_zip2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_zip2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_zip2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_zip2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v8b_v8b_v8b(dst, src, src2)) } emit_zip2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v16b_v16b_v16b(dst, src, src2)) } emit_zip2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_zip2_v4h_v4h_v4h(dst, src, src2)) } @@ -3223,18 +3223,18 @@ emit_zip2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_zip2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zs_zs_zs(rz, rz2, rz3)) } emit_zip2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_zd_zd_zd(rz, rz2, rz3)) } emit_zip2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip2_pb_pb_pb(rz, rz2, rz3)) } -inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uzp1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uzp1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uzp1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uzp1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uzp1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uzp1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uzp1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uzp1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uzp1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_uzp1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_uzp1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v8b_v8b_v8b(dst, src, src2)) } emit_uzp1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v16b_v16b_v16b(dst, src, src2)) } emit_uzp1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp1_v4h_v4h_v4h(dst, src, src2)) } @@ -3247,18 +3247,18 @@ emit_uzp1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zs_zs_zs(rz, rz2, rz3)) } emit_uzp1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_zd_zd_zd(rz, rz2, rz3)) } emit_uzp1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp1_pb_pb_pb(rz, rz2, rz3)) } -inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_uzp2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_uzp2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_uzp2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_uzp2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_uzp2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_uzp2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_uzp2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_uzp2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_uzp2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_uzp2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_uzp2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_uzp2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_uzp2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v8b_v8b_v8b(dst, src, src2)) } emit_uzp2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v16b_v16b_v16b(dst, src, src2)) } emit_uzp2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uzp2_v4h_v4h_v4h(dst, src, src2)) } @@ -3271,18 +3271,18 @@ emit_uzp2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_uzp2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zs_zs_zs(rz, rz2, rz3)) } emit_uzp2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_zd_zd_zd(rz, rz2, rz3)) } emit_uzp2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp2_pb_pb_pb(rz, rz2, rz3)) } -inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn1_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_trn1_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_trn1_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_trn1_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_trn1_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_trn1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_trn1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_trn1_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_trn1_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_trn1_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_trn1_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_trn1_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN1, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_trn1_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v8b_v8b_v8b(dst, src, src2)) } emit_trn1_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v16b_v16b_v16b(dst, src, src2)) } emit_trn1_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn1_v4h_v4h_v4h(dst, src, src2)) } @@ -3295,18 +3295,18 @@ emit_trn1_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn1_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zs_zs_zs(rz, rz2, rz3)) } emit_trn1_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_zd_zd_zd(rz, rz2, rz3)) } emit_trn1_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn1_pb_pb_pb(rz, rz2, rz3)) } -inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}}} } -inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}}} } -inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}}} } -inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}}} } -inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}}} } -inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}}} } -inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}}} } -inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } -inst_trn2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_trn2_v8b_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_8b(src), op_v_8b(src2), {}, {}}} } +inst_trn2_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_16b(src), op_v_16b(src2), {}, {}}} } +inst_trn2_v4h_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), {}, {}}} } +inst_trn2_v8h_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), {}, {}}} } +inst_trn2_v2s_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2s(dst), op_v_2s(src), op_v_2s(src2), {}, {}}} } +inst_trn2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } +inst_trn2_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } +inst_trn2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_trn2_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_trn2_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_trn2_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_trn2_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TRN2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_trn2_v8b_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v8b_v8b_v8b(dst, src, src2)) } emit_trn2_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v16b_v16b_v16b(dst, src, src2)) } emit_trn2_v4h_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_trn2_v4h_v4h_v4h(dst, src, src2)) } @@ -3319,51 +3319,51 @@ emit_trn2_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Inst emit_trn2_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zs_zs_zs(rz, rz2, rz3)) } emit_trn2_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_zd_zd_zd(rz, rz2, rz3)) } emit_trn2_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_trn2_pb_pb_pb(rz, rz2, rz3)) } -inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_not_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_not_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_not_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_not_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .NOT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_not_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v8b_v8b(dst, src)) } emit_not_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v16b_v16b(dst, src)) } emit_not_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_not_pb_p_pb(rz, rz2, rz3)) } -inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}}} } -inst_rev64_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}}} } -inst_rev64_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_rev64_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_rev64_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_rev64_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_rev64_v4h_v4h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_v_4h(src), {}, {}, {}}} } +inst_rev64_v8h_v8h :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_v_8h(src), {}, {}, {}}} } +inst_rev64_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_rev64_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV64, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_rev64_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8b_v8b(dst, src)) } emit_rev64_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v16b_v16b(dst, src)) } emit_rev64_v4h_v4h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4h_v4h(dst, src)) } emit_rev64_v8h_v8h :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v8h_v8h(dst, src)) } emit_rev64_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v2s_v2s(dst, src)) } emit_rev64_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev64_v4s_v4s(dst, src)) } -inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}}} } -inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}}} } -inst_cnt_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } -inst_cnt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } -inst_cnt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_cnt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_cnt_v8b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_v_8b(src), {}, {}, {}}} } +inst_cnt_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_v_16b(src), {}, {}, {}}} } +inst_cnt_zb_p_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}, {}}} } +inst_cnt_zh_p_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}, {}}} } +inst_cnt_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_cnt_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .CNT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_cnt_v8b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v8b_v8b(dst, src)) } emit_cnt_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cnt_v16b_v16b(dst, src)) } emit_cnt_zb_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zb_p_zb(rz, rz2, rz3)) } emit_cnt_zh_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zh_p_zh(rz, rz2, rz3)) } emit_cnt_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zs_p_zs(rz, rz2, rz3)) } emit_cnt_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_cnt_zd_p_zd(rz, rz2, rz3)) } -inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_urecpe_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_urecpe_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URECPE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_urecpe_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v2s_v2s(dst, src)) } emit_urecpe_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_urecpe_v4s_v4s(dst, src)) } -inst_ursqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}}} } -inst_ursqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}}} } +inst_ursqrte_v2s_v2s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_v_2s(src), {}, {}, {}}} } +inst_ursqrte_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .URSQRTE, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_v_4s(src), {}, {}, {}}} } emit_ursqrte_v2s_v2s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v2s_v2s(dst, src)) } emit_ursqrte_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ursqrte_v4s_v4s(dst, src)) } -inst_movi_v8b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v16b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } -inst_movi_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}}} } +inst_movi_v8b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8b(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v16b_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_16b(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_movi_v2d_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVI, operand_count = 2, length = 4, ops = {op_v_2d(dst), op_imm(imm, 1), {}, {}, {}}} } emit_movi_v8b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v8b_i(dst, imm)) } emit_movi_v16b_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v16b_i(dst, imm)) } emit_movi_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4h_i(dst, imm)) } @@ -3371,22 +3371,22 @@ emit_movi_v8h_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_movi_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2s_i(dst, imm)) } emit_movi_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v4s_i(dst, imm)) } emit_movi_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movi_v2d_i(dst, imm)) } -inst_mvni_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}}} } -inst_mvni_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}}} } +inst_mvni_v4h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v8h_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_8h(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v2s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_2s(dst), op_imm(imm, 1), {}, {}, {}}} } +inst_mvni_v4s_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVNI, operand_count = 2, length = 4, ops = {op_v_4s(dst), op_imm(imm, 1), {}, {}, {}}} } emit_mvni_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4h_i(dst, imm)) } emit_mvni_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v8h_i(dst, imm)) } emit_mvni_v2s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v2s_i(dst, imm)) } emit_mvni_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvni_v4s_i(dst, imm)) } -inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } -inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } -inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } -inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } -inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}, {}}} } +inst_ld1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v16b_m(dst, mem)) } emit_ld1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v8h_m(dst, mem)) } emit_ld1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_v4s_m(dst, mem)) } @@ -3395,44 +3395,44 @@ emit_ld1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_ld1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_veh_i_m(dst, imm, mem)) } emit_ld1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ves_i_m(dst, imm, mem)) } emit_ld1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld1_ved_i_m(dst, imm, mem)) } -inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } -inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } +inst_ld2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2_v16b_m(dst, mem)) } emit_ld2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veb_i_m(dst, imm, mem)) } emit_ld2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_veh_i_m(dst, imm, mem)) } emit_ld2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ves_i_m(dst, imm, mem)) } emit_ld2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld2_ved_i_m(dst, imm, mem)) } -inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } -inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } +inst_ld3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3_v16b_m(dst, mem)) } emit_ld3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veb_i_m(dst, imm, mem)) } emit_ld3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_veh_i_m(dst, imm, mem)) } emit_ld3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ves_i_m(dst, imm, mem)) } emit_ld3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld3_ved_i_m(dst, imm, mem)) } -inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } -inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_ld4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } +inst_ld4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_ld4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_ld4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4_v16b_m(dst, mem)) } emit_ld4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veb_i_m(dst, imm, mem)) } emit_ld4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_veh_i_m(dst, imm, mem)) } emit_ld4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ves_i_m(dst, imm, mem)) } emit_ld4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_ld4_ved_i_m(dst, imm, mem)) } -inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } -inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}}} } -inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}}} } -inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}}} } -inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}}} } -inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}}} } +inst_st1_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v8h_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_8H, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v4s_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_4S, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_v2d_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_2D, 1), op_mem(mem), {}, {}, {}}} } +inst_st1_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st1_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 1), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st1_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v16b_m(dst, mem)) } emit_st1_v8h_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v8h_m(dst, mem)) } emit_st1_v4s_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_v4s_m(dst, mem)) } @@ -3441,481 +3441,481 @@ emit_st1_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Inst emit_st1_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_veh_i_m(dst, imm, mem)) } emit_st1_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ves_i_m(dst, imm, mem)) } emit_st1_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st1_ved_i_m(dst, imm, mem)) } -inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } -inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}}} } -inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}}} } +inst_st2_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } +inst_st2_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st2_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST2, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 2), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st2_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2_v16b_m(dst, mem)) } emit_st2_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veb_i_m(dst, imm, mem)) } emit_st2_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_veh_i_m(dst, imm, mem)) } emit_st2_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ves_i_m(dst, imm, mem)) } emit_st2_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st2_ved_i_m(dst, imm, mem)) } -inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } -inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}}} } -inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}}} } +inst_st3_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } +inst_st3_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st3_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST3, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 3), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st3_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st3_v16b_m(dst, mem)) } emit_st3_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veb_i_m(dst, imm, mem)) } emit_st3_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_veh_i_m(dst, imm, mem)) } emit_st3_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ves_i_m(dst, imm, mem)) } emit_st3_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st3_ved_i_m(dst, imm, mem)) } -inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } -inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}}} } -inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}}} } +inst_st4_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } +inst_st4_veb_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_B, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_veh_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_H, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_ves_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_S, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } +inst_st4_ved_i_m :: #force_inline proc "contextless" (dst: Register, imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST4, operand_count = 3, length = 4, ops = {op_v_list(dst, VSHAPE_ELEM_D, 4), op_lane_index(imm), op_mem(mem), {}, {}}} } emit_st4_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st4_v16b_m(dst, mem)) } emit_st4_veb_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veb_i_m(dst, imm, mem)) } emit_st4_veh_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_veh_i_m(dst, imm, mem)) } emit_st4_ves_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ves_i_m(dst, imm, mem)) } emit_st4_ved_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, mem: Memory) { append(instructions, inst_st4_ved_i_m(dst, imm, mem)) } -inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}}} } +inst_ld1r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 1), op_mem(mem), {}, {}, {}}} } emit_ld1r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1r_v16b_m(dst, mem)) } -inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}}} } +inst_ld2r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD2R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 2), op_mem(mem), {}, {}, {}}} } emit_ld2r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld2r_v16b_m(dst, mem)) } -inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}}} } +inst_ld3r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD3R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 3), op_mem(mem), {}, {}, {}}} } emit_ld3r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld3r_v16b_m(dst, mem)) } -inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}}} } +inst_ld4r_v16b_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD4R, operand_count = 2, length = 4, ops = {op_v_list(dst, VSHAPE_16B, 4), op_mem(mem), {}, {}, {}}} } emit_ld4r_v16b_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld4r_v16b_m(dst, mem)) } -inst_subr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_subr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_subr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_subr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_subr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_subr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_subr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_subr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_subr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_subr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_subr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_subr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_subr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_asrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_asrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_asrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_asrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_asrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_asrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_asrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_asrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ASRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_asrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_asrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_asrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_asrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_asrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_lslr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lslr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lslr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lslr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lslr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lslr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lslr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lslr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSLR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_lslr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_lslr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_lslr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_lslr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lslr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_lsrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_lsrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_lsrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_lsrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_lsrr_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_lsrr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_lsrr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_lsrr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .LSRR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_lsrr_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_lsrr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_lsrr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_lsrr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_lsrr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_ftsmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_ftsmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_ftsmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_ftsmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_ftsmul_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_ftsmul_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FTSMUL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_ftsmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zh_zh_zh(rz, rz2, rz3)) } emit_ftsmul_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zs_zs_zs(rz, rz2, rz3)) } emit_ftsmul_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_ftsmul_zd_zd_zd(rz, rz2, rz3)) } -inst_fsubr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fsubr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fsubr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fsubr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fsubr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fsubr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FSUBR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fsubr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fsubr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fsubr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fsubr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fdivr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fdivr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fdivr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fdivr_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fdivr_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fdivr_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FDIVR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fdivr_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fdivr_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fdivr_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fdivr_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fnmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fnmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fnmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fnmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fnmla_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fnmla_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLA, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fnmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmla_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmla_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmla_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fnmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fnmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fnmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fnmls_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fnmls_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FNMLS, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fnmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fnmls_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fnmls_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fnmls_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_nand_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nand_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NAND, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nand_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nand_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nor_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NOR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nor_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nor_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_sel_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_sel_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sel_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orrs_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orrs_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORRS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orrs_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orrs_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_eors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_eors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .EORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_eors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_eors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nands_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NANDS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nands_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nands_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_nors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_nors_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NORS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_nors_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nors_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_orns_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_orns_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .ORNS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_orns_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_orns_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_movs_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_movs_pb_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .MOVS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_movs_pb_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_movs_pb_p_p(rz, rz2, rz3)) } -inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_ptrue_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}, {}}} } emit_ptrue_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrue_pb_i(rz, imm)) } -inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}, {}}} } emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } -inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } -inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } -inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } -inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkb_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkb_pb_p_pb(rz, rz2, rz3)) } -inst_brkas_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkas_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKAS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkas_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkas_pb_p_pb(rz, rz2, rz3)) } -inst_brkbs_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +inst_brkbs_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKBS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}, {}}} } emit_brkbs_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brkbs_pb_p_pb(rz, rz2, rz3)) } -inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkpa_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPA, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkpa_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpa_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkpb_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKPB, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkpb_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkpb_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_brkn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +inst_brkn_pb_p_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BRKN, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF))), {}}} } emit_brkn_pb_p_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_brkn_pb_p_pb_pb(rz, rz2, rz3, rz4)) } -inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_rdffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .RDFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_rdffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_rdffr_pb(rz)) } -inst_wrffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +inst_wrffr_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .WRFFR, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}, {}}} } emit_wrffr_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_wrffr_pb(rz)) } inst_setffr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SETFFR) } emit_setffr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_setffr_none()) } -inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpeq_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpeq_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpeq_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpeq_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpeq_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpeq_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpeq_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpeq_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpeq_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpne_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpne_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpne_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpge_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpge_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpge_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpge_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpge_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpge_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpge_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpge_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpge_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpge_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpgt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpgt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpgt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpgt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpgt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpgt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpgt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpgt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpgt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpgt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmple_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmple_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmple_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmple_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmple_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmple_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmple_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmple_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmple_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmple_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmple_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmple_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmple_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmplt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmplt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmplt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmplt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmplt_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmplt_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmplt_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmplt_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmplt_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmplt_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmplt_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmplt_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplt_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmphi_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmphi_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmphi_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmphi_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmphi_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmphi_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmphi_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmphi_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmphi_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmphi_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmphi_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmphi_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphi_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmphs_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmphs_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmphs_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmphs_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmphs_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmphs_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmphs_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmphs_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmphs_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmphs_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmphs_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmphs_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmphs_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmplo_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmplo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmplo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmplo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmplo_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmplo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmplo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmplo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmplo_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmplo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmplo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmplo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmplo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_cmpls_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_cmpls_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_cmpls_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_cmpls_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_cmpls_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_cmpls_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_cmpls_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_cmpls_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .CMPLS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_cmpls_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_cmpls_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_cmpls_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_cmpls_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_cmpls_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmne_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmne_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmne_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmne_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmne_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmne_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmne_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_fcmuo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_fcmuo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_fcmuo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_fcmuo_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_fcmuo_ps_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_fcmuo_pd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FCMUO, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_fcmuo_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ph_p_zh_zh(rz, rz2, rz3, rz4)) } emit_fcmuo_ps_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_ps_p_zs_zs(rz, rz2, rz3, rz4)) } emit_fcmuo_pd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fcmuo_pd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_insr_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } -inst_insr_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}}} } -inst_insr_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}}} } -inst_insr_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}}} } +inst_insr_zb_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zh_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zs_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(src), {}, {}, {}}} } +inst_insr_zd_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .INSR, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(src), {}, {}, {}}} } emit_insr_zb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zb_r(rz, src)) } emit_insr_zh_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zh_r(rz, src)) } emit_insr_zs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zs_r(rz, src)) } emit_insr_zd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_insr_zd_r(rz, src)) } -inst_cpy_zb_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zh_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zs_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } -inst_cpy_zd_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}}} } +inst_cpy_zb_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zh_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zs_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } +inst_cpy_zd_p_r :: #force_inline proc "contextless" (rz: u8, rz2: u8, src: Register) -> Instruction { return Instruction{mnemonic = .CPY, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(src), {}, {}}} } emit_cpy_zb_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zb_p_r(rz, rz2, src)) } emit_cpy_zh_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zh_p_r(rz, rz2, src)) } emit_cpy_zs_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zs_p_r(rz, rz2, src)) } emit_cpy_zd_p_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, src: Register) { append(instructions, inst_cpy_zd_p_r(rz, rz2, src)) } -inst_compact_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } -inst_compact_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}}} } +inst_compact_zs_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } +inst_compact_zd_p_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .COMPACT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), {}, {}}} } emit_compact_zs_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zs_p_zs(rz, rz2, rz3)) } emit_compact_zd_p_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_compact_zd_p_zd(rz, rz2, rz3)) } -inst_ld1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1b_zpb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1b_zqb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1b_zpb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1b_zqb_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zb_p_m(rz, rz2, mem)) } emit_ld1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zs_p_m(rz, rz2, mem)) } emit_ld1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zd_p_m(rz, rz2, mem)) } emit_ld1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1b_i_p_m(imm, rz1, mem)) } emit_ld1b_zpb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zpb_pnz_m(rz, rz2, mem)) } emit_ld1b_zqb_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1b_zqb_pnz_m(rz, rz2, mem)) } -inst_ld1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1h_zph_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1h_zqh_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1h_zph_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1h_zqh_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zh_p_m(rz, rz2, mem)) } emit_ld1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zs_p_m(rz, rz2, mem)) } emit_ld1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zd_p_m(rz, rz2, mem)) } emit_ld1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1h_i_p_m(imm, rz1, mem)) } emit_ld1h_zph_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zph_pnz_m(rz, rz2, mem)) } emit_ld1h_zqh_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1h_zqh_pnz_m(rz, rz2, mem)) } -inst_ld1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1w_zps_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1w_zqs_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1w_zps_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1w_zqs_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zs_p_m(rz, rz2, mem)) } emit_ld1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zd_p_m(rz, rz2, mem)) } emit_ld1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1w_i_p_m(imm, rz1, mem)) } emit_ld1w_zps_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zps_pnz_m(rz, rz2, mem)) } emit_ld1w_zqs_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1w_zqs_pnz_m(rz, rz2, mem)) } -inst_ld1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_ld1d_zpd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_ld1d_zqd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_ld1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1d_zpd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_ld1d_zqd_pnz_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_ld1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zd_p_m(rz, rz2, mem)) } emit_ld1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1d_i_p_m(imm, rz1, mem)) } emit_ld1d_zpd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zpd_pnz_m(rz, rz2, mem)) } emit_ld1d_zqd_pnz_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1d_zqd_pnz_m(rz, rz2, mem)) } -inst_ld1sb_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sb_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sb_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sb_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sb_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SB, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sb_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zh_p_m(rz, rz2, mem)) } emit_ld1sb_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zs_p_m(rz, rz2, mem)) } emit_ld1sb_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sb_zd_p_m(rz, rz2, mem)) } -inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sh_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_ld1sh_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SH, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sh_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zd_p_m(rz, rz2, mem)) } emit_ld1sh_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sh_zs_p_m(rz, rz2, mem)) } -inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ld1sw_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1SW, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1sw_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ld1sw_zd_p_m(rz, rz2, mem)) } -inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1b_zpb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1b_zqb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1b_zpb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1b_zqb_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zb_p_m(rz, rz2, mem)) } emit_st1b_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zs_p_m(rz, rz2, mem)) } emit_st1b_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zd_p_m(rz, rz2, mem)) } emit_st1b_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1b_i_p_m(imm, rz1, mem)) } emit_st1b_zpb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zpb_pn_m(rz, rz2, mem)) } emit_st1b_zqb_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1b_zqb_pn_m(rz, rz2, mem)) } -inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_st1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1h_zph_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1h_zqh_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1h_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_st1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zh_p_m(rz, rz2, mem)) } emit_st1h_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zd_p_m(rz, rz2, mem)) } emit_st1h_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1h_i_p_m(imm, rz1, mem)) } emit_st1h_zph_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zph_pn_m(rz, rz2, mem)) } emit_st1h_zqh_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zqh_pn_m(rz, rz2, mem)) } emit_st1h_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1h_zs_p_m(rz, rz2, mem)) } -inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1w_zps_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1w_zqs_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1w_zps_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1w_zqs_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zs_p_m(rz, rz2, mem)) } emit_st1w_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zd_p_m(rz, rz2, mem)) } emit_st1w_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1w_i_p_m(imm, rz1, mem)) } emit_st1w_zps_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zps_pn_m(rz, rz2, mem)) } emit_st1w_zqs_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1w_zqs_pn_m(rz, rz2, mem)) } -inst_st1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } -inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } -inst_st1d_zpd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } -inst_st1d_zqd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}}} } +inst_st1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1d_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } +inst_st1d_zpd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } +inst_st1d_zqd_pn_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_PN | (8 + (u16(rz2) & 0x7)))), op_mem(mem), {}, {}}} } emit_st1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zd_p_m(rz, rz2, mem)) } emit_st1d_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1d_i_p_m(imm, rz1, mem)) } emit_st1d_zpd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zpd_pn_m(rz, rz2, mem)) } emit_st1d_zqd_pn_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_st1d_zqd_pn_m(rz, rz2, mem)) } -inst_ldff1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1b_zb_p_m(rz, rz2, mem)) } -inst_ldff1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1h_zh_p_m(rz, rz2, mem)) } -inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1w_zs_p_m(rz, rz2, mem)) } -inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldff1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDFF1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldff1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldff1d_zd_p_m(rz, rz2, mem)) } -inst_whilege_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilege_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilege_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilege_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilege_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pb_r_r(rz, src, src2)) } emit_whilege_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ph_r_r(rz, src, src2)) } emit_whilege_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_ps_r_r(rz, src, src2)) } emit_whilege_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilege_pd_r_r(rz, src, src2)) } -inst_whilegt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilegt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilegt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilegt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilegt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pb_r_r(rz, src, src2)) } emit_whilegt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ph_r_r(rz, src, src2)) } emit_whilegt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_ps_r_r(rz, src, src2)) } emit_whilegt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilegt_pd_r_r(rz, src, src2)) } -inst_whilele_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilele_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilele_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilele_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilele_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pb_r_r(rz, src, src2)) } emit_whilele_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ph_r_r(rz, src, src2)) } emit_whilele_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_ps_r_r(rz, src, src2)) } emit_whilele_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilele_pd_r_r(rz, src, src2)) } -inst_whilelt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelt_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelt_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilelt_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pb_r_r(rz, src, src2)) } emit_whilelt_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ph_r_r(rz, src, src2)) } emit_whilelt_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_ps_r_r(rz, src, src2)) } emit_whilelt_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelt_pd_r_r(rz, src, src2)) } -inst_whilehi_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehi_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehi_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehi_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilehi_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pb_r_r(rz, src, src2)) } emit_whilehi_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ph_r_r(rz, src, src2)) } emit_whilehi_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_ps_r_r(rz, src, src2)) } emit_whilehi_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehi_pd_r_r(rz, src, src2)) } -inst_whilehs_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilehs_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilehs_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilehs_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilehs_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pb_r_r(rz, src, src2)) } emit_whilehs_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ph_r_r(rz, src, src2)) } emit_whilehs_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_ps_r_r(rz, src, src2)) } emit_whilehs_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilehs_pd_r_r(rz, src, src2)) } -inst_whilelo_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilelo_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilelo_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilelo_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilelo_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pb_r_r(rz, src, src2)) } emit_whilelo_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ph_r_r(rz, src, src2)) } emit_whilelo_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_ps_r_r(rz, src, src2)) } emit_whilelo_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilelo_pd_r_r(rz, src, src2)) } -inst_whilels_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } -inst_whilels_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +inst_whilels_pb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_ph_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_ps_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } +inst_whilels_pd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}, {}}} } emit_whilels_pb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pb_r_r(rz, src, src2)) } emit_whilels_ph_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ph_r_r(rz, src, src2)) } emit_whilels_ps_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_ps_r_r(rz, src, src2)) } emit_whilels_pd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_whilels_pd_r_r(rz, src, src2)) } -inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqrdmlah_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqrdmlah_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqrdmlah_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqrdmlah_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqrdmlah_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqrdmlah_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zb_zb_zb(rz, rz2, rz3)) } emit_sqrdmlah_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zh_zh_zh(rz, rz2, rz3)) } emit_sqrdmlah_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zs_zs_zs(rz, rz2, rz3)) } emit_sqrdmlah_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlah_zd_zd_zd(rz, rz2, rz3)) } -inst_sqrdmlsh_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_sqrdmlsh_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } -inst_sqrdmlsh_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sqrdmlsh_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sqrdmlsh_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_sqrdmlsh_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } +inst_sqrdmlsh_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sqrdmlsh_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sqrdmlsh_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zb_zb_zb(rz, rz2, rz3)) } emit_sqrdmlsh_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zh_zh_zh(rz, rz2, rz3)) } emit_sqrdmlsh_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zs_zs_zs(rz, rz2, rz3)) } emit_sqrdmlsh_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sqrdmlsh_zd_zd_zd(rz, rz2, rz3)) } -inst_adclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_adclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_adclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_adclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_adclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zs_zs_zs(rz, rz2, rz3)) } emit_adclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclb_zd_zd_zd(rz, rz2, rz3)) } -inst_adclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_adclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_adclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_adclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_adclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zs_zs_zs(rz, rz2, rz3)) } emit_adclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_adclt_zd_zd_zd(rz, rz2, rz3)) } -inst_sbclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sbclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sbclb_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sbclb_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sbclb_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zs_zs_zs(rz, rz2, rz3)) } emit_sbclb_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclb_zd_zd_zd(rz, rz2, rz3)) } -inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } -inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}}} } +inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } +inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sbclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zs_zs_zs(rz, rz2, rz3)) } emit_sbclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zd_zd_zd(rz, rz2, rz3)) } -inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_tbl2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_zb_zb_zb(rz, rz2, rz3)) } -inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_match_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_match_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_ph_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_nmatch_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } -inst_nmatch_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_nmatch_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } +inst_nmatch_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_nmatch_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_pb_p_zb_zb(rz, rz2, rz3, rz4)) } emit_nmatch_ph_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nmatch_ph_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_histcnt_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } -inst_histcnt_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +inst_histcnt_zs_p_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4), {}}} } +inst_histcnt_zd_p_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .HISTCNT, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4), {}}} } emit_histcnt_zs_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zs_p_zs_zs(rz, rz2, rz3, rz4)) } emit_histcnt_zd_p_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_histcnt_zd_p_zd_zd(rz, rz2, rz3, rz4)) } -inst_histseg_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_histseg_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_histseg_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_histseg_zb_zb_zb(rz, rz2, rz3)) } inst_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SMSTART) } emit_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstart_none()) } @@ -3923,163 +3923,163 @@ inst_smstop_none :: #force_inline proc "contextless" () -> Instruct emit_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_smstop_none()) } inst_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.RDSVL, dst, imm) } emit_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_rdsvl_r_i(dst, imm)) } -inst_addha_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +inst_addha_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDHA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_addha_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addha_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_addva_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +inst_addva_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ADDVA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } emit_addva_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_addva_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } +inst_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}, {}}} } emit_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_zero_i(imm)) } -inst_fmopa_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmopa_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmopa_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_fmops_i_p_p_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } -emit_fmops_i_p_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_fmops_i_p_p_zs(imm, rz1, rz2, rz3)) } -inst_bfmopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_bfmops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_bfmops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_smopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_smopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_smopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_smopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_smops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_smops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_smops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_smops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_smops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_umopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_umopa_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_umopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_umopa_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umopa_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_umops_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -inst_umops_i_p_p_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } -emit_umops_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zb(imm, rz1, rz2, rz3)) } -emit_umops_i_p_p_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_umops_i_p_p_zh(imm, rz1, rz2, rz3)) } -inst_usmopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_usmopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_usmopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -inst_sumopa_i_p_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } -emit_sumopa_i_p_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sumopa_i_p_p_zb(imm, rz1, rz2, rz3)) } -inst_cntb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_fmopa_i_p_p_zs_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_fmopa_i_p_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmopa_i_p_p_zs_zs(imm, rz1, rz2, rz3, rz4)) } +inst_fmops_i_p_p_zs_zs :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .FMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_fmops_i_p_p_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_fmops_i_p_p_zs_zs(imm, rz1, rz2, rz3, rz4)) } +inst_bfmopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_bfmops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_bfmops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_smopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_smopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_smopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_smops_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_smops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_smops_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smops_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_smops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_smops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_umopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umopa_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_umopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_umopa_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umopa_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_umops_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_umops_i_p_p_zh_zh :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .UMOPS, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_umops_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umops_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +emit_umops_i_p_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_umops_i_p_p_zh_zh(imm, rz1, rz2, rz3, rz4)) } +inst_usmopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .USMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_usmopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_usmopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +inst_sumopa_i_p_p_zb_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SUMOPA, operand_count = 5, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sumopa_i_p_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sumopa_i_p_p_zb_zb(imm, rz1, rz2, rz3, rz4)) } +inst_cntb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntb_r_i_i(dst, imm, imm2)) } -inst_cnth_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cnth_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cnth_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cnth_r_i_i(dst, imm, imm2)) } -inst_cntw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cntw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntw_r_i_i(dst, imm, imm2)) } -inst_cntd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_cntd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .CNTD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_cntd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_cntd_r_i_i(dst, imm, imm2)) } -inst_incb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incb_r_i_i(dst, imm, imm2)) } -inst_inch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_inch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_inch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_inch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_inch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_inch_r_i_i(dst, imm, imm2)) } emit_inch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_inch_zh_i_i(rz, imm, imm2)) } -inst_incw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_incw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_incw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incw_r_i_i(dst, imm, imm2)) } emit_incw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incw_zs_i_i(rz, imm, imm2)) } -inst_incd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_incd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_incd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_incd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_incd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_incd_r_i_i(dst, imm, imm2)) } emit_incd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_incd_zd_i_i(rz, imm, imm2)) } -inst_decb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decb_r_i_i(dst, imm, imm2)) } -inst_dech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_dech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_dech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_dech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_dech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_dech_r_i_i(dst, imm, imm2)) } emit_dech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_dech_zh_i_i(rz, imm, imm2)) } -inst_decw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_decw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_decw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decw_r_i_i(dst, imm, imm2)) } emit_decw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decw_zs_i_i(rz, imm, imm2)) } -inst_decd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_decd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_decd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .DECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_decd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_decd_r_i_i(dst, imm, imm2)) } emit_decd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_decd_zd_i_i(rz, imm, imm2)) } -inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } +inst_sqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_i_i(dst, imm, imm2)) } emit_sqincb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincb_r_r_i_i(dst, src, imm, imm2)) } -inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqinch_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqinch_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_i_i(dst, imm, imm2)) } emit_sqinch_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqinch_r_r_i_i(dst, src, imm, imm2)) } emit_sqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqinch_zh_i_i(rz, imm, imm2)) } -inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_i_i(dst, imm, imm2)) } emit_sqincw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincw_r_r_i_i(dst, src, imm, imm2)) } emit_sqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincw_zs_i_i(rz, imm, imm2)) } -inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqincd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqincd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_i_i(dst, imm, imm2)) } emit_sqincd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqincd_r_r_i_i(dst, src, imm, imm2)) } emit_sqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqincd_zd_i_i(rz, imm, imm2)) } -inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } +inst_sqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecb_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECB, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_sqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_i_i(dst, imm, imm2)) } emit_sqdecb_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecb_r_r_i_i(dst, src, imm, imm2)) } -inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdech_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdech_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_i_i(dst, imm, imm2)) } emit_sqdech_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdech_r_r_i_i(dst, src, imm, imm2)) } emit_sqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdech_zh_i_i(rz, imm, imm2)) } -inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecw_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_i_i(dst, imm, imm2)) } emit_sqdecw_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecw_zs_i_i(rz, imm, imm2)) } -inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_sqdecd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4)}} } -inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_sqdecd_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_sqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_sqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_i_i(dst, imm, imm2)) } emit_sqdecd_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_r_r_i_i(dst, src, imm, imm2)) } emit_sqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sqdecd_zd_i_i(rz, imm, imm2)) } -inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincb_r_i_i(dst, imm, imm2)) } -inst_uqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqinch_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqinch_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqinch_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqinch_r_i_i(dst, imm, imm2)) } emit_uqinch_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqinch_zh_i_i(rz, imm, imm2)) } -inst_uqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqincw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincw_r_i_i(dst, imm, imm2)) } emit_uqincw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincw_zs_i_i(rz, imm, imm2)) } -inst_uqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqincd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqincd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQINCD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqincd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqincd_r_i_i(dst, imm, imm2)) } emit_uqincd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqincd_zd_i_i(rz, imm, imm2)) } -inst_uqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecb_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECB, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecb_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecb_r_i_i(dst, imm, imm2)) } -inst_uqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdech_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdech_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECH, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdech_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdech_r_i_i(dst, imm, imm2)) } emit_uqdech_zh_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdech_zh_i_i(rz, imm, imm2)) } -inst_uqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecw_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdecw_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECW, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecw_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_r_i_i(dst, imm, imm2)) } emit_uqdecw_zs_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecw_zs_i_i(rz, imm, imm2)) } -inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}}} } -inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } +inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } +inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}, {}}} } emit_uqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_r_i_i(dst, imm, imm2)) } emit_uqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_zd_i_i(rz, imm, imm2)) } -inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } emit_cntp_r_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pb(dst, rz1, rz2)) } emit_cntp_r_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ph(dst, rz1, rz2)) } emit_cntp_r_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ps(dst, rz1, rz2)) } emit_cntp_r_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pd(dst, rz1, rz2)) } -inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_incp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pb(dst, rz1)) } emit_incp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ph(dst, rz1)) } emit_incp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ps(dst, rz1)) } @@ -4087,13 +4087,13 @@ emit_incp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_incp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_ph(rz, rz2)) } emit_incp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_ps(rz, rz2)) } emit_incp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_pd(rz, rz2)) } -inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_decp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pb(dst, rz1)) } emit_decp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ph(dst, rz1)) } emit_decp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ps(dst, rz1)) } @@ -4101,17 +4101,17 @@ emit_decp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_decp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_ph(rz, rz2)) } emit_decp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_ps(rz, rz2)) } emit_decp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_pd(rz, rz2)) } -inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqincp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_sqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pb(dst, rz1)) } emit_sqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ph(dst, rz1)) } emit_sqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ps(dst, rz1)) } @@ -4123,17 +4123,17 @@ emit_sqincp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_ph(rz, rz2)) } emit_sqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_ps(rz, rz2)) } emit_sqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_pd(rz, rz2)) } -inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}}} } -inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_sqdecp_r_pb_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_ph_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_ps_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_r_pd_r :: #force_inline proc "contextless" (dst: Register, rz1: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(src), {}, {}}} } +inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_sqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pb(dst, rz1)) } emit_sqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ph(dst, rz1)) } emit_sqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ps(dst, rz1)) } @@ -4145,13 +4145,13 @@ emit_sqdecp_r_pd_r :: #force_inline proc(instructions: ^[dynamic]Inst emit_sqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_ph(rz, rz2)) } emit_sqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_ps(rz, rz2)) } emit_sqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_pd(rz, rz2)) } -inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_uqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pb(dst, rz1)) } emit_uqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ph(dst, rz1)) } emit_uqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ps(dst, rz1)) } @@ -4159,13 +4159,13 @@ emit_uqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_ph(rz, rz2)) } emit_uqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_ps(rz, rz2)) } emit_uqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_pd(rz, rz2)) } -inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } +inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}, {}}} } emit_uqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pb(dst, rz1)) } emit_uqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ph(dst, rz1)) } emit_uqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ps(dst, rz1)) } @@ -4173,72 +4173,72 @@ emit_uqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Inst emit_uqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_ph(rz, rz2)) } emit_uqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_ps(rz, rz2)) } emit_uqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_pd(rz, rz2)) } -inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } -inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_st1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_st1q_i_p_m(imm, rz1, mem)) } -inst_mova_zb_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } -inst_mova_i_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +inst_mova_zb_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}, {}}} } +inst_mova_i_p_zb :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .MOVA, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}, {}}} } emit_mova_zb_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_mova_zb_p_i(rz, rz2, imm)) } emit_mova_i_p_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_mova_i_p_zb(imm, rz1, rz2)) } -inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } -inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } -inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } -inst_fcmla_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +inst_fcmla_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1), {}}} } +inst_fcmla_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } emit_fcmla_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4h_v4h_v4h_i(dst, src, src2, imm)) } emit_fcmla_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v8h_v8h_v8h_i(dst, src, src2, imm)) } emit_fcmla_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v4s_v4s_v4s_i(dst, src, src2, imm)) } emit_fcmla_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_v2d_v2d_v2d_i(dst, src, src2, imm)) } -inst_fcadd_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1)}} } -inst_fcadd_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1)}} } -inst_fcadd_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1)}} } -inst_fcadd_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1)}} } +inst_fcadd_v4h_v4h_v4h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4h(dst), op_v_4h(src), op_v_4h(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v8h_v8h_v8h_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_8h(dst), op_v_8h(src), op_v_8h(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v4s_v4s_v4s_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), op_imm(imm, 1), {}}} } +inst_fcadd_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } emit_fcadd_v4h_v4h_v4h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4h_v4h_v4h_i(dst, src, src2, imm)) } emit_fcadd_v8h_v8h_v8h_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v8h_v8h_v8h_i(dst, src, src2, imm)) } emit_fcadd_v4s_v4s_v4s_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v4s_v4s_v4s_i(dst, src, src2, imm)) } emit_fcadd_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_v2d_v2d_v2d_i(dst, src, src2, imm)) } -inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfb_i_p_m(imm, rz1, mem)) } -inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfh_i_p_m(imm, rz1, mem)) } -inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfw_i_p_m(imm, rz1, mem)) } -inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +inst_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}, {}}} } emit_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_prfd_i_p_m(imm, rz1, mem)) } -inst_ldnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1b_zb_p_m(rz, rz2, mem)) } -inst_ldnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1h_zh_p_m(rz, rz2, mem)) } -inst_ldnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1w_zs_p_m(rz, rz2, mem)) } -inst_ldnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_ldnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_ldnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_ldnt1d_zd_p_m(rz, rz2, mem)) } -inst_stnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1b_zb_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1B, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_B, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1b_zb_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1b_zb_p_m(rz, rz2, mem)) } -inst_stnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1h_zh_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1H, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_H, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1h_zh_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1h_zh_p_m(rz, rz2, mem)) } -inst_stnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1w_zs_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1W, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_S, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1w_zs_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1w_zs_p_m(rz, rz2, mem)) } -inst_stnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +inst_stnt1d_zd_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STNT1D, operand_count = 3, length = 4, ops = {op_v_list(Register(REG_Z | (u16(rz) & 0x1F)), ZSHAPE_D, 1), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}, {}}} } emit_stnt1d_zd_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_stnt1d_zd_p_m(rz, rz2, mem)) } -inst_splice_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +inst_splice_zb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } emit_splice_zb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_splice_zb_p_zb_zb(rz, rz2, rz3, rz4)) } -inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zh_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zh_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zh_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zs_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zs_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zs_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_reg(src2), {}}} } -inst_index_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } -inst_index_zd_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_reg(src), {}}} } -inst_index_zd_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_imm(imm, 1), {}}} } -inst_index_zd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_reg(src2), {}}} } +inst_index_zb_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zb_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zb_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zb_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zh_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zh_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zh_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zh_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zs_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zs_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zs_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zs_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(src), op_reg(src2), {}, {}}} } +inst_index_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_imm(imm2, 1), {}, {}}} } +inst_index_zd_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 1), op_reg(src), {}, {}}} } +inst_index_zd_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_imm(imm, 1), {}, {}}} } +inst_index_zd_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .INDEX, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(src), op_reg(src2), {}, {}}} } emit_index_zb_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_index_zb_i_i(rz, imm, imm2)) } emit_index_zb_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zb_i_r(rz, imm, src)) } emit_index_zb_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zb_r_i(rz, src, imm)) } @@ -4255,19 +4255,19 @@ emit_index_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_index_zd_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_index_zd_i_r(rz, imm, src)) } emit_index_zd_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_index_zd_r_i(rz, src, imm)) } emit_index_zd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_index_zd_r_r(rz, src, src2)) } -inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl1n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl1n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl1n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_bsl2n_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_bsl2n_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bsl2n_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_nbsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +inst_nbsl_zd_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4), {}}} } emit_nbsl_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_nbsl_zd_zd_zd_zd(rz, rz2, rz3, rz4)) } -inst_pmul_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +inst_pmul_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMUL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } emit_pmul_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmul_zb_zb_zb(rz, rz2, rz3)) } -inst_pmullb_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_pmullb_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } emit_pmullb_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullb_zd_zs_zs(rz, rz2, rz3)) } -inst_pmullt_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +inst_pmullt_zd_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } emit_pmullt_zd_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pmullt_zd_zs_zs(rz, rz2, rz3)) } -inst_bfcvtnt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +inst_bfcvtnt_zh_p_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}, {}}} } emit_bfcvtnt_zh_p_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfcvtnt_zh_p_zs(rz, rz2, rz3)) } inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } @@ -4277,7 +4277,7 @@ inst_tstart_r :: #force_inline proc "contextless" (dst: Register emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } -inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}, {}}} } emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } @@ -4359,21 +4359,21 @@ inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_bfadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfadd_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfadd_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFADD, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfadd_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfadd_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfadd_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfadd_zh_zh_zh(rz, rz2, rz3)) } -inst_bfsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfsub_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfsub_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFSUB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfsub_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfsub_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfsub_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfsub_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } -inst_bfmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfmul_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } +inst_bfmul_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfmul_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmul_zh_p_zh_zh(rz, rz2, rz3, rz4)) } emit_bfmul_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfmul_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmla_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmla_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmla_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_bfmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmls_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmls_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmls_zh_p_zh_zh(rz, rz2, rz3, rz4)) } inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } @@ -4391,30 +4391,30 @@ inst_bti_c_none :: #force_inline proc "contextless" () -> Instruct emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_bfclamp_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +inst_bfclamp_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } emit_bfclamp_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_bfclamp_zh_zh_zh(rz, rz2, rz3)) } -inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfmaxnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfmaxnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfmaxnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +inst_bfminnm_zh_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_bfminnm_zh_p_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_bfminnm_zh_p_zh_zh(rz, rz2, rz3, rz4)) } -inst_luti2_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti2_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti2_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti2_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti2_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti2_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI2, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } emit_luti2_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zpb_zt_z_i(rz, rz2, imm)) } emit_luti2_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zph_zt_z_i(rz, rz2, imm)) } emit_luti2_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti2_zps_zt_z_i(rz, rz2, imm)) } -inst_luti4_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti4_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } -inst_luti4_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm)}} } +inst_luti4_zpb_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti4_zph_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } +inst_luti4_zps_zt_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .LUTI4, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(ZT0), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_lane_index(imm), {}}} } emit_luti4_zpb_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zpb_zt_z_i(rz, rz2, imm)) } emit_luti4_zph_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zph_zt_z_i(rz, rz2, imm)) } emit_luti4_zps_zt_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_luti4_zps_zt_z_i(rz, rz2, imm)) } -inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_zip_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_zip_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .ZIP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_zip_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_zip_zpb_zb_zb(rz, rz2, rz3)) } emit_zip_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_zip_zqb_zqb(rz, rz2)) } -inst_uzp_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } -inst_uzp_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +inst_uzp_zpb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } +inst_uzp_zqb_zqb :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UZP, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}, {}}} } emit_uzp_zpb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_uzp_zpb_zb_zb(rz, rz2, rz3)) } emit_uzp_zqb_zqb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uzp_zqb_zqb(rz, rz2)) } inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } @@ -4579,22 +4579,22 @@ inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruct emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } -inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } +inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } +inst_prfm_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}, {}}} } emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } emit_prfm_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_i_l(imm, label)) } -inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } -inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } -inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmp_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } +inst_cmp_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}, {}}} } inst_cmp_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP, dst, imm) } emit_cmp_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_r_sh(dst, src, src_shift, src_amount)) } emit_cmp_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_r_ex(dst, src, src_ext, src_amount)) } emit_cmp_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_i(dst, imm)) } -inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } -inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +inst_cmn_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}, {}}} } +inst_cmn_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}, {}}} } inst_cmn_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN, dst, imm) } emit_cmn_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_r_sh(dst, src, src_shift, src_amount)) } emit_cmn_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_r_ex(dst, src, src_ext, src_amount)) } @@ -5870,26 +5870,26 @@ inst_addva :: inst_addva_i_p_p_zs emit_addva :: emit_addva_i_p_p_zs inst_zero :: inst_zero_i emit_zero :: emit_zero_i -inst_fmopa :: inst_fmopa_i_p_p_zs -emit_fmopa :: emit_fmopa_i_p_p_zs -inst_fmops :: inst_fmops_i_p_p_zs -emit_fmops :: emit_fmops_i_p_p_zs -inst_bfmopa :: inst_bfmopa_i_p_p_zh -emit_bfmopa :: emit_bfmopa_i_p_p_zh -inst_bfmops :: inst_bfmops_i_p_p_zh -emit_bfmops :: emit_bfmops_i_p_p_zh -inst_smopa :: inst_smopa_i_p_p_zb -emit_smopa :: emit_smopa_i_p_p_zb -inst_smops :: inst_smops_i_p_p_zb -emit_smops :: emit_smops_i_p_p_zb -inst_umopa :: inst_umopa_i_p_p_zb -emit_umopa :: emit_umopa_i_p_p_zb -inst_umops :: inst_umops_i_p_p_zb -emit_umops :: emit_umops_i_p_p_zb -inst_usmopa :: inst_usmopa_i_p_p_zb -emit_usmopa :: emit_usmopa_i_p_p_zb -inst_sumopa :: inst_sumopa_i_p_p_zb -emit_sumopa :: emit_sumopa_i_p_p_zb +inst_fmopa :: inst_fmopa_i_p_p_zs_zs +emit_fmopa :: emit_fmopa_i_p_p_zs_zs +inst_fmops :: inst_fmops_i_p_p_zs_zs +emit_fmops :: emit_fmops_i_p_p_zs_zs +inst_bfmopa :: inst_bfmopa_i_p_p_zh_zh +emit_bfmopa :: emit_bfmopa_i_p_p_zh_zh +inst_bfmops :: inst_bfmops_i_p_p_zh_zh +emit_bfmops :: emit_bfmops_i_p_p_zh_zh +inst_smopa :: inst_smopa_i_p_p_zb_zb +emit_smopa :: emit_smopa_i_p_p_zb_zb +inst_smops :: inst_smops_i_p_p_zb_zb +emit_smops :: emit_smops_i_p_p_zb_zb +inst_umopa :: inst_umopa_i_p_p_zb_zb +emit_umopa :: emit_umopa_i_p_p_zb_zb +inst_umops :: inst_umops_i_p_p_zb_zb +emit_umops :: emit_umops_i_p_p_zb_zb +inst_usmopa :: inst_usmopa_i_p_p_zb_zb +emit_usmopa :: emit_usmopa_i_p_p_zb_zb +inst_sumopa :: inst_sumopa_i_p_p_zb_zb +emit_sumopa :: emit_sumopa_i_p_p_zb_zb inst_cntb :: inst_cntb_r_i_i emit_cntb :: emit_cntb_r_i_i inst_cnth :: inst_cnth_r_i_i diff --git a/core/rexcode/isa/arm64/tablegen/gen.odin b/core/rexcode/isa/arm64/tablegen/gen.odin index 74ea5654e..283cabe73 100644 --- a/core/rexcode/isa/arm64/tablegen/gen.odin +++ b/core/rexcode/isa/arm64/tablegen/gen.odin @@ -44,8 +44,8 @@ PATH_LOADER :: #directory + "/../tables.odin" Entry :: struct { mnemonic: lib.Mnemonic, - ops: [4]lib.Operand_Type, - enc: [4]lib.Operand_Encoding, + ops: [5]lib.Operand_Type, + enc: [5]lib.Operand_Encoding, bits: u32, mask: u32, feature: lib.Feature, @@ -260,13 +260,13 @@ emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { // Shared row + flags formatting (compact, matching arm64's original generator) // ----------------------------------------------------------------------------- -write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, - enc: [4]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { - fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", - mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], bits, mask, feature, flags_lit(flags, ops)) +write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [5]lib.Operand_Type, + enc: [5]lib.Operand_Encoding, bits, mask: u32, feature: lib.Feature, flags: lib.Encoding_Flags) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, {{%s}} }},\n", + mn, ops[0], ops[1], ops[2], ops[3], ops[4], enc[0], enc[1], enc[2], enc[3], enc[4], bits, mask, feature, flags_lit(flags, ops)) } -flags_lit :: proc(f: lib.Encoding_Flags, ops: [4]lib.Operand_Type) -> string { +flags_lit :: proc(f: lib.Encoding_Flags, ops: [5]lib.Operand_Type) -> string { parts: [dynamic]string defer delete(parts) if f.branch { append(&parts, "branch=true") } @@ -321,14 +321,14 @@ Encode_Run :: struct { Decode_Entry :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 22) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index cc2ec5558..e3c910592 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -9,2679 +9,2679 @@ import lib "../.." @(rodata) DECODE_ENTRIES := [2673]lib.Decode_Entry{ - { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, - { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, - { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, - { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, - { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, - { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, - { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, - { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, - { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, - { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, - { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, - { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, - { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, - { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, - { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, - { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, - { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, 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{explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, - { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, - { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, - { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, - { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, - { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAXRB, 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{explicit_count=3} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, 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{explicit_count=3} }, - { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, 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{.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, + { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 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{.RD,.PN,.NONE,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PD,.NONE}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, 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{.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, 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{.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, 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{.VD,.VN,.VM,.NONE,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, 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.SHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + 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{explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, 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0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 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0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, 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0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, 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0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, 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{ .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, 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{.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6,.NONE}, {.VD,.VN,.VM,.IMM6,.NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, + { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF2000000, 0xFF800000, .BASE, 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{explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 7c4ba00a4..5dbff414b 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -10,3531 +10,3531 @@ import lib "../.." @(rodata) ENCODE_FORMS := [2671]lib.Encoding{ // .ADD - { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .ADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ADD, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ADD, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .ADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ADD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04000000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04400000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04800000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ADDS - { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADDS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADDS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SUB - { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, - { .SUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUB, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x51000000, 0xFF800000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4B000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .SUB, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4B200000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .SUB, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .SUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SUB, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04010000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04410000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04810000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SUBS - { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBS, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .SUBS, {.X_REG,.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .MOVZ - { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x52800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVN - { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x12800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVN, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .MOVK - { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, - { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .MOVK, {.W_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0x72800000, 0xFF800000, .BASE, {explicit_count=3} }, + { .MOVK, {.X_REG,.IMM_16,.HW_SHIFT,.NONE,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE,.NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, // .ADR - { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADR, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x10000000, 0x9F000000, .BASE, {explicit_count=2} }, // .ADRP - { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, + { .ADRP, {.X_REG,.REL_PG21,.NONE,.NONE,.NONE}, {.RD,.BRANCH_PG21,.NONE,.NONE,.NONE}, 0x90000000, 0x9F000000, .BASE, {explicit_count=2} }, // .AND - { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .AND, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .AND, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .AND, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x12000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .AND, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .AND, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .AND, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .AND, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .AND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ANDS - { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, - { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ANDS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.W_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true, explicit_count=3} }, + { .ANDS, {.X_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORR - { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .ORR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORR, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORR, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x32000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .ORR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .ORR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04180000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04580000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04980000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ORR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ORR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EOR - { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, - { .EOR, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .EOR, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4A000000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EOR, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x52000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .EOR, {.XSP_REG,.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, + { .EOR, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .EOR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04190000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04590000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04990000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .EOR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .EOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BIC - { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .BIC, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .BIC, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x0A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .BIC, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .BIC, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIC, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x041B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x045B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x049B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BIC, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .BICS - { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, - { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, - { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .BICS, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true, explicit_count=3} }, + { .BICS, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORN - { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, - { .ORN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .ORN, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x2A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .ORN, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .ORN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, // .EON - { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, - { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE}, {.RD,.RN,.RM,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, + { .EON, {.W_REG,.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x4A200000, 0xFF200000, .BASE, {explicit_count=3} }, + { .EON, {.X_REG,.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true, explicit_count=3} }, // .LSL - { .LSL, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04138000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04538000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04938000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSL, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE,.NONE}, 0x53000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LSL, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LSR - { .LSR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .LSR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04118000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04518000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04918000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .LSR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ASR - { .ASR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, - { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, - { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ASR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04108000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04508000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04908000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {explicit_count=3} }, + { .ASR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.RN,.ENC_SHIFT_IMMR,.NONE,.NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ROR - { .ROR, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, - { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, + { .ROR, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ROR, {.W_REG,.W_REG,.IMM_5,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x13800000, 0xFFE00000, .BASE, {explicit_count=3} }, + { .ROR, {.X_REG,.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true, explicit_count=3} }, // .UDIV - { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UDIV, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .UDIV, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04950000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SDIV - { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SDIV, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SDIV, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04940000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MADD - { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .MADD, {.W_REG,.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1B000000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MADD, {.X_REG,.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .MSUB - { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG}, {.RD,.RN,.RM,.RA}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .MSUB, {.W_REG,.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1B008000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .MSUB, {.X_REG,.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMADDL - { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .SMADDL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMSUBL - { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .SMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMADDL - { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .UMADDL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .UMSUBL - { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG}, {.RD,.RN,.RM,.RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .UMSUBL, {.X_REG,.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .SMULH - { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMULH, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04120000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04520000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04920000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMULH - { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, - { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMULH, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .UMULH, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04130000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04530000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04930000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMULH, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .CLZ - { .CLZ, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .CLZ, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .CLZ, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, - { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLZ, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLZ, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLZ, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLZ, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0419A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0459A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0499A000, 0xFFF9E000, .SVE, {explicit_count=3} }, + { .CLZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true, explicit_count=3} }, // .CLS - { .CLS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .CLS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .CLS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, - { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, + { .CLS, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .CLS, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .CLS, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CLS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0418A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, + { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, // .RBIT - { .RBIT, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .RBIT, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .RBIT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .RBIT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .RBIT, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .RBIT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .RBIT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV - { .REV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, - { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, + { .REV, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .REV, {.Z_REG_D,.Z_REG_D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, // .REV16 - { .REV16, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .REV16, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV16, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV16, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .REV16, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV16, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV16, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .REV32 - { .REV32, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, - { .REV32, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV32, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .REV32, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV32, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CSEL - { .CSEL, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSEL, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSEL, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSEL, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINC - { .CSINC, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINC, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINC, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINC, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSINV - { .CSINV, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSINV, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSINV, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x5A800000, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSINV, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CSNEG - { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, - { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, + { .CSNEG, {.W_REG,.W_REG,.W_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x5A800400, 0xFFE00C00, .BASE, {explicit_count=4} }, + { .CSNEG, {.X_REG,.X_REG,.X_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=4} }, // .CCMP - { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.W_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.X_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMP, {.W_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMP, {.X_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CCMN - { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, - { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, - { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMN, {.W_REG,.W_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.X_REG,.NZCV_IMM,.COND,.NONE}, {.RN,.RM,.NZCV_FIELD,.COND_HI,.NONE}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CCMN, {.W_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true, explicit_count=4} }, + { .CCMN, {.X_REG,.IMM_5,.NZCV_IMM,.COND,.NONE}, {.RN,.IMM5_HI,.NZCV_FIELD,.COND_HI,.NONE}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CSET - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSET, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSET, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, // .CSETM - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, - { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.W_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true, explicit_count=2} }, + { .CSETM, {.X_REG,.COND_NOT_AL,.NONE,.NONE,.NONE}, {.RD,.COND_HI_INV,.NONE,.NONE,.NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true, explicit_count=2} }, // .CINC - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINC, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINC, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .CINV - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A800000, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CINV, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CINV, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .CNEG - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, - { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, - { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A800400, 0xFFE08C00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {explicit_count=3} }, + { .CNEG, {.W_REG,.W_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true, explicit_count=3} }, + { .CNEG, {.X_REG,.X_REG,.COND_NOT_AL,.NONE,.NONE}, {.RD,.RN_RM,.COND_HI_INV,.NONE,.NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true, explicit_count=3} }, // .EXTR - { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x13800000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.RM,.IMM6,.NONE}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .B - { .B, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .B, {.REL_26,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE,.NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BL - { .BL, {.REL_26,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, + { .BL, {.REL_26,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_26,.NONE,.NONE,.NONE,.NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true, explicit_count=1} }, // .BR - { .BR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BR, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .BLR - { .BLR, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLR, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, // .RET - { .RET, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, - { .RET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, + { .RET, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true, explicit_count=1} }, + { .RET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .B_EQ - { .B_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_EQ, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_NE - { .B_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_CS - { .B_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_CC - { .B_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_CC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_MI - { .B_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_MI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_PL - { .B_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_PL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_VS - { .B_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_VC - { .B_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_VC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_HI - { .B_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_HI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LS - { .B_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_GE - { .B_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LT - { .B_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_GT - { .B_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_GT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_LE - { .B_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_LE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_AL - { .B_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_AL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .B_NV - { .B_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .B_NV, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .CBZ - { .CBZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, - { .CBZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBZ, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBZ, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .CBNZ - { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, - { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, + { .CBNZ, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true, explicit_count=2} }, + { .CBNZ, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true, explicit_count=2} }, // .TBZ - { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .TBZ, {.X_REG,.IMM_5,.REL_14,.NONE,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE,.NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .TBNZ - { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, + { .TBNZ, {.X_REG,.IMM_5,.REL_14,.NONE,.NONE}, {.RT,.TBZ_BIT,.BRANCH_14,.NONE,.NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true, explicit_count=3} }, // .LDR - { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, - { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, + { .LDR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x18000000, 0xFF000000, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xB8400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDR, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDR, {.B_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.H_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, + { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR - { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STR, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, - { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, + { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xB8000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STR, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STR, {.B_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.H_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, + { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, + { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB - { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x38400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRB - { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x38000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x38000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSB - { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSB, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSB, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRH - { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79400000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x78400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x78400400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78600800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STRH - { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79000000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x78000C00, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_POST,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_POST,.NONE,.NONE,.NONE}, 0x78000400, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STRH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78200800, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDRSH - { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, - { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x79C00000, 0xFFC00000, .BASE, {explicit_count=2} }, + { .LDRSH, {.W_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78E00800, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDRSH, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDRSW - { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .LDRSW, {.X_REG,.MEM_REG,.NONE,.NONE,.NONE}, {.RT,.OFFSET_REG,.NONE,.NONE,.NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDP - { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.W_REG,.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28C00000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDP, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x2D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0x6D400000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .LDP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0xAD400000, 0xFFC00000, .NEON, {explicit_count=3} }, // .STP - { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, - { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x29800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.W_REG,.W_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28800000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STP, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STP, {.S_REG,.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x2D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.D_REG,.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0x6D000000, 0xFFC00000, .NEON, {explicit_count=3} }, + { .STP, {.Q_REG,.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0xAD000000, 0xFFC00000, .NEON, {explicit_count=3} }, // .LDPSW - { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, - { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDPSW, {.X_REG,.X_REG,.MEM_POST,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDAR - { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLR - { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .LDARB - { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDARB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRB - { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDARH - { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDARH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLRH - { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .STLRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .LDXR - { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STXR - { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .STXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .LDAXR - { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, - { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAXR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .STLXR - { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .STLXR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXR, {.W_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .NOP - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {} }, // .YIELD - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {} }, // .WFE - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {} }, // .WFI - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {} }, // .SEV - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {} }, // .SEVL - { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, + { .SEVL, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {} }, // .HINT - { .HINT, {.IMM_8,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, + { .HINT, {.IMM_8,.NONE,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {explicit_count=1} }, // .MRS - { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, + { .MRS, {.X_REG,.SYS_REG,.NONE,.NONE,.NONE}, {.RT,.SYS_FIELD,.NONE,.NONE,.NONE}, 0xD5300000, 0xFFF00000, .BASE, {explicit_count=2} }, // .MSR - { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, - { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, + { .MSR, {.PSTATE_FIELD,.IMM_4,.NONE,.NONE,.NONE}, {.MSR_PSTATE,.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {explicit_count=2} }, + { .MSR, {.SYS_REG,.X_REG,.NONE,.NONE,.NONE}, {.SYS_FIELD,.RT,.NONE,.NONE,.NONE}, 0xD5100000, 0xFFF00000, .BASE, {explicit_count=2} }, // .ISB - { .ISB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .ISB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DSB - { .DSB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .DSB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .DMB - { .DMB, {.IMM_4,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, + { .DMB, {.IMM_4,.NONE,.NONE,.NONE,.NONE}, {.BARRIER_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {explicit_count=1} }, // .SVC - { .SVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .SVC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HVC - { .HVC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .HVC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .SMC - { .SMC, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .SMC, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .BRK - { .BRK, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .BRK, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .HLT - { .HLT, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, + { .HLT, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true, explicit_count=1} }, // .ERET - { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, + { .ERET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true} }, // .FMOV - { .FMOV, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, - { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, - { .FMOV, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FMOV, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FMOV, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, - { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E201000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.D_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1E601000, 0xFFE01FE0, .FP, {explicit_count=2} }, + { .FMOV, {.H_REG,.IMM_8,.NONE,.NONE,.NONE}, {.RD,.FMOV_SCALAR_IMM,.NONE,.NONE,.NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {explicit_count=2} }, + { .FMOV, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E260000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E270000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FMOV, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FMOV, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_2D,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .FMOV, {.V_4H_FP16,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, + { .FMOV, {.V_8H_FP16,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {explicit_count=2} }, // .FABS - { .FABS, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FABS, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, - { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, + { .FABS, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FABS, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FABS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049CA000, 0xFFFCE000, .SVE, {explicit_count=3} }, + { .FABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true, explicit_count=3} }, // .FNEG - { .FNEG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FNEG, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, - { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FNEG, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E214000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E614000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FNEG, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FNEG, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, + { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, // .FSQRT - { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, - { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, + { .FSQRT, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FSQRT, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FSQRT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FSQRT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658DA000, 0xFFEDE000, .SVE, {explicit_count=3} }, + { .FSQRT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true, explicit_count=3} }, // .FADD - { .FADD, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FADD, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FADD, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E202800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E602800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FADD, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65408000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65808000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FADD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FSUB - { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUB, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E203800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E603800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FSUB, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65418000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65818000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUB, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMUL - { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E200800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E600800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMUL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65428000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65828000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIV - { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIV, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E201800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E601800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FDIV, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FDIV, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FDIV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658D8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMUL - { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FNMUL, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E208800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E608800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FNMUL, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMADD - { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F000000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F400000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FMSUB - { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F008000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F408000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FC08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMADD - { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMADD, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F200000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F600000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMADD, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE00000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FNMSUB - { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG}, {.RD,.RN,.RM,.RA}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG}, {.RD,.RN,.RM,.RA}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, - { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG}, {.RD,.RN,.RM,.RA}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, + { .FNMSUB, {.S_REG,.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F208000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.D_REG,.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1F608000, 0xFFE08000, .FP, {explicit_count=4} }, + { .FNMSUB, {.H_REG,.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.RA,.NONE}, 0x1FE08000, 0xFFE08000, .FP16, {explicit_count=4} }, // .FCMP - { .FCMP, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMP, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMP, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMP, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCMPE - { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, - { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true, explicit_count=2} }, + { .FCMPE, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true, explicit_count=2} }, // .FCSEL - { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, - { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND}, {.RD,.RN,.RM,.COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, + { .FCSEL, {.S_REG,.S_REG,.S_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E200C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.D_REG,.D_REG,.D_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1E600C00, 0xFFE00C00, .FP, {explicit_count=4} }, + { .FCSEL, {.H_REG,.H_REG,.H_REG,.COND,.NONE}, {.RD,.RN,.RM,.COND_HI,.NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {explicit_count=4} }, // .FMAX - { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAX, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E204800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E604800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAX, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65468000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65868000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMIN - { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMIN, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E205800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E605800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMIN, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMIN, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65478000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65878000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMAXNM - { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMAXNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E206800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E606800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMAXNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65448000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65848000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMAXNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FMINNM - { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, - { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FMINNM, {.S_REG,.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E207800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.D_REG,.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1E607800, 0xFFE0FC00, .FP, {explicit_count=3} }, + { .FMINNM, {.H_REG,.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNM, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65458000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65858000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FMINNM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FCVT - { .FCVT, {.D_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.S_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.H_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.S_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVT, {.D_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.S_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E624000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVT, {.H_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.H_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.S_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVT, {.D_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .SCVTF - { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E220000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.D_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E620000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .SCVTF, {.S_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .SCVTF, {.H_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .SCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .UCVTF - { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.S_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E230000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.D_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E630000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .UCVTF, {.S_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .UCVTF, {.H_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UCVTF, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .UCVTF, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZS - { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E380000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E780000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTZU - { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, - { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E390000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E790000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTZU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} }, + { .FCVTZU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTZU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTZU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAS - { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E240000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E640000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTAU - { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E250000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E650000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTAU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTAU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTAU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNS - { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E200000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E600000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTNU - { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E210000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E610000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTNU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTNU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTNU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPS - { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E280000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E680000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTPU - { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E290000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E690000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTPU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTPU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTPU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMS - { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E300000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E700000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMS, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMS, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMS, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FCVTMU - { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.W_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E310000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E710000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FCVTMU, {.X_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTMU, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTMU, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRINTA - { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTA, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E264000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E664000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTA, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTA, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6544A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6584A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTI - { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTI, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTI, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTI, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTI, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6547A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6587A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTI, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTM - { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTM, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E254000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E654000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTM, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTM, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6542A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6582A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTM, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTN - { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTN, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E244000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E644000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTN, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTN, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6540A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6580A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTP - { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTP, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTP, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTP, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTP, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6541A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6581A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTP, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTX - { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E274000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E674000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTX, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6546A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6586A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FRINTZ - { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRINTZ, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRINTZ, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRINTZ, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .TST - { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RN,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .TST, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .TST, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDUR - { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xBC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xFC400000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .LDUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .STUR - { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, - { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STUR, {.S_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xBC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.D_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xFC000000, 0xFFE00C00, .NEON, {explicit_count=2} }, + { .STUR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x3C800000, 0xFFE00C00, .NEON, {explicit_count=2} }, // .LDURB - { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURB - { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSB - { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x38C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURH - { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STURH - { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSH - { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x78C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDURSW - { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDNP - { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .LDNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28400000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .LDNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .STNP - { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, - { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, + { .STNP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_4,.NONE,.NONE}, 0x28000000, 0xFFC00000, .BASE, {explicit_count=3} }, + { .STNP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_8,.NONE,.NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=3} }, // .LDXP - { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0x887F0000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STXP - { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .STXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x88200000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDAXP - { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, - { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, + { .LDAXP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0x887F8000, 0xFFFF8000, .BASE, {explicit_count=3} }, + { .LDAXP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_BASE_A,.NONE,.NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true, explicit_count=3} }, // .STLXP - { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, - { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET}, {.RD,.RT,.RT2,.OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, + { .STLXP, {.W_REG,.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0x88208000, 0xFFE08000, .BASE, {explicit_count=4} }, + { .STLXP, {.W_REG,.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.RT2,.OFFSET_BASE_A,.NONE}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true, explicit_count=4} }, // .LDXRB - { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRB - { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRB - { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRB - { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXRB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDXRH - { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STXRH - { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAXRH - { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .LDAXRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .STLXRH - { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .STLXRH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RD,.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {explicit_count=3} }, // .LDAPR - { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, - { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, + { .LDAPR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true, explicit_count=2} }, // .LDAPRB - { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDAPRH - { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, + { .LDAPRH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {explicit_count=2} }, // .LDADD - { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADD, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADD, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDA - { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDL - { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDADDAL - { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDADDAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDADDAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLR - { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRA - { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRL - { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDCLRAL - { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDCLRAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDCLRAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEOR - { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEOR, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEOR, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORA - { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORL - { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDEORAL - { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDEORAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDEORAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSET - { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSET, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSET, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETA - { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETL - { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSETAL - { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSETAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSETAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAX - { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXA - { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXL - { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMAXAL - { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMIN - { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINA - { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINL - { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDSMINAL - { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDSMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDSMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAX - { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAX, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAX, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXA - { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXL - { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMAXAL - { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMAXAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMAXAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMIN - { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMIN, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMIN, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINA - { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINL - { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .LDUMINAL - { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .LDUMINAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .LDUMINAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWP - { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPA - { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPL - { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .SWPAL - { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .SWPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .SWPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CAS - { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CAS, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CAS, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASA - { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASL - { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASAL - { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASB - { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAB - { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLB - { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASLB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALB - { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASALB, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASH - { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASAH - { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASAH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASLH - { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASLH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASALH - { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASALH, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, // .CASP - { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASP, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPA - { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPA, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPA, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPL - { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .CASPAL - { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, - { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, + { .CASPAL, {.W_REG,.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {explicit_count=3} }, + { .CASPAL, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.ATOMIC_RS,.ATOMIC_RT,.ATOMIC_RN,.NONE,.NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true, explicit_count=3} }, // .PACIA - { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACIA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIB - { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACIB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDA - { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACDA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACDB - { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .PACDB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .PACIZA - { .PACIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACIZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIZB - { .PACIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACIZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZA - { .PACDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACDZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACDZB - { .PACDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .PACDZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIA - { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTIA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIB - { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTIB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDA - { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTDA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTDB - { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, + { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true, explicit_count=2} }, // .AUTIZA - { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTIZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTIZB - { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTIZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZA - { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTDZA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .AUTDZB - { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .AUTDZB, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .PACIASP - { .PACIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, + { .PACIASP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {} }, // .PACIBSP - { .PACIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {} }, + { .PACIBSP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {} }, // .AUTIASP - { .AUTIASP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIASP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {} }, // .AUTIBSP - { .AUTIBSP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIBSP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {} }, // .PACIA1716 - { .PACIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {} }, + { .PACIA1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {} }, // .PACIB1716 - { .PACIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {} }, + { .PACIB1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {} }, // .AUTIA1716 - { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, + { .AUTIA1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {} }, // .AUTIB1716 - { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, + { .AUTIB1716, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {} }, // .PACGA - { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, + { .PACGA, {.X_REG,.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true, explicit_count=3} }, // .XPACI - { .XPACI, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .XPACI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACD - { .XPACD, {.X_REG,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, + { .XPACD, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE,.NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true, explicit_count=1} }, // .XPACLRI - { .XPACLRI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, + { .XPACLRI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {} }, // .RETAA - { .RETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .RETAA, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .RETAB - { .RETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .RETAB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BRAA - { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BRAA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAB - { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BRAB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BRAAZ - { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRAAZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BRABZ - { .BRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BRABZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRAA - { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAA, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAB - { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, + { .BLRAB, {.X_REG,.XSP_REG,.NONE,.NONE,.NONE}, {.RN,.RD,.NONE,.NONE,.NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true, explicit_count=2} }, // .BLRAAZ - { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRAAZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .BLRABZ - { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, + { .BLRABZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RN,.NONE,.NONE,.NONE,.NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true, explicit_count=1} }, // .ERETAA - { .ERETAA, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .ERETAA, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .ERETAB - { .ERETAB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, + { .ERETAB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true} }, // .BTI - { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {} }, // .IRG - { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .IRG, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .ADDG - { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .ADDG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .SUBG - { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4}, {.RD,.RN,.IMM6,.IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, + { .SUBG, {.XSP_REG,.XSP_REG,.IMM_6,.IMM_4,.NONE}, {.RD,.RN,.IMM6,.IMM_HW,.NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true, explicit_count=4} }, // .GMI - { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .GMI, {.X_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBP - { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, + { .SUBP, {.X_REG,.XSP_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true, explicit_count=3} }, // .SUBPS - { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SUBPS, {.X_REG,.XSP_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true, explicit_count=3} }, // .LDG - { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .LDG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STG - { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .ST2G - { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .ST2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZG - { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZG, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZ2G - { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZ2G, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGP - { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, + { .STGP, {.X_REG,.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.RT2,.OFFSET_PAIR_16,.NONE,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true, explicit_count=3} }, // .LDGM - { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .LDGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STGM - { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .STZGM - { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, + { .STZGM, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true, explicit_count=2} }, // .CRC32B - { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32B, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32H - { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32H, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32W - { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32W, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32X - { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, + { .CRC32X, {.W_REG,.W_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .CRC32CB - { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CB, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CH - { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CH, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CW - { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, + { .CRC32CW, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {explicit_count=3} }, // .CRC32CX - { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, + { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true, explicit_count=3} }, // .AESE - { .AESE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESE, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESE, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESD - { .AESD, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VD,.VN,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, + { .AESD, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.VN,.NONE,.NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {explicit_count=3} }, // .AESMC - { .AESMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESMC, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .AESIMC - { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, - { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, + { .AESIMC, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, // .SHA1H - { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1H, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA1C - { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1C, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1P - { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1P, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1M - { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1M, {.Q_REG,.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU0 - { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA1SU0, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA1SU1 - { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA1SU1, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256H - { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256H2 - { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256H2, {.Q_REG,.Q_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA256SU0 - { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA256SU0, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA256SU1 - { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA256SU1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H - { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512H2 - { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512H2, {.Q_REG,.Q_REG,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SHA512SU0 - { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SHA512SU0, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SHA512SU1 - { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SHA512SU1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .EOR3 - { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .EOR3, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .BCAX - { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B}, {.VD,.VN,.VM,.VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, - { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .BCAX, {.V_16B,.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .RAX1 - { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .XAR - { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6}, {.VD,.VN,.VM,.IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6,.NONE}, {.VD,.VN,.VM,.IMM6,.NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, + { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, // .SM3PARTW1 - { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3PARTW2 - { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM3PARTW2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3SS1 - { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S}, {.VD,.VN,.VM,.VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, + { .SM3SS1, {.V_4S,.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.VA,.NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {explicit_count=4} }, // .SM3TT1A - { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT1B - { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2A - { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM3TT2B - { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, + { .SM3TT2B, {.V_4S,.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_IDX2,.NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {explicit_count=4} }, // .SM4E - { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, + { .SM4E, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {explicit_count=2} }, // .SM4EKEY - { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .SM4EKEY, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL - { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL, {.V_1Q,.V_1D,.V_1D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .PMULL2 - { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, - { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, + { .PMULL2, {.V_1Q,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .BFCVT - { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, - { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFCVT, {.H_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .BFDOT - { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFDOT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMMLA - { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMMLA, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALB - { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALB, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFMLALT - { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, + { .BFMLALT, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {explicit_count=3} }, // .BFCVTN - { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .BFCVTN2 - { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, + { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {explicit_count=2} }, // .MUL - { .MUL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .MUL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04900000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .MUL, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .MLA - { .MLA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MLS - { .MLS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .MLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .MLS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .NEG - { .NEG, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, - { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, - { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, - { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, + { .NEG, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, + { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .NEG, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {explicit_count=2} }, + { .NEG, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true, explicit_count=2} }, // .ABS - { .ABS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, - { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, + { .ABS, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, + { .ABS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true, explicit_count=3} }, // .SHADD - { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHADD - { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHSUB - { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UHSUB - { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UHSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SRHADD - { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URHADD - { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URHADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQADD - { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQADD - { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQADD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQADD, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQADD, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SQSUB - { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .SQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .UQSUB - { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQSUB, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSUB, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UQSUB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .SMAX - { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04080000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04480000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04880000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMAX - { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMAX, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAX, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04090000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04490000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04890000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMAX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SMIN - { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SMIN, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048A0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UMIN - { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UMIN, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMIN, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048B0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UMIN, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABD - { .SABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SABD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048C0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .UABD - { .UABD, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .UABD, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABD, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x040D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x044D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x048D0000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .UABD, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .SABA - { .SABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SABA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UABA - { .UABA, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UABA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UABA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDP - { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDV - { .ADDV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ADDV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ADDV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLP - { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLP - { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADALP - { .SADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADALP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADALP - { .UADALP, {.V_4H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_1D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADALP, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_1D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADALP, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SADDLV - { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.H_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.H_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.S_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SADDLV, {.D_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UADDLV - { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.H_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.S_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UADDLV, {.D_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXV - { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMAXV - { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMINV - { .SMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UMINV - { .UMINV, {.B_REG,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.B_REG,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.H_REG,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.B_REG,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.B_REG,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.H_REG,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMAXP - { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMAXP - { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMINP - { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMINP - { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL - { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDL2 - { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL - { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDL2 - { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL - { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBL2 - { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL - { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBL2 - { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW - { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SADDW2 - { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW - { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UADDW2 - { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW - { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSUBW2 - { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW - { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USUBW2 - { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN - { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RADDHN2 - { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN - { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSUBHN2 - { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN - { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .ADDHN2 - { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN - { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SUBHN2 - { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .XTN - { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .XTN2 - { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .XTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN - { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTN2 - { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN - { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UQXTN2 - { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN - { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SQXTUN2 - { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SMULL - { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMULL2 - { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL - { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMULL2 - { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL - { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLAL2 - { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL - { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLAL2 - { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL - { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SMLSL2 - { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL - { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UMLSL2 - { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL - { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULL2 - { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL - { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLAL2 - { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL - { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMLSL2 - { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQDMULH - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRDMULH - { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SDOT - { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .UDOT - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .USDOT - { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, - { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_2S,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, + { .USDOT, {.V_4S,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {explicit_count=3} }, // .FMLA - { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65600000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A00000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLA, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMLS - { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, - { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, - { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65602000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A02000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_S,.NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {explicit_count=4} }, + { .FMLS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.IMM_2,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_D,.NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, // .FMULX - { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMULX, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMULX, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXP - { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINP - { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXNMP - { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMAXNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMAXNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMINNMP - { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FMINNMP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FMINNMP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FMAXV - { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINV - { .FMINV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMAXNMV - { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXNMV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMAXNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FMINNMV - { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINNMV, {.S_REG,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FMINNMV, {.H_REG,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPE - { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRECPE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRSQRTE - { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRSQRTE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FRSQRTE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRSQRTE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, // .FRECPS - { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRECPS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRSQRTS - { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FRSQRTS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FRSQRTS, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FRECPX - { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, - { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .FRECPX, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {explicit_count=2} }, + { .FRECPX, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FRECPX, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x654CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658CA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .FRECPX, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .FADDP - { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FADDP, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FADDP, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FCVTL - { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTL, {.V_4S,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTL2 - { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTL2, {.V_4S,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN - { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTN, {.V_4H_FP16,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTN2 - { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTN2, {.V_8H_FP16,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCVTN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN - { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTXN, {.V_2S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCVTXN2 - { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCVTXN2, {.V_4S,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .FCMEQ - { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMEQ, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMEQ, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGE - { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMGT - { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FCMGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FCMGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65404010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65804010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMLE - { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLE, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FCMLT - { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, - { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, - { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, + { .FCMLT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .FCMLT, {.V_4H_FP16,.V_4H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.V_8H_FP16,.V_8H_FP16,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {explicit_count=2} }, + { .FCMLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65512000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65912000, 0xFFFFE010, .SVE, {explicit_count=3} }, + { .FCMLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE,.NONE}, {.PD,.PG,.VN,.NONE,.NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, // .FACGE - { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGE, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGE, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .FACGT - { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, - { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .FACGT, {.V_4H_FP16,.V_4H_FP16,.V_4H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, + { .FACGT, {.V_8H_FP16,.V_8H_FP16,.V_8H_FP16,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {explicit_count=3} }, // .CMEQ - { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGE - { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMGT - { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHI - { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMHS - { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .CMLE - { .CMLE, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLE, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLE, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMLT - { .CMLT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CMLT, {.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CMLT, {.V_2D,.V_2D,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CMTST - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .MVN - { .MVN, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .MVN, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .MVN, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .MVN, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MVN, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .BIT - { .BIT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIT, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BIF - { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BIF, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .BSL - { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .SHL - { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHL - { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHL, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SQSHLU - { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHLU, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHL - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .URSHL - { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHR - { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USHR - { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSRA - { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .USRA - { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSHR - { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSHR - { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSHR, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRSRA - { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .URSRA - { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .URSRA, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHL - { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHL - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHL, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SLI - { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SLI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SRI - { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8B,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_16B,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4H,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_8H,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2S,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_4S,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SRI, {.V_2D,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {explicit_count=3} }, // .SSHLL - { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SSHLL2 - { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SSHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL - { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_8H,.V_8B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_4S,.V_4H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL, {.V_2D,.V_2S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .USHLL2 - { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_8H,.V_16B,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_4S,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .USHLL2, {.V_2D,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHL_IMM,.NONE,.NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SXTL - { .SXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_8H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_4S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SXTL2 - { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .SXTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL - { .UXTL, {.V_8H,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL, {.V_4S,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL, {.V_2D,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_8H,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_4S,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL, {.V_2D,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .UXTL2 - { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_8H,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_4S,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .UXTL2, {.V_2D,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SHRN - { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SHRN2 - { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN - { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .RSHRN2 - { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .RSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN - { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRN2 - { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN - { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQSHRN2 - { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN - { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRN2 - { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN - { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .UQRSHRN2 - { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .UQRSHRN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN - { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQSHRUN2 - { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN - { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_8B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_4H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN, {.V_2S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .SQRSHRUN2 - { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, - { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_16B,.V_8H,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_8H,.V_4S,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {explicit_count=3} }, + { .SQRSHRUN2, {.V_4S,.V_2D,.VEC_SHIFT,.NONE,.NONE}, {.VD,.VN,.NEON_SHR_IMM,.NONE,.NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {explicit_count=3} }, // .DUP - { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, - { .DUP, {.V_8B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_16B,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_8H,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_4S,.W_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.V_2D,.X_REG,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .DUP, {.V_8B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4H,.V_ELEM_H,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8H,.V_ELEM_H,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2S,.V_ELEM_S,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_4S,.V_ELEM_S,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_2D,.V_ELEM_D,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {explicit_count=3} }, + { .DUP, {.V_8B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_16B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_8H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_4S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.V_2D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .DUP, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .DUP, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .INS - { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, - { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, - { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.V_ELEM_B,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E010400, 0xFFE18400, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.V_ELEM_H,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E020400, 0xFFE38C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.V_ELEM_D,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E080400, 0xFFEFBC00, .NEON, {explicit_count=4} }, + { .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_H,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_S,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {explicit_count=3} }, + { .INS, {.V_ELEM_D,.VEC_INDEX,.X_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {explicit_count=3} }, // .MOV - { .MOV, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, - { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, - { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, - { .MOV, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .MOV, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, - { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, - { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, + { .MOV, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN_VM_DUP,.NONE,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {explicit_count=2} }, + { .MOV, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0520C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x0560C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .MOV, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.ZD_ZM_DUP,.PG,.VN,.NONE,.NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25004000, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .MOV, {.P_REG_B,.P_REG,.NONE,.NONE,.NONE}, {.PD,.PN_PG_PM_DUP,.NONE,.NONE,.NONE}, 0x25804000, 0xFFE0C210, .SVE, {explicit_count=2} }, + { .MOV, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .MOV, {.W_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0x320003E0, 0xFFC003E0, .BASE, {explicit_count=2} }, + { .MOV, {.X_REG,.BITMASK_IMM,.NONE,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true, explicit_count=2} }, // .EXT - { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, - { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX}, {.VD,.VN,.VM,.NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT}, {.VD,.VD,.VN,.SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.V_8B,.V_8B,.V_8B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x2E000000, 0xFFE0C400, .NEON, {explicit_count=4} }, + { .EXT, {.V_16B,.V_16B,.V_16B,.VEC_INDEX,.NONE}, {.VD,.VN,.VM,.NEON_EXT_IDX,.NONE}, 0x6E000000, 0xFFE08400, .NEON, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .EXT, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD,.VD,.VN,.SVE_EXT_IMM,.NONE}, 0x05200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .TBL - { .TBL, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .TBX - { .TBX, {.V_8B,.V_16B,.V_8B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN_LIST1,.VM,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .TBX, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .ZIP1 - { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .ZIP2 - { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .ZIP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .ZIP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .ZIP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .ZIP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP1 - { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204800, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .UZP2 - { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .UZP2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .UZP2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .UZP2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UZP2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN1 - { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN1, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN1, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN1, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205000, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .TRN2 - { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PM,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, + { .TRN2, {.V_8B,.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4H,.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2S,.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {explicit_count=3} }, + { .TRN2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TRN2, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TRN2, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PM,.NONE,.NONE}, 0x05205400, 0xFFE0FE10, .SVE, {explicit_count=3} }, // .NOT - { .NOT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, + { .NOT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .NOT, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4_PM_DUP,.PN,.NONE,.NONE}, 0x25004200, 0xFFE0C210, .SVE, {explicit_count=3} }, // .REV64 - { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_8H,.V_8H,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .REV64, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .CNT - { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, - { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, + { .CNT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .CNT, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x041AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049AA000, 0xFFFAE000, .SVE, {explicit_count=3} }, + { .CNT, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true, explicit_count=3} }, // .URECPE - { .URECPE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URECPE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URECPE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .URSQRTE - { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_2S,.V_2S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .URSQRTE, {.V_4S,.V_4S,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .MOVI - { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8B,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_16B,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_8H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MOVI, {.V_2D,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .MVNI - { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, - { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_8H,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_2S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, + { .MVNI, {.V_4S,.IMM_8,.NONE,.NONE,.NONE}, {.VD,.NEON_IMM8_FMOV,.NONE,.NONE,.NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {explicit_count=2} }, // .LD1 - { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .LD1, {.V_8H,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .LD1, {.V_4S,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .LD1, {.V_2D,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D400000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D404000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD2 - { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D600000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D604000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD3 - { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D402000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D406000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD4 - { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D602000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D606000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .LD4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST1 - { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, - { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, - { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, - { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007000, 0xFFFFF000, .NEON, {explicit_count=2} }, + { .ST1, {.V_8H,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007400, 0xFFFFF400, .NEON, {explicit_count=2} }, + { .ST1, {.V_4S,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007800, 0xFFFFF800, .NEON, {explicit_count=2} }, + { .ST1, {.V_2D,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST1, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D000000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D004000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST1, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST2 - { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST2, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D200000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D204000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST2, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST3 - { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST3, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D002000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D006000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST3, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .ST4 - { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, - { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, - { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .ST4, {.V_ELEM_B,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_B,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D202000, 0xBFFFE000, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_H,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_H,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D206000, 0xBFFFE400, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_S,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_S,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {explicit_count=3} }, + { .ST4, {.V_ELEM_D,.VEC_INDEX,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.NEON_LANE_D,.OFFSET_BASE_A,.NONE,.NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {explicit_count=3} }, // .LD1R - { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD1R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST1,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD2R - { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD2R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST2,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD3R - { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD3R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST3,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .LD4R - { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, + { .LD4R, {.V_16B,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.VD_LIST4,.OFFSET_BASE_A,.NONE,.NONE,.NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {explicit_count=2} }, // .SUBR - { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .SUBR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04030000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04430000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04830000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .ASRR - { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .ASRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04148000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04548000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04948000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .ASRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSLR - { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSLR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04178000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04578000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04978000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSLR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .LSRR - { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .LSRR, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04158000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04558000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04958000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .LSRR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FTSMUL - { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, // .FSUBR - { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FSUBR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65438000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65838000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FSUBR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FDIVR - { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VN}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, + { .FDIVR, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x654C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x658C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .FDIVR, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLA - { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65604000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A04000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .FNMLS - { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, - { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, + { .FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65606000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65A06000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=4} }, // .NAND - { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NAND, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .NOR - { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .NOR, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804200, 0xFFE0C210, .SVE, {explicit_count=4} }, // .SEL - { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, + { .SEL, {.P_REG_B,.P_REG,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25004210, 0xFFE0C210, .SVE, {explicit_count=4} }, // .ORRS - { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORRS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .EORS - { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .EORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NANDS - { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .NORS - { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .NORS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .ORNS - { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, + { .ORNS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, // .MOVS - { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, + { .MOVS, {.P_REG_B,.P_REG_ZERO,.P_REG,.NONE,.NONE}, {.PD,.PG4,.PN_PM_DUP,.NONE,.NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=3} }, // .PTRUE - { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, + { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, // .PTRUES - { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, + { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, // .PFALSE - { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.PD,.NONE,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA - { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB - { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, + { .BRKB, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25904010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKAS - { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKAS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKBS - { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, + { .BRKBS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.NONE,.NONE}, {.PD,.PG4,.PN,.NONE,.NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true, explicit_count=3} }, // .BRKPA - { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPA, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C000, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKPB - { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, + { .BRKPB, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x2500C010, 0xFFF0C210, .SVE, {explicit_count=4} }, // .BRKN - { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PD}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, + { .BRKN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PD,.NONE}, 0x25184000, 0xFFFFC210, .SVE, {explicit_count=4} }, // .RDFFR - { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, + { .RDFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE,.NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .WRFFR - { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, + { .WRFFR, {.P_REG_B,.NONE,.NONE,.NONE,.NONE}, {.PN,.NONE,.NONE,.NONE,.NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {explicit_count=1} }, // .SETFFR - { .SETFFR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, + { .SETFFR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {} }, // .CMPEQ - { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPNE - { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPNE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGE - { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPGT - { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPGT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPGT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLE - { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLE, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLT - { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLT, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLT, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHI - { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHI, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHI, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPHS - { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPHS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPHS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLO - { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLO, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .CMPLS - { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VM,.VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VM,.VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VM,.VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, - { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VM,.VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, + { .CMPLS, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true, explicit_count=4} }, + { .CMPLS, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VM,.VN,.NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true, explicit_count=4} }, // .FCMNE - { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMNE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806010, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMNE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .FCMUO - { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, - { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, + { .FCMUO, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6540C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x6580C000, 0xFFE0E010, .SVE, {explicit_count=4} }, + { .FCMUO, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, // .INSR - { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, - { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, + { .INSR, {.Z_REG_B,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05243800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_H,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05643800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, + { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, // .CPY - { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .CPY, {.Z_REG_B,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0528A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_H,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0568A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_S,.P_REG_MERGE,.W_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .CPY, {.Z_REG_D,.P_REG_MERGE,.X_REG,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .COMPACT - { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, - { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .COMPACT, {.Z_REG_S,.P_REG_GOV,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05A18000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .COMPACT, {.Z_REG_D,.P_REG_GOV,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, // .LD1B - { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1B, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1B, {.Z_PAIR_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0000000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1B, {.Z_QUAD_B,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0008000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1H - { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84804000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1H, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1H, {.Z_PAIR_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA0002000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1H, {.Z_QUAD_H,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA000A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1W - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, - { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x85004000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1W, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1W, {.Z_PAIR_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA0004000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .LD1W, {.Z_QUAD_S,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA000C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .LD1D - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1D, {.SME_SLICE_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_PAIR_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .LD1D, {.Z_QUAD_D,.PN_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LD1SB - { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SB, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84000000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SB, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SH - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, - { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA5204000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_S,.NONE,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .LD1SW - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC_D,.NONE,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B - { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1B, {.Z_QUAD_B,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA0208000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1H - { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1H, {.SME_SLICE_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0600000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1H, {.Z_PAIR_H,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA0202000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE4C08000, 0xFFE0A000, .SME, {explicit_count=3} }, // .ST1W - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, - { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, - { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_S,.NONE,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, + { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VECST_D,.NONE,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, // .LDFF1B - { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1H - { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1W - { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDFF1D - { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .WHILEGE - { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEGT - { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEGT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELE - { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELE, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI - { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHI, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS - { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILEHS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELO - { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELO, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELS - { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_B,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_H,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_S,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELS, {.P_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.PD,.RN,.RM,.NONE,.NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .SQRDMLAH - { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SQRDMLSH - { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLB - { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .ADCLT - { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLB - { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .SBCLT - { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, - { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .TBL2 - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .MATCH - { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .NMATCH - { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, - { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, + { .NMATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, // .HISTCNT - { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, - { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, + { .HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {explicit_count=4} }, + { .HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true, explicit_count=4} }, // .HISTSEG - { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .SMSTART - { .SMSTART, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, + { .SMSTART, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {} }, // .SMSTOP - { .SMSTOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, + { .SMSTOP, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {} }, // .RDSVL - { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, + { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, // .ADDHA - { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, + { .ADDHA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZA_TILE_LOW,.PG,.PM3,.VN,.NONE}, 0xC0900000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ADDVA - { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_LOW,.PG,.PM3,.VN}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, + { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZA_TILE_LOW,.PG,.PM3,.VN,.NONE}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ZERO - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, // .FMOPA - { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800000, 0xFFE08010, .SME, {explicit_count=5} }, // .FMOPS - { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800010, 0xFFE08010, .SME, {explicit_count=5} }, // .BFMOPA - { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800000, 0xFFE08010, .SME, {explicit_count=5} }, // .BFMOPS - { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {explicit_count=4} }, + { .BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x81800010, 0xFFE08010, .SME, {explicit_count=5} }, // .SMOPA - { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800000, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .SMOPS - { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=4} }, - { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0800010, 0xFFE08010, .SME, {explicit_count=5} }, + { .SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .UMOPA - { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00000, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .UMOPS - { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=4} }, - { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=4} }, + { .UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1A00010, 0xFFE08010, .SME, {explicit_count=5} }, + { .UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN,.VM}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true, explicit_count=5} }, // .USMOPA - { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=4} }, + { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=5} }, // .SUMOPA - { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=4} }, + { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=5} }, // .CNTB - { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTH - { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTW - { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .CNTD - { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .CNTD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .INCB - { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .INCH - { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .INCW - { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .INCD - { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .INCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .INCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECB - { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, // .DECH - { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECW - { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .DECD - { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .DECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .DECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCB - { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQINCH - { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCW - { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQINCD - { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQINCD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECB - { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECB, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, // .SQDECH - { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECH, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECW - { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECW, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .SQDECD - { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, - { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .SQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .SQDECD, {.X_REG,.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {explicit_count=4} }, + { .SQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCB - { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCH - { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCW - { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQINCD - { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQINCD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQINCD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECB - { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECB, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECH - { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECH, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECH, {.Z_REG_H,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECW - { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECW, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECW, {.Z_REG_S,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .UQDECD - { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, - { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, - { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, + { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .CNTP - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE,.NONE}, {.RD,.PG,.PN,.NONE,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, // .INCP - { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .DECP - { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQINCP - { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQDECP - { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE}, {.RD,.PN,.RD,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, - { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_H,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_S,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.X_REG,.P_REG_D,.W_REG,.NONE,.NONE}, {.RD,.PN,.RD,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=3} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQINCP - { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQDECP - { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .LD1Q - { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q - { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, + { .ST1Q, {.SME_SLICE_Q,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE,.NONE}, 0xE1E00000, 0xFFE00010, .SME, {explicit_count=3} }, // .MOVA - { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, - { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, + { .MOVA, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE,.NONE}, 0xC0020000, 0xFFE28010, .SME, {explicit_count=3} }, + { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, // .FCMLA - { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, - { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, + { .FCMLA, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCMLA_ROT,.NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {explicit_count=4} }, // .FCADD - { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, - { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2}, {.VD,.VN,.VM,.ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4H,.V_4H,.V_4H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_8H,.V_8H,.V_8H,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_4S,.V_4S,.V_4S,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {explicit_count=4} }, + { .FCADD, {.V_2D,.V_2D,.V_2D,.IMM_2,.NONE}, {.VD,.VN,.VM,.ENC_FCADD_ROT,.NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {explicit_count=4} }, // .PRFB - { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFB, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFH - { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFH, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFW - { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFW, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .PRFD - { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .PRFD, {.IMM_4,.P_REG_GOV,.MEM_SVE_SS,.NONE,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0x8580C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1B - { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1B, {.Z_REG_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xA400C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1H - { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1H, {.Z_REG_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xA480C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1W - { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .LDNT1W, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xA500C000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .LDNT1D - { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .LDNT1D, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .STNT1B - { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE4006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1H - { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1H, {.Z_REG_H,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE4806000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1W - { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, + { .STNT1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE5006000, 0xFFE0E000, .SVE, {explicit_count=3} }, // .STNT1D - { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, + { .STNT1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE,.NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, // .SPLICE - { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x052C8000, 0xFFFFE000, .SVE, {explicit_count=4} }, // .INDEX - { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE}, {.VD,.RN,.RM,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04204400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_B,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04604000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04604800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04604400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_H,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_S,.W_REG,.W_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.IMM_5,.X_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.IMM_5,.NONE,.NONE}, {.VD,.RN,.SVE_IMM5,.NONE,.NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .INDEX, {.Z_REG_D,.X_REG,.X_REG,.NONE,.NONE}, {.VD,.RN,.RM,.NONE,.NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, // .BSL1N - { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL1N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .BSL2N - { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .BSL2N, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .NBSL - { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D}, {.VD,.VD,.VM,.VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, + { .NBSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, // .PMUL - { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .PMUL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .PMULLB - { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLB, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .PMULLT - { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, + { .PMULLT, {.Z_REG_D,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, // .BFCVTNT - { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, + { .BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, // .LDRAA - { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAA, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .LDRAB - { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, - { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, + { .LDRAB, {.X_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true, explicit_count=2} }, // .TSTART - { .TSTART, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TSTART, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TCOMMIT - { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, + { .TCOMMIT, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {} }, // .TCANCEL - { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, + { .TCANCEL, {.IMM_16,.NONE,.NONE,.NONE,.NONE}, {.IMM16,.NONE,.NONE,.NONE,.NONE}, 0xD4600000, 0xFFE0001F, .BASE, {explicit_count=1} }, // .TTEST - { .TTEST, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TTEST, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFET - { .WFET, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .WFET, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .WFIT - { .WFIT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .WFIT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .BC_EQ - { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_EQ, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_NE - { .BC_NE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_CS - { .BC_CS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_CC - { .BC_CC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_CC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_MI - { .BC_MI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_MI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_PL - { .BC_PL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_PL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_VS - { .BC_VS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_VC - { .BC_VC, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_VC, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_HI - { .BC_HI, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_HI, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LS - { .BC_LS, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LS, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_GE - { .BC_GE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LT - { .BC_LT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_GT - { .BC_GT, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_GT, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_LE - { .BC_LE, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_LE, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_AL - { .BC_AL, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_AL, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .BC_NV - { .BC_NV, {.REL_19,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, + { .BC_NV, {.REL_19,.NONE,.NONE,.NONE,.NONE}, {.BRANCH_19,.NONE,.NONE,.NONE,.NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true, explicit_count=1} }, // .UXTB - { .UXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTH - { .UXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .UXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .UXTW - { .UXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .UXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .SXTB - { .SXTB, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTB, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTH - { .SXTH, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, + { .SXTH, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {explicit_count=2} }, // .SXTW - { .SXTW, {.X_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, + { .SXTW, {.X_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, // .ADC - { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .ADC, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .ADC, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .ADCS - { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .SBC - { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, + { .SBC, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {explicit_count=3} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true, explicit_count=3} }, // .SBCS - { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, - { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, + { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true, explicit_count=3} }, + { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true, explicit_count=3} }, // .NGC - { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, - { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, + { .NGC, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {explicit_count=2} }, + { .NGC, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true, explicit_count=2} }, // .NGCS - { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NGCS, {.W_REG,.W_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .LDAPUR - { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .STLUR - { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, - { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .STLUR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLUR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .LDAPURB - { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURB - { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLURB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURH - { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59400000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .STLURH - { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .STLURH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSB - { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSB, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSH - { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, - { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, + { .LDAPURSH, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSH, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {explicit_count=2} }, // .LDAPURSW - { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .LDAPURSW, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .BFADD - { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFADD, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65008000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFADD, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFSUB - { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFSUB, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65018000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFSUB, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMUL - { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, - { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFMUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65028000, 0xFFFFE000, .SVE, {explicit_count=4} }, + { .BFMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMLA - { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65200000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .BFMLS - { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, + { .BFMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.VM,.NONE}, 0x65202000, 0xFFE0E000, .SVE, {explicit_count=4} }, // .SB - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, + { .SB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {} }, // .CSDB - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {} }, // .DGH - { .DGH, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, + { .DGH, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {} }, // .PSB_CSYNC - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {} }, // .TSB_CSYNC - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {} }, // .BTI_J - { .BTI_J, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_J, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {} }, // .BTI_C - { .BTI_C, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, + { .BTI_C, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {} }, // .BTI_JC - { .BTI_JC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, + { .BTI_JC, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {} }, // .BFCLAMP - { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, + { .BFCLAMP, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .BFMAXNM - { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMAXNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65048000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .BFMINNM - { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VN}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, + { .BFMINNM, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x65058000, 0xFFFFE000, .SVE2, {explicit_count=4} }, // .LUTI2 - { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI2, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .LUTI4 - { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, - { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A4000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_H,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A5000, 0xFFFE7C00, .SME, {explicit_count=4} }, + { .LUTI4, {.Z_PAIR_S,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08A6000, 0xFFFE7C00, .SME, {explicit_count=4} }, // .ZIP - { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, - { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, + { .ZIP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE,.NONE}, 0xC120D000, 0xFFE0FC00, .SME, {explicit_count=3} }, + { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, // .UZP - { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, - { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, + { .UZP, {.Z_PAIR_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.ENC_Z_PAIR_VD,.VN,.VM,.NONE,.NONE}, 0xC120D001, 0xFFE0FC01, .SME, {explicit_count=3} }, + { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, // .TLBI_RPALOS - { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_RPALOS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_RPAOS - { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_RPAOS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1A - { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1A, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIPAPA - { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIPAPA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIGDPAPA - { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIGDPAPA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_PAALL - { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALL, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_PAALLOS - { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_PAALLOS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {} }, // .AMX_LDX - { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDY - { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STX - { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STY - { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZ - { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZ - { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZ, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_LDZI - { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_LDZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_STZI - { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_STZI, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRX - { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_EXTRY - { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_EXTRY, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA64 - { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA64, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS64 - { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS64, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA32 - { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA32, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS32 - { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS32, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MAC16 - { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MAC16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMA16 - { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMA16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_FMS16 - { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_FMS16, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_SET - { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, + { .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, // .AMX_CLR - { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, + { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, // .AMX_VECINT - { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_VECINT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_VECFP - { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_VECFP, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATINT - { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_MATFP - { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .AMX_GENLUT - { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, + { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, // .CPYP - { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYP, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYM - { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYE - { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFP - { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFP, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFM - { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFM, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .CPYFE - { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .CPYFE, {.XSP_REG,.XSP_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETP - { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETP, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true, explicit_count=3} }, // .SETM - { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, + { .SETM, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true, explicit_count=3} }, // .SETE - { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, + { .SETE, {.XSP_REG,.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RN,.RM,.NONE,.NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true, explicit_count=3} }, // .DC_IVAC - { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_IVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ISW - { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_ISW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CSW - { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CSW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CISW - { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CISW, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_ZVA - { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_ZVA, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAC - { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CVAU - { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CVAU, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .DC_CIVAC - { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .DC_CIVAC, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .IC_IALLUIS - { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, + { .IC_IALLUIS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {} }, // .IC_IALLU - { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, + { .IC_IALLU, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {} }, // .IC_IVAU - { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .IC_IVAU, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1R - { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E1W - { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E1W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0R - { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E0R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E0W - { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E0W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2R - { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E2R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E2W - { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E2W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3R - { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E3R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S1E3W - { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S1E3W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1R - { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E1R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E1W - { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E1W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0R - { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E0R, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .AT_S12E0W - { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .AT_S12E0W, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VMALLE1 - { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_VMALLE1, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VMALLE1IS - { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_VMALLE1IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_VAE1 - { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAE1IS - { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1 - { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_ASIDE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ASIDE1IS - { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_ASIDE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1 - { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAAE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAAE1IS - { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAAE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1 - { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VALE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VALE1IS - { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VALE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1 - { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAALE1, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_VAALE1IS - { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, + { .TLBI_VAALE1IS, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true, explicit_count=1} }, // .TLBI_ALLE1 - { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE1, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE1IS - { .TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE1IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE2 - { .TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE2, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE2IS - { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE2IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE3 - { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE3, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {} }, // .TLBI_ALLE3IS - { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, + { .TLBI_ALLE3IS, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {} }, // .PRFM - { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, - { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, + { .PRFM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, + { .PRFM, {.IMM_5,.REL_19,.NONE,.NONE,.NONE}, {.RT,.BRANCH_19,.NONE,.NONE,.NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true, explicit_count=2} }, // .PRFUM - { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, + { .PRFUM, {.IMM_5,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true, explicit_count=2} }, // .NEGS - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, - { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true, explicit_count=2} }, + { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMP - { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.W_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.X_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMP, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMP, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, // .CMN - { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, - { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, - { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.W_REG,.W_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.X_REG,.X_SHIFTED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.W_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.X_EXTENDED,.NONE,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, + { .CMN, {.WSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true, explicit_count=2} }, + { .CMN, {.XSP_REG,.IMM_12,.NONE,.NONE,.NONE}, {.RN,.IMM12,.NONE,.NONE,.NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true, explicit_count=2} }, } @(rodata) diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index d9ed00761..89a3fbc05 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -105,4384 +105,4384 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = { }, .ADD = { - {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04000000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04400000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04800000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x11000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADD, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8B000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04200000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04600000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04000000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04400000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04800000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ADDS = { - {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x31000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xB1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ADDS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SUB = { - {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04010000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04410000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04810000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x51000000, 0xFF800000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xD1000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUB, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4B000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCB000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.WSP_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4B200000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.XSP_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCB200000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE08400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04200400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04600400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUB, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04010000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04410000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04810000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C10000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SUBS = { - {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE}, {.RD, .RN, .IMM12, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0x71000000, 0xFF800000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .IMM_12, .NONE, .NONE}, {.RD, .RN, .IMM12, .NONE, .NONE}, 0xF1000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6B000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEB000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.W_REG, .WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6B200000, 0xFFE00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBS, {.X_REG, .XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEB200000, 0xFFE00000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVZ = { - {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVZ, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x52800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVZ, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVN = { - {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVN, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x12800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVN, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x92800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .MOVK = { - {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, - {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOVK, {.W_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0x72800000, 0xFF800000, .BASE, {}}, Clobber{written={0}}}, + {{.MOVK, {.X_REG, .IMM_16, .HW_SHIFT, .NONE, .NONE}, {.RD, .IMM16, .IMM_HW, .NONE, .NONE}, 0xF2800000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .ADR = { - {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, + {{.ADR, {.X_REG, .REL_PG21, .NONE, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE, .NONE}, 0x10000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .ADRP = { - {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, + {{.ADRP, {.X_REG, .REL_PG21, .NONE, .NONE, .NONE}, {.RD, .BRANCH_PG21, .NONE, .NONE, .NONE}, 0x90000000, 0x9F000000, .BASE, {}}, Clobber{written={0}}}, }, .AND = { - {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.AND, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8A000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x12000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.AND, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x92000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.AND, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.AND, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x041A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x045A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x049A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04DA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.AND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ANDS = { - {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6A000000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEA000000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.W_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.X_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF2000000, 0xFF800000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORR = { - {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04180000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x32000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xB2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ORR, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04180000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04580000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04980000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EOR = { - {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04190000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4A000000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCA000000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.WSP_REG, .W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0x52000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.XSP_REG, .X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .RN, .BITMASK_FIELD, .NONE, .NONE}, 0xD2000000, 0xFF800000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.EOR, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EOR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04190000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04590000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04990000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BIC = { - {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x041B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x0A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x8A200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BIC, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x041B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x045B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x049B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04DB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BIC, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BICS = { - {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x6A200000, 0xFF200000, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xEA200000, 0xFF200000, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BICS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORN = { - {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ORN, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x2A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xAA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ORN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804010, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .EON = { - {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE}, {.RD, .RN, .RM, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.W_REG, .W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x4A200000, 0xFF200000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EON, {.X_REG, .X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xCA200000, 0xFF200000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LSL = { - {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04138000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04538000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04938000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04138000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04538000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04938000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSL, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_LSL_IMM_W, .NONE, .NONE}, 0x53000000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSL, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_LSL_IMM_X, .NONE, .NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .LSR = { - {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04118000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04518000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04918000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02400, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.LSR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04118000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04518000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04918000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x53007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.LSR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0xD340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ASR = { - {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04108000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04508000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04908000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ASR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04108000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04508000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04908000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x13007C00, 0xFFC0FC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ASR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .RN, .ENC_SHIFT_IMMR, .NONE, .NONE}, 0x9340FC00, 0xFFC0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ROR = { - {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC02C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC02C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ROR, {.W_REG, .W_REG, .IMM_5, .NONE, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE, .NONE}, 0x13800000, 0xFFE00000, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.ROR, {.X_REG, .X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_DUAL_RN_RM, .ENC_ROR_SHIFT, .NONE, .NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .UDIV = { - {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04950000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC00800, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00800, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04950000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D50000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SDIV = { - {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04940000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC00C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04940000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D40000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MADD = { - {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.W_REG, .W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1B000000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MADD, {.X_REG, .X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B000000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MSUB = { - {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG}, {.RD, .RN, .RM, .RA}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.W_REG, .W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1B008000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MSUB, {.X_REG, .X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B008000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMADDL = { - {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMADDL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMSUBL = { - {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9B208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMADDL = { - {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMADDL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9BA00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMSUBL = { - {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG}, {.RD, .RN, .RM, .RA}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMSUBL, {.X_REG, .W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x9BA08000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMULH = { - {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04120000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04520000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04920000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9B407C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04120000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04520000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04920000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D20000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMULH = { - {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04130000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04530000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04930000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9BC07C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULH, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04130000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04530000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04930000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMULH, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .CLZ = { - {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC01000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC01000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLZ, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0419A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0459A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0499A000, 0xFFF9E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D9A000, 0xFFF9E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CLS = { - {{.CLS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC01400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC01400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CLS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0418A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0458A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0498A000, 0xFFF8E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .RBIT = { - {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00000, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00000, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RBIT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV = { - {{.REV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00800, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05383800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_H, .Z_REG_H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05783800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_S, .Z_REG_S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.REV, {.Z_REG_D, .Z_REG_D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV, {.P_REG_B, .P_REG_B, .NONE, .NONE, .NONE}, {.PD, .PN, .NONE, .NONE, .NONE}, 0x05344000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1}}}, }, .REV16 = { - {{.REV16, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV16, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5AC00400, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00400, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV16, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .REV32 = { - {{.REV32, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV32, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC00800, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV32, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CSEL = { - {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSEL, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x9A800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINC = { - {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINC, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x9A800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSINV = { - {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x5A800000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSINV, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0xDA800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSNEG = { - {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.W_REG, .W_REG, .W_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x5A800400, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSNEG, {.X_REG, .X_REG, .X_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0xDA800400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMP = { - {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .W_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .X_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.W_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0x7A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMP, {.X_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0xFA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CCMN = { - {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND}, {.RN, .RM, .NZCV_FIELD, .COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .W_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0x3A400000, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .X_REG, .NZCV_IMM, .COND, .NONE}, {.RN, .RM, .NZCV_FIELD, .COND_HI, .NONE}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.W_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0x3A400800, 0xFFE00C10, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CCMN, {.X_REG, .IMM_5, .NZCV_IMM, .COND, .NONE}, {.RN, .IMM5_HI, .NZCV_FIELD, .COND_HI, .NONE}, 0xBA400800, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSET = { - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9F07E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9F87E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x1A9FC7E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9F07E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9F87E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSET, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x9A9FC7E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CSETM = { - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9F03E0, 0xFFFF8FE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9F83E0, 0xFFFFCFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.W_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0x5A9FC3E0, 0xFFFFEFE0, .BASE, {}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9F03E0, 0xFFFF8FE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9F83E0, 0xFFFFCFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CSETM, {.X_REG, .COND_NOT_AL, .NONE, .NONE, .NONE}, {.RD, .COND_HI_INV, .NONE, .NONE, .NONE}, 0xDA9FC3E0, 0xFFFFEFE0, .BASE, {is_64=true}}, Clobber{written={0}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINC = { - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x1A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINC, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x9A80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CINV = { - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A800000, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A808000, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A80C000, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA800000, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA808000, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CINV, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA80C000, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .CNEG = { - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A800400, 0xFFE08C00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A808400, 0xFFE0CC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.W_REG, .W_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0x5A80C400, 0xFFE0EC00, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA800400, 0xFFE08C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA808400, 0xFFE0CC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.CNEG, {.X_REG, .X_REG, .COND_NOT_AL, .NONE, .NONE}, {.RD, .RN_RM, .COND_HI_INV, .NONE, .NONE}, 0xDA80C400, 0xFFE0EC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.N, .Z, .C, .V}}}, }, .EXTR = { - {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6}, {.RD, .RN, .RM, .IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.W_REG, .W_REG, .W_REG, .IMM_6, .NONE}, {.RD, .RN, .RM, .IMM6, .NONE}, 0x13800000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXTR, {.X_REG, .X_REG, .X_REG, .IMM_6, .NONE}, {.RD, .RN, .RM, .IMM6, .NONE}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .B = { - {{.B, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B, {.REL_26, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE, .NONE}, 0x14000000, 0xFC000000, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BL = { - {{.BL, {.REL_26, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BL, {.REL_26, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_26, .NONE, .NONE, .NONE, .NONE}, 0x94000000, 0xFC000000, .BASE, {branch=true}}, Clobber{implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .BR = { - {{.BR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.BR, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .BLR = { - {{.BLR, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, + {{.BLR, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL}}}, }, .RET = { - {{.RET, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, + {{.RET, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD65F0000, 0xFFFFFC1F, .BASE, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F03C0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR}, side_effects={.CONTROL}}}, }, .B_EQ = { - {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_EQ, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000000, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_NE = { - {{.B_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.B_NE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000001, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .B_CS = { - {{.B_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000002, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_CC = { - {{.B_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.B_CC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000003, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .B_MI = { - {{.B_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_MI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000004, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_PL = { - {{.B_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.B_PL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000005, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .B_VS = { - {{.B_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000006, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_VC = { - {{.B_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.B_VC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000007, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .B_HI = { - {{.B_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_HI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000008, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_LS = { - {{.B_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.B_LS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000009, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .B_GE = { - {{.B_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_GE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_LT = { - {{.B_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.B_LT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .B_GT = { - {{.B_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_GT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_LE = { - {{.B_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.B_LE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .B_AL = { - {{.B_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B_AL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .B_NV = { - {{.B_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.B_NV, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400000F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .CBZ = { - {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x34000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBZ, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xB4000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .CBNZ = { - {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, - {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x35000000, 0xFF000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.CBNZ, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xB5000000, 0xFF000000, .BASE, {cond_branch=true, is_64=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBZ = { - {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.TBZ, {.X_REG, .IMM_5, .REL_14, .NONE, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE, .NONE}, 0x36000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .TBNZ = { - {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, + {{.TBNZ, {.X_REG, .IMM_5, .REL_14, .NONE, .NONE}, {.RT, .TBZ_BIT, .BRANCH_14, .NONE, .NONE}, 0x37000000, 0x7F000000, .BASE, {cond_branch=true}}, Clobber{read={0}, side_effects={.CONTROL}}}, }, .LDR = { - {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, - {{.LDR, {.X_REG, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, - {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x18000000, 0xFF000000, .BASE, {}}, Clobber{written={0}}}, + {{.LDR, {.X_REG, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0x58000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.LDR, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xB8400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8400C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xB8400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xF8400400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDR, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xF8600800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.B_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.H_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x7D400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xBD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { - {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xB8000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8000C00, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xB8000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0xF8000400, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STR, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xF8200800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.B_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.H_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x7D000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xBD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { - {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x38400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x38400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRB = { - {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x38000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x38000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSB = { - {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSB, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x38A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRH = { - {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, - {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x78400C00, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x78400400, 0xFFE00C00, .BASE, {}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78600800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STRH = { - {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, - {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0x78000C00, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_POST, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_POST, .NONE, .NONE, .NONE}, 0x78000400, 0xFFE00C00, .BASE, {}}, Clobber{written={1}, read={0, 1}, writes_mem=true}}, + {{.STRH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78200800, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDRSH = { - {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x79C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.W_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78E00800, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSH, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0x78A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDRSW = { - {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRSW, {.X_REG, .MEM_REG, .NONE, .NONE, .NONE}, {.RT, .OFFSET_REG, .NONE, .NONE, .NONE}, 0xB8A00800, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDP = { - {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.W_REG, .W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28C00000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x2D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0x6D400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0xAD400000, 0xFFC00000, .NEON, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STP = { - {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x29800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.W_REG, .W_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28800000, 0xFFC00000, .BASE, {}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={2}, read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.S_REG, .S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x2D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.D_REG, .D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0x6D000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STP, {.Q_REG, .Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0xAD000000, 0xFFC00000, .NEON, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDPSW = { - {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, - {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x69400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x69C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, + {{.LDPSW, {.X_REG, .X_REG, .MEM_POST, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x68C00000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={2}, reads_mem=true}}, }, .LDAR = { - {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLR = { - {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC89FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARB = { - {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x08DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRB = { - {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x089FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDARH = { - {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDARH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x48DFFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLRH = { - {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x489FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDXR = { - {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x885F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC85F7C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXR = { - {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x88007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC8007C00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXR = { - {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x885FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xC85FFC00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXR = { - {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x8800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXR, {.W_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xC800FC00, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .NOP = { - {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .YIELD = { - {{.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.YIELD, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503203F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .WFE = { - {{.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, + {{.WFE, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503205F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .WFI = { - {{.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, + {{.WFI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503207F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.WAIT}}}, }, .SEV = { - {{.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.SEV, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503209F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .SEVL = { - {{.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.SEVL, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320BF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .HINT = { - {{.HINT, {.IMM_8, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.HINT, {.IMM_8, .NONE, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD503201F, 0xFFFFF01F, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .MRS = { - {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MRS, {.X_REG, .SYS_REG, .NONE, .NONE, .NONE}, {.RT, .SYS_FIELD, .NONE, .NONE, .NONE}, 0xD5300000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .MSR = { - {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, - {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, + {{.MSR, {.PSTATE_FIELD, .IMM_4, .NONE, .NONE, .NONE}, {.MSR_PSTATE, .BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD500401F, 0xFFF8F01F, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.MSR, {.SYS_REG, .X_REG, .NONE, .NONE, .NONE}, {.SYS_FIELD, .RT, .NONE, .NONE, .NONE}, 0xD5100000, 0xFFF00000, .BASE, {}}, Clobber{written={0}, read={1}, side_effects={.PRIVILEGED}}}, }, .ISB = { - {{.ISB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, + {{.ISB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD50330DF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.ISYNC}}}, }, .DSB = { - {{.DSB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.DSB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD503309F, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DMB = { - {{.DMB, {.IMM_4, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.DMB, {.IMM_4, .NONE, .NONE, .NONE, .NONE}, {.BARRIER_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xD50330BF, 0xFFFFF0FF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .SVC = { - {{.SVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, + {{.SVC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000001, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION}}}, }, .HVC = { - {{.HVC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.HVC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000002, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .SMC = { - {{.SMC, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, + {{.SMC, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4000003, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .EXCEPTION, .PRIVILEGED}}}, }, .BRK = { - {{.BRK, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, + {{.BRK, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4200000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .HLT = { - {{.HLT, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, + {{.HLT, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4400000, 0xFFE0001F, .BASE, {branch=true}}, Clobber{side_effects={.CONTROL, .TRAP}}}, }, .ERET = { - {{.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, + {{.ERET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PRIVILEGED}}}, }, .FMOV = { - {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, - {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, - {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, - {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, - {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, Clobber{written={0}}}, + {{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, + {{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, Clobber{written={0}}}, }, .FABS = { - {{.FABS, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049CA000, 0xFFFCE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DCA000, 0xFFFCE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FNEG = { - {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, - {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E214000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E614000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE14000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF8F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}}}, + {{.FNEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049DA000, 0xFFFDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.FNEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .FSQRT = { - {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E21C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E61C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE1C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x654DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658DA000, 0xFFEDE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSQRT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65CDA000, 0xFFEDE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC, .IDC}, reads_fpcr=true}}, }, .FADD = { - {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65408000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65808000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E202800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E602800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE02800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65408000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65808000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C08000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUB = { - {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65418000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65818000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E203800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E603800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE03800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65418000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65818000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUB, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMUL = { - {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65428000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65828000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E200800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E600800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE00800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65428000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65828000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C28000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIV = { - {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E201800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E601800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE01800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x654D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x658D8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65CD8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMUL = { - {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E208800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E608800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMUL, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE08800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMADD = { - {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F000000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F400000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMADD, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FC00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMSUB = { - {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F008000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F408000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMSUB, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FC08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMADD = { - {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F200000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F600000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMADD, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FE00000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMSUB = { - {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG}, {.RD, .RN, .RM, .RA}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG}, {.RD, .RN, .RM, .RA}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG}, {.RD, .RN, .RM, .RA}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.S_REG, .S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F208000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.D_REG, .D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1F608000, 0xFFE08000, .FP, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FNMSUB, {.H_REG, .H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .RA, .NONE}, 0x1FE08000, 0xFFE08000, .FP16, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCMP = { - {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E202000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E602000, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMP, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1EE02000, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCMPE = { - {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, - {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E202010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1E602010, 0xFFE0FC1F, .FP, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, + {{.FCMPE, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x1EE02010, 0xFFE0FC1F, .FP16, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}, fpsr_wr={.IOC}}}, }, .FCSEL = { - {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, - {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND}, {.RD, .RN, .RM, .COND_HI}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.S_REG, .S_REG, .S_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1E200C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.D_REG, .D_REG, .D_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1E600C00, 0xFFE00C00, .FP, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, + {{.FCSEL, {.H_REG, .H_REG, .H_REG, .COND, .NONE}, {.RD, .RN, .RM, .COND_HI, .NONE}, 0x1EE00C00, 0xFFE00C00, .FP16, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.N, .Z, .C, .V}}}, }, .FMAX = { - {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65468000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65868000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E204800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E604800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE04800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65468000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65868000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C68000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMIN = { - {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65478000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65878000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E205800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E605800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE05800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65478000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65878000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNM = { - {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65448000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65848000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E206800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E606800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE06800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65448000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65848000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNM = { - {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65458000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65858000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.S_REG, .S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E207800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.D_REG, .D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1E607800, 0xFFE0FC00, .FP, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.H_REG, .H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1EE07800, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65458000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65858000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FCVT = { - {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E22C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E624000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E23C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.H_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E63C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.S_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE24000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVT, {.D_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE2C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SCVTF = { - {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E220000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E620000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.S_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E220000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E620000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.H_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE20000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.SCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .UCVTF = { - {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, - {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E230000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E630000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.S_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E230000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E630000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.H_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE30000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, + {{.UCVTF, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IXC}, reads_fpcr=true}}, }, .FCVTZS = { - {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E380000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E780000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E380000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E780000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTZU = { - {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E390000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E790000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E390000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E790000, 0xFFFFFC00, .FP, {is_64=true}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTZU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAS = { - {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E240000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E640000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE40000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTAU = { - {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E250000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E650000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE50000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTAU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNS = { - {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E200000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E600000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTNU = { - {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E210000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E610000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTNU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPS = { - {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E280000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E680000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE80000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTPU = { - {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E290000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E690000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EE90000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTPU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9A800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMS = { - {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E300000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E700000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EF00000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMS, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTMU = { - {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, - {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.W_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E310000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E710000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.X_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EF10000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E21B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E61B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTMU, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E79B800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FRINTA = { - {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E264000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E664000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE64000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6544A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6584A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C4A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTI = { - {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, - {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E27C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E67C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE7C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6547A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6587A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, + {{.FRINTI, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C7A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}, reads_fpcr=true}}, }, .FRINTM = { - {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E254000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E654000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE54000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6542A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6582A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTM, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C2A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTN = { - {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E244000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E644000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE44000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E218800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E618800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E798800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6540A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6580A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C0A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTP = { - {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E24C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E64C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE4C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE18800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF98800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6541A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6581A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTP, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C1A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FRINTX = { - {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, - {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E274000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E674000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE74000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E219800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E619800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E799800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6546A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6586A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, + {{.FRINTX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C6A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IXC}, reads_fpcr=true}}, }, .FRINTZ = { - {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E25C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E65C000, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE5C000, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE19800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF99800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6543A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x6583A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FRINTZ, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .TST = { - {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x7200001F, 0xFFC0001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RN, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xF200001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.TST, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDUR = { - {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xBC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xFC400000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x3CC00000, 0xFFE00C00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STUR = { - {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.S_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xBC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.D_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xFC000000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STUR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x3C800000, 0xFFE00C00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURB = { - {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURB = { - {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSB = { - {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x38C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURH = { - {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STURH = { - {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, }, .LDURSH = { - {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x78C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDURSW = { - {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xB8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LDNP = { - {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, - {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28400000, 0xFFC00000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, + {{.LDNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8400000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true}}, }, .STNP = { - {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_4, .NONE, .NONE}, 0x28000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_8, .NONE, .NONE}, 0xA8000000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDXP = { - {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0x887F0000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0xC87F0000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXP = { - {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, - {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x88200000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC8200000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXP = { - {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0x887F8000, 0xFFFF8000, .BASE, {}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_BASE_A, .NONE, .NONE}, 0xC87F8000, 0xFFFF8000, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={2}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXP = { - {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, - {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET}, {.RD, .RT, .RT2, .OFFSET_BASE_A}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0x88208000, 0xFFE08000, .BASE, {}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXP, {.W_REG, .X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .RT2, .OFFSET_BASE_A, .NONE}, 0xC8208000, 0xFFE08000, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRB = { - {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x085F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRB = { - {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x08007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRB = { - {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x085FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRB = { - {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x0800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDXRH = { - {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.LDXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x485F7C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .STXRH = { - {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, + {{.STXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x48007C00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.ATOMIC, .RESERVATION}}}, }, .LDAXRH = { - {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.LDAXRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x485FFC00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .STLXRH = { - {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, + {{.STLXRH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RD, .RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x4800FC00, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, writes_mem=true, side_effects={.FENCE, .ATOMIC, .RESERVATION}}}, }, .LDAPR = { - {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xB8BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xF8BFC000, 0xFFFFFC00, .LSE2, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRB = { - {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x38BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPRH = { - {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPRH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x78BFC000, 0xFFFFFC00, .LSE2, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDADD = { - {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8200000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDADD, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8200000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDADDA = { - {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDL = { - {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8600000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8600000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDADDAL = { - {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E00000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDADDAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E00000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLR = { - {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8201000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDCLR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8201000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDCLRA = { - {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRL = { - {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8601000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8601000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDCLRAL = { - {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E01000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDCLRAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E01000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEOR = { - {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8202000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDEOR, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8202000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDEORA = { - {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORL = { - {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8602000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8602000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDEORAL = { - {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E02000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDEORAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E02000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSET = { - {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8203000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSET, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8203000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSETA = { - {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETL = { - {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8603000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8603000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSETAL = { - {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E03000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSETAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E03000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAX = { - {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8204000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8204000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMAXA = { - {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXL = { - {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8604000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8604000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMAXAL = { - {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E04000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E04000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMIN = { - {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8205000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDSMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8205000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDSMINA = { - {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINL = { - {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8605000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8605000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDSMINAL = { - {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E05000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDSMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E05000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAX = { - {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8206000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMAX, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8206000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMAXA = { - {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXL = { - {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8606000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8606000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMAXAL = { - {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E06000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMAXAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E06000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMIN = { - {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8207000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.LDUMIN, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8207000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .LDUMINA = { - {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINL = { - {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8607000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8607000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .LDUMINAL = { - {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E07000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.LDUMINAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E07000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWP = { - {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8208000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.SWP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8208000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .SWPA = { - {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8A08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8A08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPL = { - {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8608000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8608000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .SWPAL = { - {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xB8E08000, 0xFFE0FC00, .LSE, {}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.SWPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xF8E08000, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={1}, read={0, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CAS = { - {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CAS, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8A07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASA = { - {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8E07C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASL = { - {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8A0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASAL = { - {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x88E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0xC8E0FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASB = { - {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAB = { - {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLB = { - {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALB = { - {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALB, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASH = { - {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48A07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASAH = { - {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASAH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48E07C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASLH = { - {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASLH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48A0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASALH = { - {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASALH, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48E0FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASP = { - {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, - {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08207C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, + {{.CASP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48207C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.ATOMIC}}}, }, .CASPA = { - {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x08607C00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPA, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x48607C00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPL = { - {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x0820FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x4820FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .CASPAL = { - {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, - {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.W_REG, .W_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x0860FC00, 0xFFE0FC00, .LSE, {}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, + {{.CASPAL, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.ATOMIC_RS, .ATOMIC_RT, .ATOMIC_RN, .NONE, .NONE}, 0x4860FC00, 0xFFE0FC00, .LSE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, writes_mem=true, reads_mem=true, side_effects={.FENCE, .ATOMIC}}}, }, .PACIA = { - {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIB = { - {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACIB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDA = { - {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACDB = { - {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.PACDB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC10C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .PACIZA = { - {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC123E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIZB = { - {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACIZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC127E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZA = { - {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC12BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACDZB = { - {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.PACDZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC12FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIA = { - {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11000, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIB = { - {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTIB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11400, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDA = { - {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11800, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTDB = { - {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, + {{.AUTDB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1}, side_effects={.PAC}}}, }, .AUTIZA = { - {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC133E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTIZB = { - {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTIZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC137E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZA = { - {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC13BE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .AUTDZB = { - {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.AUTDZB, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC13FE0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .PACIASP = { - {{.PACIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIASP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503233F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIBSP = { - {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.PACIBSP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503237F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIASP = { - {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIASP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50323BF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .AUTIBSP = { - {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, + {{.AUTIBSP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50323FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR, .SP}, side_effects={.PAC}}}, }, .PACIA1716 = { - {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIA1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503211F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACIB1716 = { - {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.PACIB1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503215F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIA1716 = { - {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIA1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503219F, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .AUTIB1716 = { - {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, + {{.AUTIB1716, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50321DF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.X17}, implicit_rd={.X16, .X17}, side_effects={.PAC}}}, }, .PACGA = { - {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, + {{.PACGA, {.X_REG, .X_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC03000, 0xFFE0FC00, .PAC, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, side_effects={.PAC}}}, }, .XPACI = { - {{.XPACI, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC143E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACD = { - {{.XPACD, {.X_REG, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, + {{.XPACD, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE, .NONE}, 0xDAC147E0, 0xFFFFFFE0, .PAC, {is_64=true}}, Clobber{written={0}, read={0}, side_effects={.PAC}}}, }, .XPACLRI = { - {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, + {{.XPACLRI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320FF, 0xFFFFFFFF, .PAC, {}}, Clobber{implicit_wr={.LR}, implicit_rd={.LR}, side_effects={.PAC}}}, }, .RETAA = { - {{.RETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAA, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .RETAB = { - {{.RETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, + {{.RETAB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD65F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{implicit_rd={.LR, .SP}, side_effects={.CONTROL, .PAC}}}, }, .BRAA = { - {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD71F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAB = { - {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, + {{.BRAB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD71F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, side_effects={.CONTROL, .PAC}}}, }, .BRAAZ = { - {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRAAZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BRABZ = { - {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, + {{.BRABZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD61F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, side_effects={.CONTROL, .PAC}}}, }, .BLRAA = { - {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAA, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD73F0800, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAB = { - {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAB, {.X_REG, .XSP_REG, .NONE, .NONE, .NONE}, {.RN, .RD, .NONE, .NONE, .NONE}, 0xD73F0C00, 0xFFFFFC00, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0, 1}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRAAZ = { - {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRAAZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F081F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .BLRABZ = { - {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, + {{.BLRABZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RN, .NONE, .NONE, .NONE, .NONE}, 0xD63F0C1F, 0xFFFFFC1F, .PAC, {branch=true, writes_pc=true}}, Clobber{read={0}, implicit_wr={.LR}, side_effects={.CONTROL, .PAC}}}, }, .ERETAA = { - {{.ERETAA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAA, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F0BFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .ERETAB = { - {{.ERETAB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, + {{.ERETAB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F0FFF, 0xFFFFFFFF, .PAC, {branch=true, writes_pc=true}}, Clobber{side_effects={.CONTROL, .PAC, .PRIVILEGED}}}, }, .BTI = { - {{.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503241F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .IRG = { - {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.IRG, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC01000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADDG = { - {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.ADDG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4, .NONE}, {.RD, .RN, .IMM6, .IMM_HW, .NONE}, 0x91800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SUBG = { - {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4}, {.RD, .RN, .IMM6, .IMM_HW}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SUBG, {.XSP_REG, .XSP_REG, .IMM_6, .IMM_4, .NONE}, {.RD, .RN, .IMM6, .IMM_HW, .NONE}, 0xD1800000, 0xFFC0C000, .MTE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .GMI = { - {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.GMI, {.X_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC01400, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBP = { - {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBP, {.X_REG, .XSP_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC00000, 0xFFE0FC00, .MTE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SUBPS = { - {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.SUBPS, {.X_REG, .XSP_REG, .XSP_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xBAC00000, 0xFFE0FC00, .MTE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .LDG = { - {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9600000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STG = { - {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9200800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .ST2G = { - {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9A00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZG = { - {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZG, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9600800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZ2G = { - {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZ2G, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9E00800, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STGP = { - {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STGP, {.X_REG, .X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .RT2, .OFFSET_PAIR_16, .NONE, .NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDGM = { - {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9E00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .STGM = { - {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9A00000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .STZGM = { - {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STZGM, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0xD9200000, 0xFFE00C00, .MTE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true}}, }, .CRC32B = { - {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32B, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32H = { - {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32H, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32W = { - {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32W, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC04800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32X = { - {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32X, {.W_REG, .W_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC04C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CB = { - {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CB, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05000, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CH = { - {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CH, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05400, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CW = { - {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CW, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1AC05800, 0xFFE0FC00, .CRC32, {}}, Clobber{written={0}, read={1, 2}}}, }, .CRC32CX = { - {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CRC32CX, {.W_REG, .W_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .AESE = { - {{.AESE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E284800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESE, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .VN, .NONE, .NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESD = { - {{.AESD, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VD, .VN, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E285800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .VN, .NONE, .NONE}, 0x4522E400, 0xFFFFFC00, .SVE2, {}}, Clobber{written={0}, read={0, 1}}}, }, .AESMC = { - {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESMC, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E286800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE, .NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .AESIMC = { - {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, - {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, + {{.AESIMC, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E287800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.AESIMC, {.Z_REG_B, .Z_REG_B, .NONE, .NONE, .NONE}, {.VD, .VD, .NONE, .NONE, .NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {}}, Clobber{written={0}, read={0}}}, }, .SHA1H = { - {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, + {{.SHA1H, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E280800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={1}}}, }, .SHA1C = { - {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1C, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E000000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1P = { - {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1P, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E001000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1M = { - {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1M, {.Q_REG, .S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E002000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU0 = { - {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA1SU0, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E003000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA1SU1 = { - {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA1SU1, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E281800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256H = { - {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256H, {.Q_REG, .Q_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E004000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256H2 = { - {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256H2, {.Q_REG, .Q_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E005000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA256SU0 = { - {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA256SU0, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x5E282800, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA256SU1 = { - {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA256SU1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x5E006000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H = { - {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512H, {.Q_REG, .Q_REG, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512H2 = { - {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512H2, {.Q_REG, .Q_REG, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SHA512SU0 = { - {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SHA512SU0, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0xCEC08000, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SHA512SU1 = { - {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SHA512SU1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .EOR3 = { - {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.V_16B, .V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE000000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.EOR3, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BCAX = { - {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B}, {.VD, .VN, .VM, .VA}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.V_16B, .V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE200000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BCAX, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RAX1 = { - {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RAX1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .XAR = { - {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6}, {.VD, .VN, .VM, .IMM6}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6, .NONE}, {.VD, .VN, .VM, .IMM6, .NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SM3PARTW1 = { - {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3PARTW2 = { - {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3PARTW2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C400, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3SS1 = { - {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S}, {.VD, .VN, .VM, .VA}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SM3SS1, {.V_4S, .V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .VA, .NONE}, 0xCE400000, 0xFFE08000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SM3TT1A = { - {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT1A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT1B = { - {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT1B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2A = { - {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT2A, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM3TT2B = { - {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_IDX2}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SM3TT2B, {.V_4S, .V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_IDX2, .NONE}, 0xCE408C00, 0xFFE0CC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SM4E = { - {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SM4E, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1}}}, }, .SM4EKEY = { - {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SM4EKEY, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C800, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL = { - {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL, {.V_1Q, .V_1D, .V_1D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULL2 = { - {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULL2, {.V_1Q, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0E000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVT = { - {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.H_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E634000, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFDOT = { - {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFDOT, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E40FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMMLA = { - {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMMLA, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E40EC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALB = { - {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALB, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLALT = { - {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLALT, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC0FC00, 0xFFE0FC00, .BF16, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN = { - {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFCVTN2 = { - {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .MUL = { - {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04100000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04500000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04900000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MUL, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04100000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04500000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04900000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.MUL, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D00000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .MLA = { - {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .MLS = { - {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E609400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.MLS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA09400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .NEG = { - {{.NEG, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0417A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0457A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0497A000, 0xFFF7E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.NEG, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.NEG, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ABS = { - {{.ABS, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E20B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E60B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ABS, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0416A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0456A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0496A000, 0xFFF6E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ABS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04D6A000, 0xFFF6E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SHADD = { - {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHADD = { - {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SHSUB = { - {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SHSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UHSUB = { - {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UHSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SRHADD = { - {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URHADD = { - {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URHADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SQADD = { - {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQADD = { - {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE00C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQADD, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQSUB = { - {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .UQSUB = { - {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE02C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.UQSUB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SMAX = { - {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04080000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04480000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04880000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04080000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04480000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04880000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C80000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMAX = { - {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04090000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04490000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04890000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAX, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04090000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04490000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04890000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMAX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C90000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SMIN = { - {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048A0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CA0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UMIN = { - {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMIN, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048B0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UMIN, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CB0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABD = { - {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048C0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CC0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .UABD = { - {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x040D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x044D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x048D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E607400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA07400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UABD, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x040D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x044D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x048D0000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.UABD, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04CD0000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SABA = { - {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SABA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UABA = { - {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E207C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E607C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UABA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA07C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ADDP = { - {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0BC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDV = { - {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E31B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E71B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.ADDV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB1B800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADDLP = { - {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLP = { - {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E202800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E602800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA02800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SADALP = { - {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SADALP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .UADALP = { - {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E206800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E606800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_1D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.UADALP, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA06800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SADDLV = { - {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.H_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.S_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SADDLV, {.D_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UADDLV = { - {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.H_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E303800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.S_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E703800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UADDLV, {.D_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB03800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXV = { - {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMAXV = { - {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E70A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMINV = { - {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UMINV = { - {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.B_REG, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E31A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.H_REG, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E71A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB1A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SMAXP = { - {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMAXP = { - {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMINP = { - {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMINP = { - {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0AC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL = { - {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDL2 = { - {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL = { - {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDL2 = { - {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E200000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E600000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA00000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL = { - {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBL2 = { - {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL = { - {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBL2 = { - {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW = { - {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SADDW2 = { - {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW = { - {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UADDW2 = { - {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW = { - {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSUBW2 = { - {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW = { - {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_8H, .V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_4S, .V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW, {.V_2D, .V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USUBW2 = { - {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN = { - {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RADDHN2 = { - {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN = { - {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .RSUBHN2 = { - {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN = { - {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .ADDHN2 = { - {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN = { - {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SUBHN2 = { - {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .XTN = { - {{.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .XTN2 = { - {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.XTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQXTN = { - {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTN2 = { - {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN = { - {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQXTN2 = { - {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN = { - {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQXTUN2 = { - {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SMULL = { - {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMULL2 = { - {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL = { - {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .UMULL2 = { - {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMLAL = { - {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLAL2 = { - {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL = { - {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLAL2 = { - {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL = { - {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SMLSL2 = { - {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL = { - {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_8H, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UMLSL2 = { - {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_8H, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .SQDMULL = { - {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMULL2 = { - {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL = { - {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLAL2 = { - {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLAL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL = { - {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_4S, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL, {.V_2D, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMLSL2 = { - {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQDMULH = { - {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQDMULH, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SQRDMULH = { - {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMULH, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.QC}}}, }, .SDOT = { - {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.SDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .UDOT = { - {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.UDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .USDOT = { - {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_2S, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.USDOT, {.V_4S, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E809C00, 0xFFE0FC00, .DOT, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .FMLA = { - {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65600000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A00000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H, .NONE}, 0x64200000, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S, .NONE}, 0x64A00000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLA, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D, .NONE}, 0x64E00000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMLS = { - {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65602000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A02000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .IMM_3, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_H, .NONE}, 0x64200400, 0xFFA0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_S, .NONE}, 0x64A00400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMLS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .IMM_2, .NONE}, {.VD, .VN, .VM, .SVE_FMLA_IDX_D, .NONE}, 0x64E00400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMULX = { - {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60DC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMULX, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E401C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMAXP = { - {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E403400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINP = { - {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0F400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC03400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMP = { - {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E400400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMP = { - {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0C400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC00400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXV = { - {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINV = { - {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0F800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMAXNMV = { - {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E30C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMAXNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E30C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FMINNMV = { - {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, - {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.S_REG, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EB0C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, + {{.FMINNMV, {.H_REG, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EB0C800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IDC}, reads_fpcr=true}}, }, .FRECPE = { - {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRSQRTE = { - {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE1D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRSQRTE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF9D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, }, .FRECPS = { - {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65401800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65801800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRECPS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRSQRTS = { - {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE0FC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FRSQRTS, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FRECPX = { - {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, - {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EA1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EE1F800, 0xFFFFFC00, .FP, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x5EF9F800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x654CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x658CA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, + {{.FRECPX, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x65CCA000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_fpcr=true}}, }, .FADDP = { - {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60D400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FADDP, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E401400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL = { - {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_4S, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTL2 = { - {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_4S, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E217800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E617800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN = { - {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_4H_FP16, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTN2 = { - {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_8H_FP16, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E216800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCVTN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCVTXN = { - {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN, {.V_2S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCVTXN2 = { - {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, + {{.FCVTXN2, {.V_4S, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E616800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC, .IXC}}}, }, .FCMEQ = { - {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65406000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65806000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGE = { - {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E402400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65404000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65804000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C04000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMGT = { - {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0E400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC02400, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65404010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65804010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C04010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMLE = { - {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE0D800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EF8D800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65512010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65912010, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FCMLT = { - {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0E800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_4H_FP16, .V_4H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.V_8H_FP16, .V_8H_FP16, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EF8E800, 0xFFFFFC00, .FP16, {}}, Clobber{written={0}, read={1}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65512000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65912000, 0xFFFFE010, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FCMLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .NONE, .NONE}, {.PD, .PG, .VN, .NONE, .NONE}, 0x65D12000, 0xFFFFE010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGE = { - {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E20EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E60EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGE, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E402C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .FACGT = { - {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, - {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE0EC00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_4H_FP16, .V_4H_FP16, .V_4H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, + {{.FACGT, {.V_8H_FP16, .V_8H_FP16, .V_8H_FP16, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EC02C00, 0xFFE0FC00, .FP16, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC}}}, }, .CMEQ = { - {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMEQ, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGE = { - {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGE, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMGT = { - {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMGT, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHI = { - {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHI, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMHS = { - {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMHS, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .CMLE = { - {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E209800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E609800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLE, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EE09800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMLT = { - {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E20A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E60A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CMLT, {.V_2D, .V_2D, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EE0A800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CMTST = { - {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CMTST, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .MVN = { - {{.MVN, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.MVN, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MVN, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .BIT = { - {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BIT, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BIF = { - {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BIF, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .BSL = { - {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.BSL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.BSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SHL = { - {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHL = { - {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F087400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F107400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F207400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHL, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F407400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHLU = { - {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F086400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F106400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F206400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHLU, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F406400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SRSHL = { - {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SRSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .URSHL = { - {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.URSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SSHR = { - {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHR = { - {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F080400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F100400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F200400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F400400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSRA = { - {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .USRA = { - {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F081400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F101400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F201400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.USRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F401400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRSHR = { - {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SRSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSHR = { - {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F082400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F102400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F202400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSHR, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F402400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SRSRA = { - {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .URSRA = { - {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F083400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F103400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F203400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.URSRA, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F403400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHL = { - {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SSHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .USHL = { - {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.USHL, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, }, .SLI = { - {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F085400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F105400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F205400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SLI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F405400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SRI = { - {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, - {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8B, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_16B, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F084400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4H, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_8H, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F104400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2S, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_4S, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F204400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, + {{.SRI, {.V_2D, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F404400, 0xFFC0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1}}}, }, .SSHLL = { - {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x0F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SSHLL2 = { - {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SSHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x4F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL = { - {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_8H, .V_8B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_4S, .V_4H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL, {.V_2D, .V_2S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x2F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .USHLL2 = { - {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_8H, .V_16B, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F08A400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_4S, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F10A400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.USHLL2, {.V_2D, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHL_IMM, .NONE, .NONE}, 0x6F20A400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL = { - {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_8H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_4S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SXTL2 = { - {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SXTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL = { - {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_8H, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_4S, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL, {.V_2D, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .UXTL2 = { - {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_8H, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F08A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_4S, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F10A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.UXTL2, {.V_2D, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6F20A400, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN = { - {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SHRN2 = { - {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.SHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN = { - {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .RSHRN2 = { - {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.RSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .SQSHRN = { - {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRN2 = { - {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN = { - {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQSHRN2 = { - {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F089400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F109400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F209400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN = { - {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x0F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRN2 = { - {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x4F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN = { - {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .UQRSHRN2 = { - {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F089C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F109C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.UQRSHRN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F209C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN = { - {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQSHRUN2 = { - {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F088400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F108400, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F208400, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN = { - {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_8B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_4H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN, {.V_2S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x2F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .SQRSHRUN2 = { - {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, - {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_16B, .V_8H, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F088C00, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_8H, .V_4S, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F108C00, 0xFFF0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, + {{.SQRSHRUN2, {.V_4S, .V_2D, .VEC_SHIFT, .NONE, .NONE}, {.VD, .VN, .NEON_SHR_IMM, .NONE, .NONE}, 0x6F208C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}, fpsr_wr={.QC}}}, }, .DUP = { - {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_16B, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_8H, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_4S, .W_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.V_2D, .X_REG, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .V_ELEM_B, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .V_ELEM_B, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .V_ELEM_H, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .V_ELEM_H, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E020400, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .V_ELEM_S, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x0E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .V_ELEM_S, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E040400, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .V_ELEM_D, .VEC_INDEX, .NONE, .NONE}, {.VD, .VN, .NEON_IDX5, .NONE, .NONE}, 0x4E080400, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_16B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E010C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_8H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E020C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_4S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.V_2D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .RN, .NONE, .NONE, .NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05203800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05603800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.DUP, {.Z_REG_D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .INS = { - {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, - {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .V_ELEM_B, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E010400, 0xFFE18400, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .V_ELEM_H, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E020400, 0xFFE38C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .V_ELEM_S, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E040400, 0xFFE79C00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .V_ELEM_D, .VEC_INDEX, .NONE}, {.VD, .NEON_IDX5, .VN, .NEON_IDX4, .NONE}, 0x6E080400, 0xFFEFBC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_B, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_H, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E021C00, 0xFFE3FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_S, .VEC_INDEX, .W_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E041C00, 0xFFE7FC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, + {{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, Clobber{written={0}, read={0, 2}}}, }, .MOV = { - {{.MOV, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, - {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, - {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.MOV, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}}}, + {{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, Clobber{written={0}}}, + {{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .EXT = { - {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX}, {.VD, .VN, .VM, .NEON_EXT_IDX}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT}, {.VD, .VD, .VN, .SVE_EXT_IMM}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_EXT_IDX, .NONE}, 0x2E000000, 0xFFE0C400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.V_16B, .V_16B, .V_16B, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_EXT_IDX, .NONE}, 0x6E000000, 0xFFE08400, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT, .NONE}, {.VD, .VD, .VN, .SVE_EXT_IMM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.EXT, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT, .NONE}, {.VD, .VD, .VN, .SVE_EXT_IMM, .NONE}, 0x05200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBL = { - {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBX = { - {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN_LIST1, .VM, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, - {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, + {{.TBX, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}}}, }, .ZIP1 = { - {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E003800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E403800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E803800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC03800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .ZIP2 = { - {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E007800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E407800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E807800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC07800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP1 = { - {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E001800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E401800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E801800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC01800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204800, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP2 = { - {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E005800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E405800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E805800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC05800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05204C00, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN1 = { - {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E002800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E402800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E802800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC02800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05207000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05607000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN1, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05205000, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .TRN2 = { - {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PM, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8B, .V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E006800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4H, .V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_8H, .V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E406800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2S, .V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x0E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4E806800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.V_2D, .V_2D, .V_2D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4EC06800, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05207400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05607400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TRN2, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PM, .NONE, .NONE}, 0x05205400, 0xFFE0FE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .NOT = { - {{.NOT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NOT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.NOT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.NOT, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4_PM_DUP, .PN, .NONE, .NONE}, 0x25004200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .REV64 = { - {{.REV64, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_4H, .V_4H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_8H, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.REV64, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4H, .V_4H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_8H, .V_8H, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.REV64, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .CNT = { - {{.CNT, {.V_8B, .V_8B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CNT, {.V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.VD, .PG, .VN, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.CNT, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x041AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x045AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x049AA000, 0xFFFAE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CNT, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x04DAA000, 0xFFFAE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .URECPE = { - {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URECPE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .URSQRTE = { - {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, - {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_2S, .V_2S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, + {{.URSQRTE, {.V_4S, .V_4S, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}}}, }, .MOVI = { - {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8B, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_16B, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_8H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MOVI, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00E400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .MVNI = { - {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, - {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x2F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_8H, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F008400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x2F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, + {{.MVNI, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F000400, 0xFFF8FC00, .NEON, {}}, Clobber{written={0}}}, }, .LD1 = { - {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407000, 0xFFFFF000, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_8H, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407400, 0xFFFFF400, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_4S, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407800, 0xFFFFF800, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_2D, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C407C00, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D400000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D404000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D408000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D408400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD2 = { - {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C408000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D600000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D604000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D608000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D608400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD3 = { - {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C404000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D402000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D406000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D40A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D40A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .LD4 = { - {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, - {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C400000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D602000, 0xBFFFE000, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D606000, 0xBFFFE400, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D60A000, 0xBFFFEC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, + {{.LD4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D60A400, 0xBFFFFC00, .NEON, {}}, Clobber{written={0}, read={2}, reads_mem=true}}, }, .ST1 = { - {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007000, 0xFFFFF000, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_8H, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007400, 0xFFFFF400, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_4S, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007800, 0xFFFFF800, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_2D, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C007C00, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST1, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D000000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D004000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D008000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST1, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D008400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST2 = { - {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C008000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST2, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D200000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D204000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D208000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST2, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D208400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST3 = { - {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C004000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST3, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D002000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D006000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D00A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST3, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D00A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .ST4 = { - {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, - {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4C000000, 0xFFFFFC00, .NEON, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.ST4, {.V_ELEM_B, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_B, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D202000, 0xBFFFE000, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_H, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_H, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D206000, 0xBFFFE400, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_S, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_S, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D20A000, 0xBFFFEC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, + {{.ST4, {.V_ELEM_D, .VEC_INDEX, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .NEON_LANE_D, .OFFSET_BASE_A, .NONE, .NONE}, 0x0D20A400, 0xBFFFFC00, .NEON, {}}, Clobber{read={0, 2}, writes_mem=true}}, }, .LD1R = { - {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD1R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST1, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D40C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD2R = { - {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD2R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST2, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D60C000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD3R = { - {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD3R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST3, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D40E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .LD4R = { - {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LD4R, {.V_16B, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.VD_LIST4, .OFFSET_BASE_A, .NONE, .NONE, .NONE}, 0x4D60E000, 0xFFFFFC00, .NEON, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, }, .SUBR = { - {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04030000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04430000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04830000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04030000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04430000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04830000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04C30000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ASRR = { - {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04148000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04548000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04948000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.ASRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D48000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSLR = { - {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04178000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04578000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04978000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSLR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D78000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LSRR = { - {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04158000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04558000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04958000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.LSRR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x04D58000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .FTSMUL = { - {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FTSMUL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FSUBR = { - {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65438000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65838000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FSUBR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65C38000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FDIVR = { - {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VD, .VN}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VD, .VN}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x654C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x658C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FDIVR, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65CC8000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .DZC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FNMLA = { - {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65604000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLA, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .FNMLS = { - {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65606000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.FNMLS, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .NAND = { - {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NAND, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NOR = { - {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NOR, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25804200, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .SEL = { - {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SEL, {.P_REG_B, .P_REG, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25004210, 0xFFE0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .ORRS = { - {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORRS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .EORS = { - {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.EORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NANDS = { - {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NANDS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NORS = { - {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NORS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04200, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .ORNS = { - {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.ORNS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x25C04010, 0xFFF0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .MOVS = { - {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MOVS, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25404000, 0xFFE0C210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PTRUE = { - {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, + {{.PTRUE, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE, .NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {}}, Clobber{written={0}}}, }, .PTRUES = { - {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.PTRUES, {.P_REG_B, .SVE_PATTERN, .NONE, .NONE, .NONE}, {.PD, .SVE_PATTERN, .NONE, .NONE, .NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true}}, Clobber{written={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .PFALSE = { - {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, + {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PD, .NONE, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE, .NONE}, {.PD, .PN, .PD, .NONE, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { - {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKB = { - {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BRKB, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25904010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKAS = { - {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKAS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25504000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKBS = { - {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.BRKBS, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .NONE, .NONE}, {.PD, .PG4, .PN, .NONE, .NONE}, 0x25D04000, 0xFFFFC210, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .BRKPA = { - {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPA, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x2500C000, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKPB = { - {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PM}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKPB, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PM, .NONE}, 0x2500C010, 0xFFF0C210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BRKN = { - {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B}, {.PD, .PG4, .PN, .PD}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BRKN, {.P_REG_B, .P_REG_ZERO, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .PD, .NONE}, 0x25184000, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .RDFFR = { - {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, + {{.RDFFR, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE, .NONE}, 0x2519F000, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}, side_effects={.FFR}}}, }, .WRFFR = { - {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, + {{.WRFFR, {.P_REG_B, .NONE, .NONE, .NONE, .NONE}, {.PN, .NONE, .NONE, .NONE, .NONE}, 0x25289000, 0xFFFFFE1F, .SVE, {}}, Clobber{read={0}, side_effects={.FFR}}}, }, .SETFFR = { - {{.SETFFR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, + {{.SETFFR, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x252C9000, 0xFFFFFFFF, .SVE, {}}, Clobber{side_effects={.FFR}}}, }, .CMPEQ = { - {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPEQ, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPNE = { - {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGE = { - {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPGT = { - {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPGT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLE = { - {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLT = { - {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLT, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHI = { - {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHI, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPHS = { - {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPHS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLO = { - {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMPLS = { - {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VM, .VN}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VM, .VN}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VM, .VN}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VM, .VN}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24400000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMPLS, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VM, .VN, .NONE}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .FCMNE = { - {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65406010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65806010, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMNE, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C06010, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .FCMUO = { - {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.PD, .PG, .VN, .VM}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, - {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.PD, .PG, .VN, .VM}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x6540C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x6580C000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, + {{.FCMUO, {.P_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x65C0C000, 0xFFE0E010, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC}}}, }, .INSR = { - {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_B, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05243800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_H, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05643800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_S, .W_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INSR, {.Z_REG_D, .X_REG, .NONE, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE, .NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .CPY = { - {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_B, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0528A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_H, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x0568A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_S, .P_REG_MERGE, .W_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05A8A000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.CPY, {.Z_REG_D, .P_REG_MERGE, .X_REG, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05E8A000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .COMPACT = { - {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_S, .P_REG_GOV, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05A18000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.COMPACT, {.Z_REG_D, .P_REG_GOV, .Z_REG_D, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x05E18000, 0xFFFFE000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .LD1B = { - {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA4004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.SME_SLICE_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE0000000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_PAIR_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0000000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1B, {.Z_QUAD_B, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0008000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1H = { - {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84804000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.SME_SLICE_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE0400000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_PAIR_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA0002000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1H, {.Z_QUAD_H, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA000A000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1W = { - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA5404000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x85004000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5004000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.SME_SLICE_W, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE0800000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_PAIR_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA0004000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1W, {.Z_QUAD_S, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA000C000, 0xFFE0E000, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1D = { - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5804000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.SME_SLICE_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE0C00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_PAIR_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA0006000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1D, {.Z_QUAD_D, .PN_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA000E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SB = { - {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA5C04000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84000000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SB, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SH = { - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA5004000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA5204000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_S, .NONE, .NONE}, 0x84800000, 0xFFA0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SH, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LD1SW = { - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, - {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA4804000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1SW, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC_D, .NONE, .NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1B = { - {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_QUAD_B, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA0208000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1H = { - {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE4C08000, 0xFFE0A000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE4A04000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE4808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.SME_SLICE_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_H, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE0600000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_PAIR_H, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA0202000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_QUAD_H, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA020A000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1H, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE4C08000, 0xFFE0A000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1W = { - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_S, .NONE, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE5008000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_QUAD_S, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA020C000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .ST1D = { - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VECST_D, .NONE, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .LDFF1B = { - {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA4006000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1H = { - {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1W = { - {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA5406000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .LDFF1D = { - {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, + {{.LDFF1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true, side_effects={.FFR}}}, }, .WHILEGE = { - {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGE, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01000, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEGT = { - {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEGT, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01010, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELE = { - {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELE, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01410, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { - {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHI, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01810, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHS = { - {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILEHS, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01800, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELO = { - {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELO, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01C00, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELS = { - {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_B, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25201C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_H, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25601C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_S, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25A01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELS, {.P_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.PD, .RN, .RM, .NONE, .NONE}, 0x25E01C10, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .SQRDMLAH = { - {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLAH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .SQRDMLSH = { - {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, - {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, + {{.SQRDMLSH, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.QC}}}, }, .ADCLB = { - {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .ADCLT = { - {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ADCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLB = { - {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLB, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .SBCLT = { - {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .MATCH = { - {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .NMATCH = { - {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B}, {.PD, .PG, .VN, .VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H}, {.PD, .PG, .VN, .VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NMATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, }, .HISTCNT = { - {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S}, {.VD, .PG, .VN, .VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, - {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D}, {.VD, .PG, .VN, .VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_S, .P_REG_ZERO, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x45A0C000, 0xFFE0E000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.HISTCNT, {.Z_REG_D, .P_REG_ZERO, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .HISTSEG = { - {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.HISTSEG, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SMSTART = { - {{.SMSTART, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, + {{.SMSTART, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503477F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .SMSTOP = { - {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, + {{.SMSTOP, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503467F, 0xFFFFFFFF, .SME, {}}, Clobber{}}, }, .RDSVL = { - {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, + {{.RDSVL, {.X_REG, .IMM_6, .NONE, .NONE, .NONE}, {.RD, .ENC_IMM6_LO, .NONE, .NONE, .NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true}}, Clobber{written={0}}}, }, .ADDHA = { - {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.ADDHA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZA_TILE_LOW, .PG, .PM3, .VN, .NONE}, 0xC0900000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ADDVA = { - {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_LOW, .PG, .PM3, .VN}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZA_TILE_LOW, .PG, .PM3, .VN, .NONE}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, }, .FMOPA = { - {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FMOPS = { - {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x80800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPA = { - {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x81800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMOPS = { - {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x81800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SMOPA = { - {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SMOPS = { - {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0800010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPA = { - {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPA, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .UMOPS = { - {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, - {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1A00010, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.UMOPS, {.ZA_TILE_D, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.ZA_TILE_NUM_D, .PG, .PM3, .VN, .VM}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .USMOPA = { - {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.USMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA1800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .SUMOPA = { - {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, + {{.SUMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_B, .Z_REG_B}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0xA0A00000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .CNTB = { - {{.CNTB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTH = { - {{.CNTH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTW = { - {{.CNTW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .CNTD = { - {{.CNTD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, + {{.CNTD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}}}, }, .INCB = { - {{.INCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, }, .INCH = { - {{.INCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .INCW = { - {{.INCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .INCD = { - {{.INCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.INCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.INCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0E000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.INCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECB = { - {{.DECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, }, .DECH = { - {{.DECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECW = { - {{.DECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .DECD = { - {{.DECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, - {{.DECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, + {{.DECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0E400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}}}, + {{.DECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}}}, }, .SQINCB = { - {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCH = { - {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCW = { - {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQINCD = { - {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F000, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C000, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECB = { - {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECB, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECH = { - {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECW = { - {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .SQDECD = { - {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F800, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.X_REG, .W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.SQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C800, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCB = { - {{.UQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCH = { - {{.UQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCW = { - {{.UQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQINCD = { - {{.UQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0F400, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0F400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQINCD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0C400, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECB = { - {{.UQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECB, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0430FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECB, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0420FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECH = { - {{.UQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0470FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECH, {.Z_REG_H, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x0460CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECW = { - {{.UQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04B0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECW, {.Z_REG_S, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04A0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .UQDECD = { - {{.UQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, - {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.X_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04F0FC00, 0xFFF0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.W_REG, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.RD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, + {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .CNTP = { - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE, .NONE}, {.RD, .PG, .PN, .NONE, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .INCP = { - {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .DECP = { - {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .SQINCP = { - {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .SQDECP = { - {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_B, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_H, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_S, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG_D, .W_REG, .NONE}, {.RD, .PN, .RD, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .W_REG, .NONE, .NONE}, {.RD, .PN, .RD, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQINCP = { - {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQDECP = { - {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { - {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .ST1Q = { - {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1Q, {.SME_SLICE_Q, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE, .NONE}, 0xE1E00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .MOVA = { - {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.Z_REG_B, .P_REG_MERGE, .SME_SLICE_B, .NONE, .NONE}, {.VD, .PG, .SME_SLICE_B, .NONE, .NONE}, 0xC0020000, 0xFFE28010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.MOVA, {.SME_SLICE_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.SME_SLICE_B, .PG, .VN, .NONE, .NONE}, 0xC0000000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .FCMLA = { - {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCMLA_ROT}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4H, .V_4H, .V_4H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x2E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_8H, .V_8H, .V_8H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6E40C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_4S, .V_4S, .V_4S, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6E80C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCMLA, {.V_2D, .V_2D, .V_2D, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCMLA_ROT, .NONE}, 0x6EC0C400, 0xFFE0CC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .FCADD = { - {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2}, {.VD, .VN, .VM, .ENC_FCADD_ROT}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4H, .V_4H, .V_4H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x2E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_8H, .V_8H, .V_8H, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6E40E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_4S, .V_4S, .V_4S, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6E80E400, 0xFFA0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.FCADD, {.V_2D, .V_2D, .V_2D, .IMM_2, .NONE}, {.VD, .VN, .VM, .ENC_FCADD_ROT, .NONE}, 0x6EC0E400, 0xFFE0EC00, .NEON, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .PRFB = { - {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFB, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0x8400C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFH = { - {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFH, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0x8480C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFW = { - {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFW, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0x8500C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .PRFD = { - {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, + {{.PRFD, {.IMM_4, .P_REG_GOV, .MEM_SVE_SS, .NONE, .NONE}, {.ENC_SVE_PRFOP, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0x8580C000, 0xFFE0E000, .SVE, {}}, Clobber{read={1, 2}, side_effects={.HINT}}}, }, .LDNT1B = { - {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1B, {.Z_REG_B, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xA400C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1H = { - {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1H, {.Z_REG_H, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xA480C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1W = { - {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1W, {.Z_REG_S, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xA500C000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .LDNT1D = { - {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, + {{.LDNT1D, {.Z_REG_D, .P_REG_ZERO, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xA580C000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, }, .STNT1B = { - {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE, .NONE}, 0xE4006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1H = { - {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1H, {.Z_REG_H, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS1, .NONE, .NONE}, 0xE4806000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1W = { - {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE, .NONE}, 0xE5006000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .STNT1D = { - {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.STNT1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE, .NONE}, 0xE5806000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, }, .SPLICE = { - {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B}, {.VD, .PG, .VD, .VN}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.SPLICE, {.Z_REG_B, .P_REG_GOV, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x052C8000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .INDEX = { - {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, - {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, - {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE}, {.VD, .RN, .RM, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04204000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}}}, + {{.INDEX, {.Z_REG_B, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04204800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={2}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04204400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1}}}, + {{.INDEX, {.Z_REG_B, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04204C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04604000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04604800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04604400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_H, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04604C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04A04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .IMM_5, .W_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04A04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04A04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_S, .W_REG, .W_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04A04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .IMM_5, .NONE, .NONE}, {.VD, .SVE_IMM5A, .SVE_IMM5, .NONE, .NONE}, 0x04E04000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .IMM_5, .X_REG, .NONE, .NONE}, {.VD, .SVE_IMM5A, .RM, .NONE, .NONE}, 0x04E04800, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .IMM_5, .NONE, .NONE}, {.VD, .RN, .SVE_IMM5, .NONE, .NONE}, 0x04E04400, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.INDEX, {.Z_REG_D, .X_REG, .X_REG, .NONE, .NONE}, {.VD, .RN, .RM, .NONE, .NONE}, 0x04E04C00, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BSL1N = { - {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BSL1N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04603C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BSL2N = { - {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BSL2N, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04A03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .NBSL = { - {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D}, {.VD, .VD, .VM, .VN}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.NBSL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE}, {.VD, .VD, .VM, .VN, .NONE}, 0x04E03C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2, 3}}}, }, .PMUL = { - {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PMUL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x04206400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLB = { - {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULLB, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C06800, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .PMULLT = { - {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.PMULLT, {.Z_REG_D, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C06C00, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .BFCVTNT = { - {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE}, {.VD, .PG, .VN, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFCVTNT, {.Z_REG_H, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.VD, .PG, .VN, .NONE, .NONE}, 0x648AA000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .LDRAA = { - {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAA, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8200C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .LDRAB = { - {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF8A00400, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDRAB, {.X_REG, .MEM_PRE, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_PRE, .NONE, .NONE, .NONE}, 0xF8A00C00, 0xFFA00C00, .PAC, {is_64=true}}, Clobber{written={0, 1}, read={1}, reads_mem=true}}, }, .TSTART = { - {{.TSTART, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, + {{.TSTART, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5233060, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}, side_effects={.NONDETERMINISTIC}}}, }, .TCOMMIT = { - {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, + {{.TCOMMIT, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503307F, 0xFFFFFFFF, .BASE, {}}, Clobber{}}, }, .TCANCEL = { - {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, + {{.TCANCEL, {.IMM_16, .NONE, .NONE, .NONE, .NONE}, {.IMM16, .NONE, .NONE, .NONE, .NONE}, 0xD4600000, 0xFFE0001F, .BASE, {}}, Clobber{side_effects={.CONTROL}}}, }, .TTEST = { - {{.TTEST, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, + {{.TTEST, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5233160, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{written={0}}}, }, .WFET = { - {{.WFET, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, + {{.WFET, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5031000, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .WFIT = { - {{.WFIT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, + {{.WFIT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5031020, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.WAIT}}}, }, .BC_EQ = { - {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_EQ, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000010, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_NE = { - {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, + {{.BC_NE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000011, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z}, side_effects={.CONTROL}}}, }, .BC_CS = { - {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000012, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_CC = { - {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, + {{.BC_CC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000013, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.C}, side_effects={.CONTROL}}}, }, .BC_MI = { - {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_MI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000014, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_PL = { - {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, + {{.BC_PL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000015, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N}, side_effects={.CONTROL}}}, }, .BC_VS = { - {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000016, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_VC = { - {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, + {{.BC_VC, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000017, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.V}, side_effects={.CONTROL}}}, }, .BC_HI = { - {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_HI, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000018, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_LS = { - {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, + {{.BC_LS, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x54000019, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.Z, .C}, side_effects={.CONTROL}}}, }, .BC_GE = { - {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_GE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001A, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_LT = { - {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, + {{.BC_LT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001B, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .V}, side_effects={.CONTROL}}}, }, .BC_GT = { - {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_GT, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001C, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_LE = { - {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, + {{.BC_LE, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001D, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{nzcv_rd={.N, .Z, .V}, side_effects={.CONTROL}}}, }, .BC_AL = { - {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.BC_AL, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001E, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .BC_NV = { - {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, + {{.BC_NV, {.REL_19, .NONE, .NONE, .NONE, .NONE}, {.BRANCH_19, .NONE, .NONE, .NONE, .NONE}, 0x5400001F, 0xFF00001F, .BASE, {cond_branch=true}}, Clobber{side_effects={.CONTROL}}}, }, .UXTB = { - {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.UXTB, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x53001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTH = { - {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.UXTH, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x53003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .UXTW = { - {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.UXTW, {.X_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0xD3407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .SXTB = { - {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SXTB, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x13001C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTH = { - {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, + {{.SXTH, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x13003C00, 0xFFFFFC00, .BASE, {}}, Clobber{written={0}, read={1}}}, }, .SXTW = { - {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, + {{.SXTW, {.X_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x93407C00, 0xFFFFFC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}}}, }, .ADC = { - {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.ADC, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .ADCS = { - {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.ADCS, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .SBC = { - {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, - {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, + {{.SBC, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_rd={.C}}}, }, .SBCS = { - {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.W_REG, .W_REG, .W_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.SBCS, {.X_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .NGC = { - {{.NGC, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, - {{.NGC, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, + {{.NGC, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, nzcv_rd={.C}}}, }, .NGCS = { - {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, - {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, + {{.NGCS, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}, nzcv_rd={.C}}}, }, .LDAPUR = { - {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9400000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLUR = { - {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, - {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLUR, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xD9000000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURB = { - {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURB = { - {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURH = { - {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59400000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .STLURH = { - {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, + {{.STLURH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59000000, 0xFFE00C00, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true, side_effects={.FENCE}}}, }, .LDAPURSB = { - {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x19C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSH = { - {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, - {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSH, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x59C00000, 0xFFE00C00, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .LDAPURSW = { - {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, + {{.LDAPURSW, {.X_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{written={0}, read={1}, reads_mem=true, side_effects={.FENCE}}}, }, .BFADD = { - {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65008000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65008000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFADD, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000000, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFSUB = { - {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65018000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65018000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFSUB, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMUL = { - {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65028000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, - {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65028000, 0xFFFFE000, .SVE, {}}, Clobber{written={0}, read={1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMUL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x65000800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLA = { - {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLA, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65200000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .BFMLS = { - {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VN, .VM}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, + {{.BFMLS, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VN, .VM, .NONE}, 0x65202000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, }, .SB = { - {{.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.SB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50330FF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .CSDB = { - {{.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, + {{.CSDB, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503229F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.FENCE}}}, }, .DGH = { - {{.DGH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.DGH, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50320DF, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .PSB_CSYNC = { - {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503223F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .TSB_CSYNC = { - {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, + {{.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503225F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.HINT}}}, }, .BTI_J = { - {{.BTI_J, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_J, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503249F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_C = { - {{.BTI_C, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_C, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD503245F, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BTI_JC = { - {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, + {{.BTI_JC, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50324DF, 0xFFFFFFFF, .BTI, {}}, Clobber{side_effects={.BTI}}}, }, .BFCLAMP = { - {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.BFCLAMP, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x64202400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .BFMAXNM = { - {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65048000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BFMAXNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65048000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .BFMINNM = { - {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H}, {.VD, .PG, .VD, .VN}, 0x65058000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, + {{.BFMINNM, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .Z_REG_H, .NONE}, {.VD, .PG, .VD, .VN, .NONE}, 0x65058000, 0xFFFFE000, .SVE2, {}}, Clobber{written={0}, read={1, 2, 3}}}, }, .LUTI2 = { - {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI2, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08C6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .LUTI4 = { - {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, - {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_B, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A4000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_H, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A5000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, + {{.LUTI4, {.Z_PAIR_S, .ZT_REG, .Z_REG_ANY, .VEC_INDEX, .NONE}, {.ENC_Z_PAIR_VD, .ENC_ZT0, .VN, .LUTI_IDX, .NONE}, 0xC08A6000, 0xFFFE7C00, .SME, {}}, Clobber{written={0}, read={2}}}, }, .ZIP = { - {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE, .NONE}, 0xC120D000, 0xFFE0FC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.ZIP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE, .NONE}, 0xC136E000, 0xFFFFFC00, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .UZP = { - {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, Clobber{written={0}, read={1, 2}}}, - {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_PAIR_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.ENC_Z_PAIR_VD, .VN, .VM, .NONE, .NONE}, 0xC120D001, 0xFFE0FC01, .SME, {}}, Clobber{written={0}, read={1, 2}}}, + {{.UZP, {.Z_QUAD_B, .Z_QUAD_B, .NONE, .NONE, .NONE}, {.ENC_Z_QUAD_VD, .ENC_Z_QUAD_VN, .NONE, .NONE, .NONE}, 0xC136E002, 0xFFFFFC02, .SME, {}}, Clobber{written={0}, read={1, 2}}}, }, .TLBI_RPALOS = { - {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPALOS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5084EE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_RPAOS = { - {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_RPAOS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5084EA0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1A = { - {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1A, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5079140, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .DC_CIPAPA = { - {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIPAPA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7CE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIGDPAPA = { - {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIGDPAPA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7DE0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .TLBI_PAALL = { - {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALL, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E879F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_PAALLOS = { - {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_PAALLOS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E819F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .AMX_LDX = { - {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDY = { - {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201020, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STX = { - {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201040, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STY = { - {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201060, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZ = { - {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201080, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZ = { - {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STZ, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_LDZI = { - {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_LDZI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_STZI = { - {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_STZI, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002010E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRX = { - {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_EXTRX, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201100, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_EXTRY = { - {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_EXTRY, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201120, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA64 = { - {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA64, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201140, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS64 = { - {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS64, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201160, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA32 = { - {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA32, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201180, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS32 = { - {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS32, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MAC16 = { - {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MAC16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMA16 = { - {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMA16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002011E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_FMS16 = { - {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_FMS16, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201200, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_SET = { - {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, + {{.AMX_SET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_CLR = { - {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, + {{.AMX_CLR, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {}}, Clobber{}}, }, .AMX_VECINT = { - {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_VECINT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201260, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_VECFP = { - {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_VECFP, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x00201280, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATINT = { - {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MATINT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_MATFP = { - {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_MATFP, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .AMX_GENLUT = { - {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, + {{.AMX_GENLUT, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true}}, Clobber{read={0}}}, }, .CPYP = { - {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYP, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYM = { - {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYM, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYE = { - {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYE, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFP = { - {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFP, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19000400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFM = { - {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFM, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19400400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .CPYFE = { - {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, + {{.CPYFE, {.XSP_REG, .XSP_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19800400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1, 2}, read={0, 1, 2}, writes_mem=true, reads_mem=true}}, }, .SETP = { - {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETP, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C00400, 0xFFE03C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETM = { - {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETM, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C04400, 0xFFE07C00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .SETE = { - {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE}, {.RD, .RN, .RM, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, + {{.SETE, {.XSP_REG, .X_REG, .X_REG, .NONE, .NONE}, {.RD, .RN, .RM, .NONE, .NONE}, 0x19C08400, 0xFFE0BC00, .BASE, {is_64=true}}, Clobber{written={0, 1}, read={0, 1, 2}, writes_mem=true}}, }, .DC_IVAC = { - {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_IVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087620, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ISW = { - {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_ISW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087640, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CSW = { - {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CSW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087A40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_CISW = { - {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, + {{.DC_CISW, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087E40, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE, .PRIVILEGED}}}, }, .DC_ZVA = { - {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, + {{.DC_ZVA, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7420, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, writes_mem=true, side_effects={.CACHE}}}, }, .DC_CVAC = { - {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7A20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CVAU = { - {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CVAU, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7B20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .DC_CIVAC = { - {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.DC_CIVAC, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7E20, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .IC_IALLUIS = { - {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLUIS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508711F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IALLU = { - {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, + {{.IC_IALLU, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508751F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.CACHE, .PRIVILEGED}}}, }, .IC_IVAU = { - {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, + {{.IC_IVAU, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50B7520, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.CACHE}}}, }, .AT_S1E1R = { - {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E1W = { - {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E1W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0R = { - {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087840, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E0W = { - {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E0W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5087860, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2R = { - {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E2W = { - {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E2W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3R = { - {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7800, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S1E3W = { - {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S1E3W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50E7820, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1R = { - {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C7880, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E1W = { - {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E1W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0R = { - {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0R, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78C0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .AT_S12E0W = { - {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.AT_S12E0W, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50C78E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1 = { - {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VMALLE1IS = { - {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_VMALLE1IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1 = { - {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088720, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAE1IS = { - {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088320, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1 = { - {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088740, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ASIDE1IS = { - {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_ASIDE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088340, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1 = { - {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088760, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAAE1IS = { - {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAAE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD5088360, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1 = { - {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50887A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VALE1IS = { - {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VALE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50883A0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1 = { - {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50887E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_VAALE1IS = { - {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, + {{.TLBI_VAALE1IS, {.X_REG, .NONE, .NONE, .NONE, .NONE}, {.RT, .NONE, .NONE, .NONE, .NONE}, 0xD50883E0, 0xFFFFFFE0, .BASE, {is_64=true}}, Clobber{read={0}, side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1 = { - {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE1IS = { - {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE1IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD508831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2 = { - {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50C871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE2IS = { - {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE2IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50C831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3 = { - {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E871F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .TLBI_ALLE3IS = { - {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, + {{.TLBI_ALLE3IS, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD50E831F, 0xFFFFFFFF, .BASE, {}}, Clobber{side_effects={.PRIVILEGED}}}, }, .PRFM = { - {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, - {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xF9800000, 0xFFC00000, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFM, {.IMM_5, .REL_19, .NONE, .NONE, .NONE}, {.RT, .BRANCH_19, .NONE, .NONE, .NONE}, 0xD8000000, 0xFF000000, .BASE, {is_64=true}}, Clobber{side_effects={.HINT}}}, }, .PRFUM = { - {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, + {{.PRFUM, {.IMM_5, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_S9, .NONE, .NONE, .NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true}}, Clobber{read={1}, side_effects={.HINT}}}, }, .NEGS = { - {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.NEGS, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMP = { - {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .W_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .X_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.WSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0x7100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMP, {.XSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0xF100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, .CMN = { - {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, - {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.W_REG, .W_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.X_REG, .X_SHIFTED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .W_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .X_EXTENDED, .NONE, .NONE, .NONE}, {.RN, .RM, .NONE, .NONE, .NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0, 1}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.WSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0x3100001F, 0xFF80001F, .BASE, {sets_flags=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.CMN, {.XSP_REG, .IMM_12, .NONE, .NONE, .NONE}, {.RN, .IMM12, .NONE, .NONE, .NONE}, 0xB100001F, 0xFF80001F, .BASE, {sets_flags=true, is_64=true}}, Clobber{read={0}, nzcv_wr={.N, .Z, .C, .V}}}, }, } diff --git a/core/rexcode/isa/arm64/tables.odin b/core/rexcode/isa/arm64/tables.odin index 1f19e6ed1..a4ada97b1 100644 --- a/core/rexcode/isa/arm64/tables.odin +++ b/core/rexcode/isa/arm64/tables.odin @@ -25,14 +25,14 @@ Encode_Run :: struct { Decode_Entry :: struct #packed { mnemonic: Mnemonic, // 2 - ops: [4]Operand_Type, // 4 - enc: [4]Operand_Encoding, // 4 + ops: [5]Operand_Type, // 4 + enc: [5]Operand_Encoding, // 4 bits: u32, // 4 mask: u32, // 4 feature: Feature, // 1 flags: Encoding_Flags, // 1 } -#assert(size_of(Decode_Entry) == 20) +#assert(size_of(Decode_Entry) == 22) Decode_Index :: struct #packed { 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proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_shifted(a.X2, .LSL, 3), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_shifted(a.X2, .LSL, 3), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -126,7 +126,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.SP), a.op_extended(a.W1, .UXTW, 2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.SP), a.op_extended(a.W1, .UXTW, 2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -281,7 +281,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADR, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_label(0, 4), {}, {}}, + ops = {a.op_reg(a.X0), a.op_label(0, 4), {}, {}, {}}, }, a.inst_none(.NOP), a.inst_none(.NOP), @@ -308,11 +308,11 @@ run_pipeline_tests :: proc() { a.inst_none(.NOP), a.Instruction{ mnemonic = .SVC, operand_count = 1, length = 4, - ops = {a.op_imm(1, 2), {}, {}, {}}, + ops = {a.op_imm(1, 2), {}, {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}}, + ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -484,7 +484,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 3, length = 4, - ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), {}}, + ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -511,7 +511,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .ADD, operand_count = 4, length = 4, - ops = {a.op_z_s(0), a.op_reg(p0), a.op_z_s(0), a.op_z_s(1)}, + ops = {a.op_z_s(0), a.op_reg(p0), a.op_z_s(0), a.op_z_s(1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -529,7 +529,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .PTRUE, operand_count = 2, length = 4, - ops = {a.op_reg(p0), a.op_imm(0x1F, 1), {}, {}}, + ops = {a.op_reg(p0), a.op_imm(0x1F, 1), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -568,8 +568,9 @@ run_pipeline_tests :: proc() { p1 := a.Register(a.REG_P | 1) insts := []a.Instruction{ a.Instruction{ - mnemonic = .FMOPA, operand_count = 4, length = 4, - ops = {a.op_imm(0, 1), a.op_reg(p0), a.op_reg(p1), a.op_z_s(0)}, + mnemonic = .FMOPA, operand_count = 5, length = 4, + ops = {a.op_reg(a.Register(a.REG_ZA | 0)), a.op_reg(p0), a.op_reg(p1), + a.op_z_s(0), a.op_z_s(0)}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -698,19 +699,19 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}}, + ops = {a.op_reg(a.X0), a.op_sysreg(a.NZCV), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X1), a.op_sysreg(a.TPIDR_EL0), {}, {}}, + ops = {a.op_reg(a.X1), a.op_sysreg(a.TPIDR_EL0), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X2), a.op_sysreg(a.CNTVCT_EL0), {}, {}}, + ops = {a.op_reg(a.X2), a.op_sysreg(a.CNTVCT_EL0), {}, {}, {}}, }, a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X3), a.op_sysreg(a.DCZID_EL0), {}, {}}, + ops = {a.op_reg(a.X3), a.op_sysreg(a.DCZID_EL0), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -753,7 +754,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .CMP, operand_count = 2, length = 4, - ops = {a.op_reg(a.X0), a.op_shifted(a.X1, .LSL, 0), {}, {}}, + ops = {a.op_reg(a.X0), a.op_shifted(a.X1, .LSL, 0), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -775,15 +776,15 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .CPYP, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, a.Instruction{ mnemonic = .CPYM, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, a.Instruction{ mnemonic = .CPYE, operand_count = 3, length = 4, - ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, + ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -805,7 +806,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .FMLA, operand_count = 4, length = 4, - ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), a.op_imm(2, 1)}, + ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), a.op_imm(2, 1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -832,7 +833,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .LD1W, operand_count = 3, length = 4, - ops = {a.op_z_s(0), a.op_reg(p0), a.op_mem(mem), {}}, + ops = {a.op_z_s(0), a.op_reg(p0), a.op_mem(mem), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -859,7 +860,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .LD1B, operand_count = 3, length = 4, - ops = {a.op_za_slice(0, 2, 5, a.ZSHAPE_B, true), a.op_reg(p5), a.op_mem(mem), {}}, + ops = {a.op_za_slice(0, 2, 5, a.ZSHAPE_B, true), a.op_reg(p5), a.op_mem(mem), {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -888,7 +889,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .FCMLA, operand_count = 4, length = 4, - ops = {a.op_v_4s(a.V0), a.op_v_4s(a.V1), a.op_v_4s(a.V2), a.op_imm(0, 1)}, + ops = {a.op_v_4s(a.V0), a.op_v_4s(a.V1), a.op_v_4s(a.V2), a.op_imm(0, 1), {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) @@ -958,7 +959,7 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.Instruction{ mnemonic = .MRS, operand_count = 2, length = 4, - ops = {a.op_reg(a.X7), a.op_sysreg(a.RNDR), {}, {}}, + ops = {a.op_reg(a.X7), a.op_sysreg(a.RNDR), {}, {}, {}}, }, } byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) diff --git a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin index 1baf215a4..5108643b5 100644 --- a/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/tools/gen_mnemonic_builders.odin @@ -77,12 +77,12 @@ Operand_Category :: enum { } Operand_Signature :: struct { - types: [4]a.Operand_Type, + types: [5]a.Operand_Type, // The encoding each operand uses. Needed because the operand TYPE is not // always enough: .VEC_INDEX is a lane index under NEON_IDX*/NEON_LANE_*, // which prints glued to its register, but EXT's byte index shares the type // and prints as a plain `#3`. - encs: [4]a.Operand_Encoding, + encs: [5]a.Operand_Encoding, count: int, } @@ -305,7 +305,7 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { // included; only truly implicit operands (enc == .IMPL, which AArch64's tables // never actually use) carry no param. build_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) { - for i in 0..<4 { + for i in 0..<5 { op := form.ops[i] if op == .NONE { continue } @@ -333,8 +333,8 @@ Param :: struct { // the shift/extend kind and amount. This is the single source of truth for // parameter names; param_list derives the typed declarations from it so the // declared params always match the expressions that reference them. -operand_primary_names :: proc(sig: Operand_Signature) -> [4][3]string { - result: [4][3]string +operand_primary_names :: proc(sig: Operand_Signature) -> [5][3]string { + result: [5][3]string reg_count := 0 imm_count := 0 zp_count := 0 @@ -620,7 +620,7 @@ write_inst_fallback :: proc(sb: ^strings.Builder, entry: Proc_Entry) { defer delete(mstr) fmt.sbprintf(sb, "Instruction{{mnemonic = .%s, operand_count = %d, length = 4, ops = {{", mstr, sig.count) - for i in 0..<4 { + for i in 0..<5 { if i > 0 { strings.write_string(sb, ", ") } if i < sig.count { write_operand_expr(sb, sig.types[i], sig.encs[i], pnames[i]) From 22292b9d35b9d09e6e48f08de78e722ab664cb98 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 19:36:08 -0400 Subject: [PATCH 53/89] rexcode/arm64: the last of the SVE and SME gaps TBL2 is gone: SVE2's two-table lookup is spelled `tbl`, and the reason it could not merge before was that the arity is the caller's choice, so the matcher needs it in the operand type rather than the encoding. It has that now, and both forms stay reachable. TBX, which takes no braces, was briefly given them and is back to plain. ZERO's operand is a mask with one bit per .d tile, and it is written as the list of the largest tiles that exactly cover it -- a .s tile being two .d tiles four apart, a .h tile four two apart. A mask of every bit is just `{za}`. It had been printing the raw number. ZA array vectors (`ldr za[w12, 0], [x0]`) are their own operand shape, with no tile and no element size; they printed as a bare immediate. The pair and quad register fields were read a bit too wide. A pair starts on an even register and a quad on a multiple of four, and ZIP and UZP tell themselves apart with the bits below that -- so every UZP decoded as naming the register one or two above the one it writes. SVE/SME2 against llvm-mc: 703 byte-exact of 704, with nothing mismatched. The one left is a reserved encoding -- XAR with a tsz of zero names no element size, and llvm-mc calls it invalid too. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/decoder.odin | 22 +- core/rexcode/isa/arm64/encoder.odin | 13 +- core/rexcode/isa/arm64/encoding_types.odin | 8 + core/rexcode/isa/arm64/mnemonic_builders.odin | 30 ++- core/rexcode/isa/arm64/mnemonics.odin | 1 - core/rexcode/isa/arm64/operands.odin | 5 + core/rexcode/isa/arm64/printer.odin | 53 +++- .../tablegen/generated/decode_tables.odin | 16 +- .../tablegen/generated/encode_tables.odin | 229 +++++++++--------- .../isa/arm64/tablegen/instruction_table.odin | 19 +- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 37394 -> 37394 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 58762 -> 58762 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6848 -> 6840 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 58806 -> 58806 bytes .../arm64/tools/gen_mnemonic_builders.odin | 12 +- 15 files changed, 245 insertions(+), 163 deletions(-) diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index 94c98341b..3e246d90d 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -507,6 +507,11 @@ extract_operand_inline :: #force_inline proc "contextless" ( return Operand{reg = Register(REG_P | u16((word >> 5) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} case .PM: return Operand{reg = Register(REG_P | u16((word >> 16) & 0xF)), kind = .REGISTER, size = pqual_for_type(ot)} + case .SME_ZA_MASK: + return Operand{immediate = i64(word & 0xFF), kind = .IMMEDIATE, size = ZA_TILE_MASK} + case .SME_ZA_ARRAY: + // elem 0 marks it as an array vector rather than a tile slice. + return op_za_slice(0, u8((word >> 13) & 0x3), u8(word & 0xF), 0) case .ENC_ZT0: return Operand{reg = ZT0, kind = .REGISTER, size = 0} case .LUTI_IDX: @@ -702,8 +707,12 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .ENC_ROR_SHIFT: return Operand{immediate = i64((word >> 10) & 0x3F), kind = .IMMEDIATE, size = 1} case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - return Operand{reg = Register(REG_Z | u16(word & 0x1F)), kind = .REGISTER, - size = reg_size_for_type(ot), list_count = en == .ENC_Z_PAIR_VD ? 2 : 4} + // A pair starts on an even register and a quad on a multiple of four, + // so the bits below that are not part of the field -- ZIP and UZP tell + // themselves apart with them. + pair := en == .ENC_Z_PAIR_VD + return Operand{reg = Register(REG_Z | u16(word & (pair ? 0x1E : 0x1C))), kind = .REGISTER, + size = reg_size_for_type(ot), list_count = pair ? 2 : 4} case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: return Operand{reg = Register(REG_Z | u16((word >> 5) & 0x1F)), kind = .REGISTER, size = reg_size_for_type(ot), list_count = en == .ENC_Z_PAIR_VN ? 2 : 4} @@ -737,7 +746,8 @@ reg_from_field :: #force_inline proc "contextless" ( .V_4H_FP16, .V_8H_FP16, .V_1Q, .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: cls = REG_V - case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_REG_ANY: + case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_REG_ANY, + .Z_LIST1_B, .Z_LIST1_H, .Z_LIST1_S, .Z_LIST1_D, .Z_LIST2_B: cls = REG_Z case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV, .P_REG_B, .P_REG_H, .P_REG_S, .P_REG_D: @@ -746,6 +756,8 @@ reg_from_field :: #force_inline proc "contextless" ( cls = REG_PN case .ZT_REG: cls = REG_ZT + case .ZA_ARRAY: + cls = REG_ZA case .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D, .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: cls = REG_Z @@ -786,6 +798,10 @@ reg_size_for_type :: #force_inline proc "contextless" (ot: Operand_Type) -> u8 { case .Z_REG_S: return 4 case .Z_REG_D: return 8 case .Z_REG_ANY: return 0 // no element size in the syntax + case .Z_LIST1_B, .Z_LIST2_B: return 1 + case .Z_LIST1_H: return 2 + case .Z_LIST1_S: return 4 + case .Z_LIST1_D: return 8 case .P_REG_ZERO, .PN_REG_ZERO: return PQUAL_ZERO case .P_REG_MERGE: return PQUAL_MERGE case .P_REG_B: return PSHAPE_B diff --git a/core/rexcode/isa/arm64/encoder.odin b/core/rexcode/isa/arm64/encoder.odin index 58a5699d3..a4936559a 100644 --- a/core/rexcode/isa/arm64/encoder.odin +++ b/core/rexcode/isa/arm64/encoder.odin @@ -263,6 +263,12 @@ operand_matches_inline :: #force_inline proc "contextless" ( return op.kind == .REGISTER && reg_class(op.reg) == REG_PN case .ZT_REG: return op.kind == .REGISTER && reg_class(op.reg) == REG_ZT + case .ZA_ARRAY: + return op.kind == .ZA_SLICE + case .Z_LIST1_B, .Z_LIST1_H, .Z_LIST1_S, .Z_LIST1_D: + return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && op.list_count <= 1 + case .Z_LIST2_B: + return op.kind == .REGISTER && reg_class(op.reg) == REG_Z && op.list_count == 2 // The first register of a pair must be even, of a quad a multiple of four. case .Z_REG_ANY: return op.kind == .REGISTER && reg_class(op.reg) == REG_Z @@ -661,6 +667,10 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0xF) << 5 case .PM: return (u32(reg_hw(op.reg)) & 0xF) << 16 + case .SME_ZA_MASK: + return u32(op.immediate) & 0xFF + case .SME_ZA_ARRAY: + return ((u32(op.za.ws) & 0x3) << 13) | (u32(op.za.offset) & 0xF) case .ENC_ZT0: return 0 case .LUTI_IDX: @@ -852,8 +862,7 @@ pack_operand_inline :: #force_inline proc( return (u32(op.immediate) & 0x3F) << 10 case .ENC_Z_PAIR_VD, .ENC_Z_QUAD_VD: - // Pack first Z reg into Vd slot (bits 4:0). - return (u32(reg_hw(op.reg)) & 0x1F) << 0 + return u32(reg_hw(op.reg)) & (enc == .ENC_Z_PAIR_VD ? 0x1E : 0x1C) case .ENC_Z_PAIR_VN, .ENC_Z_QUAD_VN: return (u32(reg_hw(op.reg)) & 0x1F) << 5 case .ENC_Z_PAIR_VM, .ENC_Z_QUAD_VM: diff --git a/core/rexcode/isa/arm64/encoding_types.odin b/core/rexcode/isa/arm64/encoding_types.odin index b0f8092e4..83f06358e 100644 --- a/core/rexcode/isa/arm64/encoding_types.odin +++ b/core/rexcode/isa/arm64/encoding_types.odin @@ -203,6 +203,12 @@ Operand_Type :: enum u8 { // needs; a store writes it bare. PN_REG, PN_REG_ZERO, ZT_REG, // ZT0 -- SME2's lookup table, and the only one of its kind + ZA_ARRAY, // a ZA array vector, addressed by Wn plus an offset + // A Z register written as a table list. SVE's TBL takes one table or two, + // and unlike LD2 the caller chooses which, so the count has to be in the + // operand type for the matcher to tell the two forms apart. + Z_LIST1_B, Z_LIST1_H, Z_LIST1_S, Z_LIST1_D, + Z_LIST2_B, // A predicate that is written with an element size because it is the // instruction's destination (`cmpge p0.b, p1/z, ...`). P_REG_B, P_REG_H, P_REG_S, P_REG_D, @@ -412,6 +418,8 @@ Operand_Encoding :: enum u8 { PNG, // bits 10-12, predicate-as-counter (SME2) ENC_ZT0, // no bits at all; there is only one ZT register LUTI_IDX, // bits 15-16, LUTI2/LUTI4 table index + SME_ZA_ARRAY, // `za[w12, 0]` -- a vector of the ZA array, not a tile + SME_ZA_MASK, // bits 0-7, ZERO's per-tile mask // SVE scalar+scalar addressing scales the index by the access size, and the // assembler wants that written out (`[x0, x0, lsl #2]`). The amount is a // property of the form, so it rides on the encoding. diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 606deca71..56f9855e0 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -435,7 +435,7 @@ inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}, {}}} } inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } -inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } +inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_mem(mem), {}, {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } @@ -444,7 +444,7 @@ emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Inst inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}, {}}} } inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}, {}}} } -inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}, {}}} } +inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_mem(mem), {}, {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } @@ -3159,16 +3159,18 @@ emit_ext_v16b_v16b_v16b_i :: #force_inline proc(instructions: ^[dynamic]Inst emit_ext_zb_zb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_ext_zb_zb_zb_i(rz, rz2, rz3, imm)) } inst_tbl_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } inst_tbl_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } -inst_tbl_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } -inst_tbl_zh_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}, {}}} } -inst_tbl_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}, {}}} } -inst_tbl_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } +inst_tbl_zb_zl1b_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_v_list(Register(REG_Z | (u16(rz2) & 0x1F)), ZSHAPE_B, 1), op_z_b(rz3), {}, {}}} } +inst_tbl_zh_zl1h_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_v_list(Register(REG_Z | (u16(rz2) & 0x1F)), ZSHAPE_H, 1), op_z_h(rz3), {}, {}}} } +inst_tbl_zs_zl1s_zs :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_s(rz), op_v_list(Register(REG_Z | (u16(rz2) & 0x1F)), ZSHAPE_S, 1), op_z_s(rz3), {}, {}}} } +inst_tbl_zd_zl1d_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_d(rz), op_v_list(Register(REG_Z | (u16(rz2) & 0x1F)), ZSHAPE_D, 1), op_z_d(rz3), {}, {}}} } +inst_tbl_zb_zl2b_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_v_list(Register(REG_Z | (u16(rz2) & 0x1F)), ZSHAPE_B, 2), op_z_b(rz3), {}, {}}} } emit_tbl_v8b_v16b_v8b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v8b_v16b_v8b(dst, src, src2)) } emit_tbl_v16b_v16b_v16b :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_tbl_v16b_v16b_v16b(dst, src, src2)) } -emit_tbl_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zb_zb(rz, rz2, rz3)) } -emit_tbl_zh_zh_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zh_zh_zh(rz, rz2, rz3)) } -emit_tbl_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zs_zs_zs(rz, rz2, rz3)) } -emit_tbl_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zd_zd_zd(rz, rz2, rz3)) } +emit_tbl_zb_zl1b_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zl1b_zb(rz, rz2, rz3)) } +emit_tbl_zh_zl1h_zh :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zh_zl1h_zh(rz, rz2, rz3)) } +emit_tbl_zs_zl1s_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zs_zl1s_zs(rz, rz2, rz3)) } +emit_tbl_zd_zl1d_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zd_zl1d_zd(rz, rz2, rz3)) } +emit_tbl_zb_zl2b_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl_zb_zl2b_zb(rz, rz2, rz3)) } inst_tbx_v8b_v16b_v8b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_8b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_8b(src2), {}, {}}} } inst_tbx_v16b_v16b_v16b :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_v_16b(dst), op_v_list(src, VSHAPE_16B, 1), op_v_16b(src2), {}, {}}} } inst_tbx_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } @@ -3901,8 +3903,6 @@ inst_sbclt_zs_zs_zs :: #force_inline proc "contextless" (rz: u8, rz2: inst_sbclt_zd_zd_zd :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SBCLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), {}, {}}} } emit_sbclt_zs_zs_zs :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zs_zs_zs(rz, rz2, rz3)) } emit_sbclt_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sbclt_zd_zd_zd(rz, rz2, rz3)) } -inst_tbl2_zb_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}, {}}} } -emit_tbl2_zb_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_tbl2_zb_zb_zb(rz, rz2, rz3)) } inst_match_pb_p_zb_zb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4), {}}} } inst_match_ph_p_zh_zh :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4), {}}} } emit_match_pb_p_zb_zb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_match_pb_p_zb_zb(rz, rz2, rz3, rz4)) } @@ -5640,8 +5640,8 @@ inst_mov :: proc{ inst_mov_v8b_v8b, inst_mov_zb_p_zb, emit_mov :: proc{ emit_mov_v8b_v8b, emit_mov_zb_p_zb, emit_mov_pb_p, emit_mov_r_i } inst_ext :: proc{ inst_ext_v8b_v8b_v8b_i, inst_ext_zb_zb_zb_i } emit_ext :: proc{ emit_ext_v8b_v8b_v8b_i, emit_ext_zb_zb_zb_i } -inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_zb_zb_zb } -emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_zb_zb_zb } +inst_tbl :: proc{ inst_tbl_v8b_v16b_v8b, inst_tbl_zb_zl1b_zb } +emit_tbl :: proc{ emit_tbl_v8b_v16b_v8b, emit_tbl_zb_zl1b_zb } inst_tbx :: proc{ inst_tbx_v8b_v16b_v8b, inst_tbx_zb_zb_zb } emit_tbx :: proc{ emit_tbx_v8b_v16b_v8b, emit_tbx_zb_zb_zb } inst_zip1 :: proc{ inst_zip1_v8b_v8b_v8b, inst_zip1_zb_zb_zb } @@ -5848,8 +5848,6 @@ inst_sbclb :: inst_sbclb_zs_zs_zs emit_sbclb :: emit_sbclb_zs_zs_zs inst_sbclt :: inst_sbclt_zs_zs_zs emit_sbclt :: emit_sbclt_zs_zs_zs -inst_tbl2 :: inst_tbl2_zb_zb_zb -emit_tbl2 :: emit_tbl2_zb_zb_zb inst_match :: inst_match_pb_p_zb_zb emit_match :: emit_match_pb_p_zb_zb inst_nmatch :: inst_nmatch_pb_p_zb_zb diff --git a/core/rexcode/isa/arm64/mnemonics.odin b/core/rexcode/isa/arm64/mnemonics.odin index f0b78fc27..2d8b8dd46 100644 --- a/core/rexcode/isa/arm64/mnemonics.odin +++ b/core/rexcode/isa/arm64/mnemonics.odin @@ -378,7 +378,6 @@ Mnemonic :: enum u16 { WHILEHI, WHILEHS, WHILELO, WHILELS, SQRDMLAH, SQRDMLSH, ADCLB, ADCLT, SBCLB, SBCLT, - TBL2, MATCH, NMATCH, HISTCNT, HISTSEG, diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index dc38c0db3..fe769cde6 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -181,6 +181,11 @@ LANE_INDEX :: u8(0xFF) SVE_PATTERN_IMM :: u8(0xFE) SVE_MUL_IMM :: u8(0xFD) +// ZERO's operand is an 8-bit mask, one bit per .d tile, written as the list of +// the largest tiles that exactly cover it: a .s tile is two .d tiles four +// apart, a .h tile is four two apart, and the single .b tile is all eight. +ZA_TILE_MASK :: u8(0xFC) + // The 32 SVE element-count patterns; the gaps are reserved and print as a // bare number. @(rodata) diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index cf8f3f21d..10f7f1374 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -395,6 +395,46 @@ write_sysreg :: proc(sb: ^strings.Builder, sr: System_Register, uppercase: bool) } } +// ZERO's tile list: the largest tiles that exactly cover the mask, biggest +// first, so a mask of every bit reads `{za}` rather than eight .d tiles. +@(private="file") +write_za_tile_mask :: proc(sb: ^strings.Builder, mask: u8, opts: ^Print_Options) { + strings.write_byte(sb, '{') + rest := mask + first := true + emit :: proc(sb: ^strings.Builder, first: ^bool, opts: ^Print_Options, n: int, suffix: string) { + if !first^ { + strings.write_byte(sb, ',') + if opts.space_after_comma { strings.write_byte(sb, ' ') } + } + first^ = false + strings.write_string(sb, opts.uppercase ? "ZA" : "za") + write_decimal_u32(sb, u32(n)) + if suffix != "" { + strings.write_byte(sb, '.') + strings.write_string(sb, suffix) + } + } + if rest == 0xFF { + strings.write_string(sb, opts.uppercase ? "ZA" : "za") + strings.write_byte(sb, '}') + return + } + for n in 0 ..< 2 { + bit := u8(0x55) << u8(n) + if rest & bit == bit { emit(sb, &first, opts, n, opts.uppercase ? "H" : "h"); rest &~= bit } + } + for n in 0 ..< 4 { + bit := u8(0x11) << u8(n) + if rest & bit == bit { emit(sb, &first, opts, n, opts.uppercase ? "S" : "s"); rest &~= bit } + } + for n in 0 ..< 8 { + bit := u8(1) << u8(n) + if rest & bit == bit { emit(sb, &first, opts, n, opts.uppercase ? "D" : "d"); rest &~= bit } + } + strings.write_byte(sb, '}') +} + @(private="file") write_lowercase :: proc(sb: ^strings.Builder, s: string, uppercase: bool) { for i in 0 ..< len(s) { @@ -549,6 +589,9 @@ write_operand :: proc( write_lowercase(sb, name, opts.uppercase) return } + } else if op.size == ZA_TILE_MASK { + write_za_tile_mask(sb, u8(op.immediate), opts) + return } else if op.size == SVE_MUL_IMM { strings.write_string(sb, opts.uppercase ? "MUL #" : "mul #") write_signed_decimal(sb, op.immediate) @@ -561,11 +604,13 @@ write_operand :: proc( write_sysreg(sb, op.sysreg, opts.uppercase) case .ZA_SLICE: - // `za0h.b[w12, 0]` + // `za0h.b[w12, 0]`, or plain `za[w12, 0]` for a whole array vector strings.write_string(sb, opts.uppercase ? "ZA" : "za") - write_decimal_u32(sb, u32(op.za.tile)) - strings.write_byte(sb, op.za.vertical ? (opts.uppercase ? 'V' : 'v') : (opts.uppercase ? 'H' : 'h')) - write_vector_shape(sb, Register(REG_Z), op.za.elem, opts.uppercase) + if op.za.elem != 0 { + write_decimal_u32(sb, u32(op.za.tile)) + strings.write_byte(sb, op.za.vertical ? (opts.uppercase ? 'V' : 'v') : (opts.uppercase ? 'H' : 'h')) + write_vector_shape(sb, Register(REG_Z), op.za.elem, opts.uppercase) + } strings.write_byte(sb, '[') strings.write_string(sb, opts.uppercase ? "W" : "w") write_decimal_u32(sb, 12 + u32(op.za.ws)) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index e3c910592..5957a3b13 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -33,7 +33,7 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .AMX_MATINT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012A0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .AMX_MATFP, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012C0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, { .AMX_GENLUT, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x002012E0, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_ZA_MASK,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, { .UZP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E002, 0xFFFFFC02, .SME, {explicit_count=2} }, { .ZIP, {.Z_QUAD_B,.Z_QUAD_B,.NONE,.NONE,.NONE}, {.ENC_Z_QUAD_VD,.ENC_Z_QUAD_VN,.NONE,.NONE,.NONE}, 0xC136E000, 0xFFFFFC00, .SME, {explicit_count=2} }, { .LUTI2, {.Z_PAIR_B,.ZT_REG,.Z_REG_ANY,.VEC_INDEX,.NONE}, {.ENC_Z_PAIR_VD,.ENC_ZT0,.VN,.LUTI_IDX,.NONE}, 0xC08C4000, 0xFFFE7C00, .SME, {explicit_count=4} }, @@ -78,8 +78,8 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA1800000, 0xFFE08010, .SME, {explicit_count=5} }, { .SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0xA0A00000, 0xFFE08010, .SME, {explicit_count=5} }, { .MOVA, {.SME_SLICE_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.SME_SLICE_B,.PG,.VN,.NONE,.NONE}, 0xC0000000, 0xFFE08010, .SME, {explicit_count=3} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, + { .LDR, {.ZA_ARRAY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SME_ZA_ARRAY,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, + { .STR, {.ZA_ARRAY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SME_ZA_ARRAY,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, { .LD1B, {.SME_SLICE_B,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE,.NONE}, 0xE0000000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1H, {.SME_SLICE_H,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_H,.PG,.SVE_OFFSET_BASE_SS1,.NONE,.NONE}, 0xE0400000, 0xFFE00010, .SME, {explicit_count=3} }, { .LD1W, {.SME_SLICE_W,.P_REG_ZERO,.MEM_SVE_SS,.NONE,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE,.NONE}, 0xE0800000, 0xFFE00010, .SME, {explicit_count=3} }, @@ -516,10 +516,11 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .BSL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203C00, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=4} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_LIST1_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_LIST1_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_LIST1_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_LIST1_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_LIST2_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN_LIST2,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .TBX, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202C00, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .ZIP1, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .ZIP1, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {explicit_count=3} }, @@ -568,7 +569,6 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .SBCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D000, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .HISTSEG, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4520A000, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.IMM_5,.IMM_5,.NONE,.NONE}, {.VD,.SVE_IMM5A,.SVE_IMM5,.NONE,.NONE}, 0x04204000, 0xFFE0FC00, .SVE, {explicit_count=3} }, { .INDEX, {.Z_REG_B,.IMM_5,.W_REG,.NONE,.NONE}, {.VD,.SVE_IMM5A,.RM,.NONE,.NONE}, 0x04204800, 0xFFE0FC00, .SVE, {explicit_count=3} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 5dbff414b..63513037f 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -386,7 +386,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, + { .LDR, {.ZA_ARRAY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SME_ZA_ARRAY,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, { .STR, {.X_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0xF9000000, 0xFFC00000, .BASE, {is_64=true, explicit_count=2} }, @@ -403,7 +403,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, + { .STR, {.ZA_ARRAY,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.SME_ZA_ARRAY,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, { .LDRB, {.W_REG,.MEM_PRE,.NONE,.NONE,.NONE}, {.RT,.OFFSET_BASE_PRE,.NONE,.NONE,.NONE}, 0x38400C00, 0xFFE00C00, .BASE, {explicit_count=2} }, @@ -2437,10 +2437,11 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .TBL { .TBL, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBL, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {explicit_count=3} }, - { .TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, - { .TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_LIST1_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_H,.Z_LIST1_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_S,.Z_LIST1_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {explicit_count=3} }, + { .TBL, {.Z_REG_D,.Z_LIST1_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, + { .TBL, {.Z_REG_B,.Z_LIST2_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN_LIST2,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .TBX { .TBX, {.V_8B,.V_16B,.V_8B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, { .TBX, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN_LIST1,.VM,.NONE,.NONE}, 0x4E001000, 0xFFE0FC00, .NEON, {explicit_count=3} }, @@ -2918,8 +2919,6 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .SBCLT { .SBCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {explicit_count=3} }, { .SBCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true, explicit_count=3} }, - // .TBL2 - { .TBL2, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {explicit_count=3} }, // .MATCH { .MATCH, {.P_REG_B,.P_REG_ZERO,.Z_REG_B,.Z_REG_B,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, { .MATCH, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true, explicit_count=4} }, @@ -2942,7 +2941,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .ADDVA { .ADDVA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.NONE}, {.ZA_TILE_LOW,.PG,.PM3,.VN,.NONE}, 0xC0910000, 0xFFFF001C, .SME, {explicit_count=4} }, // .ZERO - { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_PATTERN_FIELD,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, + { .ZERO, {.SME_PATTERN,.NONE,.NONE,.NONE,.NONE}, {.SME_ZA_MASK,.NONE,.NONE,.NONE,.NONE}, 0xC0080000, 0xFFFFFF00, .SME, {explicit_count=1} }, // .FMOPA { .FMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN,.VM}, 0x80800000, 0xFFE08010, .SME, {explicit_count=5} }, // .FMOPS @@ -5971,6 +5970,7 @@ CLOBBER_FORMS := [2671]lib.Clobber{ {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .TBX {written={0}, read={0, 1, 2}}, {written={0}, read={0, 1, 2}}, @@ -6448,8 +6448,6 @@ CLOBBER_FORMS := [2671]lib.Clobber{ // .SBCLT {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, - // .TBL2 - {written={0}, read={1, 2}}, // .MATCH {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, {written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}, @@ -7588,111 +7586,110 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .INS = { 1883, 8}, .MOV = { 1891, 12}, .EXT = { 1903, 4}, - .TBL = { 1907, 6}, - .TBX = { 1913, 3}, - .ZIP1 = { 1916, 12}, - .ZIP2 = { 1928, 12}, - .UZP1 = { 1940, 12}, - .UZP2 = { 1952, 12}, - .TRN1 = { 1964, 12}, - .TRN2 = { 1976, 12}, - .NOT = { 1988, 3}, - .REV64 = { 1991, 6}, - .CNT = { 1997, 6}, - .URECPE = { 2003, 2}, - .URSQRTE = { 2005, 2}, - .MOVI = { 2007, 7}, - .MVNI = { 2014, 4}, - .LD1 = { 2018, 8}, - .LD2 = { 2026, 5}, - .LD3 = { 2031, 5}, - .LD4 = { 2036, 5}, - .ST1 = { 2041, 8}, - .ST2 = { 2049, 5}, - .ST3 = { 2054, 5}, - .ST4 = { 2059, 5}, - .LD1R = { 2064, 1}, - .LD2R = { 2065, 1}, - .LD3R = { 2066, 1}, - .LD4R = { 2067, 1}, - .SUBR = { 2068, 4}, - .ASRR = { 2072, 4}, - .LSLR = { 2076, 4}, - .LSRR = { 2080, 4}, - .FTSMUL = { 2084, 3}, - .FSUBR = { 2087, 3}, - .FDIVR = { 2090, 3}, - .FNMLA = { 2093, 3}, - .FNMLS = { 2096, 3}, - .NAND = { 2099, 1}, - .NOR = { 2100, 1}, - .SEL = { 2101, 1}, - .ORRS = { 2102, 1}, - .EORS = { 2103, 1}, - .NANDS = { 2104, 1}, - .NORS = { 2105, 1}, - .ORNS = { 2106, 1}, - .MOVS = { 2107, 1}, - .PTRUE = { 2108, 1}, - .PTRUES = { 2109, 1}, - .PFALSE = { 2110, 1}, - .PFIRST = { 2111, 1}, - .PNEXT = { 2112, 1}, - .BRKA = { 2113, 1}, - .BRKB = { 2114, 1}, - .BRKAS = { 2115, 1}, - .BRKBS = { 2116, 1}, - .BRKPA = { 2117, 1}, - .BRKPB = { 2118, 1}, - .BRKN = { 2119, 1}, - .RDFFR = { 2120, 1}, - .WRFFR = { 2121, 1}, - .SETFFR = { 2122, 1}, - .CMPEQ = { 2123, 4}, - .CMPNE = { 2127, 4}, - .CMPGE = { 2131, 4}, - .CMPGT = { 2135, 4}, - .CMPLE = { 2139, 4}, - .CMPLT = { 2143, 4}, - .CMPHI = { 2147, 4}, - .CMPHS = { 2151, 4}, - .CMPLO = { 2155, 4}, - .CMPLS = { 2159, 4}, - .FCMNE = { 2163, 3}, - .FCMUO = { 2166, 3}, - .INSR = { 2169, 4}, - .CPY = { 2173, 4}, - .COMPACT = { 2177, 2}, - .LD1B = { 2179, 6}, - .LD1H = { 2185, 6}, - .LD1W = { 2191, 6}, - .LD1D = { 2197, 5}, - .LD1SB = { 2202, 3}, - .LD1SH = { 2205, 4}, - .LD1SW = { 2209, 2}, - .ST1B = { 2211, 6}, - .ST1H = { 2217, 7}, - .ST1W = { 2224, 6}, - .ST1D = { 2230, 5}, - .LDFF1B = { 2235, 1}, - .LDFF1H = { 2236, 1}, - .LDFF1W = { 2237, 1}, - .LDFF1D = { 2238, 1}, - .WHILEGE = { 2239, 4}, - .WHILEGT = { 2243, 4}, - .WHILELE = { 2247, 4}, - .WHILELT = { 2251, 4}, - .WHILEHI = { 2255, 4}, - .WHILEHS = { 2259, 4}, - .WHILELO = { 2263, 4}, - .WHILELS = { 2267, 4}, - .SQRDMLAH = { 2271, 4}, - .SQRDMLSH = { 2275, 4}, - .ADCLB = { 2279, 2}, - .ADCLT = { 2281, 2}, - .SBCLB = { 2283, 2}, - .SBCLT = { 2285, 2}, - .TBL2 = { 2287, 1}, + .TBL = { 1907, 7}, + .TBX = { 1914, 3}, + .ZIP1 = { 1917, 12}, + .ZIP2 = { 1929, 12}, + .UZP1 = { 1941, 12}, + .UZP2 = { 1953, 12}, + .TRN1 = { 1965, 12}, + .TRN2 = { 1977, 12}, + .NOT = { 1989, 3}, + .REV64 = { 1992, 6}, + .CNT = { 1998, 6}, + .URECPE = { 2004, 2}, + .URSQRTE = { 2006, 2}, + .MOVI = { 2008, 7}, + .MVNI = { 2015, 4}, + .LD1 = { 2019, 8}, + .LD2 = { 2027, 5}, + .LD3 = { 2032, 5}, + .LD4 = { 2037, 5}, + .ST1 = { 2042, 8}, + .ST2 = { 2050, 5}, + .ST3 = { 2055, 5}, + .ST4 = { 2060, 5}, + .LD1R = { 2065, 1}, + .LD2R = { 2066, 1}, + .LD3R = { 2067, 1}, + .LD4R = { 2068, 1}, + .SUBR = { 2069, 4}, + .ASRR = { 2073, 4}, + .LSLR = { 2077, 4}, + .LSRR = { 2081, 4}, + .FTSMUL = { 2085, 3}, + .FSUBR = { 2088, 3}, + .FDIVR = { 2091, 3}, + .FNMLA = { 2094, 3}, + .FNMLS = { 2097, 3}, + .NAND = { 2100, 1}, + .NOR = { 2101, 1}, + .SEL = { 2102, 1}, + .ORRS = { 2103, 1}, + .EORS = { 2104, 1}, + .NANDS = { 2105, 1}, + .NORS = { 2106, 1}, + .ORNS = { 2107, 1}, + .MOVS = { 2108, 1}, + .PTRUE = { 2109, 1}, + .PTRUES = { 2110, 1}, + .PFALSE = { 2111, 1}, + .PFIRST = { 2112, 1}, + .PNEXT = { 2113, 1}, + .BRKA = { 2114, 1}, + .BRKB = { 2115, 1}, + .BRKAS = { 2116, 1}, + .BRKBS = { 2117, 1}, + .BRKPA = { 2118, 1}, + .BRKPB = { 2119, 1}, + .BRKN = { 2120, 1}, + .RDFFR = { 2121, 1}, + .WRFFR = { 2122, 1}, + .SETFFR = { 2123, 1}, + .CMPEQ = { 2124, 4}, + .CMPNE = { 2128, 4}, + .CMPGE = { 2132, 4}, + .CMPGT = { 2136, 4}, + .CMPLE = { 2140, 4}, + .CMPLT = { 2144, 4}, + .CMPHI = { 2148, 4}, + .CMPHS = { 2152, 4}, + .CMPLO = { 2156, 4}, + .CMPLS = { 2160, 4}, + .FCMNE = { 2164, 3}, + .FCMUO = { 2167, 3}, + .INSR = { 2170, 4}, + .CPY = { 2174, 4}, + .COMPACT = { 2178, 2}, + .LD1B = { 2180, 6}, + .LD1H = { 2186, 6}, + .LD1W = { 2192, 6}, + .LD1D = { 2198, 5}, + .LD1SB = { 2203, 3}, + .LD1SH = { 2206, 4}, + .LD1SW = { 2210, 2}, + .ST1B = { 2212, 6}, + .ST1H = { 2218, 7}, + .ST1W = { 2225, 6}, + .ST1D = { 2231, 5}, + .LDFF1B = { 2236, 1}, + .LDFF1H = { 2237, 1}, + .LDFF1W = { 2238, 1}, + .LDFF1D = { 2239, 1}, + .WHILEGE = { 2240, 4}, + .WHILEGT = { 2244, 4}, + .WHILELE = { 2248, 4}, + .WHILELT = { 2252, 4}, + .WHILEHI = { 2256, 4}, + .WHILEHS = { 2260, 4}, + .WHILELO = { 2264, 4}, + .WHILELS = { 2268, 4}, + .SQRDMLAH = { 2272, 4}, + .SQRDMLSH = { 2276, 4}, + .ADCLB = { 2280, 2}, + .ADCLT = { 2282, 2}, + .SBCLB = { 2284, 2}, + .SBCLT = { 2286, 2}, .MATCH = { 2288, 2}, .NMATCH = { 2290, 2}, .HISTCNT = { 2292, 2}, diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 89a3fbc05..7a1c27281 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -555,7 +555,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, + {{.LDR, {.ZA_ARRAY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SME_ZA_ARRAY, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { {{.STR, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0xB9000000, 0xFFC00000, .BASE, {}}, Clobber{read={0, 1}, writes_mem=true}}, @@ -573,7 +573,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, + {{.STR, {.ZA_ARRAY, .MEM_SVE_SI, .NONE, .NONE, .NONE}, {.SME_ZA_ARRAY, .SVE_OFFSET_BASE_SI, .NONE, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { {{.LDRB, {.W_REG, .MEM_OFFSET, .NONE, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE, .NONE}, 0x39400000, 0xFFC00000, .BASE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, @@ -3050,10 +3050,11 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ .TBL = { {{.TBL, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, {{.TBL, {.V_16B, .V_16B, .V_16B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x4E000000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, - {{.TBL, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_LIST1_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x05203000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_H, .Z_LIST1_H, .Z_REG_H, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x05603000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_S, .Z_LIST1_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_D, .Z_LIST1_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.TBL, {.Z_REG_B, .Z_LIST2_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN_LIST2, .VM, .NONE, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .TBX = { {{.TBX, {.V_8B, .V_16B, .V_8B, .NONE, .NONE}, {.VD, .VN_LIST1, .VM, .NONE, .NONE}, 0x0E001000, 0xFFE0FC00, .NEON, {}}, Clobber{written={0}, read={0, 1, 2}}}, @@ -3635,9 +3636,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.SBCLT, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x4580D400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, {{.SBCLT, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x45C0D400, 0xFFE0FC00, .SVE2, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, - .TBL2 = { - {{.TBL2, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0x05202800, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, - }, + .MATCH = { {{.MATCH, {.P_REG_B, .P_REG_ZERO, .Z_REG_B, .Z_REG_B, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45208000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, {{.MATCH, {.P_REG_H, .P_REG_ZERO, .Z_REG_H, .Z_REG_H, .NONE}, {.PD, .PG, .VN, .VM, .NONE}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true}}, Clobber{written={0}, read={1, 2, 3}, nzcv_wr={.N, .Z, .C, .V}}}, @@ -3669,7 +3668,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.ADDVA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .NONE}, {.ZA_TILE_LOW, .PG, .PM3, .VN, .NONE}, 0xC0910000, 0xFFFF001C, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}}}, }, .ZERO = { - {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE, .NONE}, {.SME_PATTERN_FIELD, .NONE, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, + {{.ZERO, {.SME_PATTERN, .NONE, .NONE, .NONE, .NONE}, {.SME_ZA_MASK, .NONE, .NONE, .NONE, .NONE}, 0xC0080000, 0xFFFFFF00, .SME, {}}, Clobber{}}, }, .FMOPA = { {{.FMOPA, {.ZA_TILE_S, .P_REG_MERGE, .P_REG_MERGE, .Z_REG_S, .Z_REG_S}, {.ZA_TILE_NUM_S, .PG, .PM3, .VN, .VM}, 0x80800000, 0xFFE08010, .SME, {}}, Clobber{written={0}, read={0, 1, 2, 3}, fpsr_wr={.IOC, .OFC, .UFC, .IXC, .IDC}, reads_fpcr=true}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index 576647483f3e86067152c0c84119549f00f1a62a..5c167e088432ba476ef3bee12a67ea75026d6194 100644 GIT binary patch delta 38 wcmV+>0NMYNqymzp0g(qymzp0iX lFOx5CeX}5M0S=LW4wH*?JChDTCX)^h43iL!5VM|rbQCY89`67E diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index f5b8081156230b4d9278507cd03fc32614ea6b35..6a25c6860a5e8b71c17d1a162a3460b7ab4d5671 100644 GIT binary patch delta 14222 zcmZvidwf*Ywa53_6CeahPC`x~kYolDTAMHuEm&`*GRQ*&0--zuRt^d}5CTEbQXie+ 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zHR>OV^Z_TeBvwymmpQL=8uu9;SR1&txj?f67dP$``wloIuSH^66ML=i!vj}Z)?!il z#x!ej-@~)0tMim_C1QuIo3Drt#!QQFa+WL zr`MIS(ei`;Z#$`cGT+uE4!aC%n`lGRTRjlJkROcS8bEI$j bq25@kGO{gLx!x>Q5$YLQ-B Operand_Category { .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: return .REG case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_REG_ANY, + .Z_LIST1_B, .Z_LIST1_H, .Z_LIST1_S, .Z_LIST1_D, .Z_LIST2_B, .Z_PAIR_B, .Z_PAIR_H, .Z_PAIR_S, .Z_PAIR_D, .Z_QUAD_B, .Z_QUAD_H, .Z_QUAD_S, .Z_QUAD_D: return .ZREG @@ -182,9 +183,9 @@ list_count :: proc(e: a.Operand_Encoding) -> int { // The ZSHAPE_* constant naming this operand type's SVE element width. zshape_const :: proc(t: a.Operand_Type) -> string { #partial switch t { - case .Z_REG_H, .Z_PAIR_H, .Z_QUAD_H: return "ZSHAPE_H" - case .Z_REG_S, .Z_PAIR_S, .Z_QUAD_S: return "ZSHAPE_S" - case .Z_REG_D, .Z_PAIR_D, .Z_QUAD_D: return "ZSHAPE_D" + case .Z_REG_H, .Z_PAIR_H, .Z_QUAD_H, .Z_LIST1_H: return "ZSHAPE_H" + case .Z_REG_S, .Z_PAIR_S, .Z_QUAD_S, .Z_LIST1_S: return "ZSHAPE_S" + case .Z_REG_D, .Z_PAIR_D, .Z_QUAD_D, .Z_LIST1_D: return "ZSHAPE_D" } return "ZSHAPE_B" } @@ -253,6 +254,11 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { case .Z_REG_H: return "zh" case .Z_REG_S: return "zs" case .Z_REG_D: return "zd" + case .Z_LIST1_B: return "zl1b" + case .Z_LIST1_H: return "zl1h" + case .Z_LIST1_S: return "zl1s" + case .Z_LIST1_D: return "zl1d" + case .Z_LIST2_B: return "zl2b" case .Z_PAIR_B: return "zpb" case .Z_PAIR_H: return "zph" case .Z_PAIR_S: return "zps" From e4a7f6146d3a03f465b6833888dcbc46660ba662 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 19:41:43 -0400 Subject: [PATCH 54/89] rexcode/arm64: XAR's reserved encoding is not an instruction A tsz of zero has no set bit, so it names no element size at all; the architecture reserves it and llvm-mc calls the word invalid. We decoded it as `xar z0.b, z0.b, z0.b, #16` -- a shift of 16 on a byte, which is not a thing. No single mask says "tsz is not zero", but four do, the same way the cset aliases exclude AL and NV: 1xxx, 01xx, 001x, 0001 cover every non-zero value between them and nothing else. Splitting it that way broke encode at first, because the four forms have the same operand types and the matcher took whichever came first, ORing its fixed tsz bit onto a value meant for a different element size. Each pattern pins exactly the bit its own element size sets, though, so typing the operands by size makes the matcher pick the right one and the OR consistent. SVE/SME2 against llvm-mc: 707 of 707 byte-exact, nothing mismatched and nothing it cannot assemble. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm64/mnemonic_builders.odin | 14 +- .../tablegen/generated/decode_tables.odin | 33 +- .../tablegen/generated/encode_tables.odin | 1084 +++++++++-------- .../isa/arm64/tablegen/instruction_table.odin | 5 +- .../isa/arm64/tables/arm64.clobber_forms.bin | Bin 37394 -> 37436 bytes .../isa/arm64/tables/arm64.encode_forms.bin | Bin 58762 -> 58828 bytes .../isa/arm64/tables/arm64.encode_runs.bin | Bin 6840 -> 6840 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 58806 -> 58872 bytes .../isa/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes 9 files changed, 577 insertions(+), 559 deletions(-) diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 56f9855e0..477f8b11e 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -1372,9 +1372,15 @@ emit_bcax_zd_zd_zd_zd :: #force_inline proc(instructions: ^[dynamic]Inst inst_rax1_v2d_v2d_v2d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), {}, {}}} } emit_rax1_v2d_v2d_v2d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_v2d_v2d_v2d(dst, src, src2)) } inst_xar_v2d_v2d_v2d_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(dst), op_v_2d(src), op_v_2d(src2), op_imm(imm, 1), {}}} } -inst_xar_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_reg(Register(REG_Z | (u16(rz3) & 0x1F))), op_imm(imm, 4), {}}} } +inst_xar_zd_zd_zd_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 4), {}}} } +inst_xar_zs_zs_zs_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 4), {}}} } +inst_xar_zh_zh_zh_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 4), {}}} } +inst_xar_zb_zb_zb_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 4), {}}} } emit_xar_v2d_v2d_v2d_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_v2d_v2d_v2d_i(dst, src, src2, imm)) } -emit_xar_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_z_z_z_i(rz, rz2, rz3, imm)) } +emit_xar_zd_zd_zd_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_zd_zd_zd_i(rz, rz2, rz3, imm)) } +emit_xar_zs_zs_zs_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_zs_zs_zs_i(rz, rz2, rz3, imm)) } +emit_xar_zh_zh_zh_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_zh_zh_zh_i(rz, rz2, rz3, imm)) } +emit_xar_zb_zb_zb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_xar_zb_zb_zb_i(rz, rz2, rz3, imm)) } inst_sm3partw1_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } emit_sm3partw1_v4s_v4s_v4s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_v4s_v4s_v4s(dst, src, src2)) } inst_sm3partw2_v4s_v4s_v4s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(dst), op_v_4s(src), op_v_4s(src2), {}, {}}} } @@ -5240,8 +5246,8 @@ inst_bcax :: proc{ inst_bcax_v16b_v16b_v16b_v16b, inst_ emit_bcax :: proc{ emit_bcax_v16b_v16b_v16b_v16b, emit_bcax_zd_zd_zd_zd } inst_rax1 :: inst_rax1_v2d_v2d_v2d emit_rax1 :: emit_rax1_v2d_v2d_v2d -inst_xar :: proc{ inst_xar_v2d_v2d_v2d_i, inst_xar_z_z_z_i } -emit_xar :: proc{ emit_xar_v2d_v2d_v2d_i, emit_xar_z_z_z_i } +inst_xar :: proc{ inst_xar_v2d_v2d_v2d_i, inst_xar_zd_zd_zd_i } +emit_xar :: proc{ emit_xar_v2d_v2d_v2d_i, emit_xar_zd_zd_zd_i } inst_sm3partw1 :: inst_sm3partw1_v4s_v4s_v4s emit_sm3partw1 :: emit_sm3partw1_v4s_v4s_v4s inst_sm3partw2 :: inst_sm3partw2_v4s_v4s_v4s diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 5957a3b13..ee8e512ac 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [2673]lib.Decode_Entry{ +DECODE_ENTRIES := [2676]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} }, @@ -282,6 +282,7 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .FRINTZ, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6543A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x6583A000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .FRINTZ, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x65C3A000, 0xFFFFE000, .SVE, {is_64=true, explicit_count=3} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04283400, 0xFFF8FC00, .SVE2, {explicit_count=4} }, { .BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {explicit_count=3} }, { .MUL, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04100000, 0xFFFFE000, .SVE, {explicit_count=4} }, { .MUL, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.PG,.VD,.VN,.NONE}, 0x04500000, 0xFFFFE000, .SVE, {explicit_count=4} }, @@ -358,6 +359,7 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .FNEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x045DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x049DA000, 0xFFFDE000, .SVE, {explicit_count=3} }, { .FNEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04DDA000, 0xFFFDE000, .SVE, {is_64=true, explicit_count=3} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04303400, 0xFFF0FC00, .SVE2, {explicit_count=4} }, { .NEG, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0417A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, @@ -485,6 +487,7 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .FMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=3} }, { .EOR3, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04203800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, { .BCAX, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VD,.VM,.VN,.NONE}, 0x04603800, 0xFFE0FC00, .SVE, {is_64=true, explicit_count=4} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04603400, 0xFFE0FC00, .SVE2, {explicit_count=4} }, { .ABS, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0416A000, 0xFFF6E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0456A000, 0xFFF6E000, .SVE, {explicit_count=3} }, { .ABS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0496A000, 0xFFF6E000, .SVE, {explicit_count=3} }, @@ -600,6 +603,7 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .CLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0458A000, 0xFFF8E000, .SVE, {explicit_count=3} }, { .CLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x0498A000, 0xFFF8E000, .SVE, {explicit_count=3} }, { .CLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE,.NONE}, {.VD,.PG,.VN,.NONE,.NONE}, 0x04D8A000, 0xFFF8E000, .SVE, {is_64=true, explicit_count=3} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04A03400, 0xFFA0FC00, .SVE2, {explicit_count=4} }, { .FMLA, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200000, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .FMLS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.IMM_3,.NONE}, {.VD,.VN,.VM,.SVE_FMLA_IDX_H,.NONE}, 0x64200400, 0xFFA0FC00, .SVE, {explicit_count=4} }, { .NANDS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25C04210, 0xFFF0C210, .SVE, {sets_flags=true, explicit_count=4} }, @@ -616,7 +620,6 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.PM,.NONE}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.VM,.NONE}, 0x65C06000, 0xFFE0E010, .SVE, {is_64=true, explicit_count=4} }, @@ -2687,18 +2690,18 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ @(rodata) DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x00 = { 0, 81}, - 0x02 = { 81, 667}, - 0x04 = { 748, 76}, - 0x05 = { 824, 50}, - 0x06 = { 874, 56}, - 0x07 = { 930, 1058}, - 0x08 = {1988, 16}, - 0x09 = {2004, 34}, - 0x0A = {2038, 130}, - 0x0B = {2168, 21}, - 0x0C = {2189, 167}, - 0x0D = {2356, 122}, - 0x0E = {2478, 19}, - 0x0F = {2497, 176}, + 0x02 = { 81, 670}, + 0x04 = { 751, 76}, + 0x05 = { 827, 50}, + 0x06 = { 877, 56}, + 0x07 = { 933, 1058}, + 0x08 = {1991, 16}, + 0x09 = {2007, 34}, + 0x0A = {2041, 130}, + 0x0B = {2171, 21}, + 0x0C = {2192, 167}, + 0x0D = {2359, 122}, + 0x0E = {2481, 19}, + 0x0F = {2500, 176}, } diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index 63513037f..d23ce437b 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [2671]lib.Encoding{ +ENCODE_FORMS := [2674]lib.Encoding{ // .ADD { .ADD, {.WSP_REG,.WSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x11000000, 0xFF800000, .BASE, {explicit_count=3} }, { .ADD, {.XSP_REG,.XSP_REG,.IMM_12,.NONE,.NONE}, {.RD,.RN,.IMM12,.NONE,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true, explicit_count=3} }, @@ -1336,7 +1336,10 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .RAX1, {.V_2D,.V_2D,.V_2D,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE608C00, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .XAR { .XAR, {.V_2D,.V_2D,.V_2D,.IMM_6,.NONE}, {.VD,.VN,.VM,.IMM6,.NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {explicit_count=4} }, - { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04A03400, 0xFFA0FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04603400, 0xFFE0FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04303400, 0xFFF0FC00, .SVE2, {explicit_count=4} }, + { .XAR, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.VEC_SHIFT,.NONE}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT,.NONE}, 0x04283400, 0xFFF8FC00, .SVE2, {explicit_count=4} }, // .SM3PARTW1 { .SM3PARTW1, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {explicit_count=3} }, // .SM3PARTW2 @@ -3537,7 +3540,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ } @(rodata) -CLOBBER_FORMS := [2671]lib.Clobber{ +CLOBBER_FORMS := [2674]lib.Clobber{ // .ADD {written={0}, read={1}}, {written={0}, read={1}}, @@ -4866,6 +4869,9 @@ CLOBBER_FORMS := [2671]lib.Clobber{ // .XAR {written={0}, read={1, 2}}, {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}}, // .SM3PARTW1 {written={0}, read={0, 1, 2}}, // .SM3PARTW2 @@ -7386,540 +7392,540 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .EOR3 = { 1002, 2}, .BCAX = { 1004, 2}, .RAX1 = { 1006, 1}, - .XAR = { 1007, 2}, - .SM3PARTW1 = { 1009, 1}, - .SM3PARTW2 = { 1010, 1}, - .SM3SS1 = { 1011, 1}, - .SM3TT1A = { 1012, 1}, - .SM3TT1B = { 1013, 1}, - .SM3TT2A = { 1014, 1}, - .SM3TT2B = { 1015, 1}, - .SM4E = { 1016, 1}, - .SM4EKEY = { 1017, 1}, - .PMULL = { 1018, 2}, - .PMULL2 = { 1020, 2}, - .BFCVT = { 1022, 2}, - .BFDOT = { 1024, 1}, - .BFMMLA = { 1025, 1}, - .BFMLALB = { 1026, 1}, - .BFMLALT = { 1027, 1}, - .BFCVTN = { 1028, 1}, - .BFCVTN2 = { 1029, 1}, - .MUL = { 1030, 7}, - .MLA = { 1037, 6}, - .MLS = { 1043, 6}, - .NEG = { 1049, 13}, - .ABS = { 1062, 11}, - .SHADD = { 1073, 6}, - .UHADD = { 1079, 6}, - .SHSUB = { 1085, 6}, - .UHSUB = { 1091, 6}, - .SRHADD = { 1097, 6}, - .URHADD = { 1103, 6}, - .SQADD = { 1109, 11}, - .UQADD = { 1120, 11}, - .SQSUB = { 1131, 11}, - .UQSUB = { 1142, 11}, - .SMAX = { 1153, 10}, - .UMAX = { 1163, 10}, - .SMIN = { 1173, 10}, - .UMIN = { 1183, 10}, - .SABD = { 1193, 10}, - .UABD = { 1203, 10}, - .SABA = { 1213, 6}, - .UABA = { 1219, 6}, - .ADDP = { 1225, 7}, - .ADDV = { 1232, 5}, - .SADDLP = { 1237, 6}, - .UADDLP = { 1243, 6}, - .SADALP = { 1249, 6}, - .UADALP = { 1255, 6}, - .SADDLV = { 1261, 5}, - .UADDLV = { 1266, 5}, - .SMAXV = { 1271, 5}, - .UMAXV = { 1276, 5}, - .SMINV = { 1281, 5}, - .UMINV = { 1286, 5}, - .SMAXP = { 1291, 6}, - .UMAXP = { 1297, 6}, - .SMINP = { 1303, 6}, - .UMINP = { 1309, 6}, - .SADDL = { 1315, 3}, - .SADDL2 = { 1318, 3}, - .UADDL = { 1321, 3}, - .UADDL2 = { 1324, 3}, - .SSUBL = { 1327, 3}, - .SSUBL2 = { 1330, 3}, - .USUBL = { 1333, 3}, - .USUBL2 = { 1336, 3}, - .SADDW = { 1339, 3}, - .SADDW2 = { 1342, 3}, - .UADDW = { 1345, 3}, - .UADDW2 = { 1348, 3}, - .SSUBW = { 1351, 3}, - .SSUBW2 = { 1354, 3}, - .USUBW = { 1357, 3}, - .USUBW2 = { 1360, 3}, - .RADDHN = { 1363, 3}, - .RADDHN2 = { 1366, 3}, - .RSUBHN = { 1369, 3}, - .RSUBHN2 = { 1372, 3}, - .ADDHN = { 1375, 3}, - .ADDHN2 = { 1378, 3}, - .SUBHN = { 1381, 3}, - .SUBHN2 = { 1384, 3}, - .XTN = { 1387, 3}, - .XTN2 = { 1390, 3}, - .SQXTN = { 1393, 3}, - .SQXTN2 = { 1396, 3}, - .UQXTN = { 1399, 3}, - .UQXTN2 = { 1402, 3}, - .SQXTUN = { 1405, 3}, - .SQXTUN2 = { 1408, 3}, - .SMULL = { 1411, 3}, - .SMULL2 = { 1414, 3}, - .UMULL = { 1417, 3}, - .UMULL2 = { 1420, 3}, - .SMLAL = { 1423, 3}, - .SMLAL2 = { 1426, 3}, - .UMLAL = { 1429, 3}, - .UMLAL2 = { 1432, 3}, - .SMLSL = { 1435, 3}, - .SMLSL2 = { 1438, 3}, - .UMLSL = { 1441, 3}, - .UMLSL2 = { 1444, 3}, - .SQDMULL = { 1447, 2}, - .SQDMULL2 = { 1449, 2}, - .SQDMLAL = { 1451, 2}, - .SQDMLAL2 = { 1453, 2}, - .SQDMLSL = { 1455, 2}, - .SQDMLSL2 = { 1457, 2}, - .SQDMULH = { 1459, 4}, - .SQRDMULH = { 1463, 4}, - .SDOT = { 1467, 2}, - .UDOT = { 1469, 2}, - .USDOT = { 1471, 2}, - .FMLA = { 1473, 8}, - .FMLS = { 1481, 8}, - .FMULX = { 1489, 5}, - .FMAXP = { 1494, 5}, - .FMINP = { 1499, 5}, - .FMAXNMP = { 1504, 5}, - .FMINNMP = { 1509, 5}, - .FMAXV = { 1514, 3}, - .FMINV = { 1517, 3}, - .FMAXNMV = { 1520, 3}, - .FMINNMV = { 1523, 3}, - .FRECPE = { 1526, 5}, - .FRSQRTE = { 1531, 5}, - .FRECPS = { 1536, 8}, - .FRSQRTS = { 1544, 8}, - .FRECPX = { 1552, 6}, - .FADDP = { 1558, 5}, - .FCVTL = { 1563, 2}, - .FCVTL2 = { 1565, 2}, - .FCVTN = { 1567, 2}, - .FCVTN2 = { 1569, 2}, - .FCVTXN = { 1571, 1}, - .FCVTXN2 = { 1572, 1}, - .FCMEQ = { 1573, 8}, - .FCMGE = { 1581, 8}, - .FCMGT = { 1589, 8}, - .FCMLE = { 1597, 8}, - .FCMLT = { 1605, 8}, - .FACGE = { 1613, 5}, - .FACGT = { 1618, 5}, - .CMEQ = { 1623, 4}, - .CMGE = { 1627, 7}, - .CMGT = { 1634, 2}, - .CMHI = { 1636, 2}, - .CMHS = { 1638, 7}, - .CMLE = { 1645, 7}, - .CMLT = { 1652, 7}, - .CMTST = { 1659, 7}, - .MVN = { 1666, 4}, - .BIT = { 1670, 1}, - .BIF = { 1671, 1}, - .BSL = { 1672, 2}, - .SHL = { 1674, 7}, - .SQSHL = { 1681, 7}, - .SQSHLU = { 1688, 7}, - .SRSHL = { 1695, 7}, - .URSHL = { 1702, 7}, - .SSHR = { 1709, 7}, - .USHR = { 1716, 7}, - .SSRA = { 1723, 7}, - .USRA = { 1730, 7}, - .SRSHR = { 1737, 7}, - .URSHR = { 1744, 7}, - .SRSRA = { 1751, 7}, - .URSRA = { 1758, 7}, - .SSHL = { 1765, 7}, - .USHL = { 1772, 7}, - .SLI = { 1779, 7}, - .SRI = { 1786, 7}, - .SSHLL = { 1793, 3}, - .SSHLL2 = { 1796, 3}, - .USHLL = { 1799, 3}, - .USHLL2 = { 1802, 3}, - .SXTL = { 1805, 3}, - .SXTL2 = { 1808, 3}, - .UXTL = { 1811, 3}, - .UXTL2 = { 1814, 3}, - .SHRN = { 1817, 3}, - .SHRN2 = { 1820, 3}, - .RSHRN = { 1823, 3}, - .RSHRN2 = { 1826, 3}, - .SQSHRN = { 1829, 3}, - .SQSHRN2 = { 1832, 3}, - .UQSHRN = { 1835, 3}, - .UQSHRN2 = { 1838, 3}, - .SQRSHRN = { 1841, 3}, - .SQRSHRN2 = { 1844, 3}, - .UQRSHRN = { 1847, 3}, - .UQRSHRN2 = { 1850, 3}, - .SQSHRUN = { 1853, 3}, - .SQSHRUN2 = { 1856, 3}, - .SQRSHRUN = { 1859, 3}, - .SQRSHRUN2 = { 1862, 3}, - .DUP = { 1865, 18}, - .INS = { 1883, 8}, - .MOV = { 1891, 12}, - .EXT = { 1903, 4}, - .TBL = { 1907, 7}, - .TBX = { 1914, 3}, - .ZIP1 = { 1917, 12}, - .ZIP2 = { 1929, 12}, - .UZP1 = { 1941, 12}, - .UZP2 = { 1953, 12}, - .TRN1 = { 1965, 12}, - .TRN2 = { 1977, 12}, - .NOT = { 1989, 3}, - .REV64 = { 1992, 6}, - .CNT = { 1998, 6}, - .URECPE = { 2004, 2}, - .URSQRTE = { 2006, 2}, - .MOVI = { 2008, 7}, - .MVNI = { 2015, 4}, - .LD1 = { 2019, 8}, - .LD2 = { 2027, 5}, - .LD3 = { 2032, 5}, - .LD4 = { 2037, 5}, - .ST1 = { 2042, 8}, - .ST2 = { 2050, 5}, - .ST3 = { 2055, 5}, - .ST4 = { 2060, 5}, - .LD1R = { 2065, 1}, - .LD2R = { 2066, 1}, - .LD3R = { 2067, 1}, - .LD4R = { 2068, 1}, - .SUBR = { 2069, 4}, - .ASRR = { 2073, 4}, - .LSLR = { 2077, 4}, - .LSRR = { 2081, 4}, - .FTSMUL = { 2085, 3}, - .FSUBR = { 2088, 3}, - .FDIVR = { 2091, 3}, - .FNMLA = { 2094, 3}, - .FNMLS = { 2097, 3}, - .NAND = { 2100, 1}, - .NOR = { 2101, 1}, - .SEL = { 2102, 1}, - .ORRS = { 2103, 1}, - .EORS = { 2104, 1}, - .NANDS = { 2105, 1}, - .NORS = { 2106, 1}, - .ORNS = { 2107, 1}, - .MOVS = { 2108, 1}, - .PTRUE = { 2109, 1}, - .PTRUES = { 2110, 1}, - .PFALSE = { 2111, 1}, - .PFIRST = { 2112, 1}, - .PNEXT = { 2113, 1}, - .BRKA = { 2114, 1}, - .BRKB = { 2115, 1}, - .BRKAS = { 2116, 1}, - .BRKBS = { 2117, 1}, - .BRKPA = { 2118, 1}, - .BRKPB = { 2119, 1}, - .BRKN = { 2120, 1}, - .RDFFR = { 2121, 1}, - .WRFFR = { 2122, 1}, - .SETFFR = { 2123, 1}, - .CMPEQ = { 2124, 4}, - .CMPNE = { 2128, 4}, - .CMPGE = { 2132, 4}, - .CMPGT = { 2136, 4}, - .CMPLE = { 2140, 4}, - .CMPLT = { 2144, 4}, - .CMPHI = { 2148, 4}, - .CMPHS = { 2152, 4}, - .CMPLO = { 2156, 4}, - .CMPLS = { 2160, 4}, - .FCMNE = { 2164, 3}, - .FCMUO = { 2167, 3}, - .INSR = { 2170, 4}, - .CPY = { 2174, 4}, - .COMPACT = { 2178, 2}, - .LD1B = { 2180, 6}, - .LD1H = { 2186, 6}, - .LD1W = { 2192, 6}, - .LD1D = { 2198, 5}, - .LD1SB = { 2203, 3}, - .LD1SH = { 2206, 4}, - .LD1SW = { 2210, 2}, - .ST1B = { 2212, 6}, - .ST1H = { 2218, 7}, - .ST1W = { 2225, 6}, - .ST1D = { 2231, 5}, - .LDFF1B = { 2236, 1}, - .LDFF1H = { 2237, 1}, - .LDFF1W = { 2238, 1}, - .LDFF1D = { 2239, 1}, - .WHILEGE = { 2240, 4}, - .WHILEGT = { 2244, 4}, - .WHILELE = { 2248, 4}, - .WHILELT = { 2252, 4}, - .WHILEHI = { 2256, 4}, - .WHILEHS = { 2260, 4}, - .WHILELO = { 2264, 4}, - .WHILELS = { 2268, 4}, - .SQRDMLAH = { 2272, 4}, - .SQRDMLSH = { 2276, 4}, - .ADCLB = { 2280, 2}, - .ADCLT = { 2282, 2}, - .SBCLB = { 2284, 2}, - .SBCLT = { 2286, 2}, - .MATCH = { 2288, 2}, - .NMATCH = { 2290, 2}, - .HISTCNT = { 2292, 2}, - .HISTSEG = { 2294, 1}, - .SMSTART = { 2295, 1}, - .SMSTOP = { 2296, 1}, - .RDSVL = { 2297, 1}, - .ADDHA = { 2298, 1}, - .ADDVA = { 2299, 1}, - .ZERO = { 2300, 1}, - .FMOPA = { 2301, 1}, - .FMOPS = { 2302, 1}, - .BFMOPA = { 2303, 1}, - .BFMOPS = { 2304, 1}, - .SMOPA = { 2305, 2}, - .SMOPS = { 2307, 2}, - .UMOPA = { 2309, 2}, - .UMOPS = { 2311, 2}, - .USMOPA = { 2313, 1}, - .SUMOPA = { 2314, 1}, - .CNTB = { 2315, 1}, - .CNTH = { 2316, 1}, - .CNTW = { 2317, 1}, - .CNTD = { 2318, 1}, - .INCB = { 2319, 1}, - .INCH = { 2320, 2}, - .INCW = { 2322, 2}, - .INCD = { 2324, 2}, - .DECB = { 2326, 1}, - .DECH = { 2327, 2}, - .DECW = { 2329, 2}, - .DECD = { 2331, 2}, - .SQINCB = { 2333, 2}, - .SQINCH = { 2335, 3}, - .SQINCW = { 2338, 3}, - .SQINCD = { 2341, 3}, - .SQDECB = { 2344, 2}, - .SQDECH = { 2346, 3}, - .SQDECW = { 2349, 3}, - .SQDECD = { 2352, 3}, - .UQINCB = { 2355, 2}, - .UQINCH = { 2357, 3}, - .UQINCW = { 2360, 3}, - .UQINCD = { 2363, 3}, - .UQDECB = { 2366, 2}, - .UQDECH = { 2368, 3}, - .UQDECW = { 2371, 3}, - .UQDECD = { 2374, 3}, - .CNTP = { 2377, 4}, - .INCP = { 2381, 7}, - .DECP = { 2388, 7}, - .SQINCP = { 2395, 11}, - .SQDECP = { 2406, 11}, - .UQINCP = { 2417, 11}, - .UQDECP = { 2428, 11}, - .LD1Q = { 2439, 1}, - .ST1Q = { 2440, 1}, - .MOVA = { 2441, 2}, - .FCMLA = { 2443, 4}, - .FCADD = { 2447, 4}, - .PRFB = { 2451, 1}, - .PRFH = { 2452, 1}, - .PRFW = { 2453, 1}, - .PRFD = { 2454, 1}, - .LDNT1B = { 2455, 1}, - .LDNT1H = { 2456, 1}, - .LDNT1W = { 2457, 1}, - .LDNT1D = { 2458, 1}, - .STNT1B = { 2459, 1}, - .STNT1H = { 2460, 1}, - .STNT1W = { 2461, 1}, - .STNT1D = { 2462, 1}, - .SPLICE = { 2463, 1}, - .INDEX = { 2464, 16}, - .BSL1N = { 2480, 1}, - .BSL2N = { 2481, 1}, - .NBSL = { 2482, 1}, - .PMUL = { 2483, 1}, - .PMULLB = { 2484, 1}, - .PMULLT = { 2485, 1}, - .BFCVTNT = { 2486, 1}, - .LDRAA = { 2487, 2}, - .LDRAB = { 2489, 2}, - .TSTART = { 2491, 1}, - .TCOMMIT = { 2492, 1}, - .TCANCEL = { 2493, 1}, - .TTEST = { 2494, 1}, - .WFET = { 2495, 1}, - .WFIT = { 2496, 1}, - .BC_EQ = { 2497, 1}, - .BC_NE = { 2498, 1}, - .BC_CS = { 2499, 1}, - .BC_CC = { 2500, 1}, - .BC_MI = { 2501, 1}, - .BC_PL = { 2502, 1}, - .BC_VS = { 2503, 1}, - .BC_VC = { 2504, 1}, - .BC_HI = { 2505, 1}, - .BC_LS = { 2506, 1}, - .BC_GE = { 2507, 1}, - .BC_LT = { 2508, 1}, - .BC_GT = { 2509, 1}, - .BC_LE = { 2510, 1}, - .BC_AL = { 2511, 1}, - .BC_NV = { 2512, 1}, - .UXTB = { 2513, 1}, - .UXTH = { 2514, 1}, - .UXTW = { 2515, 1}, - .SXTB = { 2516, 1}, - .SXTH = { 2517, 1}, - .SXTW = { 2518, 1}, - .ADC = { 2519, 2}, - .ADCS = { 2521, 2}, - .SBC = { 2523, 2}, - .SBCS = { 2525, 2}, - .NGC = { 2527, 2}, - .NGCS = { 2529, 2}, - .LDAPUR = { 2531, 2}, - .STLUR = { 2533, 2}, - .LDAPURB = { 2535, 1}, - .STLURB = { 2536, 1}, - .LDAPURH = { 2537, 1}, - .STLURH = { 2538, 1}, - .LDAPURSB = { 2539, 2}, - .LDAPURSH = { 2541, 2}, - .LDAPURSW = { 2543, 1}, - .BFADD = { 2544, 2}, - .BFSUB = { 2546, 2}, - .BFMUL = { 2548, 2}, - .BFMLA = { 2550, 1}, - .BFMLS = { 2551, 1}, - .SB = { 2552, 1}, - .CSDB = { 2553, 1}, - .DGH = { 2554, 1}, - .PSB_CSYNC = { 2555, 1}, - .TSB_CSYNC = { 2556, 1}, - .BTI_J = { 2557, 1}, - .BTI_C = { 2558, 1}, - .BTI_JC = { 2559, 1}, - .BFCLAMP = { 2560, 1}, - .BFMAXNM = { 2561, 1}, - .BFMINNM = { 2562, 1}, - .LUTI2 = { 2563, 3}, - .LUTI4 = { 2566, 3}, - .ZIP = { 2569, 2}, - .UZP = { 2571, 2}, - .TLBI_RPALOS = { 2573, 1}, - .TLBI_RPAOS = { 2574, 1}, - .AT_S1E1A = { 2575, 1}, - .DC_CIPAPA = { 2576, 1}, - .DC_CIGDPAPA = { 2577, 1}, - .TLBI_PAALL = { 2578, 1}, - .TLBI_PAALLOS = { 2579, 1}, - .AMX_LDX = { 2580, 1}, - .AMX_LDY = { 2581, 1}, - .AMX_STX = { 2582, 1}, - .AMX_STY = { 2583, 1}, - .AMX_LDZ = { 2584, 1}, - .AMX_STZ = { 2585, 1}, - .AMX_LDZI = { 2586, 1}, - .AMX_STZI = { 2587, 1}, - .AMX_EXTRX = { 2588, 1}, - .AMX_EXTRY = { 2589, 1}, - .AMX_FMA64 = { 2590, 1}, - .AMX_FMS64 = { 2591, 1}, - .AMX_FMA32 = { 2592, 1}, - .AMX_FMS32 = { 2593, 1}, - .AMX_MAC16 = { 2594, 1}, - .AMX_FMA16 = { 2595, 1}, - .AMX_FMS16 = { 2596, 1}, - .AMX_SET = { 2597, 1}, - .AMX_CLR = { 2598, 1}, - .AMX_VECINT = { 2599, 1}, - .AMX_VECFP = { 2600, 1}, - .AMX_MATINT = { 2601, 1}, - .AMX_MATFP = { 2602, 1}, - .AMX_GENLUT = { 2603, 1}, - .CPYP = { 2604, 1}, - .CPYM = { 2605, 1}, - .CPYE = { 2606, 1}, - .CPYFP = { 2607, 1}, - .CPYFM = { 2608, 1}, - .CPYFE = { 2609, 1}, - .SETP = { 2610, 1}, - .SETM = { 2611, 1}, - .SETE = { 2612, 1}, - .DC_IVAC = { 2613, 1}, - .DC_ISW = { 2614, 1}, - .DC_CSW = { 2615, 1}, - .DC_CISW = { 2616, 1}, - .DC_ZVA = { 2617, 1}, - .DC_CVAC = { 2618, 1}, - .DC_CVAU = { 2619, 1}, - .DC_CIVAC = { 2620, 1}, - .IC_IALLUIS = { 2621, 1}, - .IC_IALLU = { 2622, 1}, - .IC_IVAU = { 2623, 1}, - .AT_S1E1R = { 2624, 1}, - .AT_S1E1W = { 2625, 1}, - .AT_S1E0R = { 2626, 1}, - .AT_S1E0W = { 2627, 1}, - .AT_S1E2R = { 2628, 1}, - .AT_S1E2W = { 2629, 1}, - .AT_S1E3R = { 2630, 1}, - .AT_S1E3W = { 2631, 1}, - .AT_S12E1R = { 2632, 1}, - .AT_S12E1W = { 2633, 1}, - .AT_S12E0R = { 2634, 1}, - .AT_S12E0W = { 2635, 1}, - .TLBI_VMALLE1 = { 2636, 1}, - .TLBI_VMALLE1IS = { 2637, 1}, - .TLBI_VAE1 = { 2638, 1}, - .TLBI_VAE1IS = { 2639, 1}, - .TLBI_ASIDE1 = { 2640, 1}, - .TLBI_ASIDE1IS = { 2641, 1}, - .TLBI_VAAE1 = { 2642, 1}, - .TLBI_VAAE1IS = { 2643, 1}, - .TLBI_VALE1 = { 2644, 1}, - .TLBI_VALE1IS = { 2645, 1}, - .TLBI_VAALE1 = { 2646, 1}, - .TLBI_VAALE1IS = { 2647, 1}, - .TLBI_ALLE1 = { 2648, 1}, - .TLBI_ALLE1IS = { 2649, 1}, - .TLBI_ALLE2 = { 2650, 1}, - .TLBI_ALLE2IS = { 2651, 1}, - .TLBI_ALLE3 = { 2652, 1}, - .TLBI_ALLE3IS = { 2653, 1}, - .PRFM = { 2654, 2}, - .PRFUM = { 2656, 1}, - .NEGS = { 2657, 2}, - .CMP = { 2659, 6}, - .CMN = { 2665, 6}, + .XAR = { 1007, 5}, + .SM3PARTW1 = { 1012, 1}, + .SM3PARTW2 = { 1013, 1}, + .SM3SS1 = { 1014, 1}, + .SM3TT1A = { 1015, 1}, + .SM3TT1B = { 1016, 1}, + .SM3TT2A = { 1017, 1}, + .SM3TT2B = { 1018, 1}, + .SM4E = { 1019, 1}, + .SM4EKEY = { 1020, 1}, + .PMULL = { 1021, 2}, + .PMULL2 = { 1023, 2}, + .BFCVT = { 1025, 2}, + .BFDOT = { 1027, 1}, + .BFMMLA = { 1028, 1}, + .BFMLALB = { 1029, 1}, + .BFMLALT = { 1030, 1}, + .BFCVTN = { 1031, 1}, + .BFCVTN2 = { 1032, 1}, + .MUL = { 1033, 7}, + .MLA = { 1040, 6}, + .MLS = { 1046, 6}, + .NEG = { 1052, 13}, + .ABS = { 1065, 11}, + .SHADD = { 1076, 6}, + .UHADD = { 1082, 6}, + .SHSUB = { 1088, 6}, + .UHSUB = { 1094, 6}, + .SRHADD = { 1100, 6}, + .URHADD = { 1106, 6}, + .SQADD = { 1112, 11}, + .UQADD = { 1123, 11}, + .SQSUB = { 1134, 11}, + .UQSUB = { 1145, 11}, + .SMAX = { 1156, 10}, + .UMAX = { 1166, 10}, + .SMIN = { 1176, 10}, + .UMIN = { 1186, 10}, + .SABD = { 1196, 10}, + .UABD = { 1206, 10}, + .SABA = { 1216, 6}, + .UABA = { 1222, 6}, + .ADDP = { 1228, 7}, + .ADDV = { 1235, 5}, + .SADDLP = { 1240, 6}, + .UADDLP = { 1246, 6}, + .SADALP = { 1252, 6}, + .UADALP = { 1258, 6}, + .SADDLV = { 1264, 5}, + .UADDLV = { 1269, 5}, + .SMAXV = { 1274, 5}, + .UMAXV = { 1279, 5}, + .SMINV = { 1284, 5}, + .UMINV = { 1289, 5}, + .SMAXP = { 1294, 6}, + .UMAXP = { 1300, 6}, + .SMINP = { 1306, 6}, + .UMINP = { 1312, 6}, + .SADDL = { 1318, 3}, + .SADDL2 = { 1321, 3}, + .UADDL = { 1324, 3}, + .UADDL2 = { 1327, 3}, + .SSUBL = { 1330, 3}, + .SSUBL2 = { 1333, 3}, + .USUBL = { 1336, 3}, + .USUBL2 = { 1339, 3}, + .SADDW = { 1342, 3}, + .SADDW2 = { 1345, 3}, + .UADDW = { 1348, 3}, + .UADDW2 = { 1351, 3}, + .SSUBW = { 1354, 3}, + .SSUBW2 = { 1357, 3}, + .USUBW = { 1360, 3}, + .USUBW2 = { 1363, 3}, + .RADDHN = { 1366, 3}, + .RADDHN2 = { 1369, 3}, + .RSUBHN = { 1372, 3}, + .RSUBHN2 = { 1375, 3}, + .ADDHN = { 1378, 3}, + .ADDHN2 = { 1381, 3}, + .SUBHN = { 1384, 3}, + .SUBHN2 = { 1387, 3}, + .XTN = { 1390, 3}, + .XTN2 = { 1393, 3}, + .SQXTN = { 1396, 3}, + .SQXTN2 = { 1399, 3}, + .UQXTN = { 1402, 3}, + .UQXTN2 = { 1405, 3}, + .SQXTUN = { 1408, 3}, + .SQXTUN2 = { 1411, 3}, + .SMULL = { 1414, 3}, + .SMULL2 = { 1417, 3}, + .UMULL = { 1420, 3}, + .UMULL2 = { 1423, 3}, + .SMLAL = { 1426, 3}, + .SMLAL2 = { 1429, 3}, + .UMLAL = { 1432, 3}, + .UMLAL2 = { 1435, 3}, + .SMLSL = { 1438, 3}, + .SMLSL2 = { 1441, 3}, + .UMLSL = { 1444, 3}, + .UMLSL2 = { 1447, 3}, + .SQDMULL = { 1450, 2}, + .SQDMULL2 = { 1452, 2}, + .SQDMLAL = { 1454, 2}, + .SQDMLAL2 = { 1456, 2}, + .SQDMLSL = { 1458, 2}, + .SQDMLSL2 = { 1460, 2}, + .SQDMULH = { 1462, 4}, + .SQRDMULH = { 1466, 4}, + .SDOT = { 1470, 2}, + .UDOT = { 1472, 2}, + .USDOT = { 1474, 2}, + .FMLA = { 1476, 8}, + .FMLS = { 1484, 8}, + .FMULX = { 1492, 5}, + .FMAXP = { 1497, 5}, + .FMINP = { 1502, 5}, + .FMAXNMP = { 1507, 5}, + .FMINNMP = { 1512, 5}, + .FMAXV = { 1517, 3}, + .FMINV = { 1520, 3}, + .FMAXNMV = { 1523, 3}, + .FMINNMV = { 1526, 3}, + .FRECPE = { 1529, 5}, + .FRSQRTE = { 1534, 5}, + .FRECPS = { 1539, 8}, + .FRSQRTS = { 1547, 8}, + .FRECPX = { 1555, 6}, + .FADDP = { 1561, 5}, + .FCVTL = { 1566, 2}, + .FCVTL2 = { 1568, 2}, + .FCVTN = { 1570, 2}, + .FCVTN2 = { 1572, 2}, + .FCVTXN = { 1574, 1}, + .FCVTXN2 = { 1575, 1}, + .FCMEQ = { 1576, 8}, + .FCMGE = { 1584, 8}, + .FCMGT = { 1592, 8}, + .FCMLE = { 1600, 8}, + .FCMLT = { 1608, 8}, + .FACGE = { 1616, 5}, + .FACGT = { 1621, 5}, + .CMEQ = { 1626, 4}, + .CMGE = { 1630, 7}, + .CMGT = { 1637, 2}, + .CMHI = { 1639, 2}, + .CMHS = { 1641, 7}, + .CMLE = { 1648, 7}, + .CMLT = { 1655, 7}, + .CMTST = { 1662, 7}, + .MVN = { 1669, 4}, + .BIT = { 1673, 1}, + .BIF = { 1674, 1}, + .BSL = { 1675, 2}, + .SHL = { 1677, 7}, + .SQSHL = { 1684, 7}, + .SQSHLU = { 1691, 7}, + .SRSHL = { 1698, 7}, + .URSHL = { 1705, 7}, + .SSHR = { 1712, 7}, + .USHR = { 1719, 7}, + .SSRA = { 1726, 7}, + .USRA = { 1733, 7}, + .SRSHR = { 1740, 7}, + .URSHR = { 1747, 7}, + .SRSRA = { 1754, 7}, + .URSRA = { 1761, 7}, + .SSHL = { 1768, 7}, + .USHL = { 1775, 7}, + .SLI = { 1782, 7}, + .SRI = { 1789, 7}, + .SSHLL = { 1796, 3}, + .SSHLL2 = { 1799, 3}, + .USHLL = { 1802, 3}, + .USHLL2 = { 1805, 3}, + .SXTL = { 1808, 3}, + .SXTL2 = { 1811, 3}, + .UXTL = { 1814, 3}, + .UXTL2 = { 1817, 3}, + .SHRN = { 1820, 3}, + .SHRN2 = { 1823, 3}, + .RSHRN = { 1826, 3}, + .RSHRN2 = { 1829, 3}, + .SQSHRN = { 1832, 3}, + .SQSHRN2 = { 1835, 3}, + .UQSHRN = { 1838, 3}, + .UQSHRN2 = { 1841, 3}, + .SQRSHRN = { 1844, 3}, + .SQRSHRN2 = { 1847, 3}, + .UQRSHRN = { 1850, 3}, + .UQRSHRN2 = { 1853, 3}, + .SQSHRUN = { 1856, 3}, + .SQSHRUN2 = { 1859, 3}, + .SQRSHRUN = { 1862, 3}, + .SQRSHRUN2 = { 1865, 3}, + .DUP = { 1868, 18}, + .INS = { 1886, 8}, + .MOV = { 1894, 12}, + .EXT = { 1906, 4}, + .TBL = { 1910, 7}, + .TBX = { 1917, 3}, + .ZIP1 = { 1920, 12}, + .ZIP2 = { 1932, 12}, + .UZP1 = { 1944, 12}, + .UZP2 = { 1956, 12}, + .TRN1 = { 1968, 12}, + .TRN2 = { 1980, 12}, + .NOT = { 1992, 3}, + .REV64 = { 1995, 6}, + .CNT = { 2001, 6}, + .URECPE = { 2007, 2}, + .URSQRTE = { 2009, 2}, + .MOVI = { 2011, 7}, + .MVNI = { 2018, 4}, + .LD1 = { 2022, 8}, + .LD2 = { 2030, 5}, + .LD3 = { 2035, 5}, + .LD4 = { 2040, 5}, + .ST1 = { 2045, 8}, + .ST2 = { 2053, 5}, + .ST3 = { 2058, 5}, + .ST4 = { 2063, 5}, + .LD1R = { 2068, 1}, + .LD2R = { 2069, 1}, + .LD3R = { 2070, 1}, + .LD4R = { 2071, 1}, + .SUBR = { 2072, 4}, + .ASRR = { 2076, 4}, + .LSLR = { 2080, 4}, + .LSRR = { 2084, 4}, + .FTSMUL = { 2088, 3}, + .FSUBR = { 2091, 3}, + .FDIVR = { 2094, 3}, + .FNMLA = { 2097, 3}, + .FNMLS = { 2100, 3}, + .NAND = { 2103, 1}, + .NOR = { 2104, 1}, + .SEL = { 2105, 1}, + .ORRS = { 2106, 1}, + .EORS = { 2107, 1}, + .NANDS = { 2108, 1}, + .NORS = { 2109, 1}, + .ORNS = { 2110, 1}, + .MOVS = { 2111, 1}, + .PTRUE = { 2112, 1}, + .PTRUES = { 2113, 1}, + .PFALSE = { 2114, 1}, + .PFIRST = { 2115, 1}, + .PNEXT = { 2116, 1}, + .BRKA = { 2117, 1}, + .BRKB = { 2118, 1}, + .BRKAS = { 2119, 1}, + .BRKBS = { 2120, 1}, + .BRKPA = { 2121, 1}, + .BRKPB = { 2122, 1}, + .BRKN = { 2123, 1}, + .RDFFR = { 2124, 1}, + .WRFFR = { 2125, 1}, + .SETFFR = { 2126, 1}, + .CMPEQ = { 2127, 4}, + .CMPNE = { 2131, 4}, + .CMPGE = { 2135, 4}, + .CMPGT = { 2139, 4}, + .CMPLE = { 2143, 4}, + .CMPLT = { 2147, 4}, + .CMPHI = { 2151, 4}, + .CMPHS = { 2155, 4}, + .CMPLO = { 2159, 4}, + .CMPLS = { 2163, 4}, + .FCMNE = { 2167, 3}, + .FCMUO = { 2170, 3}, + .INSR = { 2173, 4}, + .CPY = { 2177, 4}, + .COMPACT = { 2181, 2}, + .LD1B = { 2183, 6}, + .LD1H = { 2189, 6}, + .LD1W = { 2195, 6}, + .LD1D = { 2201, 5}, + .LD1SB = { 2206, 3}, + .LD1SH = { 2209, 4}, + .LD1SW = { 2213, 2}, + .ST1B = { 2215, 6}, + .ST1H = { 2221, 7}, + .ST1W = { 2228, 6}, + .ST1D = { 2234, 5}, + .LDFF1B = { 2239, 1}, + .LDFF1H = { 2240, 1}, + .LDFF1W = { 2241, 1}, + .LDFF1D = { 2242, 1}, + .WHILEGE = { 2243, 4}, + .WHILEGT = { 2247, 4}, + .WHILELE = { 2251, 4}, + .WHILELT = { 2255, 4}, + .WHILEHI = { 2259, 4}, + .WHILEHS = { 2263, 4}, + .WHILELO = { 2267, 4}, + .WHILELS = { 2271, 4}, + .SQRDMLAH = { 2275, 4}, + .SQRDMLSH = { 2279, 4}, + .ADCLB = { 2283, 2}, + .ADCLT = { 2285, 2}, + .SBCLB = { 2287, 2}, + .SBCLT = { 2289, 2}, + .MATCH = { 2291, 2}, + .NMATCH = { 2293, 2}, + .HISTCNT = { 2295, 2}, + .HISTSEG = { 2297, 1}, + .SMSTART = { 2298, 1}, + .SMSTOP = { 2299, 1}, + .RDSVL = { 2300, 1}, + .ADDHA = { 2301, 1}, + .ADDVA = { 2302, 1}, + .ZERO = { 2303, 1}, + .FMOPA = { 2304, 1}, + .FMOPS = { 2305, 1}, + .BFMOPA = { 2306, 1}, + .BFMOPS = { 2307, 1}, + .SMOPA = { 2308, 2}, + .SMOPS = { 2310, 2}, + .UMOPA = { 2312, 2}, + .UMOPS = { 2314, 2}, + .USMOPA = { 2316, 1}, + .SUMOPA = { 2317, 1}, + .CNTB = { 2318, 1}, + .CNTH = { 2319, 1}, + .CNTW = { 2320, 1}, + .CNTD = { 2321, 1}, + .INCB = { 2322, 1}, + .INCH = { 2323, 2}, + .INCW = { 2325, 2}, + .INCD = { 2327, 2}, + .DECB = { 2329, 1}, + .DECH = { 2330, 2}, + .DECW = { 2332, 2}, + .DECD = { 2334, 2}, + .SQINCB = { 2336, 2}, + .SQINCH = { 2338, 3}, + .SQINCW = { 2341, 3}, + .SQINCD = { 2344, 3}, + .SQDECB = { 2347, 2}, + .SQDECH = { 2349, 3}, + .SQDECW = { 2352, 3}, + .SQDECD = { 2355, 3}, + .UQINCB = { 2358, 2}, + .UQINCH = { 2360, 3}, + .UQINCW = { 2363, 3}, + .UQINCD = { 2366, 3}, + .UQDECB = { 2369, 2}, + .UQDECH = { 2371, 3}, + .UQDECW = { 2374, 3}, + .UQDECD = { 2377, 3}, + .CNTP = { 2380, 4}, + .INCP = { 2384, 7}, + .DECP = { 2391, 7}, + .SQINCP = { 2398, 11}, + .SQDECP = { 2409, 11}, + .UQINCP = { 2420, 11}, + .UQDECP = { 2431, 11}, + .LD1Q = { 2442, 1}, + .ST1Q = { 2443, 1}, + .MOVA = { 2444, 2}, + .FCMLA = { 2446, 4}, + .FCADD = { 2450, 4}, + .PRFB = { 2454, 1}, + .PRFH = { 2455, 1}, + .PRFW = { 2456, 1}, + .PRFD = { 2457, 1}, + .LDNT1B = { 2458, 1}, + .LDNT1H = { 2459, 1}, + .LDNT1W = { 2460, 1}, + .LDNT1D = { 2461, 1}, + .STNT1B = { 2462, 1}, + .STNT1H = { 2463, 1}, + .STNT1W = { 2464, 1}, + .STNT1D = { 2465, 1}, + .SPLICE = { 2466, 1}, + .INDEX = { 2467, 16}, + .BSL1N = { 2483, 1}, + .BSL2N = { 2484, 1}, + .NBSL = { 2485, 1}, + .PMUL = { 2486, 1}, + .PMULLB = { 2487, 1}, + .PMULLT = { 2488, 1}, + .BFCVTNT = { 2489, 1}, + .LDRAA = { 2490, 2}, + .LDRAB = { 2492, 2}, + .TSTART = { 2494, 1}, + .TCOMMIT = { 2495, 1}, + .TCANCEL = { 2496, 1}, + .TTEST = { 2497, 1}, + .WFET = { 2498, 1}, + .WFIT = { 2499, 1}, + .BC_EQ = { 2500, 1}, + .BC_NE = { 2501, 1}, + .BC_CS = { 2502, 1}, + .BC_CC = { 2503, 1}, + .BC_MI = { 2504, 1}, + .BC_PL = { 2505, 1}, + .BC_VS = { 2506, 1}, + .BC_VC = { 2507, 1}, + .BC_HI = { 2508, 1}, + .BC_LS = { 2509, 1}, + .BC_GE = { 2510, 1}, + .BC_LT = { 2511, 1}, + .BC_GT = { 2512, 1}, + .BC_LE = { 2513, 1}, + .BC_AL = { 2514, 1}, + .BC_NV = { 2515, 1}, + .UXTB = { 2516, 1}, + .UXTH = { 2517, 1}, + .UXTW = { 2518, 1}, + .SXTB = { 2519, 1}, + .SXTH = { 2520, 1}, + .SXTW = { 2521, 1}, + .ADC = { 2522, 2}, + .ADCS = { 2524, 2}, + .SBC = { 2526, 2}, + .SBCS = { 2528, 2}, + .NGC = { 2530, 2}, + .NGCS = { 2532, 2}, + .LDAPUR = { 2534, 2}, + .STLUR = { 2536, 2}, + .LDAPURB = { 2538, 1}, + .STLURB = { 2539, 1}, + .LDAPURH = { 2540, 1}, + .STLURH = { 2541, 1}, + .LDAPURSB = { 2542, 2}, + .LDAPURSH = { 2544, 2}, + .LDAPURSW = { 2546, 1}, + .BFADD = { 2547, 2}, + .BFSUB = { 2549, 2}, + .BFMUL = { 2551, 2}, + .BFMLA = { 2553, 1}, + .BFMLS = { 2554, 1}, + .SB = { 2555, 1}, + .CSDB = { 2556, 1}, + .DGH = { 2557, 1}, + .PSB_CSYNC = { 2558, 1}, + .TSB_CSYNC = { 2559, 1}, + .BTI_J = { 2560, 1}, + .BTI_C = { 2561, 1}, + .BTI_JC = { 2562, 1}, + .BFCLAMP = { 2563, 1}, + .BFMAXNM = { 2564, 1}, + .BFMINNM = { 2565, 1}, + .LUTI2 = { 2566, 3}, + .LUTI4 = { 2569, 3}, + .ZIP = { 2572, 2}, + .UZP = { 2574, 2}, + .TLBI_RPALOS = { 2576, 1}, + .TLBI_RPAOS = { 2577, 1}, + .AT_S1E1A = { 2578, 1}, + .DC_CIPAPA = { 2579, 1}, + .DC_CIGDPAPA = { 2580, 1}, + .TLBI_PAALL = { 2581, 1}, + .TLBI_PAALLOS = { 2582, 1}, + .AMX_LDX = { 2583, 1}, + .AMX_LDY = { 2584, 1}, + .AMX_STX = { 2585, 1}, + .AMX_STY = { 2586, 1}, + .AMX_LDZ = { 2587, 1}, + .AMX_STZ = { 2588, 1}, + .AMX_LDZI = { 2589, 1}, + .AMX_STZI = { 2590, 1}, + .AMX_EXTRX = { 2591, 1}, + .AMX_EXTRY = { 2592, 1}, + .AMX_FMA64 = { 2593, 1}, + .AMX_FMS64 = { 2594, 1}, + .AMX_FMA32 = { 2595, 1}, + .AMX_FMS32 = { 2596, 1}, + .AMX_MAC16 = { 2597, 1}, + .AMX_FMA16 = { 2598, 1}, + .AMX_FMS16 = { 2599, 1}, + .AMX_SET = { 2600, 1}, + .AMX_CLR = { 2601, 1}, + .AMX_VECINT = { 2602, 1}, + .AMX_VECFP = { 2603, 1}, + .AMX_MATINT = { 2604, 1}, + .AMX_MATFP = { 2605, 1}, + .AMX_GENLUT = { 2606, 1}, + .CPYP = { 2607, 1}, + .CPYM = { 2608, 1}, + .CPYE = { 2609, 1}, + .CPYFP = { 2610, 1}, + .CPYFM = { 2611, 1}, + .CPYFE = { 2612, 1}, + .SETP = { 2613, 1}, + .SETM = { 2614, 1}, + .SETE = { 2615, 1}, + .DC_IVAC = { 2616, 1}, + .DC_ISW = { 2617, 1}, + .DC_CSW = { 2618, 1}, + .DC_CISW = { 2619, 1}, + .DC_ZVA = { 2620, 1}, + .DC_CVAC = { 2621, 1}, + .DC_CVAU = { 2622, 1}, + .DC_CIVAC = { 2623, 1}, + .IC_IALLUIS = { 2624, 1}, + .IC_IALLU = { 2625, 1}, + .IC_IVAU = { 2626, 1}, + .AT_S1E1R = { 2627, 1}, + .AT_S1E1W = { 2628, 1}, + .AT_S1E0R = { 2629, 1}, + .AT_S1E0W = { 2630, 1}, + .AT_S1E2R = { 2631, 1}, + .AT_S1E2W = { 2632, 1}, + .AT_S1E3R = { 2633, 1}, + .AT_S1E3W = { 2634, 1}, + .AT_S12E1R = { 2635, 1}, + .AT_S12E1W = { 2636, 1}, + .AT_S12E0R = { 2637, 1}, + .AT_S12E0W = { 2638, 1}, + .TLBI_VMALLE1 = { 2639, 1}, + .TLBI_VMALLE1IS = { 2640, 1}, + .TLBI_VAE1 = { 2641, 1}, + .TLBI_VAE1IS = { 2642, 1}, + .TLBI_ASIDE1 = { 2643, 1}, + .TLBI_ASIDE1IS = { 2644, 1}, + .TLBI_VAAE1 = { 2645, 1}, + .TLBI_VAAE1IS = { 2646, 1}, + .TLBI_VALE1 = { 2647, 1}, + .TLBI_VALE1IS = { 2648, 1}, + .TLBI_VAALE1 = { 2649, 1}, + .TLBI_VAALE1IS = { 2650, 1}, + .TLBI_ALLE1 = { 2651, 1}, + .TLBI_ALLE1IS = { 2652, 1}, + .TLBI_ALLE2 = { 2653, 1}, + .TLBI_ALLE2IS = { 2654, 1}, + .TLBI_ALLE3 = { 2655, 1}, + .TLBI_ALLE3IS = { 2656, 1}, + .PRFM = { 2657, 2}, + .PRFUM = { 2659, 1}, + .NEGS = { 2660, 2}, + .CMP = { 2662, 6}, + .CMN = { 2668, 6}, } diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 7a1c27281..d88b97811 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -1749,7 +1749,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .XAR = { {{.XAR, {.V_2D, .V_2D, .V_2D, .IMM_6, .NONE}, {.VD, .VN, .VM, .IMM6, .NONE}, 0xCE800000, 0xFFE00000, .CRYPTO, {}}, Clobber{written={0}, read={1, 2}}}, - {{.XAR, {.Z_REG_ANY, .Z_REG_ANY, .Z_REG_ANY, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04203400, 0xFF20FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_D, .Z_REG_D, .Z_REG_D, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04A03400, 0xFFA0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_S, .Z_REG_S, .Z_REG_S, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04603400, 0xFFE0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_H, .Z_REG_H, .Z_REG_H, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04303400, 0xFFF0FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, + {{.XAR, {.Z_REG_B, .Z_REG_B, .Z_REG_B, .VEC_SHIFT, .NONE}, {.VD_TSZ, .VD_TSZ, .VN_TSZ, .SVE_XAR_SHIFT, .NONE}, 0x04283400, 0xFFF8FC00, .SVE2, {}}, Clobber{written={0}, read={1, 2}}}, }, .SM3PARTW1 = { {{.SM3PARTW1, {.V_4S, .V_4S, .V_4S, .NONE, .NONE}, {.VD, .VN, .VM, .NONE, .NONE}, 0xCE60C000, 0xFFE0FC00, .CRYPTO, {}}, Clobber{written={0}, read={0, 1, 2}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin b/core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin index 5c167e088432ba476ef3bee12a67ea75026d6194..a9bdf5709ea398d8aa97bcc1cc2deac206bb6ca3 100644 GIT binary patch delta 17 ZcmbQVglW$brVaY$6YI4$>zhB00sulM2SES; delta 33 pcmdn9glW3$OqH diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 6a25c6860a5e8b71c17d1a162a3460b7ab4d5671..dcca7270f41177b96682ec02461e0484efcd12f2 100644 GIT binary patch delta 98 zcmeA=&3xuG^M*xX!3qirISf@*)vgQ-CJR^?{w(;<*I>^mFE0-lO#q5M0E^1W$-zYp YfTAD3qO!8Ga8V7Q=#R~t!>;!M09BG8^Z)<= delta 32 ocmX?enz`#V^M*xXf?;7{ISf@*)vgQ-CJHPJe-t)<4ZGe40MWM$r2qf` diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_runs.bin 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zSeX0!aX!gKe2R;?B#fmjEaP(ZE4Y%Y!u-ComYc#j3S0OgKjU`p40FAAaX0sJe;7yM zC+6nK>m0#qVeY3o@sa1%3-kUOupy7(v0*;P$FXskA;iN zk)3!lJF^QyF9 zdAo)a)Zf5KVXpfvVeW_Nyq))ixt{aF9A|!*`8^b7zlX!@_e2<5ps-lHEX;l{hPfUq z_!3w0G`f8rq?=Fj|v z`Nx19uSA&nlwui{WBD-8tH6q^#LBF~s;m~~xHVXdb+p$N7qK22uwj_%*@%tVRC{xA zOP=R%`15wr-V6AQ#mcn`=1f!c(Zty z_PaTo_izs9@?PG@dAy$wa6T7sVVHkkds@7h&u|Hs@>xE|Wnt$30+*|Qkt_HTSMp`9 z;wxOuSNR%W=NnwZwS1FraUIul1K;LGZsI$9mz((>xA6Ti?{_Od`rYC^+{gXe5Aa7GWHEo@As*(>{Dt`?=GW()C0Q!W=d3KthnZ(Z zRt~dY6;@?6R%Z>?WG&Wa9oFTMEaGoikM-GrN3kJ~<}qxI$lH4}%4>5knTU1;Zj{C6*)X0t{E!l^DLUH!)Ojh%)qYEN3v` PtYTQlDa>$?a{~haQgjS@ From b1fb9be5c9882eb1fdc38dbe3d1d3127390cf70d Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 19:58:06 -0400 Subject: [PATCH 55/89] rexcode/arm32: the halfword and dual load/stores, checked against llvm-mc arm32 had only ever been checked against itself. Its sweep round-trips our own encode and decode, which agree with each other whether or not either is right -- exactly how the arm64 bugs stayed hidden for months. Decoding each entry and handing the text to llvm-mc says something different: 683 of 1139 A32 entries byte-exact, 166 wrong, 290 that no assembler would take. Three real faults out of that first pass: - The halfword and dual load/stores split their 8-bit offset around the opcode at bits 7:4, and their pre/post-indexed forms were using the 12-bit decoder. It swallowed the opcode nibble, so `strht r0, [r0]` came back as `[r0], #-176` -- 0xb0 being the halfword opcode read as an offset. 16 forms. - LDRD and STRD name a register pair and we printed one half of it. The second is always the first plus one and occupies no bits, so it needed an encoding that reads Rt and adds one. - An indexed form printed no displacement when it was zero, which turns `[r0], #0` into `[r0]` -- a different instruction, since the writeback is the whole point of the form. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 12 ++++++ core/rexcode/isa/arm32/encoder.odin | 4 +- core/rexcode/isa/arm32/encoding_types.odin | 7 +++ core/rexcode/isa/arm32/mnemonic_builders.odin | 16 +++---- core/rexcode/isa/arm32/printer.odin | 16 ++++--- .../isa/arm32/tablegen/encoding_table.odin | 40 +++++++++--------- .../tablegen/generated/decode_tables.odin | 40 +++++++++--------- .../tablegen/generated/encode_tables.odin | 40 +++++++++--------- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes 10 files changed, 98 insertions(+), 77 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 255009b26..ef8b1e7dc 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -560,6 +560,18 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op // PRE_INDEX and POST_INDEX wrap MEM_IMM12_OFFSET: same field layout but the // addressing mode flag is set differently. We reconstruct the full Memory // operand here (base, disp, sign, mode). + case .RT2_A32_PAIR: + return op_reg(Register(REG_GPR | u16(((word >> 12) + 1) & 0xF))) + case .MEM_IMM8_PRE_INDEX: + base := Register(REG_GPR | u16((word >> 16) & 0xF)) + disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) + if (word >> 23) & 1 == 0 { disp = -disp } + return op_mem(mem_imm_pre(base, disp)) + case .MEM_IMM8_POST_INDEX: + base := Register(REG_GPR | u16((word >> 16) & 0xF)) + disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) + if (word >> 23) & 1 == 0 { disp = -disp } + return op_mem(mem_imm_post(base, disp)) case .MEM_PRE_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 71735a8dd..7243cf6aa 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -519,7 +519,9 @@ pack_operand_inline :: #force_inline proc( u_bit: u32 = m.disp >= 0 ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp - case .MEM_IMM8_OFFSET: + case .RT2_A32_PAIR: + return 0 + case .MEM_IMM8_PRE_INDEX, .MEM_IMM8_POST_INDEX, .MEM_IMM8_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 u_bit: u32 = m.disp >= 0 ? 1 : 0 diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index b977fe734..d600b6a88 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -352,6 +352,13 @@ Operand_Encoding :: enum u8 { // ---- Memory addressing composites ---- MEM_IMM12_OFFSET, // [Rn, #ยฑimm12] + // The halfword and dual load/stores split their 8-bit offset around the + // opcode at bits 7:4, so they cannot use the 12-bit forms below. + // LDRD/STRD name a register pair, and the second is always the first plus + // one, so it occupies no bits of its own. + RT2_A32_PAIR, + MEM_IMM8_PRE_INDEX, + MEM_IMM8_POST_INDEX, MEM_IMM8_OFFSET, // [Rn, #ยฑimm8] (LDRH/STRH/LDRSB/STRD) MEM_REG_OFFSET, // [Rn, ยฑRm{, shift}] MEM_PRE_INDEX, // [Rn, #imm]! / [Rn, ยฑRm]! diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index c8db616d1..9e53fb4ac 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -528,13 +528,9 @@ inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, s emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) } inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) } -inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) } +inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) } -inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) } +inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) } inst_ldrt_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } emit_ldrt_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrt_r_mem(dst, src)) } @@ -1807,10 +1803,10 @@ inst_ldrsb :: inst_ldrsb_r_mem emit_ldrsb :: emit_ldrsb_r_mem inst_ldrsh :: inst_ldrsh_r_mem emit_ldrsh :: emit_ldrsh_r_mem -inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem } -emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem } -inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem } -emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem } +inst_ldrd :: inst_ldrd_r_r_mem +emit_ldrd :: emit_ldrd_r_r_mem +inst_strd :: inst_strd_r_r_mem +emit_strd :: emit_strd_r_r_mem inst_ldrt :: inst_ldrt_r_mem emit_ldrt :: emit_ldrt_r_mem inst_strt :: inst_strt_r_mem diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 492e813ce..dd21c4e68 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -592,15 +592,19 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory) { if m.sign < 0 { strings.write_string(sb, "-") } write_register(sb, m.index) } - } else if m.disp != 0 { - // Immediate offset + } else { + // An indexed form writes its displacement even when it is zero: the + // writeback is the point, and `[r0]` alone is the plain offset form. switch m.mode { - case .OFFSET: fmt.sbprintf(sb, ", #%d]", m.disp) - case .PRE_INDEX: fmt.sbprintf(sb, ", #%d]!", m.disp) + case .OFFSET: + if m.disp != 0 { + fmt.sbprintf(sb, ", #%d]", m.disp) + } else { + strings.write_string(sb, "]") + } + case .PRE_INDEX: fmt.sbprintf(sb, ", #%d]!", m.disp) case .POST_INDEX: fmt.sbprintf(sb, "], #%d", m.disp) } - } else { - strings.write_string(sb, "]") } } diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 70ad7ed67..56a3f0579 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1043,8 +1043,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .LDRH = { // LDRH imm offset (P=1 W=0): cond 000 1 U 1 0 1 Rn Rt imm4H 1011 imm4L {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_PRE_INDEX, .NONE, .NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, // LDRH reg offset: cond 000 1 U 0 0 1 Rn Rt 0000 1011 Rm {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRH reg-offset: 0101 101 Rm Rb Rd @@ -1057,8 +1057,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .STRH = { {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_PRE_INDEX, .NONE, .NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 STRH reg-offset: 0101 001 Rm Rb Rd {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, @@ -1070,8 +1070,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .LDRSB = { {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_PRE_INDEX, .NONE, .NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSB reg-offset: 0101 011 Rm Rb Rd {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, @@ -1081,8 +1081,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .LDRSH = { {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_PRE_INDEX, .NONE, .NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSH reg-offset: 0101 111 Rm Rb Rd {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, @@ -1092,18 +1092,18 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .LDRD = { // LDRD imm offset (ARMv5TE+): cond 000 P U 1 W 0 Rn Rt imm4H 1101 imm4L - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_OFFSET, .NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_PRE_INDEX, .NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_POST_INDEX, .NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_REG_OFFSET, .NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 LDRD imm8: high=11101001 X101 Rn low=Rt Rt2 imm8 {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRD = { - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_OFFSET, .NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_PRE_INDEX, .NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_IMM8_POST_INDEX, .NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_A32, .RT2_A32_PAIR, .MEM_REG_OFFSET, .NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 STRD imm8: high=11101001 X100 Rn low=Rt Rt2 imm8 {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, @@ -3521,10 +3521,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {}} }, .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {}} }, .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {}} }, - .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, - .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_POST_INDEX, .NONE, .NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, // NEON rounding shift-right-accumulate (imm); FP reciprocal/rsqrt estimate; // FP pairwise add; VFP convert-to-integer using the FPSCR rounding mode. diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 11bf858cc..779676d58 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -22,23 +22,23 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_POST_INDEX,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_POST_INDEX,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {.NONE,.NONE} }, - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -73,8 +73,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_REG_OFFSET,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_REG_OFFSET,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, @@ -110,8 +110,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_OFFSET,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_OFFSET,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -125,14 +125,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_PRE_INDEX,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_PRE_INDEX,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 1fed899bc..66dc5bdfc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -686,8 +686,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRH { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, @@ -695,8 +695,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .LDRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRH { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x016000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x004000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000B0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, @@ -704,31 +704,31 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .STRH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRSB { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000D0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRSB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRSH { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x015000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_PRE_INDEX,.NONE,.NONE}, 0x017000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x005000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x011000F0, 0x0F700FF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRSH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRSH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRD - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .LDRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_OFFSET,.NONE}, 0x014000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_PRE_INDEX,.NONE}, 0x016000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_POST_INDEX,.NONE}, 0x004000D0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_REG_OFFSET,.NONE}, 0x010000D0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRD - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, - { .STRD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_OFFSET,.NONE}, 0x014000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_PRE_INDEX,.NONE}, 0x016000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_IMM8_POST_INDEX,.NONE}, 0x004000F0, 0x0F7000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_A32,.RT2_A32_PAIR,.MEM_REG_OFFSET,.NONE}, 0x010000F0, 0x0F700FF0, .V5TE, .A32, {}, {.NONE,.NONE} }, { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRT { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -739,13 +739,13 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .STRBT { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRHT - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x007000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRHT - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x006000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSBT - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM8_POST_INDEX,.NONE,.NONE}, 0x007000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSHT - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x007000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, 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words and whichever sorted first answered for the lot. That is where the NEON element sizes went: `vabs.s8`, `.s16` and `.s32` are three patterns differing at bits 19:18, and with those bits outside the mask the first one spoke for all three. 121 rows. Two things that exposed: - LDM and STM differ only in the writeback bit, and nothing in the operand model recorded it, so the two forms printed identically. Instruction carries it now and the base register wears its `!`. - The T32 shifts left the S bit free, and their patterns sort ahead of MOV's, so `movs.w r1, r2` came back as `lsl r1, r2, #0`. There is no LSLS form in the table for it to have become instead; pinning the bit at least stops it answering for a word that is not its own. Also: r0 could not be used as an index register. The printer took a register-offset operand to be immediate-only unless the index was non-zero, when the class alone already says whether there is one -- `[r0, -r0]` printed as `[r0]`. And a displacement of zero lost its U bit, which llvm-mc writes as `#-0` because it is a different word. Against llvm-mc, A32 entries whose disassembly assembles back to the same word: 760 of 1139, from 683. Wrong: 81, from 158. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 36 +- core/rexcode/isa/arm32/encoder.odin | 22 +- core/rexcode/isa/arm32/instructions.odin | 5 +- core/rexcode/isa/arm32/printer.odin | 19 +- .../isa/arm32/tablegen/encoding_table.odin | 258 +-- .../tablegen/generated/decode_tables.odin | 1836 ++++++++--------- .../tablegen/generated/encode_tables.odin | 258 +-- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10718 -> 10670 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3298 -> 3298 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 38 +- 16 files changed, 1260 insertions(+), 1212 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index ef8b1e7dc..633ad28e6 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -165,6 +165,14 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in if e.flags.sets_flags { inst.sets_flags = true } + // LDM/STM carry the writeback in bit 21; nothing else in the operand + // model records it, and without it the two forms print identically. + for k in 0 ..< len(e.enc) { + if e.enc[k] == .A32_REG_LIST { + inst.writeback = (word >> 21) & 1 != 0 + break + } + } for _, k in e.enc { if e.enc[k] == .NONE { continue } @@ -379,13 +387,17 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm(base, disp)) + mm := mem_imm(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_IMM8_OFFSET: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm(base, disp)) + mm := mem_imm(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_REG_OFFSET: base := Register(REG_GPR | u16((word >> 16) & 0xF)) idx := Register(REG_GPR | u16(word & 0xF)) @@ -566,24 +578,36 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op base := Register(REG_GPR | u16((word >> 16) & 0xF)) disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if (word >> 23) & 1 == 0 { disp = -disp } - return op_mem(mem_imm_pre(base, disp)) + mm := mem_imm_pre(base, disp) + + if (word >> 23) & 1 == 0 { mm.sign = -1 } + + return op_mem(mm) case .MEM_IMM8_POST_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) disp := i32(((word >> 8) & 0xF) << 4 | (word & 0xF)) if (word >> 23) & 1 == 0 { disp = -disp } - return op_mem(mem_imm_post(base, disp)) + mm := mem_imm_post(base, disp) + + if (word >> 23) & 1 == 0 { mm.sign = -1 } + + return op_mem(mm) case .MEM_PRE_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm_pre(base, disp)) + mm := mem_imm_pre(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_POST_INDEX: base := Register(REG_GPR | u16((word >> 16) & 0xF)) u_bit := (word >> 23) & 1 disp := i32(word & 0xFFF) if u_bit == 0 { disp = -disp } - return op_mem(mem_imm_post(base, disp)) + mm := mem_imm_post(base, disp) + if u_bit == 0 { mm.sign = -1 } + return op_mem(mm) case .MEM_LITERAL: // PC-relative literal load: U bit + 12-bit signed disp u_bit := (word >> 23) & 1 diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 7243cf6aa..d5b8a68b1 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -164,6 +164,7 @@ encode_one_inline :: #force_inline proc( (want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) && encoding_matches_inline(inst, f) && inst.sets_flags == f.flags.sets_flags && + writeback_matches(inst, f) && mem_mode_matches(inst, f) { form = f } @@ -180,6 +181,7 @@ encode_one_inline :: #force_inline proc( if !encoding_matches_inline(inst, &f) { continue } if inst.sets_flags && !f.flags.sets_flags { continue } if !inst.sets_flags && f.flags.sets_flags { continue } + if !writeback_matches(inst, &f) { continue } if !mem_mode_matches(inst, &f) { continue } form = &f break @@ -516,7 +518,7 @@ pack_operand_inline :: #force_inline proc( case .MEM_IMM12_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .RT2_A32_PAIR: @@ -524,7 +526,7 @@ pack_operand_inline :: #force_inline proc( case .MEM_IMM8_PRE_INDEX, .MEM_IMM8_POST_INDEX, .MEM_IMM8_OFFSET: m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFF return base | (u_bit << 23) | ((disp >> 4) & 0xF) << 8 | (disp & 0xF) case .MEM_REG_OFFSET: @@ -538,14 +540,14 @@ pack_operand_inline :: #force_inline proc( // P=1, W=1 in bits 24/21 to select pre-index addressing mode. m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .MEM_POST_INDEX: // Same layout as MEM_IMM12_OFFSET; form bits select P=0 in bit 24. m := op.mem base := (u32(reg_hw(m.base)) & 0xF) << 16 - u_bit: u32 = m.disp >= 0 ? 1 : 0 + u_bit: u32 = (m.disp > 0 || (m.disp == 0 && m.sign >= 0)) ? 1 : 0 disp := u32(abs_i32(m.disp)) & 0xFFF return base | (u_bit << 23) | disp case .MEM_LITERAL: @@ -882,3 +884,15 @@ neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (sh case: return 7, 0x1, 4 } } + +// LDM/STM come in a writeback form and a plain one that differ only in bit 21, +// so the operand shapes cannot tell them apart. +@(private="file", require_results) +writeback_matches :: #force_inline proc "contextless" (inst: ^Instruction, f: ^Encoding) -> bool { + for e in f.enc { + if e == .A32_REG_LIST { + return ((f.bits >> 21) & 1 != 0) == inst.writeback + } + } + return true +} diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 5cb3ed3aa..e27e2558e 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -39,7 +39,10 @@ Instruction :: struct #align(64) { length: u8 | 3, // 2 or 4 bytes on the wire sets_flags: bool | 1, // S bit (writes APSR.NZCV) wide: bool | 1, // force the T32 wide form when both exist - // 3 bits spare + // LDM/STM write the updated base back when this is set, which the + // syntax shows as a `!` after the base register. + writeback: bool | 1, + // 2 bits spare }, // Form-id hint: when non-zero, this is (1 + the index into // ENCODING_TABLE[mnemonic]) of the form the decoder produced. The encoder diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index dd21c4e68..889ac3cfe 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -136,6 +136,9 @@ sbprint :: proc( for k in 0.. 0 { strings.write_string(sb, ", ") } write_operand(sb, &inst.ops[k], inst, offset, &display, opts) + // LDM/STM write the updated base back, and the syntax marks + // that with a `!` on the base register itself. + if k == 0 && inst.writeback { strings.write_byte(sb, '!') } } } strings.write_string(sb, "\n") @@ -573,7 +576,10 @@ write_operand :: proc( write_memory :: proc(sb: ^strings.Builder, m: Memory) { strings.write_string(sb, "[") write_register(sb, m.base) - if reg_class(m.index) == REG_GPR && reg_hw(m.index) != 0 { + // An immediate-only form leaves index at Register(0), whose class is not + // REG_GPR -- so the class alone says whether there is an index. Excluding + // hw 0 as well made r0 unusable as one. + if reg_class(m.index) == REG_GPR { // Register offset switch m.mode { case .OFFSET: @@ -595,15 +601,18 @@ write_memory :: proc(sb: ^strings.Builder, m: Memory) { } else { // An indexed form writes its displacement even when it is zero: the // writeback is the point, and `[r0]` alone is the plain offset form. + // The U bit also survives a zero displacement, and an assembler needs + // to see it -- `#-0` and `#0` are different words. + neg := m.disp == 0 && m.sign < 0 ? "-" : "" switch m.mode { case .OFFSET: - if m.disp != 0 { - fmt.sbprintf(sb, ", #%d]", m.disp) + if m.disp != 0 || m.sign < 0 { + fmt.sbprintf(sb, ", #%s%d]", neg, m.disp) } else { strings.write_string(sb, "]") } - case .PRE_INDEX: fmt.sbprintf(sb, ", #%d]!", m.disp) - case .POST_INDEX: fmt.sbprintf(sb, "], #%d", m.disp) + case .PRE_INDEX: fmt.sbprintf(sb, ", #%s%d]!", neg, m.disp) + case .POST_INDEX: fmt.sbprintf(sb, "], #%s%d", neg, m.disp) } } } diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 56a3f0579..1f67e57ea 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -164,11 +164,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4 AND: 010000 0000 Rm Rd {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 AND imm12: high=11110 i 0 0000 S Rn low=0 imm3 Rd imm8 - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 AND reg: high=11101 01 0000 S Rn low=imm3 Rd imm2 type Rm - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .EOR = { {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {}}, @@ -224,11 +224,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 5 hi-reg MOV: 010001 10 H1 H2 Rm Rd {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MOV imm12-mod (encoding T2): high=11110 i 0 0010 S 1111 low=0 imm3 Rd imm8 - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 MOV reg (encoding T3): high=11101 01 0010 S 1111 low=0 imm3 Rd imm2 00 Rm - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .MVN = { {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {}}, @@ -1116,17 +1116,17 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // base register + register-list into Rn + register_list operand slots. .LDM = { // LDM IA (default) - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {}}, // LDMIA writeback (LDM Rn!, {reglist}): W=1 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {}}, // T16 Format 15 LDMIA: 11001 Rb reg_list8 {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14 {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STM = { - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {}}, // T16 Format 15 STMIA: 11000 Rb reg_list8 {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STMIA: 0xE8800000 @@ -1442,23 +1442,23 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1110 .I8 โ†’ 0xF2800E10 // 1111 .F32 (special: high bit = 0) โ†’ 0xF2800F10 (limited to specific imm patterns) // 1110 op=1 + bit 5 set โ†’ .I64 โ†’ 0xF2800E30 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) // Q forms (Q=1, bit 6 = 1) - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q // ---- VMOV scalar to/from GPR (lane access) ---- // VMOV. Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000 // VMOV. Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000 @@ -1883,11 +1883,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 @@ -1906,10 +1906,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 @@ -1927,10 +1927,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { @@ -2136,15 +2136,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer: 1111 0011 1011 size 01 Vd 0011 0 Q M 0 Vm - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 (size=10, bit 10 = 1) - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vabs.s8 q,q = FFB1_0340; vabs.f32 q,q = FFB9_0740 (bit 19 = 1 for FP). {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, @@ -2153,15 +2153,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer (bit 7 = 1 distinguishes VNEG from VABS) - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vneg.s8 q,q = FFB1_03C0; vneg.f32 q,q = FFB9_07C0. {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, @@ -2173,36 +2173,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VCLZ = { - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VCLS = { - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VREV16 / VREV32 / VREV64 (byte/half/word reverse within block) ---- .VREV64 = { - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VREV32 = { - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, }, .VREV16 = { {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, @@ -2234,26 +2234,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---- VTRN / VUZP / VZIP (interleave / deinterleave) ---- .VTRN = { - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VUZP = { - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VZIP = { - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTBL / VTBX (table lookup) ---- @@ -2510,26 +2510,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .VMOVN = { // VMOVN.I D, Q : 1111 0011 1 D 11 size 10 Vd 0010 0 0 M 0 Vm - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 }, .VQMOVN = { // VQMOVN. (signed saturating narrowing move) // .S: 1111 0011 1 D 11 size 10 Vd 0010 1 0 M 0 Vm // .U: same with op bit 6 = 1 - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, .VQMOVUN = { // VQMOVUN (signed input, unsigned saturating output): 1111 0011 1 D 11 size 10 Vd 0010 0 1 M 0 Vm (bit 6=1, bit 7=0) - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, }, // ---- VSHLL / VSHRN / VRSHRN / VQSHRN / VQRSHRN ---- @@ -2538,9 +2538,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm @@ -2571,13 +2571,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1111 0011 1 D 11 size 00 Vd 0010 op Q M 0 Vm (op=0 add long, op=1 accumulate) .VPADDL = { // .S: - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // Q form {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .U variants: bit 7 = 1 - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VPADAL = { @@ -2655,9 +2655,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: LSL reg (Rd = Rd <<= Rs) {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSL imm (encoded as MOV with shift LSL): high=11101010 0100 1111 low=0 imm3 Rd imm2 00 Rm - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSL reg: high=11111010 0000 Rn low=1111 Rd 0000 Rm - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LSR = { {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2667,9 +2667,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: LSR reg {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSR imm (MOV with shift LSR): bits 5:4 = 01 - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSR reg: 0xFA20F000 - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ASR = { {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2679,9 +2679,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: ASR reg {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ASR imm: bits 5:4 = 10 - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ASR reg: 0xFA40F000 - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ROR = { {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {}}, @@ -2689,9 +2689,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // T16 Format 4: ROR reg {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ROR imm: bits 5:4 = 11 - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ROR reg: 0xFA60F000 - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RRX = { // RRX is ROR with imm=0 (cond 00011010 0000 Rd 00000110 Rm) @@ -3623,10 +3623,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, @@ -3643,10 +3643,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 779676d58..f7f3870a1 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -215,8 +215,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -267,8 +267,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -367,41 +367,41 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -469,8 +469,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -491,8 +491,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, @@ -518,8 +518,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -583,8 +583,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -656,8 +656,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -682,123 +682,123 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, 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{.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -822,10 +822,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -988,11 +988,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1210,19 +1210,19 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .LDRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .STRD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1367,13 +1367,13 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1443,6 +1443,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1492,10 +1496,6 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1674,46 +1674,46 @@ DECODE_FORM_IDX := [1649]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, + 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, - 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 23, 25, 22, 21, 0, 0, - 0, 0, 11, 10, 19, 20, 17, 18, 10, 12, 14, 16, 13, 15, 11, 0, - 6, 0, 0, 7, 4, 3, 9, 2, 6, 5, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 24, 23, 25, 21, 22, 0, 0, 0, 19, 12, + 17, 14, 20, 18, 10, 16, 13, 15, 11, 0, 0, 0, 0, 11, 10, 0, + 6, 0, 0, 7, 2, 6, 3, 4, 9, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 3, 1, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, - 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, + 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, + 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, - 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, + 20, 14, 13, 9, 4, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 10, 0, 2, 1, 3, 1, 2, 0, 3, 0, 0, 0, 9, 5, 4, - 7, 8, 3, 2, 6, 5, 7, 6, 3, 4, 8, 9, 2, 1, 0, 0, - 1, 2, 0, 1, 3, 5, 4, 2, 0, 2, 1, 11, 10, 13, 12, 12, - 15, 13, 14, 14, 12, 15, 13, 16, 14, 17, 15, 17, 16, 14, 15, 5, - 2, 1, 0, 4, 3, 1, 0, 3, 2, 2, 1, 3, 1, 5, 4, 0, - 2, 3, 1, 3, 2, 4, 0, 5, 1, 0, 0, 1, 1, 0, 3, 2, - 5, 2, 1, 0, 4, 3, 1, 0, 2, 3, 4, 5, 2, 1, 0, 4, - 3, 2, 1, 0, 4, 3, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, - 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 0, 2, 0, - 2, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, + 0, 5, 4, 6, 8, 9, 2, 3, 7, 3, 7, 5, 6, 4, 2, 9, + 8, 10, 1, 0, 2, 0, 5, 1, 2, 3, 4, 2, 1, 0, 2, 0, + 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 5, 1, 3, + 2, 0, 4, 2, 0, 4, 5, 1, 3, 0, 5, 1, 3, 2, 4, 0, + 1, 2, 3, 4, 5, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 10, + 13, 12, 15, 12, 13, 14, 13, 14, 12, 15, 17, 15, 16, 14, 14, 16, + 15, 17, 1, 2, 0, 3, 0, 1, 0, 1, 0, 1, 3, 5, 0, 2, + 1, 3, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, + 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 2, 0, 2, + 0, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, @@ -1751,10 +1751,10 @@ DECODE_FORM_IDX := [1649]u16{ 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, - 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, + 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, + 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, @@ -1769,7 +1769,7 @@ DECODE_FORM_IDX := [1649]u16{ } @(rodata) -DECODE_BUCKET_LIST := [5359]u16{ +DECODE_BUCKET_LIST := [5335]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1807,26 +1807,26 @@ DECODE_BUCKET_LIST := [5359]u16{ 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, - 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 359, 360, 365, 361, 362, 363, - 364, 366, 367, 368, 369, 370, 371, 374, 380, 372, 379, 381, 378, 377, 373, 375, - 376, 382, 383, 384, 385, 386, 387, 389, 388, 394, 391, 393, 392, 390, 395, 396, + 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 361, 360, 362, 359, 363, 364, + 365, 370, 375, 376, 369, 374, 371, 368, 372, 367, 373, 366, 377, 378, 379, 380, + 381, 382, 384, 383, 385, 386, 392, 388, 387, 393, 391, 390, 389, 394, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 427, 428, - 430, 429, 431, 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, + 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 428, 427, + 429, 430, 431, 432, 433, 434, 436, 435, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 441, - 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 456, - 457, 459, 458, 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, + 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 454, 455, 456, + 457, 458, 459, 461, 460, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 468, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, - 412, 413, 469, 470, 471, 468, 358, 359, 360, 365, 364, 363, 362, 361, 366, 367, - 368, 369, 370, 371, 382, 381, 380, 379, 378, 377, 376, 374, 373, 372, 375, 383, + 412, 413, 469, 470, 471, 468, 362, 360, 361, 359, 358, 363, 364, 365, 376, 375, + 374, 372, 371, 370, 373, 368, 369, 367, 366, 377, 378, 379, 380, 382, 381, 383, 384, 385, 386, 394, 393, 392, 391, 389, 390, 388, 387, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 472, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 428, 427, 429, 430, 431, + 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 473, 472, 442, 443, - 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 455, 454, 456, 457, 459, 458, - 461, 460, 463, 462, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, + 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 457, 456, 458, 459, + 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 474, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 469, 470, 475, 474, 477, 476, 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, @@ -1835,37 +1835,37 @@ DECODE_BUCKET_LIST := [5359]u16{ 520, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, - 569, 570, 571, 572, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, + 569, 570, 571, 572, 573, 575, 574, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 477, 476, - 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 493, - 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, - 510, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, + 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 494, + 493, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 510, + 509, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, 527, 526, 528, 529, 530, 531, 532, 615, 534, 535, 536, 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, 558, 559, 616, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, - 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, - 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 617, 618, 619, 620, - 365, 364, 363, 361, 362, 621, 622, 623, 624, 370, 371, 382, 380, 379, 381, 378, - 375, 376, 377, 374, 373, 372, 625, 626, 627, 394, 393, 390, 391, 392, 389, 388, + 586, 587, 589, 588, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, + 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 617, 361, 362, 360, + 359, 358, 618, 619, 620, 376, 373, 374, 375, 372, 371, 370, 368, 367, 369, 366, + 621, 622, 623, 624, 382, 381, 625, 626, 627, 394, 393, 390, 391, 392, 389, 388, 387, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, - 640, 641, 642, 644, 643, 645, 646, 647, 648, 649, 650, 628, 629, 395, 396, 397, + 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, - 651, 630, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, - 667, 666, 669, 668, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, - 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 672, 673, 677, 675, 674, - 676, 680, 679, 678, 681, 682, 683, 684, 692, 690, 687, 688, 689, 691, 685, 686, - 698, 694, 700, 697, 696, 693, 699, 695, 702, 701, 704, 703, 705, 711, 709, 710, - 708, 706, 707, 713, 712, 714, 718, 716, 717, 715, 719, 721, 720, 722, 724, 725, - 726, 723, 730, 729, 727, 728, 733, 731, 734, 732, 740, 737, 735, 738, 739, 736, - 743, 744, 742, 741, 745, 746, 747, 752, 748, 753, 749, 750, 751, 759, 757, 755, - 754, 758, 756, 760, 761, 762, 763, 765, 766, 764, 767, 771, 773, 769, 768, 772, - 770, 777, 775, 779, 776, 778, 774, 780, 784, 783, 782, 781, 789, 787, 788, 785, - 786, 791, 790, 792, 793, 794, 795, 797, 799, 798, 796, 802, 800, 803, 801, 805, + 651, 630, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 665, 664, + 667, 666, 668, 669, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, + 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 672, 675, 674, 673, 680, + 679, 678, 677, 676, 683, 687, 688, 682, 685, 684, 686, 681, 689, 692, 690, 691, + 695, 698, 693, 697, 696, 694, 701, 700, 699, 704, 702, 703, 705, 709, 708, 706, + 707, 711, 713, 710, 712, 714, 716, 715, 718, 717, 720, 722, 721, 719, 724, 728, + 725, 727, 726, 723, 733, 730, 729, 731, 734, 732, 740, 738, 739, 735, 737, 736, + 742, 741, 743, 746, 745, 744, 747, 748, 749, 753, 752, 751, 750, 757, 755, 756, + 754, 760, 761, 759, 758, 765, 762, 763, 764, 767, 769, 766, 768, 773, 770, 771, + 772, 775, 774, 776, 777, 779, 778, 781, 780, 782, 785, 783, 784, 787, 786, 789, + 788, 791, 790, 792, 793, 794, 795, 797, 799, 798, 796, 802, 800, 803, 801, 805, 804, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 412, 413, 806, 672, 618, 619, 620, 365, 364, 363, 361, 362, - 621, 622, 623, 624, 371, 370, 382, 380, 379, 378, 376, 375, 374, 372, 373, 377, + 408, 409, 410, 411, 412, 413, 806, 672, 362, 361, 359, 360, 358, 618, 619, 620, + 376, 374, 373, 372, 369, 370, 371, 375, 366, 367, 368, 621, 622, 623, 624, 382, 381, 625, 626, 627, 394, 392, 393, 391, 390, 387, 388, 389, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 807, 631, 632, 633, 634, 635, 636, 637, 638, 639, 640, 641, 642, 643, 644, @@ -1873,14 +1873,14 @@ DECODE_BUCKET_LIST := [5359]u16{ 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 808, 807, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 664, 665, 667, 666, 669, 668, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 412, 413, 809, 673, 677, 675, 674, 676, 680, 678, 679, 681, - 682, 683, 684, 690, 691, 692, 687, 688, 686, 685, 689, 700, 699, 698, 696, 695, - 693, 694, 697, 701, 702, 705, 704, 703, 711, 707, 708, 709, 706, 710, 714, 712, - 713, 717, 716, 715, 718, 721, 722, 720, 719, 726, 725, 724, 723, 728, 729, 730, - 727, 734, 733, 732, 731, 739, 740, 736, 737, 738, 735, 742, 741, 743, 744, 745, - 747, 746, 753, 750, 751, 752, 748, 749, 758, 759, 756, 754, 755, 757, 761, 760, - 763, 762, 764, 765, 766, 767, 772, 771, 769, 768, 770, 773, 778, 776, 777, 775, - 774, 779, 782, 780, 784, 781, 783, 786, 787, 785, 789, 788, 791, 790, 792, 793, + 408, 409, 410, 411, 412, 413, 809, 680, 677, 678, 679, 675, 674, 673, 676, 687, + 688, 686, 685, 683, 682, 681, 684, 689, 690, 691, 692, 698, 696, 695, 693, 694, + 697, 700, 701, 699, 705, 704, 703, 702, 707, 708, 709, 706, 711, 712, 713, 710, + 716, 714, 715, 721, 722, 720, 719, 717, 718, 728, 726, 727, 725, 724, 723, 734, + 733, 732, 729, 730, 731, 739, 740, 736, 737, 738, 735, 742, 741, 743, 744, 745, + 746, 747, 748, 749, 753, 750, 751, 752, 756, 754, 755, 757, 761, 758, 759, 760, + 764, 763, 762, 765, 769, 766, 767, 768, 772, 771, 770, 773, 775, 774, 776, 777, + 778, 779, 780, 781, 785, 784, 782, 783, 786, 787, 788, 789, 791, 790, 792, 793, 794, 795, 799, 797, 798, 796, 802, 800, 801, 803, 804, 805, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, @@ -1897,214 +1897,213 @@ DECODE_BUCKET_LIST := [5359]u16{ 938, 939, 940, 941, 942, 943, 939, 944, 945, 946, 947, 948, 949, 950, 951, 952, 953, 954, 955, 956, 957, 958, 959, 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 952, 954, 970, 970, 971, 972, 960, 971, 972, 967, 973, 974, 973, 975, 976, - 977, 975, 976, 977, 978, 976, 978, 976, 979, 981, 976, 983, 980, 979, 981, 976, - 982, 983, 980, 978, 976, 978, 976, 984, 976, 985, 986, 984, 976, 985, 978, 976, - 978, 976, 987, 976, 988, 987, 976, 988, 978, 976, 978, 976, 989, 990, 989, 990, + 977, 975, 976, 977, 978, 976, 978, 976, 979, 976, 980, 981, 976, 982, 983, 978, + 976, 978, 976, 984, 976, 985, 986, 984, 976, 985, 978, 976, 978, 976, 987, 976, + 988, 987, 976, 988, 978, 976, 978, 976, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, - 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 990, 989, 991, 989, 991, + 989, 990, 989, 990, 989, 990, 989, 990, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, - 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, - 1008, 995, 996, 1007, 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 995, 996, 1009, 1007, 1008, 997, 998, 992, 993, 994, 1010, 1011, 1007, 1012, 1008, - 995, 1013, 996, 1014, 1015, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, - 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 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1242, 1243, 1244, 1253, 1254, 1255, 1256, 1545, 1546, 1547, + 1548, 1554, 1299, 1300, 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1564, 1566, 1568, 1530, + 1531, 1251, 1252, 1270, 1271, 1281, 1282, 1287, 1288, 1545, 1546, 1547, 1548, 1554, 1299, 1300, + 1307, 1308, 1309, 1310, 1311, 1312, 1313, 1314, 1555, 1556, 1557, 1558, 1564, 1566, 1568, 1542, + 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, + 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, - 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, - 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, - 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, - 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, + 1326, 1327, 1328, 1329, 1330, 1544, 1293, 1553, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, + 1325, 1326, 1327, 1328, 1329, 1330, 1542, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, + 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, + 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, + 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, + 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, + 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, + 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, + 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, + 1539, 1540, 1541, 1554, 1333, 1334, 1335, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2237,519 +2236,518 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x85 = { 2037, 1}, 0x86 = { 2038, 1}, 0x87 = { 2039, 1}, - 0x88 = { 2040, 2}, - 0x89 = { 2042, 3}, - 0x8A = { 2045, 2}, - 0x8B = { 2047, 4}, - 0x8C = { 2051, 1}, - 0x8D = { 2052, 1}, - 0x8E = { 2053, 1}, - 0x8F = { 2054, 1}, - 0x90 = { 2055, 1}, - 0x91 = { 2056, 2}, - 0x92 = { 2058, 2}, - 0x93 = { 2060, 2}, - 0x94 = { 2062, 1}, - 0x95 = { 2063, 1}, - 0x96 = { 2064, 1}, - 0x97 = { 2065, 1}, - 0x98 = { 2066, 1}, - 0x99 = { 2067, 2}, - 0x9A = { 2069, 1}, - 0x9B = { 2070, 2}, - 0x9C = { 2072, 1}, - 0x9D = { 2073, 1}, - 0x9E = { 2074, 1}, - 0x9F = { 2075, 1}, - 0xA0 = { 2076, 2}, - 0xA1 = { 2078, 2}, - 0xA2 = { 2080, 2}, - 0xA3 = { 2082, 2}, - 0xA4 = { 2084, 2}, - 0xA5 = { 2086, 2}, - 0xA6 = { 2088, 2}, - 0xA7 = { 2090, 2}, - 0xA8 = { 2092, 2}, - 0xA9 = { 2094, 2}, - 0xAA = { 2096, 2}, - 0xAB = { 2098, 2}, - 0xAC = { 2100, 2}, - 0xAD = { 2102, 2}, - 0xAE = { 2104, 2}, - 0xAF = { 2106, 2}, - 0xB0 = { 2108, 2}, - 0xB1 = { 2110, 2}, - 0xB2 = { 2112, 2}, - 0xB3 = { 2114, 2}, - 0xB4 = { 2116, 2}, - 0xB5 = { 2118, 2}, - 0xB6 = { 2120, 2}, - 0xB7 = { 2122, 2}, - 0xB8 = { 2124, 2}, - 0xB9 = { 2126, 2}, - 0xBA = { 2128, 2}, - 0xBB = { 2130, 2}, - 0xBC = { 2132, 2}, - 0xBD = { 2134, 2}, - 0xBE = { 2136, 2}, - 0xBF = { 2138, 2}, - 0xC0 = { 2140, 7}, - 0xC1 = { 2147, 4}, - 0xC2 = { 2151, 12}, - 0xC3 = { 2163, 5}, - 0xC4 = { 2168, 11}, - 0xC5 = { 2179, 8}, - 0xC6 = { 2187, 12}, - 0xC7 = { 2199, 5}, - 0xC8 = { 2204, 6}, - 0xC9 = { 2210, 6}, - 0xCA = { 2216, 12}, - 0xCB = { 2228, 8}, - 0xCC = { 2236, 6}, - 0xCD = { 2242, 6}, - 0xCE = { 2248, 12}, - 0xCF = { 2260, 6}, - 0xD0 = { 2266, 4}, - 0xD1 = { 2270, 4}, - 0xD2 = { 2274, 4}, - 0xD3 = { 2278, 2}, - 0xD4 = { 2280, 4}, - 0xD5 = { 2284, 4}, - 0xD6 = { 2288, 2}, - 0xD7 = { 2290, 2}, - 0xD8 = { 2292, 4}, - 0xD9 = { 2296, 4}, - 0xDA = { 2300, 2}, - 0xDB = { 2302, 2}, - 0xDC = { 2304, 4}, - 0xDD = { 2308, 4}, - 0xDE = { 2312, 2}, - 0xDF = { 2314, 2}, - 0xE0 = { 2316, 19}, - 0xE1 = { 2335, 14}, - 0xE2 = { 2349, 19}, - 0xE3 = { 2368, 15}, - 0xE4 = { 2383, 17}, - 0xE5 = { 2400, 13}, - 0xE6 = { 2413, 18}, - 0xE7 = { 2431, 15}, - 0xE8 = { 2446, 14}, - 0xE9 = { 2460, 11}, - 0xEA = { 2471, 10}, - 0xEB = { 2481, 77}, - 0xEC = { 2558, 15}, - 0xED = { 2573, 11}, - 0xEE = { 2584, 12}, - 0xEF = { 2596, 78}, - 0xF0 = { 2674, 3}, - 0xF1 = { 2677, 3}, - 0xF2 = { 2680, 3}, - 0xF3 = { 2683, 3}, - 0xF4 = { 2686, 3}, - 0xF5 = { 2689, 3}, - 0xF6 = { 2692, 3}, - 0xF7 = { 2695, 3}, - 0xF8 = { 2698, 1}, - 0xF9 = { 2699, 1}, - 0xFA = { 2700, 1}, - 0xFB = { 2701, 1}, - 0xFC = { 2702, 1}, - 0xFD = { 2703, 1}, - 0xFE = { 2704, 1}, - 0xFF = { 2705, 1}, + 0x88 = { 2040, 1}, + 0x89 = { 2041, 2}, + 0x8A = { 2043, 1}, + 0x8B = { 2044, 3}, + 0x8C = { 2047, 1}, + 0x8D = { 2048, 1}, + 0x8E = { 2049, 1}, + 0x8F = { 2050, 1}, + 0x90 = { 2051, 1}, + 0x91 = { 2052, 2}, + 0x92 = { 2054, 2}, + 0x93 = { 2056, 2}, + 0x94 = { 2058, 1}, + 0x95 = { 2059, 1}, + 0x96 = { 2060, 1}, + 0x97 = { 2061, 1}, + 0x98 = { 2062, 1}, + 0x99 = { 2063, 2}, + 0x9A = { 2065, 1}, + 0x9B = { 2066, 2}, + 0x9C = { 2068, 1}, + 0x9D = { 2069, 1}, + 0x9E = { 2070, 1}, + 0x9F = { 2071, 1}, + 0xA0 = { 2072, 2}, + 0xA1 = { 2074, 2}, + 0xA2 = { 2076, 2}, + 0xA3 = { 2078, 2}, + 0xA4 = { 2080, 2}, + 0xA5 = { 2082, 2}, + 0xA6 = { 2084, 2}, + 0xA7 = { 2086, 2}, + 0xA8 = { 2088, 2}, + 0xA9 = { 2090, 2}, + 0xAA = { 2092, 2}, + 0xAB = { 2094, 2}, + 0xAC = { 2096, 2}, + 0xAD = { 2098, 2}, + 0xAE = { 2100, 2}, + 0xAF = { 2102, 2}, + 0xB0 = { 2104, 2}, + 0xB1 = { 2106, 2}, + 0xB2 = { 2108, 2}, + 0xB3 = { 2110, 2}, + 0xB4 = { 2112, 2}, + 0xB5 = { 2114, 2}, + 0xB6 = { 2116, 2}, + 0xB7 = { 2118, 2}, + 0xB8 = { 2120, 2}, + 0xB9 = { 2122, 2}, + 0xBA = { 2124, 2}, + 0xBB = { 2126, 2}, + 0xBC = { 2128, 2}, + 0xBD = { 2130, 2}, + 0xBE = { 2132, 2}, + 0xBF = { 2134, 2}, + 0xC0 = { 2136, 7}, + 0xC1 = { 2143, 4}, + 0xC2 = { 2147, 12}, + 0xC3 = { 2159, 5}, + 0xC4 = { 2164, 11}, + 0xC5 = { 2175, 8}, + 0xC6 = { 2183, 12}, + 0xC7 = { 2195, 5}, + 0xC8 = { 2200, 6}, + 0xC9 = { 2206, 6}, + 0xCA = { 2212, 12}, + 0xCB = { 2224, 8}, + 0xCC = { 2232, 6}, + 0xCD = { 2238, 6}, + 0xCE = { 2244, 12}, + 0xCF = { 2256, 6}, + 0xD0 = { 2262, 4}, + 0xD1 = { 2266, 4}, + 0xD2 = { 2270, 4}, + 0xD3 = { 2274, 2}, + 0xD4 = { 2276, 4}, + 0xD5 = { 2280, 4}, + 0xD6 = { 2284, 2}, + 0xD7 = { 2286, 2}, + 0xD8 = { 2288, 4}, + 0xD9 = { 2292, 4}, + 0xDA = { 2296, 2}, + 0xDB = { 2298, 2}, + 0xDC = { 2300, 4}, + 0xDD = { 2304, 4}, + 0xDE = { 2308, 2}, + 0xDF = { 2310, 2}, + 0xE0 = { 2312, 19}, + 0xE1 = { 2331, 14}, + 0xE2 = { 2345, 19}, + 0xE3 = { 2364, 15}, + 0xE4 = { 2379, 17}, + 0xE5 = { 2396, 13}, + 0xE6 = { 2409, 18}, + 0xE7 = { 2427, 15}, + 0xE8 = { 2442, 14}, + 0xE9 = { 2456, 11}, + 0xEA = { 2467, 10}, + 0xEB = { 2477, 77}, + 0xEC = { 2554, 15}, + 0xED = { 2569, 11}, + 0xEE = { 2580, 12}, + 0xEF = { 2592, 78}, + 0xF0 = { 2670, 3}, + 0xF1 = { 2673, 3}, + 0xF2 = { 2676, 3}, + 0xF3 = { 2679, 3}, + 0xF4 = { 2682, 3}, + 0xF5 = { 2685, 3}, + 0xF6 = { 2688, 3}, + 0xF7 = { 2691, 3}, + 0xF8 = { 2694, 1}, + 0xF9 = { 2695, 1}, + 0xFA = { 2696, 1}, + 0xFB = { 2697, 1}, + 0xFC = { 2698, 1}, + 0xFD = { 2699, 1}, + 0xFE = { 2700, 1}, + 0xFF = { 2701, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2706, 23}, - 0x75 = { 2729, 19}, - 0x76 = { 2748, 19}, - 0x77 = { 2767, 104}, - 0x78 = { 2871, 31}, - 0x79 = { 2902, 38}, - 0x7A = { 2940, 23}, - 0x7B = { 2963, 14}, - 0x7C = { 2977, 20}, - 0x7D = { 2997, 71}, - 0x7E = { 3068, 23}, - 0x7F = { 3091, 126}, + 0x74 = { 2702, 23}, + 0x75 = { 2725, 19}, + 0x76 = { 2744, 19}, + 0x77 = { 2763, 104}, + 0x78 = { 2867, 31}, + 0x79 = { 2898, 38}, + 0x7A = { 2936, 23}, + 0x7B = { 2959, 14}, + 0x7C = { 2973, 20}, + 0x7D = { 2993, 71}, + 0x7E = { 3064, 23}, + 0x7F = { 3087, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3217, 1}, - 0x01 = { 3218, 1}, - 0x02 = { 3219, 1}, - 0x03 = { 3220, 1}, - 0x04 = { 3221, 1}, - 0x05 = { 3222, 1}, - 0x06 = { 3223, 2}, - 0x07 = { 3225, 2}, - 0x08 = { 3227, 1}, - 0x09 = { 3228, 1}, - 0x0A = { 3229, 1}, - 0x0B = { 3230, 1}, - 0x0C = { 3231, 1}, - 0x0D = { 3232, 1}, - 0x0E = { 3233, 1}, - 0x0F = { 3234, 1}, - 0x10 = { 3235, 16}, - 0x11 = { 3251, 7}, - 0x12 = { 3258, 1}, - 0x13 = { 3259, 1}, - 0x14 = { 3260, 2}, - 0x15 = { 3262, 2}, - 0x16 = { 3264, 2}, - 0x17 = { 3266, 2}, - 0x18 = { 3268, 1}, - 0x19 = { 3269, 1}, - 0x1A = { 3270, 1}, - 0x1B = { 3271, 1}, - 0x1C = { 3272, 1}, - 0x1D = { 3273, 1}, - 0x1E = { 3274, 1}, - 0x1F = { 3275, 1}, - 0x20 = { 3276, 1}, - 0x21 = { 3277, 1}, - 0x22 = { 3278, 1}, - 0x23 = { 3279, 1}, - 0x24 = { 3280, 1}, - 0x25 = { 3281, 1}, - 0x26 = { 3282, 1}, - 0x27 = { 3283, 1}, - 0x28 = { 3284, 1}, - 0x29 = { 3285, 1}, - 0x2A = { 3286, 1}, - 0x2B = { 3287, 1}, - 0x2C = { 3288, 7}, - 0x2D = { 3295, 2}, - 0x2E = { 3297, 4}, - 0x2F = { 3301, 8}, - 0x30 = { 3309, 1}, - 0x31 = { 3310, 1}, - 0x32 = { 3311, 1}, - 0x33 = { 3312, 1}, - 0x34 = { 3313, 1}, - 0x35 = { 3314, 1}, - 0x36 = { 3315, 1}, - 0x37 = { 3316, 3}, - 0x38 = { 3319, 1}, - 0x39 = { 3320, 1}, + 0x00 = { 3213, 1}, + 0x01 = { 3214, 1}, + 0x02 = { 3215, 1}, + 0x03 = { 3216, 1}, + 0x04 = { 3217, 1}, + 0x05 = { 3218, 1}, + 0x06 = { 3219, 2}, + 0x07 = { 3221, 2}, + 0x08 = { 3223, 1}, + 0x09 = { 3224, 1}, + 0x0A = { 3225, 1}, + 0x0B = { 3226, 1}, + 0x0C = { 3227, 1}, + 0x0D = { 3228, 1}, + 0x0E = { 3229, 1}, + 0x0F = { 3230, 1}, + 0x10 = { 3231, 16}, + 0x11 = { 3247, 7}, + 0x12 = { 3254, 1}, + 0x13 = { 3255, 1}, + 0x14 = { 3256, 2}, + 0x15 = { 3258, 2}, + 0x16 = { 3260, 2}, + 0x17 = { 3262, 2}, + 0x18 = { 3264, 1}, + 0x19 = { 3265, 1}, + 0x1A = { 3266, 1}, + 0x1B = { 3267, 1}, + 0x1C = { 3268, 1}, + 0x1D = { 3269, 1}, + 0x1E = { 3270, 1}, + 0x1F = { 3271, 1}, + 0x20 = { 3272, 1}, + 0x21 = { 3273, 1}, + 0x22 = { 3274, 1}, + 0x23 = { 3275, 1}, + 0x24 = { 3276, 1}, + 0x25 = { 3277, 1}, + 0x26 = { 3278, 1}, + 0x27 = { 3279, 1}, + 0x28 = { 3280, 1}, + 0x29 = { 3281, 1}, + 0x2A = { 3282, 1}, + 0x2B = { 3283, 1}, + 0x2C = { 3284, 7}, + 0x2D = { 3291, 2}, + 0x2E = { 3293, 4}, + 0x2F = { 3297, 8}, + 0x30 = { 3305, 1}, + 0x31 = { 3306, 1}, + 0x32 = { 3307, 1}, + 0x33 = { 3308, 1}, + 0x34 = { 3309, 1}, + 0x35 = { 3310, 1}, + 0x36 = { 3311, 1}, + 0x37 = { 3312, 3}, + 0x38 = { 3315, 1}, + 0x39 = { 3316, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3321, 6}, - 0xE85 = { 3327, 2}, - 0xE86 = { 3329, 1}, - 0xE87 = { 3330, 1}, - 0xE88 = { 3331, 1}, - 0xE89 = { 3332, 1}, - 0xE8A = { 3333, 1}, - 0xE8B = { 3334, 2}, - 0xE8C = { 3336, 4}, - 0xE8D = { 3340, 6}, - 0xE8E = { 3346, 1}, - 0xE8F = { 3347, 1}, - 0xE90 = { 3348, 1}, - 0xE91 = { 3349, 1}, - 0xE92 = { 3350, 2}, - 0xE93 = { 3352, 1}, - 0xE94 = { 3353, 1}, - 0xE95 = { 3354, 1}, - 0xE96 = { 3355, 1}, - 0xE97 = { 3356, 2}, - 0xE9C = { 3358, 1}, - 0xE9D = { 3359, 1}, - 0xE9E = { 3360, 1}, - 0xE9F = { 3361, 1}, - 0xEA0 = { 3362, 2}, - 0xEA1 = { 3364, 3}, - 0xEA2 = { 3367, 1}, - 0xEA3 = { 3368, 1}, - 0xEA4 = { 3369, 7}, - 0xEA5 = { 3376, 7}, - 0xEA6 = { 3383, 1}, - 0xEA7 = { 3384, 1}, - 0xEA8 = { 3385, 1}, - 0xEA9 = { 3386, 2}, - 0xEB1 = { 3388, 1}, - 0xEB4 = { 3389, 1}, - 0xEB5 = { 3390, 1}, - 0xEB6 = { 3391, 1}, - 0xEB7 = { 3392, 1}, - 0xEBB = { 3393, 1}, - 0xEBC = { 3394, 1}, - 0xEBD = { 3395, 1}, - 0xEC0 = { 3396, 2}, - 0xEC1 = { 3398, 1}, - 0xEC2 = { 3399, 3}, - 0xEC3 = { 3402, 2}, - 0xEC4 = { 3404, 2}, - 0xEC5 = { 3406, 1}, - 0xEC6 = { 3407, 7}, - 0xEC7 = { 3414, 2}, - 0xEC8 = { 3416, 1}, - 0xEC9 = { 3417, 1}, - 0xECA = { 3418, 2}, - 0xECB = { 3420, 2}, - 0xECC = { 3422, 1}, - 0xECD = { 3423, 1}, - 0xECE = { 3424, 2}, - 0xECF = { 3426, 2}, - 0xED6 = { 3428, 4}, - 0xED8 = { 3432, 4}, - 0xED9 = { 3436, 4}, - 0xEDC = { 3440, 4}, - 0xEDD = { 3444, 4}, - 0xEE0 = { 3448, 24}, - 0xEE1 = { 3472, 23}, - 0xEE2 = { 3495, 22}, - 0xEE3 = { 3517, 29}, - 0xEE4 = { 3546, 23}, - 0xEE5 = { 3569, 22}, - 0xEE6 = { 3591, 22}, - 0xEE7 = { 3613, 29}, - 0xEE8 = { 3642, 28}, - 0xEE9 = { 3670, 12}, - 0xEEA = { 3682, 13}, - 0xEEB = { 3695, 18}, - 0xEEC = { 3713, 27}, - 0xEED = { 3740, 13}, - 0xEEE = { 3753, 22}, - 0xEEF = { 3775, 23}, - 0xEF0 = { 3798, 15}, - 0xEF1 = { 3813, 15}, - 0xEF2 = { 3828, 15}, - 0xEF3 = { 3843, 15}, - 0xEF4 = { 3858, 15}, - 0xEF5 = { 3873, 15}, - 0xEF6 = { 3888, 15}, - 0xEF7 = { 3903, 15}, - 0xEF8 = { 3918, 3}, - 0xEF9 = { 3921, 3}, - 0xEFA = { 3924, 3}, - 0xEFB = { 3927, 3}, - 0xEFC = { 3930, 3}, - 0xEFD = { 3933, 3}, - 0xEFE = { 3936, 3}, - 0xEFF = { 3939, 3}, - 0xF00 = { 3942, 12}, - 0xF01 = { 3954, 11}, - 0xF02 = { 3965, 8}, - 0xF03 = { 3973, 8}, - 0xF04 = { 3981, 9}, - 0xF05 = { 3990, 6}, - 0xF06 = { 3996, 5}, - 0xF07 = { 4001, 5}, - 0xF08 = { 4006, 6}, - 0xF09 = { 4012, 6}, - 0xF0A = { 4018, 4}, - 0xF0B = { 4022, 4}, - 0xF0C = { 4026, 4}, - 0xF0D = { 4030, 3}, - 0xF0E = { 4033, 4}, - 0xF0F = { 4037, 4}, - 0xF10 = { 4041, 7}, - 0xF11 = { 4048, 7}, - 0xF12 = { 4055, 6}, - 0xF13 = { 4061, 6}, - 0xF14 = { 4067, 5}, - 0xF15 = { 4072, 4}, - 0xF16 = { 4076, 5}, - 0xF17 = { 4081, 5}, - 0xF18 = { 4086, 5}, - 0xF19 = { 4091, 4}, - 0xF1A = { 4095, 4}, - 0xF1B = { 4099, 5}, - 0xF1C = { 4104, 5}, - 0xF1D = { 4109, 4}, - 0xF1E = { 4113, 4}, - 0xF1F = { 4117, 4}, - 0xF20 = { 4121, 5}, - 0xF21 = { 4126, 4}, - 0xF22 = { 4130, 4}, - 0xF23 = { 4134, 4}, - 0xF24 = { 4138, 5}, - 0xF25 = { 4143, 3}, - 0xF26 = { 4146, 4}, - 0xF27 = { 4150, 4}, - 0xF28 = { 4154, 5}, - 0xF29 = { 4159, 4}, - 0xF2A = { 4163, 4}, - 0xF2B = { 4167, 4}, - 0xF2C = { 4171, 5}, - 0xF2D = { 4176, 3}, - 0xF2E = { 4179, 4}, - 0xF2F = { 4183, 4}, - 0xF30 = { 4187, 6}, - 0xF31 = { 4193, 4}, - 0xF32 = { 4197, 6}, - 0xF33 = { 4203, 4}, - 0xF34 = { 4207, 5}, - 0xF35 = { 4212, 3}, - 0xF36 = { 4215, 6}, - 0xF37 = { 4221, 4}, - 0xF38 = { 4225, 7}, - 0xF39 = { 4232, 4}, - 0xF3A = { 4236, 19}, - 0xF3B = { 4255, 9}, - 0xF3C = { 4264, 5}, - 0xF3D = { 4269, 3}, - 0xF3E = { 4272, 5}, - 0xF3F = { 4277, 4}, - 0xF40 = { 4281, 7}, - 0xF41 = { 4288, 7}, - 0xF42 = { 4295, 5}, - 0xF43 = { 4300, 5}, - 0xF44 = { 4305, 7}, - 0xF45 = { 4312, 6}, - 0xF46 = { 4318, 5}, - 0xF47 = { 4323, 5}, - 0xF48 = { 4328, 6}, - 0xF49 = { 4334, 6}, - 0xF4A = { 4340, 4}, - 0xF4B = { 4344, 4}, - 0xF4C = { 4348, 4}, - 0xF4D = { 4352, 3}, - 0xF4E = { 4355, 4}, - 0xF4F = { 4359, 4}, - 0xF50 = { 4363, 5}, - 0xF51 = { 4368, 5}, - 0xF52 = { 4373, 4}, - 0xF53 = { 4377, 4}, - 0xF54 = { 4381, 5}, - 0xF55 = { 4386, 4}, - 0xF56 = { 4390, 5}, - 0xF57 = { 4395, 5}, - 0xF58 = { 4400, 5}, - 0xF59 = { 4405, 4}, - 0xF5A = { 4409, 4}, - 0xF5B = { 4413, 5}, - 0xF5C = { 4418, 5}, - 0xF5D = { 4423, 4}, - 0xF5E = { 4427, 4}, - 0xF5F = { 4431, 4}, - 0xF60 = { 4435, 5}, - 0xF61 = { 4440, 4}, - 0xF62 = { 4444, 4}, - 0xF63 = { 4448, 4}, - 0xF64 = { 4452, 5}, - 0xF65 = { 4457, 3}, - 0xF66 = { 4460, 4}, - 0xF67 = { 4464, 4}, - 0xF68 = { 4468, 5}, - 0xF69 = { 4473, 4}, - 0xF6A = { 4477, 4}, - 0xF6B = { 4481, 4}, - 0xF6C = { 4485, 5}, - 0xF6D = { 4490, 3}, - 0xF6E = { 4493, 4}, - 0xF6F = { 4497, 4}, - 0xF70 = { 4501, 5}, - 0xF71 = { 4506, 4}, - 0xF72 = { 4510, 4}, - 0xF73 = { 4514, 4}, - 0xF74 = { 4518, 4}, - 0xF75 = { 4522, 3}, - 0xF76 = { 4525, 4}, - 0xF77 = { 4529, 4}, - 0xF78 = { 4533, 8}, - 0xF79 = { 4541, 4}, - 0xF7A = { 4545, 4}, - 0xF7B = { 4549, 4}, - 0xF7C = { 4553, 4}, - 0xF7D = { 4557, 3}, - 0xF7E = { 4560, 4}, - 0xF7F = { 4564, 5}, - 0xF80 = { 4569, 1}, - 0xF81 = { 4570, 1}, - 0xF82 = { 4571, 1}, - 0xF83 = { 4572, 2}, - 0xF84 = { 4574, 1}, - 0xF85 = { 4575, 2}, - 0xF88 = { 4577, 1}, - 0xF89 = { 4578, 2}, - 0xF8A = { 4580, 1}, - 0xF8B = { 4581, 1}, - 0xF8C = { 4582, 1}, - 0xF8D = { 4583, 2}, - 0xF91 = { 4585, 1}, - 0xF93 = { 4586, 1}, - 0xF99 = { 4587, 2}, - 0xF9B = { 4589, 1}, - 0xFA0 = { 4590, 3}, - 0xFA1 = { 4593, 3}, - 0xFA2 = { 4596, 3}, - 0xFA3 = { 4599, 3}, - 0xFA4 = { 4602, 3}, - 0xFA5 = { 4605, 3}, - 0xFA6 = { 4608, 1}, - 0xFA7 = { 4609, 1}, - 0xFA8 = { 4610, 10}, - 0xFA9 = { 4620, 10}, - 0xFAA = { 4630, 6}, - 0xFAB = { 4636, 1}, - 0xFAC = { 4637, 6}, - 0xFAD = { 4643, 6}, - 0xFAE = { 4649, 6}, - 0xFB0 = { 4655, 3}, - 0xFB5 = { 4658, 1}, - 0xFB8 = { 4659, 1}, - 0xFB9 = { 4660, 1}, - 0xFBA = { 4661, 1}, - 0xFBB = { 4662, 1}, - 0xFBC = { 4663, 1}, - 0xFBE = { 4664, 1}, - 0xFC0 = { 4665, 1}, - 0xFC1 = { 4666, 1}, - 0xFC2 = { 4667, 3}, - 0xFC3 = { 4670, 3}, - 0xFC4 = { 4673, 1}, - 0xFC5 = { 4674, 1}, - 0xFC6 = { 4675, 2}, - 0xFC7 = { 4677, 2}, - 0xFC8 = { 4679, 7}, - 0xFC9 = { 4686, 11}, - 0xFCA = { 4697, 3}, - 0xFCB = { 4700, 3}, - 0xFCC = { 4703, 7}, - 0xFCD = { 4710, 7}, - 0xFCE = { 4717, 2}, - 0xFCF = { 4719, 2}, - 0xFD2 = { 4721, 1}, - 0xFD3 = { 4722, 1}, - 0xFD9 = { 4723, 4}, - 0xFDA = { 4727, 1}, - 0xFDB = { 4728, 1}, - 0xFE0 = { 4729, 28}, - 0xFE1 = { 4757, 26}, - 0xFE2 = { 4783, 26}, - 0xFE3 = { 4809, 32}, - 0xFE4 = { 4841, 29}, - 0xFE5 = { 4870, 27}, - 0xFE6 = { 4897, 27}, - 0xFE7 = { 4924, 33}, - 0xFE8 = { 4957, 32}, - 0xFE9 = { 4989, 17}, - 0xFEA = { 5006, 17}, - 0xFEB = { 5023, 29}, - 0xFEC = { 5052, 31}, - 0xFED = { 5083, 18}, - 0xFEE = { 5101, 26}, - 0xFEF = { 5127, 32}, - 0xFF0 = { 5159, 19}, - 0xFF1 = { 5178, 18}, - 0xFF2 = { 5196, 17}, - 0xFF3 = { 5213, 17}, - 0xFF4 = { 5230, 19}, - 0xFF5 = { 5249, 18}, - 0xFF6 = { 5267, 17}, - 0xFF7 = { 5284, 17}, - 0xFF8 = { 5301, 4}, - 0xFF9 = { 5305, 4}, - 0xFFA = { 5309, 4}, - 0xFFB = { 5313, 17}, - 0xFFC = { 5330, 4}, - 0xFFD = { 5334, 4}, - 0xFFE = { 5338, 4}, - 0xFFF = { 5342, 17}, + 0xE84 = { 3317, 6}, + 0xE85 = { 3323, 2}, + 0xE86 = { 3325, 1}, + 0xE87 = { 3326, 1}, + 0xE88 = { 3327, 1}, + 0xE89 = { 3328, 1}, + 0xE8A = { 3329, 1}, + 0xE8B = { 3330, 2}, + 0xE8C = { 3332, 4}, + 0xE8D = { 3336, 6}, + 0xE8E = { 3342, 1}, + 0xE8F = { 3343, 1}, + 0xE90 = { 3344, 1}, + 0xE91 = { 3345, 1}, + 0xE92 = { 3346, 2}, + 0xE93 = { 3348, 1}, + 0xE94 = { 3349, 1}, + 0xE95 = { 3350, 1}, + 0xE96 = { 3351, 1}, + 0xE97 = { 3352, 2}, + 0xE9C = { 3354, 1}, + 0xE9D = { 3355, 1}, + 0xE9E = { 3356, 1}, + 0xE9F = { 3357, 1}, + 0xEA0 = { 3358, 1}, + 0xEA1 = { 3359, 2}, + 0xEA2 = { 3361, 1}, + 0xEA3 = { 3362, 1}, + 0xEA4 = { 3363, 6}, + 0xEA5 = { 3369, 2}, + 0xEA6 = { 3371, 1}, + 0xEA7 = { 3372, 1}, + 0xEA8 = { 3373, 1}, + 0xEA9 = { 3374, 2}, + 0xEB1 = { 3376, 1}, + 0xEB4 = { 3377, 1}, + 0xEB5 = { 3378, 1}, + 0xEB6 = { 3379, 1}, + 0xEB7 = { 3380, 1}, + 0xEBB = { 3381, 1}, + 0xEBC = { 3382, 1}, + 0xEBD = { 3383, 1}, + 0xEC0 = { 3384, 2}, + 0xEC1 = { 3386, 1}, + 0xEC2 = { 3387, 3}, + 0xEC3 = { 3390, 2}, + 0xEC4 = { 3392, 2}, + 0xEC5 = { 3394, 1}, + 0xEC6 = { 3395, 7}, + 0xEC7 = { 3402, 2}, + 0xEC8 = { 3404, 1}, + 0xEC9 = { 3405, 1}, + 0xECA = { 3406, 2}, + 0xECB = { 3408, 2}, + 0xECC = { 3410, 1}, + 0xECD = { 3411, 1}, + 0xECE = { 3412, 2}, + 0xECF = { 3414, 2}, + 0xED6 = { 3416, 4}, + 0xED8 = { 3420, 4}, + 0xED9 = { 3424, 4}, + 0xEDC = { 3428, 4}, + 0xEDD = { 3432, 4}, + 0xEE0 = { 3436, 24}, + 0xEE1 = { 3460, 23}, + 0xEE2 = { 3483, 22}, + 0xEE3 = { 3505, 29}, + 0xEE4 = { 3534, 23}, + 0xEE5 = { 3557, 22}, + 0xEE6 = { 3579, 22}, + 0xEE7 = { 3601, 29}, + 0xEE8 = { 3630, 28}, + 0xEE9 = { 3658, 12}, + 0xEEA = { 3670, 13}, + 0xEEB = { 3683, 18}, + 0xEEC = { 3701, 27}, + 0xEED = { 3728, 13}, + 0xEEE = { 3741, 22}, + 0xEEF = { 3763, 23}, + 0xEF0 = { 3786, 15}, + 0xEF1 = { 3801, 15}, + 0xEF2 = { 3816, 15}, + 0xEF3 = { 3831, 15}, + 0xEF4 = { 3846, 15}, + 0xEF5 = { 3861, 15}, + 0xEF6 = { 3876, 15}, + 0xEF7 = { 3891, 15}, + 0xEF8 = { 3906, 3}, + 0xEF9 = { 3909, 3}, + 0xEFA = { 3912, 3}, + 0xEFB = { 3915, 3}, + 0xEFC = { 3918, 3}, + 0xEFD = { 3921, 3}, + 0xEFE = { 3924, 3}, + 0xEFF = { 3927, 3}, + 0xF00 = { 3930, 11}, + 0xF01 = { 3941, 10}, + 0xF02 = { 3951, 8}, + 0xF03 = { 3959, 8}, + 0xF04 = { 3967, 8}, + 0xF05 = { 3975, 5}, + 0xF06 = { 3980, 5}, + 0xF07 = { 3985, 5}, + 0xF08 = { 3990, 6}, + 0xF09 = { 3996, 6}, + 0xF0A = { 4002, 4}, + 0xF0B = { 4006, 4}, + 0xF0C = { 4010, 4}, + 0xF0D = { 4014, 3}, + 0xF0E = { 4017, 4}, + 0xF0F = { 4021, 4}, + 0xF10 = { 4025, 7}, + 0xF11 = { 4032, 7}, + 0xF12 = { 4039, 6}, + 0xF13 = { 4045, 6}, + 0xF14 = { 4051, 5}, + 0xF15 = { 4056, 4}, + 0xF16 = { 4060, 5}, + 0xF17 = { 4065, 5}, + 0xF18 = { 4070, 5}, + 0xF19 = { 4075, 4}, + 0xF1A = { 4079, 4}, + 0xF1B = { 4083, 5}, + 0xF1C = { 4088, 5}, + 0xF1D = { 4093, 4}, + 0xF1E = { 4097, 4}, + 0xF1F = { 4101, 4}, + 0xF20 = { 4105, 5}, + 0xF21 = { 4110, 4}, + 0xF22 = { 4114, 4}, + 0xF23 = { 4118, 4}, + 0xF24 = { 4122, 5}, + 0xF25 = { 4127, 3}, + 0xF26 = { 4130, 4}, + 0xF27 = { 4134, 4}, + 0xF28 = { 4138, 5}, + 0xF29 = { 4143, 4}, + 0xF2A = { 4147, 4}, + 0xF2B = { 4151, 4}, + 0xF2C = { 4155, 5}, + 0xF2D = { 4160, 3}, + 0xF2E = { 4163, 4}, + 0xF2F = { 4167, 4}, + 0xF30 = { 4171, 6}, + 0xF31 = { 4177, 4}, + 0xF32 = { 4181, 6}, + 0xF33 = { 4187, 4}, + 0xF34 = { 4191, 5}, + 0xF35 = { 4196, 3}, + 0xF36 = { 4199, 6}, + 0xF37 = { 4205, 4}, + 0xF38 = { 4209, 7}, + 0xF39 = { 4216, 4}, + 0xF3A = { 4220, 19}, + 0xF3B = { 4239, 9}, + 0xF3C = { 4248, 5}, + 0xF3D = { 4253, 3}, + 0xF3E = { 4256, 5}, + 0xF3F = { 4261, 4}, + 0xF40 = { 4265, 6}, + 0xF41 = { 4271, 6}, + 0xF42 = { 4277, 5}, + 0xF43 = { 4282, 5}, + 0xF44 = { 4287, 6}, + 0xF45 = { 4293, 5}, + 0xF46 = { 4298, 5}, + 0xF47 = { 4303, 5}, + 0xF48 = { 4308, 6}, + 0xF49 = { 4314, 6}, + 0xF4A = { 4320, 4}, + 0xF4B = { 4324, 4}, + 0xF4C = { 4328, 4}, + 0xF4D = { 4332, 3}, + 0xF4E = { 4335, 4}, + 0xF4F = { 4339, 4}, + 0xF50 = { 4343, 5}, + 0xF51 = { 4348, 5}, + 0xF52 = { 4353, 4}, + 0xF53 = { 4357, 4}, + 0xF54 = { 4361, 5}, + 0xF55 = { 4366, 4}, + 0xF56 = { 4370, 5}, + 0xF57 = { 4375, 5}, + 0xF58 = { 4380, 5}, + 0xF59 = { 4385, 4}, + 0xF5A = { 4389, 4}, + 0xF5B = { 4393, 5}, + 0xF5C = { 4398, 5}, + 0xF5D = { 4403, 4}, + 0xF5E = { 4407, 4}, + 0xF5F = { 4411, 4}, + 0xF60 = { 4415, 5}, + 0xF61 = { 4420, 4}, + 0xF62 = { 4424, 4}, + 0xF63 = { 4428, 4}, + 0xF64 = { 4432, 5}, + 0xF65 = { 4437, 3}, + 0xF66 = { 4440, 4}, + 0xF67 = { 4444, 4}, + 0xF68 = { 4448, 5}, + 0xF69 = { 4453, 4}, + 0xF6A = { 4457, 4}, + 0xF6B = { 4461, 4}, + 0xF6C = { 4465, 5}, + 0xF6D = { 4470, 3}, + 0xF6E = { 4473, 4}, + 0xF6F = { 4477, 4}, + 0xF70 = { 4481, 5}, + 0xF71 = { 4486, 4}, + 0xF72 = { 4490, 4}, + 0xF73 = { 4494, 4}, + 0xF74 = { 4498, 4}, + 0xF75 = { 4502, 3}, + 0xF76 = { 4505, 4}, + 0xF77 = { 4509, 4}, + 0xF78 = { 4513, 8}, + 0xF79 = { 4521, 4}, + 0xF7A = { 4525, 4}, + 0xF7B = { 4529, 4}, + 0xF7C = { 4533, 4}, + 0xF7D = { 4537, 3}, + 0xF7E = { 4540, 4}, + 0xF7F = { 4544, 5}, + 0xF80 = { 4549, 1}, + 0xF81 = { 4550, 1}, + 0xF82 = { 4551, 1}, + 0xF83 = { 4552, 2}, + 0xF84 = { 4554, 1}, + 0xF85 = { 4555, 2}, + 0xF88 = { 4557, 1}, + 0xF89 = { 4558, 2}, + 0xF8A = { 4560, 1}, + 0xF8B = { 4561, 1}, + 0xF8C = { 4562, 1}, + 0xF8D = { 4563, 2}, + 0xF91 = { 4565, 1}, + 0xF93 = { 4566, 1}, + 0xF99 = { 4567, 2}, + 0xF9B = { 4569, 1}, + 0xFA0 = { 4570, 3}, + 0xFA1 = { 4573, 2}, + 0xFA2 = { 4575, 3}, + 0xFA3 = { 4578, 2}, + 0xFA4 = { 4580, 3}, + 0xFA5 = { 4583, 2}, + 0xFA6 = { 4585, 1}, + 0xFA8 = { 4586, 10}, + 0xFA9 = { 4596, 10}, + 0xFAA = { 4606, 6}, + 0xFAB = { 4612, 1}, + 0xFAC = { 4613, 6}, + 0xFAD = { 4619, 6}, + 0xFAE = { 4625, 6}, + 0xFB0 = { 4631, 3}, + 0xFB5 = { 4634, 1}, + 0xFB8 = { 4635, 1}, + 0xFB9 = { 4636, 1}, + 0xFBA = { 4637, 1}, + 0xFBB = { 4638, 1}, + 0xFBC = { 4639, 1}, + 0xFBE = { 4640, 1}, + 0xFC0 = { 4641, 1}, + 0xFC1 = { 4642, 1}, + 0xFC2 = { 4643, 3}, + 0xFC3 = { 4646, 3}, + 0xFC4 = { 4649, 1}, + 0xFC5 = { 4650, 1}, + 0xFC6 = { 4651, 2}, + 0xFC7 = { 4653, 2}, + 0xFC8 = { 4655, 7}, + 0xFC9 = { 4662, 11}, + 0xFCA = { 4673, 3}, + 0xFCB = { 4676, 3}, + 0xFCC = { 4679, 7}, + 0xFCD = { 4686, 7}, + 0xFCE = { 4693, 2}, + 0xFCF = { 4695, 2}, + 0xFD2 = { 4697, 1}, + 0xFD3 = { 4698, 1}, + 0xFD9 = { 4699, 4}, + 0xFDA = { 4703, 1}, + 0xFDB = { 4704, 1}, + 0xFE0 = { 4705, 28}, + 0xFE1 = { 4733, 26}, + 0xFE2 = { 4759, 26}, + 0xFE3 = { 4785, 32}, + 0xFE4 = { 4817, 29}, + 0xFE5 = { 4846, 27}, + 0xFE6 = { 4873, 27}, + 0xFE7 = { 4900, 33}, + 0xFE8 = { 4933, 32}, + 0xFE9 = { 4965, 17}, + 0xFEA = { 4982, 17}, + 0xFEB = { 4999, 29}, + 0xFEC = { 5028, 31}, + 0xFED = { 5059, 18}, + 0xFEE = { 5077, 26}, + 0xFEF = { 5103, 32}, + 0xFF0 = { 5135, 19}, + 0xFF1 = { 5154, 18}, + 0xFF2 = { 5172, 17}, + 0xFF3 = { 5189, 17}, + 0xFF4 = { 5206, 19}, + 0xFF5 = { 5225, 18}, + 0xFF6 = { 5243, 17}, + 0xFF7 = { 5260, 17}, + 0xFF8 = { 5277, 4}, + 0xFF9 = { 5281, 4}, + 0xFFA = { 5285, 4}, + 0xFFB = { 5289, 17}, + 0xFFC = { 5306, 4}, + 0xFFD = { 5310, 4}, + 0xFFE = { 5314, 4}, + 0xFFF = { 5318, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 66dc5bdfc..9bcca5dae 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -17,10 +17,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFF08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .EOR { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -139,10 +139,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFFF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .BIC { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -168,28 +168,28 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSR { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ASR { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ROR { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFFF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RRX { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} }, // .ADR @@ -799,13 +799,13 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .STLEXD { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDM - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STM - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDMIB @@ -1012,27 +1012,27 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VABS { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VNEG { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VSQRT @@ -1109,22 +1109,22 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, @@ -1429,20 +1429,20 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMOVN - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, // .VQMOVN - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, // .VQMOVUN - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, // .VMOVL { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1468,10 +1468,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1485,10 +1485,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1502,10 +1502,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1521,10 +1521,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1540,10 +1540,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -1603,11 +1603,11 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, // .VPADDL - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VPADAL { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1706,23 +1706,23 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCLS - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, // .VCLZ - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCNT { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -1730,17 +1730,17 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VREV32 - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, // .VREV64 - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VEXT { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, @@ -1755,24 +1755,24 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VUZP - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VZIP - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, 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b/core/rexcode/isa/arm32/tests/smoke.odin index 0c5aa80aa..bb56137a0 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -102,7 +102,7 @@ run_smoke :: proc() { check("STRH imm", .STRH, 0, 0x014000B0, 0x0F7000F0) check("LDRSB imm", .LDRSB, 0, 0x015000D0, 0x0F7000F0) check("LDRD", .LDRD, 0, 0x014000D0, 0x0F7000F0) - check("LDM", .LDM, 0, 0x08900000, 0x0FD00000) + check("LDM", .LDM, 0, 0x08900000, 0x0FF00000) check("STM DB", .STMDB, 0, 0x09000000, 0x0FD00000) check("PUSH", .PUSH, 0, 0x092D0000, 0x0FFF0000) check("POP", .POP, 0, 0x08BD0000, 0x0FFF0000) @@ -174,18 +174,18 @@ run_smoke :: proc() { check("VABD.S8 D", .VABD, 0, 0xF2000700, 0xFFB00F10) check("VPADD.I8 D", .VPADD, 0, 0xF2000B10, 0xFFB00F10) // NEON unary + shifts - check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFB30FD0) - check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFB30FD0) + check("VABS NEON.S8 D", .VABS, 2, 0xF3B10300, 0xFFBF0FD0) + check("VNEG NEON.F32 D", .VNEG, 8, 0xF3B90780, 0xFFBF0FD0) check("VMVN", .VMVN, 0, 0xF3B00580, 0xFFB30FD0) check("VCNT", .VCNT, 0, 0xF3B00500, 0xFFB30FD0) - check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFB30FD0) + check("VCLZ.I8 D", .VCLZ, 0, 0xF3B00480, 0xFFBF0FD0) check("VSHR.S8 D imm", .VSHR, 0, 0xF2800010, 0xFE800F10) check("VSHL reg.S8 D", .VSHL, 0, 0xF2000400, 0xFFB00F10) check("VEXT D", .VEXT, 0, 0xF2B00000, 0xFFB00010) check("VDUP from Rt D", .VDUP, 0, 0x0EC00B10, 0x0FF00FD0) - check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFB30FD0) - check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFB30FD0) - check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB30FD0) + check("VREV64.I8 D", .VREV64, 0, 0xF3B00000, 0xFFBF0FD0) + check("VTRN.I8 D", .VTRN, 0, 0xF3B20080, 0xFFBF0FD0) + check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB70FD0) check("VTBL", .VTBL, 0, 0xF3B00800, 0xFFB00F70) check("VRECPE F32 D", .VRECPE, 2, 0xF3BB0500, 0xFFBF0FD0) check("VLD1 1-reg", .VLD1, 0, 0xF420070F, 0xFFF00F0F) @@ -289,8 +289,8 @@ run_smoke :: proc() { check("CLREX T32", .CLREX, 1, 0xF3BF8F2F, 0xFFFFFFFF) // ---- T32 32-bit Thumb-2 data-processing ---- - check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBE08000) - check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFE08000) + check("AND T32 imm", .AND, 7, 0xF0000000, 0xFBF08000) + check("AND T32 reg", .AND, 9, 0xEA000000, 0xFFF08000) check("EOR T32 imm", .EOR, 7, 0xF0800000, 0xFBE08000) check("ORR T32 imm", .ORR, 7, 0xF0400000, 0xFBE08000) check("BIC T32 imm", .BIC, 7, 0xF0200000, 0xFBE08000) @@ -337,12 +337,12 @@ run_smoke :: proc() { check("VQRDMULH.S16", .VQRDMULH, 0, 0xF3100B00, 0xFFB00F10) check("VQDMULL.S16", .VQDMULL, 0, 0xF2900D00, 0xFFB00F50) check("VMOVL.S8", .VMOVL, 0, 0xF2880A10, 0xFFB80FD0) - check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFB30FD0) - check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFB30FD0) - check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFB30FD0) + check("VMOVN.I16", .VMOVN, 0, 0xF3B20200, 0xFFBF0FD0) + check("VQMOVN.S16", .VQMOVN, 0, 0xF3B20280, 0xFFBF0FD0) + check("VQMOVUN.S16", .VQMOVUN, 0, 0xF3B20240, 0xFFBF0FD0) check("VSHRN imm", .VSHRN, 0, 0xF2800810, 0xFE800FD0) check("VQSHRN.S", .VQSHRN, 0, 0xF2800910, 0xFE800FD0) - check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFB30FD0) + check("VPADDL.S8", .VPADDL, 0, 0xF3B00200, 0xFFBF0FD0) check("VPADAL.S8", .VPADAL, 0, 0xF3B00600, 0xFFB30FD0) check("VSWP.I8", .VSWP, 0, 0xF3B20000, 0xFFB30FD0) check("VACGE.F32 D", .VACGE, 0, 0xF3000E10, 0xFFB00F10) @@ -537,12 +537,12 @@ run_smoke :: proc() { check("VCVT F16", .VCVT, 19, 0x0EBE0940, 0x0FBF0FD0) // ---- NEON compare-with-zero ---- - check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFB30FD0) - check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFB30FD0) - check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFB30FD0) - check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFB30FD0) - check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFB30FD0) - check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFB30FD0) + check("VCEQ D .I8", .VCEQ, 10, 0xF3B10100, 0xFFBB0FD0) + check("VCEQ Q .F32", .VCEQ, 13, 0xF3B90540, 0xFFBB0FD0) + check("VCGE D", .VCGE, 12, 0xF3B10080, 0xFFBB0FD0) + check("VCGT D", .VCGT, 12, 0xF3B10000, 0xFFBB0FD0) + check("VCLE D", .VCLE, 14, 0xF3B10180, 0xFFBB0FD0) + check("VCLT D", .VCLT, 14, 0xF3B10200, 0xFFBB0FD0) // ---- NEON replicate loads ---- check("VLD2R", .VLD2R, 0, 0xF4A00D0F, 0xFFB00F0F) From 32ef0682238d268e8b6613926aebc0aaaf41396d Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:23:24 -0400 Subject: [PATCH 57/89] rexcode/arm32: the width and saturate fields hold one less than they name SSAT, SSAT16, USAT and USAT16 encode their saturate position minus one, and SBFX and UBFX their width minus one, so a field of zero means one. All of them printed the raw field, which is not a value the instruction can take -- `ssat r0, #0, r0` is not assemblable. BFI and BFC are different again: their field is the top bit's position, and the width the syntax wants is msb - lsb + 1. They shared an encoding with SBFX and UBFX, which need the opposite arithmetic, so they now have their own. Packing an msb needs the lsb from a sibling operand, so the packer takes the instruction rather than one operand in isolation. Also worth recording: the sweep had been running llvm-mc with `-mattr=+all`, which that target does not recognise and silently ignores, so every CRC32, FP16, v8.1a and dot-product entry looked like a reserved encoding. With the features actually enabled, 815 of 1139 A32 entries round-trip, and 38 rather than 143 are genuinely reserved. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 11 +++++++-- core/rexcode/isa/arm32/encoder.odin | 22 ++++++++++++------ core/rexcode/isa/arm32/encoding_types.odin | 3 +++ .../isa/arm32/tablegen/encoding_table.odin | 8 +++---- .../tablegen/generated/decode_tables.odin | 8 +++---- .../tablegen/generated/encode_tables.odin | 8 +++---- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes 8 files changed, 39 insertions(+), 21 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 633ad28e6..7e7c740f1 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -529,8 +529,15 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op return op_imm(i64((word >> 18) & 0xF)) // ---- Saturate / bit field ---- - case .SAT_IMM5, .SAT_IMM5_T32, .BFI_MSB: - return op_imm(i64((word >> 16) & 0x1F)) + case .SAT_IMM5, .SAT_IMM5_T32: + // The field holds one less than the saturate position it names. + return op_imm(i64(((word >> 16) & 0x1F) + 1)) + case .BFX_WIDTH: + // One less than the width. + return op_imm(i64(((word >> 16) & 0x1F) + 1)) + case .BFI_MSB: + // The top bit's position; the syntax wants the width. + return op_imm(i64(((word >> 16) & 0x1F) - ((word >> 7) & 0x1F) + 1)) case .BFI_LSB, .BFI_LSB_T32: return op_imm(i64((word >> 7) & 0x1F)) case .NEON_SHIFT_IMM6: diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index d5b8a68b1..666266a27 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -202,10 +202,10 @@ encode_one_inline :: #force_inline proc( word = (word & 0x0FFFFFFF) | (u32(inst.cond) << 28) } - if form.enc[0] != .NONE { word |= pack_operand_inline(&inst.ops[0], form.enc[0], pc, inst_idx, relocs, form) } - if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], pc, inst_idx, relocs, form) } - if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], pc, inst_idx, relocs, form) } - if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], pc, inst_idx, relocs, form) } + if form.enc[0] != .NONE { word |= pack_operand_inline(&inst.ops[0], form.enc[0], pc, inst_idx, relocs, form, inst) } + if form.enc[1] != .NONE { word |= pack_operand_inline(&inst.ops[1], form.enc[1], pc, inst_idx, relocs, form, inst) } + if form.enc[2] != .NONE { word |= pack_operand_inline(&inst.ops[2], form.enc[2], pc, inst_idx, relocs, form, inst) } + if form.enc[3] != .NONE { word |= pack_operand_inline(&inst.ops[3], form.enc[3], pc, inst_idx, relocs, form, inst) } return word, inst_size_from_bits(form.bits, form.mode), true } @@ -334,6 +334,8 @@ pack_operand_inline :: #force_inline proc( inst_idx: u16, relocs: ^[dynamic]Relocation, form: ^Encoding, + // BFI's msb is lsb + width - 1, so packing it needs a sibling operand. + inst: ^Instruction, ) -> u32 { switch enc { case .NONE, .IMPL: @@ -631,9 +633,15 @@ pack_operand_inline :: #force_inline proc( case .IT_MASK: return u32(op.immediate) & 0xFF case .CPS_IFLAGS: return u32(op.immediate) & 0x1FF case .HINT_FIELD: return u32(op.immediate) & 0xFF - case .SAT_IMM5, .SAT_IMM5_T32: - return (u32(op.immediate) & 0x1F) << 16 - case .BFI_MSB: return (u32(op.immediate) & 0x1F) << 16 + case .SAT_IMM5, .SAT_IMM5_T32, .BFX_WIDTH: + return ((u32(op.immediate) - 1) & 0x1F) << 16 + case .BFI_MSB: + // msb = lsb + width - 1; the lsb rides in whichever slot carries it. + lsb: u32 = 0 + for e, k in form.enc { + if e == .BFI_LSB || e == .BFI_LSB_T32 { lsb = u32(inst.ops[k].immediate); break } + } + return ((lsb + u32(op.immediate) - 1) & 0x1F) << 16 case .BFI_LSB, .BFI_LSB_T32: return (u32(op.immediate) & 0x1F) << 7 case .NEON_SHIFT_IMM6: return (u32(op.immediate) & 0x3F) << 16 diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index d600b6a88..82643db9d 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -400,6 +400,9 @@ Operand_Encoding :: enum u8 { SAT_IMM5_T32, // Thumb-2 saturate amount // ---- BFC/BFI/SBFX/UBFX ---- + // SBFX/UBFX hold the width less one, where BFI/BFC hold the top bit's + // position and the width is msb - lsb + 1. + BFX_WIDTH, BFI_MSB, // bits 20-16 (msb position) BFI_LSB, // bits 11-7 (lsb position; also shift_imm slot) BFI_LSB_T32, // Thumb-2 BFI lsb (different layout) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 1f67e57ea..ec127ce1a 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -754,14 +754,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SBFX = { - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFX_WIDTH}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 SBFX - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFX_WIDTH}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UBFX = { - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFX_WIDTH}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 UBFX - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFX_WIDTH}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index f7f3870a1..fbf32d8d7 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -979,10 +979,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07500000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {.NONE,.NONE} }, { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, @@ -1407,8 +1407,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 9bcca5dae..7b0e2b271 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -209,11 +209,11 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SBFX - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UBFX - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFX_WIDTH}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTB { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index c3ad6e7d879195a4272a1d51340cb07fb7813497..510521e939844c6ce2517016f1c9a7dcddcb4517 100644 GIT binary patch delta 1403 zcmY+DO-~b16o$_kAniH672LVdh>pvv}V3yyxCC_iSxTTieo3MwRAkZca_5 z7is`7cMgu{#V`xd4~QvU>L$6YrY4y@MQS@xuZC*144bhE9IG)ZhX5y%3srz|?j8`_ z$J`xYayR$X#ru6GXyBY_s?*T`67T>OMT26=bSJ7hiDht3CsgOOAF~OVMp@RtD44Dt zi0GV^!^&x@O!<{Bs%tD(5@H`lv3G0wB*jWX>`WL7T9;5W6V^bPaMWj(yL$xpZ0L4( zYwX}!w;;|%;%TkQ#F!vfBJs)m4JOLY*+FnC1*$01JdBdrd^KN3c5+c&2vsP@opUPk zXow1!5!T{D)?$Ro&09Q1g{E38n9b+rzKY9krLNQWY5jKJGW}g_scmd~UK;ZNuhAg1 z?EbEA+E&75fByvN^$cJZ;0@+bgA3e=@LK^p+`TVi?tVuYH7k*%@Nsgtg6snkle^{F ze$PXJx48Yih<&^7{=hI&crTrfyFZGUyFUq7$o?E)*ICumR-Vlu`v+h&IOiA4(J(E; zc6U~<*cbBONd6kiR5i-+H_XN3nw1}-v?(4&m>#@k6bM&1{w}(C2x0E_anir^4`z>B z?!7gA(lUk%01ck?GZ6EGLo^YdMOc>Q3pd9{I5wgvOE6Lb6+7(>?9g7y@C(Q2K1`mJ4qjeo^cXj<4z5Q|3IXTSu>kg2X z!i~PUv5BU8yulW0_nKh29$79m*j|&^p?Z&60}O`Z|FJ_HXM`vt!nedj42RfVX|VP! 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VTBL and VTBX read their table from a run of one to four D registers, and the run length is a fixed pattern bit of the form rather than something the operand encodes. They printed a bare `d0`, which is not the syntax -- the table is a list even when it holds one register. The length now rides in the operand encoding, the way the NEON structure-list lengths already do, and the encoder checks it, so `{d0}` and `{d0, d1}` select different forms instead of both landing on whichever sorted first. The NEON compare-with-zero forms and VCMP/VCMPE against zero take a literal `#0` that no field encodes. Modelling it as an implicit operand is enough for it to print; nothing is emitted for it. VCMP left bit 7 out of its mask. That bit is the E, which is the only thing separating VCMP from VCMPE, so VCMP matched both and VCMPE could never be decoded at all. Also: VPUSH and VPOP take no data type, but the printer's fallback guessed one from the register bank whenever the table gave none, and produced `vpop.f64 {d0}`. A leading register list now suppresses it -- the load/store-multiple forms are exactly the ones that lead with a list. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 19 +- core/rexcode/isa/arm32/encoder.odin | 25 ++- core/rexcode/isa/arm32/encoding_types.odin | 7 + core/rexcode/isa/arm32/mnemonic_builders.odin | 12 +- core/rexcode/isa/arm32/printer.odin | 4 + .../isa/arm32/tablegen/encoding_table.odin | 76 +++---- .../tablegen/generated/decode_tables.odin | 208 +++++++++--------- .../tablegen/generated/encode_tables.odin | 76 +++---- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10670 -> 10670 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3298 -> 3298 bytes 12 files changed, 231 insertions(+), 196 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 7e7c740f1..c7d453b38 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -463,16 +463,19 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) op.list = {count = count, stride = 1} return op + case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: + n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF) + return op_reg_run(Register(REG_DPR | u16(n)), table_run_length(enc)) case .VFP_S_LIST: // {S, ...} -- imm8 counts the registers, and the run starts at Vd. // Both halves matter: keeping only the count printed the wrong bank // and the wrong registers. n := ((word >> 12) & 0xF) << 1 | ((word >> 22) & 1) - return op_reg_run(Register(REG_SPR | u16(n)), u8(word & 0xFF)) + return op_reg_run(Register(REG_SPR | u16(n)), max(u8(word & 0xFF), 1)) case .VFP_D_LIST: // {D, ...} -- imm8 counts half-words here, two per D register. n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) - return op_reg_run(Register(REG_DPR | u16(n)), u8((word & 0xFF) / 2)) + return op_reg_run(Register(REG_DPR | u16(n)), max(u8((word & 0xFF) / 2), 1)) // ---- Branch fields (decoded into RELATIVE) ---- case .BRANCH_24: @@ -639,6 +642,18 @@ decode_max_instruction_count :: #force_inline proc "contextless" (data: []u8) -> return len(data) / 2 } +// How many D registers a VTBL/VTBX table spans. +@(private="file", require_results) +table_run_length :: #force_inline proc "contextless" (e: Operand_Encoding) -> u8 { + #partial switch e { + case .NEON_VN_TABLE_1: return 1 + case .NEON_VN_TABLE_2: return 2 + case .NEON_VN_TABLE_3: return 3 + case .NEON_VN_TABLE_4: return 4 + } + return 1 +} + // Typical-case estimate of the instruction count for `data`. @(require_results) decode_estimate_instruction_count :: #force_inline proc "contextless" (data: []u8) -> int { diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 666266a27..9b675919e 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -264,14 +264,14 @@ mem_mode_matches :: #force_inline proc "contextless" (inst: ^Instruction, form: @(private="file") encoding_matches_inline :: #force_inline proc "contextless" (inst: ^Instruction, form: ^Encoding) -> bool { - return operand_matches_inline(&inst.ops[0], form.ops[0]) && - operand_matches_inline(&inst.ops[1], form.ops[1]) && - operand_matches_inline(&inst.ops[2], form.ops[2]) && - operand_matches_inline(&inst.ops[3], form.ops[3]) + return operand_matches_inline(&inst.ops[0], form.ops[0], form.enc[0]) && + operand_matches_inline(&inst.ops[1], form.ops[1], form.enc[1]) && + operand_matches_inline(&inst.ops[2], form.ops[2], form.enc[2]) && + operand_matches_inline(&inst.ops[3], form.ops[3], form.enc[3]) } @(private="file") -operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Operand_Type) -> bool { +operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Operand_Type, enc: Operand_Encoding) -> bool { #partial switch ot { case .NONE: return op.kind == .NONE @@ -292,7 +292,16 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op case .SPR_LIST: return op.kind == .REGISTER && is_spr(op.reg) case .DPR_LIST: - return op.kind == .REGISTER && is_dpr(op.reg) + if op.kind != .REGISTER || !is_dpr(op.reg) { return false } + // Forms whose run length is a fixed pattern bit are told apart only + // by that length -- {d0} and {d0, d1} are different instructions. + #partial switch enc { + case .NEON_VN_TABLE_1: return op.list.count == 1 + case .NEON_VN_TABLE_2: return op.list.count == 2 + case .NEON_VN_TABLE_3: return op.list.count == 3 + case .NEON_VN_TABLE_4: return op.list.count == 4 + } + return true case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, @@ -509,6 +518,10 @@ pack_operand_inline :: #force_inline proc( n := u32(reg_hw(op.reg)) & 0x1F shift, mask, _ := neon_lane_shape(enc) return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift + case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: + // The run length is already a fixed bit of the form; only Vn is ours. + n := u32(reg_hw(op.reg)) & 0x1F + return ((n >> 4) & 1) << 7 | (n & 0xF) << 16 case .VFP_S_LIST: n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF) diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 82643db9d..4ac261bbd 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -329,6 +329,13 @@ Operand_Encoding :: enum u8 { // ---- VFP / NEON list ---- VFP_S_LIST, // VLDM/VSTM single-prec list (8-bit count, start in Vd_S) VFP_D_LIST, // VLDM/VSTM double-prec list (8-bit count, start in Vd_D) + + // VTBL/VTBX read their table from a run of one to four D registers + // starting at Vn. Which run length applies is the `len` field, which is + // a fixed pattern bit of each form rather than something the operand + // encodes -- so the length rides in the encoding, the way the NEON + // structure-list lengths already do, and the encoder emits only Vn. + NEON_VN_TABLE_1, NEON_VN_TABLE_2, NEON_VN_TABLE_3, NEON_VN_TABLE_4, // NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list, // the register count is part of the form's type field at bits 11:8, so the // encoding writes only Vd; how many registers -- and whether the run steps diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 9e53fb4ac..5e4bdd9a3 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -976,13 +976,9 @@ inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } -inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) } -inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } -emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) } inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } @@ -2187,10 +2183,10 @@ inst_vrev64 :: inst_vrev64_d_d emit_vrev64 :: emit_vrev64_d_d inst_vext :: inst_vext_d_d_d_imm4 emit_vext :: emit_vext_d_d_d_imm4 -inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d } -emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d } -inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d } -emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d } +inst_vtbl :: inst_vtbl_d_dlist_d +emit_vtbl :: emit_vtbl_d_dlist_d +inst_vtbx :: inst_vtbx_d_dlist_d +emit_vtbx :: emit_vtbx_d_dlist_d inst_vtrn :: inst_vtrn_d_d emit_vtrn :: emit_vtrn_d_d inst_vuzp :: inst_vuzp_d_d diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 889ac3cfe..e7ac5999d 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -213,6 +213,10 @@ infer_dt_suffix_from_inst :: proc(inst: ^Instruction) -> string { if inst.operand_count == 0 { return "" } op0 := &inst.ops[0] if op0.kind != .REGISTER { return "" } + // A register list leads the load/store-multiple forms -- VPUSH, VPOP and + // friends -- and none of them take a data type. Guessing one from the + // bank produced `vpop.f64 {d0}`, which is not accepted syntax. + if op0.list.count > 0 { return "" } switch reg_class(op0.reg) { case REG_SPR: return ".f32" case REG_DPR: return ".f64" diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index ec127ce1a..562003868 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1498,14 +1498,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCMP / VCMPE: cond 1110 1011 D 0100 Vd 101 sz E 1 M 0 Vm (E=1 raises invalid op on QNaN) .VCMP = { - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VCMP with zero: cond 1110 1011 D 0101 Vd 101 sz E 1 (0) 0 0000 - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMP, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .IMPL, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, // MVE VCMP Qn, Qm -- writes VPR.P0. Per LLVM: // vcmp.i8 eq,q2,q3 -> 0xFE05_0F06 base 0xFE01_0F00 // vcmp.f32 eq,q2,q3 -> 0xEE35_0F06 base 0xEE31_0F00 @@ -1513,10 +1513,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VCMPE = { - {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, - {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, - {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .IMM, .NONE, .NONE}, {.VD_S, .IMPL, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .IMPL, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VCVT family: int<->float and float<->float @@ -1883,11 +1883,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 @@ -1906,10 +1906,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 @@ -1927,10 +1927,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F16 {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { @@ -2261,19 +2261,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // len = 00,01,10,11 selects 1/2/3/4-vec table; op=0 TBL, 1 TBX .VTBL = { // 1-vec table - {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_1, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 2-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_2, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 3-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_3, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 4-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_4, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VTBX = { - {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_1, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_2, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_3, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .NEON_VN_TABLE_4, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VRECPE / VRSQRTE (reciprocal estimates) ---- @@ -3623,10 +3623,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, @@ -3643,10 +3643,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .IMPL, .NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .IMPL, .NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index fbf32d8d7..cf783d63c 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -262,8 +262,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, @@ -367,25 +367,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -398,10 +398,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -436,14 +436,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -469,8 +469,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -684,12 +684,12 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, @@ -726,17 +726,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, @@ -745,11 +745,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, @@ -759,26 +759,26 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB70FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -805,14 +805,14 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -1110,11 +1110,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, @@ -1138,6 +1138,11 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, @@ -1173,11 +1178,6 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, @@ -1673,24 +1673,24 @@ DECODE_FORM_IDX := [1649]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 24, 23, 25, 21, 22, 0, 0, 0, 19, 12, - 17, 14, 20, 18, 10, 16, 13, 15, 11, 0, 0, 0, 0, 11, 10, 0, - 6, 0, 0, 7, 2, 6, 3, 4, 9, 5, 8, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 23, 24, 25, 22, 21, 0, 0, 0, 19, 20, + 14, 17, 16, 13, 18, 10, 12, 11, 15, 0, 0, 0, 0, 11, 10, 0, + 6, 0, 0, 7, 2, 4, 6, 9, 3, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, - 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 3, 1, 1, 3, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 1, 6, 1, 6, 2, + 0, 0, 2, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, @@ -1704,12 +1704,12 @@ DECODE_FORM_IDX := [1649]u16{ 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 9, 4, 4, 8, 8, 4, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 5, 4, 6, 8, 9, 2, 3, 7, 3, 7, 5, 6, 4, 2, 9, + 0, 5, 4, 3, 9, 6, 7, 8, 2, 3, 7, 5, 6, 4, 2, 9, 8, 10, 1, 0, 2, 0, 5, 1, 2, 3, 4, 2, 1, 0, 2, 0, - 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 5, 1, 3, - 2, 0, 4, 2, 0, 4, 5, 1, 3, 0, 5, 1, 3, 2, 4, 0, - 1, 2, 3, 4, 5, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 10, - 13, 12, 15, 12, 13, 14, 13, 14, 12, 15, 17, 15, 16, 14, 14, 16, + 1, 4, 2, 0, 1, 3, 1, 2, 0, 3, 2, 1, 3, 1, 3, 5, + 2, 0, 4, 2, 0, 1, 4, 5, 3, 0, 5, 1, 3, 2, 4, 0, + 2, 3, 4, 5, 1, 2, 4, 3, 2, 4, 3, 0, 0, 0, 11, 12, + 10, 13, 12, 15, 13, 14, 12, 14, 15, 13, 17, 14, 16, 15, 14, 16, 15, 17, 1, 2, 0, 3, 0, 1, 0, 1, 0, 1, 3, 5, 0, 2, 1, 3, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 2, 0, 2, @@ -1732,10 +1732,10 @@ DECODE_FORM_IDX := [1649]u16{ 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, 3, 2, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, - 0, 1, 0, 1, 1, 0, 2, 0, 1, 19, 18, 20, 17, 14, 12, 9, - 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, 0, 1, 0, 1, 2, - 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 4, 0, - 1, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, + 0, 1, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 19, 18, + 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, + 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, + 0, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, @@ -1905,38 +1905,38 @@ DECODE_BUCKET_LIST := [5335]u16{ 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 989, 991, 992, 993, 994, 1007, 1008, 995, 996, 1007, 1008, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, 1008, 995, 996, 1009, - 1007, 1008, 997, 998, 992, 993, 994, 1011, 1010, 1007, 1012, 1008, 995, 1013, 996, 1015, + 1007, 1008, 997, 998, 992, 993, 994, 1010, 1011, 1007, 1012, 1008, 995, 1013, 996, 1015, 1014, 1007, 1016, 1008, 997, 1017, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007, - 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1020, 1021, 995, 996, 1018, 1019, - 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, + 1008, 995, 996, 1009, 1007, 1008, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, + 1022, 1023, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1020, 1021, 995, 996, 1031, 1030, 1018, 1019, 1023, 1022, 997, 998, 1018, 1019, 1021, 1020, 995, 996, 1018, 1019, - 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1021, 1020, 995, 996, - 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, 1035, 1034, 1036, 1037, - 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1034, 1035, 1007, 1008, 1007, 1008, - 1018, 1019, 1033, 1032, 1018, 1019, 1034, 1035, 1018, 1019, 1018, 1019, 1018, 1019, 1033, 1032, - 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, 1042, 1044, 1043, 1045, - 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1055, 1043, 1044, 1056, 1007, - 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, 1064, 1065, 1066, 1044, - 1043, 1067, 1007, 1069, 1068, 1070, 1071, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1072, - 1073, 1007, 1075, 1074, 1076, 1077, 1008, 1061, 1052, 1062, 1054, 1041, 1078, 1042, 1044, 1043, + 1023, 1022, 997, 998, 1024, 1025, 1026, 1027, 1028, 1029, 1018, 1019, 1020, 1021, 995, 996, + 1018, 1019, 1022, 1023, 997, 998, 1007, 1008, 1033, 1032, 1007, 1008, 1035, 1034, 1037, 1036, + 1007, 1008, 1007, 1008, 1007, 1008, 1032, 1033, 1007, 1008, 1035, 1034, 1007, 1008, 1007, 1008, + 1018, 1019, 1033, 1032, 1018, 1019, 1035, 1034, 1018, 1019, 1018, 1019, 1018, 1019, 1033, 1032, + 1018, 1019, 1034, 1035, 1018, 1019, 1018, 1019, 1038, 1039, 1040, 1041, 1042, 1043, 1044, 1045, + 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1055, 1044, 1043, 1056, 1007, + 1058, 1057, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1039, 1040, 1063, 1064, 1065, 1066, 1044, + 1043, 1067, 1007, 1068, 1069, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1072, + 1073, 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1041, 1078, 1042, 1044, 1043, 1045, 1046, 1007, 1047, 1048, 1049, 1050, 1008, 1051, 1052, 1053, 1054, 1043, 1044, 1056, 1007, - 1057, 1058, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, 1065, 1066, 1043, 1044, - 1067, 1007, 1069, 1068, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1044, 1043, 1056, 1072, 1073, - 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1083, 1084, - 1085, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, 1092, 1094, 1093, 1061, - 1052, 1062, 1054, 1095, 1096, 1097, 1098, 1099, 1100, 1051, 1052, 1053, 1054, 1102, 1103, 1101, - 1104, 1105, 1107, 1106, 1108, 1109, 1110, 1111, 1113, 1112, 1114, 1115, 1116, 1117, 1118, 1119, - 1121, 1120, 1123, 1122, 1125, 1124, 1126, 1128, 1127, 1129, 1137, 1130, 1145, 1132, 1139, 1143, - 1146, 1133, 1134, 1144, 1131, 1142, 1138, 1141, 1136, 1135, 1140, 1148, 1147, 1149, 1150, 1152, - 1151, 1154, 1153, 1155, 1156, 1157, 1158, 1159, 1160, 1162, 1161, 1163, 1165, 1166, 1164, 1167, + 1058, 1057, 1059, 1060, 1008, 1061, 1052, 1062, 1054, 1063, 1064, 1078, 1065, 1066, 1043, 1044, + 1067, 1007, 1068, 1069, 1071, 1070, 1008, 1051, 1052, 1053, 1054, 1044, 1043, 1056, 1072, 1073, + 1007, 1075, 1074, 1077, 1076, 1008, 1061, 1052, 1062, 1054, 1079, 1080, 1082, 1081, 1083, 1084, + 1085, 1086, 1088, 1087, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1091, 1092, 1094, 1093, 1061, + 1052, 1062, 1054, 1095, 1096, 1097, 1098, 1099, 1100, 1051, 1052, 1053, 1054, 1101, 1102, 1103, + 1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1113, 1112, 1114, 1115, 1117, 1116, 1119, 1118, + 1121, 1120, 1123, 1122, 1125, 1124, 1128, 1127, 1126, 1129, 1130, 1131, 1133, 1132, 1151, 1150, + 1137, 1145, 1142, 1139, 1149, 1143, 1134, 1138, 1144, 1148, 1147, 1141, 1146, 1136, 1135, 1140, + 1153, 1152, 1154, 1155, 1158, 1159, 1156, 1157, 1160, 1161, 1163, 1162, 1165, 1164, 1167, 1166, 1168, 1169, 1170, 1172, 1171, 1056, 1061, 1052, 1062, 1054, 1079, 1080, 1081, 1082, 1084, 1083, 1085, 1173, 1086, 1087, 1088, 1051, 1052, 1053, 1054, 1056, 1089, 1090, 1092, 1091, 1094, 1093, 1061, 1052, 1062, 1054, 1174, 1175, 1095, 1096, 1098, 1097, 1099, 1100, 1051, 1052, 1053, 1054, 1176, 1101, 1102, 1103, 1104, 1105, 1106, 1107, 1108, 1109, 1111, 1110, 1113, 1112, 1115, 1114, - 1116, 1117, 1119, 1118, 1120, 1121, 1122, 1123, 1124, 1125, 1128, 1127, 1126, 1136, 1133, 1134, - 1135, 1137, 1130, 1131, 1132, 1129, 1138, 1145, 1144, 1142, 1139, 1140, 1141, 1143, 1146, 1148, - 1147, 1149, 1150, 1151, 1152, 1153, 1154, 1155, 1156, 1158, 1157, 1159, 1160, 1162, 1161, 1163, - 1166, 1164, 1165, 1168, 1167, 1170, 1169, 1171, 1172, 1056, 1061, 1052, 1062, 1054, 1007, 1008, + 1116, 1117, 1119, 1118, 1120, 1121, 1122, 1123, 1124, 1125, 1128, 1127, 1126, 1130, 1131, 1129, + 1133, 1132, 1151, 1136, 1134, 1135, 1137, 1138, 1145, 1144, 1142, 1148, 1149, 1150, 1147, 1139, + 1140, 1141, 1143, 1146, 1152, 1153, 1155, 1154, 1159, 1158, 1157, 1156, 1160, 1161, 1163, 1162, + 1164, 1165, 1166, 1167, 1168, 1170, 1169, 1171, 1172, 1056, 1061, 1052, 1062, 1054, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1007, 1008, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1177, 1178, 1179, 1180, 1181, 1182, 1183, 1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index 7b0e2b271..f7b48caaa 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -1040,19 +1040,19 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VCMP - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VCMPE - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VCVT { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, @@ -1468,10 +1468,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10100, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10140, 0xFFBB0FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90500, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90540, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1485,10 +1485,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10080, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B100C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90480, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B904C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1502,10 +1502,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10000, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10040, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90400, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90440, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1521,10 +1521,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10180, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B101C0, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90580, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B905C0, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, @@ -1540,10 +1540,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B10200, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B10240, 0xFFBB0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.IMPL,.NONE}, 0xF3B90600, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.IMPL,.NONE}, 0xF3B90640, 0xFFBB0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -1745,15 +1745,15 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, // .VTBL - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTBX - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFBF0FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, diff --git 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zQFA@~p@J3d-w~$k8sgUzNZXXYf3INf#4O-*5AC@1p6}8D_Vggl(#*vLjBcEFSOWu) zIOE|r8NYkR=*@DGJR^b7{*A=A{^4khge;dNSzgNCW(^JGX$P7QS8Me3c+M&cF^zadUy630C(pN2@RUvdM>r#iM1 zi9^-fD^B6xobWTA&@M2A5!23X@{$|Jt|w)+ntRK{{<&!K%fcctRV(3U?Yc&qs4=oza<>c=ieYEGb7%d0b(mE4+ID1bY+@?my`a#>?(te2JJ@ojb6=m)%U=?4&oXHbyf9jz9@5m@D|L$JZ!n z3jBtL>8YcOU-vLSIyu_MJj_q34nFK*9+qR=KN%9Up-<6!&DO&gCyfD~$reRuC&#L q*;N29$p>e+ZEA#V$B(9_*>2p6ee65<9>d_bCUxIkQRxCmN!r!DheI|QXYi1EtXlR)MBuWYf04W2ZS26+(QYK&mprWD52Gj@%Cjnb$ z$>+0ubx{}RJ+Ve$OWHEvAMUxm(VRml`=RS>f-wpVF+vwPddLuCfIb4Gh>#$(FQ@P{ z7z)N_yi7DmQp1rYfh~E#462TNqEN$!5t`xIjl15tBIQ=9ezjwO|3t|dYB!W{j=X8~ lP3 Date: Sat, 29 Aug 2026 00:33:26 -0400 Subject: [PATCH 59/89] rexcode/arm32: the VCMP smoke test asserted the mask without the E bit Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/tests/smoke.odin | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index bb56137a0..c1f7ae638 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -136,7 +136,7 @@ run_smoke :: proc() { check("VMSR", .VMSR, 0, 0x0EE10A10, 0x0FFF0FFF) check("VPUSH.F32", .VPUSH,0, 0x0D2D0A00, 0x0FFF0F00) check("VPOP.F64", .VPOP, 1, 0x0CBD0B00, 0x0FFF0F00) - check("VCMP.F32", .VCMP, 0, 0x0EB40A40, 0x0FBF0F50) + check("VCMP.F32", .VCMP, 0, 0x0EB40A40, 0x0FBF0FD0) // ---- ARMv8 FP ---- check("VMAXNM.F32", .VMAXNM, 0, 0xFE800A00, 0xFFB00B50) From 421262e84ea73b779d1cd3c830f4b585dbc0c5ba Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:37:11 -0400 Subject: [PATCH 60/89] rexcode/arm32: the NEON by-scalar forms dropped the lane they multiply by VMLA, VMUL, VMLAL, VQDMULL, VSDOT, VCMLA and the rest of the by-scalar family take one lane of a low D register as the multiplier -- `d0[2]`, not `d0`. Every one of them printed the bare register, which is not only missing information but assembles to a different instruction: the by-vector form. The forms already declared the operand type as DPR_ELEM; what they lacked was an encoding that knows the register number and the lane number share a single four-bit field. How they share it depends on the element size, and the two splits are different enough to be separate encodings: 16-bit takes Vm from bits 2:0, so D0..D7, and the lane from M:bit3, giving four lanes; 32-bit takes Vm from bits 3:0, so D0..D15, and the lane from M alone, giving two. The dot-product and complex forms share the 32-bit split despite being 8- and 16-bit operations. Those reaches are now checked when selecting a form, so `d8[0]` on a 16-bit form matches nothing rather than quietly encoding as `d0[0]`, and a lane-less operand no longer matches a by-scalar form at all. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 5 + core/rexcode/isa/arm32/encoder.odin | 16 ++- core/rexcode/isa/arm32/encoding_types.odin | 7 ++ .../isa/arm32/tablegen/encoding_table.odin | 98 +++++++++--------- .../tablegen/generated/decode_tables.odin | 98 +++++++++--------- .../tablegen/generated/encode_tables.odin | 98 +++++++++--------- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes 8 files changed, 174 insertions(+), 148 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index c7d453b38..594021caf 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -463,6 +463,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) op.list = {count = count, stride = 1} return op + case .NEON_VM_SCALAR_16: + return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)), + u8(((word >> 5) & 1) << 1 | ((word >> 3) & 1))) + case .NEON_VM_SCALAR_32: + return op_dpr_lane(Register(REG_DPR | u16(word & 0xF)), u8((word >> 5) & 1)) case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF) return op_reg_run(Register(REG_DPR | u16(n)), table_run_length(enc)) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 9b675919e..036d97567 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -286,7 +286,15 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op case .SPR: return op.kind == .REGISTER && is_spr(op.reg) case .DPR: return op.kind == .REGISTER && is_dpr(op.reg) case .QPR: return op.kind == .REGISTER && is_qpr(op.reg) - case .DPR_ELEM: return op.kind == .REGISTER && is_dpr(op.reg) + case .DPR_ELEM: + if op.kind != .REGISTER || !is_dpr(op.reg) { return false } + // A by-scalar multiplier names a lane, and how far the register and + // lane numbers reach depends on how they share the field. + #partial switch enc { + case .NEON_VM_SCALAR_16: return op.has_lane && reg_hw(op.reg) < 8 && op.lane < 4 + case .NEON_VM_SCALAR_32: return op.has_lane && reg_hw(op.reg) < 16 && op.lane < 2 + } + return true case .QPR_ELEM: return op.kind == .REGISTER && is_qpr(op.reg) case .SPR_ELEM: return op.kind == .REGISTER && is_spr(op.reg) case .SPR_LIST: @@ -518,6 +526,12 @@ pack_operand_inline :: #force_inline proc( n := u32(reg_hw(op.reg)) & 0x1F shift, mask, _ := neon_lane_shape(enc) return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift + case .NEON_VM_SCALAR_16: + n := u32(reg_hw(op.reg)) & 0x7 + idx := u32(op.lane) & 0x3 + return n | ((idx >> 1) & 1) << 5 | (idx & 1) << 3 + case .NEON_VM_SCALAR_32: + return (u32(reg_hw(op.reg)) & 0xF) | (u32(op.lane) & 1) << 5 case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: // The run length is already a fixed bit of the form; only Vn is ours. n := u32(reg_hw(op.reg)) & 0x1F diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 4ac261bbd..4d423bc8d 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -336,6 +336,13 @@ Operand_Encoding :: enum u8 { // encodes -- so the length rides in the encoding, the way the NEON // structure-list lengths already do, and the encoder emits only Vn. NEON_VN_TABLE_1, NEON_VN_TABLE_2, NEON_VN_TABLE_3, NEON_VN_TABLE_4, + + // NEON "by scalar": the multiplier is one lane of a low D register, and + // the register number and the lane number share one four-bit field. How + // they share it depends on the element size -- 16-bit takes Vm from bits + // 2:0, so D0..D7, and the lane from M:bit3; 32-bit takes Vm from bits + // 3:0, so D0..D15, and the lane from M alone. + NEON_VM_SCALAR_16, NEON_VM_SCALAR_32, // NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list, // the register count is part of the form's type field at bits 11:8, so the // encoding writes only Vd; how many registers -- and whether the run steps diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 562003868..5266b6b11 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1736,11 +1736,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VMUL MVE scalar: per LLVM 0xEE05_3E63 -> base 0xEE011E60 {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // Integer D-form .I16/.I32 - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Integer Q-form .I16/.I32 (bit 24 = 1) - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { @@ -1760,10 +1760,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE VMLA Qda, Qn, Rm (scalar) {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, @@ -1780,10 +1780,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON F32 (bit 21 = 1 distinguishes FMLS from FMLA) {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { @@ -2226,8 +2226,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, // VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm - {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, - {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, // MVE VDUP Qd, Rt {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, }, @@ -2394,11 +2394,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // polynomial: U=0, op=10 {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // signed .S16/.S32 - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned .U16/.U32 (top byte 0xF3) - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // VMLAL / VMLSL (widening multiply-accumulate) // VMLAL: signed F2800800 / unsigned F3800800; op=1000 (no minus); minus bit at 21 @@ -2409,10 +2409,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VMLSL = { // VMLSL: op=1010 (bit 9 = 1) @@ -2422,10 +2422,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // ---- VQDMULH / VQRDMULH (saturating doubling multiply, high half) ---- @@ -2459,42 +2459,42 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMLSH = { {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMULL: 1111 0010 1 D size Vn Vd 1101 N 0 M 0 Vm .VQDMULL = { {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMLAL / VQDMLSL (saturating doubling multiply-accumulate long) .VQDMLAL = { // signed: 1111 0010 1 D size Vn Vd 1001 N 0 M 0 Vm {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQDMLSL = { // signed: 1111 0010 1 D size Vn Vd 1011 N 0 M 0 Vm {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VMOVL / VMOVN / VQMOVN / VQMOVUN (widening/narrowing moves) ---- @@ -2725,8 +2725,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VSDOT.S8 D: 0xFC200D00 {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VUDOT (unsigned): bit 4 = 1 distinguishes from VSDOT (bit 4 = 0). // vudot.u8 d0,d1,d2 = 0xFC21_0D12 -> base 0xFC200D10 @@ -2734,8 +2734,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, // vudot.u8 d0,d1,d2[0] = 0xFE21_0D12 -> base 0xFE200D10 (bit 4 = 1 for U) - {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, - {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // FEAT_FCMA (ARMv8.3): VCMLA / VCADD (complex multiply-add + add) @@ -2745,8 +2745,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VCADD = { @@ -2797,13 +2797,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only) .VSUDOT = { {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {}}, - {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSDOT = { {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // ========================================================================= diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index cf783d63c..986c3ebe8 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -431,25 +431,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -458,25 +458,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, @@ -649,17 +649,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -670,17 +670,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, @@ -813,8 +813,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -1050,8 +1050,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, @@ -1072,10 +1072,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1088,13 +1088,13 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index f7b48caaa..b6f98c6fc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -935,10 +935,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -956,10 +956,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -972,10 +972,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1274,10 +1274,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLAL { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1285,10 +1285,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLSL { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1296,25 +1296,25 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VQDMULL { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLAL { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLSL { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMULH { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, @@ -1338,19 +1338,19 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VQRDMLSH { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VABA { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1776,8 +1776,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VDUP { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, // .VSWP { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, @@ -1870,13 +1870,13 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VSDOT { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, // .VUDOT { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, // .VDOT { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {}, {.BF16,.NONE} }, { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, @@ -1891,8 +1891,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VCMLA { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VCADD { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, @@ -1905,12 +1905,12 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VSUDOT { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSDOT { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VQABS { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQNEG diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 76d1bda3b96e7ff2e1abfa5562664ef71155b3f8..f92d9332841f8601dc7d105b881c54b820c97c1e 100644 GIT binary patch delta 5847 zcmZXYdvH`&9mjuXv)N5Ho9s=KTvxDUL-X8h9zzShsM&=isA#*?67n#x3|KAlSOVo4 z*aZ>@Ee$D0XPj|_#TQklcE_F3LJI`zqgpAc^-;8~na=260t*2r)SC5o9`~M;p)>b3 z{d|AF@9%dW_uSh(^StBC^Nw_-&#`AWt@2gO*}EG6woE}XmvfT~7| z+#Ukr&xfL&w6xq5;-nH6T4Gzd*@>C0zLYEL%ZkiJC=$%{qDx>Zo0VOEoMQ)%o>b8S z7wyb^yZlGq{wG*z01sY1HX=9%^^E`<7@WW>3pg5%>+rvxWOx#s5-US|;W|;5B9|}xw)|h@FwsNt61OU!Rv9i`AU71C-TZo^J5R99-|K)OQCE;gc z;PiamzZP->1GiXQ%;!r$u&C?HEUxt)+|RJ#q?hW=``m`gabiyS>Jts7zYhbt@tR>< z0RR0GFs-zgHaD34y$HUA7vCRTWW`E&4-*LG07VZa%nG8@ zY6R!N#b>vR#)Gogxa#$s7)U=o88rLF;8nNhRJUx5R<{zfwsvW42`e$NxO1$DmAH?V zHp;CNR^?xoD^J@R%>-ZQFg{gsTS$?26;@rnth#z!>q=tQRb1;zn24^Dsw;`PH;Bpd zk^sOfqM=?oiQRSsq#;hSRzp(kp(PgqAAD~VZGNv$hkBDzYc zt|aD@70@Q@f;CyuCO%mc`eaG5hwg9UlQp4F)&%50vYOZjs>Z5Nrhn8V-R!_bpJ-ZRhWR`2;9u|#P+{a5l18+{(+T zd09A;S5rE_c6A&?en$`f(jg zL<9H@m4^p~+!OS@URL8y?*Oae6E+y)fQYqfG||VW%O?gcMUfxLywG>d^bg|Ke)5*# zOX9PFJMKwzHy{`qq$>uP7=`4G6~5$+xg<~o8_?H)x`siT5F$z9wv(9~FtdVZzA$i< z**Y}ajkfJ0+suBnb!fJmEL$-0w46;=4nz^#bvCQ$d@Xvj6-_T~U)d;LrB$oIJew|)3&ilxfn z2=U@GwUn+IG!yMibloF%FzmPoe~w{q3axk{W>tb#pJy0Sw<~Akf99jh-uAo=;nTf}k=+O+H=7xN(KroCbKhCgQ z8-u_r87|W2>KR^h361YJ{Y#nZ0kyJ1Y^NvpoBd)5XNhX9l4`A<;Y%piDyh~=V6j$7 zzE*q=kBOzCr3q`TvhVm_R*#eE0=$ubLoXPW2%-)Ex1GWQ(%1)kaqhFCrn^@d|a4M=orH#epAEa zD*BH)R?%-UOwb#@wplCEq3T+6izze2_(~nBYd{=V_-}f&GC{1OIrj1y z{W}XU7^06JHT#F^>KpKv0_F9N5UXoyaY~dI;=;m08LjZU=iK=|a7T+DaOuFb#o@>JURepD$V1F;<_jUaK z9KT=W_iHDbI(uQ1YRy7IP|>oqkOa~|Xz@`ju)HA( zyGdFImWGt0GtM}|;)|+Nn{j8fv;~6oQLRX7eH3kLrZf7N!18iJtyzD+bI!fzWa!Mj zq@VBab$-8d?>)(>XFaE$^^8@7JbU->%24_2eR}|4>kUZda()&8m;;QJ+a52<@lg3X zlKW82O7+8zx;qYOe*z{$esl+ki-P-h1H`oTU553fww9QzGp~dedBZ!sU_si~g3`P84KHm_ zyD6sAzoa$;Z*8!XV)ijTdnJmhV!EoAbX7D)rz(Z1DtZWvZRZ3T-u$+(4te0g$ z-Fy9Q1F!v~^v z7=6YdrqiF1wRQ66qjs`Oh~U#7tM&59V! zI_oqm-YA+iVKz&NUHm|!Xx4<;th2f-Y_i)d>7%yLZFdVPEb?2o-KX=Mlm41akG;^% zQeqdcXcCWM)=Ym+r(b8Jmp*DJI=#XoeTz;%j@v#8zSZ6M*^yJq!&u_8Yb%wgY(}?9~>$-t0ZGFSU+WID8w(e1% zACE~v+*I<^a?8Z;(_Sma_Y%N=6zAE6>i9oCVK>)7tRQ_o9vaJG3yQ$Y0)Y~!Zy-E+L*anNnX3D?vJO;X z)Nu-cj};b{K<#|OMl7F>1x73vXD;18OT_XTvHUug*NElUvAjks7iSi9=0903-fMW^(_%!4nYWg|Rv5QwZnG4-A*|| zG7Oq{V6ihbp6n6+Az7&sm4D{Bo+Ea+AAbQzUAIChd{%JBJ%-UOsE_vZmD@>-L+a|v zQ0nR&7Ab;F7}tW@x_+LNB1_@6Q=Xg9vs`#SxBW1M^%!9vcf&rg!|uhf9wY2#CoEWb zhRCKje?x4B_DvQ_X@yEQrt4V!r;Xc5(@czB|M=!k#j#W6c6-zJgC;wQ_n!iV-onZ7Z7DuKn+}&k(poZi4su15}UO7l_c1w%-aKaV$5B`%p z3qW|{-x7-9dn8);CFlJ^KgYNBf+xryit*)%!STh+;76|i$P+(f+cHa^tY>V1Cl1